drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  48
  49 #define I40E_CLEAR_PXE_WAIT_MS     200
  50
  51 /* Maximun number of capability elements */
  52 #define I40E_MAX_CAP_ELE_NUM       128
  53
  54 /* Wait count and interval */
  55 #define I40E_CHK_Q_ENA_COUNT       1000
  56 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  57
  58 /* Maximun number of VSI */
  59 #define I40E_MAX_NUM_VSIS          (384UL)
  60
  61 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  62
  63 /* Flow control default timer */
  64 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  65
  66 /* Flow control enable fwd bit */
  67 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  68
  69 /* Receive Packet Buffer size */
  70 #define I40E_RXPBSIZE (968 * 1024)
  71
  72 /* Kilobytes shift */
  73 #define I40E_KILOSHIFT 10
  74
  75 /* Flow control default high water */
  76 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  77
  78 /* Flow control default low water */
  79 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  80
  81 /* Receive Average Packet Size in Byte*/
  82 #define I40E_PACKET_AVERAGE_SIZE 128
  83
  84 /* Mask of PF interrupt causes */
  85 #define I40E_PFINT_ICR0_ENA_MASK ( \
  86                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  87                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  88                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  89                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  90                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  91                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  95
  96 #define I40E_FLOW_TYPES ( \
  97         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 102         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 107         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 108
 109 /* Additional timesync values. */
 110 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 111 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 112 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 113 #define I40E_PRTTSYN_TSYNENA     0x80000000
 114 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 115 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 116
 117 /**
 118  * Below are values for writing un-exposed registers suggested
 119  * by silicon experts
 120  */
 121 /* Destination MAC address */
 122 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 123 /* Source MAC address */
 124 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 125 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 126 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 127 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 128 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 129 /* Single VLAN tag in the inner L2 header */
 130 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 131 /* Source IPv4 address */
 132 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 133 /* Destination IPv4 address */
 134 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 135 /* Source IPv4 address for X722 */
 136 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 137 /* Destination IPv4 address for X722 */
 138 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 139 /* IPv4 Protocol for X722 */
 140 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 141 /* IPv4 Time to Live for X722 */
 142 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 143 /* IPv4 Type of Service (TOS) */
 144 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 145 /* IPv4 Protocol */
 146 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 147 /* IPv4 Time to Live */
 148 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 149 /* Source IPv6 address */
 150 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 151 /* Destination IPv6 address */
 152 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 153 /* IPv6 Traffic Class (TC) */
 154 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 155 /* IPv6 Next Header */
 156 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 157 /* IPv6 Hop Limit */
 158 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 159 /* Source L4 port */
 160 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 161 /* Destination L4 port */
 162 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 163 /* SCTP verification tag */
 164 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 165 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 166 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 167 /* Source port of tunneling UDP */
 168 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 169 /* Destination port of tunneling UDP */
 170 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 171 /* UDP Tunneling ID, NVGRE/GRE key */
 172 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 173 /* Last ether type */
 174 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 175 /* Tunneling outer destination IPv4 address */
 176 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 177 /* Tunneling outer destination IPv6 address */
 178 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 179 /* 1st word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 181 /* 2nd word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 183 /* 3rd word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 185 /* 4th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 187 /* 5th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 189 /* 6th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 191 /* 7th word of flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 193 /* 8th word of flex payload */
 194 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 195 /* all 8 words flex payload */
 196 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 197 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 198
 199 #define I40E_TRANSLATE_INSET 0
 200 #define I40E_TRANSLATE_REG   1
 201
 202 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 203 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 204 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 205 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 206 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 207 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 208
 209 /* PCI offset for querying capability */
 210 #define PCI_DEV_CAP_REG            0xA4
 211 /* PCI offset for enabling/disabling Extended Tag */
 212 #define PCI_DEV_CTRL_REG           0xA8
 213 /* Bit mask of Extended Tag capability */
 214 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 215 /* Bit shift of Extended Tag enable/disable */
 216 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 217 /* Bit mask of Extended Tag enable/disable */
 218 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 219
 220 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 221 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 222 static int i40e_dev_configure(struct rte_eth_dev *dev);
 223 static int i40e_dev_start(struct rte_eth_dev *dev);
 224 static void i40e_dev_stop(struct rte_eth_dev *dev);
 225 static void i40e_dev_close(struct rte_eth_dev *dev);
 226 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 227 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 229 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 233 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 234                                struct rte_eth_stats *stats);
 235 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 236                                struct rte_eth_xstat *xstats, unsigned n);
 237 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 238                                      struct rte_eth_xstat_name *xstats_names,
 239                                      unsigned limit);
 240 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 244                              struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct rte_ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static void i40e_dev_alarm_handler(void *param);
 293 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 294                                 uint32_t base, uint32_t num);
 295 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 296 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 297                         uint32_t base);
 298 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 299                         uint16_t num);
 300 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 301 static int i40e_veb_release(struct i40e_veb *veb);
 302 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 303                                                 struct i40e_vsi *vsi);
 304 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 305 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 306 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 307                                              struct i40e_macvlan_filter *mv_f,
 308                                              int num,
 309                                              uint16_t vlan);
 310 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 311 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 312                                     struct rte_eth_rss_conf *rss_conf);
 313 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 314                                       struct rte_eth_rss_conf *rss_conf);
 315 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 316                                         struct rte_eth_udp_tunnel *udp_tunnel);
 317 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 318                                         struct rte_eth_udp_tunnel *udp_tunnel);
 319 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 320 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 321                                 enum rte_filter_op filter_op,
 322                                 void *arg);
 323 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 324                                 enum rte_filter_type filter_type,
 325                                 enum rte_filter_op filter_op,
 326                                 void *arg);
 327 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 328                                   struct rte_eth_dcb_info *dcb_info);
 329 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 330 static void i40e_configure_registers(struct i40e_hw *hw);
 331 static void i40e_hw_init(struct rte_eth_dev *dev);
 332 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 333 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 334                                                      uint16_t seid,
 335                                                      uint16_t rule_type,
 336                                                      uint16_t *entries,
 337                                                      uint16_t count,
 338                                                      uint16_t rule_id);
 339 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 340                         struct rte_eth_mirror_conf *mirror_conf,
 341                         uint8_t sw_id, uint8_t on);
 342 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 343
 344 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 347                                            struct timespec *timestamp,
 348                                            uint32_t flags);
 349 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp);
 351 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 352
 353 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 354
 355 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 356                                    struct timespec *timestamp);
 357 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 358                                     const struct timespec *timestamp);
 359
 360 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 361                                          uint16_t queue_id);
 362 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 363                                           uint16_t queue_id);
 364
 365 static int i40e_get_regs(struct rte_eth_dev *dev,
 366                          struct rte_dev_reg_info *regs);
 367
 368 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 369
 370 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 371                            struct rte_dev_eeprom_info *eeprom);
 372
 373 static int i40e_get_module_info(struct rte_eth_dev *dev,
 374                                 struct rte_eth_dev_module_info *modinfo);
 375 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 376                                   struct rte_dev_eeprom_info *info);
 377
 378 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 379                                       struct rte_ether_addr *mac_addr);
 380
 381 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 382
 383 static int i40e_ethertype_filter_convert(
 384         const struct rte_eth_ethertype_filter *input,
 385         struct i40e_ethertype_filter *filter);
 386 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 387                                    struct i40e_ethertype_filter *filter);
 388
 389 static int i40e_tunnel_filter_convert(
 390         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 391         struct i40e_tunnel_filter *tunnel_filter);
 392 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 393                                 struct i40e_tunnel_filter *tunnel_filter);
 394 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 395
 396 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 397 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 398 static void i40e_filter_restore(struct i40e_pf *pf);
 399 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 400
 401 int i40e_logtype_init;
 402 int i40e_logtype_driver;
 403 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
 404 int i40e_logtype_rx;
 405 #endif
 406 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
 407 int i40e_logtype_tx;
 408 #endif
 409 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
 410 int i40e_logtype_tx_free;
 411 #endif
 412
 413 static const char *const valid_keys[] = {
 414         ETH_I40E_FLOATING_VEB_ARG,
 415         ETH_I40E_FLOATING_VEB_LIST_ARG,
 416         ETH_I40E_SUPPORT_MULTI_DRIVER,
 417         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 418         ETH_I40E_USE_LATEST_VEC,
 419         ETH_I40E_VF_MSG_CFG,
 420         NULL};
 421
 422 static const struct rte_pci_id pci_id_i40e_map[] = {
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 439         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 440         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 441         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 442         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 443         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 444         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 445         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 446         { .vendor_id = 0, /* sentinel */ },
 447 };
 448
 449 static const struct eth_dev_ops i40e_eth_dev_ops = {
 450         .dev_configure                = i40e_dev_configure,
 451         .dev_start                    = i40e_dev_start,
 452         .dev_stop                     = i40e_dev_stop,
 453         .dev_close                    = i40e_dev_close,
 454         .dev_reset                    = i40e_dev_reset,
 455         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 456         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 457         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 458         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 459         .dev_set_link_up              = i40e_dev_set_link_up,
 460         .dev_set_link_down            = i40e_dev_set_link_down,
 461         .link_update                  = i40e_dev_link_update,
 462         .stats_get                    = i40e_dev_stats_get,
 463         .xstats_get                   = i40e_dev_xstats_get,
 464         .xstats_get_names             = i40e_dev_xstats_get_names,
 465         .stats_reset                  = i40e_dev_stats_reset,
 466         .xstats_reset                 = i40e_dev_stats_reset,
 467         .fw_version_get               = i40e_fw_version_get,
 468         .dev_infos_get                = i40e_dev_info_get,
 469         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 470         .vlan_filter_set              = i40e_vlan_filter_set,
 471         .vlan_tpid_set                = i40e_vlan_tpid_set,
 472         .vlan_offload_set             = i40e_vlan_offload_set,
 473         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 474         .vlan_pvid_set                = i40e_vlan_pvid_set,
 475         .rx_queue_start               = i40e_dev_rx_queue_start,
 476         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 477         .tx_queue_start               = i40e_dev_tx_queue_start,
 478         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 479         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 480         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 481         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 482         .rx_queue_release             = i40e_dev_rx_queue_release,
 483         .rx_queue_count               = i40e_dev_rx_queue_count,
 484         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 485         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 486         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 487         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 488         .tx_queue_release             = i40e_dev_tx_queue_release,
 489         .dev_led_on                   = i40e_dev_led_on,
 490         .dev_led_off                  = i40e_dev_led_off,
 491         .flow_ctrl_get                = i40e_flow_ctrl_get,
 492         .flow_ctrl_set                = i40e_flow_ctrl_set,
 493         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 494         .mac_addr_add                 = i40e_macaddr_add,
 495         .mac_addr_remove              = i40e_macaddr_remove,
 496         .reta_update                  = i40e_dev_rss_reta_update,
 497         .reta_query                   = i40e_dev_rss_reta_query,
 498         .rss_hash_update              = i40e_dev_rss_hash_update,
 499         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 500         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 501         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 502         .filter_ctrl                  = i40e_dev_filter_ctrl,
 503         .rxq_info_get                 = i40e_rxq_info_get,
 504         .txq_info_get                 = i40e_txq_info_get,
 505         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 506         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 507         .mirror_rule_set              = i40e_mirror_rule_set,
 508         .mirror_rule_reset            = i40e_mirror_rule_reset,
 509         .timesync_enable              = i40e_timesync_enable,
 510         .timesync_disable             = i40e_timesync_disable,
 511         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 512         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 513         .get_dcb_info                 = i40e_dev_get_dcb_info,
 514         .timesync_adjust_time         = i40e_timesync_adjust_time,
 515         .timesync_read_time           = i40e_timesync_read_time,
 516         .timesync_write_time          = i40e_timesync_write_time,
 517         .get_reg                      = i40e_get_regs,
 518         .get_eeprom_length            = i40e_get_eeprom_length,
 519         .get_eeprom                   = i40e_get_eeprom,
 520         .get_module_info              = i40e_get_module_info,
 521         .get_module_eeprom            = i40e_get_module_eeprom,
 522         .mac_addr_set                 = i40e_set_default_mac_addr,
 523         .mtu_set                      = i40e_dev_mtu_set,
 524         .tm_ops_get                   = i40e_tm_ops_get,
 525 };
 526
 527 /* store statistics names and its offset in stats structure */
 528 struct rte_i40e_xstats_name_off {
 529         char name[RTE_ETH_XSTATS_NAME_SIZE];
 530         unsigned offset;
 531 };
 532
 533 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 534         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 535         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 536         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 537         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 538         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 539                 rx_unknown_protocol)},
 540         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 541         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 542         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 543         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 544 };
 545
 546 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 547                 sizeof(rte_i40e_stats_strings[0]))
 548
 549 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 550         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 551                 tx_dropped_link_down)},
 552         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 553         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 554                 illegal_bytes)},
 555         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 556         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 557                 mac_local_faults)},
 558         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 559                 mac_remote_faults)},
 560         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 561                 rx_length_errors)},
 562         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 563         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 564         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 565         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 566         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 567         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_127)},
 569         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_255)},
 571         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 572                 rx_size_511)},
 573         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 574                 rx_size_1023)},
 575         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 576                 rx_size_1522)},
 577         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 578                 rx_size_big)},
 579         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 580                 rx_undersize)},
 581         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 582                 rx_oversize)},
 583         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 584                 mac_short_packet_dropped)},
 585         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 586                 rx_fragments)},
 587         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 588         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 589         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_127)},
 591         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_255)},
 593         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 594                 tx_size_511)},
 595         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 596                 tx_size_1023)},
 597         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 598                 tx_size_1522)},
 599         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 600                 tx_size_big)},
 601         {"rx_flow_director_atr_match_packets",
 602                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 603         {"rx_flow_director_sb_match_packets",
 604                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 605         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 606                 tx_lpi_status)},
 607         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 608                 rx_lpi_status)},
 609         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 610                 tx_lpi_count)},
 611         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 612                 rx_lpi_count)},
 613 };
 614
 615 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 616                 sizeof(rte_i40e_hw_port_strings[0]))
 617
 618 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 619         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 620                 priority_xon_rx)},
 621         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xoff_rx)},
 623 };
 624
 625 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 626                 sizeof(rte_i40e_rxq_prio_strings[0]))
 627
 628 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 629         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 630                 priority_xon_tx)},
 631         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 632                 priority_xoff_tx)},
 633         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 634                 priority_xon_2_xoff)},
 635 };
 636
 637 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 638                 sizeof(rte_i40e_txq_prio_strings[0]))
 639
 640 static int
 641 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 642         struct rte_pci_device *pci_dev)
 643 {
 644         char name[RTE_ETH_NAME_MAX_LEN];
 645         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 646         int i, retval;
 647
 648         if (pci_dev->device.devargs) {
 649                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 650                                 &eth_da);
 651                 if (retval)
 652                         return retval;
 653         }
 654
 655         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 656                 sizeof(struct i40e_adapter),
 657                 eth_dev_pci_specific_init, pci_dev,
 658                 eth_i40e_dev_init, NULL);
 659
 660         if (retval || eth_da.nb_representor_ports < 1)
 661                 return retval;
 662
 663         /* probe VF representor ports */
 664         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 665                 pci_dev->device.name);
 666
 667         if (pf_ethdev == NULL)
 668                 return -ENODEV;
 669
 670         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 671                 struct i40e_vf_representor representor = {
 672                         .vf_id = eth_da.representor_ports[i],
 673                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 674                                 pf_ethdev->data->dev_private)->switch_domain_id,
 675                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 676                                 pf_ethdev->data->dev_private)
 677                 };
 678
 679                 /* representor port net_bdf_port */
 680                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 681                         pci_dev->device.name, eth_da.representor_ports[i]);
 682
 683                 retval = rte_eth_dev_create(&pci_dev->device, name,
 684                         sizeof(struct i40e_vf_representor), NULL, NULL,
 685                         i40e_vf_representor_init, &representor);
 686
 687                 if (retval)
 688                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 689                                 "representor %s.", name);
 690         }
 691
 692         return 0;
 693 }
 694
 695 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 696 {
 697         struct rte_eth_dev *ethdev;
 698
 699         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 700         if (!ethdev)
 701                 return 0;
 702
 703         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 704                 return rte_eth_dev_pci_generic_remove(pci_dev,
 705                                         i40e_vf_representor_uninit);
 706         else
 707                 return rte_eth_dev_pci_generic_remove(pci_dev,
 708                                                 eth_i40e_dev_uninit);
 709 }
 710
 711 static struct rte_pci_driver rte_i40e_pmd = {
 712         .id_table = pci_id_i40e_map,
 713         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 714         .probe = eth_i40e_pci_probe,
 715         .remove = eth_i40e_pci_remove,
 716 };
 717
 718 static inline void
 719 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 720                          uint32_t reg_val)
 721 {
 722         uint32_t ori_reg_val;
 723         struct rte_eth_dev *dev;
 724
 725         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 726         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 727         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 728         if (ori_reg_val != reg_val)
 729                 PMD_DRV_LOG(WARNING,
 730                             "i40e device %s changed global register [0x%08x]."
 731                             " original: 0x%08x, new: 0x%08x",
 732                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 733 }
 734
 735 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 736 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 737 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 738
 739 #ifndef I40E_GLQF_ORT
 740 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 741 #endif
 742 #ifndef I40E_GLQF_PIT
 743 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 744 #endif
 745 #ifndef I40E_GLQF_L3_MAP
 746 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 747 #endif
 748
 749 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 750 {
 751         /*
 752          * Initialize registers for parsing packet type of QinQ
 753          * This should be removed from code once proper
 754          * configuration API is added to avoid configuration conflicts
 755          * between ports of the same device.
 756          */
 757         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 758         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 759 }
 760
 761 static inline void i40e_config_automask(struct i40e_pf *pf)
 762 {
 763         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 764         uint32_t val;
 765
 766         /* INTENA flag is not auto-cleared for interrupt */
 767         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 768         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 769                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 770
 771         /* If support multi-driver, PF will use INT0. */
 772         if (!pf->support_multi_driver)
 773                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 774
 775         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 776 }
 777
 778 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 779
 780 /*
 781  * Add a ethertype filter to drop all flow control frames transmitted
 782  * from VSIs.
 783 */
 784 static void
 785 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 786 {
 787         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 788         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 789                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 790                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 791         int ret;
 792
 793         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 794                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 795                                 pf->main_vsi_seid, 0,
 796                                 TRUE, NULL, NULL);
 797         if (ret)
 798                 PMD_INIT_LOG(ERR,
 799                         "Failed to add filter to drop flow control frames from VSIs.");
 800 }
 801
 802 static int
 803 floating_veb_list_handler(__rte_unused const char *key,
 804                           const char *floating_veb_value,
 805                           void *opaque)
 806 {
 807         int idx = 0;
 808         unsigned int count = 0;
 809         char *end = NULL;
 810         int min, max;
 811         bool *vf_floating_veb = opaque;
 812
 813         while (isblank(*floating_veb_value))
 814                 floating_veb_value++;
 815
 816         /* Reset floating VEB configuration for VFs */
 817         for (idx = 0; idx < I40E_MAX_VF; idx++)
 818                 vf_floating_veb[idx] = false;
 819
 820         min = I40E_MAX_VF;
 821         do {
 822                 while (isblank(*floating_veb_value))
 823                         floating_veb_value++;
 824                 if (*floating_veb_value == '\0')
 825                         return -1;
 826                 errno = 0;
 827                 idx = strtoul(floating_veb_value, &end, 10);
 828                 if (errno || end == NULL)
 829                         return -1;
 830                 while (isblank(*end))
 831                         end++;
 832                 if (*end == '-') {
 833                         min = idx;
 834                 } else if ((*end == ';') || (*end == '\0')) {
 835                         max = idx;
 836                         if (min == I40E_MAX_VF)
 837                                 min = idx;
 838                         if (max >= I40E_MAX_VF)
 839                                 max = I40E_MAX_VF - 1;
 840                         for (idx = min; idx <= max; idx++) {
 841                                 vf_floating_veb[idx] = true;
 842                                 count++;
 843                         }
 844                         min = I40E_MAX_VF;
 845                 } else {
 846                         return -1;
 847                 }
 848                 floating_veb_value = end + 1;
 849         } while (*end != '\0');
 850
 851         if (count == 0)
 852                 return -1;
 853
 854         return 0;
 855 }
 856
 857 static void
 858 config_vf_floating_veb(struct rte_devargs *devargs,
 859                        uint16_t floating_veb,
 860                        bool *vf_floating_veb)
 861 {
 862         struct rte_kvargs *kvlist;
 863         int i;
 864         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 865
 866         if (!floating_veb)
 867                 return;
 868         /* All the VFs attach to the floating VEB by default
 869          * when the floating VEB is enabled.
 870          */
 871         for (i = 0; i < I40E_MAX_VF; i++)
 872                 vf_floating_veb[i] = true;
 873
 874         if (devargs == NULL)
 875                 return;
 876
 877         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 878         if (kvlist == NULL)
 879                 return;
 880
 881         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 882                 rte_kvargs_free(kvlist);
 883                 return;
 884         }
 885         /* When the floating_veb_list parameter exists, all the VFs
 886          * will attach to the legacy VEB firstly, then configure VFs
 887          * to the floating VEB according to the floating_veb_list.
 888          */
 889         if (rte_kvargs_process(kvlist, floating_veb_list,
 890                                floating_veb_list_handler,
 891                                vf_floating_veb) < 0) {
 892                 rte_kvargs_free(kvlist);
 893                 return;
 894         }
 895         rte_kvargs_free(kvlist);
 896 }
 897
 898 static int
 899 i40e_check_floating_handler(__rte_unused const char *key,
 900                             const char *value,
 901                             __rte_unused void *opaque)
 902 {
 903         if (strcmp(value, "1"))
 904                 return -1;
 905
 906         return 0;
 907 }
 908
 909 static int
 910 is_floating_veb_supported(struct rte_devargs *devargs)
 911 {
 912         struct rte_kvargs *kvlist;
 913         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 914
 915         if (devargs == NULL)
 916                 return 0;
 917
 918         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 919         if (kvlist == NULL)
 920                 return 0;
 921
 922         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 923                 rte_kvargs_free(kvlist);
 924                 return 0;
 925         }
 926         /* Floating VEB is enabled when there's key-value:
 927          * enable_floating_veb=1
 928          */
 929         if (rte_kvargs_process(kvlist, floating_veb_key,
 930                                i40e_check_floating_handler, NULL) < 0) {
 931                 rte_kvargs_free(kvlist);
 932                 return 0;
 933         }
 934         rte_kvargs_free(kvlist);
 935
 936         return 1;
 937 }
 938
 939 static void
 940 config_floating_veb(struct rte_eth_dev *dev)
 941 {
 942         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 945
 946         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 947
 948         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 949                 pf->floating_veb =
 950                         is_floating_veb_supported(pci_dev->device.devargs);
 951                 config_vf_floating_veb(pci_dev->device.devargs,
 952                                        pf->floating_veb,
 953                                        pf->floating_veb_list);
 954         } else {
 955                 pf->floating_veb = false;
 956         }
 957 }
 958
 959 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 960 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 961
 962 static int
 963 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 964 {
 965         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 966         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 967         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 968         int ret;
 969
 970         struct rte_hash_parameters ethertype_hash_params = {
 971                 .name = ethertype_hash_name,
 972                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 973                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 974                 .hash_func = rte_hash_crc,
 975                 .hash_func_init_val = 0,
 976                 .socket_id = rte_socket_id(),
 977         };
 978
 979         /* Initialize ethertype filter rule list and hash */
 980         TAILQ_INIT(&ethertype_rule->ethertype_list);
 981         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 982                  "ethertype_%s", dev->device->name);
 983         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 984         if (!ethertype_rule->hash_table) {
 985                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 986                 return -EINVAL;
 987         }
 988         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 989                                        sizeof(struct i40e_ethertype_filter *) *
 990                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 991                                        0);
 992         if (!ethertype_rule->hash_map) {
 993                 PMD_INIT_LOG(ERR,
 994                              "Failed to allocate memory for ethertype hash map!");
 995                 ret = -ENOMEM;
 996                 goto err_ethertype_hash_map_alloc;
 997         }
 998
 999         return 0;
1000
1001 err_ethertype_hash_map_alloc:
1002         rte_hash_free(ethertype_rule->hash_table);
1003
1004         return ret;
1005 }
1006
1007 static int
1008 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1009 {
1010         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1011         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1012         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1013         int ret;
1014
1015         struct rte_hash_parameters tunnel_hash_params = {
1016                 .name = tunnel_hash_name,
1017                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1018                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1019                 .hash_func = rte_hash_crc,
1020                 .hash_func_init_val = 0,
1021                 .socket_id = rte_socket_id(),
1022         };
1023
1024         /* Initialize tunnel filter rule list and hash */
1025         TAILQ_INIT(&tunnel_rule->tunnel_list);
1026         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1027                  "tunnel_%s", dev->device->name);
1028         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1029         if (!tunnel_rule->hash_table) {
1030                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1031                 return -EINVAL;
1032         }
1033         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1034                                     sizeof(struct i40e_tunnel_filter *) *
1035                                     I40E_MAX_TUNNEL_FILTER_NUM,
1036                                     0);
1037         if (!tunnel_rule->hash_map) {
1038                 PMD_INIT_LOG(ERR,
1039                              "Failed to allocate memory for tunnel hash map!");
1040                 ret = -ENOMEM;
1041                 goto err_tunnel_hash_map_alloc;
1042         }
1043
1044         return 0;
1045
1046 err_tunnel_hash_map_alloc:
1047         rte_hash_free(tunnel_rule->hash_table);
1048
1049         return ret;
1050 }
1051
1052 static int
1053 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1054 {
1055         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1056         struct i40e_fdir_info *fdir_info = &pf->fdir;
1057         char fdir_hash_name[RTE_HASH_NAMESIZE];
1058         int ret;
1059
1060         struct rte_hash_parameters fdir_hash_params = {
1061                 .name = fdir_hash_name,
1062                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1063                 .key_len = sizeof(struct i40e_fdir_input),
1064                 .hash_func = rte_hash_crc,
1065                 .hash_func_init_val = 0,
1066                 .socket_id = rte_socket_id(),
1067         };
1068
1069         /* Initialize flow director filter rule list and hash */
1070         TAILQ_INIT(&fdir_info->fdir_list);
1071         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1072                  "fdir_%s", dev->device->name);
1073         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1074         if (!fdir_info->hash_table) {
1075                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1076                 return -EINVAL;
1077         }
1078         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1079                                           sizeof(struct i40e_fdir_filter *) *
1080                                           I40E_MAX_FDIR_FILTER_NUM,
1081                                           0);
1082         if (!fdir_info->hash_map) {
1083                 PMD_INIT_LOG(ERR,
1084                              "Failed to allocate memory for fdir hash map!");
1085                 ret = -ENOMEM;
1086                 goto err_fdir_hash_map_alloc;
1087         }
1088         return 0;
1089
1090 err_fdir_hash_map_alloc:
1091         rte_hash_free(fdir_info->hash_table);
1092
1093         return ret;
1094 }
1095
1096 static void
1097 i40e_init_customized_info(struct i40e_pf *pf)
1098 {
1099         int i;
1100
1101         /* Initialize customized pctype */
1102         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1103                 pf->customized_pctype[i].index = i;
1104                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1105                 pf->customized_pctype[i].valid = false;
1106         }
1107
1108         pf->gtp_support = false;
1109 }
1110
1111 void
1112 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1113 {
1114         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1116         struct i40e_queue_regions *info = &pf->queue_region;
1117         uint16_t i;
1118
1119         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1120                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1121
1122         memset(info, 0, sizeof(struct i40e_queue_regions));
1123 }
1124
1125 static int
1126 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1127                                const char *value,
1128                                void *opaque)
1129 {
1130         struct i40e_pf *pf;
1131         unsigned long support_multi_driver;
1132         char *end;
1133
1134         pf = (struct i40e_pf *)opaque;
1135
1136         errno = 0;
1137         support_multi_driver = strtoul(value, &end, 10);
1138         if (errno != 0 || end == value || *end != 0) {
1139                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1140                 return -(EINVAL);
1141         }
1142
1143         if (support_multi_driver == 1 || support_multi_driver == 0)
1144                 pf->support_multi_driver = (bool)support_multi_driver;
1145         else
1146                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1147                             "enable global configuration by default."
1148                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1149         return 0;
1150 }
1151
1152 static int
1153 i40e_support_multi_driver(struct rte_eth_dev *dev)
1154 {
1155         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1156         struct rte_kvargs *kvlist;
1157         int kvargs_count;
1158
1159         /* Enable global configuration by default */
1160         pf->support_multi_driver = false;
1161
1162         if (!dev->device->devargs)
1163                 return 0;
1164
1165         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1166         if (!kvlist)
1167                 return -EINVAL;
1168
1169         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1170         if (!kvargs_count) {
1171                 rte_kvargs_free(kvlist);
1172                 return 0;
1173         }
1174
1175         if (kvargs_count > 1)
1176                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1177                             "the first invalid or last valid one is used !",
1178                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1179
1180         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1181                                i40e_parse_multi_drv_handler, pf) < 0) {
1182                 rte_kvargs_free(kvlist);
1183                 return -EINVAL;
1184         }
1185
1186         rte_kvargs_free(kvlist);
1187         return 0;
1188 }
1189
1190 static int
1191 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1192                                     uint32_t reg_addr, uint64_t reg_val,
1193                                     struct i40e_asq_cmd_details *cmd_details)
1194 {
1195         uint64_t ori_reg_val;
1196         struct rte_eth_dev *dev;
1197         int ret;
1198
1199         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1200         if (ret != I40E_SUCCESS) {
1201                 PMD_DRV_LOG(ERR,
1202                             "Fail to debug read from 0x%08x",
1203                             reg_addr);
1204                 return -EIO;
1205         }
1206         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1207
1208         if (ori_reg_val != reg_val)
1209                 PMD_DRV_LOG(WARNING,
1210                             "i40e device %s changed global register [0x%08x]."
1211                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1212                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1213
1214         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1215 }
1216
1217 static int
1218 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1219                                 const char *value,
1220                                 void *opaque)
1221 {
1222         struct i40e_adapter *ad = opaque;
1223         int use_latest_vec;
1224
1225         use_latest_vec = atoi(value);
1226
1227         if (use_latest_vec != 0 && use_latest_vec != 1)
1228                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1229
1230         ad->use_latest_vec = (uint8_t)use_latest_vec;
1231
1232         return 0;
1233 }
1234
1235 static int
1236 i40e_use_latest_vec(struct rte_eth_dev *dev)
1237 {
1238         struct i40e_adapter *ad =
1239                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1240         struct rte_kvargs *kvlist;
1241         int kvargs_count;
1242
1243         ad->use_latest_vec = false;
1244
1245         if (!dev->device->devargs)
1246                 return 0;
1247
1248         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1249         if (!kvlist)
1250                 return -EINVAL;
1251
1252         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1253         if (!kvargs_count) {
1254                 rte_kvargs_free(kvlist);
1255                 return 0;
1256         }
1257
1258         if (kvargs_count > 1)
1259                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1260                             "the first invalid or last valid one is used !",
1261                             ETH_I40E_USE_LATEST_VEC);
1262
1263         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1264                                 i40e_parse_latest_vec_handler, ad) < 0) {
1265                 rte_kvargs_free(kvlist);
1266                 return -EINVAL;
1267         }
1268
1269         rte_kvargs_free(kvlist);
1270         return 0;
1271 }
1272
1273 static int
1274 read_vf_msg_config(__rte_unused const char *key,
1275                                const char *value,
1276                                void *opaque)
1277 {
1278         struct i40e_vf_msg_cfg *cfg = opaque;
1279
1280         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1281                         &cfg->ignore_second) != 3) {
1282                 memset(cfg, 0, sizeof(*cfg));
1283                 PMD_DRV_LOG(ERR, "format error! example: "
1284                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1285                 return -EINVAL;
1286         }
1287
1288         /*
1289          * If the message validation function been enabled, the 'period'
1290          * and 'ignore_second' must greater than 0.
1291          */
1292         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1293                 memset(cfg, 0, sizeof(*cfg));
1294                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1295                                 " number must be greater than 0!",
1296                                 ETH_I40E_VF_MSG_CFG);
1297                 return -EINVAL;
1298         }
1299
1300         return 0;
1301 }
1302
1303 static int
1304 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1305                 struct i40e_vf_msg_cfg *msg_cfg)
1306 {
1307         struct rte_kvargs *kvlist;
1308         int kvargs_count;
1309         int ret = 0;
1310
1311         memset(msg_cfg, 0, sizeof(*msg_cfg));
1312
1313         if (!dev->device->devargs)
1314                 return ret;
1315
1316         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1317         if (!kvlist)
1318                 return -EINVAL;
1319
1320         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1321         if (!kvargs_count)
1322                 goto free_end;
1323
1324         if (kvargs_count > 1) {
1325                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1326                                 ETH_I40E_VF_MSG_CFG);
1327                 ret = -EINVAL;
1328                 goto free_end;
1329         }
1330
1331         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1332                         read_vf_msg_config, msg_cfg) < 0)
1333                 ret = -EINVAL;
1334
1335 free_end:
1336         rte_kvargs_free(kvlist);
1337         return ret;
1338 }
1339
1340 #define I40E_ALARM_INTERVAL 50000 /* us */
1341
1342 static int
1343 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1344 {
1345         struct rte_pci_device *pci_dev;
1346         struct rte_intr_handle *intr_handle;
1347         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1348         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         struct i40e_vsi *vsi;
1350         int ret;
1351         uint32_t len, val;
1352         uint8_t aq_fail = 0;
1353
1354         PMD_INIT_FUNC_TRACE();
1355
1356         dev->dev_ops = &i40e_eth_dev_ops;
1357         dev->rx_pkt_burst = i40e_recv_pkts;
1358         dev->tx_pkt_burst = i40e_xmit_pkts;
1359         dev->tx_pkt_prepare = i40e_prep_pkts;
1360
1361         /* for secondary processes, we don't initialise any further as primary
1362          * has already done this work. Only check we don't need a different
1363          * RX function */
1364         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1365                 i40e_set_rx_function(dev);
1366                 i40e_set_tx_function(dev);
1367                 return 0;
1368         }
1369         i40e_set_default_ptype_table(dev);
1370         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1371         intr_handle = &pci_dev->intr_handle;
1372
1373         rte_eth_copy_pci_info(dev, pci_dev);
1374
1375         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1376         pf->adapter->eth_dev = dev;
1377         pf->dev_data = dev->data;
1378
1379         hw->back = I40E_PF_TO_ADAPTER(pf);
1380         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1381         if (!hw->hw_addr) {
1382                 PMD_INIT_LOG(ERR,
1383                         "Hardware is not available, as address is NULL");
1384                 return -ENODEV;
1385         }
1386
1387         hw->vendor_id = pci_dev->id.vendor_id;
1388         hw->device_id = pci_dev->id.device_id;
1389         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1390         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1391         hw->bus.device = pci_dev->addr.devid;
1392         hw->bus.func = pci_dev->addr.function;
1393         hw->adapter_stopped = 0;
1394         hw->adapter_closed = 0;
1395
1396         /*
1397          * Switch Tag value should not be identical to either the First Tag
1398          * or Second Tag values. So set something other than common Ethertype
1399          * for internal switching.
1400          */
1401         hw->switch_tag = 0xffff;
1402
1403         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1404         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1405                 PMD_INIT_LOG(ERR, "\nERROR: "
1406                         "Firmware recovery mode detected. Limiting functionality.\n"
1407                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1408                         "User Guide for details on firmware recovery mode.");
1409                 return -EIO;
1410         }
1411
1412         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1413         /* Check if need to support multi-driver */
1414         i40e_support_multi_driver(dev);
1415         /* Check if users want the latest supported vec path */
1416         i40e_use_latest_vec(dev);
1417
1418         /* Make sure all is clean before doing PF reset */
1419         i40e_clear_hw(hw);
1420
1421         /* Reset here to make sure all is clean for each PF */
1422         ret = i40e_pf_reset(hw);
1423         if (ret) {
1424                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1425                 return ret;
1426         }
1427
1428         /* Initialize the shared code (base driver) */
1429         ret = i40e_init_shared_code(hw);
1430         if (ret) {
1431                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1432                 return ret;
1433         }
1434
1435         /* Initialize the parameters for adminq */
1436         i40e_init_adminq_parameter(hw);
1437         ret = i40e_init_adminq(hw);
1438         if (ret != I40E_SUCCESS) {
1439                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1440                 return -EIO;
1441         }
1442         /* Firmware of SFP x722 does not support adminq option */
1443         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1444                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1445
1446         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1447                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1448                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1449                      ((hw->nvm.version >> 12) & 0xf),
1450                      ((hw->nvm.version >> 4) & 0xff),
1451                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1452
1453         /* Initialize the hardware */
1454         i40e_hw_init(dev);
1455
1456         i40e_config_automask(pf);
1457
1458         i40e_set_default_pctype_table(dev);
1459
1460         /*
1461          * To work around the NVM issue, initialize registers
1462          * for packet type of QinQ by software.
1463          * It should be removed once issues are fixed in NVM.
1464          */
1465         if (!pf->support_multi_driver)
1466                 i40e_GLQF_reg_init(hw);
1467
1468         /* Initialize the input set for filters (hash and fd) to default value */
1469         i40e_filter_input_set_init(pf);
1470
1471         /* initialise the L3_MAP register */
1472         if (!pf->support_multi_driver) {
1473                 ret = i40e_aq_debug_write_global_register(hw,
1474                                                    I40E_GLQF_L3_MAP(40),
1475                                                    0x00000028,  NULL);
1476                 if (ret)
1477                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1478                                      ret);
1479                 PMD_INIT_LOG(DEBUG,
1480                              "Global register 0x%08x is changed with 0x28",
1481                              I40E_GLQF_L3_MAP(40));
1482         }
1483
1484         /* Need the special FW version to support floating VEB */
1485         config_floating_veb(dev);
1486         /* Clear PXE mode */
1487         i40e_clear_pxe_mode(hw);
1488         i40e_dev_sync_phy_type(hw);
1489
1490         /*
1491          * On X710, performance number is far from the expectation on recent
1492          * firmware versions. The fix for this issue may not be integrated in
1493          * the following firmware version. So the workaround in software driver
1494          * is needed. It needs to modify the initial values of 3 internal only
1495          * registers. Note that the workaround can be removed when it is fixed
1496          * in firmware in the future.
1497          */
1498         i40e_configure_registers(hw);
1499
1500         /* Get hw capabilities */
1501         ret = i40e_get_cap(hw);
1502         if (ret != I40E_SUCCESS) {
1503                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1504                 goto err_get_capabilities;
1505         }
1506
1507         /* Initialize parameters for PF */
1508         ret = i40e_pf_parameter_init(dev);
1509         if (ret != 0) {
1510                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1511                 goto err_parameter_init;
1512         }
1513
1514         /* Initialize the queue management */
1515         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1516         if (ret < 0) {
1517                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1518                 goto err_qp_pool_init;
1519         }
1520         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1521                                 hw->func_caps.num_msix_vectors - 1);
1522         if (ret < 0) {
1523                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1524                 goto err_msix_pool_init;
1525         }
1526
1527         /* Initialize lan hmc */
1528         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1529                                 hw->func_caps.num_rx_qp, 0, 0);
1530         if (ret != I40E_SUCCESS) {
1531                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1532                 goto err_init_lan_hmc;
1533         }
1534
1535         /* Configure lan hmc */
1536         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1537         if (ret != I40E_SUCCESS) {
1538                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1539                 goto err_configure_lan_hmc;
1540         }
1541
1542         /* Get and check the mac address */
1543         i40e_get_mac_addr(hw, hw->mac.addr);
1544         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1545                 PMD_INIT_LOG(ERR, "mac address is not valid");
1546                 ret = -EIO;
1547                 goto err_get_mac_addr;
1548         }
1549         /* Copy the permanent MAC address */
1550         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1551                         (struct rte_ether_addr *)hw->mac.perm_addr);
1552
1553         /* Disable flow control */
1554         hw->fc.requested_mode = I40E_FC_NONE;
1555         i40e_set_fc(hw, &aq_fail, TRUE);
1556
1557         /* Set the global registers with default ether type value */
1558         if (!pf->support_multi_driver) {
1559                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1560                                          RTE_ETHER_TYPE_VLAN);
1561                 if (ret != I40E_SUCCESS) {
1562                         PMD_INIT_LOG(ERR,
1563                                      "Failed to set the default outer "
1564                                      "VLAN ether type");
1565                         goto err_setup_pf_switch;
1566                 }
1567         }
1568
1569         /* PF setup, which includes VSI setup */
1570         ret = i40e_pf_setup(pf);
1571         if (ret) {
1572                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1573                 goto err_setup_pf_switch;
1574         }
1575
1576         vsi = pf->main_vsi;
1577
1578         /* Disable double vlan by default */
1579         i40e_vsi_config_double_vlan(vsi, FALSE);
1580
1581         /* Disable S-TAG identification when floating_veb is disabled */
1582         if (!pf->floating_veb) {
1583                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1584                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1585                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1586                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1587                 }
1588         }
1589
1590         if (!vsi->max_macaddrs)
1591                 len = RTE_ETHER_ADDR_LEN;
1592         else
1593                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1594
1595         /* Should be after VSI initialized */
1596         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1597         if (!dev->data->mac_addrs) {
1598                 PMD_INIT_LOG(ERR,
1599                         "Failed to allocated memory for storing mac address");
1600                 goto err_mac_alloc;
1601         }
1602         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1603                                         &dev->data->mac_addrs[0]);
1604
1605         /* Pass the information to the rte_eth_dev_close() that it should also
1606          * release the private port resources.
1607          */
1608         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1609
1610         /* Init dcb to sw mode by default */
1611         ret = i40e_dcb_init_configure(dev, TRUE);
1612         if (ret != I40E_SUCCESS) {
1613                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1614                 pf->flags &= ~I40E_FLAG_DCB;
1615         }
1616         /* Update HW struct after DCB configuration */
1617         i40e_get_cap(hw);
1618
1619         /* initialize pf host driver to setup SRIOV resource if applicable */
1620         i40e_pf_host_init(dev);
1621
1622         /* register callback func to eal lib */
1623         rte_intr_callback_register(intr_handle,
1624                                    i40e_dev_interrupt_handler, dev);
1625
1626         /* configure and enable device interrupt */
1627         i40e_pf_config_irq0(hw, TRUE);
1628         i40e_pf_enable_irq0(hw);
1629
1630         /* enable uio intr after callback register */
1631         rte_intr_enable(intr_handle);
1632
1633         /* By default disable flexible payload in global configuration */
1634         if (!pf->support_multi_driver)
1635                 i40e_flex_payload_reg_set_default(hw);
1636
1637         /*
1638          * Add an ethertype filter to drop all flow control frames transmitted
1639          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1640          * frames to wire.
1641          */
1642         i40e_add_tx_flow_control_drop_filter(pf);
1643
1644         /* Set the max frame size to 0x2600 by default,
1645          * in case other drivers changed the default value.
1646          */
1647         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1648
1649         /* initialize mirror rule list */
1650         TAILQ_INIT(&pf->mirror_list);
1651
1652         /* initialize Traffic Manager configuration */
1653         i40e_tm_conf_init(dev);
1654
1655         /* Initialize customized information */
1656         i40e_init_customized_info(pf);
1657
1658         ret = i40e_init_ethtype_filter_list(dev);
1659         if (ret < 0)
1660                 goto err_init_ethtype_filter_list;
1661         ret = i40e_init_tunnel_filter_list(dev);
1662         if (ret < 0)
1663                 goto err_init_tunnel_filter_list;
1664         ret = i40e_init_fdir_filter_list(dev);
1665         if (ret < 0)
1666                 goto err_init_fdir_filter_list;
1667
1668         /* initialize queue region configuration */
1669         i40e_init_queue_region_conf(dev);
1670
1671         /* initialize rss configuration from rte_flow */
1672         memset(&pf->rss_info, 0,
1673                 sizeof(struct i40e_rte_flow_rss_conf));
1674
1675         /* reset all stats of the device, including pf and main vsi */
1676         i40e_dev_stats_reset(dev);
1677
1678         return 0;
1679
1680 err_init_fdir_filter_list:
1681         rte_free(pf->tunnel.hash_table);
1682         rte_free(pf->tunnel.hash_map);
1683 err_init_tunnel_filter_list:
1684         rte_free(pf->ethertype.hash_table);
1685         rte_free(pf->ethertype.hash_map);
1686 err_init_ethtype_filter_list:
1687         rte_free(dev->data->mac_addrs);
1688         dev->data->mac_addrs = NULL;
1689 err_mac_alloc:
1690         i40e_vsi_release(pf->main_vsi);
1691 err_setup_pf_switch:
1692 err_get_mac_addr:
1693 err_configure_lan_hmc:
1694         (void)i40e_shutdown_lan_hmc(hw);
1695 err_init_lan_hmc:
1696         i40e_res_pool_destroy(&pf->msix_pool);
1697 err_msix_pool_init:
1698         i40e_res_pool_destroy(&pf->qp_pool);
1699 err_qp_pool_init:
1700 err_parameter_init:
1701 err_get_capabilities:
1702         (void)i40e_shutdown_adminq(hw);
1703
1704         return ret;
1705 }
1706
1707 static void
1708 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1709 {
1710         struct i40e_ethertype_filter *p_ethertype;
1711         struct i40e_ethertype_rule *ethertype_rule;
1712
1713         ethertype_rule = &pf->ethertype;
1714         /* Remove all ethertype filter rules and hash */
1715         if (ethertype_rule->hash_map)
1716                 rte_free(ethertype_rule->hash_map);
1717         if (ethertype_rule->hash_table)
1718                 rte_hash_free(ethertype_rule->hash_table);
1719
1720         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1721                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1722                              p_ethertype, rules);
1723                 rte_free(p_ethertype);
1724         }
1725 }
1726
1727 static void
1728 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1729 {
1730         struct i40e_tunnel_filter *p_tunnel;
1731         struct i40e_tunnel_rule *tunnel_rule;
1732
1733         tunnel_rule = &pf->tunnel;
1734         /* Remove all tunnel director rules and hash */
1735         if (tunnel_rule->hash_map)
1736                 rte_free(tunnel_rule->hash_map);
1737         if (tunnel_rule->hash_table)
1738                 rte_hash_free(tunnel_rule->hash_table);
1739
1740         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1741                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1742                 rte_free(p_tunnel);
1743         }
1744 }
1745
1746 static void
1747 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1748 {
1749         struct i40e_fdir_filter *p_fdir;
1750         struct i40e_fdir_info *fdir_info;
1751
1752         fdir_info = &pf->fdir;
1753         /* Remove all flow director rules and hash */
1754         if (fdir_info->hash_map)
1755                 rte_free(fdir_info->hash_map);
1756         if (fdir_info->hash_table)
1757                 rte_hash_free(fdir_info->hash_table);
1758
1759         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1760                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1761                 rte_free(p_fdir);
1762         }
1763 }
1764
1765 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1766 {
1767         /*
1768          * Disable by default flexible payload
1769          * for corresponding L2/L3/L4 layers.
1770          */
1771         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1772         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1773         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1774 }
1775
1776 static int
1777 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1778 {
1779         struct i40e_hw *hw;
1780
1781         PMD_INIT_FUNC_TRACE();
1782
1783         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1784                 return 0;
1785
1786         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787
1788         if (hw->adapter_closed == 0)
1789                 i40e_dev_close(dev);
1790
1791         return 0;
1792 }
1793
1794 static int
1795 i40e_dev_configure(struct rte_eth_dev *dev)
1796 {
1797         struct i40e_adapter *ad =
1798                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1799         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1800         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1801         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1802         int i, ret;
1803
1804         ret = i40e_dev_sync_phy_type(hw);
1805         if (ret)
1806                 return ret;
1807
1808         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1809          * bulk allocation or vector Rx preconditions we will reset it.
1810          */
1811         ad->rx_bulk_alloc_allowed = true;
1812         ad->rx_vec_allowed = true;
1813         ad->tx_simple_allowed = true;
1814         ad->tx_vec_allowed = true;
1815
1816         dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1817
1818         /* Only legacy filter API needs the following fdir config. So when the
1819          * legacy filter API is deprecated, the following codes should also be
1820          * removed.
1821          */
1822         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1823                 ret = i40e_fdir_setup(pf);
1824                 if (ret != I40E_SUCCESS) {
1825                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1826                         return -ENOTSUP;
1827                 }
1828                 ret = i40e_fdir_configure(dev);
1829                 if (ret < 0) {
1830                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1831                         goto err;
1832                 }
1833         } else
1834                 i40e_fdir_teardown(pf);
1835
1836         ret = i40e_dev_init_vlan(dev);
1837         if (ret < 0)
1838                 goto err;
1839
1840         /* VMDQ setup.
1841          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1842          *  RSS setting have different requirements.
1843          *  General PMD driver call sequence are NIC init, configure,
1844          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1845          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1846          *  applicable. So, VMDQ setting has to be done before
1847          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1848          *  For RSS setting, it will try to calculate actual configured RX queue
1849          *  number, which will be available after rx_queue_setup(). dev_start()
1850          *  function is good to place RSS setup.
1851          */
1852         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1853                 ret = i40e_vmdq_setup(dev);
1854                 if (ret)
1855                         goto err;
1856         }
1857
1858         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1859                 ret = i40e_dcb_setup(dev);
1860                 if (ret) {
1861                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1862                         goto err_dcb;
1863                 }
1864         }
1865
1866         TAILQ_INIT(&pf->flow_list);
1867
1868         return 0;
1869
1870 err_dcb:
1871         /* need to release vmdq resource if exists */
1872         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1873                 i40e_vsi_release(pf->vmdq[i].vsi);
1874                 pf->vmdq[i].vsi = NULL;
1875         }
1876         rte_free(pf->vmdq);
1877         pf->vmdq = NULL;
1878 err:
1879         /* Need to release fdir resource if exists.
1880          * Only legacy filter API needs the following fdir config. So when the
1881          * legacy filter API is deprecated, the following code should also be
1882          * removed.
1883          */
1884         i40e_fdir_teardown(pf);
1885         return ret;
1886 }
1887
1888 void
1889 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1890 {
1891         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1892         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1893         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1894         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1895         uint16_t msix_vect = vsi->msix_intr;
1896         uint16_t i;
1897
1898         for (i = 0; i < vsi->nb_qps; i++) {
1899                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1900                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1901                 rte_wmb();
1902         }
1903
1904         if (vsi->type != I40E_VSI_SRIOV) {
1905                 if (!rte_intr_allow_others(intr_handle)) {
1906                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1907                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1908                         I40E_WRITE_REG(hw,
1909                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1910                                        0);
1911                 } else {
1912                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1913                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1914                         I40E_WRITE_REG(hw,
1915                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1916                                                        msix_vect - 1), 0);
1917                 }
1918         } else {
1919                 uint32_t reg;
1920                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1921                         vsi->user_param + (msix_vect - 1);
1922
1923                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1924                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1925         }
1926         I40E_WRITE_FLUSH(hw);
1927 }
1928
1929 static void
1930 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1931                        int base_queue, int nb_queue,
1932                        uint16_t itr_idx)
1933 {
1934         int i;
1935         uint32_t val;
1936         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1937         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1938
1939         /* Bind all RX queues to allocated MSIX interrupt */
1940         for (i = 0; i < nb_queue; i++) {
1941                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1942                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1943                         ((base_queue + i + 1) <<
1944                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1945                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1946                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1947
1948                 if (i == nb_queue - 1)
1949                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1950                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1951         }
1952
1953         /* Write first RX queue to Link list register as the head element */
1954         if (vsi->type != I40E_VSI_SRIOV) {
1955                 uint16_t interval =
1956                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1957
1958                 if (msix_vect == I40E_MISC_VEC_ID) {
1959                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1960                                        (base_queue <<
1961                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1962                                        (0x0 <<
1963                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1964                         I40E_WRITE_REG(hw,
1965                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1966                                        interval);
1967                 } else {
1968                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1969                                        (base_queue <<
1970                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1971                                        (0x0 <<
1972                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1973                         I40E_WRITE_REG(hw,
1974                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1975                                                        msix_vect - 1),
1976                                        interval);
1977                 }
1978         } else {
1979                 uint32_t reg;
1980
1981                 if (msix_vect == I40E_MISC_VEC_ID) {
1982                         I40E_WRITE_REG(hw,
1983                                        I40E_VPINT_LNKLST0(vsi->user_param),
1984                                        (base_queue <<
1985                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1986                                        (0x0 <<
1987                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1988                 } else {
1989                         /* num_msix_vectors_vf needs to minus irq0 */
1990                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1991                                 vsi->user_param + (msix_vect - 1);
1992
1993                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1994                                        (base_queue <<
1995                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1996                                        (0x0 <<
1997                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1998                 }
1999         }
2000
2001         I40E_WRITE_FLUSH(hw);
2002 }
2003
2004 void
2005 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2006 {
2007         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2008         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2009         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2010         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2011         uint16_t msix_vect = vsi->msix_intr;
2012         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2013         uint16_t queue_idx = 0;
2014         int record = 0;
2015         int i;
2016
2017         for (i = 0; i < vsi->nb_qps; i++) {
2018                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2019                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2020         }
2021
2022         /* VF bind interrupt */
2023         if (vsi->type == I40E_VSI_SRIOV) {
2024                 __vsi_queues_bind_intr(vsi, msix_vect,
2025                                        vsi->base_queue, vsi->nb_qps,
2026                                        itr_idx);
2027                 return;
2028         }
2029
2030         /* PF & VMDq bind interrupt */
2031         if (rte_intr_dp_is_en(intr_handle)) {
2032                 if (vsi->type == I40E_VSI_MAIN) {
2033                         queue_idx = 0;
2034                         record = 1;
2035                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2036                         struct i40e_vsi *main_vsi =
2037                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2038                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2039                         record = 1;
2040                 }
2041         }
2042
2043         for (i = 0; i < vsi->nb_used_qps; i++) {
2044                 if (nb_msix <= 1) {
2045                         if (!rte_intr_allow_others(intr_handle))
2046                                 /* allow to share MISC_VEC_ID */
2047                                 msix_vect = I40E_MISC_VEC_ID;
2048
2049                         /* no enough msix_vect, map all to one */
2050                         __vsi_queues_bind_intr(vsi, msix_vect,
2051                                                vsi->base_queue + i,
2052                                                vsi->nb_used_qps - i,
2053                                                itr_idx);
2054                         for (; !!record && i < vsi->nb_used_qps; i++)
2055                                 intr_handle->intr_vec[queue_idx + i] =
2056                                         msix_vect;
2057                         break;
2058                 }
2059                 /* 1:1 queue/msix_vect mapping */
2060                 __vsi_queues_bind_intr(vsi, msix_vect,
2061                                        vsi->base_queue + i, 1,
2062                                        itr_idx);
2063                 if (!!record)
2064                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2065
2066                 msix_vect++;
2067                 nb_msix--;
2068         }
2069 }
2070
2071 static void
2072 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2073 {
2074         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2075         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2076         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2077         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2078         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2079         uint16_t msix_intr, i;
2080
2081         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2082                 for (i = 0; i < vsi->nb_msix; i++) {
2083                         msix_intr = vsi->msix_intr + i;
2084                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2085                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2086                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2087                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2088                 }
2089         else
2090                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2091                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2092                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2093                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2094
2095         I40E_WRITE_FLUSH(hw);
2096 }
2097
2098 static void
2099 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2100 {
2101         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2102         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2103         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2104         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2105         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2106         uint16_t msix_intr, i;
2107
2108         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2109                 for (i = 0; i < vsi->nb_msix; i++) {
2110                         msix_intr = vsi->msix_intr + i;
2111                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2112                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2113                 }
2114         else
2115                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2116                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2117
2118         I40E_WRITE_FLUSH(hw);
2119 }
2120
2121 static inline uint8_t
2122 i40e_parse_link_speeds(uint16_t link_speeds)
2123 {
2124         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2125
2126         if (link_speeds & ETH_LINK_SPEED_40G)
2127                 link_speed |= I40E_LINK_SPEED_40GB;
2128         if (link_speeds & ETH_LINK_SPEED_25G)
2129                 link_speed |= I40E_LINK_SPEED_25GB;
2130         if (link_speeds & ETH_LINK_SPEED_20G)
2131                 link_speed |= I40E_LINK_SPEED_20GB;
2132         if (link_speeds & ETH_LINK_SPEED_10G)
2133                 link_speed |= I40E_LINK_SPEED_10GB;
2134         if (link_speeds & ETH_LINK_SPEED_1G)
2135                 link_speed |= I40E_LINK_SPEED_1GB;
2136         if (link_speeds & ETH_LINK_SPEED_100M)
2137                 link_speed |= I40E_LINK_SPEED_100MB;
2138
2139         return link_speed;
2140 }
2141
2142 static int
2143 i40e_phy_conf_link(struct i40e_hw *hw,
2144                    uint8_t abilities,
2145                    uint8_t force_speed,
2146                    bool is_up)
2147 {
2148         enum i40e_status_code status;
2149         struct i40e_aq_get_phy_abilities_resp phy_ab;
2150         struct i40e_aq_set_phy_config phy_conf;
2151         enum i40e_aq_phy_type cnt;
2152         uint8_t avail_speed;
2153         uint32_t phy_type_mask = 0;
2154
2155         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2156                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2157                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2158                         I40E_AQ_PHY_FLAG_LOW_POWER;
2159         int ret = -ENOTSUP;
2160
2161         /* To get phy capabilities of available speeds. */
2162         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2163                                               NULL);
2164         if (status) {
2165                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2166                                 status);
2167                 return ret;
2168         }
2169         avail_speed = phy_ab.link_speed;
2170
2171         /* To get the current phy config. */
2172         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2173                                               NULL);
2174         if (status) {
2175                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2176                                 status);
2177                 return ret;
2178         }
2179
2180         /* If link needs to go up and it is in autoneg mode the speed is OK,
2181          * no need to set up again.
2182          */
2183         if (is_up && phy_ab.phy_type != 0 &&
2184                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2185                      phy_ab.link_speed != 0)
2186                 return I40E_SUCCESS;
2187
2188         memset(&phy_conf, 0, sizeof(phy_conf));
2189
2190         /* bits 0-2 use the values from get_phy_abilities_resp */
2191         abilities &= ~mask;
2192         abilities |= phy_ab.abilities & mask;
2193
2194         phy_conf.abilities = abilities;
2195
2196         /* If link needs to go up, but the force speed is not supported,
2197          * Warn users and config the default available speeds.
2198          */
2199         if (is_up && !(force_speed & avail_speed)) {
2200                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2201                 phy_conf.link_speed = avail_speed;
2202         } else {
2203                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2204         }
2205
2206         /* PHY type mask needs to include each type except PHY type extension */
2207         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2208                 phy_type_mask |= 1 << cnt;
2209
2210         /* use get_phy_abilities_resp value for the rest */
2211         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2212         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2213                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2214                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2215         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2216         phy_conf.eee_capability = phy_ab.eee_capability;
2217         phy_conf.eeer = phy_ab.eeer_val;
2218         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2219
2220         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2221                     phy_ab.abilities, phy_ab.link_speed);
2222         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2223                     phy_conf.abilities, phy_conf.link_speed);
2224
2225         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2226         if (status)
2227                 return ret;
2228
2229         return I40E_SUCCESS;
2230 }
2231
2232 static int
2233 i40e_apply_link_speed(struct rte_eth_dev *dev)
2234 {
2235         uint8_t speed;
2236         uint8_t abilities = 0;
2237         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2238         struct rte_eth_conf *conf = &dev->data->dev_conf;
2239
2240         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2241                 conf->link_speeds = ETH_LINK_SPEED_40G |
2242                                     ETH_LINK_SPEED_25G |
2243                                     ETH_LINK_SPEED_20G |
2244                                     ETH_LINK_SPEED_10G |
2245                                     ETH_LINK_SPEED_1G |
2246                                     ETH_LINK_SPEED_100M;
2247         }
2248         speed = i40e_parse_link_speeds(conf->link_speeds);
2249         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2250                      I40E_AQ_PHY_AN_ENABLED |
2251                      I40E_AQ_PHY_LINK_ENABLED;
2252
2253         return i40e_phy_conf_link(hw, abilities, speed, true);
2254 }
2255
2256 static int
2257 i40e_dev_start(struct rte_eth_dev *dev)
2258 {
2259         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2260         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261         struct i40e_vsi *main_vsi = pf->main_vsi;
2262         int ret, i;
2263         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2264         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2265         uint32_t intr_vector = 0;
2266         struct i40e_vsi *vsi;
2267
2268         hw->adapter_stopped = 0;
2269
2270         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2271                 PMD_INIT_LOG(ERR,
2272                 "Invalid link_speeds for port %u, autonegotiation disabled",
2273                               dev->data->port_id);
2274                 return -EINVAL;
2275         }
2276
2277         rte_intr_disable(intr_handle);
2278
2279         if ((rte_intr_cap_multiple(intr_handle) ||
2280              !RTE_ETH_DEV_SRIOV(dev).active) &&
2281             dev->data->dev_conf.intr_conf.rxq != 0) {
2282                 intr_vector = dev->data->nb_rx_queues;
2283                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2284                 if (ret)
2285                         return ret;
2286         }
2287
2288         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2289                 intr_handle->intr_vec =
2290                         rte_zmalloc("intr_vec",
2291                                     dev->data->nb_rx_queues * sizeof(int),
2292                                     0);
2293                 if (!intr_handle->intr_vec) {
2294                         PMD_INIT_LOG(ERR,
2295                                 "Failed to allocate %d rx_queues intr_vec",
2296                                 dev->data->nb_rx_queues);
2297                         return -ENOMEM;
2298                 }
2299         }
2300
2301         /* Initialize VSI */
2302         ret = i40e_dev_rxtx_init(pf);
2303         if (ret != I40E_SUCCESS) {
2304                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2305                 goto err_up;
2306         }
2307
2308         /* Map queues with MSIX interrupt */
2309         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2310                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2311         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2312         i40e_vsi_enable_queues_intr(main_vsi);
2313
2314         /* Map VMDQ VSI queues with MSIX interrupt */
2315         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2316                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2317                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2318                                           I40E_ITR_INDEX_DEFAULT);
2319                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2320         }
2321
2322         /* enable FDIR MSIX interrupt */
2323         if (pf->fdir.fdir_vsi) {
2324                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2325                                           I40E_ITR_INDEX_NONE);
2326                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2327         }
2328
2329         /* Enable all queues which have been configured */
2330         ret = i40e_dev_switch_queues(pf, TRUE);
2331         if (ret != I40E_SUCCESS) {
2332                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2333                 goto err_up;
2334         }
2335
2336         /* Enable receiving broadcast packets */
2337         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2338         if (ret != I40E_SUCCESS)
2339                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2340
2341         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2342                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2343                                                 true, NULL);
2344                 if (ret != I40E_SUCCESS)
2345                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2346         }
2347
2348         /* Enable the VLAN promiscuous mode. */
2349         if (pf->vfs) {
2350                 for (i = 0; i < pf->vf_num; i++) {
2351                         vsi = pf->vfs[i].vsi;
2352                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2353                                                      true, NULL);
2354                 }
2355         }
2356
2357         /* Enable mac loopback mode */
2358         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2359             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2360                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2361                 if (ret != I40E_SUCCESS) {
2362                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2363                         goto err_up;
2364                 }
2365         }
2366
2367         /* Apply link configure */
2368         ret = i40e_apply_link_speed(dev);
2369         if (I40E_SUCCESS != ret) {
2370                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2371                 goto err_up;
2372         }
2373
2374         if (!rte_intr_allow_others(intr_handle)) {
2375                 rte_intr_callback_unregister(intr_handle,
2376                                              i40e_dev_interrupt_handler,
2377                                              (void *)dev);
2378                 /* configure and enable device interrupt */
2379                 i40e_pf_config_irq0(hw, FALSE);
2380                 i40e_pf_enable_irq0(hw);
2381
2382                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2383                         PMD_INIT_LOG(INFO,
2384                                 "lsc won't enable because of no intr multiplex");
2385         } else {
2386                 ret = i40e_aq_set_phy_int_mask(hw,
2387                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2388                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2389                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2390                 if (ret != I40E_SUCCESS)
2391                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2392
2393                 /* Call get_link_info aq commond to enable/disable LSE */
2394                 i40e_dev_link_update(dev, 0);
2395         }
2396
2397         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2398                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2399                                   i40e_dev_alarm_handler, dev);
2400         } else {
2401                 /* enable uio intr after callback register */
2402                 rte_intr_enable(intr_handle);
2403         }
2404
2405         i40e_filter_restore(pf);
2406
2407         if (pf->tm_conf.root && !pf->tm_conf.committed)
2408                 PMD_DRV_LOG(WARNING,
2409                             "please call hierarchy_commit() "
2410                             "before starting the port");
2411
2412         return I40E_SUCCESS;
2413
2414 err_up:
2415         i40e_dev_switch_queues(pf, FALSE);
2416         i40e_dev_clear_queues(dev);
2417
2418         return ret;
2419 }
2420
2421 static void
2422 i40e_dev_stop(struct rte_eth_dev *dev)
2423 {
2424         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2425         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2426         struct i40e_vsi *main_vsi = pf->main_vsi;
2427         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2428         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2429         int i;
2430
2431         if (hw->adapter_stopped == 1)
2432                 return;
2433
2434         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2435                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2436                 rte_intr_enable(intr_handle);
2437         }
2438
2439         /* Disable all queues */
2440         i40e_dev_switch_queues(pf, FALSE);
2441
2442         /* un-map queues with interrupt registers */
2443         i40e_vsi_disable_queues_intr(main_vsi);
2444         i40e_vsi_queues_unbind_intr(main_vsi);
2445
2446         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2447                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2448                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2449         }
2450
2451         if (pf->fdir.fdir_vsi) {
2452                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2453                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2454         }
2455         /* Clear all queues and release memory */
2456         i40e_dev_clear_queues(dev);
2457
2458         /* Set link down */
2459         i40e_dev_set_link_down(dev);
2460
2461         if (!rte_intr_allow_others(intr_handle))
2462                 /* resume to the default handler */
2463                 rte_intr_callback_register(intr_handle,
2464                                            i40e_dev_interrupt_handler,
2465                                            (void *)dev);
2466
2467         /* Clean datapath event and queue/vec mapping */
2468         rte_intr_efd_disable(intr_handle);
2469         if (intr_handle->intr_vec) {
2470                 rte_free(intr_handle->intr_vec);
2471                 intr_handle->intr_vec = NULL;
2472         }
2473
2474         /* reset hierarchy commit */
2475         pf->tm_conf.committed = false;
2476
2477         hw->adapter_stopped = 1;
2478
2479         pf->adapter->rss_reta_updated = 0;
2480 }
2481
2482 static void
2483 i40e_dev_close(struct rte_eth_dev *dev)
2484 {
2485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2486         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2487         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2488         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2489         struct i40e_mirror_rule *p_mirror;
2490         struct i40e_filter_control_settings settings;
2491         struct rte_flow *p_flow;
2492         uint32_t reg;
2493         int i;
2494         int ret;
2495         uint8_t aq_fail = 0;
2496         int retries = 0;
2497
2498         PMD_INIT_FUNC_TRACE();
2499
2500         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2501         if (ret)
2502                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2503
2504
2505         i40e_dev_stop(dev);
2506
2507         /* Remove all mirror rules */
2508         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2509                 ret = i40e_aq_del_mirror_rule(hw,
2510                                               pf->main_vsi->veb->seid,
2511                                               p_mirror->rule_type,
2512                                               p_mirror->entries,
2513                                               p_mirror->num_entries,
2514                                               p_mirror->id);
2515                 if (ret < 0)
2516                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2517                                     "status = %d, aq_err = %d.", ret,
2518                                     hw->aq.asq_last_status);
2519
2520                 /* remove mirror software resource anyway */
2521                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2522                 rte_free(p_mirror);
2523                 pf->nb_mirror_rule--;
2524         }
2525
2526         i40e_dev_free_queues(dev);
2527
2528         /* Disable interrupt */
2529         i40e_pf_disable_irq0(hw);
2530         rte_intr_disable(intr_handle);
2531
2532         /*
2533          * Only legacy filter API needs the following fdir config. So when the
2534          * legacy filter API is deprecated, the following code should also be
2535          * removed.
2536          */
2537         i40e_fdir_teardown(pf);
2538
2539         /* shutdown and destroy the HMC */
2540         i40e_shutdown_lan_hmc(hw);
2541
2542         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2543                 i40e_vsi_release(pf->vmdq[i].vsi);
2544                 pf->vmdq[i].vsi = NULL;
2545         }
2546         rte_free(pf->vmdq);
2547         pf->vmdq = NULL;
2548
2549         /* release all the existing VSIs and VEBs */
2550         i40e_vsi_release(pf->main_vsi);
2551
2552         /* shutdown the adminq */
2553         i40e_aq_queue_shutdown(hw, true);
2554         i40e_shutdown_adminq(hw);
2555
2556         i40e_res_pool_destroy(&pf->qp_pool);
2557         i40e_res_pool_destroy(&pf->msix_pool);
2558
2559         /* Disable flexible payload in global configuration */
2560         if (!pf->support_multi_driver)
2561                 i40e_flex_payload_reg_set_default(hw);
2562
2563         /* force a PF reset to clean anything leftover */
2564         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2565         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2566                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2567         I40E_WRITE_FLUSH(hw);
2568
2569         dev->dev_ops = NULL;
2570         dev->rx_pkt_burst = NULL;
2571         dev->tx_pkt_burst = NULL;
2572
2573         /* Clear PXE mode */
2574         i40e_clear_pxe_mode(hw);
2575
2576         /* Unconfigure filter control */
2577         memset(&settings, 0, sizeof(settings));
2578         ret = i40e_set_filter_control(hw, &settings);
2579         if (ret)
2580                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2581                                         ret);
2582
2583         /* Disable flow control */
2584         hw->fc.requested_mode = I40E_FC_NONE;
2585         i40e_set_fc(hw, &aq_fail, TRUE);
2586
2587         /* uninitialize pf host driver */
2588         i40e_pf_host_uninit(dev);
2589
2590         do {
2591                 ret = rte_intr_callback_unregister(intr_handle,
2592                                 i40e_dev_interrupt_handler, dev);
2593                 if (ret >= 0) {
2594                         break;
2595                 } else if (ret != -EAGAIN) {
2596                         PMD_INIT_LOG(ERR,
2597                                  "intr callback unregister failed: %d",
2598                                  ret);
2599                 }
2600                 i40e_msec_delay(500);
2601         } while (retries++ < 5);
2602
2603         i40e_rm_ethtype_filter_list(pf);
2604         i40e_rm_tunnel_filter_list(pf);
2605         i40e_rm_fdir_filter_list(pf);
2606
2607         /* Remove all flows */
2608         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2609                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2610                 rte_free(p_flow);
2611         }
2612
2613         /* Remove all Traffic Manager configuration */
2614         i40e_tm_conf_uninit(dev);
2615
2616         hw->adapter_closed = 1;
2617 }
2618
2619 /*
2620  * Reset PF device only to re-initialize resources in PMD layer
2621  */
2622 static int
2623 i40e_dev_reset(struct rte_eth_dev *dev)
2624 {
2625         int ret;
2626
2627         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2628          * its VF to make them align with it. The detailed notification
2629          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2630          * To avoid unexpected behavior in VF, currently reset of PF with
2631          * SR-IOV activation is not supported. It might be supported later.
2632          */
2633         if (dev->data->sriov.active)
2634                 return -ENOTSUP;
2635
2636         ret = eth_i40e_dev_uninit(dev);
2637         if (ret)
2638                 return ret;
2639
2640         ret = eth_i40e_dev_init(dev, NULL);
2641
2642         return ret;
2643 }
2644
2645 static int
2646 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2647 {
2648         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2649         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2650         struct i40e_vsi *vsi = pf->main_vsi;
2651         int status;
2652
2653         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2654                                                      true, NULL, true);
2655         if (status != I40E_SUCCESS) {
2656                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2657                 return -EAGAIN;
2658         }
2659
2660         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2661                                                         TRUE, NULL);
2662         if (status != I40E_SUCCESS) {
2663                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2664                 /* Rollback unicast promiscuous mode */
2665                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2666                                                     false, NULL, true);
2667                 return -EAGAIN;
2668         }
2669
2670         return 0;
2671 }
2672
2673 static int
2674 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2675 {
2676         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2677         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2678         struct i40e_vsi *vsi = pf->main_vsi;
2679         int status;
2680
2681         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2682                                                      false, NULL, true);
2683         if (status != I40E_SUCCESS) {
2684                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2685                 return -EAGAIN;
2686         }
2687
2688         /* must remain in all_multicast mode */
2689         if (dev->data->all_multicast == 1)
2690                 return 0;
2691
2692         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2693                                                         false, NULL);
2694         if (status != I40E_SUCCESS) {
2695                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2696                 /* Rollback unicast promiscuous mode */
2697                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2698                                                     true, NULL, true);
2699                 return -EAGAIN;
2700         }
2701
2702         return 0;
2703 }
2704
2705 static int
2706 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2707 {
2708         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2709         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2710         struct i40e_vsi *vsi = pf->main_vsi;
2711         int ret;
2712
2713         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2714         if (ret != I40E_SUCCESS) {
2715                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2716                 return -EAGAIN;
2717         }
2718
2719         return 0;
2720 }
2721
2722 static int
2723 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2724 {
2725         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2726         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2727         struct i40e_vsi *vsi = pf->main_vsi;
2728         int ret;
2729
2730         if (dev->data->promiscuous == 1)
2731                 return 0; /* must remain in all_multicast mode */
2732
2733         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2734                                 vsi->seid, FALSE, NULL);
2735         if (ret != I40E_SUCCESS) {
2736                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2737                 return -EAGAIN;
2738         }
2739
2740         return 0;
2741 }
2742
2743 /*
2744  * Set device link up.
2745  */
2746 static int
2747 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2748 {
2749         /* re-apply link speed setting */
2750         return i40e_apply_link_speed(dev);
2751 }
2752
2753 /*
2754  * Set device link down.
2755  */
2756 static int
2757 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2758 {
2759         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2760         uint8_t abilities = 0;
2761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762
2763         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2764         return i40e_phy_conf_link(hw, abilities, speed, false);
2765 }
2766
2767 static __rte_always_inline void
2768 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2769 {
2770 /* Link status registers and values*/
2771 #define I40E_PRTMAC_LINKSTA             0x001E2420
2772 #define I40E_REG_LINK_UP                0x40000080
2773 #define I40E_PRTMAC_MACC                0x001E24E0
2774 #define I40E_REG_MACC_25GB              0x00020000
2775 #define I40E_REG_SPEED_MASK             0x38000000
2776 #define I40E_REG_SPEED_0                0x00000000
2777 #define I40E_REG_SPEED_1                0x08000000
2778 #define I40E_REG_SPEED_2                0x10000000
2779 #define I40E_REG_SPEED_3                0x18000000
2780 #define I40E_REG_SPEED_4                0x20000000
2781         uint32_t link_speed;
2782         uint32_t reg_val;
2783
2784         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2785         link_speed = reg_val & I40E_REG_SPEED_MASK;
2786         reg_val &= I40E_REG_LINK_UP;
2787         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2788
2789         if (unlikely(link->link_status == 0))
2790                 return;
2791
2792         /* Parse the link status */
2793         switch (link_speed) {
2794         case I40E_REG_SPEED_0:
2795                 link->link_speed = ETH_SPEED_NUM_100M;
2796                 break;
2797         case I40E_REG_SPEED_1:
2798                 link->link_speed = ETH_SPEED_NUM_1G;
2799                 break;
2800         case I40E_REG_SPEED_2:
2801                 if (hw->mac.type == I40E_MAC_X722)
2802                         link->link_speed = ETH_SPEED_NUM_2_5G;
2803                 else
2804                         link->link_speed = ETH_SPEED_NUM_10G;
2805                 break;
2806         case I40E_REG_SPEED_3:
2807                 if (hw->mac.type == I40E_MAC_X722) {
2808                         link->link_speed = ETH_SPEED_NUM_5G;
2809                 } else {
2810                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2811
2812                         if (reg_val & I40E_REG_MACC_25GB)
2813                                 link->link_speed = ETH_SPEED_NUM_25G;
2814                         else
2815                                 link->link_speed = ETH_SPEED_NUM_40G;
2816                 }
2817                 break;
2818         case I40E_REG_SPEED_4:
2819                 if (hw->mac.type == I40E_MAC_X722)
2820                         link->link_speed = ETH_SPEED_NUM_10G;
2821                 else
2822                         link->link_speed = ETH_SPEED_NUM_20G;
2823                 break;
2824         default:
2825                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2826                 break;
2827         }
2828 }
2829
2830 static __rte_always_inline void
2831 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2832         bool enable_lse, int wait_to_complete)
2833 {
2834 #define CHECK_INTERVAL             100  /* 100ms */
2835 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2836         uint32_t rep_cnt = MAX_REPEAT_TIME;
2837         struct i40e_link_status link_status;
2838         int status;
2839
2840         memset(&link_status, 0, sizeof(link_status));
2841
2842         do {
2843                 memset(&link_status, 0, sizeof(link_status));
2844
2845                 /* Get link status information from hardware */
2846                 status = i40e_aq_get_link_info(hw, enable_lse,
2847                                                 &link_status, NULL);
2848                 if (unlikely(status != I40E_SUCCESS)) {
2849                         link->link_speed = ETH_SPEED_NUM_NONE;
2850                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2851                         PMD_DRV_LOG(ERR, "Failed to get link info");
2852                         return;
2853                 }
2854
2855                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2856                 if (!wait_to_complete || link->link_status)
2857                         break;
2858
2859                 rte_delay_ms(CHECK_INTERVAL);
2860         } while (--rep_cnt);
2861
2862         /* Parse the link status */
2863         switch (link_status.link_speed) {
2864         case I40E_LINK_SPEED_100MB:
2865                 link->link_speed = ETH_SPEED_NUM_100M;
2866                 break;
2867         case I40E_LINK_SPEED_1GB:
2868                 link->link_speed = ETH_SPEED_NUM_1G;
2869                 break;
2870         case I40E_LINK_SPEED_10GB:
2871                 link->link_speed = ETH_SPEED_NUM_10G;
2872                 break;
2873         case I40E_LINK_SPEED_20GB:
2874                 link->link_speed = ETH_SPEED_NUM_20G;
2875                 break;
2876         case I40E_LINK_SPEED_25GB:
2877                 link->link_speed = ETH_SPEED_NUM_25G;
2878                 break;
2879         case I40E_LINK_SPEED_40GB:
2880                 link->link_speed = ETH_SPEED_NUM_40G;
2881                 break;
2882         default:
2883                 link->link_speed = ETH_SPEED_NUM_NONE;
2884                 break;
2885         }
2886 }
2887
2888 int
2889 i40e_dev_link_update(struct rte_eth_dev *dev,
2890                      int wait_to_complete)
2891 {
2892         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2893         struct rte_eth_link link;
2894         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2895         int ret;
2896
2897         memset(&link, 0, sizeof(link));
2898
2899         /* i40e uses full duplex only */
2900         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2901         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2902                         ETH_LINK_SPEED_FIXED);
2903
2904         if (!wait_to_complete && !enable_lse)
2905                 update_link_reg(hw, &link);
2906         else
2907                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2908
2909         ret = rte_eth_linkstatus_set(dev, &link);
2910         i40e_notify_all_vfs_link_status(dev);
2911
2912         return ret;
2913 }
2914
2915 /* Get all the statistics of a VSI */
2916 void
2917 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2918 {
2919         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2920         struct i40e_eth_stats *nes = &vsi->eth_stats;
2921         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2922         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2923
2924         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2925                             vsi->offset_loaded, &oes->rx_bytes,
2926                             &nes->rx_bytes);
2927         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2928                             vsi->offset_loaded, &oes->rx_unicast,
2929                             &nes->rx_unicast);
2930         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2931                             vsi->offset_loaded, &oes->rx_multicast,
2932                             &nes->rx_multicast);
2933         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2934                             vsi->offset_loaded, &oes->rx_broadcast,
2935                             &nes->rx_broadcast);
2936         /* exclude CRC bytes */
2937         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2938                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2939
2940         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2941                             &oes->rx_discards, &nes->rx_discards);
2942         /* GLV_REPC not supported */
2943         /* GLV_RMPC not supported */
2944         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2945                             &oes->rx_unknown_protocol,
2946                             &nes->rx_unknown_protocol);
2947         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2948                             vsi->offset_loaded, &oes->tx_bytes,
2949                             &nes->tx_bytes);
2950         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2951                             vsi->offset_loaded, &oes->tx_unicast,
2952                             &nes->tx_unicast);
2953         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2954                             vsi->offset_loaded, &oes->tx_multicast,
2955                             &nes->tx_multicast);
2956         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2957                             vsi->offset_loaded,  &oes->tx_broadcast,
2958                             &nes->tx_broadcast);
2959         /* GLV_TDPC not supported */
2960         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2961                             &oes->tx_errors, &nes->tx_errors);
2962         vsi->offset_loaded = true;
2963
2964         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2965                     vsi->vsi_id);
2966         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2967         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2968         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2969         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2970         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2971         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2972                     nes->rx_unknown_protocol);
2973         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2974         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2975         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2976         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2977         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2978         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2979         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2980                     vsi->vsi_id);
2981 }
2982
2983 static void
2984 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2985 {
2986         unsigned int i;
2987         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2988         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2989
2990         /* Get rx/tx bytes of internal transfer packets */
2991         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2992                         I40E_GLV_GORCL(hw->port),
2993                         pf->offset_loaded,
2994                         &pf->internal_stats_offset.rx_bytes,
2995                         &pf->internal_stats.rx_bytes);
2996
2997         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2998                         I40E_GLV_GOTCL(hw->port),
2999                         pf->offset_loaded,
3000                         &pf->internal_stats_offset.tx_bytes,
3001                         &pf->internal_stats.tx_bytes);
3002         /* Get total internal rx packet count */
3003         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3004                             I40E_GLV_UPRCL(hw->port),
3005                             pf->offset_loaded,
3006                             &pf->internal_stats_offset.rx_unicast,
3007                             &pf->internal_stats.rx_unicast);
3008         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3009                             I40E_GLV_MPRCL(hw->port),
3010                             pf->offset_loaded,
3011                             &pf->internal_stats_offset.rx_multicast,
3012                             &pf->internal_stats.rx_multicast);
3013         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3014                             I40E_GLV_BPRCL(hw->port),
3015                             pf->offset_loaded,
3016                             &pf->internal_stats_offset.rx_broadcast,
3017                             &pf->internal_stats.rx_broadcast);
3018         /* Get total internal tx packet count */
3019         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3020                             I40E_GLV_UPTCL(hw->port),
3021                             pf->offset_loaded,
3022                             &pf->internal_stats_offset.tx_unicast,
3023                             &pf->internal_stats.tx_unicast);
3024         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3025                             I40E_GLV_MPTCL(hw->port),
3026                             pf->offset_loaded,
3027                             &pf->internal_stats_offset.tx_multicast,
3028                             &pf->internal_stats.tx_multicast);
3029         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3030                             I40E_GLV_BPTCL(hw->port),
3031                             pf->offset_loaded,
3032                             &pf->internal_stats_offset.tx_broadcast,
3033                             &pf->internal_stats.tx_broadcast);
3034
3035         /* exclude CRC size */
3036         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3037                 pf->internal_stats.rx_multicast +
3038                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3039
3040         /* Get statistics of struct i40e_eth_stats */
3041         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3042                             I40E_GLPRT_GORCL(hw->port),
3043                             pf->offset_loaded, &os->eth.rx_bytes,
3044                             &ns->eth.rx_bytes);
3045         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3046                             I40E_GLPRT_UPRCL(hw->port),
3047                             pf->offset_loaded, &os->eth.rx_unicast,
3048                             &ns->eth.rx_unicast);
3049         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3050                             I40E_GLPRT_MPRCL(hw->port),
3051                             pf->offset_loaded, &os->eth.rx_multicast,
3052                             &ns->eth.rx_multicast);
3053         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3054                             I40E_GLPRT_BPRCL(hw->port),
3055                             pf->offset_loaded, &os->eth.rx_broadcast,
3056                             &ns->eth.rx_broadcast);
3057         /* Workaround: CRC size should not be included in byte statistics,
3058          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3059          * packet.
3060          */
3061         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3062                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3063
3064         /* exclude internal rx bytes
3065          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3066          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3067          * value.
3068          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3069          */
3070         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3071                 ns->eth.rx_bytes = 0;
3072         else
3073                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3074
3075         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3076                 ns->eth.rx_unicast = 0;
3077         else
3078                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3079
3080         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3081                 ns->eth.rx_multicast = 0;
3082         else
3083                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3084
3085         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3086                 ns->eth.rx_broadcast = 0;
3087         else
3088                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3089
3090         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3091                             pf->offset_loaded, &os->eth.rx_discards,
3092                             &ns->eth.rx_discards);
3093         /* GLPRT_REPC not supported */
3094         /* GLPRT_RMPC not supported */
3095         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3096                             pf->offset_loaded,
3097                             &os->eth.rx_unknown_protocol,
3098                             &ns->eth.rx_unknown_protocol);
3099         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3100                             I40E_GLPRT_GOTCL(hw->port),
3101                             pf->offset_loaded, &os->eth.tx_bytes,
3102                             &ns->eth.tx_bytes);
3103         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3104                             I40E_GLPRT_UPTCL(hw->port),
3105                             pf->offset_loaded, &os->eth.tx_unicast,
3106                             &ns->eth.tx_unicast);
3107         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3108                             I40E_GLPRT_MPTCL(hw->port),
3109                             pf->offset_loaded, &os->eth.tx_multicast,
3110                             &ns->eth.tx_multicast);
3111         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3112                             I40E_GLPRT_BPTCL(hw->port),
3113                             pf->offset_loaded, &os->eth.tx_broadcast,
3114                             &ns->eth.tx_broadcast);
3115         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3116                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3117
3118         /* exclude internal tx bytes
3119          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3120          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3121          * value.
3122          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3123          */
3124         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3125                 ns->eth.tx_bytes = 0;
3126         else
3127                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3128
3129         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3130                 ns->eth.tx_unicast = 0;
3131         else
3132                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3133
3134         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3135                 ns->eth.tx_multicast = 0;
3136         else
3137                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3138
3139         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3140                 ns->eth.tx_broadcast = 0;
3141         else
3142                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3143
3144         /* GLPRT_TEPC not supported */
3145
3146         /* additional port specific stats */
3147         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3148                             pf->offset_loaded, &os->tx_dropped_link_down,
3149                             &ns->tx_dropped_link_down);
3150         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3151                             pf->offset_loaded, &os->crc_errors,
3152                             &ns->crc_errors);
3153         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3154                             pf->offset_loaded, &os->illegal_bytes,
3155                             &ns->illegal_bytes);
3156         /* GLPRT_ERRBC not supported */
3157         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3158                             pf->offset_loaded, &os->mac_local_faults,
3159                             &ns->mac_local_faults);
3160         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3161                             pf->offset_loaded, &os->mac_remote_faults,
3162                             &ns->mac_remote_faults);
3163         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3164                             pf->offset_loaded, &os->rx_length_errors,
3165                             &ns->rx_length_errors);
3166         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3167                             pf->offset_loaded, &os->link_xon_rx,
3168                             &ns->link_xon_rx);
3169         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3170                             pf->offset_loaded, &os->link_xoff_rx,
3171                             &ns->link_xoff_rx);
3172         for (i = 0; i < 8; i++) {
3173                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3174                                     pf->offset_loaded,
3175                                     &os->priority_xon_rx[i],
3176                                     &ns->priority_xon_rx[i]);
3177                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3178                                     pf->offset_loaded,
3179                                     &os->priority_xoff_rx[i],
3180                                     &ns->priority_xoff_rx[i]);
3181         }
3182         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3183                             pf->offset_loaded, &os->link_xon_tx,
3184                             &ns->link_xon_tx);
3185         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3186                             pf->offset_loaded, &os->link_xoff_tx,
3187                             &ns->link_xoff_tx);
3188         for (i = 0; i < 8; i++) {
3189                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3190                                     pf->offset_loaded,
3191                                     &os->priority_xon_tx[i],
3192                                     &ns->priority_xon_tx[i]);
3193                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3194                                     pf->offset_loaded,
3195                                     &os->priority_xoff_tx[i],
3196                                     &ns->priority_xoff_tx[i]);
3197                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3198                                     pf->offset_loaded,
3199                                     &os->priority_xon_2_xoff[i],
3200                                     &ns->priority_xon_2_xoff[i]);
3201         }
3202         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3203                             I40E_GLPRT_PRC64L(hw->port),
3204                             pf->offset_loaded, &os->rx_size_64,
3205                             &ns->rx_size_64);
3206         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3207                             I40E_GLPRT_PRC127L(hw->port),
3208                             pf->offset_loaded, &os->rx_size_127,
3209                             &ns->rx_size_127);
3210         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3211                             I40E_GLPRT_PRC255L(hw->port),
3212                             pf->offset_loaded, &os->rx_size_255,
3213                             &ns->rx_size_255);
3214         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3215                             I40E_GLPRT_PRC511L(hw->port),
3216                             pf->offset_loaded, &os->rx_size_511,
3217                             &ns->rx_size_511);
3218         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3219                             I40E_GLPRT_PRC1023L(hw->port),
3220                             pf->offset_loaded, &os->rx_size_1023,
3221                             &ns->rx_size_1023);
3222         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3223                             I40E_GLPRT_PRC1522L(hw->port),
3224                             pf->offset_loaded, &os->rx_size_1522,
3225                             &ns->rx_size_1522);
3226         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3227                             I40E_GLPRT_PRC9522L(hw->port),
3228                             pf->offset_loaded, &os->rx_size_big,
3229                             &ns->rx_size_big);
3230         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3231                             pf->offset_loaded, &os->rx_undersize,
3232                             &ns->rx_undersize);
3233         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3234                             pf->offset_loaded, &os->rx_fragments,
3235                             &ns->rx_fragments);
3236         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3237                             pf->offset_loaded, &os->rx_oversize,
3238                             &ns->rx_oversize);
3239         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3240                             pf->offset_loaded, &os->rx_jabber,
3241                             &ns->rx_jabber);
3242         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3243                             I40E_GLPRT_PTC64L(hw->port),
3244                             pf->offset_loaded, &os->tx_size_64,
3245                             &ns->tx_size_64);
3246         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3247                             I40E_GLPRT_PTC127L(hw->port),
3248                             pf->offset_loaded, &os->tx_size_127,
3249                             &ns->tx_size_127);
3250         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3251                             I40E_GLPRT_PTC255L(hw->port),
3252                             pf->offset_loaded, &os->tx_size_255,
3253                             &ns->tx_size_255);
3254         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3255                             I40E_GLPRT_PTC511L(hw->port),
3256                             pf->offset_loaded, &os->tx_size_511,
3257                             &ns->tx_size_511);
3258         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3259                             I40E_GLPRT_PTC1023L(hw->port),
3260                             pf->offset_loaded, &os->tx_size_1023,
3261                             &ns->tx_size_1023);
3262         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3263                             I40E_GLPRT_PTC1522L(hw->port),
3264                             pf->offset_loaded, &os->tx_size_1522,
3265                             &ns->tx_size_1522);
3266         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3267                             I40E_GLPRT_PTC9522L(hw->port),
3268                             pf->offset_loaded, &os->tx_size_big,
3269                             &ns->tx_size_big);
3270         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3271                            pf->offset_loaded,
3272                            &os->fd_sb_match, &ns->fd_sb_match);
3273         /* GLPRT_MSPDC not supported */
3274         /* GLPRT_XEC not supported */
3275
3276         pf->offset_loaded = true;
3277
3278         if (pf->main_vsi)
3279                 i40e_update_vsi_stats(pf->main_vsi);
3280 }
3281
3282 /* Get all statistics of a port */
3283 static int
3284 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3285 {
3286         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3288         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3289         struct i40e_vsi *vsi;
3290         unsigned i;
3291
3292         /* call read registers - updates values, now write them to struct */
3293         i40e_read_stats_registers(pf, hw);
3294
3295         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3296                         pf->main_vsi->eth_stats.rx_multicast +
3297                         pf->main_vsi->eth_stats.rx_broadcast -
3298                         pf->main_vsi->eth_stats.rx_discards;
3299         stats->opackets = ns->eth.tx_unicast +
3300                         ns->eth.tx_multicast +
3301                         ns->eth.tx_broadcast;
3302         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3303         stats->obytes   = ns->eth.tx_bytes;
3304         stats->oerrors  = ns->eth.tx_errors +
3305                         pf->main_vsi->eth_stats.tx_errors;
3306
3307         /* Rx Errors */
3308         stats->imissed  = ns->eth.rx_discards +
3309                         pf->main_vsi->eth_stats.rx_discards;
3310         stats->ierrors  = ns->crc_errors +
3311                         ns->rx_length_errors + ns->rx_undersize +
3312                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3313
3314         if (pf->vfs) {
3315                 for (i = 0; i < pf->vf_num; i++) {
3316                         vsi = pf->vfs[i].vsi;
3317                         i40e_update_vsi_stats(vsi);
3318
3319                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3320                                         vsi->eth_stats.rx_multicast +
3321                                         vsi->eth_stats.rx_broadcast -
3322                                         vsi->eth_stats.rx_discards);
3323                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3324                         stats->oerrors  += vsi->eth_stats.tx_errors;
3325                         stats->imissed  += vsi->eth_stats.rx_discards;
3326                 }
3327         }
3328
3329         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3330         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3331         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3332         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3333         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3334         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3335         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3336                     ns->eth.rx_unknown_protocol);
3337         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3338         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3339         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3340         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3341         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3342         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3343
3344         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3345                     ns->tx_dropped_link_down);
3346         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3347         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3348                     ns->illegal_bytes);
3349         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3350         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3351                     ns->mac_local_faults);
3352         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3353                     ns->mac_remote_faults);
3354         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3355                     ns->rx_length_errors);
3356         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3357         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3358         for (i = 0; i < 8; i++) {
3359                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3360                                 i, ns->priority_xon_rx[i]);
3361                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3362                                 i, ns->priority_xoff_rx[i]);
3363         }
3364         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3365         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3366         for (i = 0; i < 8; i++) {
3367                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3368                                 i, ns->priority_xon_tx[i]);
3369                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3370                                 i, ns->priority_xoff_tx[i]);
3371                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3372                                 i, ns->priority_xon_2_xoff[i]);
3373         }
3374         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3375         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3376         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3377         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3378         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3379         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3380         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3381         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3382         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3383         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3384         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3385         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3386         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3387         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3388         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3389         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3390         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3391         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3392         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3393                         ns->mac_short_packet_dropped);
3394         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3395                     ns->checksum_error);
3396         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3397         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3398         return 0;
3399 }
3400
3401 /* Reset the statistics */
3402 static int
3403 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3404 {
3405         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3406         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3407
3408         /* Mark PF and VSI stats to update the offset, aka "reset" */
3409         pf->offset_loaded = false;
3410         if (pf->main_vsi)
3411                 pf->main_vsi->offset_loaded = false;
3412
3413         /* read the stats, reading current register values into offset */
3414         i40e_read_stats_registers(pf, hw);
3415
3416         return 0;
3417 }
3418
3419 static uint32_t
3420 i40e_xstats_calc_num(void)
3421 {
3422         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3423                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3424                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3425 }
3426
3427 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3428                                      struct rte_eth_xstat_name *xstats_names,
3429                                      __rte_unused unsigned limit)
3430 {
3431         unsigned count = 0;
3432         unsigned i, prio;
3433
3434         if (xstats_names == NULL)
3435                 return i40e_xstats_calc_num();
3436
3437         /* Note: limit checked in rte_eth_xstats_names() */
3438
3439         /* Get stats from i40e_eth_stats struct */
3440         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3441                 strlcpy(xstats_names[count].name,
3442                         rte_i40e_stats_strings[i].name,
3443                         sizeof(xstats_names[count].name));
3444                 count++;
3445         }
3446
3447         /* Get individiual stats from i40e_hw_port struct */
3448         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3449                 strlcpy(xstats_names[count].name,
3450                         rte_i40e_hw_port_strings[i].name,
3451                         sizeof(xstats_names[count].name));
3452                 count++;
3453         }
3454
3455         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3456                 for (prio = 0; prio < 8; prio++) {
3457                         snprintf(xstats_names[count].name,
3458                                  sizeof(xstats_names[count].name),
3459                                  "rx_priority%u_%s", prio,
3460                                  rte_i40e_rxq_prio_strings[i].name);
3461                         count++;
3462                 }
3463         }
3464
3465         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3466                 for (prio = 0; prio < 8; prio++) {
3467                         snprintf(xstats_names[count].name,
3468                                  sizeof(xstats_names[count].name),
3469                                  "tx_priority%u_%s", prio,
3470                                  rte_i40e_txq_prio_strings[i].name);
3471                         count++;
3472                 }
3473         }
3474         return count;
3475 }
3476
3477 static int
3478 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3479                     unsigned n)
3480 {
3481         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3482         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3483         unsigned i, count, prio;
3484         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3485
3486         count = i40e_xstats_calc_num();
3487         if (n < count)
3488                 return count;
3489
3490         i40e_read_stats_registers(pf, hw);
3491
3492         if (xstats == NULL)
3493                 return 0;
3494
3495         count = 0;
3496
3497         /* Get stats from i40e_eth_stats struct */
3498         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3499                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3500                         rte_i40e_stats_strings[i].offset);
3501                 xstats[count].id = count;
3502                 count++;
3503         }
3504
3505         /* Get individiual stats from i40e_hw_port struct */
3506         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3507                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3508                         rte_i40e_hw_port_strings[i].offset);
3509                 xstats[count].id = count;
3510                 count++;
3511         }
3512
3513         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3514                 for (prio = 0; prio < 8; prio++) {
3515                         xstats[count].value =
3516                                 *(uint64_t *)(((char *)hw_stats) +
3517                                 rte_i40e_rxq_prio_strings[i].offset +
3518                                 (sizeof(uint64_t) * prio));
3519                         xstats[count].id = count;
3520                         count++;
3521                 }
3522         }
3523
3524         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3525                 for (prio = 0; prio < 8; prio++) {
3526                         xstats[count].value =
3527                                 *(uint64_t *)(((char *)hw_stats) +
3528                                 rte_i40e_txq_prio_strings[i].offset +
3529                                 (sizeof(uint64_t) * prio));
3530                         xstats[count].id = count;
3531                         count++;
3532                 }
3533         }
3534
3535         return count;
3536 }
3537
3538 static int
3539 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3540 {
3541         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3542         u32 full_ver;
3543         u8 ver, patch;
3544         u16 build;
3545         int ret;
3546
3547         full_ver = hw->nvm.oem_ver;
3548         ver = (u8)(full_ver >> 24);
3549         build = (u16)((full_ver >> 8) & 0xffff);
3550         patch = (u8)(full_ver & 0xff);
3551
3552         ret = snprintf(fw_version, fw_size,
3553                  "%d.%d%d 0x%08x %d.%d.%d",
3554                  ((hw->nvm.version >> 12) & 0xf),
3555                  ((hw->nvm.version >> 4) & 0xff),
3556                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3557                  ver, build, patch);
3558
3559         ret += 1; /* add the size of '\0' */
3560         if (fw_size < (u32)ret)
3561                 return ret;
3562         else
3563                 return 0;
3564 }
3565
3566 /*
3567  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3568  * the Rx data path does not hang if the FW LLDP is stopped.
3569  * return true if lldp need to stop
3570  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3571  */
3572 static bool
3573 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3574 {
3575         double nvm_ver;
3576         char ver_str[64] = {0};
3577         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3578
3579         i40e_fw_version_get(dev, ver_str, 64);
3580         nvm_ver = atof(ver_str);
3581         if ((hw->mac.type == I40E_MAC_X722 ||
3582              hw->mac.type == I40E_MAC_X722_VF) &&
3583              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3584                 return true;
3585         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3586                 return true;
3587
3588         return false;
3589 }
3590
3591 static int
3592 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3593 {
3594         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3595         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596         struct i40e_vsi *vsi = pf->main_vsi;
3597         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3598
3599         dev_info->max_rx_queues = vsi->nb_qps;
3600         dev_info->max_tx_queues = vsi->nb_qps;
3601         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3602         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3603         dev_info->max_mac_addrs = vsi->max_macaddrs;
3604         dev_info->max_vfs = pci_dev->max_vfs;
3605         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3606         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3607         dev_info->rx_queue_offload_capa = 0;
3608         dev_info->rx_offload_capa =
3609                 DEV_RX_OFFLOAD_VLAN_STRIP |
3610                 DEV_RX_OFFLOAD_QINQ_STRIP |
3611                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3612                 DEV_RX_OFFLOAD_UDP_CKSUM |
3613                 DEV_RX_OFFLOAD_TCP_CKSUM |
3614                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3615                 DEV_RX_OFFLOAD_KEEP_CRC |
3616                 DEV_RX_OFFLOAD_SCATTER |
3617                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3618                 DEV_RX_OFFLOAD_VLAN_FILTER |
3619                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3620                 DEV_RX_OFFLOAD_RSS_HASH;
3621
3622         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3623         dev_info->tx_offload_capa =
3624                 DEV_TX_OFFLOAD_VLAN_INSERT |
3625                 DEV_TX_OFFLOAD_QINQ_INSERT |
3626                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3627                 DEV_TX_OFFLOAD_UDP_CKSUM |
3628                 DEV_TX_OFFLOAD_TCP_CKSUM |
3629                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3630                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3631                 DEV_TX_OFFLOAD_TCP_TSO |
3632                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3633                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3634                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3635                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3636                 DEV_TX_OFFLOAD_MULTI_SEGS |
3637                 dev_info->tx_queue_offload_capa;
3638         dev_info->dev_capa =
3639                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3640                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3641
3642         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3643                                                 sizeof(uint32_t);
3644         dev_info->reta_size = pf->hash_lut_size;
3645         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3646
3647         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3648                 .rx_thresh = {
3649                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3650                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3651                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3652                 },
3653                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3654                 .rx_drop_en = 0,
3655                 .offloads = 0,
3656         };
3657
3658         dev_info->default_txconf = (struct rte_eth_txconf) {
3659                 .tx_thresh = {
3660                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3661                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3662                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3663                 },
3664                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3665                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3666                 .offloads = 0,
3667         };
3668
3669         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3670                 .nb_max = I40E_MAX_RING_DESC,
3671                 .nb_min = I40E_MIN_RING_DESC,
3672                 .nb_align = I40E_ALIGN_RING_DESC,
3673         };
3674
3675         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3676                 .nb_max = I40E_MAX_RING_DESC,
3677                 .nb_min = I40E_MIN_RING_DESC,
3678                 .nb_align = I40E_ALIGN_RING_DESC,
3679                 .nb_seg_max = I40E_TX_MAX_SEG,
3680                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3681         };
3682
3683         if (pf->flags & I40E_FLAG_VMDQ) {
3684                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3685                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3686                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3687                                                 pf->max_nb_vmdq_vsi;
3688                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3689                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3690                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3691         }
3692
3693         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3694                 /* For XL710 */
3695                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3696                 dev_info->default_rxportconf.nb_queues = 2;
3697                 dev_info->default_txportconf.nb_queues = 2;
3698                 if (dev->data->nb_rx_queues == 1)
3699                         dev_info->default_rxportconf.ring_size = 2048;
3700                 else
3701                         dev_info->default_rxportconf.ring_size = 1024;
3702                 if (dev->data->nb_tx_queues == 1)
3703                         dev_info->default_txportconf.ring_size = 1024;
3704                 else
3705                         dev_info->default_txportconf.ring_size = 512;
3706
3707         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3708                 /* For XXV710 */
3709                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3710                 dev_info->default_rxportconf.nb_queues = 1;
3711                 dev_info->default_txportconf.nb_queues = 1;
3712                 dev_info->default_rxportconf.ring_size = 256;
3713                 dev_info->default_txportconf.ring_size = 256;
3714         } else {
3715                 /* For X710 */
3716                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3717                 dev_info->default_rxportconf.nb_queues = 1;
3718                 dev_info->default_txportconf.nb_queues = 1;
3719                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3720                         dev_info->default_rxportconf.ring_size = 512;
3721                         dev_info->default_txportconf.ring_size = 256;
3722                 } else {
3723                         dev_info->default_rxportconf.ring_size = 256;
3724                         dev_info->default_txportconf.ring_size = 256;
3725                 }
3726         }
3727         dev_info->default_rxportconf.burst_size = 32;
3728         dev_info->default_txportconf.burst_size = 32;
3729
3730         return 0;
3731 }
3732
3733 static int
3734 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3735 {
3736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3737         struct i40e_vsi *vsi = pf->main_vsi;
3738         PMD_INIT_FUNC_TRACE();
3739
3740         if (on)
3741                 return i40e_vsi_add_vlan(vsi, vlan_id);
3742         else
3743                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3744 }
3745
3746 static int
3747 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3748                                 enum rte_vlan_type vlan_type,
3749                                 uint16_t tpid, int qinq)
3750 {
3751         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3752         uint64_t reg_r = 0;
3753         uint64_t reg_w = 0;
3754         uint16_t reg_id = 3;
3755         int ret;
3756
3757         if (qinq) {
3758                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3759                         reg_id = 2;
3760         }
3761
3762         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3763                                           &reg_r, NULL);
3764         if (ret != I40E_SUCCESS) {
3765                 PMD_DRV_LOG(ERR,
3766                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3767                            reg_id);
3768                 return -EIO;
3769         }
3770         PMD_DRV_LOG(DEBUG,
3771                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3772                     reg_id, reg_r);
3773
3774         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3775         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3776         if (reg_r == reg_w) {
3777                 PMD_DRV_LOG(DEBUG, "No need to write");
3778                 return 0;
3779         }
3780
3781         ret = i40e_aq_debug_write_global_register(hw,
3782                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3783                                            reg_w, NULL);
3784         if (ret != I40E_SUCCESS) {
3785                 PMD_DRV_LOG(ERR,
3786                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3787                             reg_id);
3788                 return -EIO;
3789         }
3790         PMD_DRV_LOG(DEBUG,
3791                     "Global register 0x%08x is changed with value 0x%08x",
3792                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3793
3794         return 0;
3795 }
3796
3797 static int
3798 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3799                    enum rte_vlan_type vlan_type,
3800                    uint16_t tpid)
3801 {
3802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3803         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3804         int qinq = dev->data->dev_conf.rxmode.offloads &
3805                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3806         int ret = 0;
3807
3808         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3809              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3810             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3811                 PMD_DRV_LOG(ERR,
3812                             "Unsupported vlan type.");
3813                 return -EINVAL;
3814         }
3815
3816         if (pf->support_multi_driver) {
3817                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3818                 return -ENOTSUP;
3819         }
3820
3821         /* 802.1ad frames ability is added in NVM API 1.7*/
3822         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3823                 if (qinq) {
3824                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3825                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3826                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3827                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3828                 } else {
3829                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3830                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3831                 }
3832                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3833                 if (ret != I40E_SUCCESS) {
3834                         PMD_DRV_LOG(ERR,
3835                                     "Set switch config failed aq_err: %d",
3836                                     hw->aq.asq_last_status);
3837                         ret = -EIO;
3838                 }
3839         } else
3840                 /* If NVM API < 1.7, keep the register setting */
3841                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3842                                                       tpid, qinq);
3843
3844         return ret;
3845 }
3846
3847 static int
3848 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3849 {
3850         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3851         struct i40e_vsi *vsi = pf->main_vsi;
3852         struct rte_eth_rxmode *rxmode;
3853
3854         if (mask & ETH_QINQ_STRIP_MASK) {
3855                 PMD_DRV_LOG(ERR, "Strip qinq is not supported.");
3856                 return -ENOTSUP;
3857         }
3858
3859         rxmode = &dev->data->dev_conf.rxmode;
3860         if (mask & ETH_VLAN_FILTER_MASK) {
3861                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3862                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3863                 else
3864                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3865         }
3866
3867         if (mask & ETH_VLAN_STRIP_MASK) {
3868                 /* Enable or disable VLAN stripping */
3869                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3870                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3871                 else
3872                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3873         }
3874
3875         if (mask & ETH_VLAN_EXTEND_MASK) {
3876                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3877                         i40e_vsi_config_double_vlan(vsi, TRUE);
3878                         /* Set global registers with default ethertype. */
3879                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3880                                            RTE_ETHER_TYPE_VLAN);
3881                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3882                                            RTE_ETHER_TYPE_VLAN);
3883                 }
3884                 else
3885                         i40e_vsi_config_double_vlan(vsi, FALSE);
3886         }
3887
3888         return 0;
3889 }
3890
3891 static void
3892 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3893                           __rte_unused uint16_t queue,
3894                           __rte_unused int on)
3895 {
3896         PMD_INIT_FUNC_TRACE();
3897 }
3898
3899 static int
3900 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3901 {
3902         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3903         struct i40e_vsi *vsi = pf->main_vsi;
3904         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3905         struct i40e_vsi_vlan_pvid_info info;
3906
3907         memset(&info, 0, sizeof(info));
3908         info.on = on;
3909         if (info.on)
3910                 info.config.pvid = pvid;
3911         else {
3912                 info.config.reject.tagged =
3913                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3914                 info.config.reject.untagged =
3915                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3916         }
3917
3918         return i40e_vsi_vlan_pvid_set(vsi, &info);
3919 }
3920
3921 static int
3922 i40e_dev_led_on(struct rte_eth_dev *dev)
3923 {
3924         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3925         uint32_t mode = i40e_led_get(hw);
3926
3927         if (mode == 0)
3928                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3929
3930         return 0;
3931 }
3932
3933 static int
3934 i40e_dev_led_off(struct rte_eth_dev *dev)
3935 {
3936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3937         uint32_t mode = i40e_led_get(hw);
3938
3939         if (mode != 0)
3940                 i40e_led_set(hw, 0, false);
3941
3942         return 0;
3943 }
3944
3945 static int
3946 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3947 {
3948         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3949         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3950
3951         fc_conf->pause_time = pf->fc_conf.pause_time;
3952
3953         /* read out from register, in case they are modified by other port */
3954         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3955                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3956         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3957                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3958
3959         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3960         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3961
3962          /* Return current mode according to actual setting*/
3963         switch (hw->fc.current_mode) {
3964         case I40E_FC_FULL:
3965                 fc_conf->mode = RTE_FC_FULL;
3966                 break;
3967         case I40E_FC_TX_PAUSE:
3968                 fc_conf->mode = RTE_FC_TX_PAUSE;
3969                 break;
3970         case I40E_FC_RX_PAUSE:
3971                 fc_conf->mode = RTE_FC_RX_PAUSE;
3972                 break;
3973         case I40E_FC_NONE:
3974         default:
3975                 fc_conf->mode = RTE_FC_NONE;
3976         };
3977
3978         return 0;
3979 }
3980
3981 static int
3982 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3983 {
3984         uint32_t mflcn_reg, fctrl_reg, reg;
3985         uint32_t max_high_water;
3986         uint8_t i, aq_failure;
3987         int err;
3988         struct i40e_hw *hw;
3989         struct i40e_pf *pf;
3990         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3991                 [RTE_FC_NONE] = I40E_FC_NONE,
3992                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3993                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3994                 [RTE_FC_FULL] = I40E_FC_FULL
3995         };
3996
3997         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3998
3999         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4000         if ((fc_conf->high_water > max_high_water) ||
4001                         (fc_conf->high_water < fc_conf->low_water)) {
4002                 PMD_INIT_LOG(ERR,
4003                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4004                         max_high_water);
4005                 return -EINVAL;
4006         }
4007
4008         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4009         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4010         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4011
4012         pf->fc_conf.pause_time = fc_conf->pause_time;
4013         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4014         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4015
4016         PMD_INIT_FUNC_TRACE();
4017
4018         /* All the link flow control related enable/disable register
4019          * configuration is handle by the F/W
4020          */
4021         err = i40e_set_fc(hw, &aq_failure, true);
4022         if (err < 0)
4023                 return -ENOSYS;
4024
4025         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4026                 /* Configure flow control refresh threshold,
4027                  * the value for stat_tx_pause_refresh_timer[8]
4028                  * is used for global pause operation.
4029                  */
4030
4031                 I40E_WRITE_REG(hw,
4032                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4033                                pf->fc_conf.pause_time);
4034
4035                 /* configure the timer value included in transmitted pause
4036                  * frame,
4037                  * the value for stat_tx_pause_quanta[8] is used for global
4038                  * pause operation
4039                  */
4040                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4041                                pf->fc_conf.pause_time);
4042
4043                 fctrl_reg = I40E_READ_REG(hw,
4044                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4045
4046                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4047                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4048                 else
4049                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4050
4051                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4052                                fctrl_reg);
4053         } else {
4054                 /* Configure pause time (2 TCs per register) */
4055                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4056                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4057                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4058
4059                 /* Configure flow control refresh threshold value */
4060                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4061                                pf->fc_conf.pause_time / 2);
4062
4063                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4064
4065                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4066                  *depending on configuration
4067                  */
4068                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4069                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4070                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4071                 } else {
4072                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4073                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4074                 }
4075
4076                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4077         }
4078
4079         if (!pf->support_multi_driver) {
4080                 /* config water marker both based on the packets and bytes */
4081                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4082                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4083                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4084                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4085                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4086                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4087                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4088                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4089                                   << I40E_KILOSHIFT);
4090                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4091                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4092                                    << I40E_KILOSHIFT);
4093         } else {
4094                 PMD_DRV_LOG(ERR,
4095                             "Water marker configuration is not supported.");
4096         }
4097
4098         I40E_WRITE_FLUSH(hw);
4099
4100         return 0;
4101 }
4102
4103 static int
4104 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4105                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4106 {
4107         PMD_INIT_FUNC_TRACE();
4108
4109         return -ENOSYS;
4110 }
4111
4112 /* Add a MAC address, and update filters */
4113 static int
4114 i40e_macaddr_add(struct rte_eth_dev *dev,
4115                  struct rte_ether_addr *mac_addr,
4116                  __rte_unused uint32_t index,
4117                  uint32_t pool)
4118 {
4119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4120         struct i40e_mac_filter_info mac_filter;
4121         struct i40e_vsi *vsi;
4122         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4123         int ret;
4124
4125         /* If VMDQ not enabled or configured, return */
4126         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4127                           !pf->nb_cfg_vmdq_vsi)) {
4128                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4129                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4130                         pool);
4131                 return -ENOTSUP;
4132         }
4133
4134         if (pool > pf->nb_cfg_vmdq_vsi) {
4135                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4136                                 pool, pf->nb_cfg_vmdq_vsi);
4137                 return -EINVAL;
4138         }
4139
4140         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4141         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4142                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4143         else
4144                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4145
4146         if (pool == 0)
4147                 vsi = pf->main_vsi;
4148         else
4149                 vsi = pf->vmdq[pool - 1].vsi;
4150
4151         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4152         if (ret != I40E_SUCCESS) {
4153                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4154                 return -ENODEV;
4155         }
4156         return 0;
4157 }
4158
4159 /* Remove a MAC address, and update filters */
4160 static void
4161 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4162 {
4163         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4164         struct i40e_vsi *vsi;
4165         struct rte_eth_dev_data *data = dev->data;
4166         struct rte_ether_addr *macaddr;
4167         int ret;
4168         uint32_t i;
4169         uint64_t pool_sel;
4170
4171         macaddr = &(data->mac_addrs[index]);
4172
4173         pool_sel = dev->data->mac_pool_sel[index];
4174
4175         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4176                 if (pool_sel & (1ULL << i)) {
4177                         if (i == 0)
4178                                 vsi = pf->main_vsi;
4179                         else {
4180                                 /* No VMDQ pool enabled or configured */
4181                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4182                                         (i > pf->nb_cfg_vmdq_vsi)) {
4183                                         PMD_DRV_LOG(ERR,
4184                                                 "No VMDQ pool enabled/configured");
4185                                         return;
4186                                 }
4187                                 vsi = pf->vmdq[i - 1].vsi;
4188                         }
4189                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4190
4191                         if (ret) {
4192                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4193                                 return;
4194                         }
4195                 }
4196         }
4197 }
4198
4199 /* Set perfect match or hash match of MAC and VLAN for a VF */
4200 static int
4201 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4202                  struct rte_eth_mac_filter *filter,
4203                  bool add)
4204 {
4205         struct i40e_hw *hw;
4206         struct i40e_mac_filter_info mac_filter;
4207         struct rte_ether_addr old_mac;
4208         struct rte_ether_addr *new_mac;
4209         struct i40e_pf_vf *vf = NULL;
4210         uint16_t vf_id;
4211         int ret;
4212
4213         if (pf == NULL) {
4214                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4215                 return -EINVAL;
4216         }
4217         hw = I40E_PF_TO_HW(pf);
4218
4219         if (filter == NULL) {
4220                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4221                 return -EINVAL;
4222         }
4223
4224         new_mac = &filter->mac_addr;
4225
4226         if (rte_is_zero_ether_addr(new_mac)) {
4227                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4228                 return -EINVAL;
4229         }
4230
4231         vf_id = filter->dst_id;
4232
4233         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4234                 PMD_DRV_LOG(ERR, "Invalid argument.");
4235                 return -EINVAL;
4236         }
4237         vf = &pf->vfs[vf_id];
4238
4239         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4240                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4241                 return -EINVAL;
4242         }
4243
4244         if (add) {
4245                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4246                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4247                                 RTE_ETHER_ADDR_LEN);
4248                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4249                                  RTE_ETHER_ADDR_LEN);
4250
4251                 mac_filter.filter_type = filter->filter_type;
4252                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4253                 if (ret != I40E_SUCCESS) {
4254                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4255                         return -1;
4256                 }
4257                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4258         } else {
4259                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4260                                 RTE_ETHER_ADDR_LEN);
4261                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4262                 if (ret != I40E_SUCCESS) {
4263                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4264                         return -1;
4265                 }
4266
4267                 /* Clear device address as it has been removed */
4268                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4269                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4270         }
4271
4272         return 0;
4273 }
4274
4275 /* MAC filter handle */
4276 static int
4277 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4278                 void *arg)
4279 {
4280         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4281         struct rte_eth_mac_filter *filter;
4282         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4283         int ret = I40E_NOT_SUPPORTED;
4284
4285         filter = (struct rte_eth_mac_filter *)(arg);
4286
4287         switch (filter_op) {
4288         case RTE_ETH_FILTER_NOP:
4289                 ret = I40E_SUCCESS;
4290                 break;
4291         case RTE_ETH_FILTER_ADD:
4292                 i40e_pf_disable_irq0(hw);
4293                 if (filter->is_vf)
4294                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4295                 i40e_pf_enable_irq0(hw);
4296                 break;
4297         case RTE_ETH_FILTER_DELETE:
4298                 i40e_pf_disable_irq0(hw);
4299                 if (filter->is_vf)
4300                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4301                 i40e_pf_enable_irq0(hw);
4302                 break;
4303         default:
4304                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4305                 ret = I40E_ERR_PARAM;
4306                 break;
4307         }
4308
4309         return ret;
4310 }
4311
4312 static int
4313 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4314 {
4315         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4316         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4317         uint32_t reg;
4318         int ret;
4319
4320         if (!lut)
4321                 return -EINVAL;
4322
4323         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4324                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4325                                           vsi->type != I40E_VSI_SRIOV,
4326                                           lut, lut_size);
4327                 if (ret) {
4328                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4329                         return ret;
4330                 }
4331         } else {
4332                 uint32_t *lut_dw = (uint32_t *)lut;
4333                 uint16_t i, lut_size_dw = lut_size / 4;
4334
4335                 if (vsi->type == I40E_VSI_SRIOV) {
4336                         for (i = 0; i <= lut_size_dw; i++) {
4337                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4338                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4339                         }
4340                 } else {
4341                         for (i = 0; i < lut_size_dw; i++)
4342                                 lut_dw[i] = I40E_READ_REG(hw,
4343                                                           I40E_PFQF_HLUT(i));
4344                 }
4345         }
4346
4347         return 0;
4348 }
4349
4350 int
4351 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4352 {
4353         struct i40e_pf *pf;
4354         struct i40e_hw *hw;
4355         int ret;
4356
4357         if (!vsi || !lut)
4358                 return -EINVAL;
4359
4360         pf = I40E_VSI_TO_PF(vsi);
4361         hw = I40E_VSI_TO_HW(vsi);
4362
4363         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4364                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4365                                           vsi->type != I40E_VSI_SRIOV,
4366                                           lut, lut_size);
4367                 if (ret) {
4368                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4369                         return ret;
4370                 }
4371         } else {
4372                 uint32_t *lut_dw = (uint32_t *)lut;
4373                 uint16_t i, lut_size_dw = lut_size / 4;
4374
4375                 if (vsi->type == I40E_VSI_SRIOV) {
4376                         for (i = 0; i < lut_size_dw; i++)
4377                                 I40E_WRITE_REG(
4378                                         hw,
4379                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4380                                         lut_dw[i]);
4381                 } else {
4382                         for (i = 0; i < lut_size_dw; i++)
4383                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4384                                                lut_dw[i]);
4385                 }
4386                 I40E_WRITE_FLUSH(hw);
4387         }
4388
4389         return 0;
4390 }
4391
4392 static int
4393 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4394                          struct rte_eth_rss_reta_entry64 *reta_conf,
4395                          uint16_t reta_size)
4396 {
4397         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4398         uint16_t i, lut_size = pf->hash_lut_size;
4399         uint16_t idx, shift;
4400         uint8_t *lut;
4401         int ret;
4402
4403         if (reta_size != lut_size ||
4404                 reta_size > ETH_RSS_RETA_SIZE_512) {
4405                 PMD_DRV_LOG(ERR,
4406                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4407                         reta_size, lut_size);
4408                 return -EINVAL;
4409         }
4410
4411         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4412         if (!lut) {
4413                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4414                 return -ENOMEM;
4415         }
4416         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4417         if (ret)
4418                 goto out;
4419         for (i = 0; i < reta_size; i++) {
4420                 idx = i / RTE_RETA_GROUP_SIZE;
4421                 shift = i % RTE_RETA_GROUP_SIZE;
4422                 if (reta_conf[idx].mask & (1ULL << shift))
4423                         lut[i] = reta_conf[idx].reta[shift];
4424         }
4425         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4426
4427         pf->adapter->rss_reta_updated = 1;
4428
4429 out:
4430         rte_free(lut);
4431
4432         return ret;
4433 }
4434
4435 static int
4436 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4437                         struct rte_eth_rss_reta_entry64 *reta_conf,
4438                         uint16_t reta_size)
4439 {
4440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4441         uint16_t i, lut_size = pf->hash_lut_size;
4442         uint16_t idx, shift;
4443         uint8_t *lut;
4444         int ret;
4445
4446         if (reta_size != lut_size ||
4447                 reta_size > ETH_RSS_RETA_SIZE_512) {
4448                 PMD_DRV_LOG(ERR,
4449                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4450                         reta_size, lut_size);
4451                 return -EINVAL;
4452         }
4453
4454         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4455         if (!lut) {
4456                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4457                 return -ENOMEM;
4458         }
4459
4460         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4461         if (ret)
4462                 goto out;
4463         for (i = 0; i < reta_size; i++) {
4464                 idx = i / RTE_RETA_GROUP_SIZE;
4465                 shift = i % RTE_RETA_GROUP_SIZE;
4466                 if (reta_conf[idx].mask & (1ULL << shift))
4467                         reta_conf[idx].reta[shift] = lut[i];
4468         }
4469
4470 out:
4471         rte_free(lut);
4472
4473         return ret;
4474 }
4475
4476 /**
4477  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4478  * @hw:   pointer to the HW structure
4479  * @mem:  pointer to mem struct to fill out
4480  * @size: size of memory requested
4481  * @alignment: what to align the allocation to
4482  **/
4483 enum i40e_status_code
4484 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4485                         struct i40e_dma_mem *mem,
4486                         u64 size,
4487                         u32 alignment)
4488 {
4489         const struct rte_memzone *mz = NULL;
4490         char z_name[RTE_MEMZONE_NAMESIZE];
4491
4492         if (!mem)
4493                 return I40E_ERR_PARAM;
4494
4495         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4496         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4497                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4498         if (!mz)
4499                 return I40E_ERR_NO_MEMORY;
4500
4501         mem->size = size;
4502         mem->va = mz->addr;
4503         mem->pa = mz->iova;
4504         mem->zone = (const void *)mz;
4505         PMD_DRV_LOG(DEBUG,
4506                 "memzone %s allocated with physical address: %"PRIu64,
4507                 mz->name, mem->pa);
4508
4509         return I40E_SUCCESS;
4510 }
4511
4512 /**
4513  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4514  * @hw:   pointer to the HW structure
4515  * @mem:  ptr to mem struct to free
4516  **/
4517 enum i40e_status_code
4518 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4519                     struct i40e_dma_mem *mem)
4520 {
4521         if (!mem)
4522                 return I40E_ERR_PARAM;
4523
4524         PMD_DRV_LOG(DEBUG,
4525                 "memzone %s to be freed with physical address: %"PRIu64,
4526                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4527         rte_memzone_free((const struct rte_memzone *)mem->zone);
4528         mem->zone = NULL;
4529         mem->va = NULL;
4530         mem->pa = (u64)0;
4531
4532         return I40E_SUCCESS;
4533 }
4534
4535 /**
4536  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4537  * @hw:   pointer to the HW structure
4538  * @mem:  pointer to mem struct to fill out
4539  * @size: size of memory requested
4540  **/
4541 enum i40e_status_code
4542 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4543                          struct i40e_virt_mem *mem,
4544                          u32 size)
4545 {
4546         if (!mem)
4547                 return I40E_ERR_PARAM;
4548
4549         mem->size = size;
4550         mem->va = rte_zmalloc("i40e", size, 0);
4551
4552         if (mem->va)
4553                 return I40E_SUCCESS;
4554         else
4555                 return I40E_ERR_NO_MEMORY;
4556 }
4557
4558 /**
4559  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4560  * @hw:   pointer to the HW structure
4561  * @mem:  pointer to mem struct to free
4562  **/
4563 enum i40e_status_code
4564 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4565                      struct i40e_virt_mem *mem)
4566 {
4567         if (!mem)
4568                 return I40E_ERR_PARAM;
4569
4570         rte_free(mem->va);
4571         mem->va = NULL;
4572
4573         return I40E_SUCCESS;
4574 }
4575
4576 void
4577 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4578 {
4579         rte_spinlock_init(&sp->spinlock);
4580 }
4581
4582 void
4583 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4584 {
4585         rte_spinlock_lock(&sp->spinlock);
4586 }
4587
4588 void
4589 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4590 {
4591         rte_spinlock_unlock(&sp->spinlock);
4592 }
4593
4594 void
4595 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4596 {
4597         return;
4598 }
4599
4600 /**
4601  * Get the hardware capabilities, which will be parsed
4602  * and saved into struct i40e_hw.
4603  */
4604 static int
4605 i40e_get_cap(struct i40e_hw *hw)
4606 {
4607         struct i40e_aqc_list_capabilities_element_resp *buf;
4608         uint16_t len, size = 0;
4609         int ret;
4610
4611         /* Calculate a huge enough buff for saving response data temporarily */
4612         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4613                                                 I40E_MAX_CAP_ELE_NUM;
4614         buf = rte_zmalloc("i40e", len, 0);
4615         if (!buf) {
4616                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4617                 return I40E_ERR_NO_MEMORY;
4618         }
4619
4620         /* Get, parse the capabilities and save it to hw */
4621         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4622                         i40e_aqc_opc_list_func_capabilities, NULL);
4623         if (ret != I40E_SUCCESS)
4624                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4625
4626         /* Free the temporary buffer after being used */
4627         rte_free(buf);
4628
4629         return ret;
4630 }
4631
4632 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4633
4634 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4635                 const char *value,
4636                 void *opaque)
4637 {
4638         struct i40e_pf *pf;
4639         unsigned long num;
4640         char *end;
4641
4642         pf = (struct i40e_pf *)opaque;
4643         RTE_SET_USED(key);
4644
4645         errno = 0;
4646         num = strtoul(value, &end, 0);
4647         if (errno != 0 || end == value || *end != 0) {
4648                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4649                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4650                 return -(EINVAL);
4651         }
4652
4653         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4654                 pf->vf_nb_qp_max = (uint16_t)num;
4655         else
4656                 /* here return 0 to make next valid same argument work */
4657                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4658                             "power of 2 and equal or less than 16 !, Now it is "
4659                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4660
4661         return 0;
4662 }
4663
4664 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4665 {
4666         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4667         struct rte_kvargs *kvlist;
4668         int kvargs_count;
4669
4670         /* set default queue number per VF as 4 */
4671         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4672
4673         if (dev->device->devargs == NULL)
4674                 return 0;
4675
4676         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4677         if (kvlist == NULL)
4678                 return -(EINVAL);
4679
4680         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4681         if (!kvargs_count) {
4682                 rte_kvargs_free(kvlist);
4683                 return 0;
4684         }
4685
4686         if (kvargs_count > 1)
4687                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4688                             "the first invalid or last valid one is used !",
4689                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4690
4691         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4692                            i40e_pf_parse_vf_queue_number_handler, pf);
4693
4694         rte_kvargs_free(kvlist);
4695
4696         return 0;
4697 }
4698
4699 static int
4700 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4701 {
4702         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4703         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4704         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4705         uint16_t qp_count = 0, vsi_count = 0;
4706
4707         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4708                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4709                 return -EINVAL;
4710         }
4711
4712         i40e_pf_config_vf_rxq_number(dev);
4713
4714         /* Add the parameter init for LFC */
4715         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4716         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4717         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4718
4719         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4720         pf->max_num_vsi = hw->func_caps.num_vsis;
4721         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4722         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4723
4724         /* FDir queue/VSI allocation */
4725         pf->fdir_qp_offset = 0;
4726         if (hw->func_caps.fd) {
4727                 pf->flags |= I40E_FLAG_FDIR;
4728                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4729         } else {
4730                 pf->fdir_nb_qps = 0;
4731         }
4732         qp_count += pf->fdir_nb_qps;
4733         vsi_count += 1;
4734
4735         /* LAN queue/VSI allocation */
4736         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4737         if (!hw->func_caps.rss) {
4738                 pf->lan_nb_qps = 1;
4739         } else {
4740                 pf->flags |= I40E_FLAG_RSS;
4741                 if (hw->mac.type == I40E_MAC_X722)
4742                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4743                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4744         }
4745         qp_count += pf->lan_nb_qps;
4746         vsi_count += 1;
4747
4748         /* VF queue/VSI allocation */
4749         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4750         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4751                 pf->flags |= I40E_FLAG_SRIOV;
4752                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4753                 pf->vf_num = pci_dev->max_vfs;
4754                 PMD_DRV_LOG(DEBUG,
4755                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4756                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4757         } else {
4758                 pf->vf_nb_qps = 0;
4759                 pf->vf_num = 0;
4760         }
4761         qp_count += pf->vf_nb_qps * pf->vf_num;
4762         vsi_count += pf->vf_num;
4763
4764         /* VMDq queue/VSI allocation */
4765         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4766         pf->vmdq_nb_qps = 0;
4767         pf->max_nb_vmdq_vsi = 0;
4768         if (hw->func_caps.vmdq) {
4769                 if (qp_count < hw->func_caps.num_tx_qp &&
4770                         vsi_count < hw->func_caps.num_vsis) {
4771                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4772                                 qp_count) / pf->vmdq_nb_qp_max;
4773
4774                         /* Limit the maximum number of VMDq vsi to the maximum
4775                          * ethdev can support
4776                          */
4777                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4778                                 hw->func_caps.num_vsis - vsi_count);
4779                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4780                                 ETH_64_POOLS);
4781                         if (pf->max_nb_vmdq_vsi) {
4782                                 pf->flags |= I40E_FLAG_VMDQ;
4783                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4784                                 PMD_DRV_LOG(DEBUG,
4785                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4786                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4787                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4788                         } else {
4789                                 PMD_DRV_LOG(INFO,
4790                                         "No enough queues left for VMDq");
4791                         }
4792                 } else {
4793                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4794                 }
4795         }
4796         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4797         vsi_count += pf->max_nb_vmdq_vsi;
4798
4799         if (hw->func_caps.dcb)
4800                 pf->flags |= I40E_FLAG_DCB;
4801
4802         if (qp_count > hw->func_caps.num_tx_qp) {
4803                 PMD_DRV_LOG(ERR,
4804                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4805                         qp_count, hw->func_caps.num_tx_qp);
4806                 return -EINVAL;
4807         }
4808         if (vsi_count > hw->func_caps.num_vsis) {
4809                 PMD_DRV_LOG(ERR,
4810                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4811                         vsi_count, hw->func_caps.num_vsis);
4812                 return -EINVAL;
4813         }
4814
4815         return 0;
4816 }
4817
4818 static int
4819 i40e_pf_get_switch_config(struct i40e_pf *pf)
4820 {
4821         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4822         struct i40e_aqc_get_switch_config_resp *switch_config;
4823         struct i40e_aqc_switch_config_element_resp *element;
4824         uint16_t start_seid = 0, num_reported;
4825         int ret;
4826
4827         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4828                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4829         if (!switch_config) {
4830                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4831                 return -ENOMEM;
4832         }
4833
4834         /* Get the switch configurations */
4835         ret = i40e_aq_get_switch_config(hw, switch_config,
4836                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4837         if (ret != I40E_SUCCESS) {
4838                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4839                 goto fail;
4840         }
4841         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4842         if (num_reported != 1) { /* The number should be 1 */
4843                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4844                 goto fail;
4845         }
4846
4847         /* Parse the switch configuration elements */
4848         element = &(switch_config->element[0]);
4849         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4850                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4851                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4852         } else
4853                 PMD_DRV_LOG(INFO, "Unknown element type");
4854
4855 fail:
4856         rte_free(switch_config);
4857
4858         return ret;
4859 }
4860
4861 static int
4862 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4863                         uint32_t num)
4864 {
4865         struct pool_entry *entry;
4866
4867         if (pool == NULL || num == 0)
4868                 return -EINVAL;
4869
4870         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4871         if (entry == NULL) {
4872                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4873                 return -ENOMEM;
4874         }
4875
4876         /* queue heap initialize */
4877         pool->num_free = num;
4878         pool->num_alloc = 0;
4879         pool->base = base;
4880         LIST_INIT(&pool->alloc_list);
4881         LIST_INIT(&pool->free_list);
4882
4883         /* Initialize element  */
4884         entry->base = 0;
4885         entry->len = num;
4886
4887         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4888         return 0;
4889 }
4890
4891 static void
4892 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4893 {
4894         struct pool_entry *entry, *next_entry;
4895
4896         if (pool == NULL)
4897                 return;
4898
4899         for (entry = LIST_FIRST(&pool->alloc_list);
4900                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4901                         entry = next_entry) {
4902                 LIST_REMOVE(entry, next);
4903                 rte_free(entry);
4904         }
4905
4906         for (entry = LIST_FIRST(&pool->free_list);
4907                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4908                         entry = next_entry) {
4909                 LIST_REMOVE(entry, next);
4910                 rte_free(entry);
4911         }
4912
4913         pool->num_free = 0;
4914         pool->num_alloc = 0;
4915         pool->base = 0;
4916         LIST_INIT(&pool->alloc_list);
4917         LIST_INIT(&pool->free_list);
4918 }
4919
4920 static int
4921 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4922                        uint32_t base)
4923 {
4924         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4925         uint32_t pool_offset;
4926         int insert;
4927
4928         if (pool == NULL) {
4929                 PMD_DRV_LOG(ERR, "Invalid parameter");
4930                 return -EINVAL;
4931         }
4932
4933         pool_offset = base - pool->base;
4934         /* Lookup in alloc list */
4935         LIST_FOREACH(entry, &pool->alloc_list, next) {
4936                 if (entry->base == pool_offset) {
4937                         valid_entry = entry;
4938                         LIST_REMOVE(entry, next);
4939                         break;
4940                 }
4941         }
4942
4943         /* Not find, return */
4944         if (valid_entry == NULL) {
4945                 PMD_DRV_LOG(ERR, "Failed to find entry");
4946                 return -EINVAL;
4947         }
4948
4949         /**
4950          * Found it, move it to free list  and try to merge.
4951          * In order to make merge easier, always sort it by qbase.
4952          * Find adjacent prev and last entries.
4953          */
4954         prev = next = NULL;
4955         LIST_FOREACH(entry, &pool->free_list, next) {
4956                 if (entry->base > valid_entry->base) {
4957                         next = entry;
4958                         break;
4959                 }
4960                 prev = entry;
4961         }
4962
4963         insert = 0;
4964         /* Try to merge with next one*/
4965         if (next != NULL) {
4966                 /* Merge with next one */
4967                 if (valid_entry->base + valid_entry->len == next->base) {
4968                         next->base = valid_entry->base;
4969                         next->len += valid_entry->len;
4970                         rte_free(valid_entry);
4971                         valid_entry = next;
4972                         insert = 1;
4973                 }
4974         }
4975
4976         if (prev != NULL) {
4977                 /* Merge with previous one */
4978                 if (prev->base + prev->len == valid_entry->base) {
4979                         prev->len += valid_entry->len;
4980                         /* If it merge with next one, remove next node */
4981                         if (insert == 1) {
4982                                 LIST_REMOVE(valid_entry, next);
4983                                 rte_free(valid_entry);
4984                         } else {
4985                                 rte_free(valid_entry);
4986                                 insert = 1;
4987                         }
4988                 }
4989         }
4990
4991         /* Not find any entry to merge, insert */
4992         if (insert == 0) {
4993                 if (prev != NULL)
4994                         LIST_INSERT_AFTER(prev, valid_entry, next);
4995                 else if (next != NULL)
4996                         LIST_INSERT_BEFORE(next, valid_entry, next);
4997                 else /* It's empty list, insert to head */
4998                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4999         }
5000
5001         pool->num_free += valid_entry->len;
5002         pool->num_alloc -= valid_entry->len;
5003
5004         return 0;
5005 }
5006
5007 static int
5008 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5009                        uint16_t num)
5010 {
5011         struct pool_entry *entry, *valid_entry;
5012
5013         if (pool == NULL || num == 0) {
5014                 PMD_DRV_LOG(ERR, "Invalid parameter");
5015                 return -EINVAL;
5016         }
5017
5018         if (pool->num_free < num) {
5019                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5020                             num, pool->num_free);
5021                 return -ENOMEM;
5022         }
5023
5024         valid_entry = NULL;
5025         /* Lookup  in free list and find most fit one */
5026         LIST_FOREACH(entry, &pool->free_list, next) {
5027                 if (entry->len >= num) {
5028                         /* Find best one */
5029                         if (entry->len == num) {
5030                                 valid_entry = entry;
5031                                 break;
5032                         }
5033                         if (valid_entry == NULL || valid_entry->len > entry->len)
5034                                 valid_entry = entry;
5035                 }
5036         }
5037
5038         /* Not find one to satisfy the request, return */
5039         if (valid_entry == NULL) {
5040                 PMD_DRV_LOG(ERR, "No valid entry found");
5041                 return -ENOMEM;
5042         }
5043         /**
5044          * The entry have equal queue number as requested,
5045          * remove it from alloc_list.
5046          */
5047         if (valid_entry->len == num) {
5048                 LIST_REMOVE(valid_entry, next);
5049         } else {
5050                 /**
5051                  * The entry have more numbers than requested,
5052                  * create a new entry for alloc_list and minus its
5053                  * queue base and number in free_list.
5054                  */
5055                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5056                 if (entry == NULL) {
5057                         PMD_DRV_LOG(ERR,
5058                                 "Failed to allocate memory for resource pool");
5059                         return -ENOMEM;
5060                 }
5061                 entry->base = valid_entry->base;
5062                 entry->len = num;
5063                 valid_entry->base += num;
5064                 valid_entry->len -= num;
5065                 valid_entry = entry;
5066         }
5067
5068         /* Insert it into alloc list, not sorted */
5069         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5070
5071         pool->num_free -= valid_entry->len;
5072         pool->num_alloc += valid_entry->len;
5073
5074         return valid_entry->base + pool->base;
5075 }
5076
5077 /**
5078  * bitmap_is_subset - Check whether src2 is subset of src1
5079  **/
5080 static inline int
5081 bitmap_is_subset(uint8_t src1, uint8_t src2)
5082 {
5083         return !((src1 ^ src2) & src2);
5084 }
5085
5086 static enum i40e_status_code
5087 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5088 {
5089         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5090
5091         /* If DCB is not supported, only default TC is supported */
5092         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5093                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5094                 return I40E_NOT_SUPPORTED;
5095         }
5096
5097         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5098                 PMD_DRV_LOG(ERR,
5099                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5100                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5101                 return I40E_NOT_SUPPORTED;
5102         }
5103         return I40E_SUCCESS;
5104 }
5105
5106 int
5107 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5108                                 struct i40e_vsi_vlan_pvid_info *info)
5109 {
5110         struct i40e_hw *hw;
5111         struct i40e_vsi_context ctxt;
5112         uint8_t vlan_flags = 0;
5113         int ret;
5114
5115         if (vsi == NULL || info == NULL) {
5116                 PMD_DRV_LOG(ERR, "invalid parameters");
5117                 return I40E_ERR_PARAM;
5118         }
5119
5120         if (info->on) {
5121                 vsi->info.pvid = info->config.pvid;
5122                 /**
5123                  * If insert pvid is enabled, only tagged pkts are
5124                  * allowed to be sent out.
5125                  */
5126                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5127                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5128         } else {
5129                 vsi->info.pvid = 0;
5130                 if (info->config.reject.tagged == 0)
5131                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5132
5133                 if (info->config.reject.untagged == 0)
5134                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5135         }
5136         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5137                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5138         vsi->info.port_vlan_flags |= vlan_flags;
5139         vsi->info.valid_sections =
5140                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5141         memset(&ctxt, 0, sizeof(ctxt));
5142         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5143         ctxt.seid = vsi->seid;
5144
5145         hw = I40E_VSI_TO_HW(vsi);
5146         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5147         if (ret != I40E_SUCCESS)
5148                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5149
5150         return ret;
5151 }
5152
5153 static int
5154 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5155 {
5156         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5157         int i, ret;
5158         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5159
5160         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5161         if (ret != I40E_SUCCESS)
5162                 return ret;
5163
5164         if (!vsi->seid) {
5165                 PMD_DRV_LOG(ERR, "seid not valid");
5166                 return -EINVAL;
5167         }
5168
5169         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5170         tc_bw_data.tc_valid_bits = enabled_tcmap;
5171         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5172                 tc_bw_data.tc_bw_credits[i] =
5173                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5174
5175         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5176         if (ret != I40E_SUCCESS) {
5177                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5178                 return ret;
5179         }
5180
5181         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5182                                         sizeof(vsi->info.qs_handle));
5183         return I40E_SUCCESS;
5184 }
5185
5186 static enum i40e_status_code
5187 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5188                                  struct i40e_aqc_vsi_properties_data *info,
5189                                  uint8_t enabled_tcmap)
5190 {
5191         enum i40e_status_code ret;
5192         int i, total_tc = 0;
5193         uint16_t qpnum_per_tc, bsf, qp_idx;
5194
5195         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5196         if (ret != I40E_SUCCESS)
5197                 return ret;
5198
5199         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5200                 if (enabled_tcmap & (1 << i))
5201                         total_tc++;
5202         if (total_tc == 0)
5203                 total_tc = 1;
5204         vsi->enabled_tc = enabled_tcmap;
5205
5206         /* Number of queues per enabled TC */
5207         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5208         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5209         bsf = rte_bsf32(qpnum_per_tc);
5210
5211         /* Adjust the queue number to actual queues that can be applied */
5212         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5213                 vsi->nb_qps = qpnum_per_tc * total_tc;
5214
5215         /**
5216          * Configure TC and queue mapping parameters, for enabled TC,
5217          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5218          * default queue will serve it.
5219          */
5220         qp_idx = 0;
5221         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5222                 if (vsi->enabled_tc & (1 << i)) {
5223                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5224                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5225                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5226                         qp_idx += qpnum_per_tc;
5227                 } else
5228                         info->tc_mapping[i] = 0;
5229         }
5230
5231         /* Associate queue number with VSI */
5232         if (vsi->type == I40E_VSI_SRIOV) {
5233                 info->mapping_flags |=
5234                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5235                 for (i = 0; i < vsi->nb_qps; i++)
5236                         info->queue_mapping[i] =
5237                                 rte_cpu_to_le_16(vsi->base_queue + i);
5238         } else {
5239                 info->mapping_flags |=
5240                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5241                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5242         }
5243         info->valid_sections |=
5244                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5245
5246         return I40E_SUCCESS;
5247 }
5248
5249 static int
5250 i40e_veb_release(struct i40e_veb *veb)
5251 {
5252         struct i40e_vsi *vsi;
5253         struct i40e_hw *hw;
5254
5255         if (veb == NULL)
5256                 return -EINVAL;
5257
5258         if (!TAILQ_EMPTY(&veb->head)) {
5259                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5260                 return -EACCES;
5261         }
5262         /* associate_vsi field is NULL for floating VEB */
5263         if (veb->associate_vsi != NULL) {
5264                 vsi = veb->associate_vsi;
5265                 hw = I40E_VSI_TO_HW(vsi);
5266
5267                 vsi->uplink_seid = veb->uplink_seid;
5268                 vsi->veb = NULL;
5269         } else {
5270                 veb->associate_pf->main_vsi->floating_veb = NULL;
5271                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5272         }
5273
5274         i40e_aq_delete_element(hw, veb->seid, NULL);
5275         rte_free(veb);
5276         return I40E_SUCCESS;
5277 }
5278
5279 /* Setup a veb */
5280 static struct i40e_veb *
5281 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5282 {
5283         struct i40e_veb *veb;
5284         int ret;
5285         struct i40e_hw *hw;
5286
5287         if (pf == NULL) {
5288                 PMD_DRV_LOG(ERR,
5289                             "veb setup failed, associated PF shouldn't null");
5290                 return NULL;
5291         }
5292         hw = I40E_PF_TO_HW(pf);
5293
5294         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5295         if (!veb) {
5296                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5297                 goto fail;
5298         }
5299
5300         veb->associate_vsi = vsi;
5301         veb->associate_pf = pf;
5302         TAILQ_INIT(&veb->head);
5303         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5304
5305         /* create floating veb if vsi is NULL */
5306         if (vsi != NULL) {
5307                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5308                                       I40E_DEFAULT_TCMAP, false,
5309                                       &veb->seid, false, NULL);
5310         } else {
5311                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5312                                       true, &veb->seid, false, NULL);
5313         }
5314
5315         if (ret != I40E_SUCCESS) {
5316                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5317                             hw->aq.asq_last_status);
5318                 goto fail;
5319         }
5320         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5321
5322         /* get statistics index */
5323         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5324                                 &veb->stats_idx, NULL, NULL, NULL);
5325         if (ret != I40E_SUCCESS) {
5326                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5327                             hw->aq.asq_last_status);
5328                 goto fail;
5329         }
5330         /* Get VEB bandwidth, to be implemented */
5331         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5332         if (vsi)
5333                 vsi->uplink_seid = veb->seid;
5334
5335         return veb;
5336 fail:
5337         rte_free(veb);
5338         return NULL;
5339 }
5340
5341 int
5342 i40e_vsi_release(struct i40e_vsi *vsi)
5343 {
5344         struct i40e_pf *pf;
5345         struct i40e_hw *hw;
5346         struct i40e_vsi_list *vsi_list;
5347         void *temp;
5348         int ret;
5349         struct i40e_mac_filter *f;
5350         uint16_t user_param;
5351
5352         if (!vsi)
5353                 return I40E_SUCCESS;
5354
5355         if (!vsi->adapter)
5356                 return -EFAULT;
5357
5358         user_param = vsi->user_param;
5359
5360         pf = I40E_VSI_TO_PF(vsi);
5361         hw = I40E_VSI_TO_HW(vsi);
5362
5363         /* VSI has child to attach, release child first */
5364         if (vsi->veb) {
5365                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5366                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5367                                 return -1;
5368                 }
5369                 i40e_veb_release(vsi->veb);
5370         }
5371
5372         if (vsi->floating_veb) {
5373                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5374                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5375                                 return -1;
5376                 }
5377         }
5378
5379         /* Remove all macvlan filters of the VSI */
5380         i40e_vsi_remove_all_macvlan_filter(vsi);
5381         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5382                 rte_free(f);
5383
5384         if (vsi->type != I40E_VSI_MAIN &&
5385             ((vsi->type != I40E_VSI_SRIOV) ||
5386             !pf->floating_veb_list[user_param])) {
5387                 /* Remove vsi from parent's sibling list */
5388                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5389                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5390                         return I40E_ERR_PARAM;
5391                 }
5392                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5393                                 &vsi->sib_vsi_list, list);
5394
5395                 /* Remove all switch element of the VSI */
5396                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5397                 if (ret != I40E_SUCCESS)
5398                         PMD_DRV_LOG(ERR, "Failed to delete element");
5399         }
5400
5401         if ((vsi->type == I40E_VSI_SRIOV) &&
5402             pf->floating_veb_list[user_param]) {
5403                 /* Remove vsi from parent's sibling list */
5404                 if (vsi->parent_vsi == NULL ||
5405                     vsi->parent_vsi->floating_veb == NULL) {
5406                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5407                         return I40E_ERR_PARAM;
5408                 }
5409                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5410                              &vsi->sib_vsi_list, list);
5411
5412                 /* Remove all switch element of the VSI */
5413                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5414                 if (ret != I40E_SUCCESS)
5415                         PMD_DRV_LOG(ERR, "Failed to delete element");
5416         }
5417
5418         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5419
5420         if (vsi->type != I40E_VSI_SRIOV)
5421                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5422         rte_free(vsi);
5423
5424         return I40E_SUCCESS;
5425 }
5426
5427 static int
5428 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5429 {
5430         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5431         struct i40e_aqc_remove_macvlan_element_data def_filter;
5432         struct i40e_mac_filter_info filter;
5433         int ret;
5434
5435         if (vsi->type != I40E_VSI_MAIN)
5436                 return I40E_ERR_CONFIG;
5437         memset(&def_filter, 0, sizeof(def_filter));
5438         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5439                                         ETH_ADDR_LEN);
5440         def_filter.vlan_tag = 0;
5441         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5442                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5443         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5444         if (ret != I40E_SUCCESS) {
5445                 struct i40e_mac_filter *f;
5446                 struct rte_ether_addr *mac;
5447
5448                 PMD_DRV_LOG(DEBUG,
5449                             "Cannot remove the default macvlan filter");
5450                 /* It needs to add the permanent mac into mac list */
5451                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5452                 if (f == NULL) {
5453                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5454                         return I40E_ERR_NO_MEMORY;
5455                 }
5456                 mac = &f->mac_info.mac_addr;
5457                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5458                                 ETH_ADDR_LEN);
5459                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5460                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5461                 vsi->mac_num++;
5462
5463                 return ret;
5464         }
5465         rte_memcpy(&filter.mac_addr,
5466                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5467         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5468         return i40e_vsi_add_mac(vsi, &filter);
5469 }
5470
5471 /*
5472  * i40e_vsi_get_bw_config - Query VSI BW Information
5473  * @vsi: the VSI to be queried
5474  *
5475  * Returns 0 on success, negative value on failure
5476  */
5477 static enum i40e_status_code
5478 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5479 {
5480         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5481         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5482         struct i40e_hw *hw = &vsi->adapter->hw;
5483         i40e_status ret;
5484         int i;
5485         uint32_t bw_max;
5486
5487         memset(&bw_config, 0, sizeof(bw_config));
5488         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5489         if (ret != I40E_SUCCESS) {
5490                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5491                             hw->aq.asq_last_status);
5492                 return ret;
5493         }
5494
5495         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5496         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5497                                         &ets_sla_config, NULL);
5498         if (ret != I40E_SUCCESS) {
5499                 PMD_DRV_LOG(ERR,
5500                         "VSI failed to get TC bandwdith configuration %u",
5501                         hw->aq.asq_last_status);
5502                 return ret;
5503         }
5504
5505         /* store and print out BW info */
5506         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5507         vsi->bw_info.bw_max = bw_config.max_bw;
5508         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5509         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5510         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5511                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5512                      I40E_16_BIT_WIDTH);
5513         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5514                 vsi->bw_info.bw_ets_share_credits[i] =
5515                                 ets_sla_config.share_credits[i];
5516                 vsi->bw_info.bw_ets_credits[i] =
5517                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5518                 /* 4 bits per TC, 4th bit is reserved */
5519                 vsi->bw_info.bw_ets_max[i] =
5520                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5521                                   RTE_LEN2MASK(3, uint8_t));
5522                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5523                             vsi->bw_info.bw_ets_share_credits[i]);
5524                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5525                             vsi->bw_info.bw_ets_credits[i]);
5526                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5527                             vsi->bw_info.bw_ets_max[i]);
5528         }
5529
5530         return I40E_SUCCESS;
5531 }
5532
5533 /* i40e_enable_pf_lb
5534  * @pf: pointer to the pf structure
5535  *
5536  * allow loopback on pf
5537  */
5538 static inline void
5539 i40e_enable_pf_lb(struct i40e_pf *pf)
5540 {
5541         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5542         struct i40e_vsi_context ctxt;
5543         int ret;
5544
5545         /* Use the FW API if FW >= v5.0 */
5546         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5547                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5548                 return;
5549         }
5550
5551         memset(&ctxt, 0, sizeof(ctxt));
5552         ctxt.seid = pf->main_vsi_seid;
5553         ctxt.pf_num = hw->pf_id;
5554         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5555         if (ret) {
5556                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5557                             ret, hw->aq.asq_last_status);
5558                 return;
5559         }
5560         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5561         ctxt.info.valid_sections =
5562                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5563         ctxt.info.switch_id |=
5564                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5565
5566         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5567         if (ret)
5568                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5569                             hw->aq.asq_last_status);
5570 }
5571
5572 /* Setup a VSI */
5573 struct i40e_vsi *
5574 i40e_vsi_setup(struct i40e_pf *pf,
5575                enum i40e_vsi_type type,
5576                struct i40e_vsi *uplink_vsi,
5577                uint16_t user_param)
5578 {
5579         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5580         struct i40e_vsi *vsi;
5581         struct i40e_mac_filter_info filter;
5582         int ret;
5583         struct i40e_vsi_context ctxt;
5584         struct rte_ether_addr broadcast =
5585                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5586
5587         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5588             uplink_vsi == NULL) {
5589                 PMD_DRV_LOG(ERR,
5590                         "VSI setup failed, VSI link shouldn't be NULL");
5591                 return NULL;
5592         }
5593
5594         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5595                 PMD_DRV_LOG(ERR,
5596                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5597                 return NULL;
5598         }
5599
5600         /* two situations
5601          * 1.type is not MAIN and uplink vsi is not NULL
5602          * If uplink vsi didn't setup VEB, create one first under veb field
5603          * 2.type is SRIOV and the uplink is NULL
5604          * If floating VEB is NULL, create one veb under floating veb field
5605          */
5606
5607         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5608             uplink_vsi->veb == NULL) {
5609                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5610
5611                 if (uplink_vsi->veb == NULL) {
5612                         PMD_DRV_LOG(ERR, "VEB setup failed");
5613                         return NULL;
5614                 }
5615                 /* set ALLOWLOOPBACk on pf, when veb is created */
5616                 i40e_enable_pf_lb(pf);
5617         }
5618
5619         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5620             pf->main_vsi->floating_veb == NULL) {
5621                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5622
5623                 if (pf->main_vsi->floating_veb == NULL) {
5624                         PMD_DRV_LOG(ERR, "VEB setup failed");
5625                         return NULL;
5626                 }
5627         }
5628
5629         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5630         if (!vsi) {
5631                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5632                 return NULL;
5633         }
5634         TAILQ_INIT(&vsi->mac_list);
5635         vsi->type = type;
5636         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5637         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5638         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5639         vsi->user_param = user_param;
5640         vsi->vlan_anti_spoof_on = 0;
5641         vsi->vlan_filter_on = 0;
5642         /* Allocate queues */
5643         switch (vsi->type) {
5644         case I40E_VSI_MAIN  :
5645                 vsi->nb_qps = pf->lan_nb_qps;
5646                 break;
5647         case I40E_VSI_SRIOV :
5648                 vsi->nb_qps = pf->vf_nb_qps;
5649                 break;
5650         case I40E_VSI_VMDQ2:
5651                 vsi->nb_qps = pf->vmdq_nb_qps;
5652                 break;
5653         case I40E_VSI_FDIR:
5654                 vsi->nb_qps = pf->fdir_nb_qps;
5655                 break;
5656         default:
5657                 goto fail_mem;
5658         }
5659         /*
5660          * The filter status descriptor is reported in rx queue 0,
5661          * while the tx queue for fdir filter programming has no
5662          * such constraints, can be non-zero queues.
5663          * To simplify it, choose FDIR vsi use queue 0 pair.
5664          * To make sure it will use queue 0 pair, queue allocation
5665          * need be done before this function is called
5666          */
5667         if (type != I40E_VSI_FDIR) {
5668                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5669                         if (ret < 0) {
5670                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5671                                                 vsi->seid, ret);
5672                                 goto fail_mem;
5673                         }
5674                         vsi->base_queue = ret;
5675         } else
5676                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5677
5678         /* VF has MSIX interrupt in VF range, don't allocate here */
5679         if (type == I40E_VSI_MAIN) {
5680                 if (pf->support_multi_driver) {
5681                         /* If support multi-driver, need to use INT0 instead of
5682                          * allocating from msix pool. The Msix pool is init from
5683                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5684                          * to 1 without calling i40e_res_pool_alloc.
5685                          */
5686                         vsi->msix_intr = 0;
5687                         vsi->nb_msix = 1;
5688                 } else {
5689                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5690                                                   RTE_MIN(vsi->nb_qps,
5691                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5692                         if (ret < 0) {
5693                                 PMD_DRV_LOG(ERR,
5694                                             "VSI MAIN %d get heap failed %d",
5695                                             vsi->seid, ret);
5696                                 goto fail_queue_alloc;
5697                         }
5698                         vsi->msix_intr = ret;
5699                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5700                                                RTE_MAX_RXTX_INTR_VEC_ID);
5701                 }
5702         } else if (type != I40E_VSI_SRIOV) {
5703                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5704                 if (ret < 0) {
5705                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5706                         goto fail_queue_alloc;
5707                 }
5708                 vsi->msix_intr = ret;
5709                 vsi->nb_msix = 1;
5710         } else {
5711                 vsi->msix_intr = 0;
5712                 vsi->nb_msix = 0;
5713         }
5714
5715         /* Add VSI */
5716         if (type == I40E_VSI_MAIN) {
5717                 /* For main VSI, no need to add since it's default one */
5718                 vsi->uplink_seid = pf->mac_seid;
5719                 vsi->seid = pf->main_vsi_seid;
5720                 /* Bind queues with specific MSIX interrupt */
5721                 /**
5722                  * Needs 2 interrupt at least, one for misc cause which will
5723                  * enabled from OS side, Another for queues binding the
5724                  * interrupt from device side only.
5725                  */
5726
5727                 /* Get default VSI parameters from hardware */
5728                 memset(&ctxt, 0, sizeof(ctxt));
5729                 ctxt.seid = vsi->seid;
5730                 ctxt.pf_num = hw->pf_id;
5731                 ctxt.uplink_seid = vsi->uplink_seid;
5732                 ctxt.vf_num = 0;
5733                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5734                 if (ret != I40E_SUCCESS) {
5735                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5736                         goto fail_msix_alloc;
5737                 }
5738                 rte_memcpy(&vsi->info, &ctxt.info,
5739                         sizeof(struct i40e_aqc_vsi_properties_data));
5740                 vsi->vsi_id = ctxt.vsi_number;
5741                 vsi->info.valid_sections = 0;
5742
5743                 /* Configure tc, enabled TC0 only */
5744                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5745                         I40E_SUCCESS) {
5746                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5747                         goto fail_msix_alloc;
5748                 }
5749
5750                 /* TC, queue mapping */
5751                 memset(&ctxt, 0, sizeof(ctxt));
5752                 vsi->info.valid_sections |=
5753                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5754                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5755                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5756                 rte_memcpy(&ctxt.info, &vsi->info,
5757                         sizeof(struct i40e_aqc_vsi_properties_data));
5758                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5759                                                 I40E_DEFAULT_TCMAP);
5760                 if (ret != I40E_SUCCESS) {
5761                         PMD_DRV_LOG(ERR,
5762                                 "Failed to configure TC queue mapping");
5763                         goto fail_msix_alloc;
5764                 }
5765                 ctxt.seid = vsi->seid;
5766                 ctxt.pf_num = hw->pf_id;
5767                 ctxt.uplink_seid = vsi->uplink_seid;
5768                 ctxt.vf_num = 0;
5769
5770                 /* Update VSI parameters */
5771                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5772                 if (ret != I40E_SUCCESS) {
5773                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5774                         goto fail_msix_alloc;
5775                 }
5776
5777                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5778                                                 sizeof(vsi->info.tc_mapping));
5779                 rte_memcpy(&vsi->info.queue_mapping,
5780                                 &ctxt.info.queue_mapping,
5781                         sizeof(vsi->info.queue_mapping));
5782                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5783                 vsi->info.valid_sections = 0;
5784
5785                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5786                                 ETH_ADDR_LEN);
5787
5788                 /**
5789                  * Updating default filter settings are necessary to prevent
5790                  * reception of tagged packets.
5791                  * Some old firmware configurations load a default macvlan
5792                  * filter which accepts both tagged and untagged packets.
5793                  * The updating is to use a normal filter instead if needed.
5794                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5795                  * The firmware with correct configurations load the default
5796                  * macvlan filter which is expected and cannot be removed.
5797                  */
5798                 i40e_update_default_filter_setting(vsi);
5799                 i40e_config_qinq(hw, vsi);
5800         } else if (type == I40E_VSI_SRIOV) {
5801                 memset(&ctxt, 0, sizeof(ctxt));
5802                 /**
5803                  * For other VSI, the uplink_seid equals to uplink VSI's
5804                  * uplink_seid since they share same VEB
5805                  */
5806                 if (uplink_vsi == NULL)
5807                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5808                 else
5809                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5810                 ctxt.pf_num = hw->pf_id;
5811                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5812                 ctxt.uplink_seid = vsi->uplink_seid;
5813                 ctxt.connection_type = 0x1;
5814                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5815
5816                 /* Use the VEB configuration if FW >= v5.0 */
5817                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5818                         /* Configure switch ID */
5819                         ctxt.info.valid_sections |=
5820                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5821                         ctxt.info.switch_id =
5822                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5823                 }
5824
5825                 /* Configure port/vlan */
5826                 ctxt.info.valid_sections |=
5827                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5828                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5829                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5830                                                 hw->func_caps.enabled_tcmap);
5831                 if (ret != I40E_SUCCESS) {
5832                         PMD_DRV_LOG(ERR,
5833                                 "Failed to configure TC queue mapping");
5834                         goto fail_msix_alloc;
5835                 }
5836
5837                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5838                 ctxt.info.valid_sections |=
5839                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5840                 /**
5841                  * Since VSI is not created yet, only configure parameter,
5842                  * will add vsi below.
5843                  */
5844
5845                 i40e_config_qinq(hw, vsi);
5846         } else if (type == I40E_VSI_VMDQ2) {
5847                 memset(&ctxt, 0, sizeof(ctxt));
5848                 /*
5849                  * For other VSI, the uplink_seid equals to uplink VSI's
5850                  * uplink_seid since they share same VEB
5851                  */
5852                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5853                 ctxt.pf_num = hw->pf_id;
5854                 ctxt.vf_num = 0;
5855                 ctxt.uplink_seid = vsi->uplink_seid;
5856                 ctxt.connection_type = 0x1;
5857                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5858
5859                 ctxt.info.valid_sections |=
5860                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5861                 /* user_param carries flag to enable loop back */
5862                 if (user_param) {
5863                         ctxt.info.switch_id =
5864                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5865                         ctxt.info.switch_id |=
5866                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5867                 }
5868
5869                 /* Configure port/vlan */
5870                 ctxt.info.valid_sections |=
5871                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5872                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5873                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5874                                                 I40E_DEFAULT_TCMAP);
5875                 if (ret != I40E_SUCCESS) {
5876                         PMD_DRV_LOG(ERR,
5877                                 "Failed to configure TC queue mapping");
5878                         goto fail_msix_alloc;
5879                 }
5880                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5881                 ctxt.info.valid_sections |=
5882                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5883         } else if (type == I40E_VSI_FDIR) {
5884                 memset(&ctxt, 0, sizeof(ctxt));
5885                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5886                 ctxt.pf_num = hw->pf_id;
5887                 ctxt.vf_num = 0;
5888                 ctxt.uplink_seid = vsi->uplink_seid;
5889                 ctxt.connection_type = 0x1;     /* regular data port */
5890                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5891                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5892                                                 I40E_DEFAULT_TCMAP);
5893                 if (ret != I40E_SUCCESS) {
5894                         PMD_DRV_LOG(ERR,
5895                                 "Failed to configure TC queue mapping.");
5896                         goto fail_msix_alloc;
5897                 }
5898                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5899                 ctxt.info.valid_sections |=
5900                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5901         } else {
5902                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5903                 goto fail_msix_alloc;
5904         }
5905
5906         if (vsi->type != I40E_VSI_MAIN) {
5907                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5908                 if (ret != I40E_SUCCESS) {
5909                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5910                                     hw->aq.asq_last_status);
5911                         goto fail_msix_alloc;
5912                 }
5913                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5914                 vsi->info.valid_sections = 0;
5915                 vsi->seid = ctxt.seid;
5916                 vsi->vsi_id = ctxt.vsi_number;
5917                 vsi->sib_vsi_list.vsi = vsi;
5918                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5919                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5920                                           &vsi->sib_vsi_list, list);
5921                 } else {
5922                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5923                                           &vsi->sib_vsi_list, list);
5924                 }
5925         }
5926
5927         /* MAC/VLAN configuration */
5928         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5929         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5930
5931         ret = i40e_vsi_add_mac(vsi, &filter);
5932         if (ret != I40E_SUCCESS) {
5933                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5934                 goto fail_msix_alloc;
5935         }
5936
5937         /* Get VSI BW information */
5938         i40e_vsi_get_bw_config(vsi);
5939         return vsi;
5940 fail_msix_alloc:
5941         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5942 fail_queue_alloc:
5943         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5944 fail_mem:
5945         rte_free(vsi);
5946         return NULL;
5947 }
5948
5949 /* Configure vlan filter on or off */
5950 int
5951 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5952 {
5953         int i, num;
5954         struct i40e_mac_filter *f;
5955         void *temp;
5956         struct i40e_mac_filter_info *mac_filter;
5957         enum rte_mac_filter_type desired_filter;
5958         int ret = I40E_SUCCESS;
5959
5960         if (on) {
5961                 /* Filter to match MAC and VLAN */
5962                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5963         } else {
5964                 /* Filter to match only MAC */
5965                 desired_filter = RTE_MAC_PERFECT_MATCH;
5966         }
5967
5968         num = vsi->mac_num;
5969
5970         mac_filter = rte_zmalloc("mac_filter_info_data",
5971                                  num * sizeof(*mac_filter), 0);
5972         if (mac_filter == NULL) {
5973                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5974                 return I40E_ERR_NO_MEMORY;
5975         }
5976
5977         i = 0;
5978
5979         /* Remove all existing mac */
5980         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5981                 mac_filter[i] = f->mac_info;
5982                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5983                 if (ret) {
5984                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5985                                     on ? "enable" : "disable");
5986                         goto DONE;
5987                 }
5988                 i++;
5989         }
5990
5991         /* Override with new filter */
5992         for (i = 0; i < num; i++) {
5993                 mac_filter[i].filter_type = desired_filter;
5994                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5995                 if (ret) {
5996                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5997                                     on ? "enable" : "disable");
5998                         goto DONE;
5999                 }
6000         }
6001
6002 DONE:
6003         rte_free(mac_filter);
6004         return ret;
6005 }
6006
6007 /* Configure vlan stripping on or off */
6008 int
6009 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6010 {
6011         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6012         struct i40e_vsi_context ctxt;
6013         uint8_t vlan_flags;
6014         int ret = I40E_SUCCESS;
6015
6016         /* Check if it has been already on or off */
6017         if (vsi->info.valid_sections &
6018                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6019                 if (on) {
6020                         if ((vsi->info.port_vlan_flags &
6021                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6022                                 return 0; /* already on */
6023                 } else {
6024                         if ((vsi->info.port_vlan_flags &
6025                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6026                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6027                                 return 0; /* already off */
6028                 }
6029         }
6030
6031         if (on)
6032                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6033         else
6034                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6035         vsi->info.valid_sections =
6036                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6037         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6038         vsi->info.port_vlan_flags |= vlan_flags;
6039         ctxt.seid = vsi->seid;
6040         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6041         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6042         if (ret)
6043                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6044                             on ? "enable" : "disable");
6045
6046         return ret;
6047 }
6048
6049 static int
6050 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6051 {
6052         struct rte_eth_dev_data *data = dev->data;
6053         int ret;
6054         int mask = 0;
6055
6056         /* Apply vlan offload setting */
6057         mask = ETH_VLAN_STRIP_MASK |
6058                ETH_VLAN_FILTER_MASK |
6059                ETH_VLAN_EXTEND_MASK;
6060         ret = i40e_vlan_offload_set(dev, mask);
6061         if (ret) {
6062                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6063                 return ret;
6064         }
6065
6066         /* Apply pvid setting */
6067         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6068                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6069         if (ret)
6070                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6071
6072         return ret;
6073 }
6074
6075 static int
6076 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6077 {
6078         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6079
6080         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6081 }
6082
6083 static int
6084 i40e_update_flow_control(struct i40e_hw *hw)
6085 {
6086 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6087         struct i40e_link_status link_status;
6088         uint32_t rxfc = 0, txfc = 0, reg;
6089         uint8_t an_info;
6090         int ret;
6091
6092         memset(&link_status, 0, sizeof(link_status));
6093         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6094         if (ret != I40E_SUCCESS) {
6095                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6096                 goto write_reg; /* Disable flow control */
6097         }
6098
6099         an_info = hw->phy.link_info.an_info;
6100         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6101                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6102                 ret = I40E_ERR_NOT_READY;
6103                 goto write_reg; /* Disable flow control */
6104         }
6105         /**
6106          * If link auto negotiation is enabled, flow control needs to
6107          * be configured according to it
6108          */
6109         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6110         case I40E_LINK_PAUSE_RXTX:
6111                 rxfc = 1;
6112                 txfc = 1;
6113                 hw->fc.current_mode = I40E_FC_FULL;
6114                 break;
6115         case I40E_AQ_LINK_PAUSE_RX:
6116                 rxfc = 1;
6117                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6118                 break;
6119         case I40E_AQ_LINK_PAUSE_TX:
6120                 txfc = 1;
6121                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6122                 break;
6123         default:
6124                 hw->fc.current_mode = I40E_FC_NONE;
6125                 break;
6126         }
6127
6128 write_reg:
6129         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6130                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6131         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6132         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6133         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6134         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6135
6136         return ret;
6137 }
6138
6139 /* PF setup */
6140 static int
6141 i40e_pf_setup(struct i40e_pf *pf)
6142 {
6143         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6144         struct i40e_filter_control_settings settings;
6145         struct i40e_vsi *vsi;
6146         int ret;
6147
6148         /* Clear all stats counters */
6149         pf->offset_loaded = FALSE;
6150         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6151         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6152         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6153         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6154
6155         ret = i40e_pf_get_switch_config(pf);
6156         if (ret != I40E_SUCCESS) {
6157                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6158                 return ret;
6159         }
6160
6161         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6162         if (ret)
6163                 PMD_INIT_LOG(WARNING,
6164                         "failed to allocate switch domain for device %d", ret);
6165
6166         if (pf->flags & I40E_FLAG_FDIR) {
6167                 /* make queue allocated first, let FDIR use queue pair 0*/
6168                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6169                 if (ret != I40E_FDIR_QUEUE_ID) {
6170                         PMD_DRV_LOG(ERR,
6171                                 "queue allocation fails for FDIR: ret =%d",
6172                                 ret);
6173                         pf->flags &= ~I40E_FLAG_FDIR;
6174                 }
6175         }
6176         /*  main VSI setup */
6177         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6178         if (!vsi) {
6179                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6180                 return I40E_ERR_NOT_READY;
6181         }
6182         pf->main_vsi = vsi;
6183
6184         /* Configure filter control */
6185         memset(&settings, 0, sizeof(settings));
6186         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6187                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6188         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6189                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6190         else {
6191                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6192                         hw->func_caps.rss_table_size);
6193                 return I40E_ERR_PARAM;
6194         }
6195         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6196                 hw->func_caps.rss_table_size);
6197         pf->hash_lut_size = hw->func_caps.rss_table_size;
6198
6199         /* Enable ethtype and macvlan filters */
6200         settings.enable_ethtype = TRUE;
6201         settings.enable_macvlan = TRUE;
6202         ret = i40e_set_filter_control(hw, &settings);
6203         if (ret)
6204                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6205                                                                 ret);
6206
6207         /* Update flow control according to the auto negotiation */
6208         i40e_update_flow_control(hw);
6209
6210         return I40E_SUCCESS;
6211 }
6212
6213 int
6214 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6215 {
6216         uint32_t reg;
6217         uint16_t j;
6218
6219         /**
6220          * Set or clear TX Queue Disable flags,
6221          * which is required by hardware.
6222          */
6223         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6224         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6225
6226         /* Wait until the request is finished */
6227         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6228                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6229                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6230                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6231                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6232                                                         & 0x1))) {
6233                         break;
6234                 }
6235         }
6236         if (on) {
6237                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6238                         return I40E_SUCCESS; /* already on, skip next steps */
6239
6240                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6241                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6242         } else {
6243                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6244                         return I40E_SUCCESS; /* already off, skip next steps */
6245                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6246         }
6247         /* Write the register */
6248         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6249         /* Check the result */
6250         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6251                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6252                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6253                 if (on) {
6254                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6255                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6256                                 break;
6257                 } else {
6258                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6259                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6260                                 break;
6261                 }
6262         }
6263         /* Check if it is timeout */
6264         if (j >= I40E_CHK_Q_ENA_COUNT) {
6265                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6266                             (on ? "enable" : "disable"), q_idx);
6267                 return I40E_ERR_TIMEOUT;
6268         }
6269
6270         return I40E_SUCCESS;
6271 }
6272
6273 /* Swith on or off the tx queues */
6274 static int
6275 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6276 {
6277         struct rte_eth_dev_data *dev_data = pf->dev_data;
6278         struct i40e_tx_queue *txq;
6279         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6280         uint16_t i;
6281         int ret;
6282
6283         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6284                 txq = dev_data->tx_queues[i];
6285                 /* Don't operate the queue if not configured or
6286                  * if starting only per queue */
6287                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6288                         continue;
6289                 if (on)
6290                         ret = i40e_dev_tx_queue_start(dev, i);
6291                 else
6292                         ret = i40e_dev_tx_queue_stop(dev, i);
6293                 if ( ret != I40E_SUCCESS)
6294                         return ret;
6295         }
6296
6297         return I40E_SUCCESS;
6298 }
6299
6300 int
6301 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6302 {
6303         uint32_t reg;
6304         uint16_t j;
6305
6306         /* Wait until the request is finished */
6307         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6308                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6309                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6310                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6311                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6312                         break;
6313         }
6314
6315         if (on) {
6316                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6317                         return I40E_SUCCESS; /* Already on, skip next steps */
6318                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6319         } else {
6320                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6321                         return I40E_SUCCESS; /* Already off, skip next steps */
6322                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6323         }
6324
6325         /* Write the register */
6326         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6327         /* Check the result */
6328         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6329                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6330                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6331                 if (on) {
6332                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6333                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6334                                 break;
6335                 } else {
6336                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6337                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6338                                 break;
6339                 }
6340         }
6341
6342         /* Check if it is timeout */
6343         if (j >= I40E_CHK_Q_ENA_COUNT) {
6344                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6345                             (on ? "enable" : "disable"), q_idx);
6346                 return I40E_ERR_TIMEOUT;
6347         }
6348
6349         return I40E_SUCCESS;
6350 }
6351 /* Switch on or off the rx queues */
6352 static int
6353 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6354 {
6355         struct rte_eth_dev_data *dev_data = pf->dev_data;
6356         struct i40e_rx_queue *rxq;
6357         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6358         uint16_t i;
6359         int ret;
6360
6361         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6362                 rxq = dev_data->rx_queues[i];
6363                 /* Don't operate the queue if not configured or
6364                  * if starting only per queue */
6365                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6366                         continue;
6367                 if (on)
6368                         ret = i40e_dev_rx_queue_start(dev, i);
6369                 else
6370                         ret = i40e_dev_rx_queue_stop(dev, i);
6371                 if (ret != I40E_SUCCESS)
6372                         return ret;
6373         }
6374
6375         return I40E_SUCCESS;
6376 }
6377
6378 /* Switch on or off all the rx/tx queues */
6379 int
6380 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6381 {
6382         int ret;
6383
6384         if (on) {
6385                 /* enable rx queues before enabling tx queues */
6386                 ret = i40e_dev_switch_rx_queues(pf, on);
6387                 if (ret) {
6388                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6389                         return ret;
6390                 }
6391                 ret = i40e_dev_switch_tx_queues(pf, on);
6392         } else {
6393                 /* Stop tx queues before stopping rx queues */
6394                 ret = i40e_dev_switch_tx_queues(pf, on);
6395                 if (ret) {
6396                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6397                         return ret;
6398                 }
6399                 ret = i40e_dev_switch_rx_queues(pf, on);
6400         }
6401
6402         return ret;
6403 }
6404
6405 /* Initialize VSI for TX */
6406 static int
6407 i40e_dev_tx_init(struct i40e_pf *pf)
6408 {
6409         struct rte_eth_dev_data *data = pf->dev_data;
6410         uint16_t i;
6411         uint32_t ret = I40E_SUCCESS;
6412         struct i40e_tx_queue *txq;
6413
6414         for (i = 0; i < data->nb_tx_queues; i++) {
6415                 txq = data->tx_queues[i];
6416                 if (!txq || !txq->q_set)
6417                         continue;
6418                 ret = i40e_tx_queue_init(txq);
6419                 if (ret != I40E_SUCCESS)
6420                         break;
6421         }
6422         if (ret == I40E_SUCCESS)
6423                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6424                                      ->eth_dev);
6425
6426         return ret;
6427 }
6428
6429 /* Initialize VSI for RX */
6430 static int
6431 i40e_dev_rx_init(struct i40e_pf *pf)
6432 {
6433         struct rte_eth_dev_data *data = pf->dev_data;
6434         int ret = I40E_SUCCESS;
6435         uint16_t i;
6436         struct i40e_rx_queue *rxq;
6437
6438         i40e_pf_config_mq_rx(pf);
6439         for (i = 0; i < data->nb_rx_queues; i++) {
6440                 rxq = data->rx_queues[i];
6441                 if (!rxq || !rxq->q_set)
6442                         continue;
6443
6444                 ret = i40e_rx_queue_init(rxq);
6445                 if (ret != I40E_SUCCESS) {
6446                         PMD_DRV_LOG(ERR,
6447                                 "Failed to do RX queue initialization");
6448                         break;
6449                 }
6450         }
6451         if (ret == I40E_SUCCESS)
6452                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6453                                      ->eth_dev);
6454
6455         return ret;
6456 }
6457
6458 static int
6459 i40e_dev_rxtx_init(struct i40e_pf *pf)
6460 {
6461         int err;
6462
6463         err = i40e_dev_tx_init(pf);
6464         if (err) {
6465                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6466                 return err;
6467         }
6468         err = i40e_dev_rx_init(pf);
6469         if (err) {
6470                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6471                 return err;
6472         }
6473
6474         return err;
6475 }
6476
6477 static int
6478 i40e_vmdq_setup(struct rte_eth_dev *dev)
6479 {
6480         struct rte_eth_conf *conf = &dev->data->dev_conf;
6481         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6482         int i, err, conf_vsis, j, loop;
6483         struct i40e_vsi *vsi;
6484         struct i40e_vmdq_info *vmdq_info;
6485         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6486         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6487
6488         /*
6489          * Disable interrupt to avoid message from VF. Furthermore, it will
6490          * avoid race condition in VSI creation/destroy.
6491          */
6492         i40e_pf_disable_irq0(hw);
6493
6494         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6495                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6496                 return -ENOTSUP;
6497         }
6498
6499         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6500         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6501                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6502                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6503                         pf->max_nb_vmdq_vsi);
6504                 return -ENOTSUP;
6505         }
6506
6507         if (pf->vmdq != NULL) {
6508                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6509                 return 0;
6510         }
6511
6512         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6513                                 sizeof(*vmdq_info) * conf_vsis, 0);
6514
6515         if (pf->vmdq == NULL) {
6516                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6517                 return -ENOMEM;
6518         }
6519
6520         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6521
6522         /* Create VMDQ VSI */
6523         for (i = 0; i < conf_vsis; i++) {
6524                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6525                                 vmdq_conf->enable_loop_back);
6526                 if (vsi == NULL) {
6527                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6528                         err = -1;
6529                         goto err_vsi_setup;
6530                 }
6531                 vmdq_info = &pf->vmdq[i];
6532                 vmdq_info->pf = pf;
6533                 vmdq_info->vsi = vsi;
6534         }
6535         pf->nb_cfg_vmdq_vsi = conf_vsis;
6536
6537         /* Configure Vlan */
6538         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6539         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6540                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6541                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6542                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6543                                         vmdq_conf->pool_map[i].vlan_id, j);
6544
6545                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6546                                                 vmdq_conf->pool_map[i].vlan_id);
6547                                 if (err) {
6548                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6549                                         err = -1;
6550                                         goto err_vsi_setup;
6551                                 }
6552                         }
6553                 }
6554         }
6555
6556         i40e_pf_enable_irq0(hw);
6557
6558         return 0;
6559
6560 err_vsi_setup:
6561         for (i = 0; i < conf_vsis; i++)
6562                 if (pf->vmdq[i].vsi == NULL)
6563                         break;
6564                 else
6565                         i40e_vsi_release(pf->vmdq[i].vsi);
6566
6567         rte_free(pf->vmdq);
6568         pf->vmdq = NULL;
6569         i40e_pf_enable_irq0(hw);
6570         return err;
6571 }
6572
6573 static void
6574 i40e_stat_update_32(struct i40e_hw *hw,
6575                    uint32_t reg,
6576                    bool offset_loaded,
6577                    uint64_t *offset,
6578                    uint64_t *stat)
6579 {
6580         uint64_t new_data;
6581
6582         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6583         if (!offset_loaded)
6584                 *offset = new_data;
6585
6586         if (new_data >= *offset)
6587                 *stat = (uint64_t)(new_data - *offset);
6588         else
6589                 *stat = (uint64_t)((new_data +
6590                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6591 }
6592
6593 static void
6594 i40e_stat_update_48(struct i40e_hw *hw,
6595                    uint32_t hireg,
6596                    uint32_t loreg,
6597                    bool offset_loaded,
6598                    uint64_t *offset,
6599                    uint64_t *stat)
6600 {
6601         uint64_t new_data;
6602
6603         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6604         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6605                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6606
6607         if (!offset_loaded)
6608                 *offset = new_data;
6609
6610         if (new_data >= *offset)
6611                 *stat = new_data - *offset;
6612         else
6613                 *stat = (uint64_t)((new_data +
6614                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6615
6616         *stat &= I40E_48_BIT_MASK;
6617 }
6618
6619 /* Disable IRQ0 */
6620 void
6621 i40e_pf_disable_irq0(struct i40e_hw *hw)
6622 {
6623         /* Disable all interrupt types */
6624         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6625                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6626         I40E_WRITE_FLUSH(hw);
6627 }
6628
6629 /* Enable IRQ0 */
6630 void
6631 i40e_pf_enable_irq0(struct i40e_hw *hw)
6632 {
6633         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6634                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6635                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6636                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6637         I40E_WRITE_FLUSH(hw);
6638 }
6639
6640 static void
6641 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6642 {
6643         /* read pending request and disable first */
6644         i40e_pf_disable_irq0(hw);
6645         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6646         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6647                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6648
6649         if (no_queue)
6650                 /* Link no queues with irq0 */
6651                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6652                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6653 }
6654
6655 static void
6656 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6657 {
6658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6659         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6660         int i;
6661         uint16_t abs_vf_id;
6662         uint32_t index, offset, val;
6663
6664         if (!pf->vfs)
6665                 return;
6666         /**
6667          * Try to find which VF trigger a reset, use absolute VF id to access
6668          * since the reg is global register.
6669          */
6670         for (i = 0; i < pf->vf_num; i++) {
6671                 abs_vf_id = hw->func_caps.vf_base_id + i;
6672                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6673                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6674                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6675                 /* VFR event occurred */
6676                 if (val & (0x1 << offset)) {
6677                         int ret;
6678
6679                         /* Clear the event first */
6680                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6681                                                         (0x1 << offset));
6682                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6683                         /**
6684                          * Only notify a VF reset event occurred,
6685                          * don't trigger another SW reset
6686                          */
6687                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6688                         if (ret != I40E_SUCCESS)
6689                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6690                 }
6691         }
6692 }
6693
6694 static void
6695 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6696 {
6697         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6698         int i;
6699
6700         for (i = 0; i < pf->vf_num; i++)
6701                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6702 }
6703
6704 static void
6705 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6706 {
6707         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6708         struct i40e_arq_event_info info;
6709         uint16_t pending, opcode;
6710         int ret;
6711
6712         info.buf_len = I40E_AQ_BUF_SZ;
6713         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6714         if (!info.msg_buf) {
6715                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6716                 return;
6717         }
6718
6719         pending = 1;
6720         while (pending) {
6721                 ret = i40e_clean_arq_element(hw, &info, &pending);
6722
6723                 if (ret != I40E_SUCCESS) {
6724                         PMD_DRV_LOG(INFO,
6725                                 "Failed to read msg from AdminQ, aq_err: %u",
6726                                 hw->aq.asq_last_status);
6727                         break;
6728                 }
6729                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6730
6731                 switch (opcode) {
6732                 case i40e_aqc_opc_send_msg_to_pf:
6733                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6734                         i40e_pf_host_handle_vf_msg(dev,
6735                                         rte_le_to_cpu_16(info.desc.retval),
6736                                         rte_le_to_cpu_32(info.desc.cookie_high),
6737                                         rte_le_to_cpu_32(info.desc.cookie_low),
6738                                         info.msg_buf,
6739                                         info.msg_len);
6740                         break;
6741                 case i40e_aqc_opc_get_link_status:
6742                         ret = i40e_dev_link_update(dev, 0);
6743                         if (!ret)
6744                                 _rte_eth_dev_callback_process(dev,
6745                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6746                         break;
6747                 default:
6748                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6749                                     opcode);
6750                         break;
6751                 }
6752         }
6753         rte_free(info.msg_buf);
6754 }
6755
6756 /**
6757  * Interrupt handler triggered by NIC  for handling
6758  * specific interrupt.
6759  *
6760  * @param handle
6761  *  Pointer to interrupt handle.
6762  * @param param
6763  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6764  *
6765  * @return
6766  *  void
6767  */
6768 static void
6769 i40e_dev_interrupt_handler(void *param)
6770 {
6771         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6773         uint32_t icr0;
6774
6775         /* Disable interrupt */
6776         i40e_pf_disable_irq0(hw);
6777
6778         /* read out interrupt causes */
6779         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6780
6781         /* No interrupt event indicated */
6782         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6783                 PMD_DRV_LOG(INFO, "No interrupt event");
6784                 goto done;
6785         }
6786         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6787                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6788         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6789                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6790         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6791                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6792         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6793                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6794         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6795                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6796         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6797                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6798         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6799                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6800
6801         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6802                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6803                 i40e_dev_handle_vfr_event(dev);
6804         }
6805         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6806                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6807                 i40e_dev_handle_aq_msg(dev);
6808         }
6809
6810 done:
6811         /* Enable interrupt */
6812         i40e_pf_enable_irq0(hw);
6813 }
6814
6815 static void
6816 i40e_dev_alarm_handler(void *param)
6817 {
6818         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6819         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6820         uint32_t icr0;
6821
6822         /* Disable interrupt */
6823         i40e_pf_disable_irq0(hw);
6824
6825         /* read out interrupt causes */
6826         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6827
6828         /* No interrupt event indicated */
6829         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6830                 goto done;
6831         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6832                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6833         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6834                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6835         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6836                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6837         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6838                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6839         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6840                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6841         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6842                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6843         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6844                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6845
6846         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6847                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6848                 i40e_dev_handle_vfr_event(dev);
6849         }
6850         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6851                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6852                 i40e_dev_handle_aq_msg(dev);
6853         }
6854
6855 done:
6856         /* Enable interrupt */
6857         i40e_pf_enable_irq0(hw);
6858         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6859                           i40e_dev_alarm_handler, dev);
6860 }
6861
6862 int
6863 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6864                          struct i40e_macvlan_filter *filter,
6865                          int total)
6866 {
6867         int ele_num, ele_buff_size;
6868         int num, actual_num, i;
6869         uint16_t flags;
6870         int ret = I40E_SUCCESS;
6871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6872         struct i40e_aqc_add_macvlan_element_data *req_list;
6873
6874         if (filter == NULL  || total == 0)
6875                 return I40E_ERR_PARAM;
6876         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6877         ele_buff_size = hw->aq.asq_buf_size;
6878
6879         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6880         if (req_list == NULL) {
6881                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6882                 return I40E_ERR_NO_MEMORY;
6883         }
6884
6885         num = 0;
6886         do {
6887                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6888                 memset(req_list, 0, ele_buff_size);
6889
6890                 for (i = 0; i < actual_num; i++) {
6891                         rte_memcpy(req_list[i].mac_addr,
6892                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6893                         req_list[i].vlan_tag =
6894                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6895
6896                         switch (filter[num + i].filter_type) {
6897                         case RTE_MAC_PERFECT_MATCH:
6898                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6899                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6900                                 break;
6901                         case RTE_MACVLAN_PERFECT_MATCH:
6902                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6903                                 break;
6904                         case RTE_MAC_HASH_MATCH:
6905                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6906                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6907                                 break;
6908                         case RTE_MACVLAN_HASH_MATCH:
6909                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6910                                 break;
6911                         default:
6912                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6913                                 ret = I40E_ERR_PARAM;
6914                                 goto DONE;
6915                         }
6916
6917                         req_list[i].queue_number = 0;
6918
6919                         req_list[i].flags = rte_cpu_to_le_16(flags);
6920                 }
6921
6922                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6923                                                 actual_num, NULL);
6924                 if (ret != I40E_SUCCESS) {
6925                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6926                         goto DONE;
6927                 }
6928                 num += actual_num;
6929         } while (num < total);
6930
6931 DONE:
6932         rte_free(req_list);
6933         return ret;
6934 }
6935
6936 int
6937 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6938                             struct i40e_macvlan_filter *filter,
6939                             int total)
6940 {
6941         int ele_num, ele_buff_size;
6942         int num, actual_num, i;
6943         uint16_t flags;
6944         int ret = I40E_SUCCESS;
6945         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6946         struct i40e_aqc_remove_macvlan_element_data *req_list;
6947
6948         if (filter == NULL  || total == 0)
6949                 return I40E_ERR_PARAM;
6950
6951         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6952         ele_buff_size = hw->aq.asq_buf_size;
6953
6954         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6955         if (req_list == NULL) {
6956                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6957                 return I40E_ERR_NO_MEMORY;
6958         }
6959
6960         num = 0;
6961         do {
6962                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6963                 memset(req_list, 0, ele_buff_size);
6964
6965                 for (i = 0; i < actual_num; i++) {
6966                         rte_memcpy(req_list[i].mac_addr,
6967                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6968                         req_list[i].vlan_tag =
6969                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6970
6971                         switch (filter[num + i].filter_type) {
6972                         case RTE_MAC_PERFECT_MATCH:
6973                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6974                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6975                                 break;
6976                         case RTE_MACVLAN_PERFECT_MATCH:
6977                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6978                                 break;
6979                         case RTE_MAC_HASH_MATCH:
6980                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6981                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6982                                 break;
6983                         case RTE_MACVLAN_HASH_MATCH:
6984                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6985                                 break;
6986                         default:
6987                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6988                                 ret = I40E_ERR_PARAM;
6989                                 goto DONE;
6990                         }
6991                         req_list[i].flags = rte_cpu_to_le_16(flags);
6992                 }
6993
6994                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6995                                                 actual_num, NULL);
6996                 if (ret != I40E_SUCCESS) {
6997                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6998                         goto DONE;
6999                 }
7000                 num += actual_num;
7001         } while (num < total);
7002
7003 DONE:
7004         rte_free(req_list);
7005         return ret;
7006 }
7007
7008 /* Find out specific MAC filter */
7009 static struct i40e_mac_filter *
7010 i40e_find_mac_filter(struct i40e_vsi *vsi,
7011                          struct rte_ether_addr *macaddr)
7012 {
7013         struct i40e_mac_filter *f;
7014
7015         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7016                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7017                         return f;
7018         }
7019
7020         return NULL;
7021 }
7022
7023 static bool
7024 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7025                          uint16_t vlan_id)
7026 {
7027         uint32_t vid_idx, vid_bit;
7028
7029         if (vlan_id > ETH_VLAN_ID_MAX)
7030                 return 0;
7031
7032         vid_idx = I40E_VFTA_IDX(vlan_id);
7033         vid_bit = I40E_VFTA_BIT(vlan_id);
7034
7035         if (vsi->vfta[vid_idx] & vid_bit)
7036                 return 1;
7037         else
7038                 return 0;
7039 }
7040
7041 static void
7042 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7043                        uint16_t vlan_id, bool on)
7044 {
7045         uint32_t vid_idx, vid_bit;
7046
7047         vid_idx = I40E_VFTA_IDX(vlan_id);
7048         vid_bit = I40E_VFTA_BIT(vlan_id);
7049
7050         if (on)
7051                 vsi->vfta[vid_idx] |= vid_bit;
7052         else
7053                 vsi->vfta[vid_idx] &= ~vid_bit;
7054 }
7055
7056 void
7057 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7058                      uint16_t vlan_id, bool on)
7059 {
7060         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7061         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7062         int ret;
7063
7064         if (vlan_id > ETH_VLAN_ID_MAX)
7065                 return;
7066
7067         i40e_store_vlan_filter(vsi, vlan_id, on);
7068
7069         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7070                 return;
7071
7072         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7073
7074         if (on) {
7075                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7076                                        &vlan_data, 1, NULL);
7077                 if (ret != I40E_SUCCESS)
7078                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7079         } else {
7080                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7081                                           &vlan_data, 1, NULL);
7082                 if (ret != I40E_SUCCESS)
7083                         PMD_DRV_LOG(ERR,
7084                                     "Failed to remove vlan filter");
7085         }
7086 }
7087
7088 /**
7089  * Find all vlan options for specific mac addr,
7090  * return with actual vlan found.
7091  */
7092 int
7093 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7094                            struct i40e_macvlan_filter *mv_f,
7095                            int num, struct rte_ether_addr *addr)
7096 {
7097         int i;
7098         uint32_t j, k;
7099
7100         /**
7101          * Not to use i40e_find_vlan_filter to decrease the loop time,
7102          * although the code looks complex.
7103           */
7104         if (num < vsi->vlan_num)
7105                 return I40E_ERR_PARAM;
7106
7107         i = 0;
7108         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7109                 if (vsi->vfta[j]) {
7110                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7111                                 if (vsi->vfta[j] & (1 << k)) {
7112                                         if (i > num - 1) {
7113                                                 PMD_DRV_LOG(ERR,
7114                                                         "vlan number doesn't match");
7115                                                 return I40E_ERR_PARAM;
7116                                         }
7117                                         rte_memcpy(&mv_f[i].macaddr,
7118                                                         addr, ETH_ADDR_LEN);
7119                                         mv_f[i].vlan_id =
7120                                                 j * I40E_UINT32_BIT_SIZE + k;
7121                                         i++;
7122                                 }
7123                         }
7124                 }
7125         }
7126         return I40E_SUCCESS;
7127 }
7128
7129 static inline int
7130 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7131                            struct i40e_macvlan_filter *mv_f,
7132                            int num,
7133                            uint16_t vlan)
7134 {
7135         int i = 0;
7136         struct i40e_mac_filter *f;
7137
7138         if (num < vsi->mac_num)
7139                 return I40E_ERR_PARAM;
7140
7141         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7142                 if (i > num - 1) {
7143                         PMD_DRV_LOG(ERR, "buffer number not match");
7144                         return I40E_ERR_PARAM;
7145                 }
7146                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7147                                 ETH_ADDR_LEN);
7148                 mv_f[i].vlan_id = vlan;
7149                 mv_f[i].filter_type = f->mac_info.filter_type;
7150                 i++;
7151         }
7152
7153         return I40E_SUCCESS;
7154 }
7155
7156 static int
7157 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7158 {
7159         int i, j, num;
7160         struct i40e_mac_filter *f;
7161         struct i40e_macvlan_filter *mv_f;
7162         int ret = I40E_SUCCESS;
7163
7164         if (vsi == NULL || vsi->mac_num == 0)
7165                 return I40E_ERR_PARAM;
7166
7167         /* Case that no vlan is set */
7168         if (vsi->vlan_num == 0)
7169                 num = vsi->mac_num;
7170         else
7171                 num = vsi->mac_num * vsi->vlan_num;
7172
7173         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7174         if (mv_f == NULL) {
7175                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7176                 return I40E_ERR_NO_MEMORY;
7177         }
7178
7179         i = 0;
7180         if (vsi->vlan_num == 0) {
7181                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7182                         rte_memcpy(&mv_f[i].macaddr,
7183                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7184                         mv_f[i].filter_type = f->mac_info.filter_type;
7185                         mv_f[i].vlan_id = 0;
7186                         i++;
7187                 }
7188         } else {
7189                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7190                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7191                                         vsi->vlan_num, &f->mac_info.mac_addr);
7192                         if (ret != I40E_SUCCESS)
7193                                 goto DONE;
7194                         for (j = i; j < i + vsi->vlan_num; j++)
7195                                 mv_f[j].filter_type = f->mac_info.filter_type;
7196                         i += vsi->vlan_num;
7197                 }
7198         }
7199
7200         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7201 DONE:
7202         rte_free(mv_f);
7203
7204         return ret;
7205 }
7206
7207 int
7208 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7209 {
7210         struct i40e_macvlan_filter *mv_f;
7211         int mac_num;
7212         int ret = I40E_SUCCESS;
7213
7214         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7215                 return I40E_ERR_PARAM;
7216
7217         /* If it's already set, just return */
7218         if (i40e_find_vlan_filter(vsi,vlan))
7219                 return I40E_SUCCESS;
7220
7221         mac_num = vsi->mac_num;
7222
7223         if (mac_num == 0) {
7224                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7225                 return I40E_ERR_PARAM;
7226         }
7227
7228         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7229
7230         if (mv_f == NULL) {
7231                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7232                 return I40E_ERR_NO_MEMORY;
7233         }
7234
7235         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7236
7237         if (ret != I40E_SUCCESS)
7238                 goto DONE;
7239
7240         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7241
7242         if (ret != I40E_SUCCESS)
7243                 goto DONE;
7244
7245         i40e_set_vlan_filter(vsi, vlan, 1);
7246
7247         vsi->vlan_num++;
7248         ret = I40E_SUCCESS;
7249 DONE:
7250         rte_free(mv_f);
7251         return ret;
7252 }
7253
7254 int
7255 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7256 {
7257         struct i40e_macvlan_filter *mv_f;
7258         int mac_num;
7259         int ret = I40E_SUCCESS;
7260
7261         /**
7262          * Vlan 0 is the generic filter for untagged packets
7263          * and can't be removed.
7264          */
7265         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7266                 return I40E_ERR_PARAM;
7267
7268         /* If can't find it, just return */
7269         if (!i40e_find_vlan_filter(vsi, vlan))
7270                 return I40E_ERR_PARAM;
7271
7272         mac_num = vsi->mac_num;
7273
7274         if (mac_num == 0) {
7275                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7276                 return I40E_ERR_PARAM;
7277         }
7278
7279         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7280
7281         if (mv_f == NULL) {
7282                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7283                 return I40E_ERR_NO_MEMORY;
7284         }
7285
7286         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7287
7288         if (ret != I40E_SUCCESS)
7289                 goto DONE;
7290
7291         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7292
7293         if (ret != I40E_SUCCESS)
7294                 goto DONE;
7295
7296         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7297         if (vsi->vlan_num == 1) {
7298                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7299                 if (ret != I40E_SUCCESS)
7300                         goto DONE;
7301
7302                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7303                 if (ret != I40E_SUCCESS)
7304                         goto DONE;
7305         }
7306
7307         i40e_set_vlan_filter(vsi, vlan, 0);
7308
7309         vsi->vlan_num--;
7310         ret = I40E_SUCCESS;
7311 DONE:
7312         rte_free(mv_f);
7313         return ret;
7314 }
7315
7316 int
7317 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7318 {
7319         struct i40e_mac_filter *f;
7320         struct i40e_macvlan_filter *mv_f;
7321         int i, vlan_num = 0;
7322         int ret = I40E_SUCCESS;
7323
7324         /* If it's add and we've config it, return */
7325         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7326         if (f != NULL)
7327                 return I40E_SUCCESS;
7328         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7329                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7330
7331                 /**
7332                  * If vlan_num is 0, that's the first time to add mac,
7333                  * set mask for vlan_id 0.
7334                  */
7335                 if (vsi->vlan_num == 0) {
7336                         i40e_set_vlan_filter(vsi, 0, 1);
7337                         vsi->vlan_num = 1;
7338                 }
7339                 vlan_num = vsi->vlan_num;
7340         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7341                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7342                 vlan_num = 1;
7343
7344         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7345         if (mv_f == NULL) {
7346                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7347                 return I40E_ERR_NO_MEMORY;
7348         }
7349
7350         for (i = 0; i < vlan_num; i++) {
7351                 mv_f[i].filter_type = mac_filter->filter_type;
7352                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7353                                 ETH_ADDR_LEN);
7354         }
7355
7356         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7357                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7358                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7359                                         &mac_filter->mac_addr);
7360                 if (ret != I40E_SUCCESS)
7361                         goto DONE;
7362         }
7363
7364         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7365         if (ret != I40E_SUCCESS)
7366                 goto DONE;
7367
7368         /* Add the mac addr into mac list */
7369         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7370         if (f == NULL) {
7371                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7372                 ret = I40E_ERR_NO_MEMORY;
7373                 goto DONE;
7374         }
7375         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7376                         ETH_ADDR_LEN);
7377         f->mac_info.filter_type = mac_filter->filter_type;
7378         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7379         vsi->mac_num++;
7380
7381         ret = I40E_SUCCESS;
7382 DONE:
7383         rte_free(mv_f);
7384
7385         return ret;
7386 }
7387
7388 int
7389 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7390 {
7391         struct i40e_mac_filter *f;
7392         struct i40e_macvlan_filter *mv_f;
7393         int i, vlan_num;
7394         enum rte_mac_filter_type filter_type;
7395         int ret = I40E_SUCCESS;
7396
7397         /* Can't find it, return an error */
7398         f = i40e_find_mac_filter(vsi, addr);
7399         if (f == NULL)
7400                 return I40E_ERR_PARAM;
7401
7402         vlan_num = vsi->vlan_num;
7403         filter_type = f->mac_info.filter_type;
7404         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7405                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7406                 if (vlan_num == 0) {
7407                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7408                         return I40E_ERR_PARAM;
7409                 }
7410         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7411                         filter_type == RTE_MAC_HASH_MATCH)
7412                 vlan_num = 1;
7413
7414         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7415         if (mv_f == NULL) {
7416                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7417                 return I40E_ERR_NO_MEMORY;
7418         }
7419
7420         for (i = 0; i < vlan_num; i++) {
7421                 mv_f[i].filter_type = filter_type;
7422                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7423                                 ETH_ADDR_LEN);
7424         }
7425         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7426                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7427                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7428                 if (ret != I40E_SUCCESS)
7429                         goto DONE;
7430         }
7431
7432         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7433         if (ret != I40E_SUCCESS)
7434                 goto DONE;
7435
7436         /* Remove the mac addr into mac list */
7437         TAILQ_REMOVE(&vsi->mac_list, f, next);
7438         rte_free(f);
7439         vsi->mac_num--;
7440
7441         ret = I40E_SUCCESS;
7442 DONE:
7443         rte_free(mv_f);
7444         return ret;
7445 }
7446
7447 /* Configure hash enable flags for RSS */
7448 uint64_t
7449 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7450 {
7451         uint64_t hena = 0;
7452         int i;
7453
7454         if (!flags)
7455                 return hena;
7456
7457         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7458                 if (flags & (1ULL << i))
7459                         hena |= adapter->pctypes_tbl[i];
7460         }
7461
7462         return hena;
7463 }
7464
7465 /* Parse the hash enable flags */
7466 uint64_t
7467 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7468 {
7469         uint64_t rss_hf = 0;
7470
7471         if (!flags)
7472                 return rss_hf;
7473         int i;
7474
7475         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7476                 if (flags & adapter->pctypes_tbl[i])
7477                         rss_hf |= (1ULL << i);
7478         }
7479         return rss_hf;
7480 }
7481
7482 /* Disable RSS */
7483 static void
7484 i40e_pf_disable_rss(struct i40e_pf *pf)
7485 {
7486         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7487
7488         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7489         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7490         I40E_WRITE_FLUSH(hw);
7491 }
7492
7493 int
7494 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7495 {
7496         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7497         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7498         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7499                            I40E_VFQF_HKEY_MAX_INDEX :
7500                            I40E_PFQF_HKEY_MAX_INDEX;
7501         int ret = 0;
7502
7503         if (!key || key_len == 0) {
7504                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7505                 return 0;
7506         } else if (key_len != (key_idx + 1) *
7507                 sizeof(uint32_t)) {
7508                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7509                 return -EINVAL;
7510         }
7511
7512         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7513                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7514                         (struct i40e_aqc_get_set_rss_key_data *)key;
7515
7516                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7517                 if (ret)
7518                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7519         } else {
7520                 uint32_t *hash_key = (uint32_t *)key;
7521                 uint16_t i;
7522
7523                 if (vsi->type == I40E_VSI_SRIOV) {
7524                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7525                                 I40E_WRITE_REG(
7526                                         hw,
7527                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7528                                         hash_key[i]);
7529
7530                 } else {
7531                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7532                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7533                                                hash_key[i]);
7534                 }
7535                 I40E_WRITE_FLUSH(hw);
7536         }
7537
7538         return ret;
7539 }
7540
7541 static int
7542 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7543 {
7544         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7545         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7546         uint32_t reg;
7547         int ret;
7548
7549         if (!key || !key_len)
7550                 return 0;
7551
7552         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7553                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7554                         (struct i40e_aqc_get_set_rss_key_data *)key);
7555                 if (ret) {
7556                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7557                         return ret;
7558                 }
7559         } else {
7560                 uint32_t *key_dw = (uint32_t *)key;
7561                 uint16_t i;
7562
7563                 if (vsi->type == I40E_VSI_SRIOV) {
7564                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7565                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7566                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7567                         }
7568                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7569                                    sizeof(uint32_t);
7570                 } else {
7571                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7572                                 reg = I40E_PFQF_HKEY(i);
7573                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7574                         }
7575                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7576                                    sizeof(uint32_t);
7577                 }
7578         }
7579         return 0;
7580 }
7581
7582 static int
7583 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7584 {
7585         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7586         uint64_t hena;
7587         int ret;
7588
7589         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7590                                rss_conf->rss_key_len);
7591         if (ret)
7592                 return ret;
7593
7594         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7595         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7596         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7597         I40E_WRITE_FLUSH(hw);
7598
7599         return 0;
7600 }
7601
7602 static int
7603 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7604                          struct rte_eth_rss_conf *rss_conf)
7605 {
7606         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7607         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7608         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7609         uint64_t hena;
7610
7611         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7612         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7613
7614         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7615                 if (rss_hf != 0) /* Enable RSS */
7616                         return -EINVAL;
7617                 return 0; /* Nothing to do */
7618         }
7619         /* RSS enabled */
7620         if (rss_hf == 0) /* Disable RSS */
7621                 return -EINVAL;
7622
7623         return i40e_hw_rss_hash_set(pf, rss_conf);
7624 }
7625
7626 static int
7627 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7628                            struct rte_eth_rss_conf *rss_conf)
7629 {
7630         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7631         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7632         uint64_t hena;
7633         int ret;
7634
7635         if (!rss_conf)
7636                 return -EINVAL;
7637
7638         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7639                          &rss_conf->rss_key_len);
7640         if (ret)
7641                 return ret;
7642
7643         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7644         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7645         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7646
7647         return 0;
7648 }
7649
7650 static int
7651 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7652 {
7653         switch (filter_type) {
7654         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7655                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7656                 break;
7657         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7658                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7659                 break;
7660         case RTE_TUNNEL_FILTER_IMAC_TENID:
7661                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7662                 break;
7663         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7664                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7665                 break;
7666         case ETH_TUNNEL_FILTER_IMAC:
7667                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7668                 break;
7669         case ETH_TUNNEL_FILTER_OIP:
7670                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7671                 break;
7672         case ETH_TUNNEL_FILTER_IIP:
7673                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7674                 break;
7675         default:
7676                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7677                 return -EINVAL;
7678         }
7679
7680         return 0;
7681 }
7682
7683 /* Convert tunnel filter structure */
7684 static int
7685 i40e_tunnel_filter_convert(
7686         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7687         struct i40e_tunnel_filter *tunnel_filter)
7688 {
7689         rte_ether_addr_copy((struct rte_ether_addr *)
7690                         &cld_filter->element.outer_mac,
7691                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7692         rte_ether_addr_copy((struct rte_ether_addr *)
7693                         &cld_filter->element.inner_mac,
7694                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7695         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7696         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7697              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7698             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7699                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7700         else
7701                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7702         tunnel_filter->input.flags = cld_filter->element.flags;
7703         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7704         tunnel_filter->queue = cld_filter->element.queue_number;
7705         rte_memcpy(tunnel_filter->input.general_fields,
7706                    cld_filter->general_fields,
7707                    sizeof(cld_filter->general_fields));
7708
7709         return 0;
7710 }
7711
7712 /* Check if there exists the tunnel filter */
7713 struct i40e_tunnel_filter *
7714 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7715                              const struct i40e_tunnel_filter_input *input)
7716 {
7717         int ret;
7718
7719         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7720         if (ret < 0)
7721                 return NULL;
7722
7723         return tunnel_rule->hash_map[ret];
7724 }
7725
7726 /* Add a tunnel filter into the SW list */
7727 static int
7728 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7729                              struct i40e_tunnel_filter *tunnel_filter)
7730 {
7731         struct i40e_tunnel_rule *rule = &pf->tunnel;
7732         int ret;
7733
7734         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7735         if (ret < 0) {
7736                 PMD_DRV_LOG(ERR,
7737                             "Failed to insert tunnel filter to hash table %d!",
7738                             ret);
7739                 return ret;
7740         }
7741         rule->hash_map[ret] = tunnel_filter;
7742
7743         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7744
7745         return 0;
7746 }
7747
7748 /* Delete a tunnel filter from the SW list */
7749 int
7750 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7751                           struct i40e_tunnel_filter_input *input)
7752 {
7753         struct i40e_tunnel_rule *rule = &pf->tunnel;
7754         struct i40e_tunnel_filter *tunnel_filter;
7755         int ret;
7756
7757         ret = rte_hash_del_key(rule->hash_table, input);
7758         if (ret < 0) {
7759                 PMD_DRV_LOG(ERR,
7760                             "Failed to delete tunnel filter to hash table %d!",
7761                             ret);
7762                 return ret;
7763         }
7764         tunnel_filter = rule->hash_map[ret];
7765         rule->hash_map[ret] = NULL;
7766
7767         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7768         rte_free(tunnel_filter);
7769
7770         return 0;
7771 }
7772
7773 int
7774 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7775                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7776                         uint8_t add)
7777 {
7778         uint16_t ip_type;
7779         uint32_t ipv4_addr, ipv4_addr_le;
7780         uint8_t i, tun_type = 0;
7781         /* internal varialbe to convert ipv6 byte order */
7782         uint32_t convert_ipv6[4];
7783         int val, ret = 0;
7784         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7785         struct i40e_vsi *vsi = pf->main_vsi;
7786         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7787         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7788         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7789         struct i40e_tunnel_filter *tunnel, *node;
7790         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7791
7792         cld_filter = rte_zmalloc("tunnel_filter",
7793                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7794         0);
7795
7796         if (NULL == cld_filter) {
7797                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7798                 return -ENOMEM;
7799         }
7800         pfilter = cld_filter;
7801
7802         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7803                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7804         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7805                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7806
7807         pfilter->element.inner_vlan =
7808                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7809         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7810                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7811                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7812                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7813                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7814                                 &ipv4_addr_le,
7815                                 sizeof(pfilter->element.ipaddr.v4.data));
7816         } else {
7817                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7818                 for (i = 0; i < 4; i++) {
7819                         convert_ipv6[i] =
7820                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7821                 }
7822                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7823                            &convert_ipv6,
7824                            sizeof(pfilter->element.ipaddr.v6.data));
7825         }
7826
7827         /* check tunneled type */
7828         switch (tunnel_filter->tunnel_type) {
7829         case RTE_TUNNEL_TYPE_VXLAN:
7830                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7831                 break;
7832         case RTE_TUNNEL_TYPE_NVGRE:
7833                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7834                 break;
7835         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7836                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7837                 break;
7838         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7839                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7840                 break;
7841         default:
7842                 /* Other tunnel types is not supported. */
7843                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7844                 rte_free(cld_filter);
7845                 return -EINVAL;
7846         }
7847
7848         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7849                                        &pfilter->element.flags);
7850         if (val < 0) {
7851                 rte_free(cld_filter);
7852                 return -EINVAL;
7853         }
7854
7855         pfilter->element.flags |= rte_cpu_to_le_16(
7856                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7857                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7858         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7859         pfilter->element.queue_number =
7860                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7861
7862         /* Check if there is the filter in SW list */
7863         memset(&check_filter, 0, sizeof(check_filter));
7864         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7865         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7866         if (add && node) {
7867                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7868                 rte_free(cld_filter);
7869                 return -EINVAL;
7870         }
7871
7872         if (!add && !node) {
7873                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7874                 rte_free(cld_filter);
7875                 return -EINVAL;
7876         }
7877
7878         if (add) {
7879                 ret = i40e_aq_add_cloud_filters(hw,
7880                                         vsi->seid, &cld_filter->element, 1);
7881                 if (ret < 0) {
7882                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7883                         rte_free(cld_filter);
7884                         return -ENOTSUP;
7885                 }
7886                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7887                 if (tunnel == NULL) {
7888                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7889                         rte_free(cld_filter);
7890                         return -ENOMEM;
7891                 }
7892
7893                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7894                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7895                 if (ret < 0)
7896                         rte_free(tunnel);
7897         } else {
7898                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7899                                                    &cld_filter->element, 1);
7900                 if (ret < 0) {
7901                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7902                         rte_free(cld_filter);
7903                         return -ENOTSUP;
7904                 }
7905                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7906         }
7907
7908         rte_free(cld_filter);
7909         return ret;
7910 }
7911
7912 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7913 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7914 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7915 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7916 #define I40E_TR_GRE_KEY_MASK                    0x400
7917 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7918 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7919
7920 static enum
7921 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7922 {
7923         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7924         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7925         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7926         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7927         enum i40e_status_code status = I40E_SUCCESS;
7928
7929         if (pf->support_multi_driver) {
7930                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7931                 return I40E_NOT_SUPPORTED;
7932         }
7933
7934         memset(&filter_replace, 0,
7935                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7936         memset(&filter_replace_buf, 0,
7937                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7938
7939         /* create L1 filter */
7940         filter_replace.old_filter_type =
7941                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7942         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7943         filter_replace.tr_bit = 0;
7944
7945         /* Prepare the buffer, 3 entries */
7946         filter_replace_buf.data[0] =
7947                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7948         filter_replace_buf.data[0] |=
7949                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7950         filter_replace_buf.data[2] = 0xFF;
7951         filter_replace_buf.data[3] = 0xFF;
7952         filter_replace_buf.data[4] =
7953                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7954         filter_replace_buf.data[4] |=
7955                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7956         filter_replace_buf.data[7] = 0xF0;
7957         filter_replace_buf.data[8]
7958                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7959         filter_replace_buf.data[8] |=
7960                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7961         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7962                 I40E_TR_GENEVE_KEY_MASK |
7963                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7964         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7965                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7966                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7967
7968         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7969                                                &filter_replace_buf);
7970         if (!status && (filter_replace.old_filter_type !=
7971                         filter_replace.new_filter_type))
7972                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7973                             " original: 0x%x, new: 0x%x",
7974                             dev->device->name,
7975                             filter_replace.old_filter_type,
7976                             filter_replace.new_filter_type);
7977
7978         return status;
7979 }
7980
7981 static enum
7982 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7983 {
7984         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7985         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7986         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7987         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7988         enum i40e_status_code status = I40E_SUCCESS;
7989
7990         if (pf->support_multi_driver) {
7991                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7992                 return I40E_NOT_SUPPORTED;
7993         }
7994
7995         /* For MPLSoUDP */
7996         memset(&filter_replace, 0,
7997                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7998         memset(&filter_replace_buf, 0,
7999                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8000         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8001                 I40E_AQC_MIRROR_CLOUD_FILTER;
8002         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8003         filter_replace.new_filter_type =
8004                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8005         /* Prepare the buffer, 2 entries */
8006         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8007         filter_replace_buf.data[0] |=
8008                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8009         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8010         filter_replace_buf.data[4] |=
8011                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8012         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8013                                                &filter_replace_buf);
8014         if (status < 0)
8015                 return status;
8016         if (filter_replace.old_filter_type !=
8017             filter_replace.new_filter_type)
8018                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8019                             " original: 0x%x, new: 0x%x",
8020                             dev->device->name,
8021                             filter_replace.old_filter_type,
8022                             filter_replace.new_filter_type);
8023
8024         /* For MPLSoGRE */
8025         memset(&filter_replace, 0,
8026                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8027         memset(&filter_replace_buf, 0,
8028                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8029
8030         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8031                 I40E_AQC_MIRROR_CLOUD_FILTER;
8032         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8033         filter_replace.new_filter_type =
8034                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8035         /* Prepare the buffer, 2 entries */
8036         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8037         filter_replace_buf.data[0] |=
8038                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8039         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8040         filter_replace_buf.data[4] |=
8041                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8042
8043         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8044                                                &filter_replace_buf);
8045         if (!status && (filter_replace.old_filter_type !=
8046                         filter_replace.new_filter_type))
8047                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8048                             " original: 0x%x, new: 0x%x",
8049                             dev->device->name,
8050                             filter_replace.old_filter_type,
8051                             filter_replace.new_filter_type);
8052
8053         return status;
8054 }
8055
8056 static enum i40e_status_code
8057 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8058 {
8059         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8060         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8061         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8062         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8063         enum i40e_status_code status = I40E_SUCCESS;
8064
8065         if (pf->support_multi_driver) {
8066                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8067                 return I40E_NOT_SUPPORTED;
8068         }
8069
8070         /* For GTP-C */
8071         memset(&filter_replace, 0,
8072                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8073         memset(&filter_replace_buf, 0,
8074                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8075         /* create L1 filter */
8076         filter_replace.old_filter_type =
8077                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8078         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8079         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8080                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8081         /* Prepare the buffer, 2 entries */
8082         filter_replace_buf.data[0] =
8083                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8084         filter_replace_buf.data[0] |=
8085                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8086         filter_replace_buf.data[2] = 0xFF;
8087         filter_replace_buf.data[3] = 0xFF;
8088         filter_replace_buf.data[4] =
8089                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8090         filter_replace_buf.data[4] |=
8091                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8092         filter_replace_buf.data[6] = 0xFF;
8093         filter_replace_buf.data[7] = 0xFF;
8094         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8095                                                &filter_replace_buf);
8096         if (status < 0)
8097                 return status;
8098         if (filter_replace.old_filter_type !=
8099             filter_replace.new_filter_type)
8100                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8101                             " original: 0x%x, new: 0x%x",
8102                             dev->device->name,
8103                             filter_replace.old_filter_type,
8104                             filter_replace.new_filter_type);
8105
8106         /* for GTP-U */
8107         memset(&filter_replace, 0,
8108                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8109         memset(&filter_replace_buf, 0,
8110                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8111         /* create L1 filter */
8112         filter_replace.old_filter_type =
8113                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8114         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8115         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8116                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8117         /* Prepare the buffer, 2 entries */
8118         filter_replace_buf.data[0] =
8119                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8120         filter_replace_buf.data[0] |=
8121                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8122         filter_replace_buf.data[2] = 0xFF;
8123         filter_replace_buf.data[3] = 0xFF;
8124         filter_replace_buf.data[4] =
8125                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8126         filter_replace_buf.data[4] |=
8127                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8128         filter_replace_buf.data[6] = 0xFF;
8129         filter_replace_buf.data[7] = 0xFF;
8130
8131         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8132                                                &filter_replace_buf);
8133         if (!status && (filter_replace.old_filter_type !=
8134                         filter_replace.new_filter_type))
8135                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8136                             " original: 0x%x, new: 0x%x",
8137                             dev->device->name,
8138                             filter_replace.old_filter_type,
8139                             filter_replace.new_filter_type);
8140
8141         return status;
8142 }
8143
8144 static enum
8145 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8146 {
8147         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8148         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8149         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8150         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8151         enum i40e_status_code status = I40E_SUCCESS;
8152
8153         if (pf->support_multi_driver) {
8154                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8155                 return I40E_NOT_SUPPORTED;
8156         }
8157
8158         /* for GTP-C */
8159         memset(&filter_replace, 0,
8160                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8161         memset(&filter_replace_buf, 0,
8162                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8163         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8164         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8165         filter_replace.new_filter_type =
8166                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8167         /* Prepare the buffer, 2 entries */
8168         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8169         filter_replace_buf.data[0] |=
8170                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8171         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8172         filter_replace_buf.data[4] |=
8173                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8174         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8175                                                &filter_replace_buf);
8176         if (status < 0)
8177                 return status;
8178         if (filter_replace.old_filter_type !=
8179             filter_replace.new_filter_type)
8180                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8181                             " original: 0x%x, new: 0x%x",
8182                             dev->device->name,
8183                             filter_replace.old_filter_type,
8184                             filter_replace.new_filter_type);
8185
8186         /* for GTP-U */
8187         memset(&filter_replace, 0,
8188                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8189         memset(&filter_replace_buf, 0,
8190                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8191         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8192         filter_replace.old_filter_type =
8193                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8194         filter_replace.new_filter_type =
8195                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8196         /* Prepare the buffer, 2 entries */
8197         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8198         filter_replace_buf.data[0] |=
8199                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8200         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8201         filter_replace_buf.data[4] |=
8202                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8203
8204         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8205                                                &filter_replace_buf);
8206         if (!status && (filter_replace.old_filter_type !=
8207                         filter_replace.new_filter_type))
8208                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8209                             " original: 0x%x, new: 0x%x",
8210                             dev->device->name,
8211                             filter_replace.old_filter_type,
8212                             filter_replace.new_filter_type);
8213
8214         return status;
8215 }
8216
8217 int
8218 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8219                       struct i40e_tunnel_filter_conf *tunnel_filter,
8220                       uint8_t add)
8221 {
8222         uint16_t ip_type;
8223         uint32_t ipv4_addr, ipv4_addr_le;
8224         uint8_t i, tun_type = 0;
8225         /* internal variable to convert ipv6 byte order */
8226         uint32_t convert_ipv6[4];
8227         int val, ret = 0;
8228         struct i40e_pf_vf *vf = NULL;
8229         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8230         struct i40e_vsi *vsi;
8231         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8232         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8233         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8234         struct i40e_tunnel_filter *tunnel, *node;
8235         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8236         uint32_t teid_le;
8237         bool big_buffer = 0;
8238
8239         cld_filter = rte_zmalloc("tunnel_filter",
8240                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8241                          0);
8242
8243         if (cld_filter == NULL) {
8244                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8245                 return -ENOMEM;
8246         }
8247         pfilter = cld_filter;
8248
8249         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8250                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8251         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8252                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8253
8254         pfilter->element.inner_vlan =
8255                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8256         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8257                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8258                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8259                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8260                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8261                                 &ipv4_addr_le,
8262                                 sizeof(pfilter->element.ipaddr.v4.data));
8263         } else {
8264                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8265                 for (i = 0; i < 4; i++) {
8266                         convert_ipv6[i] =
8267                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8268                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8269                 }
8270                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8271                            &convert_ipv6,
8272                            sizeof(pfilter->element.ipaddr.v6.data));
8273         }
8274
8275         /* check tunneled type */
8276         switch (tunnel_filter->tunnel_type) {
8277         case I40E_TUNNEL_TYPE_VXLAN:
8278                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8279                 break;
8280         case I40E_TUNNEL_TYPE_NVGRE:
8281                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8282                 break;
8283         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8284                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8285                 break;
8286         case I40E_TUNNEL_TYPE_MPLSoUDP:
8287                 if (!pf->mpls_replace_flag) {
8288                         i40e_replace_mpls_l1_filter(pf);
8289                         i40e_replace_mpls_cloud_filter(pf);
8290                         pf->mpls_replace_flag = 1;
8291                 }
8292                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8293                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8294                         teid_le >> 4;
8295                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8296                         (teid_le & 0xF) << 12;
8297                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8298                         0x40;
8299                 big_buffer = 1;
8300                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8301                 break;
8302         case I40E_TUNNEL_TYPE_MPLSoGRE:
8303                 if (!pf->mpls_replace_flag) {
8304                         i40e_replace_mpls_l1_filter(pf);
8305                         i40e_replace_mpls_cloud_filter(pf);
8306                         pf->mpls_replace_flag = 1;
8307                 }
8308                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8309                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8310                         teid_le >> 4;
8311                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8312                         (teid_le & 0xF) << 12;
8313                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8314                         0x0;
8315                 big_buffer = 1;
8316                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8317                 break;
8318         case I40E_TUNNEL_TYPE_GTPC:
8319                 if (!pf->gtp_replace_flag) {
8320                         i40e_replace_gtp_l1_filter(pf);
8321                         i40e_replace_gtp_cloud_filter(pf);
8322                         pf->gtp_replace_flag = 1;
8323                 }
8324                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8325                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8326                         (teid_le >> 16) & 0xFFFF;
8327                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8328                         teid_le & 0xFFFF;
8329                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8330                         0x0;
8331                 big_buffer = 1;
8332                 break;
8333         case I40E_TUNNEL_TYPE_GTPU:
8334                 if (!pf->gtp_replace_flag) {
8335                         i40e_replace_gtp_l1_filter(pf);
8336                         i40e_replace_gtp_cloud_filter(pf);
8337                         pf->gtp_replace_flag = 1;
8338                 }
8339                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8340                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8341                         (teid_le >> 16) & 0xFFFF;
8342                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8343                         teid_le & 0xFFFF;
8344                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8345                         0x0;
8346                 big_buffer = 1;
8347                 break;
8348         case I40E_TUNNEL_TYPE_QINQ:
8349                 if (!pf->qinq_replace_flag) {
8350                         ret = i40e_cloud_filter_qinq_create(pf);
8351                         if (ret < 0)
8352                                 PMD_DRV_LOG(DEBUG,
8353                                             "QinQ tunnel filter already created.");
8354                         pf->qinq_replace_flag = 1;
8355                 }
8356                 /*      Add in the General fields the values of
8357                  *      the Outer and Inner VLAN
8358                  *      Big Buffer should be set, see changes in
8359                  *      i40e_aq_add_cloud_filters
8360                  */
8361                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8362                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8363                 big_buffer = 1;
8364                 break;
8365         default:
8366                 /* Other tunnel types is not supported. */
8367                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8368                 rte_free(cld_filter);
8369                 return -EINVAL;
8370         }
8371
8372         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8373                 pfilter->element.flags =
8374                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8375         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8376                 pfilter->element.flags =
8377                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8378         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8379                 pfilter->element.flags =
8380                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8381         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8382                 pfilter->element.flags =
8383                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8384         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8385                 pfilter->element.flags |=
8386                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8387         else {
8388                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8389                                                 &pfilter->element.flags);
8390                 if (val < 0) {
8391                         rte_free(cld_filter);
8392                         return -EINVAL;
8393                 }
8394         }
8395
8396         pfilter->element.flags |= rte_cpu_to_le_16(
8397                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8398                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8399         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8400         pfilter->element.queue_number =
8401                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8402
8403         if (!tunnel_filter->is_to_vf)
8404                 vsi = pf->main_vsi;
8405         else {
8406                 if (tunnel_filter->vf_id >= pf->vf_num) {
8407                         PMD_DRV_LOG(ERR, "Invalid argument.");
8408                         rte_free(cld_filter);
8409                         return -EINVAL;
8410                 }
8411                 vf = &pf->vfs[tunnel_filter->vf_id];
8412                 vsi = vf->vsi;
8413         }
8414
8415         /* Check if there is the filter in SW list */
8416         memset(&check_filter, 0, sizeof(check_filter));
8417         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8418         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8419         check_filter.vf_id = tunnel_filter->vf_id;
8420         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8421         if (add && node) {
8422                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8423                 rte_free(cld_filter);
8424                 return -EINVAL;
8425         }
8426
8427         if (!add && !node) {
8428                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8429                 rte_free(cld_filter);
8430                 return -EINVAL;
8431         }
8432
8433         if (add) {
8434                 if (big_buffer)
8435                         ret = i40e_aq_add_cloud_filters_bb(hw,
8436                                                    vsi->seid, cld_filter, 1);
8437                 else
8438                         ret = i40e_aq_add_cloud_filters(hw,
8439                                         vsi->seid, &cld_filter->element, 1);
8440                 if (ret < 0) {
8441                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8442                         rte_free(cld_filter);
8443                         return -ENOTSUP;
8444                 }
8445                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8446                 if (tunnel == NULL) {
8447                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8448                         rte_free(cld_filter);
8449                         return -ENOMEM;
8450                 }
8451
8452                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8453                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8454                 if (ret < 0)
8455                         rte_free(tunnel);
8456         } else {
8457                 if (big_buffer)
8458                         ret = i40e_aq_rem_cloud_filters_bb(
8459                                 hw, vsi->seid, cld_filter, 1);
8460                 else
8461                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8462                                                 &cld_filter->element, 1);
8463                 if (ret < 0) {
8464                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8465                         rte_free(cld_filter);
8466                         return -ENOTSUP;
8467                 }
8468                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8469         }
8470
8471         rte_free(cld_filter);
8472         return ret;
8473 }
8474
8475 static int
8476 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8477 {
8478         uint8_t i;
8479
8480         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8481                 if (pf->vxlan_ports[i] == port)
8482                         return i;
8483         }
8484
8485         return -1;
8486 }
8487
8488 static int
8489 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8490 {
8491         int  idx, ret;
8492         uint8_t filter_idx = 0;
8493         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8494
8495         idx = i40e_get_vxlan_port_idx(pf, port);
8496
8497         /* Check if port already exists */
8498         if (idx >= 0) {
8499                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8500                 return -EINVAL;
8501         }
8502
8503         /* Now check if there is space to add the new port */
8504         idx = i40e_get_vxlan_port_idx(pf, 0);
8505         if (idx < 0) {
8506                 PMD_DRV_LOG(ERR,
8507                         "Maximum number of UDP ports reached, not adding port %d",
8508                         port);
8509                 return -ENOSPC;
8510         }
8511
8512         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8513                                         &filter_idx, NULL);
8514         if (ret < 0) {
8515                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8516                 return -1;
8517         }
8518
8519         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8520                          port,  filter_idx);
8521
8522         /* New port: add it and mark its index in the bitmap */
8523         pf->vxlan_ports[idx] = port;
8524         pf->vxlan_bitmap |= (1 << idx);
8525
8526         if (!(pf->flags & I40E_FLAG_VXLAN))
8527                 pf->flags |= I40E_FLAG_VXLAN;
8528
8529         return 0;
8530 }
8531
8532 static int
8533 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8534 {
8535         int idx;
8536         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8537
8538         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8539                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8540                 return -EINVAL;
8541         }
8542
8543         idx = i40e_get_vxlan_port_idx(pf, port);
8544
8545         if (idx < 0) {
8546                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8547                 return -EINVAL;
8548         }
8549
8550         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8551                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8552                 return -1;
8553         }
8554
8555         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8556                         port, idx);
8557
8558         pf->vxlan_ports[idx] = 0;
8559         pf->vxlan_bitmap &= ~(1 << idx);
8560
8561         if (!pf->vxlan_bitmap)
8562                 pf->flags &= ~I40E_FLAG_VXLAN;
8563
8564         return 0;
8565 }
8566
8567 /* Add UDP tunneling port */
8568 static int
8569 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8570                              struct rte_eth_udp_tunnel *udp_tunnel)
8571 {
8572         int ret = 0;
8573         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8574
8575         if (udp_tunnel == NULL)
8576                 return -EINVAL;
8577
8578         switch (udp_tunnel->prot_type) {
8579         case RTE_TUNNEL_TYPE_VXLAN:
8580                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8581                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8582                 break;
8583         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8584                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8585                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8586                 break;
8587         case RTE_TUNNEL_TYPE_GENEVE:
8588         case RTE_TUNNEL_TYPE_TEREDO:
8589                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8590                 ret = -1;
8591                 break;
8592
8593         default:
8594                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8595                 ret = -1;
8596                 break;
8597         }
8598
8599         return ret;
8600 }
8601
8602 /* Remove UDP tunneling port */
8603 static int
8604 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8605                              struct rte_eth_udp_tunnel *udp_tunnel)
8606 {
8607         int ret = 0;
8608         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8609
8610         if (udp_tunnel == NULL)
8611                 return -EINVAL;
8612
8613         switch (udp_tunnel->prot_type) {
8614         case RTE_TUNNEL_TYPE_VXLAN:
8615         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8616                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8617                 break;
8618         case RTE_TUNNEL_TYPE_GENEVE:
8619         case RTE_TUNNEL_TYPE_TEREDO:
8620                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8621                 ret = -1;
8622                 break;
8623         default:
8624                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8625                 ret = -1;
8626                 break;
8627         }
8628
8629         return ret;
8630 }
8631
8632 /* Calculate the maximum number of contiguous PF queues that are configured */
8633 static int
8634 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8635 {
8636         struct rte_eth_dev_data *data = pf->dev_data;
8637         int i, num;
8638         struct i40e_rx_queue *rxq;
8639
8640         num = 0;
8641         for (i = 0; i < pf->lan_nb_qps; i++) {
8642                 rxq = data->rx_queues[i];
8643                 if (rxq && rxq->q_set)
8644                         num++;
8645                 else
8646                         break;
8647         }
8648
8649         return num;
8650 }
8651
8652 /* Configure RSS */
8653 static int
8654 i40e_pf_config_rss(struct i40e_pf *pf)
8655 {
8656         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8657         struct rte_eth_rss_conf rss_conf;
8658         uint32_t i, lut = 0;
8659         uint16_t j, num;
8660
8661         /*
8662          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8663          * It's necessary to calculate the actual PF queues that are configured.
8664          */
8665         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8666                 num = i40e_pf_calc_configured_queues_num(pf);
8667         else
8668                 num = pf->dev_data->nb_rx_queues;
8669
8670         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8671         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8672                         num);
8673
8674         if (num == 0) {
8675                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8676                 return -ENOTSUP;
8677         }
8678
8679         if (pf->adapter->rss_reta_updated == 0) {
8680                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8681                         if (j == num)
8682                                 j = 0;
8683                         lut = (lut << 8) | (j & ((0x1 <<
8684                                 hw->func_caps.rss_table_entry_width) - 1));
8685                         if ((i & 3) == 3)
8686                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8687                                                rte_bswap32(lut));
8688                 }
8689         }
8690
8691         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8692         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8693                 i40e_pf_disable_rss(pf);
8694                 return 0;
8695         }
8696         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8697                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8698                 /* Random default keys */
8699                 static uint32_t rss_key_default[] = {0x6b793944,
8700                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8701                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8702                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8703
8704                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8705                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8706                                                         sizeof(uint32_t);
8707         }
8708
8709         return i40e_hw_rss_hash_set(pf, &rss_conf);
8710 }
8711
8712 static int
8713 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8714                                struct rte_eth_tunnel_filter_conf *filter)
8715 {
8716         if (pf == NULL || filter == NULL) {
8717                 PMD_DRV_LOG(ERR, "Invalid parameter");
8718                 return -EINVAL;
8719         }
8720
8721         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8722                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8723                 return -EINVAL;
8724         }
8725
8726         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8727                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8728                 return -EINVAL;
8729         }
8730
8731         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8732                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8733                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8734                 return -EINVAL;
8735         }
8736
8737         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8738                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8739                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8740                 return -EINVAL;
8741         }
8742
8743         return 0;
8744 }
8745
8746 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8747 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8748 static int
8749 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8750 {
8751         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8752         uint32_t val, reg;
8753         int ret = -EINVAL;
8754
8755         if (pf->support_multi_driver) {
8756                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8757                 return -ENOTSUP;
8758         }
8759
8760         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8761         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8762
8763         if (len == 3) {
8764                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8765         } else if (len == 4) {
8766                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8767         } else {
8768                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8769                 return ret;
8770         }
8771
8772         if (reg != val) {
8773                 ret = i40e_aq_debug_write_global_register(hw,
8774                                                    I40E_GL_PRS_FVBM(2),
8775                                                    reg, NULL);
8776                 if (ret != 0)
8777                         return ret;
8778                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8779                             "with value 0x%08x",
8780                             I40E_GL_PRS_FVBM(2), reg);
8781         } else {
8782                 ret = 0;
8783         }
8784         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8785                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8786
8787         return ret;
8788 }
8789
8790 static int
8791 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8792 {
8793         int ret = -EINVAL;
8794
8795         if (!hw || !cfg)
8796                 return -EINVAL;
8797
8798         switch (cfg->cfg_type) {
8799         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8800                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8801                 break;
8802         default:
8803                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8804                 break;
8805         }
8806
8807         return ret;
8808 }
8809
8810 static int
8811 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8812                                enum rte_filter_op filter_op,
8813                                void *arg)
8814 {
8815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8816         int ret = I40E_ERR_PARAM;
8817
8818         switch (filter_op) {
8819         case RTE_ETH_FILTER_SET:
8820                 ret = i40e_dev_global_config_set(hw,
8821                         (struct rte_eth_global_cfg *)arg);
8822                 break;
8823         default:
8824                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8825                 break;
8826         }
8827
8828         return ret;
8829 }
8830
8831 static int
8832 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8833                           enum rte_filter_op filter_op,
8834                           void *arg)
8835 {
8836         struct rte_eth_tunnel_filter_conf *filter;
8837         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8838         int ret = I40E_SUCCESS;
8839
8840         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8841
8842         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8843                 return I40E_ERR_PARAM;
8844
8845         switch (filter_op) {
8846         case RTE_ETH_FILTER_NOP:
8847                 if (!(pf->flags & I40E_FLAG_VXLAN))
8848                         ret = I40E_NOT_SUPPORTED;
8849                 break;
8850         case RTE_ETH_FILTER_ADD:
8851                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8852                 break;
8853         case RTE_ETH_FILTER_DELETE:
8854                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8855                 break;
8856         default:
8857                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8858                 ret = I40E_ERR_PARAM;
8859                 break;
8860         }
8861
8862         return ret;
8863 }
8864
8865 static int
8866 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8867 {
8868         int ret = 0;
8869         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8870
8871         /* RSS setup */
8872         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8873                 ret = i40e_pf_config_rss(pf);
8874         else
8875                 i40e_pf_disable_rss(pf);
8876
8877         return ret;
8878 }
8879
8880 /* Get the symmetric hash enable configurations per port */
8881 static void
8882 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8883 {
8884         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8885
8886         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8887 }
8888
8889 /* Set the symmetric hash enable configurations per port */
8890 static void
8891 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8892 {
8893         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8894
8895         if (enable > 0) {
8896                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8897                         PMD_DRV_LOG(INFO,
8898                                 "Symmetric hash has already been enabled");
8899                         return;
8900                 }
8901                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8902         } else {
8903                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8904                         PMD_DRV_LOG(INFO,
8905                                 "Symmetric hash has already been disabled");
8906                         return;
8907                 }
8908                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8909         }
8910         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8911         I40E_WRITE_FLUSH(hw);
8912 }
8913
8914 /*
8915  * Get global configurations of hash function type and symmetric hash enable
8916  * per flow type (pctype). Note that global configuration means it affects all
8917  * the ports on the same NIC.
8918  */
8919 static int
8920 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8921                                    struct rte_eth_hash_global_conf *g_cfg)
8922 {
8923         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8924         uint32_t reg;
8925         uint16_t i, j;
8926
8927         memset(g_cfg, 0, sizeof(*g_cfg));
8928         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8929         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8930                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8931         else
8932                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8933         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8934                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8935
8936         /*
8937          * As i40e supports less than 64 flow types, only first 64 bits need to
8938          * be checked.
8939          */
8940         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8941                 g_cfg->valid_bit_mask[i] = 0ULL;
8942                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8943         }
8944
8945         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8946
8947         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8948                 if (!adapter->pctypes_tbl[i])
8949                         continue;
8950                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8951                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8952                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8953                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8954                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8955                                         g_cfg->sym_hash_enable_mask[0] |=
8956                                                                 (1ULL << i);
8957                                 }
8958                         }
8959                 }
8960         }
8961
8962         return 0;
8963 }
8964
8965 static int
8966 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8967                               const struct rte_eth_hash_global_conf *g_cfg)
8968 {
8969         uint32_t i;
8970         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8971
8972         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8973                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8974                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8975                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8976                                                 g_cfg->hash_func);
8977                 return -EINVAL;
8978         }
8979
8980         /*
8981          * As i40e supports less than 64 flow types, only first 64 bits need to
8982          * be checked.
8983          */
8984         mask0 = g_cfg->valid_bit_mask[0];
8985         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8986                 if (i == 0) {
8987                         /* Check if any unsupported flow type configured */
8988                         if ((mask0 | i40e_mask) ^ i40e_mask)
8989                                 goto mask_err;
8990                 } else {
8991                         if (g_cfg->valid_bit_mask[i])
8992                                 goto mask_err;
8993                 }
8994         }
8995
8996         return 0;
8997
8998 mask_err:
8999         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9000
9001         return -EINVAL;
9002 }
9003
9004 /*
9005  * Set global configurations of hash function type and symmetric hash enable
9006  * per flow type (pctype). Note any modifying global configuration will affect
9007  * all the ports on the same NIC.
9008  */
9009 static int
9010 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9011                                    struct rte_eth_hash_global_conf *g_cfg)
9012 {
9013         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9014         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9015         int ret;
9016         uint16_t i, j;
9017         uint32_t reg;
9018         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9019
9020         if (pf->support_multi_driver) {
9021                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9022                 return -ENOTSUP;
9023         }
9024
9025         /* Check the input parameters */
9026         ret = i40e_hash_global_config_check(adapter, g_cfg);
9027         if (ret < 0)
9028                 return ret;
9029
9030         /*
9031          * As i40e supports less than 64 flow types, only first 64 bits need to
9032          * be configured.
9033          */
9034         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9035                 if (mask0 & (1UL << i)) {
9036                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9037                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9038
9039                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9040                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9041                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9042                                         i40e_write_global_rx_ctl(hw,
9043                                                           I40E_GLQF_HSYM(j),
9044                                                           reg);
9045                         }
9046                 }
9047         }
9048
9049         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9050         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9051                 /* Toeplitz */
9052                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9053                         PMD_DRV_LOG(DEBUG,
9054                                 "Hash function already set to Toeplitz");
9055                         goto out;
9056                 }
9057                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9058         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9059                 /* Simple XOR */
9060                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9061                         PMD_DRV_LOG(DEBUG,
9062                                 "Hash function already set to Simple XOR");
9063                         goto out;
9064                 }
9065                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9066         } else
9067                 /* Use the default, and keep it as it is */
9068                 goto out;
9069
9070         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9071
9072 out:
9073         I40E_WRITE_FLUSH(hw);
9074
9075         return 0;
9076 }
9077
9078 /**
9079  * Valid input sets for hash and flow director filters per PCTYPE
9080  */
9081 static uint64_t
9082 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9083                 enum rte_filter_type filter)
9084 {
9085         uint64_t valid;
9086
9087         static const uint64_t valid_hash_inset_table[] = {
9088                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9089                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9090                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9091                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9092                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9093                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9094                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9095                         I40E_INSET_FLEX_PAYLOAD,
9096                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9097                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9098                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9099                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9100                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9101                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9102                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9103                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9104                         I40E_INSET_FLEX_PAYLOAD,
9105                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9106                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9107                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9108                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9109                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9110                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9111                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9112                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9113                         I40E_INSET_FLEX_PAYLOAD,
9114                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9115                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9116                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9117                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9118                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9119                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9120                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9121                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9122                         I40E_INSET_FLEX_PAYLOAD,
9123                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9124                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9125                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9126                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9127                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9128                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9129                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9130                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9131                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9132                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9133                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9134                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9135                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9136                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9137                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9138                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9139                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9140                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9141                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9142                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9143                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9144                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9145                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9146                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9147                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9148                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9149                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9150                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9151                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9152                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9153                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9154                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9155                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9156                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9157                         I40E_INSET_FLEX_PAYLOAD,
9158                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9159                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9160                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9161                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9162                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9163                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9164                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9165                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9166                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9167                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9168                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9169                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9170                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9171                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9172                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9173                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9174                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9175                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9176                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9177                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9178                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9179                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9180                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9181                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9182                         I40E_INSET_FLEX_PAYLOAD,
9183                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9184                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9185                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9186                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9187                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9188                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9189                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9190                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9191                         I40E_INSET_FLEX_PAYLOAD,
9192                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9193                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9194                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9195                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9196                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9197                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9198                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9199                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9200                         I40E_INSET_FLEX_PAYLOAD,
9201                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9202                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9203                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9204                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9205                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9206                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9207                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9208                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9209                         I40E_INSET_FLEX_PAYLOAD,
9210                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9211                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9212                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9213                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9214                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9215                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9216                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9217                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9218                         I40E_INSET_FLEX_PAYLOAD,
9219                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9220                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9221                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9222                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9223                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9224                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9225                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9226                         I40E_INSET_FLEX_PAYLOAD,
9227                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9228                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9229                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9230                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9231                         I40E_INSET_FLEX_PAYLOAD,
9232         };
9233
9234         /**
9235          * Flow director supports only fields defined in
9236          * union rte_eth_fdir_flow.
9237          */
9238         static const uint64_t valid_fdir_inset_table[] = {
9239                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9240                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9241                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9242                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9243                 I40E_INSET_IPV4_TTL,
9244                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9245                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9246                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9247                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9248                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9249                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9250                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9251                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9252                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9253                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9254                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9255                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9256                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9257                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9258                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9259                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9260                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9261                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9262                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9263                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9264                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9265                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9266                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9267                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9268                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9269                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9270                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9271                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9272                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9273                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9274                 I40E_INSET_SCTP_VT,
9275                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9276                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9277                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9278                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9279                 I40E_INSET_IPV4_TTL,
9280                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9281                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9282                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9283                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9284                 I40E_INSET_IPV6_HOP_LIMIT,
9285                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9286                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9287                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9288                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9289                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9290                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9291                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9292                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9293                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9294                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9295                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9296                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9297                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9298                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9299                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9300                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9301                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9302                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9303                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9304                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9305                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9306                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9307                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9308                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9309                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9310                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9311                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9312                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9313                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9314                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9315                 I40E_INSET_SCTP_VT,
9316                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9317                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9318                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9319                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9320                 I40E_INSET_IPV6_HOP_LIMIT,
9321                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9322                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9323                 I40E_INSET_LAST_ETHER_TYPE,
9324         };
9325
9326         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9327                 return 0;
9328         if (filter == RTE_ETH_FILTER_HASH)
9329                 valid = valid_hash_inset_table[pctype];
9330         else
9331                 valid = valid_fdir_inset_table[pctype];
9332
9333         return valid;
9334 }
9335
9336 /**
9337  * Validate if the input set is allowed for a specific PCTYPE
9338  */
9339 int
9340 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9341                 enum rte_filter_type filter, uint64_t inset)
9342 {
9343         uint64_t valid;
9344
9345         valid = i40e_get_valid_input_set(pctype, filter);
9346         if (inset & (~valid))
9347                 return -EINVAL;
9348
9349         return 0;
9350 }
9351
9352 /* default input set fields combination per pctype */
9353 uint64_t
9354 i40e_get_default_input_set(uint16_t pctype)
9355 {
9356         static const uint64_t default_inset_table[] = {
9357                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9358                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9359                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9360                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9361                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9362                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9363                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9364                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9365                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9366                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9367                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9368                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9369                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9370                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9371                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9372                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9373                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9374                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9375                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9376                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9377                         I40E_INSET_SCTP_VT,
9378                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9379                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9380                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9381                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9382                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9383                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9384                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9385                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9386                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9387                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9388                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9389                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9390                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9391                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9392                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9393                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9394                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9395                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9396                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9397                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9398                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9399                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9400                         I40E_INSET_SCTP_VT,
9401                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9402                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9403                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9404                         I40E_INSET_LAST_ETHER_TYPE,
9405         };
9406
9407         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9408                 return 0;
9409
9410         return default_inset_table[pctype];
9411 }
9412
9413 /**
9414  * Parse the input set from index to logical bit masks
9415  */
9416 static int
9417 i40e_parse_input_set(uint64_t *inset,
9418                      enum i40e_filter_pctype pctype,
9419                      enum rte_eth_input_set_field *field,
9420                      uint16_t size)
9421 {
9422         uint16_t i, j;
9423         int ret = -EINVAL;
9424
9425         static const struct {
9426                 enum rte_eth_input_set_field field;
9427                 uint64_t inset;
9428         } inset_convert_table[] = {
9429                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9430                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9431                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9432                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9433                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9434                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9435                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9436                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9437                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9438                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9439                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9440                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9441                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9442                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9443                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9444                         I40E_INSET_IPV6_NEXT_HDR},
9445                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9446                         I40E_INSET_IPV6_HOP_LIMIT},
9447                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9448                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9449                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9450                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9451                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9452                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9453                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9454                         I40E_INSET_SCTP_VT},
9455                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9456                         I40E_INSET_TUNNEL_DMAC},
9457                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9458                         I40E_INSET_VLAN_TUNNEL},
9459                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9460                         I40E_INSET_TUNNEL_ID},
9461                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9462                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9463                         I40E_INSET_FLEX_PAYLOAD_W1},
9464                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9465                         I40E_INSET_FLEX_PAYLOAD_W2},
9466                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9467                         I40E_INSET_FLEX_PAYLOAD_W3},
9468                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9469                         I40E_INSET_FLEX_PAYLOAD_W4},
9470                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9471                         I40E_INSET_FLEX_PAYLOAD_W5},
9472                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9473                         I40E_INSET_FLEX_PAYLOAD_W6},
9474                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9475                         I40E_INSET_FLEX_PAYLOAD_W7},
9476                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9477                         I40E_INSET_FLEX_PAYLOAD_W8},
9478         };
9479
9480         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9481                 return ret;
9482
9483         /* Only one item allowed for default or all */
9484         if (size == 1) {
9485                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9486                         *inset = i40e_get_default_input_set(pctype);
9487                         return 0;
9488                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9489                         *inset = I40E_INSET_NONE;
9490                         return 0;
9491                 }
9492         }
9493
9494         for (i = 0, *inset = 0; i < size; i++) {
9495                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9496                         if (field[i] == inset_convert_table[j].field) {
9497                                 *inset |= inset_convert_table[j].inset;
9498                                 break;
9499                         }
9500                 }
9501
9502                 /* It contains unsupported input set, return immediately */
9503                 if (j == RTE_DIM(inset_convert_table))
9504                         return ret;
9505         }
9506
9507         return 0;
9508 }
9509
9510 /**
9511  * Translate the input set from bit masks to register aware bit masks
9512  * and vice versa
9513  */
9514 uint64_t
9515 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9516 {
9517         uint64_t val = 0;
9518         uint16_t i;
9519
9520         struct inset_map {
9521                 uint64_t inset;
9522                 uint64_t inset_reg;
9523         };
9524
9525         static const struct inset_map inset_map_common[] = {
9526                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9527                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9528                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9529                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9530                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9531                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9532                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9533                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9534                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9535                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9536                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9537                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9538                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9539                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9540                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9541                 {I40E_INSET_TUNNEL_DMAC,
9542                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9543                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9544                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9545                 {I40E_INSET_TUNNEL_SRC_PORT,
9546                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9547                 {I40E_INSET_TUNNEL_DST_PORT,
9548                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9549                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9550                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9551                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9552                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9553                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9554                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9555                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9556                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9557                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9558         };
9559
9560     /* some different registers map in x722*/
9561         static const struct inset_map inset_map_diff_x722[] = {
9562                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9563                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9564                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9565                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9566         };
9567
9568         static const struct inset_map inset_map_diff_not_x722[] = {
9569                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9570                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9571                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9572                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9573         };
9574
9575         if (input == 0)
9576                 return val;
9577
9578         /* Translate input set to register aware inset */
9579         if (type == I40E_MAC_X722) {
9580                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9581                         if (input & inset_map_diff_x722[i].inset)
9582                                 val |= inset_map_diff_x722[i].inset_reg;
9583                 }
9584         } else {
9585                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9586                         if (input & inset_map_diff_not_x722[i].inset)
9587                                 val |= inset_map_diff_not_x722[i].inset_reg;
9588                 }
9589         }
9590
9591         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9592                 if (input & inset_map_common[i].inset)
9593                         val |= inset_map_common[i].inset_reg;
9594         }
9595
9596         return val;
9597 }
9598
9599 int
9600 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9601 {
9602         uint8_t i, idx = 0;
9603         uint64_t inset_need_mask = inset;
9604
9605         static const struct {
9606                 uint64_t inset;
9607                 uint32_t mask;
9608         } inset_mask_map[] = {
9609                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9610                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9611                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9612                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9613                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9614                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9615                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9616                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9617         };
9618
9619         if (!inset || !mask || !nb_elem)
9620                 return 0;
9621
9622         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9623                 /* Clear the inset bit, if no MASK is required,
9624                  * for example proto + ttl
9625                  */
9626                 if ((inset & inset_mask_map[i].inset) ==
9627                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9628                         inset_need_mask &= ~inset_mask_map[i].inset;
9629                 if (!inset_need_mask)
9630                         return 0;
9631         }
9632         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9633                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9634                     inset_mask_map[i].inset) {
9635                         if (idx >= nb_elem) {
9636                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9637                                 return -EINVAL;
9638                         }
9639                         mask[idx] = inset_mask_map[i].mask;
9640                         idx++;
9641                 }
9642         }
9643
9644         return idx;
9645 }
9646
9647 void
9648 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9649 {
9650         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9651
9652         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9653         if (reg != val)
9654                 i40e_write_rx_ctl(hw, addr, val);
9655         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9656                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9657 }
9658
9659 void
9660 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9661 {
9662         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9663         struct rte_eth_dev *dev;
9664
9665         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9666         if (reg != val) {
9667                 i40e_write_rx_ctl(hw, addr, val);
9668                 PMD_DRV_LOG(WARNING,
9669                             "i40e device %s changed global register [0x%08x]."
9670                             " original: 0x%08x, new: 0x%08x",
9671                             dev->device->name, addr, reg,
9672                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9673         }
9674 }
9675
9676 static void
9677 i40e_filter_input_set_init(struct i40e_pf *pf)
9678 {
9679         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9680         enum i40e_filter_pctype pctype;
9681         uint64_t input_set, inset_reg;
9682         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9683         int num, i;
9684         uint16_t flow_type;
9685
9686         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9687              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9688                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9689
9690                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9691                         continue;
9692
9693                 input_set = i40e_get_default_input_set(pctype);
9694
9695                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9696                                                    I40E_INSET_MASK_NUM_REG);
9697                 if (num < 0)
9698                         return;
9699                 if (pf->support_multi_driver && num > 0) {
9700                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9701                         return;
9702                 }
9703                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9704                                         input_set);
9705
9706                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9707                                       (uint32_t)(inset_reg & UINT32_MAX));
9708                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9709                                      (uint32_t)((inset_reg >>
9710                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9711                 if (!pf->support_multi_driver) {
9712                         i40e_check_write_global_reg(hw,
9713                                             I40E_GLQF_HASH_INSET(0, pctype),
9714                                             (uint32_t)(inset_reg & UINT32_MAX));
9715                         i40e_check_write_global_reg(hw,
9716                                              I40E_GLQF_HASH_INSET(1, pctype),
9717                                              (uint32_t)((inset_reg >>
9718                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9719
9720                         for (i = 0; i < num; i++) {
9721                                 i40e_check_write_global_reg(hw,
9722                                                     I40E_GLQF_FD_MSK(i, pctype),
9723                                                     mask_reg[i]);
9724                                 i40e_check_write_global_reg(hw,
9725                                                   I40E_GLQF_HASH_MSK(i, pctype),
9726                                                   mask_reg[i]);
9727                         }
9728                         /*clear unused mask registers of the pctype */
9729                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9730                                 i40e_check_write_global_reg(hw,
9731                                                     I40E_GLQF_FD_MSK(i, pctype),
9732                                                     0);
9733                                 i40e_check_write_global_reg(hw,
9734                                                   I40E_GLQF_HASH_MSK(i, pctype),
9735                                                   0);
9736                         }
9737                 } else {
9738                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9739                 }
9740                 I40E_WRITE_FLUSH(hw);
9741
9742                 /* store the default input set */
9743                 if (!pf->support_multi_driver)
9744                         pf->hash_input_set[pctype] = input_set;
9745                 pf->fdir.input_set[pctype] = input_set;
9746         }
9747 }
9748
9749 int
9750 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9751                          struct rte_eth_input_set_conf *conf)
9752 {
9753         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9754         enum i40e_filter_pctype pctype;
9755         uint64_t input_set, inset_reg = 0;
9756         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9757         int ret, i, num;
9758
9759         if (!conf) {
9760                 PMD_DRV_LOG(ERR, "Invalid pointer");
9761                 return -EFAULT;
9762         }
9763         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9764             conf->op != RTE_ETH_INPUT_SET_ADD) {
9765                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9766                 return -EINVAL;
9767         }
9768
9769         if (pf->support_multi_driver) {
9770                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9771                 return -ENOTSUP;
9772         }
9773
9774         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9775         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9776                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9777                 return -EINVAL;
9778         }
9779
9780         if (hw->mac.type == I40E_MAC_X722) {
9781                 /* get translated pctype value in fd pctype register */
9782                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9783                         I40E_GLQF_FD_PCTYPES((int)pctype));
9784         }
9785
9786         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9787                                    conf->inset_size);
9788         if (ret) {
9789                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9790                 return -EINVAL;
9791         }
9792
9793         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9794                 /* get inset value in register */
9795                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9796                 inset_reg <<= I40E_32_BIT_WIDTH;
9797                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9798                 input_set |= pf->hash_input_set[pctype];
9799         }
9800         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9801                                            I40E_INSET_MASK_NUM_REG);
9802         if (num < 0)
9803                 return -EINVAL;
9804
9805         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9806
9807         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9808                                     (uint32_t)(inset_reg & UINT32_MAX));
9809         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9810                                     (uint32_t)((inset_reg >>
9811                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9812
9813         for (i = 0; i < num; i++)
9814                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9815                                             mask_reg[i]);
9816         /*clear unused mask registers of the pctype */
9817         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9818                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9819                                             0);
9820         I40E_WRITE_FLUSH(hw);
9821
9822         pf->hash_input_set[pctype] = input_set;
9823         return 0;
9824 }
9825
9826 int
9827 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9828                          struct rte_eth_input_set_conf *conf)
9829 {
9830         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9831         enum i40e_filter_pctype pctype;
9832         uint64_t input_set, inset_reg = 0;
9833         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9834         int ret, i, num;
9835
9836         if (!hw || !conf) {
9837                 PMD_DRV_LOG(ERR, "Invalid pointer");
9838                 return -EFAULT;
9839         }
9840         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9841             conf->op != RTE_ETH_INPUT_SET_ADD) {
9842                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9843                 return -EINVAL;
9844         }
9845
9846         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9847
9848         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9849                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9850                 return -EINVAL;
9851         }
9852
9853         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9854                                    conf->inset_size);
9855         if (ret) {
9856                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9857                 return -EINVAL;
9858         }
9859
9860         /* get inset value in register */
9861         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9862         inset_reg <<= I40E_32_BIT_WIDTH;
9863         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9864
9865         /* Can not change the inset reg for flex payload for fdir,
9866          * it is done by writing I40E_PRTQF_FD_FLXINSET
9867          * in i40e_set_flex_mask_on_pctype.
9868          */
9869         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9870                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9871         else
9872                 input_set |= pf->fdir.input_set[pctype];
9873         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9874                                            I40E_INSET_MASK_NUM_REG);
9875         if (num < 0)
9876                 return -EINVAL;
9877         if (pf->support_multi_driver && num > 0) {
9878                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9879                 return -ENOTSUP;
9880         }
9881
9882         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9883
9884         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9885                               (uint32_t)(inset_reg & UINT32_MAX));
9886         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9887                              (uint32_t)((inset_reg >>
9888                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9889
9890         if (!pf->support_multi_driver) {
9891                 for (i = 0; i < num; i++)
9892                         i40e_check_write_global_reg(hw,
9893                                                     I40E_GLQF_FD_MSK(i, pctype),
9894                                                     mask_reg[i]);
9895                 /*clear unused mask registers of the pctype */
9896                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9897                         i40e_check_write_global_reg(hw,
9898                                                     I40E_GLQF_FD_MSK(i, pctype),
9899                                                     0);
9900         } else {
9901                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9902         }
9903         I40E_WRITE_FLUSH(hw);
9904
9905         pf->fdir.input_set[pctype] = input_set;
9906         return 0;
9907 }
9908
9909 static int
9910 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9911 {
9912         int ret = 0;
9913
9914         if (!hw || !info) {
9915                 PMD_DRV_LOG(ERR, "Invalid pointer");
9916                 return -EFAULT;
9917         }
9918
9919         switch (info->info_type) {
9920         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9921                 i40e_get_symmetric_hash_enable_per_port(hw,
9922                                         &(info->info.enable));
9923                 break;
9924         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9925                 ret = i40e_get_hash_filter_global_config(hw,
9926                                 &(info->info.global_conf));
9927                 break;
9928         default:
9929                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9930                                                         info->info_type);
9931                 ret = -EINVAL;
9932                 break;
9933         }
9934
9935         return ret;
9936 }
9937
9938 static int
9939 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9940 {
9941         int ret = 0;
9942
9943         if (!hw || !info) {
9944                 PMD_DRV_LOG(ERR, "Invalid pointer");
9945                 return -EFAULT;
9946         }
9947
9948         switch (info->info_type) {
9949         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9950                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9951                 break;
9952         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9953                 ret = i40e_set_hash_filter_global_config(hw,
9954                                 &(info->info.global_conf));
9955                 break;
9956         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9957                 ret = i40e_hash_filter_inset_select(hw,
9958                                                &(info->info.input_set_conf));
9959                 break;
9960
9961         default:
9962                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9963                                                         info->info_type);
9964                 ret = -EINVAL;
9965                 break;
9966         }
9967
9968         return ret;
9969 }
9970
9971 /* Operations for hash function */
9972 static int
9973 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9974                       enum rte_filter_op filter_op,
9975                       void *arg)
9976 {
9977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9978         int ret = 0;
9979
9980         switch (filter_op) {
9981         case RTE_ETH_FILTER_NOP:
9982                 break;
9983         case RTE_ETH_FILTER_GET:
9984                 ret = i40e_hash_filter_get(hw,
9985                         (struct rte_eth_hash_filter_info *)arg);
9986                 break;
9987         case RTE_ETH_FILTER_SET:
9988                 ret = i40e_hash_filter_set(hw,
9989                         (struct rte_eth_hash_filter_info *)arg);
9990                 break;
9991         default:
9992                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9993                                                                 filter_op);
9994                 ret = -ENOTSUP;
9995                 break;
9996         }
9997
9998         return ret;
9999 }
10000
10001 /* Convert ethertype filter structure */
10002 static int
10003 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10004                               struct i40e_ethertype_filter *filter)
10005 {
10006         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10007                 RTE_ETHER_ADDR_LEN);
10008         filter->input.ether_type = input->ether_type;
10009         filter->flags = input->flags;
10010         filter->queue = input->queue;
10011
10012         return 0;
10013 }
10014
10015 /* Check if there exists the ehtertype filter */
10016 struct i40e_ethertype_filter *
10017 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10018                                 const struct i40e_ethertype_filter_input *input)
10019 {
10020         int ret;
10021
10022         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10023         if (ret < 0)
10024                 return NULL;
10025
10026         return ethertype_rule->hash_map[ret];
10027 }
10028
10029 /* Add ethertype filter in SW list */
10030 static int
10031 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10032                                 struct i40e_ethertype_filter *filter)
10033 {
10034         struct i40e_ethertype_rule *rule = &pf->ethertype;
10035         int ret;
10036
10037         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10038         if (ret < 0) {
10039                 PMD_DRV_LOG(ERR,
10040                             "Failed to insert ethertype filter"
10041                             " to hash table %d!",
10042                             ret);
10043                 return ret;
10044         }
10045         rule->hash_map[ret] = filter;
10046
10047         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10048
10049         return 0;
10050 }
10051
10052 /* Delete ethertype filter in SW list */
10053 int
10054 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10055                              struct i40e_ethertype_filter_input *input)
10056 {
10057         struct i40e_ethertype_rule *rule = &pf->ethertype;
10058         struct i40e_ethertype_filter *filter;
10059         int ret;
10060
10061         ret = rte_hash_del_key(rule->hash_table, input);
10062         if (ret < 0) {
10063                 PMD_DRV_LOG(ERR,
10064                             "Failed to delete ethertype filter"
10065                             " to hash table %d!",
10066                             ret);
10067                 return ret;
10068         }
10069         filter = rule->hash_map[ret];
10070         rule->hash_map[ret] = NULL;
10071
10072         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10073         rte_free(filter);
10074
10075         return 0;
10076 }
10077
10078 /*
10079  * Configure ethertype filter, which can director packet by filtering
10080  * with mac address and ether_type or only ether_type
10081  */
10082 int
10083 i40e_ethertype_filter_set(struct i40e_pf *pf,
10084                         struct rte_eth_ethertype_filter *filter,
10085                         bool add)
10086 {
10087         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10088         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10089         struct i40e_ethertype_filter *ethertype_filter, *node;
10090         struct i40e_ethertype_filter check_filter;
10091         struct i40e_control_filter_stats stats;
10092         uint16_t flags = 0;
10093         int ret;
10094
10095         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10096                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10097                 return -EINVAL;
10098         }
10099         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10100                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10101                 PMD_DRV_LOG(ERR,
10102                         "unsupported ether_type(0x%04x) in control packet filter.",
10103                         filter->ether_type);
10104                 return -EINVAL;
10105         }
10106         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10107                 PMD_DRV_LOG(WARNING,
10108                         "filter vlan ether_type in first tag is not supported.");
10109
10110         /* Check if there is the filter in SW list */
10111         memset(&check_filter, 0, sizeof(check_filter));
10112         i40e_ethertype_filter_convert(filter, &check_filter);
10113         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10114                                                &check_filter.input);
10115         if (add && node) {
10116                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10117                 return -EINVAL;
10118         }
10119
10120         if (!add && !node) {
10121                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10122                 return -EINVAL;
10123         }
10124
10125         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10126                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10127         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10128                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10129         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10130
10131         memset(&stats, 0, sizeof(stats));
10132         ret = i40e_aq_add_rem_control_packet_filter(hw,
10133                         filter->mac_addr.addr_bytes,
10134                         filter->ether_type, flags,
10135                         pf->main_vsi->seid,
10136                         filter->queue, add, &stats, NULL);
10137
10138         PMD_DRV_LOG(INFO,
10139                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10140                 ret, stats.mac_etype_used, stats.etype_used,
10141                 stats.mac_etype_free, stats.etype_free);
10142         if (ret < 0)
10143                 return -ENOSYS;
10144
10145         /* Add or delete a filter in SW list */
10146         if (add) {
10147                 ethertype_filter = rte_zmalloc("ethertype_filter",
10148                                        sizeof(*ethertype_filter), 0);
10149                 if (ethertype_filter == NULL) {
10150                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10151                         return -ENOMEM;
10152                 }
10153
10154                 rte_memcpy(ethertype_filter, &check_filter,
10155                            sizeof(check_filter));
10156                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10157                 if (ret < 0)
10158                         rte_free(ethertype_filter);
10159         } else {
10160                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10161         }
10162
10163         return ret;
10164 }
10165
10166 /*
10167  * Handle operations for ethertype filter.
10168  */
10169 static int
10170 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10171                                 enum rte_filter_op filter_op,
10172                                 void *arg)
10173 {
10174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10175         int ret = 0;
10176
10177         if (filter_op == RTE_ETH_FILTER_NOP)
10178                 return ret;
10179
10180         if (arg == NULL) {
10181                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10182                             filter_op);
10183                 return -EINVAL;
10184         }
10185
10186         switch (filter_op) {
10187         case RTE_ETH_FILTER_ADD:
10188                 ret = i40e_ethertype_filter_set(pf,
10189                         (struct rte_eth_ethertype_filter *)arg,
10190                         TRUE);
10191                 break;
10192         case RTE_ETH_FILTER_DELETE:
10193                 ret = i40e_ethertype_filter_set(pf,
10194                         (struct rte_eth_ethertype_filter *)arg,
10195                         FALSE);
10196                 break;
10197         default:
10198                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10199                 ret = -ENOSYS;
10200                 break;
10201         }
10202         return ret;
10203 }
10204
10205 static int
10206 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10207                      enum rte_filter_type filter_type,
10208                      enum rte_filter_op filter_op,
10209                      void *arg)
10210 {
10211         int ret = 0;
10212
10213         if (dev == NULL)
10214                 return -EINVAL;
10215
10216         switch (filter_type) {
10217         case RTE_ETH_FILTER_NONE:
10218                 /* For global configuration */
10219                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10220                 break;
10221         case RTE_ETH_FILTER_HASH:
10222                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10223                 break;
10224         case RTE_ETH_FILTER_MACVLAN:
10225                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10226                 break;
10227         case RTE_ETH_FILTER_ETHERTYPE:
10228                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10229                 break;
10230         case RTE_ETH_FILTER_TUNNEL:
10231                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10232                 break;
10233         case RTE_ETH_FILTER_FDIR:
10234                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10235                 break;
10236         case RTE_ETH_FILTER_GENERIC:
10237                 if (filter_op != RTE_ETH_FILTER_GET)
10238                         return -EINVAL;
10239                 *(const void **)arg = &i40e_flow_ops;
10240                 break;
10241         default:
10242                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10243                                                         filter_type);
10244                 ret = -EINVAL;
10245                 break;
10246         }
10247
10248         return ret;
10249 }
10250
10251 /*
10252  * Check and enable Extended Tag.
10253  * Enabling Extended Tag is important for 40G performance.
10254  */
10255 static void
10256 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10257 {
10258         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10259         uint32_t buf = 0;
10260         int ret;
10261
10262         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10263                                       PCI_DEV_CAP_REG);
10264         if (ret < 0) {
10265                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10266                             PCI_DEV_CAP_REG);
10267                 return;
10268         }
10269         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10270                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10271                 return;
10272         }
10273
10274         buf = 0;
10275         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10276                                       PCI_DEV_CTRL_REG);
10277         if (ret < 0) {
10278                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10279                             PCI_DEV_CTRL_REG);
10280                 return;
10281         }
10282         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10283                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10284                 return;
10285         }
10286         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10287         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10288                                        PCI_DEV_CTRL_REG);
10289         if (ret < 0) {
10290                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10291                             PCI_DEV_CTRL_REG);
10292                 return;
10293         }
10294 }
10295
10296 /*
10297  * As some registers wouldn't be reset unless a global hardware reset,
10298  * hardware initialization is needed to put those registers into an
10299  * expected initial state.
10300  */
10301 static void
10302 i40e_hw_init(struct rte_eth_dev *dev)
10303 {
10304         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10305
10306         i40e_enable_extended_tag(dev);
10307
10308         /* clear the PF Queue Filter control register */
10309         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10310
10311         /* Disable symmetric hash per port */
10312         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10313 }
10314
10315 /*
10316  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10317  * however this function will return only one highest pctype index,
10318  * which is not quite correct. This is known problem of i40e driver
10319  * and needs to be fixed later.
10320  */
10321 enum i40e_filter_pctype
10322 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10323 {
10324         int i;
10325         uint64_t pctype_mask;
10326
10327         if (flow_type < I40E_FLOW_TYPE_MAX) {
10328                 pctype_mask = adapter->pctypes_tbl[flow_type];
10329                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10330                         if (pctype_mask & (1ULL << i))
10331                                 return (enum i40e_filter_pctype)i;
10332                 }
10333         }
10334         return I40E_FILTER_PCTYPE_INVALID;
10335 }
10336
10337 uint16_t
10338 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10339                         enum i40e_filter_pctype pctype)
10340 {
10341         uint16_t flowtype;
10342         uint64_t pctype_mask = 1ULL << pctype;
10343
10344         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10345              flowtype++) {
10346                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10347                         return flowtype;
10348         }
10349
10350         return RTE_ETH_FLOW_UNKNOWN;
10351 }
10352
10353 /*
10354  * On X710, performance number is far from the expectation on recent firmware
10355  * versions; on XL710, performance number is also far from the expectation on
10356  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10357  * mode is enabled and port MAC address is equal to the packet destination MAC
10358  * address. The fix for this issue may not be integrated in the following
10359  * firmware version. So the workaround in software driver is needed. It needs
10360  * to modify the initial values of 3 internal only registers for both X710 and
10361  * XL710. Note that the values for X710 or XL710 could be different, and the
10362  * workaround can be removed when it is fixed in firmware in the future.
10363  */
10364
10365 /* For both X710 and XL710 */
10366 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10367 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10368 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10369
10370 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10371 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10372
10373 /* For X722 */
10374 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10375 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10376
10377 /* For X710 */
10378 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10379 /* For XL710 */
10380 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10381 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10382
10383 /*
10384  * GL_SWR_PM_UP_THR:
10385  * The value is not impacted from the link speed, its value is set according
10386  * to the total number of ports for a better pipe-monitor configuration.
10387  */
10388 static bool
10389 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10390 {
10391 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10392                 .device_id = (dev),   \
10393                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10394
10395 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10396                 .device_id = (dev),   \
10397                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10398
10399         static const struct {
10400                 uint16_t device_id;
10401                 uint32_t val;
10402         } swr_pm_table[] = {
10403                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10404                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10405                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10406                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10407
10408                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10409                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10410                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10411                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10412                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10413                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10414                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10415         };
10416         uint32_t i;
10417
10418         if (value == NULL) {
10419                 PMD_DRV_LOG(ERR, "value is NULL");
10420                 return false;
10421         }
10422
10423         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10424                 if (hw->device_id == swr_pm_table[i].device_id) {
10425                         *value = swr_pm_table[i].val;
10426
10427                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10428                                     "value - 0x%08x",
10429                                     hw->device_id, *value);
10430                         return true;
10431                 }
10432         }
10433
10434         return false;
10435 }
10436
10437 static int
10438 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10439 {
10440         enum i40e_status_code status;
10441         struct i40e_aq_get_phy_abilities_resp phy_ab;
10442         int ret = -ENOTSUP;
10443         int retries = 0;
10444
10445         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10446                                               NULL);
10447
10448         while (status) {
10449                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10450                         status);
10451                 retries++;
10452                 rte_delay_us(100000);
10453                 if  (retries < 5)
10454                         status = i40e_aq_get_phy_capabilities(hw, false,
10455                                         true, &phy_ab, NULL);
10456                 else
10457                         return ret;
10458         }
10459         return 0;
10460 }
10461
10462 static void
10463 i40e_configure_registers(struct i40e_hw *hw)
10464 {
10465         static struct {
10466                 uint32_t addr;
10467                 uint64_t val;
10468         } reg_table[] = {
10469                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10470                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10471                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10472         };
10473         uint64_t reg;
10474         uint32_t i;
10475         int ret;
10476
10477         for (i = 0; i < RTE_DIM(reg_table); i++) {
10478                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10479                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10480                                 reg_table[i].val =
10481                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10482                         else /* For X710/XL710/XXV710 */
10483                                 if (hw->aq.fw_maj_ver < 6)
10484                                         reg_table[i].val =
10485                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10486                                 else
10487                                         reg_table[i].val =
10488                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10489                 }
10490
10491                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10492                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10493                                 reg_table[i].val =
10494                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10495                         else /* For X710/XL710/XXV710 */
10496                                 reg_table[i].val =
10497                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10498                 }
10499
10500                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10501                         uint32_t cfg_val;
10502
10503                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10504                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10505                                             "GL_SWR_PM_UP_THR value fixup",
10506                                             hw->device_id);
10507                                 continue;
10508                         }
10509
10510                         reg_table[i].val = cfg_val;
10511                 }
10512
10513                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10514                                                         &reg, NULL);
10515                 if (ret < 0) {
10516                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10517                                                         reg_table[i].addr);
10518                         break;
10519                 }
10520                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10521                                                 reg_table[i].addr, reg);
10522                 if (reg == reg_table[i].val)
10523                         continue;
10524
10525                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10526                                                 reg_table[i].val, NULL);
10527                 if (ret < 0) {
10528                         PMD_DRV_LOG(ERR,
10529                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10530                                 reg_table[i].val, reg_table[i].addr);
10531                         break;
10532                 }
10533                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10534                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10535         }
10536 }
10537
10538 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10539 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10540 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10541 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10542 static int
10543 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10544 {
10545         uint32_t reg;
10546         int ret;
10547
10548         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10549                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10550                 return -EINVAL;
10551         }
10552
10553         /* Configure for double VLAN RX stripping */
10554         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10555         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10556                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10557                 ret = i40e_aq_debug_write_register(hw,
10558                                                    I40E_VSI_TSR(vsi->vsi_id),
10559                                                    reg, NULL);
10560                 if (ret < 0) {
10561                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10562                                     vsi->vsi_id);
10563                         return I40E_ERR_CONFIG;
10564                 }
10565         }
10566
10567         /* Configure for double VLAN TX insertion */
10568         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10569         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10570                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10571                 ret = i40e_aq_debug_write_register(hw,
10572                                                    I40E_VSI_L2TAGSTXVALID(
10573                                                    vsi->vsi_id), reg, NULL);
10574                 if (ret < 0) {
10575                         PMD_DRV_LOG(ERR,
10576                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10577                                 vsi->vsi_id);
10578                         return I40E_ERR_CONFIG;
10579                 }
10580         }
10581
10582         return 0;
10583 }
10584
10585 /**
10586  * i40e_aq_add_mirror_rule
10587  * @hw: pointer to the hardware structure
10588  * @seid: VEB seid to add mirror rule to
10589  * @dst_id: destination vsi seid
10590  * @entries: Buffer which contains the entities to be mirrored
10591  * @count: number of entities contained in the buffer
10592  * @rule_id:the rule_id of the rule to be added
10593  *
10594  * Add a mirror rule for a given veb.
10595  *
10596  **/
10597 static enum i40e_status_code
10598 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10599                         uint16_t seid, uint16_t dst_id,
10600                         uint16_t rule_type, uint16_t *entries,
10601                         uint16_t count, uint16_t *rule_id)
10602 {
10603         struct i40e_aq_desc desc;
10604         struct i40e_aqc_add_delete_mirror_rule cmd;
10605         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10606                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10607                 &desc.params.raw;
10608         uint16_t buff_len;
10609         enum i40e_status_code status;
10610
10611         i40e_fill_default_direct_cmd_desc(&desc,
10612                                           i40e_aqc_opc_add_mirror_rule);
10613         memset(&cmd, 0, sizeof(cmd));
10614
10615         buff_len = sizeof(uint16_t) * count;
10616         desc.datalen = rte_cpu_to_le_16(buff_len);
10617         if (buff_len > 0)
10618                 desc.flags |= rte_cpu_to_le_16(
10619                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10620         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10621                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10622         cmd.num_entries = rte_cpu_to_le_16(count);
10623         cmd.seid = rte_cpu_to_le_16(seid);
10624         cmd.destination = rte_cpu_to_le_16(dst_id);
10625
10626         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10627         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10628         PMD_DRV_LOG(INFO,
10629                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10630                 hw->aq.asq_last_status, resp->rule_id,
10631                 resp->mirror_rules_used, resp->mirror_rules_free);
10632         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10633
10634         return status;
10635 }
10636
10637 /**
10638  * i40e_aq_del_mirror_rule
10639  * @hw: pointer to the hardware structure
10640  * @seid: VEB seid to add mirror rule to
10641  * @entries: Buffer which contains the entities to be mirrored
10642  * @count: number of entities contained in the buffer
10643  * @rule_id:the rule_id of the rule to be delete
10644  *
10645  * Delete a mirror rule for a given veb.
10646  *
10647  **/
10648 static enum i40e_status_code
10649 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10650                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10651                 uint16_t count, uint16_t rule_id)
10652 {
10653         struct i40e_aq_desc desc;
10654         struct i40e_aqc_add_delete_mirror_rule cmd;
10655         uint16_t buff_len = 0;
10656         enum i40e_status_code status;
10657         void *buff = NULL;
10658
10659         i40e_fill_default_direct_cmd_desc(&desc,
10660                                           i40e_aqc_opc_delete_mirror_rule);
10661         memset(&cmd, 0, sizeof(cmd));
10662         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10663                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10664                                                           I40E_AQ_FLAG_RD));
10665                 cmd.num_entries = count;
10666                 buff_len = sizeof(uint16_t) * count;
10667                 desc.datalen = rte_cpu_to_le_16(buff_len);
10668                 buff = (void *)entries;
10669         } else
10670                 /* rule id is filled in destination field for deleting mirror rule */
10671                 cmd.destination = rte_cpu_to_le_16(rule_id);
10672
10673         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10674                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10675         cmd.seid = rte_cpu_to_le_16(seid);
10676
10677         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10678         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10679
10680         return status;
10681 }
10682
10683 /**
10684  * i40e_mirror_rule_set
10685  * @dev: pointer to the hardware structure
10686  * @mirror_conf: mirror rule info
10687  * @sw_id: mirror rule's sw_id
10688  * @on: enable/disable
10689  *
10690  * set a mirror rule.
10691  *
10692  **/
10693 static int
10694 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10695                         struct rte_eth_mirror_conf *mirror_conf,
10696                         uint8_t sw_id, uint8_t on)
10697 {
10698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10699         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10700         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10701         struct i40e_mirror_rule *parent = NULL;
10702         uint16_t seid, dst_seid, rule_id;
10703         uint16_t i, j = 0;
10704         int ret;
10705
10706         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10707
10708         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10709                 PMD_DRV_LOG(ERR,
10710                         "mirror rule can not be configured without veb or vfs.");
10711                 return -ENOSYS;
10712         }
10713         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10714                 PMD_DRV_LOG(ERR, "mirror table is full.");
10715                 return -ENOSPC;
10716         }
10717         if (mirror_conf->dst_pool > pf->vf_num) {
10718                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10719                                  mirror_conf->dst_pool);
10720                 return -EINVAL;
10721         }
10722
10723         seid = pf->main_vsi->veb->seid;
10724
10725         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10726                 if (sw_id <= it->index) {
10727                         mirr_rule = it;
10728                         break;
10729                 }
10730                 parent = it;
10731         }
10732         if (mirr_rule && sw_id == mirr_rule->index) {
10733                 if (on) {
10734                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10735                         return -EEXIST;
10736                 } else {
10737                         ret = i40e_aq_del_mirror_rule(hw, seid,
10738                                         mirr_rule->rule_type,
10739                                         mirr_rule->entries,
10740                                         mirr_rule->num_entries, mirr_rule->id);
10741                         if (ret < 0) {
10742                                 PMD_DRV_LOG(ERR,
10743                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10744                                         ret, hw->aq.asq_last_status);
10745                                 return -ENOSYS;
10746                         }
10747                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10748                         rte_free(mirr_rule);
10749                         pf->nb_mirror_rule--;
10750                         return 0;
10751                 }
10752         } else if (!on) {
10753                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10754                 return -ENOENT;
10755         }
10756
10757         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10758                                 sizeof(struct i40e_mirror_rule) , 0);
10759         if (!mirr_rule) {
10760                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10761                 return I40E_ERR_NO_MEMORY;
10762         }
10763         switch (mirror_conf->rule_type) {
10764         case ETH_MIRROR_VLAN:
10765                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10766                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10767                                 mirr_rule->entries[j] =
10768                                         mirror_conf->vlan.vlan_id[i];
10769                                 j++;
10770                         }
10771                 }
10772                 if (j == 0) {
10773                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10774                         rte_free(mirr_rule);
10775                         return -EINVAL;
10776                 }
10777                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10778                 break;
10779         case ETH_MIRROR_VIRTUAL_POOL_UP:
10780         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10781                 /* check if the specified pool bit is out of range */
10782                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10783                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10784                         rte_free(mirr_rule);
10785                         return -EINVAL;
10786                 }
10787                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10788                         if (mirror_conf->pool_mask & (1ULL << i)) {
10789                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10790                                 j++;
10791                         }
10792                 }
10793                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10794                         /* add pf vsi to entries */
10795                         mirr_rule->entries[j] = pf->main_vsi_seid;
10796                         j++;
10797                 }
10798                 if (j == 0) {
10799                         PMD_DRV_LOG(ERR, "pool is not specified.");
10800                         rte_free(mirr_rule);
10801                         return -EINVAL;
10802                 }
10803                 /* egress and ingress in aq commands means from switch but not port */
10804                 mirr_rule->rule_type =
10805                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10806                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10807                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10808                 break;
10809         case ETH_MIRROR_UPLINK_PORT:
10810                 /* egress and ingress in aq commands means from switch but not port*/
10811                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10812                 break;
10813         case ETH_MIRROR_DOWNLINK_PORT:
10814                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10815                 break;
10816         default:
10817                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10818                         mirror_conf->rule_type);
10819                 rte_free(mirr_rule);
10820                 return -EINVAL;
10821         }
10822
10823         /* If the dst_pool is equal to vf_num, consider it as PF */
10824         if (mirror_conf->dst_pool == pf->vf_num)
10825                 dst_seid = pf->main_vsi_seid;
10826         else
10827                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10828
10829         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10830                                       mirr_rule->rule_type, mirr_rule->entries,
10831                                       j, &rule_id);
10832         if (ret < 0) {
10833                 PMD_DRV_LOG(ERR,
10834                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10835                         ret, hw->aq.asq_last_status);
10836                 rte_free(mirr_rule);
10837                 return -ENOSYS;
10838         }
10839
10840         mirr_rule->index = sw_id;
10841         mirr_rule->num_entries = j;
10842         mirr_rule->id = rule_id;
10843         mirr_rule->dst_vsi_seid = dst_seid;
10844
10845         if (parent)
10846                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10847         else
10848                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10849
10850         pf->nb_mirror_rule++;
10851         return 0;
10852 }
10853
10854 /**
10855  * i40e_mirror_rule_reset
10856  * @dev: pointer to the device
10857  * @sw_id: mirror rule's sw_id
10858  *
10859  * reset a mirror rule.
10860  *
10861  **/
10862 static int
10863 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10864 {
10865         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10867         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10868         uint16_t seid;
10869         int ret;
10870
10871         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10872
10873         seid = pf->main_vsi->veb->seid;
10874
10875         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10876                 if (sw_id == it->index) {
10877                         mirr_rule = it;
10878                         break;
10879                 }
10880         }
10881         if (mirr_rule) {
10882                 ret = i40e_aq_del_mirror_rule(hw, seid,
10883                                 mirr_rule->rule_type,
10884                                 mirr_rule->entries,
10885                                 mirr_rule->num_entries, mirr_rule->id);
10886                 if (ret < 0) {
10887                         PMD_DRV_LOG(ERR,
10888                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10889                                 ret, hw->aq.asq_last_status);
10890                         return -ENOSYS;
10891                 }
10892                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10893                 rte_free(mirr_rule);
10894                 pf->nb_mirror_rule--;
10895         } else {
10896                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10897                 return -ENOENT;
10898         }
10899         return 0;
10900 }
10901
10902 static uint64_t
10903 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10904 {
10905         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10906         uint64_t systim_cycles;
10907
10908         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10909         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10910                         << 32;
10911
10912         return systim_cycles;
10913 }
10914
10915 static uint64_t
10916 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10917 {
10918         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10919         uint64_t rx_tstamp;
10920
10921         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10922         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10923                         << 32;
10924
10925         return rx_tstamp;
10926 }
10927
10928 static uint64_t
10929 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10930 {
10931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10932         uint64_t tx_tstamp;
10933
10934         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10935         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10936                         << 32;
10937
10938         return tx_tstamp;
10939 }
10940
10941 static void
10942 i40e_start_timecounters(struct rte_eth_dev *dev)
10943 {
10944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10945         struct i40e_adapter *adapter = dev->data->dev_private;
10946         struct rte_eth_link link;
10947         uint32_t tsync_inc_l;
10948         uint32_t tsync_inc_h;
10949
10950         /* Get current link speed. */
10951         i40e_dev_link_update(dev, 1);
10952         rte_eth_linkstatus_get(dev, &link);
10953
10954         switch (link.link_speed) {
10955         case ETH_SPEED_NUM_40G:
10956         case ETH_SPEED_NUM_25G:
10957                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10958                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10959                 break;
10960         case ETH_SPEED_NUM_10G:
10961                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10962                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10963                 break;
10964         case ETH_SPEED_NUM_1G:
10965                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10966                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10967                 break;
10968         default:
10969                 tsync_inc_l = 0x0;
10970                 tsync_inc_h = 0x0;
10971         }
10972
10973         /* Set the timesync increment value. */
10974         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10975         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10976
10977         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10978         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10979         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10980
10981         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10982         adapter->systime_tc.cc_shift = 0;
10983         adapter->systime_tc.nsec_mask = 0;
10984
10985         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10986         adapter->rx_tstamp_tc.cc_shift = 0;
10987         adapter->rx_tstamp_tc.nsec_mask = 0;
10988
10989         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10990         adapter->tx_tstamp_tc.cc_shift = 0;
10991         adapter->tx_tstamp_tc.nsec_mask = 0;
10992 }
10993
10994 static int
10995 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10996 {
10997         struct i40e_adapter *adapter = dev->data->dev_private;
10998
10999         adapter->systime_tc.nsec += delta;
11000         adapter->rx_tstamp_tc.nsec += delta;
11001         adapter->tx_tstamp_tc.nsec += delta;
11002
11003         return 0;
11004 }
11005
11006 static int
11007 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11008 {
11009         uint64_t ns;
11010         struct i40e_adapter *adapter = dev->data->dev_private;
11011
11012         ns = rte_timespec_to_ns(ts);
11013
11014         /* Set the timecounters to a new value. */
11015         adapter->systime_tc.nsec = ns;
11016         adapter->rx_tstamp_tc.nsec = ns;
11017         adapter->tx_tstamp_tc.nsec = ns;
11018
11019         return 0;
11020 }
11021
11022 static int
11023 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11024 {
11025         uint64_t ns, systime_cycles;
11026         struct i40e_adapter *adapter = dev->data->dev_private;
11027
11028         systime_cycles = i40e_read_systime_cyclecounter(dev);
11029         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11030         *ts = rte_ns_to_timespec(ns);
11031
11032         return 0;
11033 }
11034
11035 static int
11036 i40e_timesync_enable(struct rte_eth_dev *dev)
11037 {
11038         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11039         uint32_t tsync_ctl_l;
11040         uint32_t tsync_ctl_h;
11041
11042         /* Stop the timesync system time. */
11043         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11044         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11045         /* Reset the timesync system time value. */
11046         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11047         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11048
11049         i40e_start_timecounters(dev);
11050
11051         /* Clear timesync registers. */
11052         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11053         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11054         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11055         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11056         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11057         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11058
11059         /* Enable timestamping of PTP packets. */
11060         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11061         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11062
11063         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11064         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11065         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11066
11067         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11068         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11069
11070         return 0;
11071 }
11072
11073 static int
11074 i40e_timesync_disable(struct rte_eth_dev *dev)
11075 {
11076         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11077         uint32_t tsync_ctl_l;
11078         uint32_t tsync_ctl_h;
11079
11080         /* Disable timestamping of transmitted PTP packets. */
11081         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11082         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11083
11084         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11085         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11086
11087         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11088         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11089
11090         /* Reset the timesync increment value. */
11091         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11092         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11093
11094         return 0;
11095 }
11096
11097 static int
11098 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11099                                 struct timespec *timestamp, uint32_t flags)
11100 {
11101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11102         struct i40e_adapter *adapter = dev->data->dev_private;
11103         uint32_t sync_status;
11104         uint32_t index = flags & 0x03;
11105         uint64_t rx_tstamp_cycles;
11106         uint64_t ns;
11107
11108         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11109         if ((sync_status & (1 << index)) == 0)
11110                 return -EINVAL;
11111
11112         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11113         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11114         *timestamp = rte_ns_to_timespec(ns);
11115
11116         return 0;
11117 }
11118
11119 static int
11120 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11121                                 struct timespec *timestamp)
11122 {
11123         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11124         struct i40e_adapter *adapter = dev->data->dev_private;
11125         uint32_t sync_status;
11126         uint64_t tx_tstamp_cycles;
11127         uint64_t ns;
11128
11129         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11130         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11131                 return -EINVAL;
11132
11133         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11134         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11135         *timestamp = rte_ns_to_timespec(ns);
11136
11137         return 0;
11138 }
11139
11140 /*
11141  * i40e_parse_dcb_configure - parse dcb configure from user
11142  * @dev: the device being configured
11143  * @dcb_cfg: pointer of the result of parse
11144  * @*tc_map: bit map of enabled traffic classes
11145  *
11146  * Returns 0 on success, negative value on failure
11147  */
11148 static int
11149 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11150                          struct i40e_dcbx_config *dcb_cfg,
11151                          uint8_t *tc_map)
11152 {
11153         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11154         uint8_t i, tc_bw, bw_lf;
11155
11156         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11157
11158         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11159         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11160                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11161                 return -EINVAL;
11162         }
11163
11164         /* assume each tc has the same bw */
11165         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11166         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11167                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11168         /* to ensure the sum of tcbw is equal to 100 */
11169         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11170         for (i = 0; i < bw_lf; i++)
11171                 dcb_cfg->etscfg.tcbwtable[i]++;
11172
11173         /* assume each tc has the same Transmission Selection Algorithm */
11174         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11175                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11176
11177         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11178                 dcb_cfg->etscfg.prioritytable[i] =
11179                                 dcb_rx_conf->dcb_tc[i];
11180
11181         /* FW needs one App to configure HW */
11182         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11183         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11184         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11185         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11186
11187         if (dcb_rx_conf->nb_tcs == 0)
11188                 *tc_map = 1; /* tc0 only */
11189         else
11190                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11191
11192         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11193                 dcb_cfg->pfc.willing = 0;
11194                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11195                 dcb_cfg->pfc.pfcenable = *tc_map;
11196         }
11197         return 0;
11198 }
11199
11200
11201 static enum i40e_status_code
11202 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11203                               struct i40e_aqc_vsi_properties_data *info,
11204                               uint8_t enabled_tcmap)
11205 {
11206         enum i40e_status_code ret;
11207         int i, total_tc = 0;
11208         uint16_t qpnum_per_tc, bsf, qp_idx;
11209         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11210         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11211         uint16_t used_queues;
11212
11213         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11214         if (ret != I40E_SUCCESS)
11215                 return ret;
11216
11217         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11218                 if (enabled_tcmap & (1 << i))
11219                         total_tc++;
11220         }
11221         if (total_tc == 0)
11222                 total_tc = 1;
11223         vsi->enabled_tc = enabled_tcmap;
11224
11225         /* different VSI has different queues assigned */
11226         if (vsi->type == I40E_VSI_MAIN)
11227                 used_queues = dev_data->nb_rx_queues -
11228                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11229         else if (vsi->type == I40E_VSI_VMDQ2)
11230                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11231         else {
11232                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11233                 return I40E_ERR_NO_AVAILABLE_VSI;
11234         }
11235
11236         qpnum_per_tc = used_queues / total_tc;
11237         /* Number of queues per enabled TC */
11238         if (qpnum_per_tc == 0) {
11239                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11240                 return I40E_ERR_INVALID_QP_ID;
11241         }
11242         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11243                                 I40E_MAX_Q_PER_TC);
11244         bsf = rte_bsf32(qpnum_per_tc);
11245
11246         /**
11247          * Configure TC and queue mapping parameters, for enabled TC,
11248          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11249          * default queue will serve it.
11250          */
11251         qp_idx = 0;
11252         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11253                 if (vsi->enabled_tc & (1 << i)) {
11254                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11255                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11256                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11257                         qp_idx += qpnum_per_tc;
11258                 } else
11259                         info->tc_mapping[i] = 0;
11260         }
11261
11262         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11263         if (vsi->type == I40E_VSI_SRIOV) {
11264                 info->mapping_flags |=
11265                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11266                 for (i = 0; i < vsi->nb_qps; i++)
11267                         info->queue_mapping[i] =
11268                                 rte_cpu_to_le_16(vsi->base_queue + i);
11269         } else {
11270                 info->mapping_flags |=
11271                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11272                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11273         }
11274         info->valid_sections |=
11275                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11276
11277         return I40E_SUCCESS;
11278 }
11279
11280 /*
11281  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11282  * @veb: VEB to be configured
11283  * @tc_map: enabled TC bitmap
11284  *
11285  * Returns 0 on success, negative value on failure
11286  */
11287 static enum i40e_status_code
11288 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11289 {
11290         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11291         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11292         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11293         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11294         enum i40e_status_code ret = I40E_SUCCESS;
11295         int i;
11296         uint32_t bw_max;
11297
11298         /* Check if enabled_tc is same as existing or new TCs */
11299         if (veb->enabled_tc == tc_map)
11300                 return ret;
11301
11302         /* configure tc bandwidth */
11303         memset(&veb_bw, 0, sizeof(veb_bw));
11304         veb_bw.tc_valid_bits = tc_map;
11305         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11306         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11307                 if (tc_map & BIT_ULL(i))
11308                         veb_bw.tc_bw_share_credits[i] = 1;
11309         }
11310         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11311                                                    &veb_bw, NULL);
11312         if (ret) {
11313                 PMD_INIT_LOG(ERR,
11314                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11315                         hw->aq.asq_last_status);
11316                 return ret;
11317         }
11318
11319         memset(&ets_query, 0, sizeof(ets_query));
11320         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11321                                                    &ets_query, NULL);
11322         if (ret != I40E_SUCCESS) {
11323                 PMD_DRV_LOG(ERR,
11324                         "Failed to get switch_comp ETS configuration %u",
11325                         hw->aq.asq_last_status);
11326                 return ret;
11327         }
11328         memset(&bw_query, 0, sizeof(bw_query));
11329         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11330                                                   &bw_query, NULL);
11331         if (ret != I40E_SUCCESS) {
11332                 PMD_DRV_LOG(ERR,
11333                         "Failed to get switch_comp bandwidth configuration %u",
11334                         hw->aq.asq_last_status);
11335                 return ret;
11336         }
11337
11338         /* store and print out BW info */
11339         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11340         veb->bw_info.bw_max = ets_query.tc_bw_max;
11341         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11342         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11343         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11344                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11345                      I40E_16_BIT_WIDTH);
11346         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11347                 veb->bw_info.bw_ets_share_credits[i] =
11348                                 bw_query.tc_bw_share_credits[i];
11349                 veb->bw_info.bw_ets_credits[i] =
11350                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11351                 /* 4 bits per TC, 4th bit is reserved */
11352                 veb->bw_info.bw_ets_max[i] =
11353                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11354                                   RTE_LEN2MASK(3, uint8_t));
11355                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11356                             veb->bw_info.bw_ets_share_credits[i]);
11357                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11358                             veb->bw_info.bw_ets_credits[i]);
11359                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11360                             veb->bw_info.bw_ets_max[i]);
11361         }
11362
11363         veb->enabled_tc = tc_map;
11364
11365         return ret;
11366 }
11367
11368
11369 /*
11370  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11371  * @vsi: VSI to be configured
11372  * @tc_map: enabled TC bitmap
11373  *
11374  * Returns 0 on success, negative value on failure
11375  */
11376 static enum i40e_status_code
11377 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11378 {
11379         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11380         struct i40e_vsi_context ctxt;
11381         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11382         enum i40e_status_code ret = I40E_SUCCESS;
11383         int i;
11384
11385         /* Check if enabled_tc is same as existing or new TCs */
11386         if (vsi->enabled_tc == tc_map)
11387                 return ret;
11388
11389         /* configure tc bandwidth */
11390         memset(&bw_data, 0, sizeof(bw_data));
11391         bw_data.tc_valid_bits = tc_map;
11392         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11393         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11394                 if (tc_map & BIT_ULL(i))
11395                         bw_data.tc_bw_credits[i] = 1;
11396         }
11397         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11398         if (ret) {
11399                 PMD_INIT_LOG(ERR,
11400                         "AQ command Config VSI BW allocation per TC failed = %d",
11401                         hw->aq.asq_last_status);
11402                 goto out;
11403         }
11404         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11405                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11406
11407         /* Update Queue Pairs Mapping for currently enabled UPs */
11408         ctxt.seid = vsi->seid;
11409         ctxt.pf_num = hw->pf_id;
11410         ctxt.vf_num = 0;
11411         ctxt.uplink_seid = vsi->uplink_seid;
11412         ctxt.info = vsi->info;
11413         i40e_get_cap(hw);
11414         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11415         if (ret)
11416                 goto out;
11417
11418         /* Update the VSI after updating the VSI queue-mapping information */
11419         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11420         if (ret) {
11421                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11422                         hw->aq.asq_last_status);
11423                 goto out;
11424         }
11425         /* update the local VSI info with updated queue map */
11426         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11427                                         sizeof(vsi->info.tc_mapping));
11428         rte_memcpy(&vsi->info.queue_mapping,
11429                         &ctxt.info.queue_mapping,
11430                 sizeof(vsi->info.queue_mapping));
11431         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11432         vsi->info.valid_sections = 0;
11433
11434         /* query and update current VSI BW information */
11435         ret = i40e_vsi_get_bw_config(vsi);
11436         if (ret) {
11437                 PMD_INIT_LOG(ERR,
11438                          "Failed updating vsi bw info, err %s aq_err %s",
11439                          i40e_stat_str(hw, ret),
11440                          i40e_aq_str(hw, hw->aq.asq_last_status));
11441                 goto out;
11442         }
11443
11444         vsi->enabled_tc = tc_map;
11445
11446 out:
11447         return ret;
11448 }
11449
11450 /*
11451  * i40e_dcb_hw_configure - program the dcb setting to hw
11452  * @pf: pf the configuration is taken on
11453  * @new_cfg: new configuration
11454  * @tc_map: enabled TC bitmap
11455  *
11456  * Returns 0 on success, negative value on failure
11457  */
11458 static enum i40e_status_code
11459 i40e_dcb_hw_configure(struct i40e_pf *pf,
11460                       struct i40e_dcbx_config *new_cfg,
11461                       uint8_t tc_map)
11462 {
11463         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11464         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11465         struct i40e_vsi *main_vsi = pf->main_vsi;
11466         struct i40e_vsi_list *vsi_list;
11467         enum i40e_status_code ret;
11468         int i;
11469         uint32_t val;
11470
11471         /* Use the FW API if FW > v4.4*/
11472         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11473               (hw->aq.fw_maj_ver >= 5))) {
11474                 PMD_INIT_LOG(ERR,
11475                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11476                 return I40E_ERR_FIRMWARE_API_VERSION;
11477         }
11478
11479         /* Check if need reconfiguration */
11480         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11481                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11482                 return I40E_SUCCESS;
11483         }
11484
11485         /* Copy the new config to the current config */
11486         *old_cfg = *new_cfg;
11487         old_cfg->etsrec = old_cfg->etscfg;
11488         ret = i40e_set_dcb_config(hw);
11489         if (ret) {
11490                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11491                          i40e_stat_str(hw, ret),
11492                          i40e_aq_str(hw, hw->aq.asq_last_status));
11493                 return ret;
11494         }
11495         /* set receive Arbiter to RR mode and ETS scheme by default */
11496         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11497                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11498                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11499                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11500                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11501                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11502                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11503                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11504                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11505                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11506                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11507                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11508                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11509         }
11510         /* get local mib to check whether it is configured correctly */
11511         /* IEEE mode */
11512         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11513         /* Get Local DCB Config */
11514         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11515                                      &hw->local_dcbx_config);
11516
11517         /* if Veb is created, need to update TC of it at first */
11518         if (main_vsi->veb) {
11519                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11520                 if (ret)
11521                         PMD_INIT_LOG(WARNING,
11522                                  "Failed configuring TC for VEB seid=%d",
11523                                  main_vsi->veb->seid);
11524         }
11525         /* Update each VSI */
11526         i40e_vsi_config_tc(main_vsi, tc_map);
11527         if (main_vsi->veb) {
11528                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11529                         /* Beside main VSI and VMDQ VSIs, only enable default
11530                          * TC for other VSIs
11531                          */
11532                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11533                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11534                                                          tc_map);
11535                         else
11536                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11537                                                          I40E_DEFAULT_TCMAP);
11538                         if (ret)
11539                                 PMD_INIT_LOG(WARNING,
11540                                         "Failed configuring TC for VSI seid=%d",
11541                                         vsi_list->vsi->seid);
11542                         /* continue */
11543                 }
11544         }
11545         return I40E_SUCCESS;
11546 }
11547
11548 /*
11549  * i40e_dcb_init_configure - initial dcb config
11550  * @dev: device being configured
11551  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11552  *
11553  * Returns 0 on success, negative value on failure
11554  */
11555 int
11556 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11557 {
11558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11559         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11560         int i, ret = 0;
11561
11562         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11563                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11564                 return -ENOTSUP;
11565         }
11566
11567         /* DCB initialization:
11568          * Update DCB configuration from the Firmware and configure
11569          * LLDP MIB change event.
11570          */
11571         if (sw_dcb == TRUE) {
11572                 if (i40e_need_stop_lldp(dev)) {
11573                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11574                         if (ret != I40E_SUCCESS)
11575                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11576                 }
11577
11578                 ret = i40e_init_dcb(hw);
11579                 /* If lldp agent is stopped, the return value from
11580                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11581                  * adminq status. Otherwise, it should return success.
11582                  */
11583                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11584                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11585                         memset(&hw->local_dcbx_config, 0,
11586                                 sizeof(struct i40e_dcbx_config));
11587                         /* set dcb default configuration */
11588                         hw->local_dcbx_config.etscfg.willing = 0;
11589                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11590                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11591                         hw->local_dcbx_config.etscfg.tsatable[0] =
11592                                                 I40E_IEEE_TSA_ETS;
11593                         /* all UPs mapping to TC0 */
11594                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11595                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11596                         hw->local_dcbx_config.etsrec =
11597                                 hw->local_dcbx_config.etscfg;
11598                         hw->local_dcbx_config.pfc.willing = 0;
11599                         hw->local_dcbx_config.pfc.pfccap =
11600                                                 I40E_MAX_TRAFFIC_CLASS;
11601                         /* FW needs one App to configure HW */
11602                         hw->local_dcbx_config.numapps = 1;
11603                         hw->local_dcbx_config.app[0].selector =
11604                                                 I40E_APP_SEL_ETHTYPE;
11605                         hw->local_dcbx_config.app[0].priority = 3;
11606                         hw->local_dcbx_config.app[0].protocolid =
11607                                                 I40E_APP_PROTOID_FCOE;
11608                         ret = i40e_set_dcb_config(hw);
11609                         if (ret) {
11610                                 PMD_INIT_LOG(ERR,
11611                                         "default dcb config fails. err = %d, aq_err = %d.",
11612                                         ret, hw->aq.asq_last_status);
11613                                 return -ENOSYS;
11614                         }
11615                 } else {
11616                         PMD_INIT_LOG(ERR,
11617                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11618                                 ret, hw->aq.asq_last_status);
11619                         return -ENOTSUP;
11620                 }
11621         } else {
11622                 ret = i40e_aq_start_lldp(hw, NULL);
11623                 if (ret != I40E_SUCCESS)
11624                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11625
11626                 ret = i40e_init_dcb(hw);
11627                 if (!ret) {
11628                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11629                                 PMD_INIT_LOG(ERR,
11630                                         "HW doesn't support DCBX offload.");
11631                                 return -ENOTSUP;
11632                         }
11633                 } else {
11634                         PMD_INIT_LOG(ERR,
11635                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11636                                 ret, hw->aq.asq_last_status);
11637                         return -ENOTSUP;
11638                 }
11639         }
11640         return 0;
11641 }
11642
11643 /*
11644  * i40e_dcb_setup - setup dcb related config
11645  * @dev: device being configured
11646  *
11647  * Returns 0 on success, negative value on failure
11648  */
11649 static int
11650 i40e_dcb_setup(struct rte_eth_dev *dev)
11651 {
11652         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11653         struct i40e_dcbx_config dcb_cfg;
11654         uint8_t tc_map = 0;
11655         int ret = 0;
11656
11657         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11658                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11659                 return -ENOTSUP;
11660         }
11661
11662         if (pf->vf_num != 0)
11663                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11664
11665         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11666         if (ret) {
11667                 PMD_INIT_LOG(ERR, "invalid dcb config");
11668                 return -EINVAL;
11669         }
11670         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11671         if (ret) {
11672                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11673                 return -ENOSYS;
11674         }
11675
11676         return 0;
11677 }
11678
11679 static int
11680 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11681                       struct rte_eth_dcb_info *dcb_info)
11682 {
11683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11684         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11685         struct i40e_vsi *vsi = pf->main_vsi;
11686         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11687         uint16_t bsf, tc_mapping;
11688         int i, j = 0;
11689
11690         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11691                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11692         else
11693                 dcb_info->nb_tcs = 1;
11694         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11695                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11696         for (i = 0; i < dcb_info->nb_tcs; i++)
11697                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11698
11699         /* get queue mapping if vmdq is disabled */
11700         if (!pf->nb_cfg_vmdq_vsi) {
11701                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11702                         if (!(vsi->enabled_tc & (1 << i)))
11703                                 continue;
11704                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11705                         dcb_info->tc_queue.tc_rxq[j][i].base =
11706                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11707                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11708                         dcb_info->tc_queue.tc_txq[j][i].base =
11709                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11710                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11711                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11712                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11713                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11714                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11715                 }
11716                 return 0;
11717         }
11718
11719         /* get queue mapping if vmdq is enabled */
11720         do {
11721                 vsi = pf->vmdq[j].vsi;
11722                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11723                         if (!(vsi->enabled_tc & (1 << i)))
11724                                 continue;
11725                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11726                         dcb_info->tc_queue.tc_rxq[j][i].base =
11727                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11728                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11729                         dcb_info->tc_queue.tc_txq[j][i].base =
11730                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11731                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11732                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11733                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11734                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11735                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11736                 }
11737                 j++;
11738         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11739         return 0;
11740 }
11741
11742 static int
11743 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11744 {
11745         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11746         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11747         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11748         uint16_t msix_intr;
11749
11750         msix_intr = intr_handle->intr_vec[queue_id];
11751         if (msix_intr == I40E_MISC_VEC_ID)
11752                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11753                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11754                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11755                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11756         else
11757                 I40E_WRITE_REG(hw,
11758                                I40E_PFINT_DYN_CTLN(msix_intr -
11759                                                    I40E_RX_VEC_START),
11760                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11761                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11762                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11763
11764         I40E_WRITE_FLUSH(hw);
11765         rte_intr_ack(&pci_dev->intr_handle);
11766
11767         return 0;
11768 }
11769
11770 static int
11771 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11772 {
11773         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11774         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11775         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11776         uint16_t msix_intr;
11777
11778         msix_intr = intr_handle->intr_vec[queue_id];
11779         if (msix_intr == I40E_MISC_VEC_ID)
11780                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11781                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11782         else
11783                 I40E_WRITE_REG(hw,
11784                                I40E_PFINT_DYN_CTLN(msix_intr -
11785                                                    I40E_RX_VEC_START),
11786                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11787         I40E_WRITE_FLUSH(hw);
11788
11789         return 0;
11790 }
11791
11792 /**
11793  * This function is used to check if the register is valid.
11794  * Below is the valid registers list for X722 only:
11795  * 0x2b800--0x2bb00
11796  * 0x38700--0x38a00
11797  * 0x3d800--0x3db00
11798  * 0x208e00--0x209000
11799  * 0x20be00--0x20c000
11800  * 0x263c00--0x264000
11801  * 0x265c00--0x266000
11802  */
11803 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11804 {
11805         if ((type != I40E_MAC_X722) &&
11806             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11807              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11808              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11809              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11810              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11811              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11812              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11813                 return 0;
11814         else
11815                 return 1;
11816 }
11817
11818 static int i40e_get_regs(struct rte_eth_dev *dev,
11819                          struct rte_dev_reg_info *regs)
11820 {
11821         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11822         uint32_t *ptr_data = regs->data;
11823         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11824         const struct i40e_reg_info *reg_info;
11825
11826         if (ptr_data == NULL) {
11827                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11828                 regs->width = sizeof(uint32_t);
11829                 return 0;
11830         }
11831
11832         /* The first few registers have to be read using AQ operations */
11833         reg_idx = 0;
11834         while (i40e_regs_adminq[reg_idx].name) {
11835                 reg_info = &i40e_regs_adminq[reg_idx++];
11836                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11837                         for (arr_idx2 = 0;
11838                                         arr_idx2 <= reg_info->count2;
11839                                         arr_idx2++) {
11840                                 reg_offset = arr_idx * reg_info->stride1 +
11841                                         arr_idx2 * reg_info->stride2;
11842                                 reg_offset += reg_info->base_addr;
11843                                 ptr_data[reg_offset >> 2] =
11844                                         i40e_read_rx_ctl(hw, reg_offset);
11845                         }
11846         }
11847
11848         /* The remaining registers can be read using primitives */
11849         reg_idx = 0;
11850         while (i40e_regs_others[reg_idx].name) {
11851                 reg_info = &i40e_regs_others[reg_idx++];
11852                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11853                         for (arr_idx2 = 0;
11854                                         arr_idx2 <= reg_info->count2;
11855                                         arr_idx2++) {
11856                                 reg_offset = arr_idx * reg_info->stride1 +
11857                                         arr_idx2 * reg_info->stride2;
11858                                 reg_offset += reg_info->base_addr;
11859                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11860                                         ptr_data[reg_offset >> 2] = 0;
11861                                 else
11862                                         ptr_data[reg_offset >> 2] =
11863                                                 I40E_READ_REG(hw, reg_offset);
11864                         }
11865         }
11866
11867         return 0;
11868 }
11869
11870 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11871 {
11872         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11873
11874         /* Convert word count to byte count */
11875         return hw->nvm.sr_size << 1;
11876 }
11877
11878 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11879                            struct rte_dev_eeprom_info *eeprom)
11880 {
11881         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11882         uint16_t *data = eeprom->data;
11883         uint16_t offset, length, cnt_words;
11884         int ret_code;
11885
11886         offset = eeprom->offset >> 1;
11887         length = eeprom->length >> 1;
11888         cnt_words = length;
11889
11890         if (offset > hw->nvm.sr_size ||
11891                 offset + length > hw->nvm.sr_size) {
11892                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11893                 return -EINVAL;
11894         }
11895
11896         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11897
11898         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11899         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11900                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11901                 return -EIO;
11902         }
11903
11904         return 0;
11905 }
11906
11907 static int i40e_get_module_info(struct rte_eth_dev *dev,
11908                                 struct rte_eth_dev_module_info *modinfo)
11909 {
11910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11911         uint32_t sff8472_comp = 0;
11912         uint32_t sff8472_swap = 0;
11913         uint32_t sff8636_rev = 0;
11914         i40e_status status;
11915         uint32_t type = 0;
11916
11917         /* Check if firmware supports reading module EEPROM. */
11918         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11919                 PMD_DRV_LOG(ERR,
11920                             "Module EEPROM memory read not supported. "
11921                             "Please update the NVM image.\n");
11922                 return -EINVAL;
11923         }
11924
11925         status = i40e_update_link_info(hw);
11926         if (status)
11927                 return -EIO;
11928
11929         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11930                 PMD_DRV_LOG(ERR,
11931                             "Cannot read module EEPROM memory. "
11932                             "No module connected.\n");
11933                 return -EINVAL;
11934         }
11935
11936         type = hw->phy.link_info.module_type[0];
11937
11938         switch (type) {
11939         case I40E_MODULE_TYPE_SFP:
11940                 status = i40e_aq_get_phy_register(hw,
11941                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11942                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11943                                 I40E_MODULE_SFF_8472_COMP,
11944                                 &sff8472_comp, NULL);
11945                 if (status)
11946                         return -EIO;
11947
11948                 status = i40e_aq_get_phy_register(hw,
11949                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11950                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11951                                 I40E_MODULE_SFF_8472_SWAP,
11952                                 &sff8472_swap, NULL);
11953                 if (status)
11954                         return -EIO;
11955
11956                 /* Check if the module requires address swap to access
11957                  * the other EEPROM memory page.
11958                  */
11959                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11960                         PMD_DRV_LOG(WARNING,
11961                                     "Module address swap to access "
11962                                     "page 0xA2 is not supported.\n");
11963                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11964                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11965                 } else if (sff8472_comp == 0x00) {
11966                         /* Module is not SFF-8472 compliant */
11967                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11968                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11969                 } else {
11970                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11971                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11972                 }
11973                 break;
11974         case I40E_MODULE_TYPE_QSFP_PLUS:
11975                 /* Read from memory page 0. */
11976                 status = i40e_aq_get_phy_register(hw,
11977                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11978                                 0, 1,
11979                                 I40E_MODULE_REVISION_ADDR,
11980                                 &sff8636_rev, NULL);
11981                 if (status)
11982                         return -EIO;
11983                 /* Determine revision compliance byte */
11984                 if (sff8636_rev > 0x02) {
11985                         /* Module is SFF-8636 compliant */
11986                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11987                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11988                 } else {
11989                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11990                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11991                 }
11992                 break;
11993         case I40E_MODULE_TYPE_QSFP28:
11994                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11995                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11996                 break;
11997         default:
11998                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11999                 return -EINVAL;
12000         }
12001         return 0;
12002 }
12003
12004 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12005                                   struct rte_dev_eeprom_info *info)
12006 {
12007         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12008         bool is_sfp = false;
12009         i40e_status status;
12010         uint8_t *data;
12011         uint32_t value = 0;
12012         uint32_t i;
12013
12014         if (!info || !info->length || !info->data)
12015                 return -EINVAL;
12016
12017         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12018                 is_sfp = true;
12019
12020         data = info->data;
12021         for (i = 0; i < info->length; i++) {
12022                 u32 offset = i + info->offset;
12023                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12024
12025                 /* Check if we need to access the other memory page */
12026                 if (is_sfp) {
12027                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12028                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12029                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12030                         }
12031                 } else {
12032                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12033                                 /* Compute memory page number and offset. */
12034                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12035                                 addr++;
12036                         }
12037                 }
12038                 status = i40e_aq_get_phy_register(hw,
12039                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12040                                 addr, offset, 1, &value, NULL);
12041                 if (status)
12042                         return -EIO;
12043                 data[i] = (uint8_t)value;
12044         }
12045         return 0;
12046 }
12047
12048 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12049                                      struct rte_ether_addr *mac_addr)
12050 {
12051         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12052         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12053         struct i40e_vsi *vsi = pf->main_vsi;
12054         struct i40e_mac_filter_info mac_filter;
12055         struct i40e_mac_filter *f;
12056         int ret;
12057
12058         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12059                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12060                 return -EINVAL;
12061         }
12062
12063         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12064                 if (rte_is_same_ether_addr(&pf->dev_addr,
12065                                                 &f->mac_info.mac_addr))
12066                         break;
12067         }
12068
12069         if (f == NULL) {
12070                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12071                 return -EIO;
12072         }
12073
12074         mac_filter = f->mac_info;
12075         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12076         if (ret != I40E_SUCCESS) {
12077                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12078                 return -EIO;
12079         }
12080         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12081         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12082         if (ret != I40E_SUCCESS) {
12083                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12084                 return -EIO;
12085         }
12086         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12087
12088         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12089                                         mac_addr->addr_bytes, NULL);
12090         if (ret != I40E_SUCCESS) {
12091                 PMD_DRV_LOG(ERR, "Failed to change mac");
12092                 return -EIO;
12093         }
12094
12095         return 0;
12096 }
12097
12098 static int
12099 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12100 {
12101         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12102         struct rte_eth_dev_data *dev_data = pf->dev_data;
12103         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12104         int ret = 0;
12105
12106         /* check if mtu is within the allowed range */
12107         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12108                 return -EINVAL;
12109
12110         /* mtu setting is forbidden if port is start */
12111         if (dev_data->dev_started) {
12112                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12113                             dev_data->port_id);
12114                 return -EBUSY;
12115         }
12116
12117         if (frame_size > RTE_ETHER_MAX_LEN)
12118                 dev_data->dev_conf.rxmode.offloads |=
12119                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12120         else
12121                 dev_data->dev_conf.rxmode.offloads &=
12122                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12123
12124         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12125
12126         return ret;
12127 }
12128
12129 /* Restore ethertype filter */
12130 static void
12131 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12132 {
12133         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12134         struct i40e_ethertype_filter_list
12135                 *ethertype_list = &pf->ethertype.ethertype_list;
12136         struct i40e_ethertype_filter *f;
12137         struct i40e_control_filter_stats stats;
12138         uint16_t flags;
12139
12140         TAILQ_FOREACH(f, ethertype_list, rules) {
12141                 flags = 0;
12142                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12143                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12144                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12145                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12146                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12147
12148                 memset(&stats, 0, sizeof(stats));
12149                 i40e_aq_add_rem_control_packet_filter(hw,
12150                                             f->input.mac_addr.addr_bytes,
12151                                             f->input.ether_type,
12152                                             flags, pf->main_vsi->seid,
12153                                             f->queue, 1, &stats, NULL);
12154         }
12155         PMD_DRV_LOG(INFO, "Ethertype filter:"
12156                     " mac_etype_used = %u, etype_used = %u,"
12157                     " mac_etype_free = %u, etype_free = %u",
12158                     stats.mac_etype_used, stats.etype_used,
12159                     stats.mac_etype_free, stats.etype_free);
12160 }
12161
12162 /* Restore tunnel filter */
12163 static void
12164 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12165 {
12166         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12167         struct i40e_vsi *vsi;
12168         struct i40e_pf_vf *vf;
12169         struct i40e_tunnel_filter_list
12170                 *tunnel_list = &pf->tunnel.tunnel_list;
12171         struct i40e_tunnel_filter *f;
12172         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12173         bool big_buffer = 0;
12174
12175         TAILQ_FOREACH(f, tunnel_list, rules) {
12176                 if (!f->is_to_vf)
12177                         vsi = pf->main_vsi;
12178                 else {
12179                         vf = &pf->vfs[f->vf_id];
12180                         vsi = vf->vsi;
12181                 }
12182                 memset(&cld_filter, 0, sizeof(cld_filter));
12183                 rte_ether_addr_copy((struct rte_ether_addr *)
12184                                 &f->input.outer_mac,
12185                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12186                 rte_ether_addr_copy((struct rte_ether_addr *)
12187                                 &f->input.inner_mac,
12188                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12189                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12190                 cld_filter.element.flags = f->input.flags;
12191                 cld_filter.element.tenant_id = f->input.tenant_id;
12192                 cld_filter.element.queue_number = f->queue;
12193                 rte_memcpy(cld_filter.general_fields,
12194                            f->input.general_fields,
12195                            sizeof(f->input.general_fields));
12196
12197                 if (((f->input.flags &
12198                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12199                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12200                     ((f->input.flags &
12201                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12202                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12203                     ((f->input.flags &
12204                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12205                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12206                         big_buffer = 1;
12207
12208                 if (big_buffer)
12209                         i40e_aq_add_cloud_filters_bb(hw,
12210                                         vsi->seid, &cld_filter, 1);
12211                 else
12212                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12213                                                   &cld_filter.element, 1);
12214         }
12215 }
12216
12217 /* Restore rss filter */
12218 static inline void
12219 i40e_rss_filter_restore(struct i40e_pf *pf)
12220 {
12221         struct i40e_rte_flow_rss_conf *conf =
12222                                         &pf->rss_info;
12223         if (conf->conf.queue_num)
12224                 i40e_config_rss_filter(pf, conf, TRUE);
12225 }
12226
12227 static void
12228 i40e_filter_restore(struct i40e_pf *pf)
12229 {
12230         i40e_ethertype_filter_restore(pf);
12231         i40e_tunnel_filter_restore(pf);
12232         i40e_fdir_filter_restore(pf);
12233         i40e_rss_filter_restore(pf);
12234 }
12235
12236 bool
12237 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12238 {
12239         if (strcmp(dev->device->driver->name, drv->driver.name))
12240                 return false;
12241
12242         return true;
12243 }
12244
12245 bool
12246 is_i40e_supported(struct rte_eth_dev *dev)
12247 {
12248         return is_device_supported(dev, &rte_i40e_pmd);
12249 }
12250
12251 struct i40e_customized_pctype*
12252 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12253 {
12254         int i;
12255
12256         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12257                 if (pf->customized_pctype[i].index == index)
12258                         return &pf->customized_pctype[i];
12259         }
12260         return NULL;
12261 }
12262
12263 static int
12264 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12265                               uint32_t pkg_size, uint32_t proto_num,
12266                               struct rte_pmd_i40e_proto_info *proto,
12267                               enum rte_pmd_i40e_package_op op)
12268 {
12269         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12270         uint32_t pctype_num;
12271         struct rte_pmd_i40e_ptype_info *pctype;
12272         uint32_t buff_size;
12273         struct i40e_customized_pctype *new_pctype = NULL;
12274         uint8_t proto_id;
12275         uint8_t pctype_value;
12276         char name[64];
12277         uint32_t i, j, n;
12278         int ret;
12279
12280         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12281             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12282                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12283                 return -1;
12284         }
12285
12286         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12287                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12288                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12289         if (ret) {
12290                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12291                 return -1;
12292         }
12293         if (!pctype_num) {
12294                 PMD_DRV_LOG(INFO, "No new pctype added");
12295                 return -1;
12296         }
12297
12298         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12299         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12300         if (!pctype) {
12301                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12302                 return -1;
12303         }
12304         /* get information about new pctype list */
12305         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12306                                         (uint8_t *)pctype, buff_size,
12307                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12308         if (ret) {
12309                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12310                 rte_free(pctype);
12311                 return -1;
12312         }
12313
12314         /* Update customized pctype. */
12315         for (i = 0; i < pctype_num; i++) {
12316                 pctype_value = pctype[i].ptype_id;
12317                 memset(name, 0, sizeof(name));
12318                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12319                         proto_id = pctype[i].protocols[j];
12320                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12321                                 continue;
12322                         for (n = 0; n < proto_num; n++) {
12323                                 if (proto[n].proto_id != proto_id)
12324                                         continue;
12325                                 strlcat(name, proto[n].name, sizeof(name));
12326                                 strlcat(name, "_", sizeof(name));
12327                                 break;
12328                         }
12329                 }
12330                 name[strlen(name) - 1] = '\0';
12331                 if (!strcmp(name, "GTPC"))
12332                         new_pctype =
12333                                 i40e_find_customized_pctype(pf,
12334                                                       I40E_CUSTOMIZED_GTPC);
12335                 else if (!strcmp(name, "GTPU_IPV4"))
12336                         new_pctype =
12337                                 i40e_find_customized_pctype(pf,
12338                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12339                 else if (!strcmp(name, "GTPU_IPV6"))
12340                         new_pctype =
12341                                 i40e_find_customized_pctype(pf,
12342                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12343                 else if (!strcmp(name, "GTPU"))
12344                         new_pctype =
12345                                 i40e_find_customized_pctype(pf,
12346                                                       I40E_CUSTOMIZED_GTPU);
12347                 if (new_pctype) {
12348                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12349                                 new_pctype->pctype = pctype_value;
12350                                 new_pctype->valid = true;
12351                         } else {
12352                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12353                                 new_pctype->valid = false;
12354                         }
12355                 }
12356         }
12357
12358         rte_free(pctype);
12359         return 0;
12360 }
12361
12362 static int
12363 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12364                              uint32_t pkg_size, uint32_t proto_num,
12365                              struct rte_pmd_i40e_proto_info *proto,
12366                              enum rte_pmd_i40e_package_op op)
12367 {
12368         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12369         uint16_t port_id = dev->data->port_id;
12370         uint32_t ptype_num;
12371         struct rte_pmd_i40e_ptype_info *ptype;
12372         uint32_t buff_size;
12373         uint8_t proto_id;
12374         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12375         uint32_t i, j, n;
12376         bool in_tunnel;
12377         int ret;
12378
12379         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12380             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12381                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12382                 return -1;
12383         }
12384
12385         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12386                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12387                 return 0;
12388         }
12389
12390         /* get information about new ptype num */
12391         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12392                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12393                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12394         if (ret) {
12395                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12396                 return ret;
12397         }
12398         if (!ptype_num) {
12399                 PMD_DRV_LOG(INFO, "No new ptype added");
12400                 return -1;
12401         }
12402
12403         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12404         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12405         if (!ptype) {
12406                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12407                 return -1;
12408         }
12409
12410         /* get information about new ptype list */
12411         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12412                                         (uint8_t *)ptype, buff_size,
12413                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12414         if (ret) {
12415                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12416                 rte_free(ptype);
12417                 return ret;
12418         }
12419
12420         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12421         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12422         if (!ptype_mapping) {
12423                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12424                 rte_free(ptype);
12425                 return -1;
12426         }
12427
12428         /* Update ptype mapping table. */
12429         for (i = 0; i < ptype_num; i++) {
12430                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12431                 ptype_mapping[i].sw_ptype = 0;
12432                 in_tunnel = false;
12433                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12434                         proto_id = ptype[i].protocols[j];
12435                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12436                                 continue;
12437                         for (n = 0; n < proto_num; n++) {
12438                                 if (proto[n].proto_id != proto_id)
12439                                         continue;
12440                                 memset(name, 0, sizeof(name));
12441                                 strcpy(name, proto[n].name);
12442                                 if (!strncasecmp(name, "PPPOE", 5))
12443                                         ptype_mapping[i].sw_ptype |=
12444                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12445                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12446                                          !in_tunnel) {
12447                                         ptype_mapping[i].sw_ptype |=
12448                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12449                                         ptype_mapping[i].sw_ptype |=
12450                                                 RTE_PTYPE_L4_FRAG;
12451                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12452                                            in_tunnel) {
12453                                         ptype_mapping[i].sw_ptype |=
12454                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12455                                         ptype_mapping[i].sw_ptype |=
12456                                                 RTE_PTYPE_INNER_L4_FRAG;
12457                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12458                                         ptype_mapping[i].sw_ptype |=
12459                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12460                                         in_tunnel = true;
12461                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12462                                            !in_tunnel)
12463                                         ptype_mapping[i].sw_ptype |=
12464                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12465                                 else if (!strncasecmp(name, "IPV4", 4) &&
12466                                          in_tunnel)
12467                                         ptype_mapping[i].sw_ptype |=
12468                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12469                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12470                                          !in_tunnel) {
12471                                         ptype_mapping[i].sw_ptype |=
12472                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12473                                         ptype_mapping[i].sw_ptype |=
12474                                                 RTE_PTYPE_L4_FRAG;
12475                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12476                                            in_tunnel) {
12477                                         ptype_mapping[i].sw_ptype |=
12478                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12479                                         ptype_mapping[i].sw_ptype |=
12480                                                 RTE_PTYPE_INNER_L4_FRAG;
12481                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12482                                         ptype_mapping[i].sw_ptype |=
12483                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12484                                         in_tunnel = true;
12485                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12486                                            !in_tunnel)
12487                                         ptype_mapping[i].sw_ptype |=
12488                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12489                                 else if (!strncasecmp(name, "IPV6", 4) &&
12490                                          in_tunnel)
12491                                         ptype_mapping[i].sw_ptype |=
12492                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12493                                 else if (!strncasecmp(name, "UDP", 3) &&
12494                                          !in_tunnel)
12495                                         ptype_mapping[i].sw_ptype |=
12496                                                 RTE_PTYPE_L4_UDP;
12497                                 else if (!strncasecmp(name, "UDP", 3) &&
12498                                          in_tunnel)
12499                                         ptype_mapping[i].sw_ptype |=
12500                                                 RTE_PTYPE_INNER_L4_UDP;
12501                                 else if (!strncasecmp(name, "TCP", 3) &&
12502                                          !in_tunnel)
12503                                         ptype_mapping[i].sw_ptype |=
12504                                                 RTE_PTYPE_L4_TCP;
12505                                 else if (!strncasecmp(name, "TCP", 3) &&
12506                                          in_tunnel)
12507                                         ptype_mapping[i].sw_ptype |=
12508                                                 RTE_PTYPE_INNER_L4_TCP;
12509                                 else if (!strncasecmp(name, "SCTP", 4) &&
12510                                          !in_tunnel)
12511                                         ptype_mapping[i].sw_ptype |=
12512                                                 RTE_PTYPE_L4_SCTP;
12513                                 else if (!strncasecmp(name, "SCTP", 4) &&
12514                                          in_tunnel)
12515                                         ptype_mapping[i].sw_ptype |=
12516                                                 RTE_PTYPE_INNER_L4_SCTP;
12517                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12518                                           !strncasecmp(name, "ICMPV6", 6)) &&
12519                                          !in_tunnel)
12520                                         ptype_mapping[i].sw_ptype |=
12521                                                 RTE_PTYPE_L4_ICMP;
12522                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12523                                           !strncasecmp(name, "ICMPV6", 6)) &&
12524                                          in_tunnel)
12525                                         ptype_mapping[i].sw_ptype |=
12526                                                 RTE_PTYPE_INNER_L4_ICMP;
12527                                 else if (!strncasecmp(name, "GTPC", 4)) {
12528                                         ptype_mapping[i].sw_ptype |=
12529                                                 RTE_PTYPE_TUNNEL_GTPC;
12530                                         in_tunnel = true;
12531                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12532                                         ptype_mapping[i].sw_ptype |=
12533                                                 RTE_PTYPE_TUNNEL_GTPU;
12534                                         in_tunnel = true;
12535                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12536                                         ptype_mapping[i].sw_ptype |=
12537                                                 RTE_PTYPE_TUNNEL_GRENAT;
12538                                         in_tunnel = true;
12539                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12540                                            !strncasecmp(name, "L2TPV2", 6)) {
12541                                         ptype_mapping[i].sw_ptype |=
12542                                                 RTE_PTYPE_TUNNEL_L2TP;
12543                                         in_tunnel = true;
12544                                 }
12545
12546                                 break;
12547                         }
12548                 }
12549         }
12550
12551         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12552                                                 ptype_num, 0);
12553         if (ret)
12554                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12555
12556         rte_free(ptype_mapping);
12557         rte_free(ptype);
12558         return ret;
12559 }
12560
12561 void
12562 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12563                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12564 {
12565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12566         uint32_t proto_num;
12567         struct rte_pmd_i40e_proto_info *proto;
12568         uint32_t buff_size;
12569         uint32_t i;
12570         int ret;
12571
12572         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12573             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12574                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12575                 return;
12576         }
12577
12578         /* get information about protocol number */
12579         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12580                                        (uint8_t *)&proto_num, sizeof(proto_num),
12581                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12582         if (ret) {
12583                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12584                 return;
12585         }
12586         if (!proto_num) {
12587                 PMD_DRV_LOG(INFO, "No new protocol added");
12588                 return;
12589         }
12590
12591         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12592         proto = rte_zmalloc("new_proto", buff_size, 0);
12593         if (!proto) {
12594                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12595                 return;
12596         }
12597
12598         /* get information about protocol list */
12599         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12600                                         (uint8_t *)proto, buff_size,
12601                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12602         if (ret) {
12603                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12604                 rte_free(proto);
12605                 return;
12606         }
12607
12608         /* Check if GTP is supported. */
12609         for (i = 0; i < proto_num; i++) {
12610                 if (!strncmp(proto[i].name, "GTP", 3)) {
12611                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12612                                 pf->gtp_support = true;
12613                         else
12614                                 pf->gtp_support = false;
12615                         break;
12616                 }
12617         }
12618
12619         /* Update customized pctype info */
12620         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12621                                             proto_num, proto, op);
12622         if (ret)
12623                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12624
12625         /* Update customized ptype info */
12626         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12627                                            proto_num, proto, op);
12628         if (ret)
12629                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12630
12631         rte_free(proto);
12632 }
12633
12634 /* Create a QinQ cloud filter
12635  *
12636  * The Fortville NIC has limited resources for tunnel filters,
12637  * so we can only reuse existing filters.
12638  *
12639  * In step 1 we define which Field Vector fields can be used for
12640  * filter types.
12641  * As we do not have the inner tag defined as a field,
12642  * we have to define it first, by reusing one of L1 entries.
12643  *
12644  * In step 2 we are replacing one of existing filter types with
12645  * a new one for QinQ.
12646  * As we reusing L1 and replacing L2, some of the default filter
12647  * types will disappear,which depends on L1 and L2 entries we reuse.
12648  *
12649  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12650  *
12651  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12652  *              later when we define the cloud filter.
12653  *      a.      Valid_flags.replace_cloud = 0
12654  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12655  *      c.      New_filter = 0x10
12656  *      d.      TR bit = 0xff (optional, not used here)
12657  *      e.      Buffer – 2 entries:
12658  *              i.      Byte 0 = 8 (outer vlan FV index).
12659  *                      Byte 1 = 0 (rsv)
12660  *                      Byte 2-3 = 0x0fff
12661  *              ii.     Byte 0 = 37 (inner vlan FV index).
12662  *                      Byte 1 =0 (rsv)
12663  *                      Byte 2-3 = 0x0fff
12664  *
12665  * Step 2:
12666  * 2.   Create cloud filter using two L1 filters entries: stag and
12667  *              new filter(outer vlan+ inner vlan)
12668  *      a.      Valid_flags.replace_cloud = 1
12669  *      b.      Old_filter = 1 (instead of outer IP)
12670  *      c.      New_filter = 0x10
12671  *      d.      Buffer – 2 entries:
12672  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12673  *                      Byte 1-3 = 0 (rsv)
12674  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12675  *                      Byte 9-11 = 0 (rsv)
12676  */
12677 static int
12678 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12679 {
12680         int ret = -ENOTSUP;
12681         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12682         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12683         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12684         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12685
12686         if (pf->support_multi_driver) {
12687                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12688                 return ret;
12689         }
12690
12691         /* Init */
12692         memset(&filter_replace, 0,
12693                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12694         memset(&filter_replace_buf, 0,
12695                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12696
12697         /* create L1 filter */
12698         filter_replace.old_filter_type =
12699                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12700         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12701         filter_replace.tr_bit = 0;
12702
12703         /* Prepare the buffer, 2 entries */
12704         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12705         filter_replace_buf.data[0] |=
12706                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12707         /* Field Vector 12b mask */
12708         filter_replace_buf.data[2] = 0xff;
12709         filter_replace_buf.data[3] = 0x0f;
12710         filter_replace_buf.data[4] =
12711                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12712         filter_replace_buf.data[4] |=
12713                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12714         /* Field Vector 12b mask */
12715         filter_replace_buf.data[6] = 0xff;
12716         filter_replace_buf.data[7] = 0x0f;
12717         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12718                         &filter_replace_buf);
12719         if (ret != I40E_SUCCESS)
12720                 return ret;
12721
12722         if (filter_replace.old_filter_type !=
12723             filter_replace.new_filter_type)
12724                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12725                             " original: 0x%x, new: 0x%x",
12726                             dev->device->name,
12727                             filter_replace.old_filter_type,
12728                             filter_replace.new_filter_type);
12729
12730         /* Apply the second L2 cloud filter */
12731         memset(&filter_replace, 0,
12732                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12733         memset(&filter_replace_buf, 0,
12734                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12735
12736         /* create L2 filter, input for L2 filter will be L1 filter  */
12737         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12738         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12739         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12740
12741         /* Prepare the buffer, 2 entries */
12742         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12743         filter_replace_buf.data[0] |=
12744                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12745         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12746         filter_replace_buf.data[4] |=
12747                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12748         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12749                         &filter_replace_buf);
12750         if (!ret && (filter_replace.old_filter_type !=
12751                      filter_replace.new_filter_type))
12752                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12753                             " original: 0x%x, new: 0x%x",
12754                             dev->device->name,
12755                             filter_replace.old_filter_type,
12756                             filter_replace.new_filter_type);
12757
12758         return ret;
12759 }
12760
12761 int
12762 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12763                    const struct rte_flow_action_rss *in)
12764 {
12765         if (in->key_len > RTE_DIM(out->key) ||
12766             in->queue_num > RTE_DIM(out->queue))
12767                 return -EINVAL;
12768         if (!in->key && in->key_len)
12769                 return -EINVAL;
12770         out->conf = (struct rte_flow_action_rss){
12771                 .func = in->func,
12772                 .level = in->level,
12773                 .types = in->types,
12774                 .key_len = in->key_len,
12775                 .queue_num = in->queue_num,
12776                 .queue = memcpy(out->queue, in->queue,
12777                                 sizeof(*in->queue) * in->queue_num),
12778         };
12779         if (in->key)
12780                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12781         return 0;
12782 }
12783
12784 int
12785 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12786                      const struct rte_flow_action_rss *with)
12787 {
12788         return (comp->func == with->func &&
12789                 comp->level == with->level &&
12790                 comp->types == with->types &&
12791                 comp->key_len == with->key_len &&
12792                 comp->queue_num == with->queue_num &&
12793                 !memcmp(comp->key, with->key, with->key_len) &&
12794                 !memcmp(comp->queue, with->queue,
12795                         sizeof(*with->queue) * with->queue_num));
12796 }
12797
12798 int
12799 i40e_config_rss_filter(struct i40e_pf *pf,
12800                 struct i40e_rte_flow_rss_conf *conf, bool add)
12801 {
12802         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12803         uint32_t i, lut = 0;
12804         uint16_t j, num;
12805         struct rte_eth_rss_conf rss_conf = {
12806                 .rss_key = conf->conf.key_len ?
12807                         (void *)(uintptr_t)conf->conf.key : NULL,
12808                 .rss_key_len = conf->conf.key_len,
12809                 .rss_hf = conf->conf.types,
12810         };
12811         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12812
12813         if (!add) {
12814                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12815                         i40e_pf_disable_rss(pf);
12816                         memset(rss_info, 0,
12817                                 sizeof(struct i40e_rte_flow_rss_conf));
12818                         return 0;
12819                 }
12820                 return -EINVAL;
12821         }
12822
12823         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12824          * It's necessary to calculate the actual PF queues that are configured.
12825          */
12826         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12827                 num = i40e_pf_calc_configured_queues_num(pf);
12828         else
12829                 num = pf->dev_data->nb_rx_queues;
12830
12831         num = RTE_MIN(num, conf->conf.queue_num);
12832         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12833                         num);
12834
12835         if (num == 0) {
12836                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12837                 return -ENOTSUP;
12838         }
12839
12840         /* Fill in redirection table */
12841         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12842                 if (j == num)
12843                         j = 0;
12844                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12845                         hw->func_caps.rss_table_entry_width) - 1));
12846                 if ((i & 3) == 3)
12847                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12848         }
12849
12850         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12851                 i40e_pf_disable_rss(pf);
12852                 return 0;
12853         }
12854         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12855                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12856                 /* Random default keys */
12857                 static uint32_t rss_key_default[] = {0x6b793944,
12858                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12859                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12860                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12861
12862                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12863                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12864                                                         sizeof(uint32_t);
12865                 PMD_DRV_LOG(INFO,
12866                         "No valid RSS key config for i40e, using default\n");
12867         }
12868
12869         i40e_hw_rss_hash_set(pf, &rss_conf);
12870
12871         if (i40e_rss_conf_init(rss_info, &conf->conf))
12872                 return -EINVAL;
12873
12874         return 0;
12875 }
12876
12877 RTE_INIT(i40e_init_log)
12878 {
12879         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12880         if (i40e_logtype_init >= 0)
12881                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12882         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12883         if (i40e_logtype_driver >= 0)
12884                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12885
12886 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
12887         i40e_logtype_rx = rte_log_register("pmd.net.i40e.rx");
12888         if (i40e_logtype_rx >= 0)
12889                 rte_log_set_level(i40e_logtype_rx, RTE_LOG_DEBUG);
12890 #endif
12891
12892 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
12893         i40e_logtype_tx = rte_log_register("pmd.net.i40e.tx");
12894         if (i40e_logtype_tx >= 0)
12895                 rte_log_set_level(i40e_logtype_tx, RTE_LOG_DEBUG);
12896 #endif
12897
12898 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
12899         i40e_logtype_tx_free = rte_log_register("pmd.net.i40e.tx_free");
12900         if (i40e_logtype_tx_free >= 0)
12901                 rte_log_set_level(i40e_logtype_tx_free, RTE_LOG_DEBUG);
12902 #endif
12903 }
12904
12905 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12906                               ETH_I40E_FLOATING_VEB_ARG "=1"
12907                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12908                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12909                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12910                               ETH_I40E_USE_LATEST_VEC "=0|1");