drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47
  48 #define I40E_CLEAR_PXE_WAIT_MS     200
  49
  50 /* Maximun number of capability elements */
  51 #define I40E_MAX_CAP_ELE_NUM       128
  52
  53 /* Wait count and interval */
  54 #define I40E_CHK_Q_ENA_COUNT       1000
  55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  56
  57 /* Maximun number of VSI */
  58 #define I40E_MAX_NUM_VSIS          (384UL)
  59
  60 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  61
  62 /* Flow control default timer */
  63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  64
  65 /* Flow control enable fwd bit */
  66 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  67
  68 /* Receive Packet Buffer size */
  69 #define I40E_RXPBSIZE (968 * 1024)
  70
  71 /* Kilobytes shift */
  72 #define I40E_KILOSHIFT 10
  73
  74 /* Flow control default high water */
  75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Flow control default low water */
  78 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  79
  80 /* Receive Average Packet Size in Byte*/
  81 #define I40E_PACKET_AVERAGE_SIZE 128
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  94
  95 #define I40E_FLOW_TYPES ( \
  96         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 107
 108 /* Additional timesync values. */
 109 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 110 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 111 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 112 #define I40E_PRTTSYN_TSYNENA     0x80000000
 113 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 114 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 /**
 117  * Below are values for writing un-exposed registers suggested
 118  * by silicon experts
 119  */
 120 /* Destination MAC address */
 121 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 122 /* Source MAC address */
 123 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 128 /* Single VLAN tag in the inner L2 header */
 129 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 130 /* Source IPv4 address */
 131 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 132 /* Destination IPv4 address */
 133 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 134 /* Source IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 136 /* Destination IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 138 /* IPv4 Protocol for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 140 /* IPv4 Time to Live for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 142 /* IPv4 Type of Service (TOS) */
 143 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 144 /* IPv4 Protocol */
 145 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 146 /* IPv4 Time to Live */
 147 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 148 /* Source IPv6 address */
 149 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 150 /* Destination IPv6 address */
 151 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 152 /* IPv6 Traffic Class (TC) */
 153 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 154 /* IPv6 Next Header */
 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 156 /* IPv6 Hop Limit */
 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 158 /* Source L4 port */
 159 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 160 /* Destination L4 port */
 161 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 162 /* SCTP verification tag */
 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 166 /* Source port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 168 /* Destination port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 170 /* UDP Tunneling ID, NVGRE/GRE key */
 171 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 172 /* Last ether type */
 173 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 174 /* Tunneling outer destination IPv4 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 176 /* Tunneling outer destination IPv6 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 178 /* 1st word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 180 /* 2nd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 182 /* 3rd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 184 /* 4th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 186 /* 5th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 188 /* 6th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 190 /* 7th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 192 /* 8th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 194 /* all 8 words flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 196 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 197
 198 #define I40E_TRANSLATE_INSET 0
 199 #define I40E_TRANSLATE_REG   1
 200
 201 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 202 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 203 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 204 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 207
 208 /* PCI offset for querying capability */
 209 #define PCI_DEV_CAP_REG            0xA4
 210 /* PCI offset for enabling/disabling Extended Tag */
 211 #define PCI_DEV_CTRL_REG           0xA8
 212 /* Bit mask of Extended Tag capability */
 213 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 214 /* Bit shift of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 216 /* Bit mask of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 218
 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 221 static int i40e_dev_configure(struct rte_eth_dev *dev);
 222 static int i40e_dev_start(struct rte_eth_dev *dev);
 223 static void i40e_dev_stop(struct rte_eth_dev *dev);
 224 static void i40e_dev_close(struct rte_eth_dev *dev);
 225 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_stats *stats);
 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_xstat *xstats, unsigned n);
 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 237                                      struct rte_eth_xstat_name *xstats_names,
 238                                      unsigned limit);
 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 240 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 241                                 char *fw_version, size_t fw_size);
 242 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 243                               struct rte_eth_dev_info *dev_info);
 244 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 245                                 uint16_t vlan_id,
 246                                 int on);
 247 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 248                               enum rte_vlan_type vlan_type,
 249                               uint16_t tpid);
 250 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 251 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 252                                       uint16_t queue,
 253                                       int on);
 254 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 255 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 256 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 257 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 258                               struct rte_eth_fc_conf *fc_conf);
 259 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 262                                        struct rte_eth_pfc_conf *pfc_conf);
 263 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 264                             struct rte_ether_addr *mac_addr,
 265                             uint32_t index,
 266                             uint32_t pool);
 267 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 268 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 269                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 270                                     uint16_t reta_size);
 271 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 272                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 273                                    uint16_t reta_size);
 274
 275 static int i40e_get_cap(struct i40e_hw *hw);
 276 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 277 static int i40e_pf_setup(struct i40e_pf *pf);
 278 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 279 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 280 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 281 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 282                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 283 static void i40e_stat_update_48(struct i40e_hw *hw,
 284                                uint32_t hireg,
 285                                uint32_t loreg,
 286                                bool offset_loaded,
 287                                uint64_t *offset,
 288                                uint64_t *stat);
 289 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 290 static void i40e_dev_interrupt_handler(void *param);
 291 static void i40e_dev_alarm_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static int i40e_get_module_info(struct rte_eth_dev *dev,
 373                                 struct rte_eth_dev_module_info *modinfo);
 374 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 375                                   struct rte_dev_eeprom_info *info);
 376
 377 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 378                                       struct rte_ether_addr *mac_addr);
 379
 380 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 381
 382 static int i40e_ethertype_filter_convert(
 383         const struct rte_eth_ethertype_filter *input,
 384         struct i40e_ethertype_filter *filter);
 385 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 386                                    struct i40e_ethertype_filter *filter);
 387
 388 static int i40e_tunnel_filter_convert(
 389         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 390         struct i40e_tunnel_filter *tunnel_filter);
 391 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 392                                 struct i40e_tunnel_filter *tunnel_filter);
 393 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 394
 395 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 396 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 397 static void i40e_filter_restore(struct i40e_pf *pf);
 398 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 399
 400 int i40e_logtype_init;
 401 int i40e_logtype_driver;
 402
 403 static const char *const valid_keys[] = {
 404         ETH_I40E_FLOATING_VEB_ARG,
 405         ETH_I40E_FLOATING_VEB_LIST_ARG,
 406         ETH_I40E_SUPPORT_MULTI_DRIVER,
 407         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 408         ETH_I40E_USE_LATEST_VEC,
 409         NULL};
 410
 411 static const struct rte_pci_id pci_id_i40e_map[] = {
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 435         { .vendor_id = 0, /* sentinel */ },
 436 };
 437
 438 static const struct eth_dev_ops i40e_eth_dev_ops = {
 439         .dev_configure                = i40e_dev_configure,
 440         .dev_start                    = i40e_dev_start,
 441         .dev_stop                     = i40e_dev_stop,
 442         .dev_close                    = i40e_dev_close,
 443         .dev_reset                    = i40e_dev_reset,
 444         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 445         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 446         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 447         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 448         .dev_set_link_up              = i40e_dev_set_link_up,
 449         .dev_set_link_down            = i40e_dev_set_link_down,
 450         .link_update                  = i40e_dev_link_update,
 451         .stats_get                    = i40e_dev_stats_get,
 452         .xstats_get                   = i40e_dev_xstats_get,
 453         .xstats_get_names             = i40e_dev_xstats_get_names,
 454         .stats_reset                  = i40e_dev_stats_reset,
 455         .xstats_reset                 = i40e_dev_stats_reset,
 456         .fw_version_get               = i40e_fw_version_get,
 457         .dev_infos_get                = i40e_dev_info_get,
 458         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 459         .vlan_filter_set              = i40e_vlan_filter_set,
 460         .vlan_tpid_set                = i40e_vlan_tpid_set,
 461         .vlan_offload_set             = i40e_vlan_offload_set,
 462         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 463         .vlan_pvid_set                = i40e_vlan_pvid_set,
 464         .rx_queue_start               = i40e_dev_rx_queue_start,
 465         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 466         .tx_queue_start               = i40e_dev_tx_queue_start,
 467         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 468         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 469         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 470         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 471         .rx_queue_release             = i40e_dev_rx_queue_release,
 472         .rx_queue_count               = i40e_dev_rx_queue_count,
 473         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 474         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 475         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 476         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 477         .tx_queue_release             = i40e_dev_tx_queue_release,
 478         .dev_led_on                   = i40e_dev_led_on,
 479         .dev_led_off                  = i40e_dev_led_off,
 480         .flow_ctrl_get                = i40e_flow_ctrl_get,
 481         .flow_ctrl_set                = i40e_flow_ctrl_set,
 482         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 483         .mac_addr_add                 = i40e_macaddr_add,
 484         .mac_addr_remove              = i40e_macaddr_remove,
 485         .reta_update                  = i40e_dev_rss_reta_update,
 486         .reta_query                   = i40e_dev_rss_reta_query,
 487         .rss_hash_update              = i40e_dev_rss_hash_update,
 488         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 489         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 490         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 491         .filter_ctrl                  = i40e_dev_filter_ctrl,
 492         .rxq_info_get                 = i40e_rxq_info_get,
 493         .txq_info_get                 = i40e_txq_info_get,
 494         .mirror_rule_set              = i40e_mirror_rule_set,
 495         .mirror_rule_reset            = i40e_mirror_rule_reset,
 496         .timesync_enable              = i40e_timesync_enable,
 497         .timesync_disable             = i40e_timesync_disable,
 498         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 499         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 500         .get_dcb_info                 = i40e_dev_get_dcb_info,
 501         .timesync_adjust_time         = i40e_timesync_adjust_time,
 502         .timesync_read_time           = i40e_timesync_read_time,
 503         .timesync_write_time          = i40e_timesync_write_time,
 504         .get_reg                      = i40e_get_regs,
 505         .get_eeprom_length            = i40e_get_eeprom_length,
 506         .get_eeprom                   = i40e_get_eeprom,
 507         .get_module_info              = i40e_get_module_info,
 508         .get_module_eeprom            = i40e_get_module_eeprom,
 509         .mac_addr_set                 = i40e_set_default_mac_addr,
 510         .mtu_set                      = i40e_dev_mtu_set,
 511         .tm_ops_get                   = i40e_tm_ops_get,
 512 };
 513
 514 /* store statistics names and its offset in stats structure */
 515 struct rte_i40e_xstats_name_off {
 516         char name[RTE_ETH_XSTATS_NAME_SIZE];
 517         unsigned offset;
 518 };
 519
 520 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 521         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 522         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 523         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 524         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 525         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 526                 rx_unknown_protocol)},
 527         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 528         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 529         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 530         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 531 };
 532
 533 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 534                 sizeof(rte_i40e_stats_strings[0]))
 535
 536 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 537         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 538                 tx_dropped_link_down)},
 539         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 540         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 541                 illegal_bytes)},
 542         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 543         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 544                 mac_local_faults)},
 545         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 546                 mac_remote_faults)},
 547         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 548                 rx_length_errors)},
 549         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 550         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 551         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 552         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 553         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 554         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 555                 rx_size_127)},
 556         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 557                 rx_size_255)},
 558         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 559                 rx_size_511)},
 560         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_1023)},
 562         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_1522)},
 564         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_big)},
 566         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 567                 rx_undersize)},
 568         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 569                 rx_oversize)},
 570         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 571                 mac_short_packet_dropped)},
 572         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_fragments)},
 574         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 575         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 576         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 577                 tx_size_127)},
 578         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 579                 tx_size_255)},
 580         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 581                 tx_size_511)},
 582         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_1023)},
 584         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_1522)},
 586         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_big)},
 588         {"rx_flow_director_atr_match_packets",
 589                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 590         {"rx_flow_director_sb_match_packets",
 591                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 592         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 593                 tx_lpi_status)},
 594         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 595                 rx_lpi_status)},
 596         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 597                 tx_lpi_count)},
 598         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 599                 rx_lpi_count)},
 600 };
 601
 602 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 603                 sizeof(rte_i40e_hw_port_strings[0]))
 604
 605 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 606         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 607                 priority_xon_rx)},
 608         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 609                 priority_xoff_rx)},
 610 };
 611
 612 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 613                 sizeof(rte_i40e_rxq_prio_strings[0]))
 614
 615 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 616         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 617                 priority_xon_tx)},
 618         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 619                 priority_xoff_tx)},
 620         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 621                 priority_xon_2_xoff)},
 622 };
 623
 624 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 625                 sizeof(rte_i40e_txq_prio_strings[0]))
 626
 627 static int
 628 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 629         struct rte_pci_device *pci_dev)
 630 {
 631         char name[RTE_ETH_NAME_MAX_LEN];
 632         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 633         int i, retval;
 634
 635         if (pci_dev->device.devargs) {
 636                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 637                                 &eth_da);
 638                 if (retval)
 639                         return retval;
 640         }
 641
 642         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 643                 sizeof(struct i40e_adapter),
 644                 eth_dev_pci_specific_init, pci_dev,
 645                 eth_i40e_dev_init, NULL);
 646
 647         if (retval || eth_da.nb_representor_ports < 1)
 648                 return retval;
 649
 650         /* probe VF representor ports */
 651         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 652                 pci_dev->device.name);
 653
 654         if (pf_ethdev == NULL)
 655                 return -ENODEV;
 656
 657         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 658                 struct i40e_vf_representor representor = {
 659                         .vf_id = eth_da.representor_ports[i],
 660                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 661                                 pf_ethdev->data->dev_private)->switch_domain_id,
 662                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 663                                 pf_ethdev->data->dev_private)
 664                 };
 665
 666                 /* representor port net_bdf_port */
 667                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 668                         pci_dev->device.name, eth_da.representor_ports[i]);
 669
 670                 retval = rte_eth_dev_create(&pci_dev->device, name,
 671                         sizeof(struct i40e_vf_representor), NULL, NULL,
 672                         i40e_vf_representor_init, &representor);
 673
 674                 if (retval)
 675                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 676                                 "representor %s.", name);
 677         }
 678
 679         return 0;
 680 }
 681
 682 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 683 {
 684         struct rte_eth_dev *ethdev;
 685
 686         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 687         if (!ethdev)
 688                 return -ENODEV;
 689
 690
 691         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 692                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 693         else
 694                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 695 }
 696
 697 static struct rte_pci_driver rte_i40e_pmd = {
 698         .id_table = pci_id_i40e_map,
 699         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 700                      RTE_PCI_DRV_IOVA_AS_VA,
 701         .probe = eth_i40e_pci_probe,
 702         .remove = eth_i40e_pci_remove,
 703 };
 704
 705 static inline void
 706 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 707                          uint32_t reg_val)
 708 {
 709         uint32_t ori_reg_val;
 710         struct rte_eth_dev *dev;
 711
 712         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 713         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 714         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 715         if (ori_reg_val != reg_val)
 716                 PMD_DRV_LOG(WARNING,
 717                             "i40e device %s changed global register [0x%08x]."
 718                             " original: 0x%08x, new: 0x%08x",
 719                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 720 }
 721
 722 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 723 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 724 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 725
 726 #ifndef I40E_GLQF_ORT
 727 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 728 #endif
 729 #ifndef I40E_GLQF_PIT
 730 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 731 #endif
 732 #ifndef I40E_GLQF_L3_MAP
 733 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 734 #endif
 735
 736 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 737 {
 738         /*
 739          * Initialize registers for parsing packet type of QinQ
 740          * This should be removed from code once proper
 741          * configuration API is added to avoid configuration conflicts
 742          * between ports of the same device.
 743          */
 744         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 745         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 746 }
 747
 748 static inline void i40e_config_automask(struct i40e_pf *pf)
 749 {
 750         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 751         uint32_t val;
 752
 753         /* INTENA flag is not auto-cleared for interrupt */
 754         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 755         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 756                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 757
 758         /* If support multi-driver, PF will use INT0. */
 759         if (!pf->support_multi_driver)
 760                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 761
 762         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 763 }
 764
 765 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 766
 767 /*
 768  * Add a ethertype filter to drop all flow control frames transmitted
 769  * from VSIs.
 770 */
 771 static void
 772 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 773 {
 774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 775         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 776                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 777                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 778         int ret;
 779
 780         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 781                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 782                                 pf->main_vsi_seid, 0,
 783                                 TRUE, NULL, NULL);
 784         if (ret)
 785                 PMD_INIT_LOG(ERR,
 786                         "Failed to add filter to drop flow control frames from VSIs.");
 787 }
 788
 789 static int
 790 floating_veb_list_handler(__rte_unused const char *key,
 791                           const char *floating_veb_value,
 792                           void *opaque)
 793 {
 794         int idx = 0;
 795         unsigned int count = 0;
 796         char *end = NULL;
 797         int min, max;
 798         bool *vf_floating_veb = opaque;
 799
 800         while (isblank(*floating_veb_value))
 801                 floating_veb_value++;
 802
 803         /* Reset floating VEB configuration for VFs */
 804         for (idx = 0; idx < I40E_MAX_VF; idx++)
 805                 vf_floating_veb[idx] = false;
 806
 807         min = I40E_MAX_VF;
 808         do {
 809                 while (isblank(*floating_veb_value))
 810                         floating_veb_value++;
 811                 if (*floating_veb_value == '\0')
 812                         return -1;
 813                 errno = 0;
 814                 idx = strtoul(floating_veb_value, &end, 10);
 815                 if (errno || end == NULL)
 816                         return -1;
 817                 while (isblank(*end))
 818                         end++;
 819                 if (*end == '-') {
 820                         min = idx;
 821                 } else if ((*end == ';') || (*end == '\0')) {
 822                         max = idx;
 823                         if (min == I40E_MAX_VF)
 824                                 min = idx;
 825                         if (max >= I40E_MAX_VF)
 826                                 max = I40E_MAX_VF - 1;
 827                         for (idx = min; idx <= max; idx++) {
 828                                 vf_floating_veb[idx] = true;
 829                                 count++;
 830                         }
 831                         min = I40E_MAX_VF;
 832                 } else {
 833                         return -1;
 834                 }
 835                 floating_veb_value = end + 1;
 836         } while (*end != '\0');
 837
 838         if (count == 0)
 839                 return -1;
 840
 841         return 0;
 842 }
 843
 844 static void
 845 config_vf_floating_veb(struct rte_devargs *devargs,
 846                        uint16_t floating_veb,
 847                        bool *vf_floating_veb)
 848 {
 849         struct rte_kvargs *kvlist;
 850         int i;
 851         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 852
 853         if (!floating_veb)
 854                 return;
 855         /* All the VFs attach to the floating VEB by default
 856          * when the floating VEB is enabled.
 857          */
 858         for (i = 0; i < I40E_MAX_VF; i++)
 859                 vf_floating_veb[i] = true;
 860
 861         if (devargs == NULL)
 862                 return;
 863
 864         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 865         if (kvlist == NULL)
 866                 return;
 867
 868         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 869                 rte_kvargs_free(kvlist);
 870                 return;
 871         }
 872         /* When the floating_veb_list parameter exists, all the VFs
 873          * will attach to the legacy VEB firstly, then configure VFs
 874          * to the floating VEB according to the floating_veb_list.
 875          */
 876         if (rte_kvargs_process(kvlist, floating_veb_list,
 877                                floating_veb_list_handler,
 878                                vf_floating_veb) < 0) {
 879                 rte_kvargs_free(kvlist);
 880                 return;
 881         }
 882         rte_kvargs_free(kvlist);
 883 }
 884
 885 static int
 886 i40e_check_floating_handler(__rte_unused const char *key,
 887                             const char *value,
 888                             __rte_unused void *opaque)
 889 {
 890         if (strcmp(value, "1"))
 891                 return -1;
 892
 893         return 0;
 894 }
 895
 896 static int
 897 is_floating_veb_supported(struct rte_devargs *devargs)
 898 {
 899         struct rte_kvargs *kvlist;
 900         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 901
 902         if (devargs == NULL)
 903                 return 0;
 904
 905         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 906         if (kvlist == NULL)
 907                 return 0;
 908
 909         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 910                 rte_kvargs_free(kvlist);
 911                 return 0;
 912         }
 913         /* Floating VEB is enabled when there's key-value:
 914          * enable_floating_veb=1
 915          */
 916         if (rte_kvargs_process(kvlist, floating_veb_key,
 917                                i40e_check_floating_handler, NULL) < 0) {
 918                 rte_kvargs_free(kvlist);
 919                 return 0;
 920         }
 921         rte_kvargs_free(kvlist);
 922
 923         return 1;
 924 }
 925
 926 static void
 927 config_floating_veb(struct rte_eth_dev *dev)
 928 {
 929         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 931         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 932
 933         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 934
 935         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 936                 pf->floating_veb =
 937                         is_floating_veb_supported(pci_dev->device.devargs);
 938                 config_vf_floating_veb(pci_dev->device.devargs,
 939                                        pf->floating_veb,
 940                                        pf->floating_veb_list);
 941         } else {
 942                 pf->floating_veb = false;
 943         }
 944 }
 945
 946 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 947 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 948
 949 static int
 950 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 951 {
 952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 953         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 954         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 955         int ret;
 956
 957         struct rte_hash_parameters ethertype_hash_params = {
 958                 .name = ethertype_hash_name,
 959                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 960                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 961                 .hash_func = rte_hash_crc,
 962                 .hash_func_init_val = 0,
 963                 .socket_id = rte_socket_id(),
 964         };
 965
 966         /* Initialize ethertype filter rule list and hash */
 967         TAILQ_INIT(&ethertype_rule->ethertype_list);
 968         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 969                  "ethertype_%s", dev->device->name);
 970         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 971         if (!ethertype_rule->hash_table) {
 972                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 973                 return -EINVAL;
 974         }
 975         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 976                                        sizeof(struct i40e_ethertype_filter *) *
 977                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 978                                        0);
 979         if (!ethertype_rule->hash_map) {
 980                 PMD_INIT_LOG(ERR,
 981                              "Failed to allocate memory for ethertype hash map!");
 982                 ret = -ENOMEM;
 983                 goto err_ethertype_hash_map_alloc;
 984         }
 985
 986         return 0;
 987
 988 err_ethertype_hash_map_alloc:
 989         rte_hash_free(ethertype_rule->hash_table);
 990
 991         return ret;
 992 }
 993
 994 static int
 995 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 996 {
 997         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 998         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 999         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1000         int ret;
1001
1002         struct rte_hash_parameters tunnel_hash_params = {
1003                 .name = tunnel_hash_name,
1004                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1005                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1006                 .hash_func = rte_hash_crc,
1007                 .hash_func_init_val = 0,
1008                 .socket_id = rte_socket_id(),
1009         };
1010
1011         /* Initialize tunnel filter rule list and hash */
1012         TAILQ_INIT(&tunnel_rule->tunnel_list);
1013         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1014                  "tunnel_%s", dev->device->name);
1015         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1016         if (!tunnel_rule->hash_table) {
1017                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1018                 return -EINVAL;
1019         }
1020         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1021                                     sizeof(struct i40e_tunnel_filter *) *
1022                                     I40E_MAX_TUNNEL_FILTER_NUM,
1023                                     0);
1024         if (!tunnel_rule->hash_map) {
1025                 PMD_INIT_LOG(ERR,
1026                              "Failed to allocate memory for tunnel hash map!");
1027                 ret = -ENOMEM;
1028                 goto err_tunnel_hash_map_alloc;
1029         }
1030
1031         return 0;
1032
1033 err_tunnel_hash_map_alloc:
1034         rte_hash_free(tunnel_rule->hash_table);
1035
1036         return ret;
1037 }
1038
1039 static int
1040 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1041 {
1042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1043         struct i40e_fdir_info *fdir_info = &pf->fdir;
1044         char fdir_hash_name[RTE_HASH_NAMESIZE];
1045         int ret;
1046
1047         struct rte_hash_parameters fdir_hash_params = {
1048                 .name = fdir_hash_name,
1049                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1050                 .key_len = sizeof(struct i40e_fdir_input),
1051                 .hash_func = rte_hash_crc,
1052                 .hash_func_init_val = 0,
1053                 .socket_id = rte_socket_id(),
1054         };
1055
1056         /* Initialize flow director filter rule list and hash */
1057         TAILQ_INIT(&fdir_info->fdir_list);
1058         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1059                  "fdir_%s", dev->device->name);
1060         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1061         if (!fdir_info->hash_table) {
1062                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1063                 return -EINVAL;
1064         }
1065         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1066                                           sizeof(struct i40e_fdir_filter *) *
1067                                           I40E_MAX_FDIR_FILTER_NUM,
1068                                           0);
1069         if (!fdir_info->hash_map) {
1070                 PMD_INIT_LOG(ERR,
1071                              "Failed to allocate memory for fdir hash map!");
1072                 ret = -ENOMEM;
1073                 goto err_fdir_hash_map_alloc;
1074         }
1075         return 0;
1076
1077 err_fdir_hash_map_alloc:
1078         rte_hash_free(fdir_info->hash_table);
1079
1080         return ret;
1081 }
1082
1083 static void
1084 i40e_init_customized_info(struct i40e_pf *pf)
1085 {
1086         int i;
1087
1088         /* Initialize customized pctype */
1089         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1090                 pf->customized_pctype[i].index = i;
1091                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1092                 pf->customized_pctype[i].valid = false;
1093         }
1094
1095         pf->gtp_support = false;
1096 }
1097
1098 void
1099 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1100 {
1101         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1102         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1103         struct i40e_queue_regions *info = &pf->queue_region;
1104         uint16_t i;
1105
1106         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1107                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1108
1109         memset(info, 0, sizeof(struct i40e_queue_regions));
1110 }
1111
1112 static int
1113 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1114                                const char *value,
1115                                void *opaque)
1116 {
1117         struct i40e_pf *pf;
1118         unsigned long support_multi_driver;
1119         char *end;
1120
1121         pf = (struct i40e_pf *)opaque;
1122
1123         errno = 0;
1124         support_multi_driver = strtoul(value, &end, 10);
1125         if (errno != 0 || end == value || *end != 0) {
1126                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1127                 return -(EINVAL);
1128         }
1129
1130         if (support_multi_driver == 1 || support_multi_driver == 0)
1131                 pf->support_multi_driver = (bool)support_multi_driver;
1132         else
1133                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1134                             "enable global configuration by default."
1135                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1136         return 0;
1137 }
1138
1139 static int
1140 i40e_support_multi_driver(struct rte_eth_dev *dev)
1141 {
1142         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1143         struct rte_kvargs *kvlist;
1144         int kvargs_count;
1145
1146         /* Enable global configuration by default */
1147         pf->support_multi_driver = false;
1148
1149         if (!dev->device->devargs)
1150                 return 0;
1151
1152         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1153         if (!kvlist)
1154                 return -EINVAL;
1155
1156         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1157         if (!kvargs_count) {
1158                 rte_kvargs_free(kvlist);
1159                 return 0;
1160         }
1161
1162         if (kvargs_count > 1)
1163                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1164                             "the first invalid or last valid one is used !",
1165                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1166
1167         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1168                                i40e_parse_multi_drv_handler, pf) < 0) {
1169                 rte_kvargs_free(kvlist);
1170                 return -EINVAL;
1171         }
1172
1173         rte_kvargs_free(kvlist);
1174         return 0;
1175 }
1176
1177 static int
1178 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1179                                     uint32_t reg_addr, uint64_t reg_val,
1180                                     struct i40e_asq_cmd_details *cmd_details)
1181 {
1182         uint64_t ori_reg_val;
1183         struct rte_eth_dev *dev;
1184         int ret;
1185
1186         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1187         if (ret != I40E_SUCCESS) {
1188                 PMD_DRV_LOG(ERR,
1189                             "Fail to debug read from 0x%08x",
1190                             reg_addr);
1191                 return -EIO;
1192         }
1193         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1194
1195         if (ori_reg_val != reg_val)
1196                 PMD_DRV_LOG(WARNING,
1197                             "i40e device %s changed global register [0x%08x]."
1198                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1199                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1200
1201         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1202 }
1203
1204 static int
1205 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1206                                 const char *value,
1207                                 void *opaque)
1208 {
1209         struct i40e_adapter *ad = opaque;
1210         int use_latest_vec;
1211
1212         use_latest_vec = atoi(value);
1213
1214         if (use_latest_vec != 0 && use_latest_vec != 1)
1215                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1216
1217         ad->use_latest_vec = (uint8_t)use_latest_vec;
1218
1219         return 0;
1220 }
1221
1222 static int
1223 i40e_use_latest_vec(struct rte_eth_dev *dev)
1224 {
1225         struct i40e_adapter *ad =
1226                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1227         struct rte_kvargs *kvlist;
1228         int kvargs_count;
1229
1230         ad->use_latest_vec = false;
1231
1232         if (!dev->device->devargs)
1233                 return 0;
1234
1235         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1236         if (!kvlist)
1237                 return -EINVAL;
1238
1239         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1240         if (!kvargs_count) {
1241                 rte_kvargs_free(kvlist);
1242                 return 0;
1243         }
1244
1245         if (kvargs_count > 1)
1246                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1247                             "the first invalid or last valid one is used !",
1248                             ETH_I40E_USE_LATEST_VEC);
1249
1250         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1251                                 i40e_parse_latest_vec_handler, ad) < 0) {
1252                 rte_kvargs_free(kvlist);
1253                 return -EINVAL;
1254         }
1255
1256         rte_kvargs_free(kvlist);
1257         return 0;
1258 }
1259
1260 #define I40E_ALARM_INTERVAL 50000 /* us */
1261
1262 static int
1263 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1264 {
1265         struct rte_pci_device *pci_dev;
1266         struct rte_intr_handle *intr_handle;
1267         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1268         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1269         struct i40e_vsi *vsi;
1270         int ret;
1271         uint32_t len, val;
1272         uint8_t aq_fail = 0;
1273
1274         PMD_INIT_FUNC_TRACE();
1275
1276         dev->dev_ops = &i40e_eth_dev_ops;
1277         dev->rx_pkt_burst = i40e_recv_pkts;
1278         dev->tx_pkt_burst = i40e_xmit_pkts;
1279         dev->tx_pkt_prepare = i40e_prep_pkts;
1280
1281         /* for secondary processes, we don't initialise any further as primary
1282          * has already done this work. Only check we don't need a different
1283          * RX function */
1284         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1285                 i40e_set_rx_function(dev);
1286                 i40e_set_tx_function(dev);
1287                 return 0;
1288         }
1289         i40e_set_default_ptype_table(dev);
1290         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1291         intr_handle = &pci_dev->intr_handle;
1292
1293         rte_eth_copy_pci_info(dev, pci_dev);
1294
1295         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1296         pf->adapter->eth_dev = dev;
1297         pf->dev_data = dev->data;
1298
1299         hw->back = I40E_PF_TO_ADAPTER(pf);
1300         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1301         if (!hw->hw_addr) {
1302                 PMD_INIT_LOG(ERR,
1303                         "Hardware is not available, as address is NULL");
1304                 return -ENODEV;
1305         }
1306
1307         hw->vendor_id = pci_dev->id.vendor_id;
1308         hw->device_id = pci_dev->id.device_id;
1309         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1310         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1311         hw->bus.device = pci_dev->addr.devid;
1312         hw->bus.func = pci_dev->addr.function;
1313         hw->adapter_stopped = 0;
1314         hw->adapter_closed = 0;
1315
1316         /*
1317          * Switch Tag value should not be identical to either the First Tag
1318          * or Second Tag values. So set something other than common Ethertype
1319          * for internal switching.
1320          */
1321         hw->switch_tag = 0xffff;
1322
1323         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1324         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1325                 PMD_INIT_LOG(ERR, "\nERROR: "
1326                         "Firmware recovery mode detected. Limiting functionality.\n"
1327                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1328                         "User Guide for details on firmware recovery mode.");
1329                 return -EIO;
1330         }
1331
1332         /* Check if need to support multi-driver */
1333         i40e_support_multi_driver(dev);
1334         /* Check if users want the latest supported vec path */
1335         i40e_use_latest_vec(dev);
1336
1337         /* Make sure all is clean before doing PF reset */
1338         i40e_clear_hw(hw);
1339
1340         /* Reset here to make sure all is clean for each PF */
1341         ret = i40e_pf_reset(hw);
1342         if (ret) {
1343                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1344                 return ret;
1345         }
1346
1347         /* Initialize the shared code (base driver) */
1348         ret = i40e_init_shared_code(hw);
1349         if (ret) {
1350                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1351                 return ret;
1352         }
1353
1354         /* Initialize the parameters for adminq */
1355         i40e_init_adminq_parameter(hw);
1356         ret = i40e_init_adminq(hw);
1357         if (ret != I40E_SUCCESS) {
1358                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1359                 return -EIO;
1360         }
1361         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1362                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1363                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1364                      ((hw->nvm.version >> 12) & 0xf),
1365                      ((hw->nvm.version >> 4) & 0xff),
1366                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1367
1368         /* Initialize the hardware */
1369         i40e_hw_init(dev);
1370
1371         i40e_config_automask(pf);
1372
1373         i40e_set_default_pctype_table(dev);
1374
1375         /*
1376          * To work around the NVM issue, initialize registers
1377          * for packet type of QinQ by software.
1378          * It should be removed once issues are fixed in NVM.
1379          */
1380         if (!pf->support_multi_driver)
1381                 i40e_GLQF_reg_init(hw);
1382
1383         /* Initialize the input set for filters (hash and fd) to default value */
1384         i40e_filter_input_set_init(pf);
1385
1386         /* initialise the L3_MAP register */
1387         if (!pf->support_multi_driver) {
1388                 ret = i40e_aq_debug_write_global_register(hw,
1389                                                    I40E_GLQF_L3_MAP(40),
1390                                                    0x00000028,  NULL);
1391                 if (ret)
1392                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1393                                      ret);
1394                 PMD_INIT_LOG(DEBUG,
1395                              "Global register 0x%08x is changed with 0x28",
1396                              I40E_GLQF_L3_MAP(40));
1397         }
1398
1399         /* Need the special FW version to support floating VEB */
1400         config_floating_veb(dev);
1401         /* Clear PXE mode */
1402         i40e_clear_pxe_mode(hw);
1403         i40e_dev_sync_phy_type(hw);
1404
1405         /*
1406          * On X710, performance number is far from the expectation on recent
1407          * firmware versions. The fix for this issue may not be integrated in
1408          * the following firmware version. So the workaround in software driver
1409          * is needed. It needs to modify the initial values of 3 internal only
1410          * registers. Note that the workaround can be removed when it is fixed
1411          * in firmware in the future.
1412          */
1413         i40e_configure_registers(hw);
1414
1415         /* Get hw capabilities */
1416         ret = i40e_get_cap(hw);
1417         if (ret != I40E_SUCCESS) {
1418                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1419                 goto err_get_capabilities;
1420         }
1421
1422         /* Initialize parameters for PF */
1423         ret = i40e_pf_parameter_init(dev);
1424         if (ret != 0) {
1425                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1426                 goto err_parameter_init;
1427         }
1428
1429         /* Initialize the queue management */
1430         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1431         if (ret < 0) {
1432                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1433                 goto err_qp_pool_init;
1434         }
1435         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1436                                 hw->func_caps.num_msix_vectors - 1);
1437         if (ret < 0) {
1438                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1439                 goto err_msix_pool_init;
1440         }
1441
1442         /* Initialize lan hmc */
1443         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1444                                 hw->func_caps.num_rx_qp, 0, 0);
1445         if (ret != I40E_SUCCESS) {
1446                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1447                 goto err_init_lan_hmc;
1448         }
1449
1450         /* Configure lan hmc */
1451         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1452         if (ret != I40E_SUCCESS) {
1453                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1454                 goto err_configure_lan_hmc;
1455         }
1456
1457         /* Get and check the mac address */
1458         i40e_get_mac_addr(hw, hw->mac.addr);
1459         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1460                 PMD_INIT_LOG(ERR, "mac address is not valid");
1461                 ret = -EIO;
1462                 goto err_get_mac_addr;
1463         }
1464         /* Copy the permanent MAC address */
1465         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1466                         (struct rte_ether_addr *)hw->mac.perm_addr);
1467
1468         /* Disable flow control */
1469         hw->fc.requested_mode = I40E_FC_NONE;
1470         i40e_set_fc(hw, &aq_fail, TRUE);
1471
1472         /* Set the global registers with default ether type value */
1473         if (!pf->support_multi_driver) {
1474                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1475                                          RTE_ETHER_TYPE_VLAN);
1476                 if (ret != I40E_SUCCESS) {
1477                         PMD_INIT_LOG(ERR,
1478                                      "Failed to set the default outer "
1479                                      "VLAN ether type");
1480                         goto err_setup_pf_switch;
1481                 }
1482         }
1483
1484         /* PF setup, which includes VSI setup */
1485         ret = i40e_pf_setup(pf);
1486         if (ret) {
1487                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1488                 goto err_setup_pf_switch;
1489         }
1490
1491         vsi = pf->main_vsi;
1492
1493         /* Disable double vlan by default */
1494         i40e_vsi_config_double_vlan(vsi, FALSE);
1495
1496         /* Disable S-TAG identification when floating_veb is disabled */
1497         if (!pf->floating_veb) {
1498                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1499                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1500                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1501                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1502                 }
1503         }
1504
1505         if (!vsi->max_macaddrs)
1506                 len = RTE_ETHER_ADDR_LEN;
1507         else
1508                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1509
1510         /* Should be after VSI initialized */
1511         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1512         if (!dev->data->mac_addrs) {
1513                 PMD_INIT_LOG(ERR,
1514                         "Failed to allocated memory for storing mac address");
1515                 goto err_mac_alloc;
1516         }
1517         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1518                                         &dev->data->mac_addrs[0]);
1519
1520         /* Init dcb to sw mode by default */
1521         ret = i40e_dcb_init_configure(dev, TRUE);
1522         if (ret != I40E_SUCCESS) {
1523                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1524                 pf->flags &= ~I40E_FLAG_DCB;
1525         }
1526         /* Update HW struct after DCB configuration */
1527         i40e_get_cap(hw);
1528
1529         /* initialize pf host driver to setup SRIOV resource if applicable */
1530         i40e_pf_host_init(dev);
1531
1532         /* register callback func to eal lib */
1533         rte_intr_callback_register(intr_handle,
1534                                    i40e_dev_interrupt_handler, dev);
1535
1536         /* configure and enable device interrupt */
1537         i40e_pf_config_irq0(hw, TRUE);
1538         i40e_pf_enable_irq0(hw);
1539
1540         /* enable uio intr after callback register */
1541         rte_intr_enable(intr_handle);
1542
1543         /* By default disable flexible payload in global configuration */
1544         if (!pf->support_multi_driver)
1545                 i40e_flex_payload_reg_set_default(hw);
1546
1547         /*
1548          * Add an ethertype filter to drop all flow control frames transmitted
1549          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1550          * frames to wire.
1551          */
1552         i40e_add_tx_flow_control_drop_filter(pf);
1553
1554         /* Set the max frame size to 0x2600 by default,
1555          * in case other drivers changed the default value.
1556          */
1557         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1558
1559         /* initialize mirror rule list */
1560         TAILQ_INIT(&pf->mirror_list);
1561
1562         /* initialize Traffic Manager configuration */
1563         i40e_tm_conf_init(dev);
1564
1565         /* Initialize customized information */
1566         i40e_init_customized_info(pf);
1567
1568         ret = i40e_init_ethtype_filter_list(dev);
1569         if (ret < 0)
1570                 goto err_init_ethtype_filter_list;
1571         ret = i40e_init_tunnel_filter_list(dev);
1572         if (ret < 0)
1573                 goto err_init_tunnel_filter_list;
1574         ret = i40e_init_fdir_filter_list(dev);
1575         if (ret < 0)
1576                 goto err_init_fdir_filter_list;
1577
1578         /* initialize queue region configuration */
1579         i40e_init_queue_region_conf(dev);
1580
1581         /* initialize rss configuration from rte_flow */
1582         memset(&pf->rss_info, 0,
1583                 sizeof(struct i40e_rte_flow_rss_conf));
1584
1585         /* reset all stats of the device, including pf and main vsi */
1586         i40e_dev_stats_reset(dev);
1587
1588         return 0;
1589
1590 err_init_fdir_filter_list:
1591         rte_free(pf->tunnel.hash_table);
1592         rte_free(pf->tunnel.hash_map);
1593 err_init_tunnel_filter_list:
1594         rte_free(pf->ethertype.hash_table);
1595         rte_free(pf->ethertype.hash_map);
1596 err_init_ethtype_filter_list:
1597         rte_free(dev->data->mac_addrs);
1598         dev->data->mac_addrs = NULL;
1599 err_mac_alloc:
1600         i40e_vsi_release(pf->main_vsi);
1601 err_setup_pf_switch:
1602 err_get_mac_addr:
1603 err_configure_lan_hmc:
1604         (void)i40e_shutdown_lan_hmc(hw);
1605 err_init_lan_hmc:
1606         i40e_res_pool_destroy(&pf->msix_pool);
1607 err_msix_pool_init:
1608         i40e_res_pool_destroy(&pf->qp_pool);
1609 err_qp_pool_init:
1610 err_parameter_init:
1611 err_get_capabilities:
1612         (void)i40e_shutdown_adminq(hw);
1613
1614         return ret;
1615 }
1616
1617 static void
1618 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1619 {
1620         struct i40e_ethertype_filter *p_ethertype;
1621         struct i40e_ethertype_rule *ethertype_rule;
1622
1623         ethertype_rule = &pf->ethertype;
1624         /* Remove all ethertype filter rules and hash */
1625         if (ethertype_rule->hash_map)
1626                 rte_free(ethertype_rule->hash_map);
1627         if (ethertype_rule->hash_table)
1628                 rte_hash_free(ethertype_rule->hash_table);
1629
1630         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1631                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1632                              p_ethertype, rules);
1633                 rte_free(p_ethertype);
1634         }
1635 }
1636
1637 static void
1638 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1639 {
1640         struct i40e_tunnel_filter *p_tunnel;
1641         struct i40e_tunnel_rule *tunnel_rule;
1642
1643         tunnel_rule = &pf->tunnel;
1644         /* Remove all tunnel director rules and hash */
1645         if (tunnel_rule->hash_map)
1646                 rte_free(tunnel_rule->hash_map);
1647         if (tunnel_rule->hash_table)
1648                 rte_hash_free(tunnel_rule->hash_table);
1649
1650         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1651                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1652                 rte_free(p_tunnel);
1653         }
1654 }
1655
1656 static void
1657 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1658 {
1659         struct i40e_fdir_filter *p_fdir;
1660         struct i40e_fdir_info *fdir_info;
1661
1662         fdir_info = &pf->fdir;
1663         /* Remove all flow director rules and hash */
1664         if (fdir_info->hash_map)
1665                 rte_free(fdir_info->hash_map);
1666         if (fdir_info->hash_table)
1667                 rte_hash_free(fdir_info->hash_table);
1668
1669         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1670                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1671                 rte_free(p_fdir);
1672         }
1673 }
1674
1675 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1676 {
1677         /*
1678          * Disable by default flexible payload
1679          * for corresponding L2/L3/L4 layers.
1680          */
1681         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1682         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1683         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1684 }
1685
1686 static int
1687 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1688 {
1689         struct i40e_pf *pf;
1690         struct rte_pci_device *pci_dev;
1691         struct rte_intr_handle *intr_handle;
1692         struct i40e_hw *hw;
1693         struct i40e_filter_control_settings settings;
1694         struct rte_flow *p_flow;
1695         int ret;
1696         uint8_t aq_fail = 0;
1697         int retries = 0;
1698
1699         PMD_INIT_FUNC_TRACE();
1700
1701         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1702                 return 0;
1703
1704         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1705         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1706         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1707         intr_handle = &pci_dev->intr_handle;
1708
1709         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1710         if (ret)
1711                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1712
1713         if (hw->adapter_closed == 0)
1714                 i40e_dev_close(dev);
1715
1716         dev->dev_ops = NULL;
1717         dev->rx_pkt_burst = NULL;
1718         dev->tx_pkt_burst = NULL;
1719
1720         /* Clear PXE mode */
1721         i40e_clear_pxe_mode(hw);
1722
1723         /* Unconfigure filter control */
1724         memset(&settings, 0, sizeof(settings));
1725         ret = i40e_set_filter_control(hw, &settings);
1726         if (ret)
1727                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1728                                         ret);
1729
1730         /* Disable flow control */
1731         hw->fc.requested_mode = I40E_FC_NONE;
1732         i40e_set_fc(hw, &aq_fail, TRUE);
1733
1734         /* uninitialize pf host driver */
1735         i40e_pf_host_uninit(dev);
1736
1737         /* disable uio intr before callback unregister */
1738         rte_intr_disable(intr_handle);
1739
1740         /* unregister callback func to eal lib */
1741         do {
1742                 ret = rte_intr_callback_unregister(intr_handle,
1743                                 i40e_dev_interrupt_handler, dev);
1744                 if (ret >= 0) {
1745                         break;
1746                 } else if (ret != -EAGAIN) {
1747                         PMD_INIT_LOG(ERR,
1748                                  "intr callback unregister failed: %d",
1749                                  ret);
1750                         return ret;
1751                 }
1752                 i40e_msec_delay(500);
1753         } while (retries++ < 5);
1754
1755         i40e_rm_ethtype_filter_list(pf);
1756         i40e_rm_tunnel_filter_list(pf);
1757         i40e_rm_fdir_filter_list(pf);
1758
1759         /* Remove all flows */
1760         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1761                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1762                 rte_free(p_flow);
1763         }
1764
1765         /* Remove all Traffic Manager configuration */
1766         i40e_tm_conf_uninit(dev);
1767
1768         return 0;
1769 }
1770
1771 static int
1772 i40e_dev_configure(struct rte_eth_dev *dev)
1773 {
1774         struct i40e_adapter *ad =
1775                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1776         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1777         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1778         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1779         int i, ret;
1780
1781         ret = i40e_dev_sync_phy_type(hw);
1782         if (ret)
1783                 return ret;
1784
1785         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1786          * bulk allocation or vector Rx preconditions we will reset it.
1787          */
1788         ad->rx_bulk_alloc_allowed = true;
1789         ad->rx_vec_allowed = true;
1790         ad->tx_simple_allowed = true;
1791         ad->tx_vec_allowed = true;
1792
1793         /* Only legacy filter API needs the following fdir config. So when the
1794          * legacy filter API is deprecated, the following codes should also be
1795          * removed.
1796          */
1797         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1798                 ret = i40e_fdir_setup(pf);
1799                 if (ret != I40E_SUCCESS) {
1800                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1801                         return -ENOTSUP;
1802                 }
1803                 ret = i40e_fdir_configure(dev);
1804                 if (ret < 0) {
1805                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1806                         goto err;
1807                 }
1808         } else
1809                 i40e_fdir_teardown(pf);
1810
1811         ret = i40e_dev_init_vlan(dev);
1812         if (ret < 0)
1813                 goto err;
1814
1815         /* VMDQ setup.
1816          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1817          *  RSS setting have different requirements.
1818          *  General PMD driver call sequence are NIC init, configure,
1819          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1820          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1821          *  applicable. So, VMDQ setting has to be done before
1822          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1823          *  For RSS setting, it will try to calculate actual configured RX queue
1824          *  number, which will be available after rx_queue_setup(). dev_start()
1825          *  function is good to place RSS setup.
1826          */
1827         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1828                 ret = i40e_vmdq_setup(dev);
1829                 if (ret)
1830                         goto err;
1831         }
1832
1833         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1834                 ret = i40e_dcb_setup(dev);
1835                 if (ret) {
1836                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1837                         goto err_dcb;
1838                 }
1839         }
1840
1841         TAILQ_INIT(&pf->flow_list);
1842
1843         return 0;
1844
1845 err_dcb:
1846         /* need to release vmdq resource if exists */
1847         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1848                 i40e_vsi_release(pf->vmdq[i].vsi);
1849                 pf->vmdq[i].vsi = NULL;
1850         }
1851         rte_free(pf->vmdq);
1852         pf->vmdq = NULL;
1853 err:
1854         /* Need to release fdir resource if exists.
1855          * Only legacy filter API needs the following fdir config. So when the
1856          * legacy filter API is deprecated, the following code should also be
1857          * removed.
1858          */
1859         i40e_fdir_teardown(pf);
1860         return ret;
1861 }
1862
1863 void
1864 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1865 {
1866         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1867         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1868         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1869         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1870         uint16_t msix_vect = vsi->msix_intr;
1871         uint16_t i;
1872
1873         for (i = 0; i < vsi->nb_qps; i++) {
1874                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1875                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1876                 rte_wmb();
1877         }
1878
1879         if (vsi->type != I40E_VSI_SRIOV) {
1880                 if (!rte_intr_allow_others(intr_handle)) {
1881                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1882                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1883                         I40E_WRITE_REG(hw,
1884                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1885                                        0);
1886                 } else {
1887                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1888                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1889                         I40E_WRITE_REG(hw,
1890                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1891                                                        msix_vect - 1), 0);
1892                 }
1893         } else {
1894                 uint32_t reg;
1895                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1896                         vsi->user_param + (msix_vect - 1);
1897
1898                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1899                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1900         }
1901         I40E_WRITE_FLUSH(hw);
1902 }
1903
1904 static void
1905 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1906                        int base_queue, int nb_queue,
1907                        uint16_t itr_idx)
1908 {
1909         int i;
1910         uint32_t val;
1911         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1912         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1913
1914         /* Bind all RX queues to allocated MSIX interrupt */
1915         for (i = 0; i < nb_queue; i++) {
1916                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1917                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1918                         ((base_queue + i + 1) <<
1919                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1920                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1921                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1922
1923                 if (i == nb_queue - 1)
1924                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1925                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1926         }
1927
1928         /* Write first RX queue to Link list register as the head element */
1929         if (vsi->type != I40E_VSI_SRIOV) {
1930                 uint16_t interval =
1931                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1932
1933                 if (msix_vect == I40E_MISC_VEC_ID) {
1934                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1935                                        (base_queue <<
1936                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1937                                        (0x0 <<
1938                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1939                         I40E_WRITE_REG(hw,
1940                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1941                                        interval);
1942                 } else {
1943                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1944                                        (base_queue <<
1945                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1946                                        (0x0 <<
1947                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1948                         I40E_WRITE_REG(hw,
1949                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1950                                                        msix_vect - 1),
1951                                        interval);
1952                 }
1953         } else {
1954                 uint32_t reg;
1955
1956                 if (msix_vect == I40E_MISC_VEC_ID) {
1957                         I40E_WRITE_REG(hw,
1958                                        I40E_VPINT_LNKLST0(vsi->user_param),
1959                                        (base_queue <<
1960                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1961                                        (0x0 <<
1962                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1963                 } else {
1964                         /* num_msix_vectors_vf needs to minus irq0 */
1965                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1966                                 vsi->user_param + (msix_vect - 1);
1967
1968                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1969                                        (base_queue <<
1970                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1971                                        (0x0 <<
1972                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1973                 }
1974         }
1975
1976         I40E_WRITE_FLUSH(hw);
1977 }
1978
1979 void
1980 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1981 {
1982         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1983         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1984         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1985         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1986         uint16_t msix_vect = vsi->msix_intr;
1987         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1988         uint16_t queue_idx = 0;
1989         int record = 0;
1990         int i;
1991
1992         for (i = 0; i < vsi->nb_qps; i++) {
1993                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1994                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1995         }
1996
1997         /* VF bind interrupt */
1998         if (vsi->type == I40E_VSI_SRIOV) {
1999                 __vsi_queues_bind_intr(vsi, msix_vect,
2000                                        vsi->base_queue, vsi->nb_qps,
2001                                        itr_idx);
2002                 return;
2003         }
2004
2005         /* PF & VMDq bind interrupt */
2006         if (rte_intr_dp_is_en(intr_handle)) {
2007                 if (vsi->type == I40E_VSI_MAIN) {
2008                         queue_idx = 0;
2009                         record = 1;
2010                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2011                         struct i40e_vsi *main_vsi =
2012                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2013                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2014                         record = 1;
2015                 }
2016         }
2017
2018         for (i = 0; i < vsi->nb_used_qps; i++) {
2019                 if (nb_msix <= 1) {
2020                         if (!rte_intr_allow_others(intr_handle))
2021                                 /* allow to share MISC_VEC_ID */
2022                                 msix_vect = I40E_MISC_VEC_ID;
2023
2024                         /* no enough msix_vect, map all to one */
2025                         __vsi_queues_bind_intr(vsi, msix_vect,
2026                                                vsi->base_queue + i,
2027                                                vsi->nb_used_qps - i,
2028                                                itr_idx);
2029                         for (; !!record && i < vsi->nb_used_qps; i++)
2030                                 intr_handle->intr_vec[queue_idx + i] =
2031                                         msix_vect;
2032                         break;
2033                 }
2034                 /* 1:1 queue/msix_vect mapping */
2035                 __vsi_queues_bind_intr(vsi, msix_vect,
2036                                        vsi->base_queue + i, 1,
2037                                        itr_idx);
2038                 if (!!record)
2039                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2040
2041                 msix_vect++;
2042                 nb_msix--;
2043         }
2044 }
2045
2046 static void
2047 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2048 {
2049         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2050         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2051         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2052         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2053         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2054         uint16_t msix_intr, i;
2055
2056         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2057                 for (i = 0; i < vsi->nb_msix; i++) {
2058                         msix_intr = vsi->msix_intr + i;
2059                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2060                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2061                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2062                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2063                 }
2064         else
2065                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2066                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2067                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2068                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2069
2070         I40E_WRITE_FLUSH(hw);
2071 }
2072
2073 static void
2074 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2075 {
2076         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2077         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2078         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2079         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2080         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2081         uint16_t msix_intr, i;
2082
2083         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2084                 for (i = 0; i < vsi->nb_msix; i++) {
2085                         msix_intr = vsi->msix_intr + i;
2086                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2087                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2088                 }
2089         else
2090                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2091                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2092
2093         I40E_WRITE_FLUSH(hw);
2094 }
2095
2096 static inline uint8_t
2097 i40e_parse_link_speeds(uint16_t link_speeds)
2098 {
2099         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2100
2101         if (link_speeds & ETH_LINK_SPEED_40G)
2102                 link_speed |= I40E_LINK_SPEED_40GB;
2103         if (link_speeds & ETH_LINK_SPEED_25G)
2104                 link_speed |= I40E_LINK_SPEED_25GB;
2105         if (link_speeds & ETH_LINK_SPEED_20G)
2106                 link_speed |= I40E_LINK_SPEED_20GB;
2107         if (link_speeds & ETH_LINK_SPEED_10G)
2108                 link_speed |= I40E_LINK_SPEED_10GB;
2109         if (link_speeds & ETH_LINK_SPEED_1G)
2110                 link_speed |= I40E_LINK_SPEED_1GB;
2111         if (link_speeds & ETH_LINK_SPEED_100M)
2112                 link_speed |= I40E_LINK_SPEED_100MB;
2113
2114         return link_speed;
2115 }
2116
2117 static int
2118 i40e_phy_conf_link(struct i40e_hw *hw,
2119                    uint8_t abilities,
2120                    uint8_t force_speed,
2121                    bool is_up)
2122 {
2123         enum i40e_status_code status;
2124         struct i40e_aq_get_phy_abilities_resp phy_ab;
2125         struct i40e_aq_set_phy_config phy_conf;
2126         enum i40e_aq_phy_type cnt;
2127         uint8_t avail_speed;
2128         uint32_t phy_type_mask = 0;
2129
2130         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2131                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2132                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2133                         I40E_AQ_PHY_FLAG_LOW_POWER;
2134         int ret = -ENOTSUP;
2135
2136         /* To get phy capabilities of available speeds. */
2137         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2138                                               NULL);
2139         if (status) {
2140                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2141                                 status);
2142                 return ret;
2143         }
2144         avail_speed = phy_ab.link_speed;
2145
2146         /* To get the current phy config. */
2147         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2148                                               NULL);
2149         if (status) {
2150                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2151                                 status);
2152                 return ret;
2153         }
2154
2155         /* If link needs to go up and it is in autoneg mode the speed is OK,
2156          * no need to set up again.
2157          */
2158         if (is_up && phy_ab.phy_type != 0 &&
2159                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2160                      phy_ab.link_speed != 0)
2161                 return I40E_SUCCESS;
2162
2163         memset(&phy_conf, 0, sizeof(phy_conf));
2164
2165         /* bits 0-2 use the values from get_phy_abilities_resp */
2166         abilities &= ~mask;
2167         abilities |= phy_ab.abilities & mask;
2168
2169         phy_conf.abilities = abilities;
2170
2171         /* If link needs to go up, but the force speed is not supported,
2172          * Warn users and config the default available speeds.
2173          */
2174         if (is_up && !(force_speed & avail_speed)) {
2175                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2176                 phy_conf.link_speed = avail_speed;
2177         } else {
2178                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2179         }
2180
2181         /* PHY type mask needs to include each type except PHY type extension */
2182         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2183                 phy_type_mask |= 1 << cnt;
2184
2185         /* use get_phy_abilities_resp value for the rest */
2186         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2187         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2188                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2189                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2190         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2191         phy_conf.eee_capability = phy_ab.eee_capability;
2192         phy_conf.eeer = phy_ab.eeer_val;
2193         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2194
2195         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2196                     phy_ab.abilities, phy_ab.link_speed);
2197         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2198                     phy_conf.abilities, phy_conf.link_speed);
2199
2200         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2201         if (status)
2202                 return ret;
2203
2204         return I40E_SUCCESS;
2205 }
2206
2207 static int
2208 i40e_apply_link_speed(struct rte_eth_dev *dev)
2209 {
2210         uint8_t speed;
2211         uint8_t abilities = 0;
2212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2213         struct rte_eth_conf *conf = &dev->data->dev_conf;
2214
2215         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2216                 conf->link_speeds = ETH_LINK_SPEED_40G |
2217                                     ETH_LINK_SPEED_25G |
2218                                     ETH_LINK_SPEED_20G |
2219                                     ETH_LINK_SPEED_10G |
2220                                     ETH_LINK_SPEED_1G |
2221                                     ETH_LINK_SPEED_100M;
2222         }
2223         speed = i40e_parse_link_speeds(conf->link_speeds);
2224         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2225                      I40E_AQ_PHY_AN_ENABLED |
2226                      I40E_AQ_PHY_LINK_ENABLED;
2227
2228         return i40e_phy_conf_link(hw, abilities, speed, true);
2229 }
2230
2231 static int
2232 i40e_dev_start(struct rte_eth_dev *dev)
2233 {
2234         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2235         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2236         struct i40e_vsi *main_vsi = pf->main_vsi;
2237         int ret, i;
2238         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2239         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2240         uint32_t intr_vector = 0;
2241         struct i40e_vsi *vsi;
2242
2243         hw->adapter_stopped = 0;
2244
2245         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2246                 PMD_INIT_LOG(ERR,
2247                 "Invalid link_speeds for port %u, autonegotiation disabled",
2248                               dev->data->port_id);
2249                 return -EINVAL;
2250         }
2251
2252         rte_intr_disable(intr_handle);
2253
2254         if ((rte_intr_cap_multiple(intr_handle) ||
2255              !RTE_ETH_DEV_SRIOV(dev).active) &&
2256             dev->data->dev_conf.intr_conf.rxq != 0) {
2257                 intr_vector = dev->data->nb_rx_queues;
2258                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2259                 if (ret)
2260                         return ret;
2261         }
2262
2263         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2264                 intr_handle->intr_vec =
2265                         rte_zmalloc("intr_vec",
2266                                     dev->data->nb_rx_queues * sizeof(int),
2267                                     0);
2268                 if (!intr_handle->intr_vec) {
2269                         PMD_INIT_LOG(ERR,
2270                                 "Failed to allocate %d rx_queues intr_vec",
2271                                 dev->data->nb_rx_queues);
2272                         return -ENOMEM;
2273                 }
2274         }
2275
2276         /* Initialize VSI */
2277         ret = i40e_dev_rxtx_init(pf);
2278         if (ret != I40E_SUCCESS) {
2279                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2280                 goto err_up;
2281         }
2282
2283         /* Map queues with MSIX interrupt */
2284         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2285                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2286         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2287         i40e_vsi_enable_queues_intr(main_vsi);
2288
2289         /* Map VMDQ VSI queues with MSIX interrupt */
2290         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2291                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2292                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2293                                           I40E_ITR_INDEX_DEFAULT);
2294                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2295         }
2296
2297         /* enable FDIR MSIX interrupt */
2298         if (pf->fdir.fdir_vsi) {
2299                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2300                                           I40E_ITR_INDEX_NONE);
2301                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2302         }
2303
2304         /* Enable all queues which have been configured */
2305         ret = i40e_dev_switch_queues(pf, TRUE);
2306         if (ret != I40E_SUCCESS) {
2307                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2308                 goto err_up;
2309         }
2310
2311         /* Enable receiving broadcast packets */
2312         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2313         if (ret != I40E_SUCCESS)
2314                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2315
2316         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2317                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2318                                                 true, NULL);
2319                 if (ret != I40E_SUCCESS)
2320                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2321         }
2322
2323         /* Enable the VLAN promiscuous mode. */
2324         if (pf->vfs) {
2325                 for (i = 0; i < pf->vf_num; i++) {
2326                         vsi = pf->vfs[i].vsi;
2327                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2328                                                      true, NULL);
2329                 }
2330         }
2331
2332         /* Enable mac loopback mode */
2333         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2334             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2335                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2336                 if (ret != I40E_SUCCESS) {
2337                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2338                         goto err_up;
2339                 }
2340         }
2341
2342         /* Apply link configure */
2343         ret = i40e_apply_link_speed(dev);
2344         if (I40E_SUCCESS != ret) {
2345                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2346                 goto err_up;
2347         }
2348
2349         if (!rte_intr_allow_others(intr_handle)) {
2350                 rte_intr_callback_unregister(intr_handle,
2351                                              i40e_dev_interrupt_handler,
2352                                              (void *)dev);
2353                 /* configure and enable device interrupt */
2354                 i40e_pf_config_irq0(hw, FALSE);
2355                 i40e_pf_enable_irq0(hw);
2356
2357                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2358                         PMD_INIT_LOG(INFO,
2359                                 "lsc won't enable because of no intr multiplex");
2360         } else {
2361                 ret = i40e_aq_set_phy_int_mask(hw,
2362                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2363                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2364                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2365                 if (ret != I40E_SUCCESS)
2366                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2367
2368                 /* Call get_link_info aq commond to enable/disable LSE */
2369                 i40e_dev_link_update(dev, 0);
2370         }
2371
2372         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2373                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2374                                   i40e_dev_alarm_handler, dev);
2375         } else {
2376                 /* enable uio intr after callback register */
2377                 rte_intr_enable(intr_handle);
2378         }
2379
2380         i40e_filter_restore(pf);
2381
2382         if (pf->tm_conf.root && !pf->tm_conf.committed)
2383                 PMD_DRV_LOG(WARNING,
2384                             "please call hierarchy_commit() "
2385                             "before starting the port");
2386
2387         return I40E_SUCCESS;
2388
2389 err_up:
2390         i40e_dev_switch_queues(pf, FALSE);
2391         i40e_dev_clear_queues(dev);
2392
2393         return ret;
2394 }
2395
2396 static void
2397 i40e_dev_stop(struct rte_eth_dev *dev)
2398 {
2399         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2400         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2401         struct i40e_vsi *main_vsi = pf->main_vsi;
2402         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2403         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2404         int i;
2405
2406         if (hw->adapter_stopped == 1)
2407                 return;
2408
2409         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2410                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2411                 rte_intr_enable(intr_handle);
2412         }
2413
2414         /* Disable all queues */
2415         i40e_dev_switch_queues(pf, FALSE);
2416
2417         /* un-map queues with interrupt registers */
2418         i40e_vsi_disable_queues_intr(main_vsi);
2419         i40e_vsi_queues_unbind_intr(main_vsi);
2420
2421         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2422                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2423                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2424         }
2425
2426         if (pf->fdir.fdir_vsi) {
2427                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2428                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2429         }
2430         /* Clear all queues and release memory */
2431         i40e_dev_clear_queues(dev);
2432
2433         /* Set link down */
2434         i40e_dev_set_link_down(dev);
2435
2436         if (!rte_intr_allow_others(intr_handle))
2437                 /* resume to the default handler */
2438                 rte_intr_callback_register(intr_handle,
2439                                            i40e_dev_interrupt_handler,
2440                                            (void *)dev);
2441
2442         /* Clean datapath event and queue/vec mapping */
2443         rte_intr_efd_disable(intr_handle);
2444         if (intr_handle->intr_vec) {
2445                 rte_free(intr_handle->intr_vec);
2446                 intr_handle->intr_vec = NULL;
2447         }
2448
2449         /* reset hierarchy commit */
2450         pf->tm_conf.committed = false;
2451
2452         hw->adapter_stopped = 1;
2453
2454         pf->adapter->rss_reta_updated = 0;
2455 }
2456
2457 static void
2458 i40e_dev_close(struct rte_eth_dev *dev)
2459 {
2460         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2462         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2463         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2464         struct i40e_mirror_rule *p_mirror;
2465         uint32_t reg;
2466         int i;
2467         int ret;
2468
2469         PMD_INIT_FUNC_TRACE();
2470
2471         i40e_dev_stop(dev);
2472
2473         /* Remove all mirror rules */
2474         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2475                 ret = i40e_aq_del_mirror_rule(hw,
2476                                               pf->main_vsi->veb->seid,
2477                                               p_mirror->rule_type,
2478                                               p_mirror->entries,
2479                                               p_mirror->num_entries,
2480                                               p_mirror->id);
2481                 if (ret < 0)
2482                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2483                                     "status = %d, aq_err = %d.", ret,
2484                                     hw->aq.asq_last_status);
2485
2486                 /* remove mirror software resource anyway */
2487                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2488                 rte_free(p_mirror);
2489                 pf->nb_mirror_rule--;
2490         }
2491
2492         i40e_dev_free_queues(dev);
2493
2494         /* Disable interrupt */
2495         i40e_pf_disable_irq0(hw);
2496         rte_intr_disable(intr_handle);
2497
2498         /*
2499          * Only legacy filter API needs the following fdir config. So when the
2500          * legacy filter API is deprecated, the following code should also be
2501          * removed.
2502          */
2503         i40e_fdir_teardown(pf);
2504
2505         /* shutdown and destroy the HMC */
2506         i40e_shutdown_lan_hmc(hw);
2507
2508         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2509                 i40e_vsi_release(pf->vmdq[i].vsi);
2510                 pf->vmdq[i].vsi = NULL;
2511         }
2512         rte_free(pf->vmdq);
2513         pf->vmdq = NULL;
2514
2515         /* release all the existing VSIs and VEBs */
2516         i40e_vsi_release(pf->main_vsi);
2517
2518         /* shutdown the adminq */
2519         i40e_aq_queue_shutdown(hw, true);
2520         i40e_shutdown_adminq(hw);
2521
2522         i40e_res_pool_destroy(&pf->qp_pool);
2523         i40e_res_pool_destroy(&pf->msix_pool);
2524
2525         /* Disable flexible payload in global configuration */
2526         if (!pf->support_multi_driver)
2527                 i40e_flex_payload_reg_set_default(hw);
2528
2529         /* force a PF reset to clean anything leftover */
2530         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2531         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2532                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2533         I40E_WRITE_FLUSH(hw);
2534
2535         hw->adapter_closed = 1;
2536 }
2537
2538 /*
2539  * Reset PF device only to re-initialize resources in PMD layer
2540  */
2541 static int
2542 i40e_dev_reset(struct rte_eth_dev *dev)
2543 {
2544         int ret;
2545
2546         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2547          * its VF to make them align with it. The detailed notification
2548          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2549          * To avoid unexpected behavior in VF, currently reset of PF with
2550          * SR-IOV activation is not supported. It might be supported later.
2551          */
2552         if (dev->data->sriov.active)
2553                 return -ENOTSUP;
2554
2555         ret = eth_i40e_dev_uninit(dev);
2556         if (ret)
2557                 return ret;
2558
2559         ret = eth_i40e_dev_init(dev, NULL);
2560
2561         return ret;
2562 }
2563
2564 static void
2565 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2566 {
2567         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2568         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2569         struct i40e_vsi *vsi = pf->main_vsi;
2570         int status;
2571
2572         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2573                                                      true, NULL, true);
2574         if (status != I40E_SUCCESS)
2575                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2576
2577         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2578                                                         TRUE, NULL);
2579         if (status != I40E_SUCCESS)
2580                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2581
2582 }
2583
2584 static void
2585 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2586 {
2587         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2588         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2589         struct i40e_vsi *vsi = pf->main_vsi;
2590         int status;
2591
2592         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2593                                                      false, NULL, true);
2594         if (status != I40E_SUCCESS)
2595                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2596
2597         /* must remain in all_multicast mode */
2598         if (dev->data->all_multicast == 1)
2599                 return;
2600
2601         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2602                                                         false, NULL);
2603         if (status != I40E_SUCCESS)
2604                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2605 }
2606
2607 static void
2608 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2609 {
2610         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         struct i40e_vsi *vsi = pf->main_vsi;
2613         int ret;
2614
2615         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2616         if (ret != I40E_SUCCESS)
2617                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2618 }
2619
2620 static void
2621 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2622 {
2623         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2624         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2625         struct i40e_vsi *vsi = pf->main_vsi;
2626         int ret;
2627
2628         if (dev->data->promiscuous == 1)
2629                 return; /* must remain in all_multicast mode */
2630
2631         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2632                                 vsi->seid, FALSE, NULL);
2633         if (ret != I40E_SUCCESS)
2634                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2635 }
2636
2637 /*
2638  * Set device link up.
2639  */
2640 static int
2641 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2642 {
2643         /* re-apply link speed setting */
2644         return i40e_apply_link_speed(dev);
2645 }
2646
2647 /*
2648  * Set device link down.
2649  */
2650 static int
2651 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2652 {
2653         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2654         uint8_t abilities = 0;
2655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2656
2657         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2658         return i40e_phy_conf_link(hw, abilities, speed, false);
2659 }
2660
2661 static __rte_always_inline void
2662 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2663 {
2664 /* Link status registers and values*/
2665 #define I40E_PRTMAC_LINKSTA             0x001E2420
2666 #define I40E_REG_LINK_UP                0x40000080
2667 #define I40E_PRTMAC_MACC                0x001E24E0
2668 #define I40E_REG_MACC_25GB              0x00020000
2669 #define I40E_REG_SPEED_MASK             0x38000000
2670 #define I40E_REG_SPEED_0                0x00000000
2671 #define I40E_REG_SPEED_1                0x08000000
2672 #define I40E_REG_SPEED_2                0x10000000
2673 #define I40E_REG_SPEED_3                0x18000000
2674 #define I40E_REG_SPEED_4                0x20000000
2675         uint32_t link_speed;
2676         uint32_t reg_val;
2677
2678         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2679         link_speed = reg_val & I40E_REG_SPEED_MASK;
2680         reg_val &= I40E_REG_LINK_UP;
2681         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2682
2683         if (unlikely(link->link_status == 0))
2684                 return;
2685
2686         /* Parse the link status */
2687         switch (link_speed) {
2688         case I40E_REG_SPEED_0:
2689                 link->link_speed = ETH_SPEED_NUM_100M;
2690                 break;
2691         case I40E_REG_SPEED_1:
2692                 link->link_speed = ETH_SPEED_NUM_1G;
2693                 break;
2694         case I40E_REG_SPEED_2:
2695                 if (hw->mac.type == I40E_MAC_X722)
2696                         link->link_speed = ETH_SPEED_NUM_2_5G;
2697                 else
2698                         link->link_speed = ETH_SPEED_NUM_10G;
2699                 break;
2700         case I40E_REG_SPEED_3:
2701                 if (hw->mac.type == I40E_MAC_X722) {
2702                         link->link_speed = ETH_SPEED_NUM_5G;
2703                 } else {
2704                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2705
2706                         if (reg_val & I40E_REG_MACC_25GB)
2707                                 link->link_speed = ETH_SPEED_NUM_25G;
2708                         else
2709                                 link->link_speed = ETH_SPEED_NUM_40G;
2710                 }
2711                 break;
2712         case I40E_REG_SPEED_4:
2713                 if (hw->mac.type == I40E_MAC_X722)
2714                         link->link_speed = ETH_SPEED_NUM_10G;
2715                 else
2716                         link->link_speed = ETH_SPEED_NUM_20G;
2717                 break;
2718         default:
2719                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2720                 break;
2721         }
2722 }
2723
2724 static __rte_always_inline void
2725 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2726         bool enable_lse, int wait_to_complete)
2727 {
2728 #define CHECK_INTERVAL             100  /* 100ms */
2729 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2730         uint32_t rep_cnt = MAX_REPEAT_TIME;
2731         struct i40e_link_status link_status;
2732         int status;
2733
2734         memset(&link_status, 0, sizeof(link_status));
2735
2736         do {
2737                 memset(&link_status, 0, sizeof(link_status));
2738
2739                 /* Get link status information from hardware */
2740                 status = i40e_aq_get_link_info(hw, enable_lse,
2741                                                 &link_status, NULL);
2742                 if (unlikely(status != I40E_SUCCESS)) {
2743                         link->link_speed = ETH_SPEED_NUM_100M;
2744                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2745                         PMD_DRV_LOG(ERR, "Failed to get link info");
2746                         return;
2747                 }
2748
2749                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2750                 if (!wait_to_complete || link->link_status)
2751                         break;
2752
2753                 rte_delay_ms(CHECK_INTERVAL);
2754         } while (--rep_cnt);
2755
2756         /* Parse the link status */
2757         switch (link_status.link_speed) {
2758         case I40E_LINK_SPEED_100MB:
2759                 link->link_speed = ETH_SPEED_NUM_100M;
2760                 break;
2761         case I40E_LINK_SPEED_1GB:
2762                 link->link_speed = ETH_SPEED_NUM_1G;
2763                 break;
2764         case I40E_LINK_SPEED_10GB:
2765                 link->link_speed = ETH_SPEED_NUM_10G;
2766                 break;
2767         case I40E_LINK_SPEED_20GB:
2768                 link->link_speed = ETH_SPEED_NUM_20G;
2769                 break;
2770         case I40E_LINK_SPEED_25GB:
2771                 link->link_speed = ETH_SPEED_NUM_25G;
2772                 break;
2773         case I40E_LINK_SPEED_40GB:
2774                 link->link_speed = ETH_SPEED_NUM_40G;
2775                 break;
2776         default:
2777                 link->link_speed = ETH_SPEED_NUM_100M;
2778                 break;
2779         }
2780 }
2781
2782 int
2783 i40e_dev_link_update(struct rte_eth_dev *dev,
2784                      int wait_to_complete)
2785 {
2786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2787         struct rte_eth_link link;
2788         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2789         int ret;
2790
2791         memset(&link, 0, sizeof(link));
2792
2793         /* i40e uses full duplex only */
2794         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2795         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2796                         ETH_LINK_SPEED_FIXED);
2797
2798         if (!wait_to_complete && !enable_lse)
2799                 update_link_reg(hw, &link);
2800         else
2801                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2802
2803         ret = rte_eth_linkstatus_set(dev, &link);
2804         i40e_notify_all_vfs_link_status(dev);
2805
2806         return ret;
2807 }
2808
2809 /* Get all the statistics of a VSI */
2810 void
2811 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2812 {
2813         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2814         struct i40e_eth_stats *nes = &vsi->eth_stats;
2815         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2816         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2817
2818         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2819                             vsi->offset_loaded, &oes->rx_bytes,
2820                             &nes->rx_bytes);
2821         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2822                             vsi->offset_loaded, &oes->rx_unicast,
2823                             &nes->rx_unicast);
2824         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2825                             vsi->offset_loaded, &oes->rx_multicast,
2826                             &nes->rx_multicast);
2827         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2828                             vsi->offset_loaded, &oes->rx_broadcast,
2829                             &nes->rx_broadcast);
2830         /* exclude CRC bytes */
2831         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2832                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2833
2834         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2835                             &oes->rx_discards, &nes->rx_discards);
2836         /* GLV_REPC not supported */
2837         /* GLV_RMPC not supported */
2838         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2839                             &oes->rx_unknown_protocol,
2840                             &nes->rx_unknown_protocol);
2841         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2842                             vsi->offset_loaded, &oes->tx_bytes,
2843                             &nes->tx_bytes);
2844         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2845                             vsi->offset_loaded, &oes->tx_unicast,
2846                             &nes->tx_unicast);
2847         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2848                             vsi->offset_loaded, &oes->tx_multicast,
2849                             &nes->tx_multicast);
2850         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2851                             vsi->offset_loaded,  &oes->tx_broadcast,
2852                             &nes->tx_broadcast);
2853         /* GLV_TDPC not supported */
2854         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2855                             &oes->tx_errors, &nes->tx_errors);
2856         vsi->offset_loaded = true;
2857
2858         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2859                     vsi->vsi_id);
2860         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2861         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2862         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2863         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2864         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2865         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2866                     nes->rx_unknown_protocol);
2867         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2868         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2869         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2870         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2871         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2872         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2873         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2874                     vsi->vsi_id);
2875 }
2876
2877 static void
2878 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2879 {
2880         unsigned int i;
2881         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2882         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2883
2884         /* Get rx/tx bytes of internal transfer packets */
2885         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2886                         I40E_GLV_GORCL(hw->port),
2887                         pf->offset_loaded,
2888                         &pf->internal_stats_offset.rx_bytes,
2889                         &pf->internal_stats.rx_bytes);
2890
2891         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2892                         I40E_GLV_GOTCL(hw->port),
2893                         pf->offset_loaded,
2894                         &pf->internal_stats_offset.tx_bytes,
2895                         &pf->internal_stats.tx_bytes);
2896         /* Get total internal rx packet count */
2897         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2898                             I40E_GLV_UPRCL(hw->port),
2899                             pf->offset_loaded,
2900                             &pf->internal_stats_offset.rx_unicast,
2901                             &pf->internal_stats.rx_unicast);
2902         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2903                             I40E_GLV_MPRCL(hw->port),
2904                             pf->offset_loaded,
2905                             &pf->internal_stats_offset.rx_multicast,
2906                             &pf->internal_stats.rx_multicast);
2907         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2908                             I40E_GLV_BPRCL(hw->port),
2909                             pf->offset_loaded,
2910                             &pf->internal_stats_offset.rx_broadcast,
2911                             &pf->internal_stats.rx_broadcast);
2912         /* Get total internal tx packet count */
2913         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2914                             I40E_GLV_UPTCL(hw->port),
2915                             pf->offset_loaded,
2916                             &pf->internal_stats_offset.tx_unicast,
2917                             &pf->internal_stats.tx_unicast);
2918         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2919                             I40E_GLV_MPTCL(hw->port),
2920                             pf->offset_loaded,
2921                             &pf->internal_stats_offset.tx_multicast,
2922                             &pf->internal_stats.tx_multicast);
2923         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2924                             I40E_GLV_BPTCL(hw->port),
2925                             pf->offset_loaded,
2926                             &pf->internal_stats_offset.tx_broadcast,
2927                             &pf->internal_stats.tx_broadcast);
2928
2929         /* exclude CRC size */
2930         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2931                 pf->internal_stats.rx_multicast +
2932                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2933
2934         /* Get statistics of struct i40e_eth_stats */
2935         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2936                             I40E_GLPRT_GORCL(hw->port),
2937                             pf->offset_loaded, &os->eth.rx_bytes,
2938                             &ns->eth.rx_bytes);
2939         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2940                             I40E_GLPRT_UPRCL(hw->port),
2941                             pf->offset_loaded, &os->eth.rx_unicast,
2942                             &ns->eth.rx_unicast);
2943         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2944                             I40E_GLPRT_MPRCL(hw->port),
2945                             pf->offset_loaded, &os->eth.rx_multicast,
2946                             &ns->eth.rx_multicast);
2947         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2948                             I40E_GLPRT_BPRCL(hw->port),
2949                             pf->offset_loaded, &os->eth.rx_broadcast,
2950                             &ns->eth.rx_broadcast);
2951         /* Workaround: CRC size should not be included in byte statistics,
2952          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2953          * packet.
2954          */
2955         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2956                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2957
2958         /* exclude internal rx bytes
2959          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2960          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2961          * value.
2962          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2963          */
2964         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2965                 ns->eth.rx_bytes = 0;
2966         else
2967                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2968
2969         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2970                 ns->eth.rx_unicast = 0;
2971         else
2972                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2973
2974         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2975                 ns->eth.rx_multicast = 0;
2976         else
2977                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2978
2979         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2980                 ns->eth.rx_broadcast = 0;
2981         else
2982                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2983
2984         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2985                             pf->offset_loaded, &os->eth.rx_discards,
2986                             &ns->eth.rx_discards);
2987         /* GLPRT_REPC not supported */
2988         /* GLPRT_RMPC not supported */
2989         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2990                             pf->offset_loaded,
2991                             &os->eth.rx_unknown_protocol,
2992                             &ns->eth.rx_unknown_protocol);
2993         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2994                             I40E_GLPRT_GOTCL(hw->port),
2995                             pf->offset_loaded, &os->eth.tx_bytes,
2996                             &ns->eth.tx_bytes);
2997         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2998                             I40E_GLPRT_UPTCL(hw->port),
2999                             pf->offset_loaded, &os->eth.tx_unicast,
3000                             &ns->eth.tx_unicast);
3001         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3002                             I40E_GLPRT_MPTCL(hw->port),
3003                             pf->offset_loaded, &os->eth.tx_multicast,
3004                             &ns->eth.tx_multicast);
3005         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3006                             I40E_GLPRT_BPTCL(hw->port),
3007                             pf->offset_loaded, &os->eth.tx_broadcast,
3008                             &ns->eth.tx_broadcast);
3009         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3010                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3011
3012         /* exclude internal tx bytes
3013          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3014          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3015          * value.
3016          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3017          */
3018         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3019                 ns->eth.tx_bytes = 0;
3020         else
3021                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3022
3023         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3024                 ns->eth.tx_unicast = 0;
3025         else
3026                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3027
3028         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3029                 ns->eth.tx_multicast = 0;
3030         else
3031                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3032
3033         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3034                 ns->eth.tx_broadcast = 0;
3035         else
3036                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3037
3038         /* GLPRT_TEPC not supported */
3039
3040         /* additional port specific stats */
3041         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3042                             pf->offset_loaded, &os->tx_dropped_link_down,
3043                             &ns->tx_dropped_link_down);
3044         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3045                             pf->offset_loaded, &os->crc_errors,
3046                             &ns->crc_errors);
3047         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3048                             pf->offset_loaded, &os->illegal_bytes,
3049                             &ns->illegal_bytes);
3050         /* GLPRT_ERRBC not supported */
3051         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3052                             pf->offset_loaded, &os->mac_local_faults,
3053                             &ns->mac_local_faults);
3054         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3055                             pf->offset_loaded, &os->mac_remote_faults,
3056                             &ns->mac_remote_faults);
3057         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3058                             pf->offset_loaded, &os->rx_length_errors,
3059                             &ns->rx_length_errors);
3060         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3061                             pf->offset_loaded, &os->link_xon_rx,
3062                             &ns->link_xon_rx);
3063         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3064                             pf->offset_loaded, &os->link_xoff_rx,
3065                             &ns->link_xoff_rx);
3066         for (i = 0; i < 8; i++) {
3067                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3068                                     pf->offset_loaded,
3069                                     &os->priority_xon_rx[i],
3070                                     &ns->priority_xon_rx[i]);
3071                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3072                                     pf->offset_loaded,
3073                                     &os->priority_xoff_rx[i],
3074                                     &ns->priority_xoff_rx[i]);
3075         }
3076         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3077                             pf->offset_loaded, &os->link_xon_tx,
3078                             &ns->link_xon_tx);
3079         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3080                             pf->offset_loaded, &os->link_xoff_tx,
3081                             &ns->link_xoff_tx);
3082         for (i = 0; i < 8; i++) {
3083                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3084                                     pf->offset_loaded,
3085                                     &os->priority_xon_tx[i],
3086                                     &ns->priority_xon_tx[i]);
3087                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3088                                     pf->offset_loaded,
3089                                     &os->priority_xoff_tx[i],
3090                                     &ns->priority_xoff_tx[i]);
3091                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3092                                     pf->offset_loaded,
3093                                     &os->priority_xon_2_xoff[i],
3094                                     &ns->priority_xon_2_xoff[i]);
3095         }
3096         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3097                             I40E_GLPRT_PRC64L(hw->port),
3098                             pf->offset_loaded, &os->rx_size_64,
3099                             &ns->rx_size_64);
3100         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3101                             I40E_GLPRT_PRC127L(hw->port),
3102                             pf->offset_loaded, &os->rx_size_127,
3103                             &ns->rx_size_127);
3104         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3105                             I40E_GLPRT_PRC255L(hw->port),
3106                             pf->offset_loaded, &os->rx_size_255,
3107                             &ns->rx_size_255);
3108         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3109                             I40E_GLPRT_PRC511L(hw->port),
3110                             pf->offset_loaded, &os->rx_size_511,
3111                             &ns->rx_size_511);
3112         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3113                             I40E_GLPRT_PRC1023L(hw->port),
3114                             pf->offset_loaded, &os->rx_size_1023,
3115                             &ns->rx_size_1023);
3116         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3117                             I40E_GLPRT_PRC1522L(hw->port),
3118                             pf->offset_loaded, &os->rx_size_1522,
3119                             &ns->rx_size_1522);
3120         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3121                             I40E_GLPRT_PRC9522L(hw->port),
3122                             pf->offset_loaded, &os->rx_size_big,
3123                             &ns->rx_size_big);
3124         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3125                             pf->offset_loaded, &os->rx_undersize,
3126                             &ns->rx_undersize);
3127         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3128                             pf->offset_loaded, &os->rx_fragments,
3129                             &ns->rx_fragments);
3130         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3131                             pf->offset_loaded, &os->rx_oversize,
3132                             &ns->rx_oversize);
3133         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3134                             pf->offset_loaded, &os->rx_jabber,
3135                             &ns->rx_jabber);
3136         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3137                             I40E_GLPRT_PTC64L(hw->port),
3138                             pf->offset_loaded, &os->tx_size_64,
3139                             &ns->tx_size_64);
3140         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3141                             I40E_GLPRT_PTC127L(hw->port),
3142                             pf->offset_loaded, &os->tx_size_127,
3143                             &ns->tx_size_127);
3144         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3145                             I40E_GLPRT_PTC255L(hw->port),
3146                             pf->offset_loaded, &os->tx_size_255,
3147                             &ns->tx_size_255);
3148         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3149                             I40E_GLPRT_PTC511L(hw->port),
3150                             pf->offset_loaded, &os->tx_size_511,
3151                             &ns->tx_size_511);
3152         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3153                             I40E_GLPRT_PTC1023L(hw->port),
3154                             pf->offset_loaded, &os->tx_size_1023,
3155                             &ns->tx_size_1023);
3156         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3157                             I40E_GLPRT_PTC1522L(hw->port),
3158                             pf->offset_loaded, &os->tx_size_1522,
3159                             &ns->tx_size_1522);
3160         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3161                             I40E_GLPRT_PTC9522L(hw->port),
3162                             pf->offset_loaded, &os->tx_size_big,
3163                             &ns->tx_size_big);
3164         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3165                            pf->offset_loaded,
3166                            &os->fd_sb_match, &ns->fd_sb_match);
3167         /* GLPRT_MSPDC not supported */
3168         /* GLPRT_XEC not supported */
3169
3170         pf->offset_loaded = true;
3171
3172         if (pf->main_vsi)
3173                 i40e_update_vsi_stats(pf->main_vsi);
3174 }
3175
3176 /* Get all statistics of a port */
3177 static int
3178 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3179 {
3180         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3182         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3183         struct i40e_vsi *vsi;
3184         unsigned i;
3185
3186         /* call read registers - updates values, now write them to struct */
3187         i40e_read_stats_registers(pf, hw);
3188
3189         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3190                         pf->main_vsi->eth_stats.rx_multicast +
3191                         pf->main_vsi->eth_stats.rx_broadcast -
3192                         pf->main_vsi->eth_stats.rx_discards;
3193         stats->opackets = ns->eth.tx_unicast +
3194                         ns->eth.tx_multicast +
3195                         ns->eth.tx_broadcast;
3196         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3197         stats->obytes   = ns->eth.tx_bytes;
3198         stats->oerrors  = ns->eth.tx_errors +
3199                         pf->main_vsi->eth_stats.tx_errors;
3200
3201         /* Rx Errors */
3202         stats->imissed  = ns->eth.rx_discards +
3203                         pf->main_vsi->eth_stats.rx_discards;
3204         stats->ierrors  = ns->crc_errors +
3205                         ns->rx_length_errors + ns->rx_undersize +
3206                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3207
3208         if (pf->vfs) {
3209                 for (i = 0; i < pf->vf_num; i++) {
3210                         vsi = pf->vfs[i].vsi;
3211                         i40e_update_vsi_stats(vsi);
3212
3213                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3214                                         vsi->eth_stats.rx_multicast +
3215                                         vsi->eth_stats.rx_broadcast -
3216                                         vsi->eth_stats.rx_discards);
3217                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3218                         stats->oerrors  += vsi->eth_stats.tx_errors;
3219                         stats->imissed  += vsi->eth_stats.rx_discards;
3220                 }
3221         }
3222
3223         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3224         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3225         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3226         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3227         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3228         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3229         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3230                     ns->eth.rx_unknown_protocol);
3231         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3232         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3233         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3234         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3235         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3236         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3237
3238         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3239                     ns->tx_dropped_link_down);
3240         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3241         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3242                     ns->illegal_bytes);
3243         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3244         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3245                     ns->mac_local_faults);
3246         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3247                     ns->mac_remote_faults);
3248         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3249                     ns->rx_length_errors);
3250         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3251         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3252         for (i = 0; i < 8; i++) {
3253                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3254                                 i, ns->priority_xon_rx[i]);
3255                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3256                                 i, ns->priority_xoff_rx[i]);
3257         }
3258         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3259         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3260         for (i = 0; i < 8; i++) {
3261                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3262                                 i, ns->priority_xon_tx[i]);
3263                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3264                                 i, ns->priority_xoff_tx[i]);
3265                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3266                                 i, ns->priority_xon_2_xoff[i]);
3267         }
3268         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3269         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3270         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3271         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3272         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3273         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3274         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3275         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3276         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3277         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3278         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3279         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3280         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3281         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3282         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3283         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3284         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3285         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3286         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3287                         ns->mac_short_packet_dropped);
3288         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3289                     ns->checksum_error);
3290         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3291         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3292         return 0;
3293 }
3294
3295 /* Reset the statistics */
3296 static void
3297 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3298 {
3299         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3300         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3301
3302         /* Mark PF and VSI stats to update the offset, aka "reset" */
3303         pf->offset_loaded = false;
3304         if (pf->main_vsi)
3305                 pf->main_vsi->offset_loaded = false;
3306
3307         /* read the stats, reading current register values into offset */
3308         i40e_read_stats_registers(pf, hw);
3309 }
3310
3311 static uint32_t
3312 i40e_xstats_calc_num(void)
3313 {
3314         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3315                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3316                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3317 }
3318
3319 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3320                                      struct rte_eth_xstat_name *xstats_names,
3321                                      __rte_unused unsigned limit)
3322 {
3323         unsigned count = 0;
3324         unsigned i, prio;
3325
3326         if (xstats_names == NULL)
3327                 return i40e_xstats_calc_num();
3328
3329         /* Note: limit checked in rte_eth_xstats_names() */
3330
3331         /* Get stats from i40e_eth_stats struct */
3332         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3333                 strlcpy(xstats_names[count].name,
3334                         rte_i40e_stats_strings[i].name,
3335                         sizeof(xstats_names[count].name));
3336                 count++;
3337         }
3338
3339         /* Get individiual stats from i40e_hw_port struct */
3340         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3341                 strlcpy(xstats_names[count].name,
3342                         rte_i40e_hw_port_strings[i].name,
3343                         sizeof(xstats_names[count].name));
3344                 count++;
3345         }
3346
3347         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3348                 for (prio = 0; prio < 8; prio++) {
3349                         snprintf(xstats_names[count].name,
3350                                  sizeof(xstats_names[count].name),
3351                                  "rx_priority%u_%s", prio,
3352                                  rte_i40e_rxq_prio_strings[i].name);
3353                         count++;
3354                 }
3355         }
3356
3357         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3358                 for (prio = 0; prio < 8; prio++) {
3359                         snprintf(xstats_names[count].name,
3360                                  sizeof(xstats_names[count].name),
3361                                  "tx_priority%u_%s", prio,
3362                                  rte_i40e_txq_prio_strings[i].name);
3363                         count++;
3364                 }
3365         }
3366         return count;
3367 }
3368
3369 static int
3370 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3371                     unsigned n)
3372 {
3373         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3374         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3375         unsigned i, count, prio;
3376         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3377
3378         count = i40e_xstats_calc_num();
3379         if (n < count)
3380                 return count;
3381
3382         i40e_read_stats_registers(pf, hw);
3383
3384         if (xstats == NULL)
3385                 return 0;
3386
3387         count = 0;
3388
3389         /* Get stats from i40e_eth_stats struct */
3390         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3391                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3392                         rte_i40e_stats_strings[i].offset);
3393                 xstats[count].id = count;
3394                 count++;
3395         }
3396
3397         /* Get individiual stats from i40e_hw_port struct */
3398         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3399                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3400                         rte_i40e_hw_port_strings[i].offset);
3401                 xstats[count].id = count;
3402                 count++;
3403         }
3404
3405         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3406                 for (prio = 0; prio < 8; prio++) {
3407                         xstats[count].value =
3408                                 *(uint64_t *)(((char *)hw_stats) +
3409                                 rte_i40e_rxq_prio_strings[i].offset +
3410                                 (sizeof(uint64_t) * prio));
3411                         xstats[count].id = count;
3412                         count++;
3413                 }
3414         }
3415
3416         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3417                 for (prio = 0; prio < 8; prio++) {
3418                         xstats[count].value =
3419                                 *(uint64_t *)(((char *)hw_stats) +
3420                                 rte_i40e_txq_prio_strings[i].offset +
3421                                 (sizeof(uint64_t) * prio));
3422                         xstats[count].id = count;
3423                         count++;
3424                 }
3425         }
3426
3427         return count;
3428 }
3429
3430 static int
3431 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3432 {
3433         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3434         u32 full_ver;
3435         u8 ver, patch;
3436         u16 build;
3437         int ret;
3438
3439         full_ver = hw->nvm.oem_ver;
3440         ver = (u8)(full_ver >> 24);
3441         build = (u16)((full_ver >> 8) & 0xffff);
3442         patch = (u8)(full_ver & 0xff);
3443
3444         ret = snprintf(fw_version, fw_size,
3445                  "%d.%d%d 0x%08x %d.%d.%d",
3446                  ((hw->nvm.version >> 12) & 0xf),
3447                  ((hw->nvm.version >> 4) & 0xff),
3448                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3449                  ver, build, patch);
3450
3451         ret += 1; /* add the size of '\0' */
3452         if (fw_size < (u32)ret)
3453                 return ret;
3454         else
3455                 return 0;
3456 }
3457
3458 /*
3459  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3460  * the Rx data path does not hang if the FW LLDP is stopped.
3461  * return true if lldp need to stop
3462  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3463  */
3464 static bool
3465 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3466 {
3467         double nvm_ver;
3468         char ver_str[64] = {0};
3469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3470
3471         i40e_fw_version_get(dev, ver_str, 64);
3472         nvm_ver = atof(ver_str);
3473         if ((hw->mac.type == I40E_MAC_X722 ||
3474              hw->mac.type == I40E_MAC_X722_VF) &&
3475              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3476                 return true;
3477         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3478                 return true;
3479
3480         return false;
3481 }
3482
3483 static void
3484 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3485 {
3486         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3487         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3488         struct i40e_vsi *vsi = pf->main_vsi;
3489         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3490
3491         dev_info->max_rx_queues = vsi->nb_qps;
3492         dev_info->max_tx_queues = vsi->nb_qps;
3493         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3494         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3495         dev_info->max_mac_addrs = vsi->max_macaddrs;
3496         dev_info->max_vfs = pci_dev->max_vfs;
3497         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3498         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3499         dev_info->rx_queue_offload_capa = 0;
3500         dev_info->rx_offload_capa =
3501                 DEV_RX_OFFLOAD_VLAN_STRIP |
3502                 DEV_RX_OFFLOAD_QINQ_STRIP |
3503                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3504                 DEV_RX_OFFLOAD_UDP_CKSUM |
3505                 DEV_RX_OFFLOAD_TCP_CKSUM |
3506                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3507                 DEV_RX_OFFLOAD_KEEP_CRC |
3508                 DEV_RX_OFFLOAD_SCATTER |
3509                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3510                 DEV_RX_OFFLOAD_VLAN_FILTER |
3511                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3512
3513         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3514         dev_info->tx_offload_capa =
3515                 DEV_TX_OFFLOAD_VLAN_INSERT |
3516                 DEV_TX_OFFLOAD_QINQ_INSERT |
3517                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3518                 DEV_TX_OFFLOAD_UDP_CKSUM |
3519                 DEV_TX_OFFLOAD_TCP_CKSUM |
3520                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3521                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3522                 DEV_TX_OFFLOAD_TCP_TSO |
3523                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3524                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3525                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3526                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3527                 DEV_TX_OFFLOAD_MULTI_SEGS |
3528                 dev_info->tx_queue_offload_capa;
3529         dev_info->dev_capa =
3530                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3531                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3532
3533         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3534                                                 sizeof(uint32_t);
3535         dev_info->reta_size = pf->hash_lut_size;
3536         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3537
3538         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3539                 .rx_thresh = {
3540                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3541                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3542                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3543                 },
3544                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3545                 .rx_drop_en = 0,
3546                 .offloads = 0,
3547         };
3548
3549         dev_info->default_txconf = (struct rte_eth_txconf) {
3550                 .tx_thresh = {
3551                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3552                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3553                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3554                 },
3555                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3556                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3557                 .offloads = 0,
3558         };
3559
3560         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3561                 .nb_max = I40E_MAX_RING_DESC,
3562                 .nb_min = I40E_MIN_RING_DESC,
3563                 .nb_align = I40E_ALIGN_RING_DESC,
3564         };
3565
3566         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3567                 .nb_max = I40E_MAX_RING_DESC,
3568                 .nb_min = I40E_MIN_RING_DESC,
3569                 .nb_align = I40E_ALIGN_RING_DESC,
3570                 .nb_seg_max = I40E_TX_MAX_SEG,
3571                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3572         };
3573
3574         if (pf->flags & I40E_FLAG_VMDQ) {
3575                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3576                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3577                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3578                                                 pf->max_nb_vmdq_vsi;
3579                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3580                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3581                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3582         }
3583
3584         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3585                 /* For XL710 */
3586                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3587                 dev_info->default_rxportconf.nb_queues = 2;
3588                 dev_info->default_txportconf.nb_queues = 2;
3589                 if (dev->data->nb_rx_queues == 1)
3590                         dev_info->default_rxportconf.ring_size = 2048;
3591                 else
3592                         dev_info->default_rxportconf.ring_size = 1024;
3593                 if (dev->data->nb_tx_queues == 1)
3594                         dev_info->default_txportconf.ring_size = 1024;
3595                 else
3596                         dev_info->default_txportconf.ring_size = 512;
3597
3598         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3599                 /* For XXV710 */
3600                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3601                 dev_info->default_rxportconf.nb_queues = 1;
3602                 dev_info->default_txportconf.nb_queues = 1;
3603                 dev_info->default_rxportconf.ring_size = 256;
3604                 dev_info->default_txportconf.ring_size = 256;
3605         } else {
3606                 /* For X710 */
3607                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3608                 dev_info->default_rxportconf.nb_queues = 1;
3609                 dev_info->default_txportconf.nb_queues = 1;
3610                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3611                         dev_info->default_rxportconf.ring_size = 512;
3612                         dev_info->default_txportconf.ring_size = 256;
3613                 } else {
3614                         dev_info->default_rxportconf.ring_size = 256;
3615                         dev_info->default_txportconf.ring_size = 256;
3616                 }
3617         }
3618         dev_info->default_rxportconf.burst_size = 32;
3619         dev_info->default_txportconf.burst_size = 32;
3620 }
3621
3622 static int
3623 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3624 {
3625         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3626         struct i40e_vsi *vsi = pf->main_vsi;
3627         PMD_INIT_FUNC_TRACE();
3628
3629         if (on)
3630                 return i40e_vsi_add_vlan(vsi, vlan_id);
3631         else
3632                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3633 }
3634
3635 static int
3636 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3637                                 enum rte_vlan_type vlan_type,
3638                                 uint16_t tpid, int qinq)
3639 {
3640         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3641         uint64_t reg_r = 0;
3642         uint64_t reg_w = 0;
3643         uint16_t reg_id = 3;
3644         int ret;
3645
3646         if (qinq) {
3647                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3648                         reg_id = 2;
3649         }
3650
3651         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3652                                           &reg_r, NULL);
3653         if (ret != I40E_SUCCESS) {
3654                 PMD_DRV_LOG(ERR,
3655                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3656                            reg_id);
3657                 return -EIO;
3658         }
3659         PMD_DRV_LOG(DEBUG,
3660                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3661                     reg_id, reg_r);
3662
3663         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3664         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3665         if (reg_r == reg_w) {
3666                 PMD_DRV_LOG(DEBUG, "No need to write");
3667                 return 0;
3668         }
3669
3670         ret = i40e_aq_debug_write_global_register(hw,
3671                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3672                                            reg_w, NULL);
3673         if (ret != I40E_SUCCESS) {
3674                 PMD_DRV_LOG(ERR,
3675                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3676                             reg_id);
3677                 return -EIO;
3678         }
3679         PMD_DRV_LOG(DEBUG,
3680                     "Global register 0x%08x is changed with value 0x%08x",
3681                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3682
3683         return 0;
3684 }
3685
3686 static int
3687 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3688                    enum rte_vlan_type vlan_type,
3689                    uint16_t tpid)
3690 {
3691         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3692         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3693         int qinq = dev->data->dev_conf.rxmode.offloads &
3694                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3695         int ret = 0;
3696
3697         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3698              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3699             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3700                 PMD_DRV_LOG(ERR,
3701                             "Unsupported vlan type.");
3702                 return -EINVAL;
3703         }
3704
3705         if (pf->support_multi_driver) {
3706                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3707                 return -ENOTSUP;
3708         }
3709
3710         /* 802.1ad frames ability is added in NVM API 1.7*/
3711         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3712                 if (qinq) {
3713                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3714                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3715                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3716                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3717                 } else {
3718                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3719                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3720                 }
3721                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3722                 if (ret != I40E_SUCCESS) {
3723                         PMD_DRV_LOG(ERR,
3724                                     "Set switch config failed aq_err: %d",
3725                                     hw->aq.asq_last_status);
3726                         ret = -EIO;
3727                 }
3728         } else
3729                 /* If NVM API < 1.7, keep the register setting */
3730                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3731                                                       tpid, qinq);
3732
3733         return ret;
3734 }
3735
3736 static int
3737 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3738 {
3739         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3740         struct i40e_vsi *vsi = pf->main_vsi;
3741         struct rte_eth_rxmode *rxmode;
3742
3743         rxmode = &dev->data->dev_conf.rxmode;
3744         if (mask & ETH_VLAN_FILTER_MASK) {
3745                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3746                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3747                 else
3748                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3749         }
3750
3751         if (mask & ETH_VLAN_STRIP_MASK) {
3752                 /* Enable or disable VLAN stripping */
3753                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3754                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3755                 else
3756                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3757         }
3758
3759         if (mask & ETH_VLAN_EXTEND_MASK) {
3760                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3761                         i40e_vsi_config_double_vlan(vsi, TRUE);
3762                         /* Set global registers with default ethertype. */
3763                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3764                                            RTE_ETHER_TYPE_VLAN);
3765                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3766                                            RTE_ETHER_TYPE_VLAN);
3767                 }
3768                 else
3769                         i40e_vsi_config_double_vlan(vsi, FALSE);
3770         }
3771
3772         return 0;
3773 }
3774
3775 static void
3776 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3777                           __rte_unused uint16_t queue,
3778                           __rte_unused int on)
3779 {
3780         PMD_INIT_FUNC_TRACE();
3781 }
3782
3783 static int
3784 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3785 {
3786         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3787         struct i40e_vsi *vsi = pf->main_vsi;
3788         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3789         struct i40e_vsi_vlan_pvid_info info;
3790
3791         memset(&info, 0, sizeof(info));
3792         info.on = on;
3793         if (info.on)
3794                 info.config.pvid = pvid;
3795         else {
3796                 info.config.reject.tagged =
3797                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3798                 info.config.reject.untagged =
3799                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3800         }
3801
3802         return i40e_vsi_vlan_pvid_set(vsi, &info);
3803 }
3804
3805 static int
3806 i40e_dev_led_on(struct rte_eth_dev *dev)
3807 {
3808         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3809         uint32_t mode = i40e_led_get(hw);
3810
3811         if (mode == 0)
3812                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3813
3814         return 0;
3815 }
3816
3817 static int
3818 i40e_dev_led_off(struct rte_eth_dev *dev)
3819 {
3820         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3821         uint32_t mode = i40e_led_get(hw);
3822
3823         if (mode != 0)
3824                 i40e_led_set(hw, 0, false);
3825
3826         return 0;
3827 }
3828
3829 static int
3830 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3831 {
3832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3834
3835         fc_conf->pause_time = pf->fc_conf.pause_time;
3836
3837         /* read out from register, in case they are modified by other port */
3838         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3839                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3840         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3841                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3842
3843         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3844         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3845
3846          /* Return current mode according to actual setting*/
3847         switch (hw->fc.current_mode) {
3848         case I40E_FC_FULL:
3849                 fc_conf->mode = RTE_FC_FULL;
3850                 break;
3851         case I40E_FC_TX_PAUSE:
3852                 fc_conf->mode = RTE_FC_TX_PAUSE;
3853                 break;
3854         case I40E_FC_RX_PAUSE:
3855                 fc_conf->mode = RTE_FC_RX_PAUSE;
3856                 break;
3857         case I40E_FC_NONE:
3858         default:
3859                 fc_conf->mode = RTE_FC_NONE;
3860         };
3861
3862         return 0;
3863 }
3864
3865 static int
3866 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3867 {
3868         uint32_t mflcn_reg, fctrl_reg, reg;
3869         uint32_t max_high_water;
3870         uint8_t i, aq_failure;
3871         int err;
3872         struct i40e_hw *hw;
3873         struct i40e_pf *pf;
3874         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3875                 [RTE_FC_NONE] = I40E_FC_NONE,
3876                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3877                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3878                 [RTE_FC_FULL] = I40E_FC_FULL
3879         };
3880
3881         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3882
3883         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3884         if ((fc_conf->high_water > max_high_water) ||
3885                         (fc_conf->high_water < fc_conf->low_water)) {
3886                 PMD_INIT_LOG(ERR,
3887                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3888                         max_high_water);
3889                 return -EINVAL;
3890         }
3891
3892         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3893         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3894         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3895
3896         pf->fc_conf.pause_time = fc_conf->pause_time;
3897         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3898         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3899
3900         PMD_INIT_FUNC_TRACE();
3901
3902         /* All the link flow control related enable/disable register
3903          * configuration is handle by the F/W
3904          */
3905         err = i40e_set_fc(hw, &aq_failure, true);
3906         if (err < 0)
3907                 return -ENOSYS;
3908
3909         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3910                 /* Configure flow control refresh threshold,
3911                  * the value for stat_tx_pause_refresh_timer[8]
3912                  * is used for global pause operation.
3913                  */
3914
3915                 I40E_WRITE_REG(hw,
3916                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3917                                pf->fc_conf.pause_time);
3918
3919                 /* configure the timer value included in transmitted pause
3920                  * frame,
3921                  * the value for stat_tx_pause_quanta[8] is used for global
3922                  * pause operation
3923                  */
3924                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3925                                pf->fc_conf.pause_time);
3926
3927                 fctrl_reg = I40E_READ_REG(hw,
3928                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3929
3930                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3931                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3932                 else
3933                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3934
3935                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3936                                fctrl_reg);
3937         } else {
3938                 /* Configure pause time (2 TCs per register) */
3939                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3940                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3941                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3942
3943                 /* Configure flow control refresh threshold value */
3944                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3945                                pf->fc_conf.pause_time / 2);
3946
3947                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3948
3949                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3950                  *depending on configuration
3951                  */
3952                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3953                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3954                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3955                 } else {
3956                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3957                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3958                 }
3959
3960                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3961         }
3962
3963         if (!pf->support_multi_driver) {
3964                 /* config water marker both based on the packets and bytes */
3965                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3966                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3967                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3968                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3969                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3970                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3971                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3972                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3973                                   << I40E_KILOSHIFT);
3974                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3975                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3976                                    << I40E_KILOSHIFT);
3977         } else {
3978                 PMD_DRV_LOG(ERR,
3979                             "Water marker configuration is not supported.");
3980         }
3981
3982         I40E_WRITE_FLUSH(hw);
3983
3984         return 0;
3985 }
3986
3987 static int
3988 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3989                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3990 {
3991         PMD_INIT_FUNC_TRACE();
3992
3993         return -ENOSYS;
3994 }
3995
3996 /* Add a MAC address, and update filters */
3997 static int
3998 i40e_macaddr_add(struct rte_eth_dev *dev,
3999                  struct rte_ether_addr *mac_addr,
4000                  __rte_unused uint32_t index,
4001                  uint32_t pool)
4002 {
4003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4004         struct i40e_mac_filter_info mac_filter;
4005         struct i40e_vsi *vsi;
4006         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4007         int ret;
4008
4009         /* If VMDQ not enabled or configured, return */
4010         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4011                           !pf->nb_cfg_vmdq_vsi)) {
4012                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4013                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4014                         pool);
4015                 return -ENOTSUP;
4016         }
4017
4018         if (pool > pf->nb_cfg_vmdq_vsi) {
4019                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4020                                 pool, pf->nb_cfg_vmdq_vsi);
4021                 return -EINVAL;
4022         }
4023
4024         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4025         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4026                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4027         else
4028                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4029
4030         if (pool == 0)
4031                 vsi = pf->main_vsi;
4032         else
4033                 vsi = pf->vmdq[pool - 1].vsi;
4034
4035         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4036         if (ret != I40E_SUCCESS) {
4037                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4038                 return -ENODEV;
4039         }
4040         return 0;
4041 }
4042
4043 /* Remove a MAC address, and update filters */
4044 static void
4045 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4046 {
4047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4048         struct i40e_vsi *vsi;
4049         struct rte_eth_dev_data *data = dev->data;
4050         struct rte_ether_addr *macaddr;
4051         int ret;
4052         uint32_t i;
4053         uint64_t pool_sel;
4054
4055         macaddr = &(data->mac_addrs[index]);
4056
4057         pool_sel = dev->data->mac_pool_sel[index];
4058
4059         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4060                 if (pool_sel & (1ULL << i)) {
4061                         if (i == 0)
4062                                 vsi = pf->main_vsi;
4063                         else {
4064                                 /* No VMDQ pool enabled or configured */
4065                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4066                                         (i > pf->nb_cfg_vmdq_vsi)) {
4067                                         PMD_DRV_LOG(ERR,
4068                                                 "No VMDQ pool enabled/configured");
4069                                         return;
4070                                 }
4071                                 vsi = pf->vmdq[i - 1].vsi;
4072                         }
4073                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4074
4075                         if (ret) {
4076                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4077                                 return;
4078                         }
4079                 }
4080         }
4081 }
4082
4083 /* Set perfect match or hash match of MAC and VLAN for a VF */
4084 static int
4085 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4086                  struct rte_eth_mac_filter *filter,
4087                  bool add)
4088 {
4089         struct i40e_hw *hw;
4090         struct i40e_mac_filter_info mac_filter;
4091         struct rte_ether_addr old_mac;
4092         struct rte_ether_addr *new_mac;
4093         struct i40e_pf_vf *vf = NULL;
4094         uint16_t vf_id;
4095         int ret;
4096
4097         if (pf == NULL) {
4098                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4099                 return -EINVAL;
4100         }
4101         hw = I40E_PF_TO_HW(pf);
4102
4103         if (filter == NULL) {
4104                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4105                 return -EINVAL;
4106         }
4107
4108         new_mac = &filter->mac_addr;
4109
4110         if (rte_is_zero_ether_addr(new_mac)) {
4111                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4112                 return -EINVAL;
4113         }
4114
4115         vf_id = filter->dst_id;
4116
4117         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4118                 PMD_DRV_LOG(ERR, "Invalid argument.");
4119                 return -EINVAL;
4120         }
4121         vf = &pf->vfs[vf_id];
4122
4123         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4124                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4125                 return -EINVAL;
4126         }
4127
4128         if (add) {
4129                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4130                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4131                                 RTE_ETHER_ADDR_LEN);
4132                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4133                                  RTE_ETHER_ADDR_LEN);
4134
4135                 mac_filter.filter_type = filter->filter_type;
4136                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4137                 if (ret != I40E_SUCCESS) {
4138                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4139                         return -1;
4140                 }
4141                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4142         } else {
4143                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4144                                 RTE_ETHER_ADDR_LEN);
4145                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4146                 if (ret != I40E_SUCCESS) {
4147                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4148                         return -1;
4149                 }
4150
4151                 /* Clear device address as it has been removed */
4152                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4153                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4154         }
4155
4156         return 0;
4157 }
4158
4159 /* MAC filter handle */
4160 static int
4161 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4162                 void *arg)
4163 {
4164         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4165         struct rte_eth_mac_filter *filter;
4166         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4167         int ret = I40E_NOT_SUPPORTED;
4168
4169         filter = (struct rte_eth_mac_filter *)(arg);
4170
4171         switch (filter_op) {
4172         case RTE_ETH_FILTER_NOP:
4173                 ret = I40E_SUCCESS;
4174                 break;
4175         case RTE_ETH_FILTER_ADD:
4176                 i40e_pf_disable_irq0(hw);
4177                 if (filter->is_vf)
4178                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4179                 i40e_pf_enable_irq0(hw);
4180                 break;
4181         case RTE_ETH_FILTER_DELETE:
4182                 i40e_pf_disable_irq0(hw);
4183                 if (filter->is_vf)
4184                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4185                 i40e_pf_enable_irq0(hw);
4186                 break;
4187         default:
4188                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4189                 ret = I40E_ERR_PARAM;
4190                 break;
4191         }
4192
4193         return ret;
4194 }
4195
4196 static int
4197 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4198 {
4199         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4200         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4201         uint32_t reg;
4202         int ret;
4203
4204         if (!lut)
4205                 return -EINVAL;
4206
4207         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4208                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4209                                           vsi->type != I40E_VSI_SRIOV,
4210                                           lut, lut_size);
4211                 if (ret) {
4212                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4213                         return ret;
4214                 }
4215         } else {
4216                 uint32_t *lut_dw = (uint32_t *)lut;
4217                 uint16_t i, lut_size_dw = lut_size / 4;
4218
4219                 if (vsi->type == I40E_VSI_SRIOV) {
4220                         for (i = 0; i <= lut_size_dw; i++) {
4221                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4222                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4223                         }
4224                 } else {
4225                         for (i = 0; i < lut_size_dw; i++)
4226                                 lut_dw[i] = I40E_READ_REG(hw,
4227                                                           I40E_PFQF_HLUT(i));
4228                 }
4229         }
4230
4231         return 0;
4232 }
4233
4234 int
4235 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4236 {
4237         struct i40e_pf *pf;
4238         struct i40e_hw *hw;
4239         int ret;
4240
4241         if (!vsi || !lut)
4242                 return -EINVAL;
4243
4244         pf = I40E_VSI_TO_PF(vsi);
4245         hw = I40E_VSI_TO_HW(vsi);
4246
4247         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4248                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4249                                           vsi->type != I40E_VSI_SRIOV,
4250                                           lut, lut_size);
4251                 if (ret) {
4252                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4253                         return ret;
4254                 }
4255         } else {
4256                 uint32_t *lut_dw = (uint32_t *)lut;
4257                 uint16_t i, lut_size_dw = lut_size / 4;
4258
4259                 if (vsi->type == I40E_VSI_SRIOV) {
4260                         for (i = 0; i < lut_size_dw; i++)
4261                                 I40E_WRITE_REG(
4262                                         hw,
4263                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4264                                         lut_dw[i]);
4265                 } else {
4266                         for (i = 0; i < lut_size_dw; i++)
4267                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4268                                                lut_dw[i]);
4269                 }
4270                 I40E_WRITE_FLUSH(hw);
4271         }
4272
4273         return 0;
4274 }
4275
4276 static int
4277 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4278                          struct rte_eth_rss_reta_entry64 *reta_conf,
4279                          uint16_t reta_size)
4280 {
4281         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4282         uint16_t i, lut_size = pf->hash_lut_size;
4283         uint16_t idx, shift;
4284         uint8_t *lut;
4285         int ret;
4286
4287         if (reta_size != lut_size ||
4288                 reta_size > ETH_RSS_RETA_SIZE_512) {
4289                 PMD_DRV_LOG(ERR,
4290                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4291                         reta_size, lut_size);
4292                 return -EINVAL;
4293         }
4294
4295         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4296         if (!lut) {
4297                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4298                 return -ENOMEM;
4299         }
4300         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4301         if (ret)
4302                 goto out;
4303         for (i = 0; i < reta_size; i++) {
4304                 idx = i / RTE_RETA_GROUP_SIZE;
4305                 shift = i % RTE_RETA_GROUP_SIZE;
4306                 if (reta_conf[idx].mask & (1ULL << shift))
4307                         lut[i] = reta_conf[idx].reta[shift];
4308         }
4309         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4310
4311         pf->adapter->rss_reta_updated = 1;
4312
4313 out:
4314         rte_free(lut);
4315
4316         return ret;
4317 }
4318
4319 static int
4320 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4321                         struct rte_eth_rss_reta_entry64 *reta_conf,
4322                         uint16_t reta_size)
4323 {
4324         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4325         uint16_t i, lut_size = pf->hash_lut_size;
4326         uint16_t idx, shift;
4327         uint8_t *lut;
4328         int ret;
4329
4330         if (reta_size != lut_size ||
4331                 reta_size > ETH_RSS_RETA_SIZE_512) {
4332                 PMD_DRV_LOG(ERR,
4333                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4334                         reta_size, lut_size);
4335                 return -EINVAL;
4336         }
4337
4338         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4339         if (!lut) {
4340                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4341                 return -ENOMEM;
4342         }
4343
4344         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4345         if (ret)
4346                 goto out;
4347         for (i = 0; i < reta_size; i++) {
4348                 idx = i / RTE_RETA_GROUP_SIZE;
4349                 shift = i % RTE_RETA_GROUP_SIZE;
4350                 if (reta_conf[idx].mask & (1ULL << shift))
4351                         reta_conf[idx].reta[shift] = lut[i];
4352         }
4353
4354 out:
4355         rte_free(lut);
4356
4357         return ret;
4358 }
4359
4360 /**
4361  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4362  * @hw:   pointer to the HW structure
4363  * @mem:  pointer to mem struct to fill out
4364  * @size: size of memory requested
4365  * @alignment: what to align the allocation to
4366  **/
4367 enum i40e_status_code
4368 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4369                         struct i40e_dma_mem *mem,
4370                         u64 size,
4371                         u32 alignment)
4372 {
4373         const struct rte_memzone *mz = NULL;
4374         char z_name[RTE_MEMZONE_NAMESIZE];
4375
4376         if (!mem)
4377                 return I40E_ERR_PARAM;
4378
4379         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4380         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4381                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4382         if (!mz)
4383                 return I40E_ERR_NO_MEMORY;
4384
4385         mem->size = size;
4386         mem->va = mz->addr;
4387         mem->pa = mz->iova;
4388         mem->zone = (const void *)mz;
4389         PMD_DRV_LOG(DEBUG,
4390                 "memzone %s allocated with physical address: %"PRIu64,
4391                 mz->name, mem->pa);
4392
4393         return I40E_SUCCESS;
4394 }
4395
4396 /**
4397  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4398  * @hw:   pointer to the HW structure
4399  * @mem:  ptr to mem struct to free
4400  **/
4401 enum i40e_status_code
4402 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4403                     struct i40e_dma_mem *mem)
4404 {
4405         if (!mem)
4406                 return I40E_ERR_PARAM;
4407
4408         PMD_DRV_LOG(DEBUG,
4409                 "memzone %s to be freed with physical address: %"PRIu64,
4410                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4411         rte_memzone_free((const struct rte_memzone *)mem->zone);
4412         mem->zone = NULL;
4413         mem->va = NULL;
4414         mem->pa = (u64)0;
4415
4416         return I40E_SUCCESS;
4417 }
4418
4419 /**
4420  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4421  * @hw:   pointer to the HW structure
4422  * @mem:  pointer to mem struct to fill out
4423  * @size: size of memory requested
4424  **/
4425 enum i40e_status_code
4426 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4427                          struct i40e_virt_mem *mem,
4428                          u32 size)
4429 {
4430         if (!mem)
4431                 return I40E_ERR_PARAM;
4432
4433         mem->size = size;
4434         mem->va = rte_zmalloc("i40e", size, 0);
4435
4436         if (mem->va)
4437                 return I40E_SUCCESS;
4438         else
4439                 return I40E_ERR_NO_MEMORY;
4440 }
4441
4442 /**
4443  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4444  * @hw:   pointer to the HW structure
4445  * @mem:  pointer to mem struct to free
4446  **/
4447 enum i40e_status_code
4448 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4449                      struct i40e_virt_mem *mem)
4450 {
4451         if (!mem)
4452                 return I40E_ERR_PARAM;
4453
4454         rte_free(mem->va);
4455         mem->va = NULL;
4456
4457         return I40E_SUCCESS;
4458 }
4459
4460 void
4461 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4462 {
4463         rte_spinlock_init(&sp->spinlock);
4464 }
4465
4466 void
4467 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4468 {
4469         rte_spinlock_lock(&sp->spinlock);
4470 }
4471
4472 void
4473 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4474 {
4475         rte_spinlock_unlock(&sp->spinlock);
4476 }
4477
4478 void
4479 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4480 {
4481         return;
4482 }
4483
4484 /**
4485  * Get the hardware capabilities, which will be parsed
4486  * and saved into struct i40e_hw.
4487  */
4488 static int
4489 i40e_get_cap(struct i40e_hw *hw)
4490 {
4491         struct i40e_aqc_list_capabilities_element_resp *buf;
4492         uint16_t len, size = 0;
4493         int ret;
4494
4495         /* Calculate a huge enough buff for saving response data temporarily */
4496         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4497                                                 I40E_MAX_CAP_ELE_NUM;
4498         buf = rte_zmalloc("i40e", len, 0);
4499         if (!buf) {
4500                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4501                 return I40E_ERR_NO_MEMORY;
4502         }
4503
4504         /* Get, parse the capabilities and save it to hw */
4505         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4506                         i40e_aqc_opc_list_func_capabilities, NULL);
4507         if (ret != I40E_SUCCESS)
4508                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4509
4510         /* Free the temporary buffer after being used */
4511         rte_free(buf);
4512
4513         return ret;
4514 }
4515
4516 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4517
4518 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4519                 const char *value,
4520                 void *opaque)
4521 {
4522         struct i40e_pf *pf;
4523         unsigned long num;
4524         char *end;
4525
4526         pf = (struct i40e_pf *)opaque;
4527         RTE_SET_USED(key);
4528
4529         errno = 0;
4530         num = strtoul(value, &end, 0);
4531         if (errno != 0 || end == value || *end != 0) {
4532                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4533                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4534                 return -(EINVAL);
4535         }
4536
4537         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4538                 pf->vf_nb_qp_max = (uint16_t)num;
4539         else
4540                 /* here return 0 to make next valid same argument work */
4541                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4542                             "power of 2 and equal or less than 16 !, Now it is "
4543                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4544
4545         return 0;
4546 }
4547
4548 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4549 {
4550         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4551         struct rte_kvargs *kvlist;
4552         int kvargs_count;
4553
4554         /* set default queue number per VF as 4 */
4555         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4556
4557         if (dev->device->devargs == NULL)
4558                 return 0;
4559
4560         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4561         if (kvlist == NULL)
4562                 return -(EINVAL);
4563
4564         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4565         if (!kvargs_count) {
4566                 rte_kvargs_free(kvlist);
4567                 return 0;
4568         }
4569
4570         if (kvargs_count > 1)
4571                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4572                             "the first invalid or last valid one is used !",
4573                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4574
4575         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4576                            i40e_pf_parse_vf_queue_number_handler, pf);
4577
4578         rte_kvargs_free(kvlist);
4579
4580         return 0;
4581 }
4582
4583 static int
4584 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4585 {
4586         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4587         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4588         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4589         uint16_t qp_count = 0, vsi_count = 0;
4590
4591         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4592                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4593                 return -EINVAL;
4594         }
4595
4596         i40e_pf_config_vf_rxq_number(dev);
4597
4598         /* Add the parameter init for LFC */
4599         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4600         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4601         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4602
4603         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4604         pf->max_num_vsi = hw->func_caps.num_vsis;
4605         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4606         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4607
4608         /* FDir queue/VSI allocation */
4609         pf->fdir_qp_offset = 0;
4610         if (hw->func_caps.fd) {
4611                 pf->flags |= I40E_FLAG_FDIR;
4612                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4613         } else {
4614                 pf->fdir_nb_qps = 0;
4615         }
4616         qp_count += pf->fdir_nb_qps;
4617         vsi_count += 1;
4618
4619         /* LAN queue/VSI allocation */
4620         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4621         if (!hw->func_caps.rss) {
4622                 pf->lan_nb_qps = 1;
4623         } else {
4624                 pf->flags |= I40E_FLAG_RSS;
4625                 if (hw->mac.type == I40E_MAC_X722)
4626                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4627                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4628         }
4629         qp_count += pf->lan_nb_qps;
4630         vsi_count += 1;
4631
4632         /* VF queue/VSI allocation */
4633         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4634         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4635                 pf->flags |= I40E_FLAG_SRIOV;
4636                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4637                 pf->vf_num = pci_dev->max_vfs;
4638                 PMD_DRV_LOG(DEBUG,
4639                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4640                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4641         } else {
4642                 pf->vf_nb_qps = 0;
4643                 pf->vf_num = 0;
4644         }
4645         qp_count += pf->vf_nb_qps * pf->vf_num;
4646         vsi_count += pf->vf_num;
4647
4648         /* VMDq queue/VSI allocation */
4649         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4650         pf->vmdq_nb_qps = 0;
4651         pf->max_nb_vmdq_vsi = 0;
4652         if (hw->func_caps.vmdq) {
4653                 if (qp_count < hw->func_caps.num_tx_qp &&
4654                         vsi_count < hw->func_caps.num_vsis) {
4655                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4656                                 qp_count) / pf->vmdq_nb_qp_max;
4657
4658                         /* Limit the maximum number of VMDq vsi to the maximum
4659                          * ethdev can support
4660                          */
4661                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4662                                 hw->func_caps.num_vsis - vsi_count);
4663                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4664                                 ETH_64_POOLS);
4665                         if (pf->max_nb_vmdq_vsi) {
4666                                 pf->flags |= I40E_FLAG_VMDQ;
4667                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4668                                 PMD_DRV_LOG(DEBUG,
4669                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4670                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4671                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4672                         } else {
4673                                 PMD_DRV_LOG(INFO,
4674                                         "No enough queues left for VMDq");
4675                         }
4676                 } else {
4677                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4678                 }
4679         }
4680         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4681         vsi_count += pf->max_nb_vmdq_vsi;
4682
4683         if (hw->func_caps.dcb)
4684                 pf->flags |= I40E_FLAG_DCB;
4685
4686         if (qp_count > hw->func_caps.num_tx_qp) {
4687                 PMD_DRV_LOG(ERR,
4688                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4689                         qp_count, hw->func_caps.num_tx_qp);
4690                 return -EINVAL;
4691         }
4692         if (vsi_count > hw->func_caps.num_vsis) {
4693                 PMD_DRV_LOG(ERR,
4694                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4695                         vsi_count, hw->func_caps.num_vsis);
4696                 return -EINVAL;
4697         }
4698
4699         return 0;
4700 }
4701
4702 static int
4703 i40e_pf_get_switch_config(struct i40e_pf *pf)
4704 {
4705         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4706         struct i40e_aqc_get_switch_config_resp *switch_config;
4707         struct i40e_aqc_switch_config_element_resp *element;
4708         uint16_t start_seid = 0, num_reported;
4709         int ret;
4710
4711         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4712                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4713         if (!switch_config) {
4714                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4715                 return -ENOMEM;
4716         }
4717
4718         /* Get the switch configurations */
4719         ret = i40e_aq_get_switch_config(hw, switch_config,
4720                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4721         if (ret != I40E_SUCCESS) {
4722                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4723                 goto fail;
4724         }
4725         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4726         if (num_reported != 1) { /* The number should be 1 */
4727                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4728                 goto fail;
4729         }
4730
4731         /* Parse the switch configuration elements */
4732         element = &(switch_config->element[0]);
4733         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4734                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4735                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4736         } else
4737                 PMD_DRV_LOG(INFO, "Unknown element type");
4738
4739 fail:
4740         rte_free(switch_config);
4741
4742         return ret;
4743 }
4744
4745 static int
4746 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4747                         uint32_t num)
4748 {
4749         struct pool_entry *entry;
4750
4751         if (pool == NULL || num == 0)
4752                 return -EINVAL;
4753
4754         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4755         if (entry == NULL) {
4756                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4757                 return -ENOMEM;
4758         }
4759
4760         /* queue heap initialize */
4761         pool->num_free = num;
4762         pool->num_alloc = 0;
4763         pool->base = base;
4764         LIST_INIT(&pool->alloc_list);
4765         LIST_INIT(&pool->free_list);
4766
4767         /* Initialize element  */
4768         entry->base = 0;
4769         entry->len = num;
4770
4771         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4772         return 0;
4773 }
4774
4775 static void
4776 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4777 {
4778         struct pool_entry *entry, *next_entry;
4779
4780         if (pool == NULL)
4781                 return;
4782
4783         for (entry = LIST_FIRST(&pool->alloc_list);
4784                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4785                         entry = next_entry) {
4786                 LIST_REMOVE(entry, next);
4787                 rte_free(entry);
4788         }
4789
4790         for (entry = LIST_FIRST(&pool->free_list);
4791                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4792                         entry = next_entry) {
4793                 LIST_REMOVE(entry, next);
4794                 rte_free(entry);
4795         }
4796
4797         pool->num_free = 0;
4798         pool->num_alloc = 0;
4799         pool->base = 0;
4800         LIST_INIT(&pool->alloc_list);
4801         LIST_INIT(&pool->free_list);
4802 }
4803
4804 static int
4805 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4806                        uint32_t base)
4807 {
4808         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4809         uint32_t pool_offset;
4810         int insert;
4811
4812         if (pool == NULL) {
4813                 PMD_DRV_LOG(ERR, "Invalid parameter");
4814                 return -EINVAL;
4815         }
4816
4817         pool_offset = base - pool->base;
4818         /* Lookup in alloc list */
4819         LIST_FOREACH(entry, &pool->alloc_list, next) {
4820                 if (entry->base == pool_offset) {
4821                         valid_entry = entry;
4822                         LIST_REMOVE(entry, next);
4823                         break;
4824                 }
4825         }
4826
4827         /* Not find, return */
4828         if (valid_entry == NULL) {
4829                 PMD_DRV_LOG(ERR, "Failed to find entry");
4830                 return -EINVAL;
4831         }
4832
4833         /**
4834          * Found it, move it to free list  and try to merge.
4835          * In order to make merge easier, always sort it by qbase.
4836          * Find adjacent prev and last entries.
4837          */
4838         prev = next = NULL;
4839         LIST_FOREACH(entry, &pool->free_list, next) {
4840                 if (entry->base > valid_entry->base) {
4841                         next = entry;
4842                         break;
4843                 }
4844                 prev = entry;
4845         }
4846
4847         insert = 0;
4848         /* Try to merge with next one*/
4849         if (next != NULL) {
4850                 /* Merge with next one */
4851                 if (valid_entry->base + valid_entry->len == next->base) {
4852                         next->base = valid_entry->base;
4853                         next->len += valid_entry->len;
4854                         rte_free(valid_entry);
4855                         valid_entry = next;
4856                         insert = 1;
4857                 }
4858         }
4859
4860         if (prev != NULL) {
4861                 /* Merge with previous one */
4862                 if (prev->base + prev->len == valid_entry->base) {
4863                         prev->len += valid_entry->len;
4864                         /* If it merge with next one, remove next node */
4865                         if (insert == 1) {
4866                                 LIST_REMOVE(valid_entry, next);
4867                                 rte_free(valid_entry);
4868                         } else {
4869                                 rte_free(valid_entry);
4870                                 insert = 1;
4871                         }
4872                 }
4873         }
4874
4875         /* Not find any entry to merge, insert */
4876         if (insert == 0) {
4877                 if (prev != NULL)
4878                         LIST_INSERT_AFTER(prev, valid_entry, next);
4879                 else if (next != NULL)
4880                         LIST_INSERT_BEFORE(next, valid_entry, next);
4881                 else /* It's empty list, insert to head */
4882                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4883         }
4884
4885         pool->num_free += valid_entry->len;
4886         pool->num_alloc -= valid_entry->len;
4887
4888         return 0;
4889 }
4890
4891 static int
4892 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4893                        uint16_t num)
4894 {
4895         struct pool_entry *entry, *valid_entry;
4896
4897         if (pool == NULL || num == 0) {
4898                 PMD_DRV_LOG(ERR, "Invalid parameter");
4899                 return -EINVAL;
4900         }
4901
4902         if (pool->num_free < num) {
4903                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4904                             num, pool->num_free);
4905                 return -ENOMEM;
4906         }
4907
4908         valid_entry = NULL;
4909         /* Lookup  in free list and find most fit one */
4910         LIST_FOREACH(entry, &pool->free_list, next) {
4911                 if (entry->len >= num) {
4912                         /* Find best one */
4913                         if (entry->len == num) {
4914                                 valid_entry = entry;
4915                                 break;
4916                         }
4917                         if (valid_entry == NULL || valid_entry->len > entry->len)
4918                                 valid_entry = entry;
4919                 }
4920         }
4921
4922         /* Not find one to satisfy the request, return */
4923         if (valid_entry == NULL) {
4924                 PMD_DRV_LOG(ERR, "No valid entry found");
4925                 return -ENOMEM;
4926         }
4927         /**
4928          * The entry have equal queue number as requested,
4929          * remove it from alloc_list.
4930          */
4931         if (valid_entry->len == num) {
4932                 LIST_REMOVE(valid_entry, next);
4933         } else {
4934                 /**
4935                  * The entry have more numbers than requested,
4936                  * create a new entry for alloc_list and minus its
4937                  * queue base and number in free_list.
4938                  */
4939                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4940                 if (entry == NULL) {
4941                         PMD_DRV_LOG(ERR,
4942                                 "Failed to allocate memory for resource pool");
4943                         return -ENOMEM;
4944                 }
4945                 entry->base = valid_entry->base;
4946                 entry->len = num;
4947                 valid_entry->base += num;
4948                 valid_entry->len -= num;
4949                 valid_entry = entry;
4950         }
4951
4952         /* Insert it into alloc list, not sorted */
4953         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4954
4955         pool->num_free -= valid_entry->len;
4956         pool->num_alloc += valid_entry->len;
4957
4958         return valid_entry->base + pool->base;
4959 }
4960
4961 /**
4962  * bitmap_is_subset - Check whether src2 is subset of src1
4963  **/
4964 static inline int
4965 bitmap_is_subset(uint8_t src1, uint8_t src2)
4966 {
4967         return !((src1 ^ src2) & src2);
4968 }
4969
4970 static enum i40e_status_code
4971 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4972 {
4973         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4974
4975         /* If DCB is not supported, only default TC is supported */
4976         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4977                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4978                 return I40E_NOT_SUPPORTED;
4979         }
4980
4981         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4982                 PMD_DRV_LOG(ERR,
4983                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4984                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4985                 return I40E_NOT_SUPPORTED;
4986         }
4987         return I40E_SUCCESS;
4988 }
4989
4990 int
4991 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4992                                 struct i40e_vsi_vlan_pvid_info *info)
4993 {
4994         struct i40e_hw *hw;
4995         struct i40e_vsi_context ctxt;
4996         uint8_t vlan_flags = 0;
4997         int ret;
4998
4999         if (vsi == NULL || info == NULL) {
5000                 PMD_DRV_LOG(ERR, "invalid parameters");
5001                 return I40E_ERR_PARAM;
5002         }
5003
5004         if (info->on) {
5005                 vsi->info.pvid = info->config.pvid;
5006                 /**
5007                  * If insert pvid is enabled, only tagged pkts are
5008                  * allowed to be sent out.
5009                  */
5010                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5011                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5012         } else {
5013                 vsi->info.pvid = 0;
5014                 if (info->config.reject.tagged == 0)
5015                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5016
5017                 if (info->config.reject.untagged == 0)
5018                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5019         }
5020         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5021                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5022         vsi->info.port_vlan_flags |= vlan_flags;
5023         vsi->info.valid_sections =
5024                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5025         memset(&ctxt, 0, sizeof(ctxt));
5026         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5027         ctxt.seid = vsi->seid;
5028
5029         hw = I40E_VSI_TO_HW(vsi);
5030         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5031         if (ret != I40E_SUCCESS)
5032                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5033
5034         return ret;
5035 }
5036
5037 static int
5038 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5039 {
5040         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5041         int i, ret;
5042         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5043
5044         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5045         if (ret != I40E_SUCCESS)
5046                 return ret;
5047
5048         if (!vsi->seid) {
5049                 PMD_DRV_LOG(ERR, "seid not valid");
5050                 return -EINVAL;
5051         }
5052
5053         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5054         tc_bw_data.tc_valid_bits = enabled_tcmap;
5055         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5056                 tc_bw_data.tc_bw_credits[i] =
5057                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5058
5059         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5060         if (ret != I40E_SUCCESS) {
5061                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5062                 return ret;
5063         }
5064
5065         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5066                                         sizeof(vsi->info.qs_handle));
5067         return I40E_SUCCESS;
5068 }
5069
5070 static enum i40e_status_code
5071 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5072                                  struct i40e_aqc_vsi_properties_data *info,
5073                                  uint8_t enabled_tcmap)
5074 {
5075         enum i40e_status_code ret;
5076         int i, total_tc = 0;
5077         uint16_t qpnum_per_tc, bsf, qp_idx;
5078
5079         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5080         if (ret != I40E_SUCCESS)
5081                 return ret;
5082
5083         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5084                 if (enabled_tcmap & (1 << i))
5085                         total_tc++;
5086         if (total_tc == 0)
5087                 total_tc = 1;
5088         vsi->enabled_tc = enabled_tcmap;
5089
5090         /* Number of queues per enabled TC */
5091         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5092         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5093         bsf = rte_bsf32(qpnum_per_tc);
5094
5095         /* Adjust the queue number to actual queues that can be applied */
5096         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5097                 vsi->nb_qps = qpnum_per_tc * total_tc;
5098
5099         /**
5100          * Configure TC and queue mapping parameters, for enabled TC,
5101          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5102          * default queue will serve it.
5103          */
5104         qp_idx = 0;
5105         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5106                 if (vsi->enabled_tc & (1 << i)) {
5107                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5108                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5109                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5110                         qp_idx += qpnum_per_tc;
5111                 } else
5112                         info->tc_mapping[i] = 0;
5113         }
5114
5115         /* Associate queue number with VSI */
5116         if (vsi->type == I40E_VSI_SRIOV) {
5117                 info->mapping_flags |=
5118                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5119                 for (i = 0; i < vsi->nb_qps; i++)
5120                         info->queue_mapping[i] =
5121                                 rte_cpu_to_le_16(vsi->base_queue + i);
5122         } else {
5123                 info->mapping_flags |=
5124                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5125                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5126         }
5127         info->valid_sections |=
5128                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5129
5130         return I40E_SUCCESS;
5131 }
5132
5133 static int
5134 i40e_veb_release(struct i40e_veb *veb)
5135 {
5136         struct i40e_vsi *vsi;
5137         struct i40e_hw *hw;
5138
5139         if (veb == NULL)
5140                 return -EINVAL;
5141
5142         if (!TAILQ_EMPTY(&veb->head)) {
5143                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5144                 return -EACCES;
5145         }
5146         /* associate_vsi field is NULL for floating VEB */
5147         if (veb->associate_vsi != NULL) {
5148                 vsi = veb->associate_vsi;
5149                 hw = I40E_VSI_TO_HW(vsi);
5150
5151                 vsi->uplink_seid = veb->uplink_seid;
5152                 vsi->veb = NULL;
5153         } else {
5154                 veb->associate_pf->main_vsi->floating_veb = NULL;
5155                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5156         }
5157
5158         i40e_aq_delete_element(hw, veb->seid, NULL);
5159         rte_free(veb);
5160         return I40E_SUCCESS;
5161 }
5162
5163 /* Setup a veb */
5164 static struct i40e_veb *
5165 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5166 {
5167         struct i40e_veb *veb;
5168         int ret;
5169         struct i40e_hw *hw;
5170
5171         if (pf == NULL) {
5172                 PMD_DRV_LOG(ERR,
5173                             "veb setup failed, associated PF shouldn't null");
5174                 return NULL;
5175         }
5176         hw = I40E_PF_TO_HW(pf);
5177
5178         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5179         if (!veb) {
5180                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5181                 goto fail;
5182         }
5183
5184         veb->associate_vsi = vsi;
5185         veb->associate_pf = pf;
5186         TAILQ_INIT(&veb->head);
5187         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5188
5189         /* create floating veb if vsi is NULL */
5190         if (vsi != NULL) {
5191                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5192                                       I40E_DEFAULT_TCMAP, false,
5193                                       &veb->seid, false, NULL);
5194         } else {
5195                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5196                                       true, &veb->seid, false, NULL);
5197         }
5198
5199         if (ret != I40E_SUCCESS) {
5200                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5201                             hw->aq.asq_last_status);
5202                 goto fail;
5203         }
5204         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5205
5206         /* get statistics index */
5207         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5208                                 &veb->stats_idx, NULL, NULL, NULL);
5209         if (ret != I40E_SUCCESS) {
5210                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5211                             hw->aq.asq_last_status);
5212                 goto fail;
5213         }
5214         /* Get VEB bandwidth, to be implemented */
5215         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5216         if (vsi)
5217                 vsi->uplink_seid = veb->seid;
5218
5219         return veb;
5220 fail:
5221         rte_free(veb);
5222         return NULL;
5223 }
5224
5225 int
5226 i40e_vsi_release(struct i40e_vsi *vsi)
5227 {
5228         struct i40e_pf *pf;
5229         struct i40e_hw *hw;
5230         struct i40e_vsi_list *vsi_list;
5231         void *temp;
5232         int ret;
5233         struct i40e_mac_filter *f;
5234         uint16_t user_param;
5235
5236         if (!vsi)
5237                 return I40E_SUCCESS;
5238
5239         if (!vsi->adapter)
5240                 return -EFAULT;
5241
5242         user_param = vsi->user_param;
5243
5244         pf = I40E_VSI_TO_PF(vsi);
5245         hw = I40E_VSI_TO_HW(vsi);
5246
5247         /* VSI has child to attach, release child first */
5248         if (vsi->veb) {
5249                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5250                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5251                                 return -1;
5252                 }
5253                 i40e_veb_release(vsi->veb);
5254         }
5255
5256         if (vsi->floating_veb) {
5257                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5258                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5259                                 return -1;
5260                 }
5261         }
5262
5263         /* Remove all macvlan filters of the VSI */
5264         i40e_vsi_remove_all_macvlan_filter(vsi);
5265         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5266                 rte_free(f);
5267
5268         if (vsi->type != I40E_VSI_MAIN &&
5269             ((vsi->type != I40E_VSI_SRIOV) ||
5270             !pf->floating_veb_list[user_param])) {
5271                 /* Remove vsi from parent's sibling list */
5272                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5273                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5274                         return I40E_ERR_PARAM;
5275                 }
5276                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5277                                 &vsi->sib_vsi_list, list);
5278
5279                 /* Remove all switch element of the VSI */
5280                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5281                 if (ret != I40E_SUCCESS)
5282                         PMD_DRV_LOG(ERR, "Failed to delete element");
5283         }
5284
5285         if ((vsi->type == I40E_VSI_SRIOV) &&
5286             pf->floating_veb_list[user_param]) {
5287                 /* Remove vsi from parent's sibling list */
5288                 if (vsi->parent_vsi == NULL ||
5289                     vsi->parent_vsi->floating_veb == NULL) {
5290                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5291                         return I40E_ERR_PARAM;
5292                 }
5293                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5294                              &vsi->sib_vsi_list, list);
5295
5296                 /* Remove all switch element of the VSI */
5297                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5298                 if (ret != I40E_SUCCESS)
5299                         PMD_DRV_LOG(ERR, "Failed to delete element");
5300         }
5301
5302         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5303
5304         if (vsi->type != I40E_VSI_SRIOV)
5305                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5306         rte_free(vsi);
5307
5308         return I40E_SUCCESS;
5309 }
5310
5311 static int
5312 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5313 {
5314         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5315         struct i40e_aqc_remove_macvlan_element_data def_filter;
5316         struct i40e_mac_filter_info filter;
5317         int ret;
5318
5319         if (vsi->type != I40E_VSI_MAIN)
5320                 return I40E_ERR_CONFIG;
5321         memset(&def_filter, 0, sizeof(def_filter));
5322         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5323                                         ETH_ADDR_LEN);
5324         def_filter.vlan_tag = 0;
5325         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5326                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5327         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5328         if (ret != I40E_SUCCESS) {
5329                 struct i40e_mac_filter *f;
5330                 struct rte_ether_addr *mac;
5331
5332                 PMD_DRV_LOG(DEBUG,
5333                             "Cannot remove the default macvlan filter");
5334                 /* It needs to add the permanent mac into mac list */
5335                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5336                 if (f == NULL) {
5337                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5338                         return I40E_ERR_NO_MEMORY;
5339                 }
5340                 mac = &f->mac_info.mac_addr;
5341                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5342                                 ETH_ADDR_LEN);
5343                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5344                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5345                 vsi->mac_num++;
5346
5347                 return ret;
5348         }
5349         rte_memcpy(&filter.mac_addr,
5350                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5351         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5352         return i40e_vsi_add_mac(vsi, &filter);
5353 }
5354
5355 /*
5356  * i40e_vsi_get_bw_config - Query VSI BW Information
5357  * @vsi: the VSI to be queried
5358  *
5359  * Returns 0 on success, negative value on failure
5360  */
5361 static enum i40e_status_code
5362 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5363 {
5364         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5365         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5366         struct i40e_hw *hw = &vsi->adapter->hw;
5367         i40e_status ret;
5368         int i;
5369         uint32_t bw_max;
5370
5371         memset(&bw_config, 0, sizeof(bw_config));
5372         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5373         if (ret != I40E_SUCCESS) {
5374                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5375                             hw->aq.asq_last_status);
5376                 return ret;
5377         }
5378
5379         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5380         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5381                                         &ets_sla_config, NULL);
5382         if (ret != I40E_SUCCESS) {
5383                 PMD_DRV_LOG(ERR,
5384                         "VSI failed to get TC bandwdith configuration %u",
5385                         hw->aq.asq_last_status);
5386                 return ret;
5387         }
5388
5389         /* store and print out BW info */
5390         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5391         vsi->bw_info.bw_max = bw_config.max_bw;
5392         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5393         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5394         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5395                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5396                      I40E_16_BIT_WIDTH);
5397         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5398                 vsi->bw_info.bw_ets_share_credits[i] =
5399                                 ets_sla_config.share_credits[i];
5400                 vsi->bw_info.bw_ets_credits[i] =
5401                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5402                 /* 4 bits per TC, 4th bit is reserved */
5403                 vsi->bw_info.bw_ets_max[i] =
5404                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5405                                   RTE_LEN2MASK(3, uint8_t));
5406                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5407                             vsi->bw_info.bw_ets_share_credits[i]);
5408                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5409                             vsi->bw_info.bw_ets_credits[i]);
5410                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5411                             vsi->bw_info.bw_ets_max[i]);
5412         }
5413
5414         return I40E_SUCCESS;
5415 }
5416
5417 /* i40e_enable_pf_lb
5418  * @pf: pointer to the pf structure
5419  *
5420  * allow loopback on pf
5421  */
5422 static inline void
5423 i40e_enable_pf_lb(struct i40e_pf *pf)
5424 {
5425         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5426         struct i40e_vsi_context ctxt;
5427         int ret;
5428
5429         /* Use the FW API if FW >= v5.0 */
5430         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5431                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5432                 return;
5433         }
5434
5435         memset(&ctxt, 0, sizeof(ctxt));
5436         ctxt.seid = pf->main_vsi_seid;
5437         ctxt.pf_num = hw->pf_id;
5438         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5439         if (ret) {
5440                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5441                             ret, hw->aq.asq_last_status);
5442                 return;
5443         }
5444         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5445         ctxt.info.valid_sections =
5446                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5447         ctxt.info.switch_id |=
5448                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5449
5450         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5451         if (ret)
5452                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5453                             hw->aq.asq_last_status);
5454 }
5455
5456 /* Setup a VSI */
5457 struct i40e_vsi *
5458 i40e_vsi_setup(struct i40e_pf *pf,
5459                enum i40e_vsi_type type,
5460                struct i40e_vsi *uplink_vsi,
5461                uint16_t user_param)
5462 {
5463         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5464         struct i40e_vsi *vsi;
5465         struct i40e_mac_filter_info filter;
5466         int ret;
5467         struct i40e_vsi_context ctxt;
5468         struct rte_ether_addr broadcast =
5469                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5470
5471         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5472             uplink_vsi == NULL) {
5473                 PMD_DRV_LOG(ERR,
5474                         "VSI setup failed, VSI link shouldn't be NULL");
5475                 return NULL;
5476         }
5477
5478         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5479                 PMD_DRV_LOG(ERR,
5480                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5481                 return NULL;
5482         }
5483
5484         /* two situations
5485          * 1.type is not MAIN and uplink vsi is not NULL
5486          * If uplink vsi didn't setup VEB, create one first under veb field
5487          * 2.type is SRIOV and the uplink is NULL
5488          * If floating VEB is NULL, create one veb under floating veb field
5489          */
5490
5491         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5492             uplink_vsi->veb == NULL) {
5493                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5494
5495                 if (uplink_vsi->veb == NULL) {
5496                         PMD_DRV_LOG(ERR, "VEB setup failed");
5497                         return NULL;
5498                 }
5499                 /* set ALLOWLOOPBACk on pf, when veb is created */
5500                 i40e_enable_pf_lb(pf);
5501         }
5502
5503         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5504             pf->main_vsi->floating_veb == NULL) {
5505                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5506
5507                 if (pf->main_vsi->floating_veb == NULL) {
5508                         PMD_DRV_LOG(ERR, "VEB setup failed");
5509                         return NULL;
5510                 }
5511         }
5512
5513         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5514         if (!vsi) {
5515                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5516                 return NULL;
5517         }
5518         TAILQ_INIT(&vsi->mac_list);
5519         vsi->type = type;
5520         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5521         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5522         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5523         vsi->user_param = user_param;
5524         vsi->vlan_anti_spoof_on = 0;
5525         vsi->vlan_filter_on = 0;
5526         /* Allocate queues */
5527         switch (vsi->type) {
5528         case I40E_VSI_MAIN  :
5529                 vsi->nb_qps = pf->lan_nb_qps;
5530                 break;
5531         case I40E_VSI_SRIOV :
5532                 vsi->nb_qps = pf->vf_nb_qps;
5533                 break;
5534         case I40E_VSI_VMDQ2:
5535                 vsi->nb_qps = pf->vmdq_nb_qps;
5536                 break;
5537         case I40E_VSI_FDIR:
5538                 vsi->nb_qps = pf->fdir_nb_qps;
5539                 break;
5540         default:
5541                 goto fail_mem;
5542         }
5543         /*
5544          * The filter status descriptor is reported in rx queue 0,
5545          * while the tx queue for fdir filter programming has no
5546          * such constraints, can be non-zero queues.
5547          * To simplify it, choose FDIR vsi use queue 0 pair.
5548          * To make sure it will use queue 0 pair, queue allocation
5549          * need be done before this function is called
5550          */
5551         if (type != I40E_VSI_FDIR) {
5552                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5553                         if (ret < 0) {
5554                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5555                                                 vsi->seid, ret);
5556                                 goto fail_mem;
5557                         }
5558                         vsi->base_queue = ret;
5559         } else
5560                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5561
5562         /* VF has MSIX interrupt in VF range, don't allocate here */
5563         if (type == I40E_VSI_MAIN) {
5564                 if (pf->support_multi_driver) {
5565                         /* If support multi-driver, need to use INT0 instead of
5566                          * allocating from msix pool. The Msix pool is init from
5567                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5568                          * to 1 without calling i40e_res_pool_alloc.
5569                          */
5570                         vsi->msix_intr = 0;
5571                         vsi->nb_msix = 1;
5572                 } else {
5573                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5574                                                   RTE_MIN(vsi->nb_qps,
5575                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5576                         if (ret < 0) {
5577                                 PMD_DRV_LOG(ERR,
5578                                             "VSI MAIN %d get heap failed %d",
5579                                             vsi->seid, ret);
5580                                 goto fail_queue_alloc;
5581                         }
5582                         vsi->msix_intr = ret;
5583                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5584                                                RTE_MAX_RXTX_INTR_VEC_ID);
5585                 }
5586         } else if (type != I40E_VSI_SRIOV) {
5587                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5588                 if (ret < 0) {
5589                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5590                         goto fail_queue_alloc;
5591                 }
5592                 vsi->msix_intr = ret;
5593                 vsi->nb_msix = 1;
5594         } else {
5595                 vsi->msix_intr = 0;
5596                 vsi->nb_msix = 0;
5597         }
5598
5599         /* Add VSI */
5600         if (type == I40E_VSI_MAIN) {
5601                 /* For main VSI, no need to add since it's default one */
5602                 vsi->uplink_seid = pf->mac_seid;
5603                 vsi->seid = pf->main_vsi_seid;
5604                 /* Bind queues with specific MSIX interrupt */
5605                 /**
5606                  * Needs 2 interrupt at least, one for misc cause which will
5607                  * enabled from OS side, Another for queues binding the
5608                  * interrupt from device side only.
5609                  */
5610
5611                 /* Get default VSI parameters from hardware */
5612                 memset(&ctxt, 0, sizeof(ctxt));
5613                 ctxt.seid = vsi->seid;
5614                 ctxt.pf_num = hw->pf_id;
5615                 ctxt.uplink_seid = vsi->uplink_seid;
5616                 ctxt.vf_num = 0;
5617                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5618                 if (ret != I40E_SUCCESS) {
5619                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5620                         goto fail_msix_alloc;
5621                 }
5622                 rte_memcpy(&vsi->info, &ctxt.info,
5623                         sizeof(struct i40e_aqc_vsi_properties_data));
5624                 vsi->vsi_id = ctxt.vsi_number;
5625                 vsi->info.valid_sections = 0;
5626
5627                 /* Configure tc, enabled TC0 only */
5628                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5629                         I40E_SUCCESS) {
5630                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5631                         goto fail_msix_alloc;
5632                 }
5633
5634                 /* TC, queue mapping */
5635                 memset(&ctxt, 0, sizeof(ctxt));
5636                 vsi->info.valid_sections |=
5637                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5638                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5639                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5640                 rte_memcpy(&ctxt.info, &vsi->info,
5641                         sizeof(struct i40e_aqc_vsi_properties_data));
5642                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5643                                                 I40E_DEFAULT_TCMAP);
5644                 if (ret != I40E_SUCCESS) {
5645                         PMD_DRV_LOG(ERR,
5646                                 "Failed to configure TC queue mapping");
5647                         goto fail_msix_alloc;
5648                 }
5649                 ctxt.seid = vsi->seid;
5650                 ctxt.pf_num = hw->pf_id;
5651                 ctxt.uplink_seid = vsi->uplink_seid;
5652                 ctxt.vf_num = 0;
5653
5654                 /* Update VSI parameters */
5655                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5656                 if (ret != I40E_SUCCESS) {
5657                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5658                         goto fail_msix_alloc;
5659                 }
5660
5661                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5662                                                 sizeof(vsi->info.tc_mapping));
5663                 rte_memcpy(&vsi->info.queue_mapping,
5664                                 &ctxt.info.queue_mapping,
5665                         sizeof(vsi->info.queue_mapping));
5666                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5667                 vsi->info.valid_sections = 0;
5668
5669                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5670                                 ETH_ADDR_LEN);
5671
5672                 /**
5673                  * Updating default filter settings are necessary to prevent
5674                  * reception of tagged packets.
5675                  * Some old firmware configurations load a default macvlan
5676                  * filter which accepts both tagged and untagged packets.
5677                  * The updating is to use a normal filter instead if needed.
5678                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5679                  * The firmware with correct configurations load the default
5680                  * macvlan filter which is expected and cannot be removed.
5681                  */
5682                 i40e_update_default_filter_setting(vsi);
5683                 i40e_config_qinq(hw, vsi);
5684         } else if (type == I40E_VSI_SRIOV) {
5685                 memset(&ctxt, 0, sizeof(ctxt));
5686                 /**
5687                  * For other VSI, the uplink_seid equals to uplink VSI's
5688                  * uplink_seid since they share same VEB
5689                  */
5690                 if (uplink_vsi == NULL)
5691                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5692                 else
5693                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5694                 ctxt.pf_num = hw->pf_id;
5695                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5696                 ctxt.uplink_seid = vsi->uplink_seid;
5697                 ctxt.connection_type = 0x1;
5698                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5699
5700                 /* Use the VEB configuration if FW >= v5.0 */
5701                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5702                         /* Configure switch ID */
5703                         ctxt.info.valid_sections |=
5704                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5705                         ctxt.info.switch_id =
5706                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5707                 }
5708
5709                 /* Configure port/vlan */
5710                 ctxt.info.valid_sections |=
5711                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5712                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5713                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5714                                                 hw->func_caps.enabled_tcmap);
5715                 if (ret != I40E_SUCCESS) {
5716                         PMD_DRV_LOG(ERR,
5717                                 "Failed to configure TC queue mapping");
5718                         goto fail_msix_alloc;
5719                 }
5720
5721                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5722                 ctxt.info.valid_sections |=
5723                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5724                 /**
5725                  * Since VSI is not created yet, only configure parameter,
5726                  * will add vsi below.
5727                  */
5728
5729                 i40e_config_qinq(hw, vsi);
5730         } else if (type == I40E_VSI_VMDQ2) {
5731                 memset(&ctxt, 0, sizeof(ctxt));
5732                 /*
5733                  * For other VSI, the uplink_seid equals to uplink VSI's
5734                  * uplink_seid since they share same VEB
5735                  */
5736                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5737                 ctxt.pf_num = hw->pf_id;
5738                 ctxt.vf_num = 0;
5739                 ctxt.uplink_seid = vsi->uplink_seid;
5740                 ctxt.connection_type = 0x1;
5741                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5742
5743                 ctxt.info.valid_sections |=
5744                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5745                 /* user_param carries flag to enable loop back */
5746                 if (user_param) {
5747                         ctxt.info.switch_id =
5748                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5749                         ctxt.info.switch_id |=
5750                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5751                 }
5752
5753                 /* Configure port/vlan */
5754                 ctxt.info.valid_sections |=
5755                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5756                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5757                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5758                                                 I40E_DEFAULT_TCMAP);
5759                 if (ret != I40E_SUCCESS) {
5760                         PMD_DRV_LOG(ERR,
5761                                 "Failed to configure TC queue mapping");
5762                         goto fail_msix_alloc;
5763                 }
5764                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5765                 ctxt.info.valid_sections |=
5766                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5767         } else if (type == I40E_VSI_FDIR) {
5768                 memset(&ctxt, 0, sizeof(ctxt));
5769                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5770                 ctxt.pf_num = hw->pf_id;
5771                 ctxt.vf_num = 0;
5772                 ctxt.uplink_seid = vsi->uplink_seid;
5773                 ctxt.connection_type = 0x1;     /* regular data port */
5774                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5775                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5776                                                 I40E_DEFAULT_TCMAP);
5777                 if (ret != I40E_SUCCESS) {
5778                         PMD_DRV_LOG(ERR,
5779                                 "Failed to configure TC queue mapping.");
5780                         goto fail_msix_alloc;
5781                 }
5782                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5783                 ctxt.info.valid_sections |=
5784                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5785         } else {
5786                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5787                 goto fail_msix_alloc;
5788         }
5789
5790         if (vsi->type != I40E_VSI_MAIN) {
5791                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5792                 if (ret != I40E_SUCCESS) {
5793                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5794                                     hw->aq.asq_last_status);
5795                         goto fail_msix_alloc;
5796                 }
5797                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5798                 vsi->info.valid_sections = 0;
5799                 vsi->seid = ctxt.seid;
5800                 vsi->vsi_id = ctxt.vsi_number;
5801                 vsi->sib_vsi_list.vsi = vsi;
5802                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5803                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5804                                           &vsi->sib_vsi_list, list);
5805                 } else {
5806                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5807                                           &vsi->sib_vsi_list, list);
5808                 }
5809         }
5810
5811         /* MAC/VLAN configuration */
5812         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5813         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5814
5815         ret = i40e_vsi_add_mac(vsi, &filter);
5816         if (ret != I40E_SUCCESS) {
5817                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5818                 goto fail_msix_alloc;
5819         }
5820
5821         /* Get VSI BW information */
5822         i40e_vsi_get_bw_config(vsi);
5823         return vsi;
5824 fail_msix_alloc:
5825         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5826 fail_queue_alloc:
5827         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5828 fail_mem:
5829         rte_free(vsi);
5830         return NULL;
5831 }
5832
5833 /* Configure vlan filter on or off */
5834 int
5835 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5836 {
5837         int i, num;
5838         struct i40e_mac_filter *f;
5839         void *temp;
5840         struct i40e_mac_filter_info *mac_filter;
5841         enum rte_mac_filter_type desired_filter;
5842         int ret = I40E_SUCCESS;
5843
5844         if (on) {
5845                 /* Filter to match MAC and VLAN */
5846                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5847         } else {
5848                 /* Filter to match only MAC */
5849                 desired_filter = RTE_MAC_PERFECT_MATCH;
5850         }
5851
5852         num = vsi->mac_num;
5853
5854         mac_filter = rte_zmalloc("mac_filter_info_data",
5855                                  num * sizeof(*mac_filter), 0);
5856         if (mac_filter == NULL) {
5857                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5858                 return I40E_ERR_NO_MEMORY;
5859         }
5860
5861         i = 0;
5862
5863         /* Remove all existing mac */
5864         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5865                 mac_filter[i] = f->mac_info;
5866                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5867                 if (ret) {
5868                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5869                                     on ? "enable" : "disable");
5870                         goto DONE;
5871                 }
5872                 i++;
5873         }
5874
5875         /* Override with new filter */
5876         for (i = 0; i < num; i++) {
5877                 mac_filter[i].filter_type = desired_filter;
5878                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5879                 if (ret) {
5880                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5881                                     on ? "enable" : "disable");
5882                         goto DONE;
5883                 }
5884         }
5885
5886 DONE:
5887         rte_free(mac_filter);
5888         return ret;
5889 }
5890
5891 /* Configure vlan stripping on or off */
5892 int
5893 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5894 {
5895         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5896         struct i40e_vsi_context ctxt;
5897         uint8_t vlan_flags;
5898         int ret = I40E_SUCCESS;
5899
5900         /* Check if it has been already on or off */
5901         if (vsi->info.valid_sections &
5902                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5903                 if (on) {
5904                         if ((vsi->info.port_vlan_flags &
5905                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5906                                 return 0; /* already on */
5907                 } else {
5908                         if ((vsi->info.port_vlan_flags &
5909                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5910                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5911                                 return 0; /* already off */
5912                 }
5913         }
5914
5915         if (on)
5916                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5917         else
5918                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5919         vsi->info.valid_sections =
5920                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5921         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5922         vsi->info.port_vlan_flags |= vlan_flags;
5923         ctxt.seid = vsi->seid;
5924         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5925         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5926         if (ret)
5927                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5928                             on ? "enable" : "disable");
5929
5930         return ret;
5931 }
5932
5933 static int
5934 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5935 {
5936         struct rte_eth_dev_data *data = dev->data;
5937         int ret;
5938         int mask = 0;
5939
5940         /* Apply vlan offload setting */
5941         mask = ETH_VLAN_STRIP_MASK |
5942                ETH_VLAN_FILTER_MASK |
5943                ETH_VLAN_EXTEND_MASK;
5944         ret = i40e_vlan_offload_set(dev, mask);
5945         if (ret) {
5946                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5947                 return ret;
5948         }
5949
5950         /* Apply pvid setting */
5951         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5952                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5953         if (ret)
5954                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5955
5956         return ret;
5957 }
5958
5959 static int
5960 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5961 {
5962         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5963
5964         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5965 }
5966
5967 static int
5968 i40e_update_flow_control(struct i40e_hw *hw)
5969 {
5970 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5971         struct i40e_link_status link_status;
5972         uint32_t rxfc = 0, txfc = 0, reg;
5973         uint8_t an_info;
5974         int ret;
5975
5976         memset(&link_status, 0, sizeof(link_status));
5977         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5978         if (ret != I40E_SUCCESS) {
5979                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5980                 goto write_reg; /* Disable flow control */
5981         }
5982
5983         an_info = hw->phy.link_info.an_info;
5984         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5985                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5986                 ret = I40E_ERR_NOT_READY;
5987                 goto write_reg; /* Disable flow control */
5988         }
5989         /**
5990          * If link auto negotiation is enabled, flow control needs to
5991          * be configured according to it
5992          */
5993         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5994         case I40E_LINK_PAUSE_RXTX:
5995                 rxfc = 1;
5996                 txfc = 1;
5997                 hw->fc.current_mode = I40E_FC_FULL;
5998                 break;
5999         case I40E_AQ_LINK_PAUSE_RX:
6000                 rxfc = 1;
6001                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6002                 break;
6003         case I40E_AQ_LINK_PAUSE_TX:
6004                 txfc = 1;
6005                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6006                 break;
6007         default:
6008                 hw->fc.current_mode = I40E_FC_NONE;
6009                 break;
6010         }
6011
6012 write_reg:
6013         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6014                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6015         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6016         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6017         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6018         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6019
6020         return ret;
6021 }
6022
6023 /* PF setup */
6024 static int
6025 i40e_pf_setup(struct i40e_pf *pf)
6026 {
6027         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6028         struct i40e_filter_control_settings settings;
6029         struct i40e_vsi *vsi;
6030         int ret;
6031
6032         /* Clear all stats counters */
6033         pf->offset_loaded = FALSE;
6034         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6035         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6036         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6037         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6038
6039         ret = i40e_pf_get_switch_config(pf);
6040         if (ret != I40E_SUCCESS) {
6041                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6042                 return ret;
6043         }
6044
6045         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6046         if (ret)
6047                 PMD_INIT_LOG(WARNING,
6048                         "failed to allocate switch domain for device %d", ret);
6049
6050         if (pf->flags & I40E_FLAG_FDIR) {
6051                 /* make queue allocated first, let FDIR use queue pair 0*/
6052                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6053                 if (ret != I40E_FDIR_QUEUE_ID) {
6054                         PMD_DRV_LOG(ERR,
6055                                 "queue allocation fails for FDIR: ret =%d",
6056                                 ret);
6057                         pf->flags &= ~I40E_FLAG_FDIR;
6058                 }
6059         }
6060         /*  main VSI setup */
6061         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6062         if (!vsi) {
6063                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6064                 return I40E_ERR_NOT_READY;
6065         }
6066         pf->main_vsi = vsi;
6067
6068         /* Configure filter control */
6069         memset(&settings, 0, sizeof(settings));
6070         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6071                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6072         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6073                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6074         else {
6075                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6076                         hw->func_caps.rss_table_size);
6077                 return I40E_ERR_PARAM;
6078         }
6079         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6080                 hw->func_caps.rss_table_size);
6081         pf->hash_lut_size = hw->func_caps.rss_table_size;
6082
6083         /* Enable ethtype and macvlan filters */
6084         settings.enable_ethtype = TRUE;
6085         settings.enable_macvlan = TRUE;
6086         ret = i40e_set_filter_control(hw, &settings);
6087         if (ret)
6088                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6089                                                                 ret);
6090
6091         /* Update flow control according to the auto negotiation */
6092         i40e_update_flow_control(hw);
6093
6094         return I40E_SUCCESS;
6095 }
6096
6097 int
6098 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6099 {
6100         uint32_t reg;
6101         uint16_t j;
6102
6103         /**
6104          * Set or clear TX Queue Disable flags,
6105          * which is required by hardware.
6106          */
6107         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6108         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6109
6110         /* Wait until the request is finished */
6111         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6112                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6113                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6114                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6115                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6116                                                         & 0x1))) {
6117                         break;
6118                 }
6119         }
6120         if (on) {
6121                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6122                         return I40E_SUCCESS; /* already on, skip next steps */
6123
6124                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6125                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6126         } else {
6127                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6128                         return I40E_SUCCESS; /* already off, skip next steps */
6129                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6130         }
6131         /* Write the register */
6132         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6133         /* Check the result */
6134         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6135                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6136                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6137                 if (on) {
6138                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6139                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6140                                 break;
6141                 } else {
6142                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6143                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6144                                 break;
6145                 }
6146         }
6147         /* Check if it is timeout */
6148         if (j >= I40E_CHK_Q_ENA_COUNT) {
6149                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6150                             (on ? "enable" : "disable"), q_idx);
6151                 return I40E_ERR_TIMEOUT;
6152         }
6153
6154         return I40E_SUCCESS;
6155 }
6156
6157 /* Swith on or off the tx queues */
6158 static int
6159 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6160 {
6161         struct rte_eth_dev_data *dev_data = pf->dev_data;
6162         struct i40e_tx_queue *txq;
6163         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6164         uint16_t i;
6165         int ret;
6166
6167         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6168                 txq = dev_data->tx_queues[i];
6169                 /* Don't operate the queue if not configured or
6170                  * if starting only per queue */
6171                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6172                         continue;
6173                 if (on)
6174                         ret = i40e_dev_tx_queue_start(dev, i);
6175                 else
6176                         ret = i40e_dev_tx_queue_stop(dev, i);
6177                 if ( ret != I40E_SUCCESS)
6178                         return ret;
6179         }
6180
6181         return I40E_SUCCESS;
6182 }
6183
6184 int
6185 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6186 {
6187         uint32_t reg;
6188         uint16_t j;
6189
6190         /* Wait until the request is finished */
6191         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6192                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6193                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6194                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6195                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6196                         break;
6197         }
6198
6199         if (on) {
6200                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6201                         return I40E_SUCCESS; /* Already on, skip next steps */
6202                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6203         } else {
6204                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6205                         return I40E_SUCCESS; /* Already off, skip next steps */
6206                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6207         }
6208
6209         /* Write the register */
6210         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6211         /* Check the result */
6212         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6213                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6214                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6215                 if (on) {
6216                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6217                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6218                                 break;
6219                 } else {
6220                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6221                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6222                                 break;
6223                 }
6224         }
6225
6226         /* Check if it is timeout */
6227         if (j >= I40E_CHK_Q_ENA_COUNT) {
6228                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6229                             (on ? "enable" : "disable"), q_idx);
6230                 return I40E_ERR_TIMEOUT;
6231         }
6232
6233         return I40E_SUCCESS;
6234 }
6235 /* Switch on or off the rx queues */
6236 static int
6237 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6238 {
6239         struct rte_eth_dev_data *dev_data = pf->dev_data;
6240         struct i40e_rx_queue *rxq;
6241         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6242         uint16_t i;
6243         int ret;
6244
6245         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6246                 rxq = dev_data->rx_queues[i];
6247                 /* Don't operate the queue if not configured or
6248                  * if starting only per queue */
6249                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6250                         continue;
6251                 if (on)
6252                         ret = i40e_dev_rx_queue_start(dev, i);
6253                 else
6254                         ret = i40e_dev_rx_queue_stop(dev, i);
6255                 if (ret != I40E_SUCCESS)
6256                         return ret;
6257         }
6258
6259         return I40E_SUCCESS;
6260 }
6261
6262 /* Switch on or off all the rx/tx queues */
6263 int
6264 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6265 {
6266         int ret;
6267
6268         if (on) {
6269                 /* enable rx queues before enabling tx queues */
6270                 ret = i40e_dev_switch_rx_queues(pf, on);
6271                 if (ret) {
6272                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6273                         return ret;
6274                 }
6275                 ret = i40e_dev_switch_tx_queues(pf, on);
6276         } else {
6277                 /* Stop tx queues before stopping rx queues */
6278                 ret = i40e_dev_switch_tx_queues(pf, on);
6279                 if (ret) {
6280                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6281                         return ret;
6282                 }
6283                 ret = i40e_dev_switch_rx_queues(pf, on);
6284         }
6285
6286         return ret;
6287 }
6288
6289 /* Initialize VSI for TX */
6290 static int
6291 i40e_dev_tx_init(struct i40e_pf *pf)
6292 {
6293         struct rte_eth_dev_data *data = pf->dev_data;
6294         uint16_t i;
6295         uint32_t ret = I40E_SUCCESS;
6296         struct i40e_tx_queue *txq;
6297
6298         for (i = 0; i < data->nb_tx_queues; i++) {
6299                 txq = data->tx_queues[i];
6300                 if (!txq || !txq->q_set)
6301                         continue;
6302                 ret = i40e_tx_queue_init(txq);
6303                 if (ret != I40E_SUCCESS)
6304                         break;
6305         }
6306         if (ret == I40E_SUCCESS)
6307                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6308                                      ->eth_dev);
6309
6310         return ret;
6311 }
6312
6313 /* Initialize VSI for RX */
6314 static int
6315 i40e_dev_rx_init(struct i40e_pf *pf)
6316 {
6317         struct rte_eth_dev_data *data = pf->dev_data;
6318         int ret = I40E_SUCCESS;
6319         uint16_t i;
6320         struct i40e_rx_queue *rxq;
6321
6322         i40e_pf_config_mq_rx(pf);
6323         for (i = 0; i < data->nb_rx_queues; i++) {
6324                 rxq = data->rx_queues[i];
6325                 if (!rxq || !rxq->q_set)
6326                         continue;
6327
6328                 ret = i40e_rx_queue_init(rxq);
6329                 if (ret != I40E_SUCCESS) {
6330                         PMD_DRV_LOG(ERR,
6331                                 "Failed to do RX queue initialization");
6332                         break;
6333                 }
6334         }
6335         if (ret == I40E_SUCCESS)
6336                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6337                                      ->eth_dev);
6338
6339         return ret;
6340 }
6341
6342 static int
6343 i40e_dev_rxtx_init(struct i40e_pf *pf)
6344 {
6345         int err;
6346
6347         err = i40e_dev_tx_init(pf);
6348         if (err) {
6349                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6350                 return err;
6351         }
6352         err = i40e_dev_rx_init(pf);
6353         if (err) {
6354                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6355                 return err;
6356         }
6357
6358         return err;
6359 }
6360
6361 static int
6362 i40e_vmdq_setup(struct rte_eth_dev *dev)
6363 {
6364         struct rte_eth_conf *conf = &dev->data->dev_conf;
6365         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6366         int i, err, conf_vsis, j, loop;
6367         struct i40e_vsi *vsi;
6368         struct i40e_vmdq_info *vmdq_info;
6369         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6370         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6371
6372         /*
6373          * Disable interrupt to avoid message from VF. Furthermore, it will
6374          * avoid race condition in VSI creation/destroy.
6375          */
6376         i40e_pf_disable_irq0(hw);
6377
6378         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6379                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6380                 return -ENOTSUP;
6381         }
6382
6383         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6384         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6385                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6386                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6387                         pf->max_nb_vmdq_vsi);
6388                 return -ENOTSUP;
6389         }
6390
6391         if (pf->vmdq != NULL) {
6392                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6393                 return 0;
6394         }
6395
6396         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6397                                 sizeof(*vmdq_info) * conf_vsis, 0);
6398
6399         if (pf->vmdq == NULL) {
6400                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6401                 return -ENOMEM;
6402         }
6403
6404         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6405
6406         /* Create VMDQ VSI */
6407         for (i = 0; i < conf_vsis; i++) {
6408                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6409                                 vmdq_conf->enable_loop_back);
6410                 if (vsi == NULL) {
6411                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6412                         err = -1;
6413                         goto err_vsi_setup;
6414                 }
6415                 vmdq_info = &pf->vmdq[i];
6416                 vmdq_info->pf = pf;
6417                 vmdq_info->vsi = vsi;
6418         }
6419         pf->nb_cfg_vmdq_vsi = conf_vsis;
6420
6421         /* Configure Vlan */
6422         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6423         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6424                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6425                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6426                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6427                                         vmdq_conf->pool_map[i].vlan_id, j);
6428
6429                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6430                                                 vmdq_conf->pool_map[i].vlan_id);
6431                                 if (err) {
6432                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6433                                         err = -1;
6434                                         goto err_vsi_setup;
6435                                 }
6436                         }
6437                 }
6438         }
6439
6440         i40e_pf_enable_irq0(hw);
6441
6442         return 0;
6443
6444 err_vsi_setup:
6445         for (i = 0; i < conf_vsis; i++)
6446                 if (pf->vmdq[i].vsi == NULL)
6447                         break;
6448                 else
6449                         i40e_vsi_release(pf->vmdq[i].vsi);
6450
6451         rte_free(pf->vmdq);
6452         pf->vmdq = NULL;
6453         i40e_pf_enable_irq0(hw);
6454         return err;
6455 }
6456
6457 static void
6458 i40e_stat_update_32(struct i40e_hw *hw,
6459                    uint32_t reg,
6460                    bool offset_loaded,
6461                    uint64_t *offset,
6462                    uint64_t *stat)
6463 {
6464         uint64_t new_data;
6465
6466         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6467         if (!offset_loaded)
6468                 *offset = new_data;
6469
6470         if (new_data >= *offset)
6471                 *stat = (uint64_t)(new_data - *offset);
6472         else
6473                 *stat = (uint64_t)((new_data +
6474                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6475 }
6476
6477 static void
6478 i40e_stat_update_48(struct i40e_hw *hw,
6479                    uint32_t hireg,
6480                    uint32_t loreg,
6481                    bool offset_loaded,
6482                    uint64_t *offset,
6483                    uint64_t *stat)
6484 {
6485         uint64_t new_data;
6486
6487         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6488         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6489                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6490
6491         if (!offset_loaded)
6492                 *offset = new_data;
6493
6494         if (new_data >= *offset)
6495                 *stat = new_data - *offset;
6496         else
6497                 *stat = (uint64_t)((new_data +
6498                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6499
6500         *stat &= I40E_48_BIT_MASK;
6501 }
6502
6503 /* Disable IRQ0 */
6504 void
6505 i40e_pf_disable_irq0(struct i40e_hw *hw)
6506 {
6507         /* Disable all interrupt types */
6508         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6509                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6510         I40E_WRITE_FLUSH(hw);
6511 }
6512
6513 /* Enable IRQ0 */
6514 void
6515 i40e_pf_enable_irq0(struct i40e_hw *hw)
6516 {
6517         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6518                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6519                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6520                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6521         I40E_WRITE_FLUSH(hw);
6522 }
6523
6524 static void
6525 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6526 {
6527         /* read pending request and disable first */
6528         i40e_pf_disable_irq0(hw);
6529         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6530         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6531                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6532
6533         if (no_queue)
6534                 /* Link no queues with irq0 */
6535                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6536                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6537 }
6538
6539 static void
6540 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6541 {
6542         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6543         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6544         int i;
6545         uint16_t abs_vf_id;
6546         uint32_t index, offset, val;
6547
6548         if (!pf->vfs)
6549                 return;
6550         /**
6551          * Try to find which VF trigger a reset, use absolute VF id to access
6552          * since the reg is global register.
6553          */
6554         for (i = 0; i < pf->vf_num; i++) {
6555                 abs_vf_id = hw->func_caps.vf_base_id + i;
6556                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6557                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6558                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6559                 /* VFR event occurred */
6560                 if (val & (0x1 << offset)) {
6561                         int ret;
6562
6563                         /* Clear the event first */
6564                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6565                                                         (0x1 << offset));
6566                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6567                         /**
6568                          * Only notify a VF reset event occurred,
6569                          * don't trigger another SW reset
6570                          */
6571                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6572                         if (ret != I40E_SUCCESS)
6573                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6574                 }
6575         }
6576 }
6577
6578 static void
6579 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6580 {
6581         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6582         int i;
6583
6584         for (i = 0; i < pf->vf_num; i++)
6585                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6586 }
6587
6588 static void
6589 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6590 {
6591         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6592         struct i40e_arq_event_info info;
6593         uint16_t pending, opcode;
6594         int ret;
6595
6596         info.buf_len = I40E_AQ_BUF_SZ;
6597         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6598         if (!info.msg_buf) {
6599                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6600                 return;
6601         }
6602
6603         pending = 1;
6604         while (pending) {
6605                 ret = i40e_clean_arq_element(hw, &info, &pending);
6606
6607                 if (ret != I40E_SUCCESS) {
6608                         PMD_DRV_LOG(INFO,
6609                                 "Failed to read msg from AdminQ, aq_err: %u",
6610                                 hw->aq.asq_last_status);
6611                         break;
6612                 }
6613                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6614
6615                 switch (opcode) {
6616                 case i40e_aqc_opc_send_msg_to_pf:
6617                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6618                         i40e_pf_host_handle_vf_msg(dev,
6619                                         rte_le_to_cpu_16(info.desc.retval),
6620                                         rte_le_to_cpu_32(info.desc.cookie_high),
6621                                         rte_le_to_cpu_32(info.desc.cookie_low),
6622                                         info.msg_buf,
6623                                         info.msg_len);
6624                         break;
6625                 case i40e_aqc_opc_get_link_status:
6626                         ret = i40e_dev_link_update(dev, 0);
6627                         if (!ret)
6628                                 _rte_eth_dev_callback_process(dev,
6629                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6630                         break;
6631                 default:
6632                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6633                                     opcode);
6634                         break;
6635                 }
6636         }
6637         rte_free(info.msg_buf);
6638 }
6639
6640 /**
6641  * Interrupt handler triggered by NIC  for handling
6642  * specific interrupt.
6643  *
6644  * @param handle
6645  *  Pointer to interrupt handle.
6646  * @param param
6647  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6648  *
6649  * @return
6650  *  void
6651  */
6652 static void
6653 i40e_dev_interrupt_handler(void *param)
6654 {
6655         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6657         uint32_t icr0;
6658
6659         /* Disable interrupt */
6660         i40e_pf_disable_irq0(hw);
6661
6662         /* read out interrupt causes */
6663         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6664
6665         /* No interrupt event indicated */
6666         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6667                 PMD_DRV_LOG(INFO, "No interrupt event");
6668                 goto done;
6669         }
6670         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6671                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6672         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6673                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6674         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6675                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6676         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6677                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6678         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6679                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6680         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6681                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6682         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6683                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6684
6685         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6686                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6687                 i40e_dev_handle_vfr_event(dev);
6688         }
6689         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6690                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6691                 i40e_dev_handle_aq_msg(dev);
6692         }
6693
6694 done:
6695         /* Enable interrupt */
6696         i40e_pf_enable_irq0(hw);
6697 }
6698
6699 static void
6700 i40e_dev_alarm_handler(void *param)
6701 {
6702         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6703         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6704         uint32_t icr0;
6705
6706         /* Disable interrupt */
6707         i40e_pf_disable_irq0(hw);
6708
6709         /* read out interrupt causes */
6710         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6711
6712         /* No interrupt event indicated */
6713         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6714                 goto done;
6715         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6716                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6717         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6718                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6719         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6720                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6721         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6722                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6723         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6724                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6725         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6726                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6727         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6728                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6729
6730         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6731                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6732                 i40e_dev_handle_vfr_event(dev);
6733         }
6734         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6735                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6736                 i40e_dev_handle_aq_msg(dev);
6737         }
6738
6739 done:
6740         /* Enable interrupt */
6741         i40e_pf_enable_irq0(hw);
6742         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6743                           i40e_dev_alarm_handler, dev);
6744 }
6745
6746 int
6747 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6748                          struct i40e_macvlan_filter *filter,
6749                          int total)
6750 {
6751         int ele_num, ele_buff_size;
6752         int num, actual_num, i;
6753         uint16_t flags;
6754         int ret = I40E_SUCCESS;
6755         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6756         struct i40e_aqc_add_macvlan_element_data *req_list;
6757
6758         if (filter == NULL  || total == 0)
6759                 return I40E_ERR_PARAM;
6760         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6761         ele_buff_size = hw->aq.asq_buf_size;
6762
6763         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6764         if (req_list == NULL) {
6765                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6766                 return I40E_ERR_NO_MEMORY;
6767         }
6768
6769         num = 0;
6770         do {
6771                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6772                 memset(req_list, 0, ele_buff_size);
6773
6774                 for (i = 0; i < actual_num; i++) {
6775                         rte_memcpy(req_list[i].mac_addr,
6776                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6777                         req_list[i].vlan_tag =
6778                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6779
6780                         switch (filter[num + i].filter_type) {
6781                         case RTE_MAC_PERFECT_MATCH:
6782                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6783                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6784                                 break;
6785                         case RTE_MACVLAN_PERFECT_MATCH:
6786                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6787                                 break;
6788                         case RTE_MAC_HASH_MATCH:
6789                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6790                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6791                                 break;
6792                         case RTE_MACVLAN_HASH_MATCH:
6793                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6794                                 break;
6795                         default:
6796                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6797                                 ret = I40E_ERR_PARAM;
6798                                 goto DONE;
6799                         }
6800
6801                         req_list[i].queue_number = 0;
6802
6803                         req_list[i].flags = rte_cpu_to_le_16(flags);
6804                 }
6805
6806                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6807                                                 actual_num, NULL);
6808                 if (ret != I40E_SUCCESS) {
6809                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6810                         goto DONE;
6811                 }
6812                 num += actual_num;
6813         } while (num < total);
6814
6815 DONE:
6816         rte_free(req_list);
6817         return ret;
6818 }
6819
6820 int
6821 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6822                             struct i40e_macvlan_filter *filter,
6823                             int total)
6824 {
6825         int ele_num, ele_buff_size;
6826         int num, actual_num, i;
6827         uint16_t flags;
6828         int ret = I40E_SUCCESS;
6829         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6830         struct i40e_aqc_remove_macvlan_element_data *req_list;
6831
6832         if (filter == NULL  || total == 0)
6833                 return I40E_ERR_PARAM;
6834
6835         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6836         ele_buff_size = hw->aq.asq_buf_size;
6837
6838         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6839         if (req_list == NULL) {
6840                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6841                 return I40E_ERR_NO_MEMORY;
6842         }
6843
6844         num = 0;
6845         do {
6846                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6847                 memset(req_list, 0, ele_buff_size);
6848
6849                 for (i = 0; i < actual_num; i++) {
6850                         rte_memcpy(req_list[i].mac_addr,
6851                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6852                         req_list[i].vlan_tag =
6853                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6854
6855                         switch (filter[num + i].filter_type) {
6856                         case RTE_MAC_PERFECT_MATCH:
6857                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6858                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6859                                 break;
6860                         case RTE_MACVLAN_PERFECT_MATCH:
6861                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6862                                 break;
6863                         case RTE_MAC_HASH_MATCH:
6864                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6865                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6866                                 break;
6867                         case RTE_MACVLAN_HASH_MATCH:
6868                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6869                                 break;
6870                         default:
6871                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6872                                 ret = I40E_ERR_PARAM;
6873                                 goto DONE;
6874                         }
6875                         req_list[i].flags = rte_cpu_to_le_16(flags);
6876                 }
6877
6878                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6879                                                 actual_num, NULL);
6880                 if (ret != I40E_SUCCESS) {
6881                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6882                         goto DONE;
6883                 }
6884                 num += actual_num;
6885         } while (num < total);
6886
6887 DONE:
6888         rte_free(req_list);
6889         return ret;
6890 }
6891
6892 /* Find out specific MAC filter */
6893 static struct i40e_mac_filter *
6894 i40e_find_mac_filter(struct i40e_vsi *vsi,
6895                          struct rte_ether_addr *macaddr)
6896 {
6897         struct i40e_mac_filter *f;
6898
6899         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6900                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6901                         return f;
6902         }
6903
6904         return NULL;
6905 }
6906
6907 static bool
6908 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6909                          uint16_t vlan_id)
6910 {
6911         uint32_t vid_idx, vid_bit;
6912
6913         if (vlan_id > ETH_VLAN_ID_MAX)
6914                 return 0;
6915
6916         vid_idx = I40E_VFTA_IDX(vlan_id);
6917         vid_bit = I40E_VFTA_BIT(vlan_id);
6918
6919         if (vsi->vfta[vid_idx] & vid_bit)
6920                 return 1;
6921         else
6922                 return 0;
6923 }
6924
6925 static void
6926 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6927                        uint16_t vlan_id, bool on)
6928 {
6929         uint32_t vid_idx, vid_bit;
6930
6931         vid_idx = I40E_VFTA_IDX(vlan_id);
6932         vid_bit = I40E_VFTA_BIT(vlan_id);
6933
6934         if (on)
6935                 vsi->vfta[vid_idx] |= vid_bit;
6936         else
6937                 vsi->vfta[vid_idx] &= ~vid_bit;
6938 }
6939
6940 void
6941 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6942                      uint16_t vlan_id, bool on)
6943 {
6944         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6945         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6946         int ret;
6947
6948         if (vlan_id > ETH_VLAN_ID_MAX)
6949                 return;
6950
6951         i40e_store_vlan_filter(vsi, vlan_id, on);
6952
6953         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6954                 return;
6955
6956         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6957
6958         if (on) {
6959                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6960                                        &vlan_data, 1, NULL);
6961                 if (ret != I40E_SUCCESS)
6962                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6963         } else {
6964                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6965                                           &vlan_data, 1, NULL);
6966                 if (ret != I40E_SUCCESS)
6967                         PMD_DRV_LOG(ERR,
6968                                     "Failed to remove vlan filter");
6969         }
6970 }
6971
6972 /**
6973  * Find all vlan options for specific mac addr,
6974  * return with actual vlan found.
6975  */
6976 int
6977 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6978                            struct i40e_macvlan_filter *mv_f,
6979                            int num, struct rte_ether_addr *addr)
6980 {
6981         int i;
6982         uint32_t j, k;
6983
6984         /**
6985          * Not to use i40e_find_vlan_filter to decrease the loop time,
6986          * although the code looks complex.
6987           */
6988         if (num < vsi->vlan_num)
6989                 return I40E_ERR_PARAM;
6990
6991         i = 0;
6992         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6993                 if (vsi->vfta[j]) {
6994                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6995                                 if (vsi->vfta[j] & (1 << k)) {
6996                                         if (i > num - 1) {
6997                                                 PMD_DRV_LOG(ERR,
6998                                                         "vlan number doesn't match");
6999                                                 return I40E_ERR_PARAM;
7000                                         }
7001                                         rte_memcpy(&mv_f[i].macaddr,
7002                                                         addr, ETH_ADDR_LEN);
7003                                         mv_f[i].vlan_id =
7004                                                 j * I40E_UINT32_BIT_SIZE + k;
7005                                         i++;
7006                                 }
7007                         }
7008                 }
7009         }
7010         return I40E_SUCCESS;
7011 }
7012
7013 static inline int
7014 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7015                            struct i40e_macvlan_filter *mv_f,
7016                            int num,
7017                            uint16_t vlan)
7018 {
7019         int i = 0;
7020         struct i40e_mac_filter *f;
7021
7022         if (num < vsi->mac_num)
7023                 return I40E_ERR_PARAM;
7024
7025         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7026                 if (i > num - 1) {
7027                         PMD_DRV_LOG(ERR, "buffer number not match");
7028                         return I40E_ERR_PARAM;
7029                 }
7030                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7031                                 ETH_ADDR_LEN);
7032                 mv_f[i].vlan_id = vlan;
7033                 mv_f[i].filter_type = f->mac_info.filter_type;
7034                 i++;
7035         }
7036
7037         return I40E_SUCCESS;
7038 }
7039
7040 static int
7041 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7042 {
7043         int i, j, num;
7044         struct i40e_mac_filter *f;
7045         struct i40e_macvlan_filter *mv_f;
7046         int ret = I40E_SUCCESS;
7047
7048         if (vsi == NULL || vsi->mac_num == 0)
7049                 return I40E_ERR_PARAM;
7050
7051         /* Case that no vlan is set */
7052         if (vsi->vlan_num == 0)
7053                 num = vsi->mac_num;
7054         else
7055                 num = vsi->mac_num * vsi->vlan_num;
7056
7057         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7058         if (mv_f == NULL) {
7059                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7060                 return I40E_ERR_NO_MEMORY;
7061         }
7062
7063         i = 0;
7064         if (vsi->vlan_num == 0) {
7065                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7066                         rte_memcpy(&mv_f[i].macaddr,
7067                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7068                         mv_f[i].filter_type = f->mac_info.filter_type;
7069                         mv_f[i].vlan_id = 0;
7070                         i++;
7071                 }
7072         } else {
7073                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7074                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7075                                         vsi->vlan_num, &f->mac_info.mac_addr);
7076                         if (ret != I40E_SUCCESS)
7077                                 goto DONE;
7078                         for (j = i; j < i + vsi->vlan_num; j++)
7079                                 mv_f[j].filter_type = f->mac_info.filter_type;
7080                         i += vsi->vlan_num;
7081                 }
7082         }
7083
7084         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7085 DONE:
7086         rte_free(mv_f);
7087
7088         return ret;
7089 }
7090
7091 int
7092 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7093 {
7094         struct i40e_macvlan_filter *mv_f;
7095         int mac_num;
7096         int ret = I40E_SUCCESS;
7097
7098         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7099                 return I40E_ERR_PARAM;
7100
7101         /* If it's already set, just return */
7102         if (i40e_find_vlan_filter(vsi,vlan))
7103                 return I40E_SUCCESS;
7104
7105         mac_num = vsi->mac_num;
7106
7107         if (mac_num == 0) {
7108                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7109                 return I40E_ERR_PARAM;
7110         }
7111
7112         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7113
7114         if (mv_f == NULL) {
7115                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7116                 return I40E_ERR_NO_MEMORY;
7117         }
7118
7119         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7120
7121         if (ret != I40E_SUCCESS)
7122                 goto DONE;
7123
7124         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7125
7126         if (ret != I40E_SUCCESS)
7127                 goto DONE;
7128
7129         i40e_set_vlan_filter(vsi, vlan, 1);
7130
7131         vsi->vlan_num++;
7132         ret = I40E_SUCCESS;
7133 DONE:
7134         rte_free(mv_f);
7135         return ret;
7136 }
7137
7138 int
7139 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7140 {
7141         struct i40e_macvlan_filter *mv_f;
7142         int mac_num;
7143         int ret = I40E_SUCCESS;
7144
7145         /**
7146          * Vlan 0 is the generic filter for untagged packets
7147          * and can't be removed.
7148          */
7149         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7150                 return I40E_ERR_PARAM;
7151
7152         /* If can't find it, just return */
7153         if (!i40e_find_vlan_filter(vsi, vlan))
7154                 return I40E_ERR_PARAM;
7155
7156         mac_num = vsi->mac_num;
7157
7158         if (mac_num == 0) {
7159                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7160                 return I40E_ERR_PARAM;
7161         }
7162
7163         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7164
7165         if (mv_f == NULL) {
7166                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7167                 return I40E_ERR_NO_MEMORY;
7168         }
7169
7170         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7171
7172         if (ret != I40E_SUCCESS)
7173                 goto DONE;
7174
7175         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7176
7177         if (ret != I40E_SUCCESS)
7178                 goto DONE;
7179
7180         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7181         if (vsi->vlan_num == 1) {
7182                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7183                 if (ret != I40E_SUCCESS)
7184                         goto DONE;
7185
7186                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7187                 if (ret != I40E_SUCCESS)
7188                         goto DONE;
7189         }
7190
7191         i40e_set_vlan_filter(vsi, vlan, 0);
7192
7193         vsi->vlan_num--;
7194         ret = I40E_SUCCESS;
7195 DONE:
7196         rte_free(mv_f);
7197         return ret;
7198 }
7199
7200 int
7201 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7202 {
7203         struct i40e_mac_filter *f;
7204         struct i40e_macvlan_filter *mv_f;
7205         int i, vlan_num = 0;
7206         int ret = I40E_SUCCESS;
7207
7208         /* If it's add and we've config it, return */
7209         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7210         if (f != NULL)
7211                 return I40E_SUCCESS;
7212         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7213                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7214
7215                 /**
7216                  * If vlan_num is 0, that's the first time to add mac,
7217                  * set mask for vlan_id 0.
7218                  */
7219                 if (vsi->vlan_num == 0) {
7220                         i40e_set_vlan_filter(vsi, 0, 1);
7221                         vsi->vlan_num = 1;
7222                 }
7223                 vlan_num = vsi->vlan_num;
7224         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7225                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7226                 vlan_num = 1;
7227
7228         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7229         if (mv_f == NULL) {
7230                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7231                 return I40E_ERR_NO_MEMORY;
7232         }
7233
7234         for (i = 0; i < vlan_num; i++) {
7235                 mv_f[i].filter_type = mac_filter->filter_type;
7236                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7237                                 ETH_ADDR_LEN);
7238         }
7239
7240         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7241                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7242                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7243                                         &mac_filter->mac_addr);
7244                 if (ret != I40E_SUCCESS)
7245                         goto DONE;
7246         }
7247
7248         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7249         if (ret != I40E_SUCCESS)
7250                 goto DONE;
7251
7252         /* Add the mac addr into mac list */
7253         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7254         if (f == NULL) {
7255                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7256                 ret = I40E_ERR_NO_MEMORY;
7257                 goto DONE;
7258         }
7259         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7260                         ETH_ADDR_LEN);
7261         f->mac_info.filter_type = mac_filter->filter_type;
7262         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7263         vsi->mac_num++;
7264
7265         ret = I40E_SUCCESS;
7266 DONE:
7267         rte_free(mv_f);
7268
7269         return ret;
7270 }
7271
7272 int
7273 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7274 {
7275         struct i40e_mac_filter *f;
7276         struct i40e_macvlan_filter *mv_f;
7277         int i, vlan_num;
7278         enum rte_mac_filter_type filter_type;
7279         int ret = I40E_SUCCESS;
7280
7281         /* Can't find it, return an error */
7282         f = i40e_find_mac_filter(vsi, addr);
7283         if (f == NULL)
7284                 return I40E_ERR_PARAM;
7285
7286         vlan_num = vsi->vlan_num;
7287         filter_type = f->mac_info.filter_type;
7288         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7289                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7290                 if (vlan_num == 0) {
7291                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7292                         return I40E_ERR_PARAM;
7293                 }
7294         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7295                         filter_type == RTE_MAC_HASH_MATCH)
7296                 vlan_num = 1;
7297
7298         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7299         if (mv_f == NULL) {
7300                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7301                 return I40E_ERR_NO_MEMORY;
7302         }
7303
7304         for (i = 0; i < vlan_num; i++) {
7305                 mv_f[i].filter_type = filter_type;
7306                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7307                                 ETH_ADDR_LEN);
7308         }
7309         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7310                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7311                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7312                 if (ret != I40E_SUCCESS)
7313                         goto DONE;
7314         }
7315
7316         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7317         if (ret != I40E_SUCCESS)
7318                 goto DONE;
7319
7320         /* Remove the mac addr into mac list */
7321         TAILQ_REMOVE(&vsi->mac_list, f, next);
7322         rte_free(f);
7323         vsi->mac_num--;
7324
7325         ret = I40E_SUCCESS;
7326 DONE:
7327         rte_free(mv_f);
7328         return ret;
7329 }
7330
7331 /* Configure hash enable flags for RSS */
7332 uint64_t
7333 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7334 {
7335         uint64_t hena = 0;
7336         int i;
7337
7338         if (!flags)
7339                 return hena;
7340
7341         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7342                 if (flags & (1ULL << i))
7343                         hena |= adapter->pctypes_tbl[i];
7344         }
7345
7346         return hena;
7347 }
7348
7349 /* Parse the hash enable flags */
7350 uint64_t
7351 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7352 {
7353         uint64_t rss_hf = 0;
7354
7355         if (!flags)
7356                 return rss_hf;
7357         int i;
7358
7359         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7360                 if (flags & adapter->pctypes_tbl[i])
7361                         rss_hf |= (1ULL << i);
7362         }
7363         return rss_hf;
7364 }
7365
7366 /* Disable RSS */
7367 static void
7368 i40e_pf_disable_rss(struct i40e_pf *pf)
7369 {
7370         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7371
7372         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7373         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7374         I40E_WRITE_FLUSH(hw);
7375 }
7376
7377 int
7378 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7379 {
7380         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7381         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7382         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7383                            I40E_VFQF_HKEY_MAX_INDEX :
7384                            I40E_PFQF_HKEY_MAX_INDEX;
7385         int ret = 0;
7386
7387         if (!key || key_len == 0) {
7388                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7389                 return 0;
7390         } else if (key_len != (key_idx + 1) *
7391                 sizeof(uint32_t)) {
7392                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7393                 return -EINVAL;
7394         }
7395
7396         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7397                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7398                         (struct i40e_aqc_get_set_rss_key_data *)key;
7399
7400                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7401                 if (ret)
7402                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7403         } else {
7404                 uint32_t *hash_key = (uint32_t *)key;
7405                 uint16_t i;
7406
7407                 if (vsi->type == I40E_VSI_SRIOV) {
7408                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7409                                 I40E_WRITE_REG(
7410                                         hw,
7411                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7412                                         hash_key[i]);
7413
7414                 } else {
7415                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7416                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7417                                                hash_key[i]);
7418                 }
7419                 I40E_WRITE_FLUSH(hw);
7420         }
7421
7422         return ret;
7423 }
7424
7425 static int
7426 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7427 {
7428         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7429         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7430         uint32_t reg;
7431         int ret;
7432
7433         if (!key || !key_len)
7434                 return 0;
7435
7436         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7437                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7438                         (struct i40e_aqc_get_set_rss_key_data *)key);
7439                 if (ret) {
7440                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7441                         return ret;
7442                 }
7443         } else {
7444                 uint32_t *key_dw = (uint32_t *)key;
7445                 uint16_t i;
7446
7447                 if (vsi->type == I40E_VSI_SRIOV) {
7448                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7449                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7450                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7451                         }
7452                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7453                                    sizeof(uint32_t);
7454                 } else {
7455                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7456                                 reg = I40E_PFQF_HKEY(i);
7457                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7458                         }
7459                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7460                                    sizeof(uint32_t);
7461                 }
7462         }
7463         return 0;
7464 }
7465
7466 static int
7467 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7468 {
7469         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7470         uint64_t hena;
7471         int ret;
7472
7473         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7474                                rss_conf->rss_key_len);
7475         if (ret)
7476                 return ret;
7477
7478         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7479         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7480         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7481         I40E_WRITE_FLUSH(hw);
7482
7483         return 0;
7484 }
7485
7486 static int
7487 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7488                          struct rte_eth_rss_conf *rss_conf)
7489 {
7490         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7491         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7492         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7493         uint64_t hena;
7494
7495         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7496         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7497
7498         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7499                 if (rss_hf != 0) /* Enable RSS */
7500                         return -EINVAL;
7501                 return 0; /* Nothing to do */
7502         }
7503         /* RSS enabled */
7504         if (rss_hf == 0) /* Disable RSS */
7505                 return -EINVAL;
7506
7507         return i40e_hw_rss_hash_set(pf, rss_conf);
7508 }
7509
7510 static int
7511 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7512                            struct rte_eth_rss_conf *rss_conf)
7513 {
7514         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7515         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7516         uint64_t hena;
7517         int ret;
7518
7519         if (!rss_conf)
7520                 return -EINVAL;
7521
7522         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7523                          &rss_conf->rss_key_len);
7524         if (ret)
7525                 return ret;
7526
7527         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7528         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7529         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7530
7531         return 0;
7532 }
7533
7534 static int
7535 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7536 {
7537         switch (filter_type) {
7538         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7539                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7540                 break;
7541         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7542                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7543                 break;
7544         case RTE_TUNNEL_FILTER_IMAC_TENID:
7545                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7546                 break;
7547         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7548                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7549                 break;
7550         case ETH_TUNNEL_FILTER_IMAC:
7551                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7552                 break;
7553         case ETH_TUNNEL_FILTER_OIP:
7554                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7555                 break;
7556         case ETH_TUNNEL_FILTER_IIP:
7557                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7558                 break;
7559         default:
7560                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7561                 return -EINVAL;
7562         }
7563
7564         return 0;
7565 }
7566
7567 /* Convert tunnel filter structure */
7568 static int
7569 i40e_tunnel_filter_convert(
7570         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7571         struct i40e_tunnel_filter *tunnel_filter)
7572 {
7573         rte_ether_addr_copy((struct rte_ether_addr *)
7574                         &cld_filter->element.outer_mac,
7575                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7576         rte_ether_addr_copy((struct rte_ether_addr *)
7577                         &cld_filter->element.inner_mac,
7578                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7579         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7580         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7581              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7582             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7583                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7584         else
7585                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7586         tunnel_filter->input.flags = cld_filter->element.flags;
7587         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7588         tunnel_filter->queue = cld_filter->element.queue_number;
7589         rte_memcpy(tunnel_filter->input.general_fields,
7590                    cld_filter->general_fields,
7591                    sizeof(cld_filter->general_fields));
7592
7593         return 0;
7594 }
7595
7596 /* Check if there exists the tunnel filter */
7597 struct i40e_tunnel_filter *
7598 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7599                              const struct i40e_tunnel_filter_input *input)
7600 {
7601         int ret;
7602
7603         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7604         if (ret < 0)
7605                 return NULL;
7606
7607         return tunnel_rule->hash_map[ret];
7608 }
7609
7610 /* Add a tunnel filter into the SW list */
7611 static int
7612 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7613                              struct i40e_tunnel_filter *tunnel_filter)
7614 {
7615         struct i40e_tunnel_rule *rule = &pf->tunnel;
7616         int ret;
7617
7618         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7619         if (ret < 0) {
7620                 PMD_DRV_LOG(ERR,
7621                             "Failed to insert tunnel filter to hash table %d!",
7622                             ret);
7623                 return ret;
7624         }
7625         rule->hash_map[ret] = tunnel_filter;
7626
7627         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7628
7629         return 0;
7630 }
7631
7632 /* Delete a tunnel filter from the SW list */
7633 int
7634 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7635                           struct i40e_tunnel_filter_input *input)
7636 {
7637         struct i40e_tunnel_rule *rule = &pf->tunnel;
7638         struct i40e_tunnel_filter *tunnel_filter;
7639         int ret;
7640
7641         ret = rte_hash_del_key(rule->hash_table, input);
7642         if (ret < 0) {
7643                 PMD_DRV_LOG(ERR,
7644                             "Failed to delete tunnel filter to hash table %d!",
7645                             ret);
7646                 return ret;
7647         }
7648         tunnel_filter = rule->hash_map[ret];
7649         rule->hash_map[ret] = NULL;
7650
7651         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7652         rte_free(tunnel_filter);
7653
7654         return 0;
7655 }
7656
7657 int
7658 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7659                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7660                         uint8_t add)
7661 {
7662         uint16_t ip_type;
7663         uint32_t ipv4_addr, ipv4_addr_le;
7664         uint8_t i, tun_type = 0;
7665         /* internal varialbe to convert ipv6 byte order */
7666         uint32_t convert_ipv6[4];
7667         int val, ret = 0;
7668         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7669         struct i40e_vsi *vsi = pf->main_vsi;
7670         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7671         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7672         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7673         struct i40e_tunnel_filter *tunnel, *node;
7674         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7675
7676         cld_filter = rte_zmalloc("tunnel_filter",
7677                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7678         0);
7679
7680         if (NULL == cld_filter) {
7681                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7682                 return -ENOMEM;
7683         }
7684         pfilter = cld_filter;
7685
7686         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7687                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7688         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7689                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7690
7691         pfilter->element.inner_vlan =
7692                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7693         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7694                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7695                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7696                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7697                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7698                                 &ipv4_addr_le,
7699                                 sizeof(pfilter->element.ipaddr.v4.data));
7700         } else {
7701                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7702                 for (i = 0; i < 4; i++) {
7703                         convert_ipv6[i] =
7704                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7705                 }
7706                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7707                            &convert_ipv6,
7708                            sizeof(pfilter->element.ipaddr.v6.data));
7709         }
7710
7711         /* check tunneled type */
7712         switch (tunnel_filter->tunnel_type) {
7713         case RTE_TUNNEL_TYPE_VXLAN:
7714                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7715                 break;
7716         case RTE_TUNNEL_TYPE_NVGRE:
7717                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7718                 break;
7719         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7720                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7721                 break;
7722         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7723                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7724                 break;
7725         default:
7726                 /* Other tunnel types is not supported. */
7727                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7728                 rte_free(cld_filter);
7729                 return -EINVAL;
7730         }
7731
7732         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7733                                        &pfilter->element.flags);
7734         if (val < 0) {
7735                 rte_free(cld_filter);
7736                 return -EINVAL;
7737         }
7738
7739         pfilter->element.flags |= rte_cpu_to_le_16(
7740                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7741                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7742         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7743         pfilter->element.queue_number =
7744                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7745
7746         /* Check if there is the filter in SW list */
7747         memset(&check_filter, 0, sizeof(check_filter));
7748         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7749         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7750         if (add && node) {
7751                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7752                 rte_free(cld_filter);
7753                 return -EINVAL;
7754         }
7755
7756         if (!add && !node) {
7757                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7758                 rte_free(cld_filter);
7759                 return -EINVAL;
7760         }
7761
7762         if (add) {
7763                 ret = i40e_aq_add_cloud_filters(hw,
7764                                         vsi->seid, &cld_filter->element, 1);
7765                 if (ret < 0) {
7766                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7767                         rte_free(cld_filter);
7768                         return -ENOTSUP;
7769                 }
7770                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7771                 if (tunnel == NULL) {
7772                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7773                         rte_free(cld_filter);
7774                         return -ENOMEM;
7775                 }
7776
7777                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7778                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7779                 if (ret < 0)
7780                         rte_free(tunnel);
7781         } else {
7782                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7783                                                    &cld_filter->element, 1);
7784                 if (ret < 0) {
7785                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7786                         rte_free(cld_filter);
7787                         return -ENOTSUP;
7788                 }
7789                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7790         }
7791
7792         rte_free(cld_filter);
7793         return ret;
7794 }
7795
7796 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7797 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7798 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7799 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7800 #define I40E_TR_GRE_KEY_MASK                    0x400
7801 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7802 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7803
7804 static enum
7805 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7806 {
7807         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7808         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7809         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7810         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7811         enum i40e_status_code status = I40E_SUCCESS;
7812
7813         if (pf->support_multi_driver) {
7814                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7815                 return I40E_NOT_SUPPORTED;
7816         }
7817
7818         memset(&filter_replace, 0,
7819                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7820         memset(&filter_replace_buf, 0,
7821                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7822
7823         /* create L1 filter */
7824         filter_replace.old_filter_type =
7825                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7826         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7827         filter_replace.tr_bit = 0;
7828
7829         /* Prepare the buffer, 3 entries */
7830         filter_replace_buf.data[0] =
7831                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7832         filter_replace_buf.data[0] |=
7833                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7834         filter_replace_buf.data[2] = 0xFF;
7835         filter_replace_buf.data[3] = 0xFF;
7836         filter_replace_buf.data[4] =
7837                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7838         filter_replace_buf.data[4] |=
7839                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7840         filter_replace_buf.data[7] = 0xF0;
7841         filter_replace_buf.data[8]
7842                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7843         filter_replace_buf.data[8] |=
7844                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7845         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7846                 I40E_TR_GENEVE_KEY_MASK |
7847                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7848         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7849                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7850                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7851
7852         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7853                                                &filter_replace_buf);
7854         if (!status && (filter_replace.old_filter_type !=
7855                         filter_replace.new_filter_type))
7856                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7857                             " original: 0x%x, new: 0x%x",
7858                             dev->device->name,
7859                             filter_replace.old_filter_type,
7860                             filter_replace.new_filter_type);
7861
7862         return status;
7863 }
7864
7865 static enum
7866 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7867 {
7868         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7869         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7870         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7871         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7872         enum i40e_status_code status = I40E_SUCCESS;
7873
7874         if (pf->support_multi_driver) {
7875                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7876                 return I40E_NOT_SUPPORTED;
7877         }
7878
7879         /* For MPLSoUDP */
7880         memset(&filter_replace, 0,
7881                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7882         memset(&filter_replace_buf, 0,
7883                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7884         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7885                 I40E_AQC_MIRROR_CLOUD_FILTER;
7886         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7887         filter_replace.new_filter_type =
7888                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7889         /* Prepare the buffer, 2 entries */
7890         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7891         filter_replace_buf.data[0] |=
7892                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7893         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7894         filter_replace_buf.data[4] |=
7895                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7896         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7897                                                &filter_replace_buf);
7898         if (status < 0)
7899                 return status;
7900         if (filter_replace.old_filter_type !=
7901             filter_replace.new_filter_type)
7902                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7903                             " original: 0x%x, new: 0x%x",
7904                             dev->device->name,
7905                             filter_replace.old_filter_type,
7906                             filter_replace.new_filter_type);
7907
7908         /* For MPLSoGRE */
7909         memset(&filter_replace, 0,
7910                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7911         memset(&filter_replace_buf, 0,
7912                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7913
7914         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7915                 I40E_AQC_MIRROR_CLOUD_FILTER;
7916         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7917         filter_replace.new_filter_type =
7918                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7919         /* Prepare the buffer, 2 entries */
7920         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7921         filter_replace_buf.data[0] |=
7922                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7923         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7924         filter_replace_buf.data[4] |=
7925                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7926
7927         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7928                                                &filter_replace_buf);
7929         if (!status && (filter_replace.old_filter_type !=
7930                         filter_replace.new_filter_type))
7931                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7932                             " original: 0x%x, new: 0x%x",
7933                             dev->device->name,
7934                             filter_replace.old_filter_type,
7935                             filter_replace.new_filter_type);
7936
7937         return status;
7938 }
7939
7940 static enum i40e_status_code
7941 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7942 {
7943         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7944         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7945         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7946         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7947         enum i40e_status_code status = I40E_SUCCESS;
7948
7949         if (pf->support_multi_driver) {
7950                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7951                 return I40E_NOT_SUPPORTED;
7952         }
7953
7954         /* For GTP-C */
7955         memset(&filter_replace, 0,
7956                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7957         memset(&filter_replace_buf, 0,
7958                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7959         /* create L1 filter */
7960         filter_replace.old_filter_type =
7961                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7962         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7963         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7964                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7965         /* Prepare the buffer, 2 entries */
7966         filter_replace_buf.data[0] =
7967                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7968         filter_replace_buf.data[0] |=
7969                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7970         filter_replace_buf.data[2] = 0xFF;
7971         filter_replace_buf.data[3] = 0xFF;
7972         filter_replace_buf.data[4] =
7973                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7974         filter_replace_buf.data[4] |=
7975                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7976         filter_replace_buf.data[6] = 0xFF;
7977         filter_replace_buf.data[7] = 0xFF;
7978         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7979                                                &filter_replace_buf);
7980         if (status < 0)
7981                 return status;
7982         if (filter_replace.old_filter_type !=
7983             filter_replace.new_filter_type)
7984                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7985                             " original: 0x%x, new: 0x%x",
7986                             dev->device->name,
7987                             filter_replace.old_filter_type,
7988                             filter_replace.new_filter_type);
7989
7990         /* for GTP-U */
7991         memset(&filter_replace, 0,
7992                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7993         memset(&filter_replace_buf, 0,
7994                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7995         /* create L1 filter */
7996         filter_replace.old_filter_type =
7997                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7998         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7999         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8000                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8001         /* Prepare the buffer, 2 entries */
8002         filter_replace_buf.data[0] =
8003                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8004         filter_replace_buf.data[0] |=
8005                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8006         filter_replace_buf.data[2] = 0xFF;
8007         filter_replace_buf.data[3] = 0xFF;
8008         filter_replace_buf.data[4] =
8009                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8010         filter_replace_buf.data[4] |=
8011                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8012         filter_replace_buf.data[6] = 0xFF;
8013         filter_replace_buf.data[7] = 0xFF;
8014
8015         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8016                                                &filter_replace_buf);
8017         if (!status && (filter_replace.old_filter_type !=
8018                         filter_replace.new_filter_type))
8019                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8020                             " original: 0x%x, new: 0x%x",
8021                             dev->device->name,
8022                             filter_replace.old_filter_type,
8023                             filter_replace.new_filter_type);
8024
8025         return status;
8026 }
8027
8028 static enum
8029 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8030 {
8031         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8032         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8033         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8034         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8035         enum i40e_status_code status = I40E_SUCCESS;
8036
8037         if (pf->support_multi_driver) {
8038                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8039                 return I40E_NOT_SUPPORTED;
8040         }
8041
8042         /* for GTP-C */
8043         memset(&filter_replace, 0,
8044                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8045         memset(&filter_replace_buf, 0,
8046                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8047         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8048         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8049         filter_replace.new_filter_type =
8050                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8051         /* Prepare the buffer, 2 entries */
8052         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8053         filter_replace_buf.data[0] |=
8054                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8055         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8056         filter_replace_buf.data[4] |=
8057                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8058         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8059                                                &filter_replace_buf);
8060         if (status < 0)
8061                 return status;
8062         if (filter_replace.old_filter_type !=
8063             filter_replace.new_filter_type)
8064                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8065                             " original: 0x%x, new: 0x%x",
8066                             dev->device->name,
8067                             filter_replace.old_filter_type,
8068                             filter_replace.new_filter_type);
8069
8070         /* for GTP-U */
8071         memset(&filter_replace, 0,
8072                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8073         memset(&filter_replace_buf, 0,
8074                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8075         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8076         filter_replace.old_filter_type =
8077                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8078         filter_replace.new_filter_type =
8079                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8080         /* Prepare the buffer, 2 entries */
8081         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8082         filter_replace_buf.data[0] |=
8083                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8084         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8085         filter_replace_buf.data[4] |=
8086                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8087
8088         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8089                                                &filter_replace_buf);
8090         if (!status && (filter_replace.old_filter_type !=
8091                         filter_replace.new_filter_type))
8092                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8093                             " original: 0x%x, new: 0x%x",
8094                             dev->device->name,
8095                             filter_replace.old_filter_type,
8096                             filter_replace.new_filter_type);
8097
8098         return status;
8099 }
8100
8101 int
8102 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8103                       struct i40e_tunnel_filter_conf *tunnel_filter,
8104                       uint8_t add)
8105 {
8106         uint16_t ip_type;
8107         uint32_t ipv4_addr, ipv4_addr_le;
8108         uint8_t i, tun_type = 0;
8109         /* internal variable to convert ipv6 byte order */
8110         uint32_t convert_ipv6[4];
8111         int val, ret = 0;
8112         struct i40e_pf_vf *vf = NULL;
8113         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8114         struct i40e_vsi *vsi;
8115         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8116         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8117         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8118         struct i40e_tunnel_filter *tunnel, *node;
8119         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8120         uint32_t teid_le;
8121         bool big_buffer = 0;
8122
8123         cld_filter = rte_zmalloc("tunnel_filter",
8124                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8125                          0);
8126
8127         if (cld_filter == NULL) {
8128                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8129                 return -ENOMEM;
8130         }
8131         pfilter = cld_filter;
8132
8133         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8134                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8135         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8136                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8137
8138         pfilter->element.inner_vlan =
8139                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8140         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8141                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8142                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8143                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8144                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8145                                 &ipv4_addr_le,
8146                                 sizeof(pfilter->element.ipaddr.v4.data));
8147         } else {
8148                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8149                 for (i = 0; i < 4; i++) {
8150                         convert_ipv6[i] =
8151                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8152                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8153                 }
8154                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8155                            &convert_ipv6,
8156                            sizeof(pfilter->element.ipaddr.v6.data));
8157         }
8158
8159         /* check tunneled type */
8160         switch (tunnel_filter->tunnel_type) {
8161         case I40E_TUNNEL_TYPE_VXLAN:
8162                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8163                 break;
8164         case I40E_TUNNEL_TYPE_NVGRE:
8165                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8166                 break;
8167         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8168                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8169                 break;
8170         case I40E_TUNNEL_TYPE_MPLSoUDP:
8171                 if (!pf->mpls_replace_flag) {
8172                         i40e_replace_mpls_l1_filter(pf);
8173                         i40e_replace_mpls_cloud_filter(pf);
8174                         pf->mpls_replace_flag = 1;
8175                 }
8176                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8177                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8178                         teid_le >> 4;
8179                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8180                         (teid_le & 0xF) << 12;
8181                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8182                         0x40;
8183                 big_buffer = 1;
8184                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8185                 break;
8186         case I40E_TUNNEL_TYPE_MPLSoGRE:
8187                 if (!pf->mpls_replace_flag) {
8188                         i40e_replace_mpls_l1_filter(pf);
8189                         i40e_replace_mpls_cloud_filter(pf);
8190                         pf->mpls_replace_flag = 1;
8191                 }
8192                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8193                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8194                         teid_le >> 4;
8195                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8196                         (teid_le & 0xF) << 12;
8197                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8198                         0x0;
8199                 big_buffer = 1;
8200                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8201                 break;
8202         case I40E_TUNNEL_TYPE_GTPC:
8203                 if (!pf->gtp_replace_flag) {
8204                         i40e_replace_gtp_l1_filter(pf);
8205                         i40e_replace_gtp_cloud_filter(pf);
8206                         pf->gtp_replace_flag = 1;
8207                 }
8208                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8209                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8210                         (teid_le >> 16) & 0xFFFF;
8211                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8212                         teid_le & 0xFFFF;
8213                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8214                         0x0;
8215                 big_buffer = 1;
8216                 break;
8217         case I40E_TUNNEL_TYPE_GTPU:
8218                 if (!pf->gtp_replace_flag) {
8219                         i40e_replace_gtp_l1_filter(pf);
8220                         i40e_replace_gtp_cloud_filter(pf);
8221                         pf->gtp_replace_flag = 1;
8222                 }
8223                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8224                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8225                         (teid_le >> 16) & 0xFFFF;
8226                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8227                         teid_le & 0xFFFF;
8228                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8229                         0x0;
8230                 big_buffer = 1;
8231                 break;
8232         case I40E_TUNNEL_TYPE_QINQ:
8233                 if (!pf->qinq_replace_flag) {
8234                         ret = i40e_cloud_filter_qinq_create(pf);
8235                         if (ret < 0)
8236                                 PMD_DRV_LOG(DEBUG,
8237                                             "QinQ tunnel filter already created.");
8238                         pf->qinq_replace_flag = 1;
8239                 }
8240                 /*      Add in the General fields the values of
8241                  *      the Outer and Inner VLAN
8242                  *      Big Buffer should be set, see changes in
8243                  *      i40e_aq_add_cloud_filters
8244                  */
8245                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8246                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8247                 big_buffer = 1;
8248                 break;
8249         default:
8250                 /* Other tunnel types is not supported. */
8251                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8252                 rte_free(cld_filter);
8253                 return -EINVAL;
8254         }
8255
8256         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8257                 pfilter->element.flags =
8258                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8259         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8260                 pfilter->element.flags =
8261                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8262         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8263                 pfilter->element.flags =
8264                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8265         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8266                 pfilter->element.flags =
8267                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8268         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8269                 pfilter->element.flags |=
8270                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8271         else {
8272                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8273                                                 &pfilter->element.flags);
8274                 if (val < 0) {
8275                         rte_free(cld_filter);
8276                         return -EINVAL;
8277                 }
8278         }
8279
8280         pfilter->element.flags |= rte_cpu_to_le_16(
8281                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8282                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8283         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8284         pfilter->element.queue_number =
8285                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8286
8287         if (!tunnel_filter->is_to_vf)
8288                 vsi = pf->main_vsi;
8289         else {
8290                 if (tunnel_filter->vf_id >= pf->vf_num) {
8291                         PMD_DRV_LOG(ERR, "Invalid argument.");
8292                         rte_free(cld_filter);
8293                         return -EINVAL;
8294                 }
8295                 vf = &pf->vfs[tunnel_filter->vf_id];
8296                 vsi = vf->vsi;
8297         }
8298
8299         /* Check if there is the filter in SW list */
8300         memset(&check_filter, 0, sizeof(check_filter));
8301         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8302         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8303         check_filter.vf_id = tunnel_filter->vf_id;
8304         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8305         if (add && node) {
8306                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8307                 rte_free(cld_filter);
8308                 return -EINVAL;
8309         }
8310
8311         if (!add && !node) {
8312                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8313                 rte_free(cld_filter);
8314                 return -EINVAL;
8315         }
8316
8317         if (add) {
8318                 if (big_buffer)
8319                         ret = i40e_aq_add_cloud_filters_bb(hw,
8320                                                    vsi->seid, cld_filter, 1);
8321                 else
8322                         ret = i40e_aq_add_cloud_filters(hw,
8323                                         vsi->seid, &cld_filter->element, 1);
8324                 if (ret < 0) {
8325                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8326                         rte_free(cld_filter);
8327                         return -ENOTSUP;
8328                 }
8329                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8330                 if (tunnel == NULL) {
8331                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8332                         rte_free(cld_filter);
8333                         return -ENOMEM;
8334                 }
8335
8336                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8337                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8338                 if (ret < 0)
8339                         rte_free(tunnel);
8340         } else {
8341                 if (big_buffer)
8342                         ret = i40e_aq_rem_cloud_filters_bb(
8343                                 hw, vsi->seid, cld_filter, 1);
8344                 else
8345                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8346                                                 &cld_filter->element, 1);
8347                 if (ret < 0) {
8348                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8349                         rte_free(cld_filter);
8350                         return -ENOTSUP;
8351                 }
8352                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8353         }
8354
8355         rte_free(cld_filter);
8356         return ret;
8357 }
8358
8359 static int
8360 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8361 {
8362         uint8_t i;
8363
8364         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8365                 if (pf->vxlan_ports[i] == port)
8366                         return i;
8367         }
8368
8369         return -1;
8370 }
8371
8372 static int
8373 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8374 {
8375         int  idx, ret;
8376         uint8_t filter_idx;
8377         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8378
8379         idx = i40e_get_vxlan_port_idx(pf, port);
8380
8381         /* Check if port already exists */
8382         if (idx >= 0) {
8383                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8384                 return -EINVAL;
8385         }
8386
8387         /* Now check if there is space to add the new port */
8388         idx = i40e_get_vxlan_port_idx(pf, 0);
8389         if (idx < 0) {
8390                 PMD_DRV_LOG(ERR,
8391                         "Maximum number of UDP ports reached, not adding port %d",
8392                         port);
8393                 return -ENOSPC;
8394         }
8395
8396         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8397                                         &filter_idx, NULL);
8398         if (ret < 0) {
8399                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8400                 return -1;
8401         }
8402
8403         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8404                          port,  filter_idx);
8405
8406         /* New port: add it and mark its index in the bitmap */
8407         pf->vxlan_ports[idx] = port;
8408         pf->vxlan_bitmap |= (1 << idx);
8409
8410         if (!(pf->flags & I40E_FLAG_VXLAN))
8411                 pf->flags |= I40E_FLAG_VXLAN;
8412
8413         return 0;
8414 }
8415
8416 static int
8417 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8418 {
8419         int idx;
8420         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8421
8422         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8423                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8424                 return -EINVAL;
8425         }
8426
8427         idx = i40e_get_vxlan_port_idx(pf, port);
8428
8429         if (idx < 0) {
8430                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8431                 return -EINVAL;
8432         }
8433
8434         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8435                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8436                 return -1;
8437         }
8438
8439         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8440                         port, idx);
8441
8442         pf->vxlan_ports[idx] = 0;
8443         pf->vxlan_bitmap &= ~(1 << idx);
8444
8445         if (!pf->vxlan_bitmap)
8446                 pf->flags &= ~I40E_FLAG_VXLAN;
8447
8448         return 0;
8449 }
8450
8451 /* Add UDP tunneling port */
8452 static int
8453 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8454                              struct rte_eth_udp_tunnel *udp_tunnel)
8455 {
8456         int ret = 0;
8457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8458
8459         if (udp_tunnel == NULL)
8460                 return -EINVAL;
8461
8462         switch (udp_tunnel->prot_type) {
8463         case RTE_TUNNEL_TYPE_VXLAN:
8464                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8465                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8466                 break;
8467         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8468                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8469                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8470                 break;
8471         case RTE_TUNNEL_TYPE_GENEVE:
8472         case RTE_TUNNEL_TYPE_TEREDO:
8473                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8474                 ret = -1;
8475                 break;
8476
8477         default:
8478                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8479                 ret = -1;
8480                 break;
8481         }
8482
8483         return ret;
8484 }
8485
8486 /* Remove UDP tunneling port */
8487 static int
8488 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8489                              struct rte_eth_udp_tunnel *udp_tunnel)
8490 {
8491         int ret = 0;
8492         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8493
8494         if (udp_tunnel == NULL)
8495                 return -EINVAL;
8496
8497         switch (udp_tunnel->prot_type) {
8498         case RTE_TUNNEL_TYPE_VXLAN:
8499         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8500                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8501                 break;
8502         case RTE_TUNNEL_TYPE_GENEVE:
8503         case RTE_TUNNEL_TYPE_TEREDO:
8504                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8505                 ret = -1;
8506                 break;
8507         default:
8508                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8509                 ret = -1;
8510                 break;
8511         }
8512
8513         return ret;
8514 }
8515
8516 /* Calculate the maximum number of contiguous PF queues that are configured */
8517 static int
8518 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8519 {
8520         struct rte_eth_dev_data *data = pf->dev_data;
8521         int i, num;
8522         struct i40e_rx_queue *rxq;
8523
8524         num = 0;
8525         for (i = 0; i < pf->lan_nb_qps; i++) {
8526                 rxq = data->rx_queues[i];
8527                 if (rxq && rxq->q_set)
8528                         num++;
8529                 else
8530                         break;
8531         }
8532
8533         return num;
8534 }
8535
8536 /* Configure RSS */
8537 static int
8538 i40e_pf_config_rss(struct i40e_pf *pf)
8539 {
8540         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8541         struct rte_eth_rss_conf rss_conf;
8542         uint32_t i, lut = 0;
8543         uint16_t j, num;
8544
8545         /*
8546          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8547          * It's necessary to calculate the actual PF queues that are configured.
8548          */
8549         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8550                 num = i40e_pf_calc_configured_queues_num(pf);
8551         else
8552                 num = pf->dev_data->nb_rx_queues;
8553
8554         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8555         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8556                         num);
8557
8558         if (num == 0) {
8559                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8560                 return -ENOTSUP;
8561         }
8562
8563         if (pf->adapter->rss_reta_updated == 0) {
8564                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8565                         if (j == num)
8566                                 j = 0;
8567                         lut = (lut << 8) | (j & ((0x1 <<
8568                                 hw->func_caps.rss_table_entry_width) - 1));
8569                         if ((i & 3) == 3)
8570                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8571                                                rte_bswap32(lut));
8572                 }
8573         }
8574
8575         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8576         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8577                 i40e_pf_disable_rss(pf);
8578                 return 0;
8579         }
8580         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8581                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8582                 /* Random default keys */
8583                 static uint32_t rss_key_default[] = {0x6b793944,
8584                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8585                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8586                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8587
8588                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8589                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8590                                                         sizeof(uint32_t);
8591         }
8592
8593         return i40e_hw_rss_hash_set(pf, &rss_conf);
8594 }
8595
8596 static int
8597 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8598                                struct rte_eth_tunnel_filter_conf *filter)
8599 {
8600         if (pf == NULL || filter == NULL) {
8601                 PMD_DRV_LOG(ERR, "Invalid parameter");
8602                 return -EINVAL;
8603         }
8604
8605         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8606                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8607                 return -EINVAL;
8608         }
8609
8610         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8611                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8612                 return -EINVAL;
8613         }
8614
8615         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8616                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8617                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8618                 return -EINVAL;
8619         }
8620
8621         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8622                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8623                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8624                 return -EINVAL;
8625         }
8626
8627         return 0;
8628 }
8629
8630 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8631 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8632 static int
8633 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8634 {
8635         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8636         uint32_t val, reg;
8637         int ret = -EINVAL;
8638
8639         if (pf->support_multi_driver) {
8640                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8641                 return -ENOTSUP;
8642         }
8643
8644         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8645         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8646
8647         if (len == 3) {
8648                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8649         } else if (len == 4) {
8650                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8651         } else {
8652                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8653                 return ret;
8654         }
8655
8656         if (reg != val) {
8657                 ret = i40e_aq_debug_write_global_register(hw,
8658                                                    I40E_GL_PRS_FVBM(2),
8659                                                    reg, NULL);
8660                 if (ret != 0)
8661                         return ret;
8662                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8663                             "with value 0x%08x",
8664                             I40E_GL_PRS_FVBM(2), reg);
8665         } else {
8666                 ret = 0;
8667         }
8668         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8669                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8670
8671         return ret;
8672 }
8673
8674 static int
8675 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8676 {
8677         int ret = -EINVAL;
8678
8679         if (!hw || !cfg)
8680                 return -EINVAL;
8681
8682         switch (cfg->cfg_type) {
8683         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8684                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8685                 break;
8686         default:
8687                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8688                 break;
8689         }
8690
8691         return ret;
8692 }
8693
8694 static int
8695 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8696                                enum rte_filter_op filter_op,
8697                                void *arg)
8698 {
8699         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8700         int ret = I40E_ERR_PARAM;
8701
8702         switch (filter_op) {
8703         case RTE_ETH_FILTER_SET:
8704                 ret = i40e_dev_global_config_set(hw,
8705                         (struct rte_eth_global_cfg *)arg);
8706                 break;
8707         default:
8708                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8709                 break;
8710         }
8711
8712         return ret;
8713 }
8714
8715 static int
8716 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8717                           enum rte_filter_op filter_op,
8718                           void *arg)
8719 {
8720         struct rte_eth_tunnel_filter_conf *filter;
8721         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8722         int ret = I40E_SUCCESS;
8723
8724         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8725
8726         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8727                 return I40E_ERR_PARAM;
8728
8729         switch (filter_op) {
8730         case RTE_ETH_FILTER_NOP:
8731                 if (!(pf->flags & I40E_FLAG_VXLAN))
8732                         ret = I40E_NOT_SUPPORTED;
8733                 break;
8734         case RTE_ETH_FILTER_ADD:
8735                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8736                 break;
8737         case RTE_ETH_FILTER_DELETE:
8738                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8739                 break;
8740         default:
8741                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8742                 ret = I40E_ERR_PARAM;
8743                 break;
8744         }
8745
8746         return ret;
8747 }
8748
8749 static int
8750 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8751 {
8752         int ret = 0;
8753         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8754
8755         /* RSS setup */
8756         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8757                 ret = i40e_pf_config_rss(pf);
8758         else
8759                 i40e_pf_disable_rss(pf);
8760
8761         return ret;
8762 }
8763
8764 /* Get the symmetric hash enable configurations per port */
8765 static void
8766 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8767 {
8768         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8769
8770         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8771 }
8772
8773 /* Set the symmetric hash enable configurations per port */
8774 static void
8775 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8776 {
8777         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8778
8779         if (enable > 0) {
8780                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8781                         PMD_DRV_LOG(INFO,
8782                                 "Symmetric hash has already been enabled");
8783                         return;
8784                 }
8785                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8786         } else {
8787                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8788                         PMD_DRV_LOG(INFO,
8789                                 "Symmetric hash has already been disabled");
8790                         return;
8791                 }
8792                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8793         }
8794         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8795         I40E_WRITE_FLUSH(hw);
8796 }
8797
8798 /*
8799  * Get global configurations of hash function type and symmetric hash enable
8800  * per flow type (pctype). Note that global configuration means it affects all
8801  * the ports on the same NIC.
8802  */
8803 static int
8804 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8805                                    struct rte_eth_hash_global_conf *g_cfg)
8806 {
8807         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8808         uint32_t reg;
8809         uint16_t i, j;
8810
8811         memset(g_cfg, 0, sizeof(*g_cfg));
8812         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8813         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8814                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8815         else
8816                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8817         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8818                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8819
8820         /*
8821          * As i40e supports less than 64 flow types, only first 64 bits need to
8822          * be checked.
8823          */
8824         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8825                 g_cfg->valid_bit_mask[i] = 0ULL;
8826                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8827         }
8828
8829         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8830
8831         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8832                 if (!adapter->pctypes_tbl[i])
8833                         continue;
8834                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8835                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8836                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8837                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8838                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8839                                         g_cfg->sym_hash_enable_mask[0] |=
8840                                                                 (1ULL << i);
8841                                 }
8842                         }
8843                 }
8844         }
8845
8846         return 0;
8847 }
8848
8849 static int
8850 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8851                               const struct rte_eth_hash_global_conf *g_cfg)
8852 {
8853         uint32_t i;
8854         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8855
8856         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8857                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8858                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8859                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8860                                                 g_cfg->hash_func);
8861                 return -EINVAL;
8862         }
8863
8864         /*
8865          * As i40e supports less than 64 flow types, only first 64 bits need to
8866          * be checked.
8867          */
8868         mask0 = g_cfg->valid_bit_mask[0];
8869         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8870                 if (i == 0) {
8871                         /* Check if any unsupported flow type configured */
8872                         if ((mask0 | i40e_mask) ^ i40e_mask)
8873                                 goto mask_err;
8874                 } else {
8875                         if (g_cfg->valid_bit_mask[i])
8876                                 goto mask_err;
8877                 }
8878         }
8879
8880         return 0;
8881
8882 mask_err:
8883         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8884
8885         return -EINVAL;
8886 }
8887
8888 /*
8889  * Set global configurations of hash function type and symmetric hash enable
8890  * per flow type (pctype). Note any modifying global configuration will affect
8891  * all the ports on the same NIC.
8892  */
8893 static int
8894 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8895                                    struct rte_eth_hash_global_conf *g_cfg)
8896 {
8897         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8898         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8899         int ret;
8900         uint16_t i, j;
8901         uint32_t reg;
8902         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8903
8904         if (pf->support_multi_driver) {
8905                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8906                 return -ENOTSUP;
8907         }
8908
8909         /* Check the input parameters */
8910         ret = i40e_hash_global_config_check(adapter, g_cfg);
8911         if (ret < 0)
8912                 return ret;
8913
8914         /*
8915          * As i40e supports less than 64 flow types, only first 64 bits need to
8916          * be configured.
8917          */
8918         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8919                 if (mask0 & (1UL << i)) {
8920                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8921                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8922
8923                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8924                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8925                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8926                                         i40e_write_global_rx_ctl(hw,
8927                                                           I40E_GLQF_HSYM(j),
8928                                                           reg);
8929                         }
8930                 }
8931         }
8932
8933         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8934         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8935                 /* Toeplitz */
8936                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8937                         PMD_DRV_LOG(DEBUG,
8938                                 "Hash function already set to Toeplitz");
8939                         goto out;
8940                 }
8941                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8942         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8943                 /* Simple XOR */
8944                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8945                         PMD_DRV_LOG(DEBUG,
8946                                 "Hash function already set to Simple XOR");
8947                         goto out;
8948                 }
8949                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8950         } else
8951                 /* Use the default, and keep it as it is */
8952                 goto out;
8953
8954         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8955
8956 out:
8957         I40E_WRITE_FLUSH(hw);
8958
8959         return 0;
8960 }
8961
8962 /**
8963  * Valid input sets for hash and flow director filters per PCTYPE
8964  */
8965 static uint64_t
8966 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8967                 enum rte_filter_type filter)
8968 {
8969         uint64_t valid;
8970
8971         static const uint64_t valid_hash_inset_table[] = {
8972                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8973                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8974                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8975                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8976                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8977                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8978                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8979                         I40E_INSET_FLEX_PAYLOAD,
8980                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8981                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8982                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8983                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8984                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8985                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8986                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8987                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8988                         I40E_INSET_FLEX_PAYLOAD,
8989                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8990                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8991                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8992                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8993                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8994                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8995                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8996                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8997                         I40E_INSET_FLEX_PAYLOAD,
8998                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8999                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9000                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9001                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9002                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9003                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9004                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9005                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9006                         I40E_INSET_FLEX_PAYLOAD,
9007                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9008                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9009                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9010                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9011                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9012                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9013                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9014                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9015                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9016                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9017                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9018                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9019                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9020                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9021                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9022                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9023                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9024                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9025                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9026                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9027                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9028                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9029                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9030                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9031                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9032                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9033                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9034                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9035                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9036                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9037                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9038                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9039                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9040                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9041                         I40E_INSET_FLEX_PAYLOAD,
9042                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9043                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9044                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9045                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9046                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9047                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9048                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9049                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9050                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9051                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9052                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9053                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9054                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9055                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9056                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9057                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9058                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9059                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9060                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9061                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9062                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9063                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9064                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9065                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9066                         I40E_INSET_FLEX_PAYLOAD,
9067                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9068                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9069                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9070                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9071                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9072                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9073                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9074                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9075                         I40E_INSET_FLEX_PAYLOAD,
9076                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9077                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9078                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9079                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9080                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9081                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9082                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9083                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9084                         I40E_INSET_FLEX_PAYLOAD,
9085                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9086                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9087                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9088                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9089                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9090                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9091                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9092                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9093                         I40E_INSET_FLEX_PAYLOAD,
9094                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9095                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9096                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9097                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9098                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9099                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9100                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9101                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9102                         I40E_INSET_FLEX_PAYLOAD,
9103                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9104                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9105                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9106                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9107                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9108                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9109                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9110                         I40E_INSET_FLEX_PAYLOAD,
9111                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9112                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9113                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9114                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9115                         I40E_INSET_FLEX_PAYLOAD,
9116         };
9117
9118         /**
9119          * Flow director supports only fields defined in
9120          * union rte_eth_fdir_flow.
9121          */
9122         static const uint64_t valid_fdir_inset_table[] = {
9123                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9124                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9125                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9126                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9127                 I40E_INSET_IPV4_TTL,
9128                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9129                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9130                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9131                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9132                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9133                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9134                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9135                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9136                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9137                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9138                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9139                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9140                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9141                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9142                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9143                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9144                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9145                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9146                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9147                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9148                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9149                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9150                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9151                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9152                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9153                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9154                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9155                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9156                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9157                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9158                 I40E_INSET_SCTP_VT,
9159                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9160                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9161                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9162                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9163                 I40E_INSET_IPV4_TTL,
9164                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9165                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9166                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9167                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9168                 I40E_INSET_IPV6_HOP_LIMIT,
9169                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9170                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9171                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9172                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9173                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9174                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9175                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9176                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9177                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9178                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9179                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9180                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9181                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9182                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9183                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9184                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9185                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9186                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9187                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9188                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9189                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9190                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9191                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9192                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9193                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9194                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9195                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9196                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9197                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9198                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9199                 I40E_INSET_SCTP_VT,
9200                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9201                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9202                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9203                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9204                 I40E_INSET_IPV6_HOP_LIMIT,
9205                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9206                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9207                 I40E_INSET_LAST_ETHER_TYPE,
9208         };
9209
9210         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9211                 return 0;
9212         if (filter == RTE_ETH_FILTER_HASH)
9213                 valid = valid_hash_inset_table[pctype];
9214         else
9215                 valid = valid_fdir_inset_table[pctype];
9216
9217         return valid;
9218 }
9219
9220 /**
9221  * Validate if the input set is allowed for a specific PCTYPE
9222  */
9223 int
9224 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9225                 enum rte_filter_type filter, uint64_t inset)
9226 {
9227         uint64_t valid;
9228
9229         valid = i40e_get_valid_input_set(pctype, filter);
9230         if (inset & (~valid))
9231                 return -EINVAL;
9232
9233         return 0;
9234 }
9235
9236 /* default input set fields combination per pctype */
9237 uint64_t
9238 i40e_get_default_input_set(uint16_t pctype)
9239 {
9240         static const uint64_t default_inset_table[] = {
9241                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9242                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9243                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9244                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9245                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9246                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9247                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9248                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9249                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9250                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9251                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9252                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9253                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9254                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9255                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9256                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9257                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9258                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9259                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9260                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9261                         I40E_INSET_SCTP_VT,
9262                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9263                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9264                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9265                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9266                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9267                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9268                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9269                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9270                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9271                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9272                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9273                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9274                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9275                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9276                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9277                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9278                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9279                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9280                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9281                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9282                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9283                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9284                         I40E_INSET_SCTP_VT,
9285                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9286                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9287                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9288                         I40E_INSET_LAST_ETHER_TYPE,
9289         };
9290
9291         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9292                 return 0;
9293
9294         return default_inset_table[pctype];
9295 }
9296
9297 /**
9298  * Parse the input set from index to logical bit masks
9299  */
9300 static int
9301 i40e_parse_input_set(uint64_t *inset,
9302                      enum i40e_filter_pctype pctype,
9303                      enum rte_eth_input_set_field *field,
9304                      uint16_t size)
9305 {
9306         uint16_t i, j;
9307         int ret = -EINVAL;
9308
9309         static const struct {
9310                 enum rte_eth_input_set_field field;
9311                 uint64_t inset;
9312         } inset_convert_table[] = {
9313                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9314                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9315                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9316                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9317                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9318                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9319                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9320                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9321                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9322                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9323                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9324                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9325                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9326                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9327                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9328                         I40E_INSET_IPV6_NEXT_HDR},
9329                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9330                         I40E_INSET_IPV6_HOP_LIMIT},
9331                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9332                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9333                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9334                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9335                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9336                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9337                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9338                         I40E_INSET_SCTP_VT},
9339                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9340                         I40E_INSET_TUNNEL_DMAC},
9341                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9342                         I40E_INSET_VLAN_TUNNEL},
9343                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9344                         I40E_INSET_TUNNEL_ID},
9345                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9346                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9347                         I40E_INSET_FLEX_PAYLOAD_W1},
9348                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9349                         I40E_INSET_FLEX_PAYLOAD_W2},
9350                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9351                         I40E_INSET_FLEX_PAYLOAD_W3},
9352                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9353                         I40E_INSET_FLEX_PAYLOAD_W4},
9354                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9355                         I40E_INSET_FLEX_PAYLOAD_W5},
9356                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9357                         I40E_INSET_FLEX_PAYLOAD_W6},
9358                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9359                         I40E_INSET_FLEX_PAYLOAD_W7},
9360                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9361                         I40E_INSET_FLEX_PAYLOAD_W8},
9362         };
9363
9364         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9365                 return ret;
9366
9367         /* Only one item allowed for default or all */
9368         if (size == 1) {
9369                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9370                         *inset = i40e_get_default_input_set(pctype);
9371                         return 0;
9372                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9373                         *inset = I40E_INSET_NONE;
9374                         return 0;
9375                 }
9376         }
9377
9378         for (i = 0, *inset = 0; i < size; i++) {
9379                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9380                         if (field[i] == inset_convert_table[j].field) {
9381                                 *inset |= inset_convert_table[j].inset;
9382                                 break;
9383                         }
9384                 }
9385
9386                 /* It contains unsupported input set, return immediately */
9387                 if (j == RTE_DIM(inset_convert_table))
9388                         return ret;
9389         }
9390
9391         return 0;
9392 }
9393
9394 /**
9395  * Translate the input set from bit masks to register aware bit masks
9396  * and vice versa
9397  */
9398 uint64_t
9399 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9400 {
9401         uint64_t val = 0;
9402         uint16_t i;
9403
9404         struct inset_map {
9405                 uint64_t inset;
9406                 uint64_t inset_reg;
9407         };
9408
9409         static const struct inset_map inset_map_common[] = {
9410                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9411                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9412                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9413                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9414                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9415                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9416                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9417                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9418                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9419                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9420                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9421                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9422                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9423                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9424                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9425                 {I40E_INSET_TUNNEL_DMAC,
9426                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9427                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9428                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9429                 {I40E_INSET_TUNNEL_SRC_PORT,
9430                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9431                 {I40E_INSET_TUNNEL_DST_PORT,
9432                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9433                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9434                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9435                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9436                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9437                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9438                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9439                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9440                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9441                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9442         };
9443
9444     /* some different registers map in x722*/
9445         static const struct inset_map inset_map_diff_x722[] = {
9446                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9447                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9448                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9449                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9450         };
9451
9452         static const struct inset_map inset_map_diff_not_x722[] = {
9453                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9454                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9455                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9456                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9457         };
9458
9459         if (input == 0)
9460                 return val;
9461
9462         /* Translate input set to register aware inset */
9463         if (type == I40E_MAC_X722) {
9464                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9465                         if (input & inset_map_diff_x722[i].inset)
9466                                 val |= inset_map_diff_x722[i].inset_reg;
9467                 }
9468         } else {
9469                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9470                         if (input & inset_map_diff_not_x722[i].inset)
9471                                 val |= inset_map_diff_not_x722[i].inset_reg;
9472                 }
9473         }
9474
9475         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9476                 if (input & inset_map_common[i].inset)
9477                         val |= inset_map_common[i].inset_reg;
9478         }
9479
9480         return val;
9481 }
9482
9483 int
9484 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9485 {
9486         uint8_t i, idx = 0;
9487         uint64_t inset_need_mask = inset;
9488
9489         static const struct {
9490                 uint64_t inset;
9491                 uint32_t mask;
9492         } inset_mask_map[] = {
9493                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9494                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9495                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9496                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9497                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9498                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9499                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9500                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9501         };
9502
9503         if (!inset || !mask || !nb_elem)
9504                 return 0;
9505
9506         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9507                 /* Clear the inset bit, if no MASK is required,
9508                  * for example proto + ttl
9509                  */
9510                 if ((inset & inset_mask_map[i].inset) ==
9511                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9512                         inset_need_mask &= ~inset_mask_map[i].inset;
9513                 if (!inset_need_mask)
9514                         return 0;
9515         }
9516         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9517                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9518                     inset_mask_map[i].inset) {
9519                         if (idx >= nb_elem) {
9520                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9521                                 return -EINVAL;
9522                         }
9523                         mask[idx] = inset_mask_map[i].mask;
9524                         idx++;
9525                 }
9526         }
9527
9528         return idx;
9529 }
9530
9531 void
9532 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9533 {
9534         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9535
9536         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9537         if (reg != val)
9538                 i40e_write_rx_ctl(hw, addr, val);
9539         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9540                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9541 }
9542
9543 void
9544 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9545 {
9546         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9547         struct rte_eth_dev *dev;
9548
9549         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9550         if (reg != val) {
9551                 i40e_write_rx_ctl(hw, addr, val);
9552                 PMD_DRV_LOG(WARNING,
9553                             "i40e device %s changed global register [0x%08x]."
9554                             " original: 0x%08x, new: 0x%08x",
9555                             dev->device->name, addr, reg,
9556                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9557         }
9558 }
9559
9560 static void
9561 i40e_filter_input_set_init(struct i40e_pf *pf)
9562 {
9563         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9564         enum i40e_filter_pctype pctype;
9565         uint64_t input_set, inset_reg;
9566         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9567         int num, i;
9568         uint16_t flow_type;
9569
9570         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9571              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9572                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9573
9574                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9575                         continue;
9576
9577                 input_set = i40e_get_default_input_set(pctype);
9578
9579                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9580                                                    I40E_INSET_MASK_NUM_REG);
9581                 if (num < 0)
9582                         return;
9583                 if (pf->support_multi_driver && num > 0) {
9584                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9585                         return;
9586                 }
9587                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9588                                         input_set);
9589
9590                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9591                                       (uint32_t)(inset_reg & UINT32_MAX));
9592                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9593                                      (uint32_t)((inset_reg >>
9594                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9595                 if (!pf->support_multi_driver) {
9596                         i40e_check_write_global_reg(hw,
9597                                             I40E_GLQF_HASH_INSET(0, pctype),
9598                                             (uint32_t)(inset_reg & UINT32_MAX));
9599                         i40e_check_write_global_reg(hw,
9600                                              I40E_GLQF_HASH_INSET(1, pctype),
9601                                              (uint32_t)((inset_reg >>
9602                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9603
9604                         for (i = 0; i < num; i++) {
9605                                 i40e_check_write_global_reg(hw,
9606                                                     I40E_GLQF_FD_MSK(i, pctype),
9607                                                     mask_reg[i]);
9608                                 i40e_check_write_global_reg(hw,
9609                                                   I40E_GLQF_HASH_MSK(i, pctype),
9610                                                   mask_reg[i]);
9611                         }
9612                         /*clear unused mask registers of the pctype */
9613                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9614                                 i40e_check_write_global_reg(hw,
9615                                                     I40E_GLQF_FD_MSK(i, pctype),
9616                                                     0);
9617                                 i40e_check_write_global_reg(hw,
9618                                                   I40E_GLQF_HASH_MSK(i, pctype),
9619                                                   0);
9620                         }
9621                 } else {
9622                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9623                 }
9624                 I40E_WRITE_FLUSH(hw);
9625
9626                 /* store the default input set */
9627                 if (!pf->support_multi_driver)
9628                         pf->hash_input_set[pctype] = input_set;
9629                 pf->fdir.input_set[pctype] = input_set;
9630         }
9631 }
9632
9633 int
9634 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9635                          struct rte_eth_input_set_conf *conf)
9636 {
9637         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9638         enum i40e_filter_pctype pctype;
9639         uint64_t input_set, inset_reg = 0;
9640         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9641         int ret, i, num;
9642
9643         if (!conf) {
9644                 PMD_DRV_LOG(ERR, "Invalid pointer");
9645                 return -EFAULT;
9646         }
9647         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9648             conf->op != RTE_ETH_INPUT_SET_ADD) {
9649                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9650                 return -EINVAL;
9651         }
9652
9653         if (pf->support_multi_driver) {
9654                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9655                 return -ENOTSUP;
9656         }
9657
9658         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9659         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9660                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9661                 return -EINVAL;
9662         }
9663
9664         if (hw->mac.type == I40E_MAC_X722) {
9665                 /* get translated pctype value in fd pctype register */
9666                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9667                         I40E_GLQF_FD_PCTYPES((int)pctype));
9668         }
9669
9670         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9671                                    conf->inset_size);
9672         if (ret) {
9673                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9674                 return -EINVAL;
9675         }
9676
9677         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9678                 /* get inset value in register */
9679                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9680                 inset_reg <<= I40E_32_BIT_WIDTH;
9681                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9682                 input_set |= pf->hash_input_set[pctype];
9683         }
9684         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9685                                            I40E_INSET_MASK_NUM_REG);
9686         if (num < 0)
9687                 return -EINVAL;
9688
9689         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9690
9691         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9692                                     (uint32_t)(inset_reg & UINT32_MAX));
9693         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9694                                     (uint32_t)((inset_reg >>
9695                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9696
9697         for (i = 0; i < num; i++)
9698                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9699                                             mask_reg[i]);
9700         /*clear unused mask registers of the pctype */
9701         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9702                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9703                                             0);
9704         I40E_WRITE_FLUSH(hw);
9705
9706         pf->hash_input_set[pctype] = input_set;
9707         return 0;
9708 }
9709
9710 int
9711 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9712                          struct rte_eth_input_set_conf *conf)
9713 {
9714         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9715         enum i40e_filter_pctype pctype;
9716         uint64_t input_set, inset_reg = 0;
9717         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9718         int ret, i, num;
9719
9720         if (!hw || !conf) {
9721                 PMD_DRV_LOG(ERR, "Invalid pointer");
9722                 return -EFAULT;
9723         }
9724         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9725             conf->op != RTE_ETH_INPUT_SET_ADD) {
9726                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9727                 return -EINVAL;
9728         }
9729
9730         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9731
9732         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9733                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9734                 return -EINVAL;
9735         }
9736
9737         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9738                                    conf->inset_size);
9739         if (ret) {
9740                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9741                 return -EINVAL;
9742         }
9743
9744         /* get inset value in register */
9745         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9746         inset_reg <<= I40E_32_BIT_WIDTH;
9747         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9748
9749         /* Can not change the inset reg for flex payload for fdir,
9750          * it is done by writing I40E_PRTQF_FD_FLXINSET
9751          * in i40e_set_flex_mask_on_pctype.
9752          */
9753         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9754                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9755         else
9756                 input_set |= pf->fdir.input_set[pctype];
9757         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9758                                            I40E_INSET_MASK_NUM_REG);
9759         if (num < 0)
9760                 return -EINVAL;
9761         if (pf->support_multi_driver && num > 0) {
9762                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9763                 return -ENOTSUP;
9764         }
9765
9766         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9767
9768         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9769                               (uint32_t)(inset_reg & UINT32_MAX));
9770         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9771                              (uint32_t)((inset_reg >>
9772                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9773
9774         if (!pf->support_multi_driver) {
9775                 for (i = 0; i < num; i++)
9776                         i40e_check_write_global_reg(hw,
9777                                                     I40E_GLQF_FD_MSK(i, pctype),
9778                                                     mask_reg[i]);
9779                 /*clear unused mask registers of the pctype */
9780                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9781                         i40e_check_write_global_reg(hw,
9782                                                     I40E_GLQF_FD_MSK(i, pctype),
9783                                                     0);
9784         } else {
9785                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9786         }
9787         I40E_WRITE_FLUSH(hw);
9788
9789         pf->fdir.input_set[pctype] = input_set;
9790         return 0;
9791 }
9792
9793 static int
9794 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9795 {
9796         int ret = 0;
9797
9798         if (!hw || !info) {
9799                 PMD_DRV_LOG(ERR, "Invalid pointer");
9800                 return -EFAULT;
9801         }
9802
9803         switch (info->info_type) {
9804         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9805                 i40e_get_symmetric_hash_enable_per_port(hw,
9806                                         &(info->info.enable));
9807                 break;
9808         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9809                 ret = i40e_get_hash_filter_global_config(hw,
9810                                 &(info->info.global_conf));
9811                 break;
9812         default:
9813                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9814                                                         info->info_type);
9815                 ret = -EINVAL;
9816                 break;
9817         }
9818
9819         return ret;
9820 }
9821
9822 static int
9823 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9824 {
9825         int ret = 0;
9826
9827         if (!hw || !info) {
9828                 PMD_DRV_LOG(ERR, "Invalid pointer");
9829                 return -EFAULT;
9830         }
9831
9832         switch (info->info_type) {
9833         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9834                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9835                 break;
9836         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9837                 ret = i40e_set_hash_filter_global_config(hw,
9838                                 &(info->info.global_conf));
9839                 break;
9840         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9841                 ret = i40e_hash_filter_inset_select(hw,
9842                                                &(info->info.input_set_conf));
9843                 break;
9844
9845         default:
9846                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9847                                                         info->info_type);
9848                 ret = -EINVAL;
9849                 break;
9850         }
9851
9852         return ret;
9853 }
9854
9855 /* Operations for hash function */
9856 static int
9857 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9858                       enum rte_filter_op filter_op,
9859                       void *arg)
9860 {
9861         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9862         int ret = 0;
9863
9864         switch (filter_op) {
9865         case RTE_ETH_FILTER_NOP:
9866                 break;
9867         case RTE_ETH_FILTER_GET:
9868                 ret = i40e_hash_filter_get(hw,
9869                         (struct rte_eth_hash_filter_info *)arg);
9870                 break;
9871         case RTE_ETH_FILTER_SET:
9872                 ret = i40e_hash_filter_set(hw,
9873                         (struct rte_eth_hash_filter_info *)arg);
9874                 break;
9875         default:
9876                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9877                                                                 filter_op);
9878                 ret = -ENOTSUP;
9879                 break;
9880         }
9881
9882         return ret;
9883 }
9884
9885 /* Convert ethertype filter structure */
9886 static int
9887 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9888                               struct i40e_ethertype_filter *filter)
9889 {
9890         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9891                 RTE_ETHER_ADDR_LEN);
9892         filter->input.ether_type = input->ether_type;
9893         filter->flags = input->flags;
9894         filter->queue = input->queue;
9895
9896         return 0;
9897 }
9898
9899 /* Check if there exists the ehtertype filter */
9900 struct i40e_ethertype_filter *
9901 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9902                                 const struct i40e_ethertype_filter_input *input)
9903 {
9904         int ret;
9905
9906         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9907         if (ret < 0)
9908                 return NULL;
9909
9910         return ethertype_rule->hash_map[ret];
9911 }
9912
9913 /* Add ethertype filter in SW list */
9914 static int
9915 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9916                                 struct i40e_ethertype_filter *filter)
9917 {
9918         struct i40e_ethertype_rule *rule = &pf->ethertype;
9919         int ret;
9920
9921         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9922         if (ret < 0) {
9923                 PMD_DRV_LOG(ERR,
9924                             "Failed to insert ethertype filter"
9925                             " to hash table %d!",
9926                             ret);
9927                 return ret;
9928         }
9929         rule->hash_map[ret] = filter;
9930
9931         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9932
9933         return 0;
9934 }
9935
9936 /* Delete ethertype filter in SW list */
9937 int
9938 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9939                              struct i40e_ethertype_filter_input *input)
9940 {
9941         struct i40e_ethertype_rule *rule = &pf->ethertype;
9942         struct i40e_ethertype_filter *filter;
9943         int ret;
9944
9945         ret = rte_hash_del_key(rule->hash_table, input);
9946         if (ret < 0) {
9947                 PMD_DRV_LOG(ERR,
9948                             "Failed to delete ethertype filter"
9949                             " to hash table %d!",
9950                             ret);
9951                 return ret;
9952         }
9953         filter = rule->hash_map[ret];
9954         rule->hash_map[ret] = NULL;
9955
9956         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9957         rte_free(filter);
9958
9959         return 0;
9960 }
9961
9962 /*
9963  * Configure ethertype filter, which can director packet by filtering
9964  * with mac address and ether_type or only ether_type
9965  */
9966 int
9967 i40e_ethertype_filter_set(struct i40e_pf *pf,
9968                         struct rte_eth_ethertype_filter *filter,
9969                         bool add)
9970 {
9971         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9972         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9973         struct i40e_ethertype_filter *ethertype_filter, *node;
9974         struct i40e_ethertype_filter check_filter;
9975         struct i40e_control_filter_stats stats;
9976         uint16_t flags = 0;
9977         int ret;
9978
9979         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9980                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9981                 return -EINVAL;
9982         }
9983         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9984                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
9985                 PMD_DRV_LOG(ERR,
9986                         "unsupported ether_type(0x%04x) in control packet filter.",
9987                         filter->ether_type);
9988                 return -EINVAL;
9989         }
9990         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
9991                 PMD_DRV_LOG(WARNING,
9992                         "filter vlan ether_type in first tag is not supported.");
9993
9994         /* Check if there is the filter in SW list */
9995         memset(&check_filter, 0, sizeof(check_filter));
9996         i40e_ethertype_filter_convert(filter, &check_filter);
9997         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9998                                                &check_filter.input);
9999         if (add && node) {
10000                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10001                 return -EINVAL;
10002         }
10003
10004         if (!add && !node) {
10005                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10006                 return -EINVAL;
10007         }
10008
10009         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10010                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10011         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10012                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10013         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10014
10015         memset(&stats, 0, sizeof(stats));
10016         ret = i40e_aq_add_rem_control_packet_filter(hw,
10017                         filter->mac_addr.addr_bytes,
10018                         filter->ether_type, flags,
10019                         pf->main_vsi->seid,
10020                         filter->queue, add, &stats, NULL);
10021
10022         PMD_DRV_LOG(INFO,
10023                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10024                 ret, stats.mac_etype_used, stats.etype_used,
10025                 stats.mac_etype_free, stats.etype_free);
10026         if (ret < 0)
10027                 return -ENOSYS;
10028
10029         /* Add or delete a filter in SW list */
10030         if (add) {
10031                 ethertype_filter = rte_zmalloc("ethertype_filter",
10032                                        sizeof(*ethertype_filter), 0);
10033                 if (ethertype_filter == NULL) {
10034                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10035                         return -ENOMEM;
10036                 }
10037
10038                 rte_memcpy(ethertype_filter, &check_filter,
10039                            sizeof(check_filter));
10040                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10041                 if (ret < 0)
10042                         rte_free(ethertype_filter);
10043         } else {
10044                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10045         }
10046
10047         return ret;
10048 }
10049
10050 /*
10051  * Handle operations for ethertype filter.
10052  */
10053 static int
10054 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10055                                 enum rte_filter_op filter_op,
10056                                 void *arg)
10057 {
10058         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10059         int ret = 0;
10060
10061         if (filter_op == RTE_ETH_FILTER_NOP)
10062                 return ret;
10063
10064         if (arg == NULL) {
10065                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10066                             filter_op);
10067                 return -EINVAL;
10068         }
10069
10070         switch (filter_op) {
10071         case RTE_ETH_FILTER_ADD:
10072                 ret = i40e_ethertype_filter_set(pf,
10073                         (struct rte_eth_ethertype_filter *)arg,
10074                         TRUE);
10075                 break;
10076         case RTE_ETH_FILTER_DELETE:
10077                 ret = i40e_ethertype_filter_set(pf,
10078                         (struct rte_eth_ethertype_filter *)arg,
10079                         FALSE);
10080                 break;
10081         default:
10082                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10083                 ret = -ENOSYS;
10084                 break;
10085         }
10086         return ret;
10087 }
10088
10089 static int
10090 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10091                      enum rte_filter_type filter_type,
10092                      enum rte_filter_op filter_op,
10093                      void *arg)
10094 {
10095         int ret = 0;
10096
10097         if (dev == NULL)
10098                 return -EINVAL;
10099
10100         switch (filter_type) {
10101         case RTE_ETH_FILTER_NONE:
10102                 /* For global configuration */
10103                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10104                 break;
10105         case RTE_ETH_FILTER_HASH:
10106                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10107                 break;
10108         case RTE_ETH_FILTER_MACVLAN:
10109                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10110                 break;
10111         case RTE_ETH_FILTER_ETHERTYPE:
10112                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10113                 break;
10114         case RTE_ETH_FILTER_TUNNEL:
10115                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10116                 break;
10117         case RTE_ETH_FILTER_FDIR:
10118                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10119                 break;
10120         case RTE_ETH_FILTER_GENERIC:
10121                 if (filter_op != RTE_ETH_FILTER_GET)
10122                         return -EINVAL;
10123                 *(const void **)arg = &i40e_flow_ops;
10124                 break;
10125         default:
10126                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10127                                                         filter_type);
10128                 ret = -EINVAL;
10129                 break;
10130         }
10131
10132         return ret;
10133 }
10134
10135 /*
10136  * Check and enable Extended Tag.
10137  * Enabling Extended Tag is important for 40G performance.
10138  */
10139 static void
10140 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10141 {
10142         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10143         uint32_t buf = 0;
10144         int ret;
10145
10146         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10147                                       PCI_DEV_CAP_REG);
10148         if (ret < 0) {
10149                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10150                             PCI_DEV_CAP_REG);
10151                 return;
10152         }
10153         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10154                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10155                 return;
10156         }
10157
10158         buf = 0;
10159         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10160                                       PCI_DEV_CTRL_REG);
10161         if (ret < 0) {
10162                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10163                             PCI_DEV_CTRL_REG);
10164                 return;
10165         }
10166         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10167                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10168                 return;
10169         }
10170         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10171         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10172                                        PCI_DEV_CTRL_REG);
10173         if (ret < 0) {
10174                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10175                             PCI_DEV_CTRL_REG);
10176                 return;
10177         }
10178 }
10179
10180 /*
10181  * As some registers wouldn't be reset unless a global hardware reset,
10182  * hardware initialization is needed to put those registers into an
10183  * expected initial state.
10184  */
10185 static void
10186 i40e_hw_init(struct rte_eth_dev *dev)
10187 {
10188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10189
10190         i40e_enable_extended_tag(dev);
10191
10192         /* clear the PF Queue Filter control register */
10193         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10194
10195         /* Disable symmetric hash per port */
10196         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10197 }
10198
10199 /*
10200  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10201  * however this function will return only one highest pctype index,
10202  * which is not quite correct. This is known problem of i40e driver
10203  * and needs to be fixed later.
10204  */
10205 enum i40e_filter_pctype
10206 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10207 {
10208         int i;
10209         uint64_t pctype_mask;
10210
10211         if (flow_type < I40E_FLOW_TYPE_MAX) {
10212                 pctype_mask = adapter->pctypes_tbl[flow_type];
10213                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10214                         if (pctype_mask & (1ULL << i))
10215                                 return (enum i40e_filter_pctype)i;
10216                 }
10217         }
10218         return I40E_FILTER_PCTYPE_INVALID;
10219 }
10220
10221 uint16_t
10222 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10223                         enum i40e_filter_pctype pctype)
10224 {
10225         uint16_t flowtype;
10226         uint64_t pctype_mask = 1ULL << pctype;
10227
10228         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10229              flowtype++) {
10230                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10231                         return flowtype;
10232         }
10233
10234         return RTE_ETH_FLOW_UNKNOWN;
10235 }
10236
10237 /*
10238  * On X710, performance number is far from the expectation on recent firmware
10239  * versions; on XL710, performance number is also far from the expectation on
10240  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10241  * mode is enabled and port MAC address is equal to the packet destination MAC
10242  * address. The fix for this issue may not be integrated in the following
10243  * firmware version. So the workaround in software driver is needed. It needs
10244  * to modify the initial values of 3 internal only registers for both X710 and
10245  * XL710. Note that the values for X710 or XL710 could be different, and the
10246  * workaround can be removed when it is fixed in firmware in the future.
10247  */
10248
10249 /* For both X710 and XL710 */
10250 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10251 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10252 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10253
10254 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10255 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10256
10257 /* For X722 */
10258 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10259 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10260
10261 /* For X710 */
10262 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10263 /* For XL710 */
10264 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10265 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10266
10267 /*
10268  * GL_SWR_PM_UP_THR:
10269  * The value is not impacted from the link speed, its value is set according
10270  * to the total number of ports for a better pipe-monitor configuration.
10271  */
10272 static bool
10273 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10274 {
10275 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10276                 .device_id = (dev),   \
10277                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10278
10279 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10280                 .device_id = (dev),   \
10281                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10282
10283         static const struct {
10284                 uint16_t device_id;
10285                 uint32_t val;
10286         } swr_pm_table[] = {
10287                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10288                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10289                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10290                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10291
10292                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10293                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10294                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10295                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10296                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10297                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10298                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10299         };
10300         uint32_t i;
10301
10302         if (value == NULL) {
10303                 PMD_DRV_LOG(ERR, "value is NULL");
10304                 return false;
10305         }
10306
10307         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10308                 if (hw->device_id == swr_pm_table[i].device_id) {
10309                         *value = swr_pm_table[i].val;
10310
10311                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10312                                     "value - 0x%08x",
10313                                     hw->device_id, *value);
10314                         return true;
10315                 }
10316         }
10317
10318         return false;
10319 }
10320
10321 static int
10322 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10323 {
10324         enum i40e_status_code status;
10325         struct i40e_aq_get_phy_abilities_resp phy_ab;
10326         int ret = -ENOTSUP;
10327         int retries = 0;
10328
10329         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10330                                               NULL);
10331
10332         while (status) {
10333                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10334                         status);
10335                 retries++;
10336                 rte_delay_us(100000);
10337                 if  (retries < 5)
10338                         status = i40e_aq_get_phy_capabilities(hw, false,
10339                                         true, &phy_ab, NULL);
10340                 else
10341                         return ret;
10342         }
10343         return 0;
10344 }
10345
10346 static void
10347 i40e_configure_registers(struct i40e_hw *hw)
10348 {
10349         static struct {
10350                 uint32_t addr;
10351                 uint64_t val;
10352         } reg_table[] = {
10353                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10354                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10355                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10356         };
10357         uint64_t reg;
10358         uint32_t i;
10359         int ret;
10360
10361         for (i = 0; i < RTE_DIM(reg_table); i++) {
10362                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10363                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10364                                 reg_table[i].val =
10365                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10366                         else /* For X710/XL710/XXV710 */
10367                                 if (hw->aq.fw_maj_ver < 6)
10368                                         reg_table[i].val =
10369                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10370                                 else
10371                                         reg_table[i].val =
10372                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10373                 }
10374
10375                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10376                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10377                                 reg_table[i].val =
10378                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10379                         else /* For X710/XL710/XXV710 */
10380                                 reg_table[i].val =
10381                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10382                 }
10383
10384                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10385                         uint32_t cfg_val;
10386
10387                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10388                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10389                                             "GL_SWR_PM_UP_THR value fixup",
10390                                             hw->device_id);
10391                                 continue;
10392                         }
10393
10394                         reg_table[i].val = cfg_val;
10395                 }
10396
10397                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10398                                                         &reg, NULL);
10399                 if (ret < 0) {
10400                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10401                                                         reg_table[i].addr);
10402                         break;
10403                 }
10404                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10405                                                 reg_table[i].addr, reg);
10406                 if (reg == reg_table[i].val)
10407                         continue;
10408
10409                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10410                                                 reg_table[i].val, NULL);
10411                 if (ret < 0) {
10412                         PMD_DRV_LOG(ERR,
10413                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10414                                 reg_table[i].val, reg_table[i].addr);
10415                         break;
10416                 }
10417                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10418                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10419         }
10420 }
10421
10422 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10423 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10424 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10425 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10426 static int
10427 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10428 {
10429         uint32_t reg;
10430         int ret;
10431
10432         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10433                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10434                 return -EINVAL;
10435         }
10436
10437         /* Configure for double VLAN RX stripping */
10438         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10439         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10440                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10441                 ret = i40e_aq_debug_write_register(hw,
10442                                                    I40E_VSI_TSR(vsi->vsi_id),
10443                                                    reg, NULL);
10444                 if (ret < 0) {
10445                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10446                                     vsi->vsi_id);
10447                         return I40E_ERR_CONFIG;
10448                 }
10449         }
10450
10451         /* Configure for double VLAN TX insertion */
10452         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10453         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10454                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10455                 ret = i40e_aq_debug_write_register(hw,
10456                                                    I40E_VSI_L2TAGSTXVALID(
10457                                                    vsi->vsi_id), reg, NULL);
10458                 if (ret < 0) {
10459                         PMD_DRV_LOG(ERR,
10460                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10461                                 vsi->vsi_id);
10462                         return I40E_ERR_CONFIG;
10463                 }
10464         }
10465
10466         return 0;
10467 }
10468
10469 /**
10470  * i40e_aq_add_mirror_rule
10471  * @hw: pointer to the hardware structure
10472  * @seid: VEB seid to add mirror rule to
10473  * @dst_id: destination vsi seid
10474  * @entries: Buffer which contains the entities to be mirrored
10475  * @count: number of entities contained in the buffer
10476  * @rule_id:the rule_id of the rule to be added
10477  *
10478  * Add a mirror rule for a given veb.
10479  *
10480  **/
10481 static enum i40e_status_code
10482 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10483                         uint16_t seid, uint16_t dst_id,
10484                         uint16_t rule_type, uint16_t *entries,
10485                         uint16_t count, uint16_t *rule_id)
10486 {
10487         struct i40e_aq_desc desc;
10488         struct i40e_aqc_add_delete_mirror_rule cmd;
10489         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10490                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10491                 &desc.params.raw;
10492         uint16_t buff_len;
10493         enum i40e_status_code status;
10494
10495         i40e_fill_default_direct_cmd_desc(&desc,
10496                                           i40e_aqc_opc_add_mirror_rule);
10497         memset(&cmd, 0, sizeof(cmd));
10498
10499         buff_len = sizeof(uint16_t) * count;
10500         desc.datalen = rte_cpu_to_le_16(buff_len);
10501         if (buff_len > 0)
10502                 desc.flags |= rte_cpu_to_le_16(
10503                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10504         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10505                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10506         cmd.num_entries = rte_cpu_to_le_16(count);
10507         cmd.seid = rte_cpu_to_le_16(seid);
10508         cmd.destination = rte_cpu_to_le_16(dst_id);
10509
10510         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10511         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10512         PMD_DRV_LOG(INFO,
10513                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10514                 hw->aq.asq_last_status, resp->rule_id,
10515                 resp->mirror_rules_used, resp->mirror_rules_free);
10516         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10517
10518         return status;
10519 }
10520
10521 /**
10522  * i40e_aq_del_mirror_rule
10523  * @hw: pointer to the hardware structure
10524  * @seid: VEB seid to add mirror rule to
10525  * @entries: Buffer which contains the entities to be mirrored
10526  * @count: number of entities contained in the buffer
10527  * @rule_id:the rule_id of the rule to be delete
10528  *
10529  * Delete a mirror rule for a given veb.
10530  *
10531  **/
10532 static enum i40e_status_code
10533 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10534                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10535                 uint16_t count, uint16_t rule_id)
10536 {
10537         struct i40e_aq_desc desc;
10538         struct i40e_aqc_add_delete_mirror_rule cmd;
10539         uint16_t buff_len = 0;
10540         enum i40e_status_code status;
10541         void *buff = NULL;
10542
10543         i40e_fill_default_direct_cmd_desc(&desc,
10544                                           i40e_aqc_opc_delete_mirror_rule);
10545         memset(&cmd, 0, sizeof(cmd));
10546         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10547                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10548                                                           I40E_AQ_FLAG_RD));
10549                 cmd.num_entries = count;
10550                 buff_len = sizeof(uint16_t) * count;
10551                 desc.datalen = rte_cpu_to_le_16(buff_len);
10552                 buff = (void *)entries;
10553         } else
10554                 /* rule id is filled in destination field for deleting mirror rule */
10555                 cmd.destination = rte_cpu_to_le_16(rule_id);
10556
10557         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10558                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10559         cmd.seid = rte_cpu_to_le_16(seid);
10560
10561         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10562         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10563
10564         return status;
10565 }
10566
10567 /**
10568  * i40e_mirror_rule_set
10569  * @dev: pointer to the hardware structure
10570  * @mirror_conf: mirror rule info
10571  * @sw_id: mirror rule's sw_id
10572  * @on: enable/disable
10573  *
10574  * set a mirror rule.
10575  *
10576  **/
10577 static int
10578 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10579                         struct rte_eth_mirror_conf *mirror_conf,
10580                         uint8_t sw_id, uint8_t on)
10581 {
10582         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10583         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10584         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10585         struct i40e_mirror_rule *parent = NULL;
10586         uint16_t seid, dst_seid, rule_id;
10587         uint16_t i, j = 0;
10588         int ret;
10589
10590         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10591
10592         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10593                 PMD_DRV_LOG(ERR,
10594                         "mirror rule can not be configured without veb or vfs.");
10595                 return -ENOSYS;
10596         }
10597         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10598                 PMD_DRV_LOG(ERR, "mirror table is full.");
10599                 return -ENOSPC;
10600         }
10601         if (mirror_conf->dst_pool > pf->vf_num) {
10602                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10603                                  mirror_conf->dst_pool);
10604                 return -EINVAL;
10605         }
10606
10607         seid = pf->main_vsi->veb->seid;
10608
10609         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10610                 if (sw_id <= it->index) {
10611                         mirr_rule = it;
10612                         break;
10613                 }
10614                 parent = it;
10615         }
10616         if (mirr_rule && sw_id == mirr_rule->index) {
10617                 if (on) {
10618                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10619                         return -EEXIST;
10620                 } else {
10621                         ret = i40e_aq_del_mirror_rule(hw, seid,
10622                                         mirr_rule->rule_type,
10623                                         mirr_rule->entries,
10624                                         mirr_rule->num_entries, mirr_rule->id);
10625                         if (ret < 0) {
10626                                 PMD_DRV_LOG(ERR,
10627                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10628                                         ret, hw->aq.asq_last_status);
10629                                 return -ENOSYS;
10630                         }
10631                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10632                         rte_free(mirr_rule);
10633                         pf->nb_mirror_rule--;
10634                         return 0;
10635                 }
10636         } else if (!on) {
10637                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10638                 return -ENOENT;
10639         }
10640
10641         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10642                                 sizeof(struct i40e_mirror_rule) , 0);
10643         if (!mirr_rule) {
10644                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10645                 return I40E_ERR_NO_MEMORY;
10646         }
10647         switch (mirror_conf->rule_type) {
10648         case ETH_MIRROR_VLAN:
10649                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10650                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10651                                 mirr_rule->entries[j] =
10652                                         mirror_conf->vlan.vlan_id[i];
10653                                 j++;
10654                         }
10655                 }
10656                 if (j == 0) {
10657                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10658                         rte_free(mirr_rule);
10659                         return -EINVAL;
10660                 }
10661                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10662                 break;
10663         case ETH_MIRROR_VIRTUAL_POOL_UP:
10664         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10665                 /* check if the specified pool bit is out of range */
10666                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10667                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10668                         rte_free(mirr_rule);
10669                         return -EINVAL;
10670                 }
10671                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10672                         if (mirror_conf->pool_mask & (1ULL << i)) {
10673                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10674                                 j++;
10675                         }
10676                 }
10677                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10678                         /* add pf vsi to entries */
10679                         mirr_rule->entries[j] = pf->main_vsi_seid;
10680                         j++;
10681                 }
10682                 if (j == 0) {
10683                         PMD_DRV_LOG(ERR, "pool is not specified.");
10684                         rte_free(mirr_rule);
10685                         return -EINVAL;
10686                 }
10687                 /* egress and ingress in aq commands means from switch but not port */
10688                 mirr_rule->rule_type =
10689                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10690                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10691                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10692                 break;
10693         case ETH_MIRROR_UPLINK_PORT:
10694                 /* egress and ingress in aq commands means from switch but not port*/
10695                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10696                 break;
10697         case ETH_MIRROR_DOWNLINK_PORT:
10698                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10699                 break;
10700         default:
10701                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10702                         mirror_conf->rule_type);
10703                 rte_free(mirr_rule);
10704                 return -EINVAL;
10705         }
10706
10707         /* If the dst_pool is equal to vf_num, consider it as PF */
10708         if (mirror_conf->dst_pool == pf->vf_num)
10709                 dst_seid = pf->main_vsi_seid;
10710         else
10711                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10712
10713         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10714                                       mirr_rule->rule_type, mirr_rule->entries,
10715                                       j, &rule_id);
10716         if (ret < 0) {
10717                 PMD_DRV_LOG(ERR,
10718                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10719                         ret, hw->aq.asq_last_status);
10720                 rte_free(mirr_rule);
10721                 return -ENOSYS;
10722         }
10723
10724         mirr_rule->index = sw_id;
10725         mirr_rule->num_entries = j;
10726         mirr_rule->id = rule_id;
10727         mirr_rule->dst_vsi_seid = dst_seid;
10728
10729         if (parent)
10730                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10731         else
10732                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10733
10734         pf->nb_mirror_rule++;
10735         return 0;
10736 }
10737
10738 /**
10739  * i40e_mirror_rule_reset
10740  * @dev: pointer to the device
10741  * @sw_id: mirror rule's sw_id
10742  *
10743  * reset a mirror rule.
10744  *
10745  **/
10746 static int
10747 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10748 {
10749         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10750         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10751         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10752         uint16_t seid;
10753         int ret;
10754
10755         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10756
10757         seid = pf->main_vsi->veb->seid;
10758
10759         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10760                 if (sw_id == it->index) {
10761                         mirr_rule = it;
10762                         break;
10763                 }
10764         }
10765         if (mirr_rule) {
10766                 ret = i40e_aq_del_mirror_rule(hw, seid,
10767                                 mirr_rule->rule_type,
10768                                 mirr_rule->entries,
10769                                 mirr_rule->num_entries, mirr_rule->id);
10770                 if (ret < 0) {
10771                         PMD_DRV_LOG(ERR,
10772                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10773                                 ret, hw->aq.asq_last_status);
10774                         return -ENOSYS;
10775                 }
10776                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10777                 rte_free(mirr_rule);
10778                 pf->nb_mirror_rule--;
10779         } else {
10780                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10781                 return -ENOENT;
10782         }
10783         return 0;
10784 }
10785
10786 static uint64_t
10787 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10788 {
10789         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10790         uint64_t systim_cycles;
10791
10792         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10793         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10794                         << 32;
10795
10796         return systim_cycles;
10797 }
10798
10799 static uint64_t
10800 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10801 {
10802         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10803         uint64_t rx_tstamp;
10804
10805         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10806         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10807                         << 32;
10808
10809         return rx_tstamp;
10810 }
10811
10812 static uint64_t
10813 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10814 {
10815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10816         uint64_t tx_tstamp;
10817
10818         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10819         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10820                         << 32;
10821
10822         return tx_tstamp;
10823 }
10824
10825 static void
10826 i40e_start_timecounters(struct rte_eth_dev *dev)
10827 {
10828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10829         struct i40e_adapter *adapter = dev->data->dev_private;
10830         struct rte_eth_link link;
10831         uint32_t tsync_inc_l;
10832         uint32_t tsync_inc_h;
10833
10834         /* Get current link speed. */
10835         i40e_dev_link_update(dev, 1);
10836         rte_eth_linkstatus_get(dev, &link);
10837
10838         switch (link.link_speed) {
10839         case ETH_SPEED_NUM_40G:
10840         case ETH_SPEED_NUM_25G:
10841                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10842                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10843                 break;
10844         case ETH_SPEED_NUM_10G:
10845                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10846                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10847                 break;
10848         case ETH_SPEED_NUM_1G:
10849                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10850                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10851                 break;
10852         default:
10853                 tsync_inc_l = 0x0;
10854                 tsync_inc_h = 0x0;
10855         }
10856
10857         /* Set the timesync increment value. */
10858         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10859         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10860
10861         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10862         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10863         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10864
10865         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10866         adapter->systime_tc.cc_shift = 0;
10867         adapter->systime_tc.nsec_mask = 0;
10868
10869         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10870         adapter->rx_tstamp_tc.cc_shift = 0;
10871         adapter->rx_tstamp_tc.nsec_mask = 0;
10872
10873         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10874         adapter->tx_tstamp_tc.cc_shift = 0;
10875         adapter->tx_tstamp_tc.nsec_mask = 0;
10876 }
10877
10878 static int
10879 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10880 {
10881         struct i40e_adapter *adapter = dev->data->dev_private;
10882
10883         adapter->systime_tc.nsec += delta;
10884         adapter->rx_tstamp_tc.nsec += delta;
10885         adapter->tx_tstamp_tc.nsec += delta;
10886
10887         return 0;
10888 }
10889
10890 static int
10891 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10892 {
10893         uint64_t ns;
10894         struct i40e_adapter *adapter = dev->data->dev_private;
10895
10896         ns = rte_timespec_to_ns(ts);
10897
10898         /* Set the timecounters to a new value. */
10899         adapter->systime_tc.nsec = ns;
10900         adapter->rx_tstamp_tc.nsec = ns;
10901         adapter->tx_tstamp_tc.nsec = ns;
10902
10903         return 0;
10904 }
10905
10906 static int
10907 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10908 {
10909         uint64_t ns, systime_cycles;
10910         struct i40e_adapter *adapter = dev->data->dev_private;
10911
10912         systime_cycles = i40e_read_systime_cyclecounter(dev);
10913         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10914         *ts = rte_ns_to_timespec(ns);
10915
10916         return 0;
10917 }
10918
10919 static int
10920 i40e_timesync_enable(struct rte_eth_dev *dev)
10921 {
10922         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10923         uint32_t tsync_ctl_l;
10924         uint32_t tsync_ctl_h;
10925
10926         /* Stop the timesync system time. */
10927         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10928         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10929         /* Reset the timesync system time value. */
10930         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10931         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10932
10933         i40e_start_timecounters(dev);
10934
10935         /* Clear timesync registers. */
10936         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10937         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10938         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10939         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10940         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10941         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10942
10943         /* Enable timestamping of PTP packets. */
10944         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10945         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10946
10947         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10948         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10949         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10950
10951         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10952         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10953
10954         return 0;
10955 }
10956
10957 static int
10958 i40e_timesync_disable(struct rte_eth_dev *dev)
10959 {
10960         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10961         uint32_t tsync_ctl_l;
10962         uint32_t tsync_ctl_h;
10963
10964         /* Disable timestamping of transmitted PTP packets. */
10965         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10966         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10967
10968         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10969         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10970
10971         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10972         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10973
10974         /* Reset the timesync increment value. */
10975         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10976         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10977
10978         return 0;
10979 }
10980
10981 static int
10982 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10983                                 struct timespec *timestamp, uint32_t flags)
10984 {
10985         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10986         struct i40e_adapter *adapter = dev->data->dev_private;
10987         uint32_t sync_status;
10988         uint32_t index = flags & 0x03;
10989         uint64_t rx_tstamp_cycles;
10990         uint64_t ns;
10991
10992         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10993         if ((sync_status & (1 << index)) == 0)
10994                 return -EINVAL;
10995
10996         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10997         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10998         *timestamp = rte_ns_to_timespec(ns);
10999
11000         return 0;
11001 }
11002
11003 static int
11004 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11005                                 struct timespec *timestamp)
11006 {
11007         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11008         struct i40e_adapter *adapter = dev->data->dev_private;
11009         uint32_t sync_status;
11010         uint64_t tx_tstamp_cycles;
11011         uint64_t ns;
11012
11013         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11014         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11015                 return -EINVAL;
11016
11017         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11018         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11019         *timestamp = rte_ns_to_timespec(ns);
11020
11021         return 0;
11022 }
11023
11024 /*
11025  * i40e_parse_dcb_configure - parse dcb configure from user
11026  * @dev: the device being configured
11027  * @dcb_cfg: pointer of the result of parse
11028  * @*tc_map: bit map of enabled traffic classes
11029  *
11030  * Returns 0 on success, negative value on failure
11031  */
11032 static int
11033 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11034                          struct i40e_dcbx_config *dcb_cfg,
11035                          uint8_t *tc_map)
11036 {
11037         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11038         uint8_t i, tc_bw, bw_lf;
11039
11040         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11041
11042         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11043         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11044                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11045                 return -EINVAL;
11046         }
11047
11048         /* assume each tc has the same bw */
11049         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11050         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11051                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11052         /* to ensure the sum of tcbw is equal to 100 */
11053         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11054         for (i = 0; i < bw_lf; i++)
11055                 dcb_cfg->etscfg.tcbwtable[i]++;
11056
11057         /* assume each tc has the same Transmission Selection Algorithm */
11058         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11059                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11060
11061         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11062                 dcb_cfg->etscfg.prioritytable[i] =
11063                                 dcb_rx_conf->dcb_tc[i];
11064
11065         /* FW needs one App to configure HW */
11066         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11067         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11068         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11069         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11070
11071         if (dcb_rx_conf->nb_tcs == 0)
11072                 *tc_map = 1; /* tc0 only */
11073         else
11074                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11075
11076         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11077                 dcb_cfg->pfc.willing = 0;
11078                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11079                 dcb_cfg->pfc.pfcenable = *tc_map;
11080         }
11081         return 0;
11082 }
11083
11084
11085 static enum i40e_status_code
11086 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11087                               struct i40e_aqc_vsi_properties_data *info,
11088                               uint8_t enabled_tcmap)
11089 {
11090         enum i40e_status_code ret;
11091         int i, total_tc = 0;
11092         uint16_t qpnum_per_tc, bsf, qp_idx;
11093         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11094         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11095         uint16_t used_queues;
11096
11097         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11098         if (ret != I40E_SUCCESS)
11099                 return ret;
11100
11101         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11102                 if (enabled_tcmap & (1 << i))
11103                         total_tc++;
11104         }
11105         if (total_tc == 0)
11106                 total_tc = 1;
11107         vsi->enabled_tc = enabled_tcmap;
11108
11109         /* different VSI has different queues assigned */
11110         if (vsi->type == I40E_VSI_MAIN)
11111                 used_queues = dev_data->nb_rx_queues -
11112                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11113         else if (vsi->type == I40E_VSI_VMDQ2)
11114                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11115         else {
11116                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11117                 return I40E_ERR_NO_AVAILABLE_VSI;
11118         }
11119
11120         qpnum_per_tc = used_queues / total_tc;
11121         /* Number of queues per enabled TC */
11122         if (qpnum_per_tc == 0) {
11123                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11124                 return I40E_ERR_INVALID_QP_ID;
11125         }
11126         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11127                                 I40E_MAX_Q_PER_TC);
11128         bsf = rte_bsf32(qpnum_per_tc);
11129
11130         /**
11131          * Configure TC and queue mapping parameters, for enabled TC,
11132          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11133          * default queue will serve it.
11134          */
11135         qp_idx = 0;
11136         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11137                 if (vsi->enabled_tc & (1 << i)) {
11138                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11139                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11140                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11141                         qp_idx += qpnum_per_tc;
11142                 } else
11143                         info->tc_mapping[i] = 0;
11144         }
11145
11146         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11147         if (vsi->type == I40E_VSI_SRIOV) {
11148                 info->mapping_flags |=
11149                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11150                 for (i = 0; i < vsi->nb_qps; i++)
11151                         info->queue_mapping[i] =
11152                                 rte_cpu_to_le_16(vsi->base_queue + i);
11153         } else {
11154                 info->mapping_flags |=
11155                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11156                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11157         }
11158         info->valid_sections |=
11159                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11160
11161         return I40E_SUCCESS;
11162 }
11163
11164 /*
11165  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11166  * @veb: VEB to be configured
11167  * @tc_map: enabled TC bitmap
11168  *
11169  * Returns 0 on success, negative value on failure
11170  */
11171 static enum i40e_status_code
11172 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11173 {
11174         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11175         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11176         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11177         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11178         enum i40e_status_code ret = I40E_SUCCESS;
11179         int i;
11180         uint32_t bw_max;
11181
11182         /* Check if enabled_tc is same as existing or new TCs */
11183         if (veb->enabled_tc == tc_map)
11184                 return ret;
11185
11186         /* configure tc bandwidth */
11187         memset(&veb_bw, 0, sizeof(veb_bw));
11188         veb_bw.tc_valid_bits = tc_map;
11189         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11190         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11191                 if (tc_map & BIT_ULL(i))
11192                         veb_bw.tc_bw_share_credits[i] = 1;
11193         }
11194         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11195                                                    &veb_bw, NULL);
11196         if (ret) {
11197                 PMD_INIT_LOG(ERR,
11198                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11199                         hw->aq.asq_last_status);
11200                 return ret;
11201         }
11202
11203         memset(&ets_query, 0, sizeof(ets_query));
11204         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11205                                                    &ets_query, NULL);
11206         if (ret != I40E_SUCCESS) {
11207                 PMD_DRV_LOG(ERR,
11208                         "Failed to get switch_comp ETS configuration %u",
11209                         hw->aq.asq_last_status);
11210                 return ret;
11211         }
11212         memset(&bw_query, 0, sizeof(bw_query));
11213         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11214                                                   &bw_query, NULL);
11215         if (ret != I40E_SUCCESS) {
11216                 PMD_DRV_LOG(ERR,
11217                         "Failed to get switch_comp bandwidth configuration %u",
11218                         hw->aq.asq_last_status);
11219                 return ret;
11220         }
11221
11222         /* store and print out BW info */
11223         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11224         veb->bw_info.bw_max = ets_query.tc_bw_max;
11225         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11226         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11227         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11228                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11229                      I40E_16_BIT_WIDTH);
11230         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11231                 veb->bw_info.bw_ets_share_credits[i] =
11232                                 bw_query.tc_bw_share_credits[i];
11233                 veb->bw_info.bw_ets_credits[i] =
11234                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11235                 /* 4 bits per TC, 4th bit is reserved */
11236                 veb->bw_info.bw_ets_max[i] =
11237                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11238                                   RTE_LEN2MASK(3, uint8_t));
11239                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11240                             veb->bw_info.bw_ets_share_credits[i]);
11241                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11242                             veb->bw_info.bw_ets_credits[i]);
11243                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11244                             veb->bw_info.bw_ets_max[i]);
11245         }
11246
11247         veb->enabled_tc = tc_map;
11248
11249         return ret;
11250 }
11251
11252
11253 /*
11254  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11255  * @vsi: VSI to be configured
11256  * @tc_map: enabled TC bitmap
11257  *
11258  * Returns 0 on success, negative value on failure
11259  */
11260 static enum i40e_status_code
11261 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11262 {
11263         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11264         struct i40e_vsi_context ctxt;
11265         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11266         enum i40e_status_code ret = I40E_SUCCESS;
11267         int i;
11268
11269         /* Check if enabled_tc is same as existing or new TCs */
11270         if (vsi->enabled_tc == tc_map)
11271                 return ret;
11272
11273         /* configure tc bandwidth */
11274         memset(&bw_data, 0, sizeof(bw_data));
11275         bw_data.tc_valid_bits = tc_map;
11276         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11277         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11278                 if (tc_map & BIT_ULL(i))
11279                         bw_data.tc_bw_credits[i] = 1;
11280         }
11281         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11282         if (ret) {
11283                 PMD_INIT_LOG(ERR,
11284                         "AQ command Config VSI BW allocation per TC failed = %d",
11285                         hw->aq.asq_last_status);
11286                 goto out;
11287         }
11288         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11289                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11290
11291         /* Update Queue Pairs Mapping for currently enabled UPs */
11292         ctxt.seid = vsi->seid;
11293         ctxt.pf_num = hw->pf_id;
11294         ctxt.vf_num = 0;
11295         ctxt.uplink_seid = vsi->uplink_seid;
11296         ctxt.info = vsi->info;
11297         i40e_get_cap(hw);
11298         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11299         if (ret)
11300                 goto out;
11301
11302         /* Update the VSI after updating the VSI queue-mapping information */
11303         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11304         if (ret) {
11305                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11306                         hw->aq.asq_last_status);
11307                 goto out;
11308         }
11309         /* update the local VSI info with updated queue map */
11310         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11311                                         sizeof(vsi->info.tc_mapping));
11312         rte_memcpy(&vsi->info.queue_mapping,
11313                         &ctxt.info.queue_mapping,
11314                 sizeof(vsi->info.queue_mapping));
11315         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11316         vsi->info.valid_sections = 0;
11317
11318         /* query and update current VSI BW information */
11319         ret = i40e_vsi_get_bw_config(vsi);
11320         if (ret) {
11321                 PMD_INIT_LOG(ERR,
11322                          "Failed updating vsi bw info, err %s aq_err %s",
11323                          i40e_stat_str(hw, ret),
11324                          i40e_aq_str(hw, hw->aq.asq_last_status));
11325                 goto out;
11326         }
11327
11328         vsi->enabled_tc = tc_map;
11329
11330 out:
11331         return ret;
11332 }
11333
11334 /*
11335  * i40e_dcb_hw_configure - program the dcb setting to hw
11336  * @pf: pf the configuration is taken on
11337  * @new_cfg: new configuration
11338  * @tc_map: enabled TC bitmap
11339  *
11340  * Returns 0 on success, negative value on failure
11341  */
11342 static enum i40e_status_code
11343 i40e_dcb_hw_configure(struct i40e_pf *pf,
11344                       struct i40e_dcbx_config *new_cfg,
11345                       uint8_t tc_map)
11346 {
11347         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11348         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11349         struct i40e_vsi *main_vsi = pf->main_vsi;
11350         struct i40e_vsi_list *vsi_list;
11351         enum i40e_status_code ret;
11352         int i;
11353         uint32_t val;
11354
11355         /* Use the FW API if FW > v4.4*/
11356         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11357               (hw->aq.fw_maj_ver >= 5))) {
11358                 PMD_INIT_LOG(ERR,
11359                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11360                 return I40E_ERR_FIRMWARE_API_VERSION;
11361         }
11362
11363         /* Check if need reconfiguration */
11364         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11365                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11366                 return I40E_SUCCESS;
11367         }
11368
11369         /* Copy the new config to the current config */
11370         *old_cfg = *new_cfg;
11371         old_cfg->etsrec = old_cfg->etscfg;
11372         ret = i40e_set_dcb_config(hw);
11373         if (ret) {
11374                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11375                          i40e_stat_str(hw, ret),
11376                          i40e_aq_str(hw, hw->aq.asq_last_status));
11377                 return ret;
11378         }
11379         /* set receive Arbiter to RR mode and ETS scheme by default */
11380         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11381                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11382                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11383                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11384                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11385                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11386                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11387                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11388                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11389                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11390                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11391                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11392                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11393         }
11394         /* get local mib to check whether it is configured correctly */
11395         /* IEEE mode */
11396         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11397         /* Get Local DCB Config */
11398         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11399                                      &hw->local_dcbx_config);
11400
11401         /* if Veb is created, need to update TC of it at first */
11402         if (main_vsi->veb) {
11403                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11404                 if (ret)
11405                         PMD_INIT_LOG(WARNING,
11406                                  "Failed configuring TC for VEB seid=%d",
11407                                  main_vsi->veb->seid);
11408         }
11409         /* Update each VSI */
11410         i40e_vsi_config_tc(main_vsi, tc_map);
11411         if (main_vsi->veb) {
11412                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11413                         /* Beside main VSI and VMDQ VSIs, only enable default
11414                          * TC for other VSIs
11415                          */
11416                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11417                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11418                                                          tc_map);
11419                         else
11420                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11421                                                          I40E_DEFAULT_TCMAP);
11422                         if (ret)
11423                                 PMD_INIT_LOG(WARNING,
11424                                         "Failed configuring TC for VSI seid=%d",
11425                                         vsi_list->vsi->seid);
11426                         /* continue */
11427                 }
11428         }
11429         return I40E_SUCCESS;
11430 }
11431
11432 /*
11433  * i40e_dcb_init_configure - initial dcb config
11434  * @dev: device being configured
11435  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11436  *
11437  * Returns 0 on success, negative value on failure
11438  */
11439 int
11440 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11441 {
11442         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11443         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11444         int i, ret = 0;
11445
11446         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11447                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11448                 return -ENOTSUP;
11449         }
11450
11451         /* DCB initialization:
11452          * Update DCB configuration from the Firmware and configure
11453          * LLDP MIB change event.
11454          */
11455         if (sw_dcb == TRUE) {
11456                 if (i40e_need_stop_lldp(dev)) {
11457                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11458                         if (ret != I40E_SUCCESS)
11459                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11460                 }
11461
11462                 ret = i40e_init_dcb(hw);
11463                 /* If lldp agent is stopped, the return value from
11464                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11465                  * adminq status. Otherwise, it should return success.
11466                  */
11467                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11468                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11469                         memset(&hw->local_dcbx_config, 0,
11470                                 sizeof(struct i40e_dcbx_config));
11471                         /* set dcb default configuration */
11472                         hw->local_dcbx_config.etscfg.willing = 0;
11473                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11474                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11475                         hw->local_dcbx_config.etscfg.tsatable[0] =
11476                                                 I40E_IEEE_TSA_ETS;
11477                         /* all UPs mapping to TC0 */
11478                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11479                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11480                         hw->local_dcbx_config.etsrec =
11481                                 hw->local_dcbx_config.etscfg;
11482                         hw->local_dcbx_config.pfc.willing = 0;
11483                         hw->local_dcbx_config.pfc.pfccap =
11484                                                 I40E_MAX_TRAFFIC_CLASS;
11485                         /* FW needs one App to configure HW */
11486                         hw->local_dcbx_config.numapps = 1;
11487                         hw->local_dcbx_config.app[0].selector =
11488                                                 I40E_APP_SEL_ETHTYPE;
11489                         hw->local_dcbx_config.app[0].priority = 3;
11490                         hw->local_dcbx_config.app[0].protocolid =
11491                                                 I40E_APP_PROTOID_FCOE;
11492                         ret = i40e_set_dcb_config(hw);
11493                         if (ret) {
11494                                 PMD_INIT_LOG(ERR,
11495                                         "default dcb config fails. err = %d, aq_err = %d.",
11496                                         ret, hw->aq.asq_last_status);
11497                                 return -ENOSYS;
11498                         }
11499                 } else {
11500                         PMD_INIT_LOG(ERR,
11501                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11502                                 ret, hw->aq.asq_last_status);
11503                         return -ENOTSUP;
11504                 }
11505         } else {
11506                 ret = i40e_aq_start_lldp(hw, NULL);
11507                 if (ret != I40E_SUCCESS)
11508                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11509
11510                 ret = i40e_init_dcb(hw);
11511                 if (!ret) {
11512                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11513                                 PMD_INIT_LOG(ERR,
11514                                         "HW doesn't support DCBX offload.");
11515                                 return -ENOTSUP;
11516                         }
11517                 } else {
11518                         PMD_INIT_LOG(ERR,
11519                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11520                                 ret, hw->aq.asq_last_status);
11521                         return -ENOTSUP;
11522                 }
11523         }
11524         return 0;
11525 }
11526
11527 /*
11528  * i40e_dcb_setup - setup dcb related config
11529  * @dev: device being configured
11530  *
11531  * Returns 0 on success, negative value on failure
11532  */
11533 static int
11534 i40e_dcb_setup(struct rte_eth_dev *dev)
11535 {
11536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11537         struct i40e_dcbx_config dcb_cfg;
11538         uint8_t tc_map = 0;
11539         int ret = 0;
11540
11541         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11542                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11543                 return -ENOTSUP;
11544         }
11545
11546         if (pf->vf_num != 0)
11547                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11548
11549         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11550         if (ret) {
11551                 PMD_INIT_LOG(ERR, "invalid dcb config");
11552                 return -EINVAL;
11553         }
11554         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11555         if (ret) {
11556                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11557                 return -ENOSYS;
11558         }
11559
11560         return 0;
11561 }
11562
11563 static int
11564 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11565                       struct rte_eth_dcb_info *dcb_info)
11566 {
11567         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11568         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11569         struct i40e_vsi *vsi = pf->main_vsi;
11570         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11571         uint16_t bsf, tc_mapping;
11572         int i, j = 0;
11573
11574         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11575                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11576         else
11577                 dcb_info->nb_tcs = 1;
11578         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11579                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11580         for (i = 0; i < dcb_info->nb_tcs; i++)
11581                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11582
11583         /* get queue mapping if vmdq is disabled */
11584         if (!pf->nb_cfg_vmdq_vsi) {
11585                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11586                         if (!(vsi->enabled_tc & (1 << i)))
11587                                 continue;
11588                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11589                         dcb_info->tc_queue.tc_rxq[j][i].base =
11590                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11591                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11592                         dcb_info->tc_queue.tc_txq[j][i].base =
11593                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11594                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11595                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11596                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11597                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11598                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11599                 }
11600                 return 0;
11601         }
11602
11603         /* get queue mapping if vmdq is enabled */
11604         do {
11605                 vsi = pf->vmdq[j].vsi;
11606                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11607                         if (!(vsi->enabled_tc & (1 << i)))
11608                                 continue;
11609                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11610                         dcb_info->tc_queue.tc_rxq[j][i].base =
11611                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11612                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11613                         dcb_info->tc_queue.tc_txq[j][i].base =
11614                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11615                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11616                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11617                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11618                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11619                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11620                 }
11621                 j++;
11622         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11623         return 0;
11624 }
11625
11626 static int
11627 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11628 {
11629         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11630         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11631         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11632         uint16_t msix_intr;
11633
11634         msix_intr = intr_handle->intr_vec[queue_id];
11635         if (msix_intr == I40E_MISC_VEC_ID)
11636                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11637                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11638                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11639                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11640         else
11641                 I40E_WRITE_REG(hw,
11642                                I40E_PFINT_DYN_CTLN(msix_intr -
11643                                                    I40E_RX_VEC_START),
11644                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11645                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11646                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11647
11648         I40E_WRITE_FLUSH(hw);
11649         rte_intr_enable(&pci_dev->intr_handle);
11650
11651         return 0;
11652 }
11653
11654 static int
11655 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11656 {
11657         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11658         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11660         uint16_t msix_intr;
11661
11662         msix_intr = intr_handle->intr_vec[queue_id];
11663         if (msix_intr == I40E_MISC_VEC_ID)
11664                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11665                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11666         else
11667                 I40E_WRITE_REG(hw,
11668                                I40E_PFINT_DYN_CTLN(msix_intr -
11669                                                    I40E_RX_VEC_START),
11670                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11671         I40E_WRITE_FLUSH(hw);
11672
11673         return 0;
11674 }
11675
11676 /**
11677  * This function is used to check if the register is valid.
11678  * Below is the valid registers list for X722 only:
11679  * 0x2b800--0x2bb00
11680  * 0x38700--0x38a00
11681  * 0x3d800--0x3db00
11682  * 0x208e00--0x209000
11683  * 0x20be00--0x20c000
11684  * 0x263c00--0x264000
11685  * 0x265c00--0x266000
11686  */
11687 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11688 {
11689         if ((type != I40E_MAC_X722) &&
11690             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11691              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11692              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11693              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11694              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11695              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11696              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11697                 return 0;
11698         else
11699                 return 1;
11700 }
11701
11702 static int i40e_get_regs(struct rte_eth_dev *dev,
11703                          struct rte_dev_reg_info *regs)
11704 {
11705         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11706         uint32_t *ptr_data = regs->data;
11707         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11708         const struct i40e_reg_info *reg_info;
11709
11710         if (ptr_data == NULL) {
11711                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11712                 regs->width = sizeof(uint32_t);
11713                 return 0;
11714         }
11715
11716         /* The first few registers have to be read using AQ operations */
11717         reg_idx = 0;
11718         while (i40e_regs_adminq[reg_idx].name) {
11719                 reg_info = &i40e_regs_adminq[reg_idx++];
11720                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11721                         for (arr_idx2 = 0;
11722                                         arr_idx2 <= reg_info->count2;
11723                                         arr_idx2++) {
11724                                 reg_offset = arr_idx * reg_info->stride1 +
11725                                         arr_idx2 * reg_info->stride2;
11726                                 reg_offset += reg_info->base_addr;
11727                                 ptr_data[reg_offset >> 2] =
11728                                         i40e_read_rx_ctl(hw, reg_offset);
11729                         }
11730         }
11731
11732         /* The remaining registers can be read using primitives */
11733         reg_idx = 0;
11734         while (i40e_regs_others[reg_idx].name) {
11735                 reg_info = &i40e_regs_others[reg_idx++];
11736                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11737                         for (arr_idx2 = 0;
11738                                         arr_idx2 <= reg_info->count2;
11739                                         arr_idx2++) {
11740                                 reg_offset = arr_idx * reg_info->stride1 +
11741                                         arr_idx2 * reg_info->stride2;
11742                                 reg_offset += reg_info->base_addr;
11743                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11744                                         ptr_data[reg_offset >> 2] = 0;
11745                                 else
11746                                         ptr_data[reg_offset >> 2] =
11747                                                 I40E_READ_REG(hw, reg_offset);
11748                         }
11749         }
11750
11751         return 0;
11752 }
11753
11754 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11755 {
11756         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11757
11758         /* Convert word count to byte count */
11759         return hw->nvm.sr_size << 1;
11760 }
11761
11762 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11763                            struct rte_dev_eeprom_info *eeprom)
11764 {
11765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11766         uint16_t *data = eeprom->data;
11767         uint16_t offset, length, cnt_words;
11768         int ret_code;
11769
11770         offset = eeprom->offset >> 1;
11771         length = eeprom->length >> 1;
11772         cnt_words = length;
11773
11774         if (offset > hw->nvm.sr_size ||
11775                 offset + length > hw->nvm.sr_size) {
11776                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11777                 return -EINVAL;
11778         }
11779
11780         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11781
11782         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11783         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11784                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11785                 return -EIO;
11786         }
11787
11788         return 0;
11789 }
11790
11791 static int i40e_get_module_info(struct rte_eth_dev *dev,
11792                                 struct rte_eth_dev_module_info *modinfo)
11793 {
11794         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11795         uint32_t sff8472_comp = 0;
11796         uint32_t sff8472_swap = 0;
11797         uint32_t sff8636_rev = 0;
11798         i40e_status status;
11799         uint32_t type = 0;
11800
11801         /* Check if firmware supports reading module EEPROM. */
11802         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11803                 PMD_DRV_LOG(ERR,
11804                             "Module EEPROM memory read not supported. "
11805                             "Please update the NVM image.\n");
11806                 return -EINVAL;
11807         }
11808
11809         status = i40e_update_link_info(hw);
11810         if (status)
11811                 return -EIO;
11812
11813         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11814                 PMD_DRV_LOG(ERR,
11815                             "Cannot read module EEPROM memory. "
11816                             "No module connected.\n");
11817                 return -EINVAL;
11818         }
11819
11820         type = hw->phy.link_info.module_type[0];
11821
11822         switch (type) {
11823         case I40E_MODULE_TYPE_SFP:
11824                 status = i40e_aq_get_phy_register(hw,
11825                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11826                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11827                                 I40E_MODULE_SFF_8472_COMP,
11828                                 &sff8472_comp, NULL);
11829                 if (status)
11830                         return -EIO;
11831
11832                 status = i40e_aq_get_phy_register(hw,
11833                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11834                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11835                                 I40E_MODULE_SFF_8472_SWAP,
11836                                 &sff8472_swap, NULL);
11837                 if (status)
11838                         return -EIO;
11839
11840                 /* Check if the module requires address swap to access
11841                  * the other EEPROM memory page.
11842                  */
11843                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11844                         PMD_DRV_LOG(WARNING,
11845                                     "Module address swap to access "
11846                                     "page 0xA2 is not supported.\n");
11847                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11848                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11849                 } else if (sff8472_comp == 0x00) {
11850                         /* Module is not SFF-8472 compliant */
11851                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11852                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11853                 } else {
11854                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11855                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11856                 }
11857                 break;
11858         case I40E_MODULE_TYPE_QSFP_PLUS:
11859                 /* Read from memory page 0. */
11860                 status = i40e_aq_get_phy_register(hw,
11861                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11862                                 0, 1,
11863                                 I40E_MODULE_REVISION_ADDR,
11864                                 &sff8636_rev, NULL);
11865                 if (status)
11866                         return -EIO;
11867                 /* Determine revision compliance byte */
11868                 if (sff8636_rev > 0x02) {
11869                         /* Module is SFF-8636 compliant */
11870                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11871                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11872                 } else {
11873                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11874                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11875                 }
11876                 break;
11877         case I40E_MODULE_TYPE_QSFP28:
11878                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11879                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11880                 break;
11881         default:
11882                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11883                 return -EINVAL;
11884         }
11885         return 0;
11886 }
11887
11888 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11889                                   struct rte_dev_eeprom_info *info)
11890 {
11891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11892         bool is_sfp = false;
11893         i40e_status status;
11894         uint8_t *data;
11895         uint32_t value = 0;
11896         uint32_t i;
11897
11898         if (!info || !info->length || !info->data)
11899                 return -EINVAL;
11900
11901         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11902                 is_sfp = true;
11903
11904         data = info->data;
11905         for (i = 0; i < info->length; i++) {
11906                 u32 offset = i + info->offset;
11907                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11908
11909                 /* Check if we need to access the other memory page */
11910                 if (is_sfp) {
11911                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11912                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11913                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11914                         }
11915                 } else {
11916                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11917                                 /* Compute memory page number and offset. */
11918                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11919                                 addr++;
11920                         }
11921                 }
11922                 status = i40e_aq_get_phy_register(hw,
11923                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11924                                 addr, offset, 1, &value, NULL);
11925                 if (status)
11926                         return -EIO;
11927                 data[i] = (uint8_t)value;
11928         }
11929         return 0;
11930 }
11931
11932 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11933                                      struct rte_ether_addr *mac_addr)
11934 {
11935         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11937         struct i40e_vsi *vsi = pf->main_vsi;
11938         struct i40e_mac_filter_info mac_filter;
11939         struct i40e_mac_filter *f;
11940         int ret;
11941
11942         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11943                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11944                 return -EINVAL;
11945         }
11946
11947         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11948                 if (rte_is_same_ether_addr(&pf->dev_addr,
11949                                                 &f->mac_info.mac_addr))
11950                         break;
11951         }
11952
11953         if (f == NULL) {
11954                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11955                 return -EIO;
11956         }
11957
11958         mac_filter = f->mac_info;
11959         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11960         if (ret != I40E_SUCCESS) {
11961                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11962                 return -EIO;
11963         }
11964         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11965         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11966         if (ret != I40E_SUCCESS) {
11967                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11968                 return -EIO;
11969         }
11970         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11971
11972         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11973                                         mac_addr->addr_bytes, NULL);
11974         if (ret != I40E_SUCCESS) {
11975                 PMD_DRV_LOG(ERR, "Failed to change mac");
11976                 return -EIO;
11977         }
11978
11979         return 0;
11980 }
11981
11982 static int
11983 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11984 {
11985         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11986         struct rte_eth_dev_data *dev_data = pf->dev_data;
11987         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11988         int ret = 0;
11989
11990         /* check if mtu is within the allowed range */
11991         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
11992                 return -EINVAL;
11993
11994         /* mtu setting is forbidden if port is start */
11995         if (dev_data->dev_started) {
11996                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11997                             dev_data->port_id);
11998                 return -EBUSY;
11999         }
12000
12001         if (frame_size > RTE_ETHER_MAX_LEN)
12002                 dev_data->dev_conf.rxmode.offloads |=
12003                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12004         else
12005                 dev_data->dev_conf.rxmode.offloads &=
12006                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12007
12008         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12009
12010         return ret;
12011 }
12012
12013 /* Restore ethertype filter */
12014 static void
12015 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12016 {
12017         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12018         struct i40e_ethertype_filter_list
12019                 *ethertype_list = &pf->ethertype.ethertype_list;
12020         struct i40e_ethertype_filter *f;
12021         struct i40e_control_filter_stats stats;
12022         uint16_t flags;
12023
12024         TAILQ_FOREACH(f, ethertype_list, rules) {
12025                 flags = 0;
12026                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12027                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12028                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12029                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12030                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12031
12032                 memset(&stats, 0, sizeof(stats));
12033                 i40e_aq_add_rem_control_packet_filter(hw,
12034                                             f->input.mac_addr.addr_bytes,
12035                                             f->input.ether_type,
12036                                             flags, pf->main_vsi->seid,
12037                                             f->queue, 1, &stats, NULL);
12038         }
12039         PMD_DRV_LOG(INFO, "Ethertype filter:"
12040                     " mac_etype_used = %u, etype_used = %u,"
12041                     " mac_etype_free = %u, etype_free = %u",
12042                     stats.mac_etype_used, stats.etype_used,
12043                     stats.mac_etype_free, stats.etype_free);
12044 }
12045
12046 /* Restore tunnel filter */
12047 static void
12048 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12049 {
12050         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12051         struct i40e_vsi *vsi;
12052         struct i40e_pf_vf *vf;
12053         struct i40e_tunnel_filter_list
12054                 *tunnel_list = &pf->tunnel.tunnel_list;
12055         struct i40e_tunnel_filter *f;
12056         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12057         bool big_buffer = 0;
12058
12059         TAILQ_FOREACH(f, tunnel_list, rules) {
12060                 if (!f->is_to_vf)
12061                         vsi = pf->main_vsi;
12062                 else {
12063                         vf = &pf->vfs[f->vf_id];
12064                         vsi = vf->vsi;
12065                 }
12066                 memset(&cld_filter, 0, sizeof(cld_filter));
12067                 rte_ether_addr_copy((struct rte_ether_addr *)
12068                                 &f->input.outer_mac,
12069                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12070                 rte_ether_addr_copy((struct rte_ether_addr *)
12071                                 &f->input.inner_mac,
12072                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12073                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12074                 cld_filter.element.flags = f->input.flags;
12075                 cld_filter.element.tenant_id = f->input.tenant_id;
12076                 cld_filter.element.queue_number = f->queue;
12077                 rte_memcpy(cld_filter.general_fields,
12078                            f->input.general_fields,
12079                            sizeof(f->input.general_fields));
12080
12081                 if (((f->input.flags &
12082                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12083                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12084                     ((f->input.flags &
12085                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12086                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12087                     ((f->input.flags &
12088                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12089                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12090                         big_buffer = 1;
12091
12092                 if (big_buffer)
12093                         i40e_aq_add_cloud_filters_bb(hw,
12094                                         vsi->seid, &cld_filter, 1);
12095                 else
12096                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12097                                                   &cld_filter.element, 1);
12098         }
12099 }
12100
12101 /* Restore rss filter */
12102 static inline void
12103 i40e_rss_filter_restore(struct i40e_pf *pf)
12104 {
12105         struct i40e_rte_flow_rss_conf *conf =
12106                                         &pf->rss_info;
12107         if (conf->conf.queue_num)
12108                 i40e_config_rss_filter(pf, conf, TRUE);
12109 }
12110
12111 static void
12112 i40e_filter_restore(struct i40e_pf *pf)
12113 {
12114         i40e_ethertype_filter_restore(pf);
12115         i40e_tunnel_filter_restore(pf);
12116         i40e_fdir_filter_restore(pf);
12117         i40e_rss_filter_restore(pf);
12118 }
12119
12120 bool
12121 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12122 {
12123         if (strcmp(dev->device->driver->name, drv->driver.name))
12124                 return false;
12125
12126         return true;
12127 }
12128
12129 bool
12130 is_i40e_supported(struct rte_eth_dev *dev)
12131 {
12132         return is_device_supported(dev, &rte_i40e_pmd);
12133 }
12134
12135 struct i40e_customized_pctype*
12136 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12137 {
12138         int i;
12139
12140         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12141                 if (pf->customized_pctype[i].index == index)
12142                         return &pf->customized_pctype[i];
12143         }
12144         return NULL;
12145 }
12146
12147 static int
12148 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12149                               uint32_t pkg_size, uint32_t proto_num,
12150                               struct rte_pmd_i40e_proto_info *proto,
12151                               enum rte_pmd_i40e_package_op op)
12152 {
12153         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12154         uint32_t pctype_num;
12155         struct rte_pmd_i40e_ptype_info *pctype;
12156         uint32_t buff_size;
12157         struct i40e_customized_pctype *new_pctype = NULL;
12158         uint8_t proto_id;
12159         uint8_t pctype_value;
12160         char name[64];
12161         uint32_t i, j, n;
12162         int ret;
12163
12164         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12165             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12166                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12167                 return -1;
12168         }
12169
12170         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12171                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12172                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12173         if (ret) {
12174                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12175                 return -1;
12176         }
12177         if (!pctype_num) {
12178                 PMD_DRV_LOG(INFO, "No new pctype added");
12179                 return -1;
12180         }
12181
12182         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12183         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12184         if (!pctype) {
12185                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12186                 return -1;
12187         }
12188         /* get information about new pctype list */
12189         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12190                                         (uint8_t *)pctype, buff_size,
12191                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12192         if (ret) {
12193                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12194                 rte_free(pctype);
12195                 return -1;
12196         }
12197
12198         /* Update customized pctype. */
12199         for (i = 0; i < pctype_num; i++) {
12200                 pctype_value = pctype[i].ptype_id;
12201                 memset(name, 0, sizeof(name));
12202                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12203                         proto_id = pctype[i].protocols[j];
12204                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12205                                 continue;
12206                         for (n = 0; n < proto_num; n++) {
12207                                 if (proto[n].proto_id != proto_id)
12208                                         continue;
12209                                 strlcat(name, proto[n].name, sizeof(name));
12210                                 strlcat(name, "_", sizeof(name));
12211                                 break;
12212                         }
12213                 }
12214                 name[strlen(name) - 1] = '\0';
12215                 if (!strcmp(name, "GTPC"))
12216                         new_pctype =
12217                                 i40e_find_customized_pctype(pf,
12218                                                       I40E_CUSTOMIZED_GTPC);
12219                 else if (!strcmp(name, "GTPU_IPV4"))
12220                         new_pctype =
12221                                 i40e_find_customized_pctype(pf,
12222                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12223                 else if (!strcmp(name, "GTPU_IPV6"))
12224                         new_pctype =
12225                                 i40e_find_customized_pctype(pf,
12226                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12227                 else if (!strcmp(name, "GTPU"))
12228                         new_pctype =
12229                                 i40e_find_customized_pctype(pf,
12230                                                       I40E_CUSTOMIZED_GTPU);
12231                 if (new_pctype) {
12232                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12233                                 new_pctype->pctype = pctype_value;
12234                                 new_pctype->valid = true;
12235                         } else {
12236                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12237                                 new_pctype->valid = false;
12238                         }
12239                 }
12240         }
12241
12242         rte_free(pctype);
12243         return 0;
12244 }
12245
12246 static int
12247 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12248                              uint32_t pkg_size, uint32_t proto_num,
12249                              struct rte_pmd_i40e_proto_info *proto,
12250                              enum rte_pmd_i40e_package_op op)
12251 {
12252         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12253         uint16_t port_id = dev->data->port_id;
12254         uint32_t ptype_num;
12255         struct rte_pmd_i40e_ptype_info *ptype;
12256         uint32_t buff_size;
12257         uint8_t proto_id;
12258         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12259         uint32_t i, j, n;
12260         bool in_tunnel;
12261         int ret;
12262
12263         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12264             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12265                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12266                 return -1;
12267         }
12268
12269         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12270                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12271                 return 0;
12272         }
12273
12274         /* get information about new ptype num */
12275         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12276                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12277                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12278         if (ret) {
12279                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12280                 return ret;
12281         }
12282         if (!ptype_num) {
12283                 PMD_DRV_LOG(INFO, "No new ptype added");
12284                 return -1;
12285         }
12286
12287         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12288         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12289         if (!ptype) {
12290                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12291                 return -1;
12292         }
12293
12294         /* get information about new ptype list */
12295         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12296                                         (uint8_t *)ptype, buff_size,
12297                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12298         if (ret) {
12299                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12300                 rte_free(ptype);
12301                 return ret;
12302         }
12303
12304         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12305         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12306         if (!ptype_mapping) {
12307                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12308                 rte_free(ptype);
12309                 return -1;
12310         }
12311
12312         /* Update ptype mapping table. */
12313         for (i = 0; i < ptype_num; i++) {
12314                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12315                 ptype_mapping[i].sw_ptype = 0;
12316                 in_tunnel = false;
12317                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12318                         proto_id = ptype[i].protocols[j];
12319                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12320                                 continue;
12321                         for (n = 0; n < proto_num; n++) {
12322                                 if (proto[n].proto_id != proto_id)
12323                                         continue;
12324                                 memset(name, 0, sizeof(name));
12325                                 strcpy(name, proto[n].name);
12326                                 if (!strncasecmp(name, "PPPOE", 5))
12327                                         ptype_mapping[i].sw_ptype |=
12328                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12329                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12330                                          !in_tunnel) {
12331                                         ptype_mapping[i].sw_ptype |=
12332                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12333                                         ptype_mapping[i].sw_ptype |=
12334                                                 RTE_PTYPE_L4_FRAG;
12335                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12336                                            in_tunnel) {
12337                                         ptype_mapping[i].sw_ptype |=
12338                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12339                                         ptype_mapping[i].sw_ptype |=
12340                                                 RTE_PTYPE_INNER_L4_FRAG;
12341                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12342                                         ptype_mapping[i].sw_ptype |=
12343                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12344                                         in_tunnel = true;
12345                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12346                                            !in_tunnel)
12347                                         ptype_mapping[i].sw_ptype |=
12348                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12349                                 else if (!strncasecmp(name, "IPV4", 4) &&
12350                                          in_tunnel)
12351                                         ptype_mapping[i].sw_ptype |=
12352                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12353                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12354                                          !in_tunnel) {
12355                                         ptype_mapping[i].sw_ptype |=
12356                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12357                                         ptype_mapping[i].sw_ptype |=
12358                                                 RTE_PTYPE_L4_FRAG;
12359                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12360                                            in_tunnel) {
12361                                         ptype_mapping[i].sw_ptype |=
12362                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12363                                         ptype_mapping[i].sw_ptype |=
12364                                                 RTE_PTYPE_INNER_L4_FRAG;
12365                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12366                                         ptype_mapping[i].sw_ptype |=
12367                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12368                                         in_tunnel = true;
12369                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12370                                            !in_tunnel)
12371                                         ptype_mapping[i].sw_ptype |=
12372                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12373                                 else if (!strncasecmp(name, "IPV6", 4) &&
12374                                          in_tunnel)
12375                                         ptype_mapping[i].sw_ptype |=
12376                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12377                                 else if (!strncasecmp(name, "UDP", 3) &&
12378                                          !in_tunnel)
12379                                         ptype_mapping[i].sw_ptype |=
12380                                                 RTE_PTYPE_L4_UDP;
12381                                 else if (!strncasecmp(name, "UDP", 3) &&
12382                                          in_tunnel)
12383                                         ptype_mapping[i].sw_ptype |=
12384                                                 RTE_PTYPE_INNER_L4_UDP;
12385                                 else if (!strncasecmp(name, "TCP", 3) &&
12386                                          !in_tunnel)
12387                                         ptype_mapping[i].sw_ptype |=
12388                                                 RTE_PTYPE_L4_TCP;
12389                                 else if (!strncasecmp(name, "TCP", 3) &&
12390                                          in_tunnel)
12391                                         ptype_mapping[i].sw_ptype |=
12392                                                 RTE_PTYPE_INNER_L4_TCP;
12393                                 else if (!strncasecmp(name, "SCTP", 4) &&
12394                                          !in_tunnel)
12395                                         ptype_mapping[i].sw_ptype |=
12396                                                 RTE_PTYPE_L4_SCTP;
12397                                 else if (!strncasecmp(name, "SCTP", 4) &&
12398                                          in_tunnel)
12399                                         ptype_mapping[i].sw_ptype |=
12400                                                 RTE_PTYPE_INNER_L4_SCTP;
12401                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12402                                           !strncasecmp(name, "ICMPV6", 6)) &&
12403                                          !in_tunnel)
12404                                         ptype_mapping[i].sw_ptype |=
12405                                                 RTE_PTYPE_L4_ICMP;
12406                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12407                                           !strncasecmp(name, "ICMPV6", 6)) &&
12408                                          in_tunnel)
12409                                         ptype_mapping[i].sw_ptype |=
12410                                                 RTE_PTYPE_INNER_L4_ICMP;
12411                                 else if (!strncasecmp(name, "GTPC", 4)) {
12412                                         ptype_mapping[i].sw_ptype |=
12413                                                 RTE_PTYPE_TUNNEL_GTPC;
12414                                         in_tunnel = true;
12415                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12416                                         ptype_mapping[i].sw_ptype |=
12417                                                 RTE_PTYPE_TUNNEL_GTPU;
12418                                         in_tunnel = true;
12419                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12420                                         ptype_mapping[i].sw_ptype |=
12421                                                 RTE_PTYPE_TUNNEL_GRENAT;
12422                                         in_tunnel = true;
12423                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12424                                            !strncasecmp(name, "L2TPV2", 6)) {
12425                                         ptype_mapping[i].sw_ptype |=
12426                                                 RTE_PTYPE_TUNNEL_L2TP;
12427                                         in_tunnel = true;
12428                                 }
12429
12430                                 break;
12431                         }
12432                 }
12433         }
12434
12435         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12436                                                 ptype_num, 0);
12437         if (ret)
12438                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12439
12440         rte_free(ptype_mapping);
12441         rte_free(ptype);
12442         return ret;
12443 }
12444
12445 void
12446 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12447                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12448 {
12449         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12450         uint32_t proto_num;
12451         struct rte_pmd_i40e_proto_info *proto;
12452         uint32_t buff_size;
12453         uint32_t i;
12454         int ret;
12455
12456         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12457             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12458                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12459                 return;
12460         }
12461
12462         /* get information about protocol number */
12463         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12464                                        (uint8_t *)&proto_num, sizeof(proto_num),
12465                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12466         if (ret) {
12467                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12468                 return;
12469         }
12470         if (!proto_num) {
12471                 PMD_DRV_LOG(INFO, "No new protocol added");
12472                 return;
12473         }
12474
12475         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12476         proto = rte_zmalloc("new_proto", buff_size, 0);
12477         if (!proto) {
12478                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12479                 return;
12480         }
12481
12482         /* get information about protocol list */
12483         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12484                                         (uint8_t *)proto, buff_size,
12485                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12486         if (ret) {
12487                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12488                 rte_free(proto);
12489                 return;
12490         }
12491
12492         /* Check if GTP is supported. */
12493         for (i = 0; i < proto_num; i++) {
12494                 if (!strncmp(proto[i].name, "GTP", 3)) {
12495                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12496                                 pf->gtp_support = true;
12497                         else
12498                                 pf->gtp_support = false;
12499                         break;
12500                 }
12501         }
12502
12503         /* Update customized pctype info */
12504         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12505                                             proto_num, proto, op);
12506         if (ret)
12507                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12508
12509         /* Update customized ptype info */
12510         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12511                                            proto_num, proto, op);
12512         if (ret)
12513                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12514
12515         rte_free(proto);
12516 }
12517
12518 /* Create a QinQ cloud filter
12519  *
12520  * The Fortville NIC has limited resources for tunnel filters,
12521  * so we can only reuse existing filters.
12522  *
12523  * In step 1 we define which Field Vector fields can be used for
12524  * filter types.
12525  * As we do not have the inner tag defined as a field,
12526  * we have to define it first, by reusing one of L1 entries.
12527  *
12528  * In step 2 we are replacing one of existing filter types with
12529  * a new one for QinQ.
12530  * As we reusing L1 and replacing L2, some of the default filter
12531  * types will disappear,which depends on L1 and L2 entries we reuse.
12532  *
12533  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12534  *
12535  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12536  *              later when we define the cloud filter.
12537  *      a.      Valid_flags.replace_cloud = 0
12538  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12539  *      c.      New_filter = 0x10
12540  *      d.      TR bit = 0xff (optional, not used here)
12541  *      e.      Buffer – 2 entries:
12542  *              i.      Byte 0 = 8 (outer vlan FV index).
12543  *                      Byte 1 = 0 (rsv)
12544  *                      Byte 2-3 = 0x0fff
12545  *              ii.     Byte 0 = 37 (inner vlan FV index).
12546  *                      Byte 1 =0 (rsv)
12547  *                      Byte 2-3 = 0x0fff
12548  *
12549  * Step 2:
12550  * 2.   Create cloud filter using two L1 filters entries: stag and
12551  *              new filter(outer vlan+ inner vlan)
12552  *      a.      Valid_flags.replace_cloud = 1
12553  *      b.      Old_filter = 1 (instead of outer IP)
12554  *      c.      New_filter = 0x10
12555  *      d.      Buffer – 2 entries:
12556  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12557  *                      Byte 1-3 = 0 (rsv)
12558  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12559  *                      Byte 9-11 = 0 (rsv)
12560  */
12561 static int
12562 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12563 {
12564         int ret = -ENOTSUP;
12565         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12566         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12567         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12568         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12569
12570         if (pf->support_multi_driver) {
12571                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12572                 return ret;
12573         }
12574
12575         /* Init */
12576         memset(&filter_replace, 0,
12577                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12578         memset(&filter_replace_buf, 0,
12579                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12580
12581         /* create L1 filter */
12582         filter_replace.old_filter_type =
12583                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12584         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12585         filter_replace.tr_bit = 0;
12586
12587         /* Prepare the buffer, 2 entries */
12588         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12589         filter_replace_buf.data[0] |=
12590                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12591         /* Field Vector 12b mask */
12592         filter_replace_buf.data[2] = 0xff;
12593         filter_replace_buf.data[3] = 0x0f;
12594         filter_replace_buf.data[4] =
12595                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12596         filter_replace_buf.data[4] |=
12597                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12598         /* Field Vector 12b mask */
12599         filter_replace_buf.data[6] = 0xff;
12600         filter_replace_buf.data[7] = 0x0f;
12601         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12602                         &filter_replace_buf);
12603         if (ret != I40E_SUCCESS)
12604                 return ret;
12605
12606         if (filter_replace.old_filter_type !=
12607             filter_replace.new_filter_type)
12608                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12609                             " original: 0x%x, new: 0x%x",
12610                             dev->device->name,
12611                             filter_replace.old_filter_type,
12612                             filter_replace.new_filter_type);
12613
12614         /* Apply the second L2 cloud filter */
12615         memset(&filter_replace, 0,
12616                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12617         memset(&filter_replace_buf, 0,
12618                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12619
12620         /* create L2 filter, input for L2 filter will be L1 filter  */
12621         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12622         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12623         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12624
12625         /* Prepare the buffer, 2 entries */
12626         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12627         filter_replace_buf.data[0] |=
12628                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12629         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12630         filter_replace_buf.data[4] |=
12631                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12632         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12633                         &filter_replace_buf);
12634         if (!ret && (filter_replace.old_filter_type !=
12635                      filter_replace.new_filter_type))
12636                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12637                             " original: 0x%x, new: 0x%x",
12638                             dev->device->name,
12639                             filter_replace.old_filter_type,
12640                             filter_replace.new_filter_type);
12641
12642         return ret;
12643 }
12644
12645 int
12646 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12647                    const struct rte_flow_action_rss *in)
12648 {
12649         if (in->key_len > RTE_DIM(out->key) ||
12650             in->queue_num > RTE_DIM(out->queue))
12651                 return -EINVAL;
12652         if (!in->key && in->key_len)
12653                 return -EINVAL;
12654         out->conf = (struct rte_flow_action_rss){
12655                 .func = in->func,
12656                 .level = in->level,
12657                 .types = in->types,
12658                 .key_len = in->key_len,
12659                 .queue_num = in->queue_num,
12660                 .queue = memcpy(out->queue, in->queue,
12661                                 sizeof(*in->queue) * in->queue_num),
12662         };
12663         if (in->key)
12664                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12665         return 0;
12666 }
12667
12668 int
12669 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12670                      const struct rte_flow_action_rss *with)
12671 {
12672         return (comp->func == with->func &&
12673                 comp->level == with->level &&
12674                 comp->types == with->types &&
12675                 comp->key_len == with->key_len &&
12676                 comp->queue_num == with->queue_num &&
12677                 !memcmp(comp->key, with->key, with->key_len) &&
12678                 !memcmp(comp->queue, with->queue,
12679                         sizeof(*with->queue) * with->queue_num));
12680 }
12681
12682 int
12683 i40e_config_rss_filter(struct i40e_pf *pf,
12684                 struct i40e_rte_flow_rss_conf *conf, bool add)
12685 {
12686         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12687         uint32_t i, lut = 0;
12688         uint16_t j, num;
12689         struct rte_eth_rss_conf rss_conf = {
12690                 .rss_key = conf->conf.key_len ?
12691                         (void *)(uintptr_t)conf->conf.key : NULL,
12692                 .rss_key_len = conf->conf.key_len,
12693                 .rss_hf = conf->conf.types,
12694         };
12695         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12696
12697         if (!add) {
12698                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12699                         i40e_pf_disable_rss(pf);
12700                         memset(rss_info, 0,
12701                                 sizeof(struct i40e_rte_flow_rss_conf));
12702                         return 0;
12703                 }
12704                 return -EINVAL;
12705         }
12706
12707         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12708          * It's necessary to calculate the actual PF queues that are configured.
12709          */
12710         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12711                 num = i40e_pf_calc_configured_queues_num(pf);
12712         else
12713                 num = pf->dev_data->nb_rx_queues;
12714
12715         num = RTE_MIN(num, conf->conf.queue_num);
12716         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12717                         num);
12718
12719         if (num == 0) {
12720                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12721                 return -ENOTSUP;
12722         }
12723
12724         /* Fill in redirection table */
12725         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12726                 if (j == num)
12727                         j = 0;
12728                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12729                         hw->func_caps.rss_table_entry_width) - 1));
12730                 if ((i & 3) == 3)
12731                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12732         }
12733
12734         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12735                 i40e_pf_disable_rss(pf);
12736                 return 0;
12737         }
12738         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12739                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12740                 /* Random default keys */
12741                 static uint32_t rss_key_default[] = {0x6b793944,
12742                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12743                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12744                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12745
12746                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12747                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12748                                                         sizeof(uint32_t);
12749                 PMD_DRV_LOG(INFO,
12750                         "No valid RSS key config for i40e, using default\n");
12751         }
12752
12753         i40e_hw_rss_hash_set(pf, &rss_conf);
12754
12755         if (i40e_rss_conf_init(rss_info, &conf->conf))
12756                 return -EINVAL;
12757
12758         return 0;
12759 }
12760
12761 RTE_INIT(i40e_init_log)
12762 {
12763         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12764         if (i40e_logtype_init >= 0)
12765                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12766         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12767         if (i40e_logtype_driver >= 0)
12768                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12769 }
12770
12771 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12772                               ETH_I40E_FLOATING_VEB_ARG "=1"
12773                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12774                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12775                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12776                               ETH_I40E_USE_LATEST_VEC "=0|1");