drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_eal.h>
  15 #include <rte_string_fns.h>
  16 #include <rte_pci.h>
  17 #include <rte_bus_pci.h>
  18 #include <rte_ether.h>
  19 #include <rte_ethdev_driver.h>
  20 #include <rte_ethdev_pci.h>
  21 #include <rte_memzone.h>
  22 #include <rte_malloc.h>
  23 #include <rte_memcpy.h>
  24 #include <rte_alarm.h>
  25 #include <rte_dev.h>
  26 #include <rte_eth_ctrl.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44
  45 #define I40E_CLEAR_PXE_WAIT_MS     200
  46
  47 /* Maximun number of capability elements */
  48 #define I40E_MAX_CAP_ELE_NUM       128
  49
  50 /* Wait count and interval */
  51 #define I40E_CHK_Q_ENA_COUNT       1000
  52 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  53
  54 /* Maximun number of VSI */
  55 #define I40E_MAX_NUM_VSIS          (384UL)
  56
  57 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  58
  59 /* Flow control default timer */
  60 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  61
  62 /* Flow control enable fwd bit */
  63 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  64
  65 /* Receive Packet Buffer size */
  66 #define I40E_RXPBSIZE (968 * 1024)
  67
  68 /* Kilobytes shift */
  69 #define I40E_KILOSHIFT 10
  70
  71 /* Flow control default high water */
  72 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  73
  74 /* Flow control default low water */
  75 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Receive Average Packet Size in Byte*/
  78 #define I40E_PACKET_AVERAGE_SIZE 128
  79
  80 /* Mask of PF interrupt causes */
  81 #define I40E_PFINT_ICR0_ENA_MASK ( \
  82                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  83                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  84                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  85                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  86                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  89                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  90                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  91
  92 #define I40E_FLOW_TYPES ( \
  93         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  94         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  95         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  96         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 104
 105 /* Additional timesync values. */
 106 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 107 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 108 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 109 #define I40E_PRTTSYN_TSYNENA     0x80000000
 110 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 111 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 112
 113 /**
 114  * Below are values for writing un-exposed registers suggested
 115  * by silicon experts
 116  */
 117 /* Destination MAC address */
 118 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 119 /* Source MAC address */
 120 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 121 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 122 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 123 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 124 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 125 /* Single VLAN tag in the inner L2 header */
 126 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 127 /* Source IPv4 address */
 128 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 129 /* Destination IPv4 address */
 130 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 131 /* Source IPv4 address for X722 */
 132 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 133 /* Destination IPv4 address for X722 */
 134 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 135 /* IPv4 Protocol for X722 */
 136 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 137 /* IPv4 Time to Live for X722 */
 138 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 139 /* IPv4 Type of Service (TOS) */
 140 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 141 /* IPv4 Protocol */
 142 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 143 /* IPv4 Time to Live */
 144 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 145 /* Source IPv6 address */
 146 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 147 /* Destination IPv6 address */
 148 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 149 /* IPv6 Traffic Class (TC) */
 150 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 151 /* IPv6 Next Header */
 152 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 153 /* IPv6 Hop Limit */
 154 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 155 /* Source L4 port */
 156 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 157 /* Destination L4 port */
 158 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 159 /* SCTP verification tag */
 160 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 161 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 162 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 163 /* Source port of tunneling UDP */
 164 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 165 /* Destination port of tunneling UDP */
 166 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 167 /* UDP Tunneling ID, NVGRE/GRE key */
 168 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 169 /* Last ether type */
 170 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 171 /* Tunneling outer destination IPv4 address */
 172 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 173 /* Tunneling outer destination IPv6 address */
 174 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 175 /* 1st word of flex payload */
 176 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 177 /* 2nd word of flex payload */
 178 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 179 /* 3rd word of flex payload */
 180 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 181 /* 4th word of flex payload */
 182 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 183 /* 5th word of flex payload */
 184 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 185 /* 6th word of flex payload */
 186 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 187 /* 7th word of flex payload */
 188 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 189 /* 8th word of flex payload */
 190 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 191 /* all 8 words flex payload */
 192 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 193 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 194
 195 #define I40E_TRANSLATE_INSET 0
 196 #define I40E_TRANSLATE_REG   1
 197
 198 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 199 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 200 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 201 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 202 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 203 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 204
 205 /* PCI offset for querying capability */
 206 #define PCI_DEV_CAP_REG            0xA4
 207 /* PCI offset for enabling/disabling Extended Tag */
 208 #define PCI_DEV_CTRL_REG           0xA8
 209 /* Bit mask of Extended Tag capability */
 210 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 211 /* Bit shift of Extended Tag enable/disable */
 212 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 213 /* Bit mask of Extended Tag enable/disable */
 214 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 215
 216 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 217 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 218 static int i40e_dev_configure(struct rte_eth_dev *dev);
 219 static int i40e_dev_start(struct rte_eth_dev *dev);
 220 static void i40e_dev_stop(struct rte_eth_dev *dev);
 221 static void i40e_dev_close(struct rte_eth_dev *dev);
 222 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 223 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 224 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 225 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 226 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 227 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 228 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 229 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 230                                struct rte_eth_stats *stats);
 231 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 232                                struct rte_eth_xstat *xstats, unsigned n);
 233 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 234                                      struct rte_eth_xstat_name *xstats_names,
 235                                      unsigned limit);
 236 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 237 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 238                                             uint16_t queue_id,
 239                                             uint8_t stat_idx,
 240                                             uint8_t is_rx);
 241 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 242                                 char *fw_version, size_t fw_size);
 243 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 244                               struct rte_eth_dev_info *dev_info);
 245 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 246                                 uint16_t vlan_id,
 247                                 int on);
 248 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 249                               enum rte_vlan_type vlan_type,
 250                               uint16_t tpid);
 251 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 252 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 253                                       uint16_t queue,
 254                                       int on);
 255 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 256 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 257 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 258 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 259                               struct rte_eth_fc_conf *fc_conf);
 260 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 261                               struct rte_eth_fc_conf *fc_conf);
 262 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 263                                        struct rte_eth_pfc_conf *pfc_conf);
 264 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 265                             struct ether_addr *mac_addr,
 266                             uint32_t index,
 267                             uint32_t pool);
 268 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 269 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 270                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 271                                     uint16_t reta_size);
 272 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 273                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                    uint16_t reta_size);
 275
 276 static int i40e_get_cap(struct i40e_hw *hw);
 277 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 278 static int i40e_pf_setup(struct i40e_pf *pf);
 279 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 280 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 281 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 282 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 283                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 284 static void i40e_stat_update_48(struct i40e_hw *hw,
 285                                uint32_t hireg,
 286                                uint32_t loreg,
 287                                bool offset_loaded,
 288                                uint64_t *offset,
 289                                uint64_t *stat);
 290 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 291 static void i40e_dev_interrupt_handler(void *param);
 292 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 293                                 uint32_t base, uint32_t num);
 294 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 295 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 296                         uint32_t base);
 297 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 298                         uint16_t num);
 299 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 300 static int i40e_veb_release(struct i40e_veb *veb);
 301 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 302                                                 struct i40e_vsi *vsi);
 303 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 304 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 305 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 306                                              struct i40e_macvlan_filter *mv_f,
 307                                              int num,
 308                                              uint16_t vlan);
 309 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 310 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 311                                     struct rte_eth_rss_conf *rss_conf);
 312 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 313                                       struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 315                                         struct rte_eth_udp_tunnel *udp_tunnel);
 316 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 319 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 320                                 enum rte_filter_op filter_op,
 321                                 void *arg);
 322 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 323                                 enum rte_filter_type filter_type,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 327                                   struct rte_eth_dcb_info *dcb_info);
 328 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 329 static void i40e_configure_registers(struct i40e_hw *hw);
 330 static void i40e_hw_init(struct rte_eth_dev *dev);
 331 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 332 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 333                                                      uint16_t seid,
 334                                                      uint16_t rule_type,
 335                                                      uint16_t *entries,
 336                                                      uint16_t count,
 337                                                      uint16_t rule_id);
 338 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 339                         struct rte_eth_mirror_conf *mirror_conf,
 340                         uint8_t sw_id, uint8_t on);
 341 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 342
 343 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 344 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 345 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 346                                            struct timespec *timestamp,
 347                                            uint32_t flags);
 348 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 349                                            struct timespec *timestamp);
 350 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 351
 352 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 353
 354 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 355                                    struct timespec *timestamp);
 356 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 357                                     const struct timespec *timestamp);
 358
 359 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 360                                          uint16_t queue_id);
 361 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 362                                           uint16_t queue_id);
 363
 364 static int i40e_get_regs(struct rte_eth_dev *dev,
 365                          struct rte_dev_reg_info *regs);
 366
 367 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 368
 369 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 370                            struct rte_dev_eeprom_info *eeprom);
 371
 372 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 373                                       struct ether_addr *mac_addr);
 374
 375 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 376
 377 static int i40e_ethertype_filter_convert(
 378         const struct rte_eth_ethertype_filter *input,
 379         struct i40e_ethertype_filter *filter);
 380 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 381                                    struct i40e_ethertype_filter *filter);
 382
 383 static int i40e_tunnel_filter_convert(
 384         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
 385         struct i40e_tunnel_filter *tunnel_filter);
 386 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 387                                 struct i40e_tunnel_filter *tunnel_filter);
 388 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 389
 390 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 391 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 392 static void i40e_filter_restore(struct i40e_pf *pf);
 393 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 394
 395 int i40e_logtype_init;
 396 int i40e_logtype_driver;
 397
 398 static const struct rte_pci_id pci_id_i40e_map[] = {
 399         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 400         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 401         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 402         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 403         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 404         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 405         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 406         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 407         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 408         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 409         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 410         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 411         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 419         { .vendor_id = 0, /* sentinel */ },
 420 };
 421
 422 static const struct eth_dev_ops i40e_eth_dev_ops = {
 423         .dev_configure                = i40e_dev_configure,
 424         .dev_start                    = i40e_dev_start,
 425         .dev_stop                     = i40e_dev_stop,
 426         .dev_close                    = i40e_dev_close,
 427         .dev_reset                    = i40e_dev_reset,
 428         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 429         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 430         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 431         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 432         .dev_set_link_up              = i40e_dev_set_link_up,
 433         .dev_set_link_down            = i40e_dev_set_link_down,
 434         .link_update                  = i40e_dev_link_update,
 435         .stats_get                    = i40e_dev_stats_get,
 436         .xstats_get                   = i40e_dev_xstats_get,
 437         .xstats_get_names             = i40e_dev_xstats_get_names,
 438         .stats_reset                  = i40e_dev_stats_reset,
 439         .xstats_reset                 = i40e_dev_stats_reset,
 440         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 441         .fw_version_get               = i40e_fw_version_get,
 442         .dev_infos_get                = i40e_dev_info_get,
 443         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 444         .vlan_filter_set              = i40e_vlan_filter_set,
 445         .vlan_tpid_set                = i40e_vlan_tpid_set,
 446         .vlan_offload_set             = i40e_vlan_offload_set,
 447         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 448         .vlan_pvid_set                = i40e_vlan_pvid_set,
 449         .rx_queue_start               = i40e_dev_rx_queue_start,
 450         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 451         .tx_queue_start               = i40e_dev_tx_queue_start,
 452         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 453         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 454         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 455         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 456         .rx_queue_release             = i40e_dev_rx_queue_release,
 457         .rx_queue_count               = i40e_dev_rx_queue_count,
 458         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 459         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 460         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 461         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 462         .tx_queue_release             = i40e_dev_tx_queue_release,
 463         .dev_led_on                   = i40e_dev_led_on,
 464         .dev_led_off                  = i40e_dev_led_off,
 465         .flow_ctrl_get                = i40e_flow_ctrl_get,
 466         .flow_ctrl_set                = i40e_flow_ctrl_set,
 467         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 468         .mac_addr_add                 = i40e_macaddr_add,
 469         .mac_addr_remove              = i40e_macaddr_remove,
 470         .reta_update                  = i40e_dev_rss_reta_update,
 471         .reta_query                   = i40e_dev_rss_reta_query,
 472         .rss_hash_update              = i40e_dev_rss_hash_update,
 473         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 474         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 475         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 476         .filter_ctrl                  = i40e_dev_filter_ctrl,
 477         .rxq_info_get                 = i40e_rxq_info_get,
 478         .txq_info_get                 = i40e_txq_info_get,
 479         .mirror_rule_set              = i40e_mirror_rule_set,
 480         .mirror_rule_reset            = i40e_mirror_rule_reset,
 481         .timesync_enable              = i40e_timesync_enable,
 482         .timesync_disable             = i40e_timesync_disable,
 483         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 484         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 485         .get_dcb_info                 = i40e_dev_get_dcb_info,
 486         .timesync_adjust_time         = i40e_timesync_adjust_time,
 487         .timesync_read_time           = i40e_timesync_read_time,
 488         .timesync_write_time          = i40e_timesync_write_time,
 489         .get_reg                      = i40e_get_regs,
 490         .get_eeprom_length            = i40e_get_eeprom_length,
 491         .get_eeprom                   = i40e_get_eeprom,
 492         .mac_addr_set                 = i40e_set_default_mac_addr,
 493         .mtu_set                      = i40e_dev_mtu_set,
 494         .tm_ops_get                   = i40e_tm_ops_get,
 495 };
 496
 497 /* store statistics names and its offset in stats structure */
 498 struct rte_i40e_xstats_name_off {
 499         char name[RTE_ETH_XSTATS_NAME_SIZE];
 500         unsigned offset;
 501 };
 502
 503 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 504         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 505         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 506         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 507         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 508         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 509                 rx_unknown_protocol)},
 510         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 511         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 512         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 513         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 514 };
 515
 516 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 517                 sizeof(rte_i40e_stats_strings[0]))
 518
 519 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 520         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 521                 tx_dropped_link_down)},
 522         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 523         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 524                 illegal_bytes)},
 525         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 526         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 527                 mac_local_faults)},
 528         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 529                 mac_remote_faults)},
 530         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 531                 rx_length_errors)},
 532         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 533         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 534         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 535         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 536         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 537         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 538                 rx_size_127)},
 539         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 540                 rx_size_255)},
 541         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 542                 rx_size_511)},
 543         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 544                 rx_size_1023)},
 545         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 546                 rx_size_1522)},
 547         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 548                 rx_size_big)},
 549         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 550                 rx_undersize)},
 551         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 552                 rx_oversize)},
 553         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 554                 mac_short_packet_dropped)},
 555         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 556                 rx_fragments)},
 557         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 558         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 559         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 tx_size_127)},
 561         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 tx_size_255)},
 563         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 tx_size_511)},
 565         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 tx_size_1023)},
 567         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 tx_size_1522)},
 569         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 tx_size_big)},
 571         {"rx_flow_director_atr_match_packets",
 572                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 573         {"rx_flow_director_sb_match_packets",
 574                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 575         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 576                 tx_lpi_status)},
 577         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 578                 rx_lpi_status)},
 579         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 580                 tx_lpi_count)},
 581         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 582                 rx_lpi_count)},
 583 };
 584
 585 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 586                 sizeof(rte_i40e_hw_port_strings[0]))
 587
 588 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 589         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 590                 priority_xon_rx)},
 591         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 592                 priority_xoff_rx)},
 593 };
 594
 595 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 596                 sizeof(rte_i40e_rxq_prio_strings[0]))
 597
 598 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 599         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 600                 priority_xon_tx)},
 601         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 602                 priority_xoff_tx)},
 603         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 604                 priority_xon_2_xoff)},
 605 };
 606
 607 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 608                 sizeof(rte_i40e_txq_prio_strings[0]))
 609
 610 static int eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 611         struct rte_pci_device *pci_dev)
 612 {
 613         return rte_eth_dev_pci_generic_probe(pci_dev,
 614                 sizeof(struct i40e_adapter), eth_i40e_dev_init);
 615 }
 616
 617 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 618 {
 619         return rte_eth_dev_pci_generic_remove(pci_dev, eth_i40e_dev_uninit);
 620 }
 621
 622 static struct rte_pci_driver rte_i40e_pmd = {
 623         .id_table = pci_id_i40e_map,
 624         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 625                      RTE_PCI_DRV_IOVA_AS_VA,
 626         .probe = eth_i40e_pci_probe,
 627         .remove = eth_i40e_pci_remove,
 628 };
 629
 630 static inline int
 631 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 632                                      struct rte_eth_link *link)
 633 {
 634         struct rte_eth_link *dst = link;
 635         struct rte_eth_link *src = &(dev->data->dev_link);
 636
 637         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 638                                         *(uint64_t *)src) == 0)
 639                 return -1;
 640
 641         return 0;
 642 }
 643
 644 static inline int
 645 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 646                                       struct rte_eth_link *link)
 647 {
 648         struct rte_eth_link *dst = &(dev->data->dev_link);
 649         struct rte_eth_link *src = link;
 650
 651         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 652                                         *(uint64_t *)src) == 0)
 653                 return -1;
 654
 655         return 0;
 656 }
 657
 658 static inline void
 659 i40e_write_global_rx_ctl(struct i40e_hw *hw, u32 reg_addr, u32 reg_val)
 660 {
 661         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 662         PMD_DRV_LOG(DEBUG, "Global register 0x%08x is modified "
 663                     "with value 0x%08x",
 664                     reg_addr, reg_val);
 665 }
 666
 667 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 668 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 669 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 670
 671 #ifndef I40E_GLQF_ORT
 672 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 673 #endif
 674 #ifndef I40E_GLQF_PIT
 675 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 676 #endif
 677 #ifndef I40E_GLQF_L3_MAP
 678 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 679 #endif
 680
 681 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 682 {
 683         /*
 684          * Initialize registers for parsing packet type of QinQ
 685          * This should be removed from code once proper
 686          * configuration API is added to avoid configuration conflicts
 687          * between ports of the same device.
 688          */
 689         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 690         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 691         i40e_global_cfg_warning(I40E_WARNING_QINQ_PARSER);
 692 }
 693
 694 static inline void i40e_config_automask(struct i40e_pf *pf)
 695 {
 696         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 697         uint32_t val;
 698
 699         /* INTENA flag is not auto-cleared for interrupt */
 700         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 701         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 702                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 703
 704         /* If support multi-driver, PF will use INT0. */
 705         if (!pf->support_multi_driver)
 706                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 707
 708         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 709 }
 710
 711 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 712
 713 /*
 714  * Add a ethertype filter to drop all flow control frames transmitted
 715  * from VSIs.
 716 */
 717 static void
 718 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 719 {
 720         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 721         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 722                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 723                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 724         int ret;
 725
 726         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 727                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 728                                 pf->main_vsi_seid, 0,
 729                                 TRUE, NULL, NULL);
 730         if (ret)
 731                 PMD_INIT_LOG(ERR,
 732                         "Failed to add filter to drop flow control frames from VSIs.");
 733 }
 734
 735 static int
 736 floating_veb_list_handler(__rte_unused const char *key,
 737                           const char *floating_veb_value,
 738                           void *opaque)
 739 {
 740         int idx = 0;
 741         unsigned int count = 0;
 742         char *end = NULL;
 743         int min, max;
 744         bool *vf_floating_veb = opaque;
 745
 746         while (isblank(*floating_veb_value))
 747                 floating_veb_value++;
 748
 749         /* Reset floating VEB configuration for VFs */
 750         for (idx = 0; idx < I40E_MAX_VF; idx++)
 751                 vf_floating_veb[idx] = false;
 752
 753         min = I40E_MAX_VF;
 754         do {
 755                 while (isblank(*floating_veb_value))
 756                         floating_veb_value++;
 757                 if (*floating_veb_value == '\0')
 758                         return -1;
 759                 errno = 0;
 760                 idx = strtoul(floating_veb_value, &end, 10);
 761                 if (errno || end == NULL)
 762                         return -1;
 763                 while (isblank(*end))
 764                         end++;
 765                 if (*end == '-') {
 766                         min = idx;
 767                 } else if ((*end == ';') || (*end == '\0')) {
 768                         max = idx;
 769                         if (min == I40E_MAX_VF)
 770                                 min = idx;
 771                         if (max >= I40E_MAX_VF)
 772                                 max = I40E_MAX_VF - 1;
 773                         for (idx = min; idx <= max; idx++) {
 774                                 vf_floating_veb[idx] = true;
 775                                 count++;
 776                         }
 777                         min = I40E_MAX_VF;
 778                 } else {
 779                         return -1;
 780                 }
 781                 floating_veb_value = end + 1;
 782         } while (*end != '\0');
 783
 784         if (count == 0)
 785                 return -1;
 786
 787         return 0;
 788 }
 789
 790 static void
 791 config_vf_floating_veb(struct rte_devargs *devargs,
 792                        uint16_t floating_veb,
 793                        bool *vf_floating_veb)
 794 {
 795         struct rte_kvargs *kvlist;
 796         int i;
 797         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 798
 799         if (!floating_veb)
 800                 return;
 801         /* All the VFs attach to the floating VEB by default
 802          * when the floating VEB is enabled.
 803          */
 804         for (i = 0; i < I40E_MAX_VF; i++)
 805                 vf_floating_veb[i] = true;
 806
 807         if (devargs == NULL)
 808                 return;
 809
 810         kvlist = rte_kvargs_parse(devargs->args, NULL);
 811         if (kvlist == NULL)
 812                 return;
 813
 814         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 815                 rte_kvargs_free(kvlist);
 816                 return;
 817         }
 818         /* When the floating_veb_list parameter exists, all the VFs
 819          * will attach to the legacy VEB firstly, then configure VFs
 820          * to the floating VEB according to the floating_veb_list.
 821          */
 822         if (rte_kvargs_process(kvlist, floating_veb_list,
 823                                floating_veb_list_handler,
 824                                vf_floating_veb) < 0) {
 825                 rte_kvargs_free(kvlist);
 826                 return;
 827         }
 828         rte_kvargs_free(kvlist);
 829 }
 830
 831 static int
 832 i40e_check_floating_handler(__rte_unused const char *key,
 833                             const char *value,
 834                             __rte_unused void *opaque)
 835 {
 836         if (strcmp(value, "1"))
 837                 return -1;
 838
 839         return 0;
 840 }
 841
 842 static int
 843 is_floating_veb_supported(struct rte_devargs *devargs)
 844 {
 845         struct rte_kvargs *kvlist;
 846         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 847
 848         if (devargs == NULL)
 849                 return 0;
 850
 851         kvlist = rte_kvargs_parse(devargs->args, NULL);
 852         if (kvlist == NULL)
 853                 return 0;
 854
 855         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 856                 rte_kvargs_free(kvlist);
 857                 return 0;
 858         }
 859         /* Floating VEB is enabled when there's key-value:
 860          * enable_floating_veb=1
 861          */
 862         if (rte_kvargs_process(kvlist, floating_veb_key,
 863                                i40e_check_floating_handler, NULL) < 0) {
 864                 rte_kvargs_free(kvlist);
 865                 return 0;
 866         }
 867         rte_kvargs_free(kvlist);
 868
 869         return 1;
 870 }
 871
 872 static void
 873 config_floating_veb(struct rte_eth_dev *dev)
 874 {
 875         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 876         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 878
 879         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 880
 881         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 882                 pf->floating_veb =
 883                         is_floating_veb_supported(pci_dev->device.devargs);
 884                 config_vf_floating_veb(pci_dev->device.devargs,
 885                                        pf->floating_veb,
 886                                        pf->floating_veb_list);
 887         } else {
 888                 pf->floating_veb = false;
 889         }
 890 }
 891
 892 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 893 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 894
 895 static int
 896 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 897 {
 898         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 899         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 900         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 901         int ret;
 902
 903         struct rte_hash_parameters ethertype_hash_params = {
 904                 .name = ethertype_hash_name,
 905                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 906                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 907                 .hash_func = rte_hash_crc,
 908                 .hash_func_init_val = 0,
 909                 .socket_id = rte_socket_id(),
 910         };
 911
 912         /* Initialize ethertype filter rule list and hash */
 913         TAILQ_INIT(&ethertype_rule->ethertype_list);
 914         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 915                  "ethertype_%s", dev->device->name);
 916         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 917         if (!ethertype_rule->hash_table) {
 918                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 919                 return -EINVAL;
 920         }
 921         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 922                                        sizeof(struct i40e_ethertype_filter *) *
 923                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 924                                        0);
 925         if (!ethertype_rule->hash_map) {
 926                 PMD_INIT_LOG(ERR,
 927                              "Failed to allocate memory for ethertype hash map!");
 928                 ret = -ENOMEM;
 929                 goto err_ethertype_hash_map_alloc;
 930         }
 931
 932         return 0;
 933
 934 err_ethertype_hash_map_alloc:
 935         rte_hash_free(ethertype_rule->hash_table);
 936
 937         return ret;
 938 }
 939
 940 static int
 941 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
 942 {
 943         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 944         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
 945         char tunnel_hash_name[RTE_HASH_NAMESIZE];
 946         int ret;
 947
 948         struct rte_hash_parameters tunnel_hash_params = {
 949                 .name = tunnel_hash_name,
 950                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
 951                 .key_len = sizeof(struct i40e_tunnel_filter_input),
 952                 .hash_func = rte_hash_crc,
 953                 .hash_func_init_val = 0,
 954                 .socket_id = rte_socket_id(),
 955         };
 956
 957         /* Initialize tunnel filter rule list and hash */
 958         TAILQ_INIT(&tunnel_rule->tunnel_list);
 959         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
 960                  "tunnel_%s", dev->device->name);
 961         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
 962         if (!tunnel_rule->hash_table) {
 963                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
 964                 return -EINVAL;
 965         }
 966         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
 967                                     sizeof(struct i40e_tunnel_filter *) *
 968                                     I40E_MAX_TUNNEL_FILTER_NUM,
 969                                     0);
 970         if (!tunnel_rule->hash_map) {
 971                 PMD_INIT_LOG(ERR,
 972                              "Failed to allocate memory for tunnel hash map!");
 973                 ret = -ENOMEM;
 974                 goto err_tunnel_hash_map_alloc;
 975         }
 976
 977         return 0;
 978
 979 err_tunnel_hash_map_alloc:
 980         rte_hash_free(tunnel_rule->hash_table);
 981
 982         return ret;
 983 }
 984
 985 static int
 986 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
 987 {
 988         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 989         struct i40e_fdir_info *fdir_info = &pf->fdir;
 990         char fdir_hash_name[RTE_HASH_NAMESIZE];
 991         int ret;
 992
 993         struct rte_hash_parameters fdir_hash_params = {
 994                 .name = fdir_hash_name,
 995                 .entries = I40E_MAX_FDIR_FILTER_NUM,
 996                 .key_len = sizeof(struct i40e_fdir_input),
 997                 .hash_func = rte_hash_crc,
 998                 .hash_func_init_val = 0,
 999                 .socket_id = rte_socket_id(),
1000         };
1001
1002         /* Initialize flow director filter rule list and hash */
1003         TAILQ_INIT(&fdir_info->fdir_list);
1004         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1005                  "fdir_%s", dev->device->name);
1006         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1007         if (!fdir_info->hash_table) {
1008                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1009                 return -EINVAL;
1010         }
1011         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1012                                           sizeof(struct i40e_fdir_filter *) *
1013                                           I40E_MAX_FDIR_FILTER_NUM,
1014                                           0);
1015         if (!fdir_info->hash_map) {
1016                 PMD_INIT_LOG(ERR,
1017                              "Failed to allocate memory for fdir hash map!");
1018                 ret = -ENOMEM;
1019                 goto err_fdir_hash_map_alloc;
1020         }
1021         return 0;
1022
1023 err_fdir_hash_map_alloc:
1024         rte_hash_free(fdir_info->hash_table);
1025
1026         return ret;
1027 }
1028
1029 static void
1030 i40e_init_customized_info(struct i40e_pf *pf)
1031 {
1032         int i;
1033
1034         /* Initialize customized pctype */
1035         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1036                 pf->customized_pctype[i].index = i;
1037                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1038                 pf->customized_pctype[i].valid = false;
1039         }
1040
1041         pf->gtp_support = false;
1042 }
1043
1044 void
1045 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1046 {
1047         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_queue_regions *info = &pf->queue_region;
1050         uint16_t i;
1051
1052         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1053                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1054
1055         memset(info, 0, sizeof(struct i40e_queue_regions));
1056 }
1057
1058 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
1059
1060 static int
1061 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1062                                const char *value,
1063                                void *opaque)
1064 {
1065         struct i40e_pf *pf;
1066         unsigned long support_multi_driver;
1067         char *end;
1068
1069         pf = (struct i40e_pf *)opaque;
1070
1071         errno = 0;
1072         support_multi_driver = strtoul(value, &end, 10);
1073         if (errno != 0 || end == value || *end != 0) {
1074                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1075                 return -(EINVAL);
1076         }
1077
1078         if (support_multi_driver == 1 || support_multi_driver == 0)
1079                 pf->support_multi_driver = (bool)support_multi_driver;
1080         else
1081                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1082                             "enable global configuration by default."
1083                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1084         return 0;
1085 }
1086
1087 static int
1088 i40e_support_multi_driver(struct rte_eth_dev *dev)
1089 {
1090         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1091         static const char *const valid_keys[] = {
1092                 ETH_I40E_SUPPORT_MULTI_DRIVER, NULL};
1093         struct rte_kvargs *kvlist;
1094
1095         /* Enable global configuration by default */
1096         pf->support_multi_driver = false;
1097
1098         if (!dev->device->devargs)
1099                 return 0;
1100
1101         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1102         if (!kvlist)
1103                 return -EINVAL;
1104
1105         if (rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER) > 1)
1106                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1107                             "the first invalid or last valid one is used !",
1108                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1109
1110         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1111                                i40e_parse_multi_drv_handler, pf) < 0) {
1112                 rte_kvargs_free(kvlist);
1113                 return -EINVAL;
1114         }
1115
1116         rte_kvargs_free(kvlist);
1117         return 0;
1118 }
1119
1120 static int
1121 eth_i40e_dev_init(struct rte_eth_dev *dev)
1122 {
1123         struct rte_pci_device *pci_dev;
1124         struct rte_intr_handle *intr_handle;
1125         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1126         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1127         struct i40e_vsi *vsi;
1128         int ret;
1129         uint32_t len;
1130         uint8_t aq_fail = 0;
1131
1132         PMD_INIT_FUNC_TRACE();
1133
1134         dev->dev_ops = &i40e_eth_dev_ops;
1135         dev->rx_pkt_burst = i40e_recv_pkts;
1136         dev->tx_pkt_burst = i40e_xmit_pkts;
1137         dev->tx_pkt_prepare = i40e_prep_pkts;
1138
1139         /* for secondary processes, we don't initialise any further as primary
1140          * has already done this work. Only check we don't need a different
1141          * RX function */
1142         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1143                 i40e_set_rx_function(dev);
1144                 i40e_set_tx_function(dev);
1145                 return 0;
1146         }
1147         i40e_set_default_ptype_table(dev);
1148         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1149         intr_handle = &pci_dev->intr_handle;
1150
1151         rte_eth_copy_pci_info(dev, pci_dev);
1152
1153         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1154         pf->adapter->eth_dev = dev;
1155         pf->dev_data = dev->data;
1156
1157         hw->back = I40E_PF_TO_ADAPTER(pf);
1158         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1159         if (!hw->hw_addr) {
1160                 PMD_INIT_LOG(ERR,
1161                         "Hardware is not available, as address is NULL");
1162                 return -ENODEV;
1163         }
1164
1165         hw->vendor_id = pci_dev->id.vendor_id;
1166         hw->device_id = pci_dev->id.device_id;
1167         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1168         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1169         hw->bus.device = pci_dev->addr.devid;
1170         hw->bus.func = pci_dev->addr.function;
1171         hw->adapter_stopped = 0;
1172
1173         /* Check if need to support multi-driver */
1174         i40e_support_multi_driver(dev);
1175
1176         /* Make sure all is clean before doing PF reset */
1177         i40e_clear_hw(hw);
1178
1179         /* Initialize the hardware */
1180         i40e_hw_init(dev);
1181
1182         /* Reset here to make sure all is clean for each PF */
1183         ret = i40e_pf_reset(hw);
1184         if (ret) {
1185                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1186                 return ret;
1187         }
1188
1189         /* Initialize the shared code (base driver) */
1190         ret = i40e_init_shared_code(hw);
1191         if (ret) {
1192                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1193                 return ret;
1194         }
1195
1196         i40e_config_automask(pf);
1197
1198         i40e_set_default_pctype_table(dev);
1199
1200         /*
1201          * To work around the NVM issue, initialize registers
1202          * for packet type of QinQ by software.
1203          * It should be removed once issues are fixed in NVM.
1204          */
1205         if (!pf->support_multi_driver)
1206                 i40e_GLQF_reg_init(hw);
1207
1208         /* Initialize the input set for filters (hash and fd) to default value */
1209         i40e_filter_input_set_init(pf);
1210
1211         /* Initialize the parameters for adminq */
1212         i40e_init_adminq_parameter(hw);
1213         ret = i40e_init_adminq(hw);
1214         if (ret != I40E_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1216                 return -EIO;
1217         }
1218         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1219                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1220                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1221                      ((hw->nvm.version >> 12) & 0xf),
1222                      ((hw->nvm.version >> 4) & 0xff),
1223                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1224
1225         /* initialise the L3_MAP register */
1226         if (!pf->support_multi_driver) {
1227                 ret = i40e_aq_debug_write_register(hw, I40E_GLQF_L3_MAP(40),
1228                                                    0x00000028,  NULL);
1229                 if (ret)
1230                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1231                                      ret);
1232                 PMD_INIT_LOG(DEBUG,
1233                              "Global register 0x%08x is changed with 0x28",
1234                              I40E_GLQF_L3_MAP(40));
1235                 i40e_global_cfg_warning(I40E_WARNING_QINQ_CLOUD_FILTER);
1236         }
1237
1238         /* Need the special FW version to support floating VEB */
1239         config_floating_veb(dev);
1240         /* Clear PXE mode */
1241         i40e_clear_pxe_mode(hw);
1242         i40e_dev_sync_phy_type(hw);
1243
1244         /*
1245          * On X710, performance number is far from the expectation on recent
1246          * firmware versions. The fix for this issue may not be integrated in
1247          * the following firmware version. So the workaround in software driver
1248          * is needed. It needs to modify the initial values of 3 internal only
1249          * registers. Note that the workaround can be removed when it is fixed
1250          * in firmware in the future.
1251          */
1252         i40e_configure_registers(hw);
1253
1254         /* Get hw capabilities */
1255         ret = i40e_get_cap(hw);
1256         if (ret != I40E_SUCCESS) {
1257                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1258                 goto err_get_capabilities;
1259         }
1260
1261         /* Initialize parameters for PF */
1262         ret = i40e_pf_parameter_init(dev);
1263         if (ret != 0) {
1264                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1265                 goto err_parameter_init;
1266         }
1267
1268         /* Initialize the queue management */
1269         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1270         if (ret < 0) {
1271                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1272                 goto err_qp_pool_init;
1273         }
1274         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1275                                 hw->func_caps.num_msix_vectors - 1);
1276         if (ret < 0) {
1277                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1278                 goto err_msix_pool_init;
1279         }
1280
1281         /* Initialize lan hmc */
1282         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1283                                 hw->func_caps.num_rx_qp, 0, 0);
1284         if (ret != I40E_SUCCESS) {
1285                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1286                 goto err_init_lan_hmc;
1287         }
1288
1289         /* Configure lan hmc */
1290         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1291         if (ret != I40E_SUCCESS) {
1292                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1293                 goto err_configure_lan_hmc;
1294         }
1295
1296         /* Get and check the mac address */
1297         i40e_get_mac_addr(hw, hw->mac.addr);
1298         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1299                 PMD_INIT_LOG(ERR, "mac address is not valid");
1300                 ret = -EIO;
1301                 goto err_get_mac_addr;
1302         }
1303         /* Copy the permanent MAC address */
1304         ether_addr_copy((struct ether_addr *) hw->mac.addr,
1305                         (struct ether_addr *) hw->mac.perm_addr);
1306
1307         /* Disable flow control */
1308         hw->fc.requested_mode = I40E_FC_NONE;
1309         i40e_set_fc(hw, &aq_fail, TRUE);
1310
1311         /* Set the global registers with default ether type value */
1312         if (!pf->support_multi_driver) {
1313                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1314                                          ETHER_TYPE_VLAN);
1315                 if (ret != I40E_SUCCESS) {
1316                         PMD_INIT_LOG(ERR,
1317                                      "Failed to set the default outer "
1318                                      "VLAN ether type");
1319                         goto err_setup_pf_switch;
1320                 }
1321         }
1322
1323         /* PF setup, which includes VSI setup */
1324         ret = i40e_pf_setup(pf);
1325         if (ret) {
1326                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1327                 goto err_setup_pf_switch;
1328         }
1329
1330         /* reset all stats of the device, including pf and main vsi */
1331         i40e_dev_stats_reset(dev);
1332
1333         vsi = pf->main_vsi;
1334
1335         /* Disable double vlan by default */
1336         i40e_vsi_config_double_vlan(vsi, FALSE);
1337
1338         /* Disable S-TAG identification when floating_veb is disabled */
1339         if (!pf->floating_veb) {
1340                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1341                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1342                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1343                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1344                 }
1345         }
1346
1347         if (!vsi->max_macaddrs)
1348                 len = ETHER_ADDR_LEN;
1349         else
1350                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
1351
1352         /* Should be after VSI initialized */
1353         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1354         if (!dev->data->mac_addrs) {
1355                 PMD_INIT_LOG(ERR,
1356                         "Failed to allocated memory for storing mac address");
1357                 goto err_mac_alloc;
1358         }
1359         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
1360                                         &dev->data->mac_addrs[0]);
1361
1362         /* Init dcb to sw mode by default */
1363         ret = i40e_dcb_init_configure(dev, TRUE);
1364         if (ret != I40E_SUCCESS) {
1365                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1366                 pf->flags &= ~I40E_FLAG_DCB;
1367         }
1368         /* Update HW struct after DCB configuration */
1369         i40e_get_cap(hw);
1370
1371         /* initialize pf host driver to setup SRIOV resource if applicable */
1372         i40e_pf_host_init(dev);
1373
1374         /* register callback func to eal lib */
1375         rte_intr_callback_register(intr_handle,
1376                                    i40e_dev_interrupt_handler, dev);
1377
1378         /* configure and enable device interrupt */
1379         i40e_pf_config_irq0(hw, TRUE);
1380         i40e_pf_enable_irq0(hw);
1381
1382         /* enable uio intr after callback register */
1383         rte_intr_enable(intr_handle);
1384
1385         /* By default disable flexible payload in global configuration */
1386         if (!pf->support_multi_driver)
1387                 i40e_flex_payload_reg_set_default(hw);
1388
1389         /*
1390          * Add an ethertype filter to drop all flow control frames transmitted
1391          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1392          * frames to wire.
1393          */
1394         i40e_add_tx_flow_control_drop_filter(pf);
1395
1396         /* Set the max frame size to 0x2600 by default,
1397          * in case other drivers changed the default value.
1398          */
1399         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1400
1401         /* initialize mirror rule list */
1402         TAILQ_INIT(&pf->mirror_list);
1403
1404         /* initialize Traffic Manager configuration */
1405         i40e_tm_conf_init(dev);
1406
1407         /* Initialize customized information */
1408         i40e_init_customized_info(pf);
1409
1410         ret = i40e_init_ethtype_filter_list(dev);
1411         if (ret < 0)
1412                 goto err_init_ethtype_filter_list;
1413         ret = i40e_init_tunnel_filter_list(dev);
1414         if (ret < 0)
1415                 goto err_init_tunnel_filter_list;
1416         ret = i40e_init_fdir_filter_list(dev);
1417         if (ret < 0)
1418                 goto err_init_fdir_filter_list;
1419
1420         /* initialize queue region configuration */
1421         i40e_init_queue_region_conf(dev);
1422
1423         /* initialize rss configuration from rte_flow */
1424         memset(&pf->rss_info, 0,
1425                 sizeof(struct i40e_rte_flow_rss_conf));
1426
1427         return 0;
1428
1429 err_init_fdir_filter_list:
1430         rte_free(pf->tunnel.hash_table);
1431         rte_free(pf->tunnel.hash_map);
1432 err_init_tunnel_filter_list:
1433         rte_free(pf->ethertype.hash_table);
1434         rte_free(pf->ethertype.hash_map);
1435 err_init_ethtype_filter_list:
1436         rte_free(dev->data->mac_addrs);
1437 err_mac_alloc:
1438         i40e_vsi_release(pf->main_vsi);
1439 err_setup_pf_switch:
1440 err_get_mac_addr:
1441 err_configure_lan_hmc:
1442         (void)i40e_shutdown_lan_hmc(hw);
1443 err_init_lan_hmc:
1444         i40e_res_pool_destroy(&pf->msix_pool);
1445 err_msix_pool_init:
1446         i40e_res_pool_destroy(&pf->qp_pool);
1447 err_qp_pool_init:
1448 err_parameter_init:
1449 err_get_capabilities:
1450         (void)i40e_shutdown_adminq(hw);
1451
1452         return ret;
1453 }
1454
1455 static void
1456 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1457 {
1458         struct i40e_ethertype_filter *p_ethertype;
1459         struct i40e_ethertype_rule *ethertype_rule;
1460
1461         ethertype_rule = &pf->ethertype;
1462         /* Remove all ethertype filter rules and hash */
1463         if (ethertype_rule->hash_map)
1464                 rte_free(ethertype_rule->hash_map);
1465         if (ethertype_rule->hash_table)
1466                 rte_hash_free(ethertype_rule->hash_table);
1467
1468         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1469                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1470                              p_ethertype, rules);
1471                 rte_free(p_ethertype);
1472         }
1473 }
1474
1475 static void
1476 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1477 {
1478         struct i40e_tunnel_filter *p_tunnel;
1479         struct i40e_tunnel_rule *tunnel_rule;
1480
1481         tunnel_rule = &pf->tunnel;
1482         /* Remove all tunnel director rules and hash */
1483         if (tunnel_rule->hash_map)
1484                 rte_free(tunnel_rule->hash_map);
1485         if (tunnel_rule->hash_table)
1486                 rte_hash_free(tunnel_rule->hash_table);
1487
1488         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1489                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1490                 rte_free(p_tunnel);
1491         }
1492 }
1493
1494 static void
1495 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1496 {
1497         struct i40e_fdir_filter *p_fdir;
1498         struct i40e_fdir_info *fdir_info;
1499
1500         fdir_info = &pf->fdir;
1501         /* Remove all flow director rules and hash */
1502         if (fdir_info->hash_map)
1503                 rte_free(fdir_info->hash_map);
1504         if (fdir_info->hash_table)
1505                 rte_hash_free(fdir_info->hash_table);
1506
1507         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1508                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1509                 rte_free(p_fdir);
1510         }
1511 }
1512
1513 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1514 {
1515         /*
1516          * Disable by default flexible payload
1517          * for corresponding L2/L3/L4 layers.
1518          */
1519         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1520         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1521         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1522         i40e_global_cfg_warning(I40E_WARNING_DIS_FLX_PLD);
1523 }
1524
1525 static int
1526 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1527 {
1528         struct i40e_pf *pf;
1529         struct rte_pci_device *pci_dev;
1530         struct rte_intr_handle *intr_handle;
1531         struct i40e_hw *hw;
1532         struct i40e_filter_control_settings settings;
1533         struct rte_flow *p_flow;
1534         int ret;
1535         uint8_t aq_fail = 0;
1536
1537         PMD_INIT_FUNC_TRACE();
1538
1539         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1540                 return 0;
1541
1542         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1543         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1544         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1545         intr_handle = &pci_dev->intr_handle;
1546
1547         if (hw->adapter_stopped == 0)
1548                 i40e_dev_close(dev);
1549
1550         dev->dev_ops = NULL;
1551         dev->rx_pkt_burst = NULL;
1552         dev->tx_pkt_burst = NULL;
1553
1554         /* Clear PXE mode */
1555         i40e_clear_pxe_mode(hw);
1556
1557         /* Unconfigure filter control */
1558         memset(&settings, 0, sizeof(settings));
1559         ret = i40e_set_filter_control(hw, &settings);
1560         if (ret)
1561                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1562                                         ret);
1563
1564         /* Disable flow control */
1565         hw->fc.requested_mode = I40E_FC_NONE;
1566         i40e_set_fc(hw, &aq_fail, TRUE);
1567
1568         /* uninitialize pf host driver */
1569         i40e_pf_host_uninit(dev);
1570
1571         rte_free(dev->data->mac_addrs);
1572         dev->data->mac_addrs = NULL;
1573
1574         /* disable uio intr before callback unregister */
1575         rte_intr_disable(intr_handle);
1576
1577         /* register callback func to eal lib */
1578         rte_intr_callback_unregister(intr_handle,
1579                                      i40e_dev_interrupt_handler, dev);
1580
1581         i40e_rm_ethtype_filter_list(pf);
1582         i40e_rm_tunnel_filter_list(pf);
1583         i40e_rm_fdir_filter_list(pf);
1584
1585         /* Remove all flows */
1586         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1587                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1588                 rte_free(p_flow);
1589         }
1590
1591         /* Remove all Traffic Manager configuration */
1592         i40e_tm_conf_uninit(dev);
1593
1594         return 0;
1595 }
1596
1597 static int
1598 i40e_dev_configure(struct rte_eth_dev *dev)
1599 {
1600         struct i40e_adapter *ad =
1601                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1602         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1603         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1604         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1605         int i, ret;
1606
1607         ret = i40e_dev_sync_phy_type(hw);
1608         if (ret)
1609                 return ret;
1610
1611         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1612          * bulk allocation or vector Rx preconditions we will reset it.
1613          */
1614         ad->rx_bulk_alloc_allowed = true;
1615         ad->rx_vec_allowed = true;
1616         ad->tx_simple_allowed = true;
1617         ad->tx_vec_allowed = true;
1618
1619         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1620                 ret = i40e_fdir_setup(pf);
1621                 if (ret != I40E_SUCCESS) {
1622                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1623                         return -ENOTSUP;
1624                 }
1625                 ret = i40e_fdir_configure(dev);
1626                 if (ret < 0) {
1627                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1628                         goto err;
1629                 }
1630         } else
1631                 i40e_fdir_teardown(pf);
1632
1633         ret = i40e_dev_init_vlan(dev);
1634         if (ret < 0)
1635                 goto err;
1636
1637         /* VMDQ setup.
1638          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1639          *  RSS setting have different requirements.
1640          *  General PMD driver call sequence are NIC init, configure,
1641          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1642          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1643          *  applicable. So, VMDQ setting has to be done before
1644          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1645          *  For RSS setting, it will try to calculate actual configured RX queue
1646          *  number, which will be available after rx_queue_setup(). dev_start()
1647          *  function is good to place RSS setup.
1648          */
1649         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1650                 ret = i40e_vmdq_setup(dev);
1651                 if (ret)
1652                         goto err;
1653         }
1654
1655         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1656                 ret = i40e_dcb_setup(dev);
1657                 if (ret) {
1658                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1659                         goto err_dcb;
1660                 }
1661         }
1662
1663         TAILQ_INIT(&pf->flow_list);
1664
1665         return 0;
1666
1667 err_dcb:
1668         /* need to release vmdq resource if exists */
1669         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1670                 i40e_vsi_release(pf->vmdq[i].vsi);
1671                 pf->vmdq[i].vsi = NULL;
1672         }
1673         rte_free(pf->vmdq);
1674         pf->vmdq = NULL;
1675 err:
1676         /* need to release fdir resource if exists */
1677         i40e_fdir_teardown(pf);
1678         return ret;
1679 }
1680
1681 void
1682 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1683 {
1684         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1685         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1686         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1687         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1688         uint16_t msix_vect = vsi->msix_intr;
1689         uint16_t i;
1690
1691         for (i = 0; i < vsi->nb_qps; i++) {
1692                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1693                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1694                 rte_wmb();
1695         }
1696
1697         if (vsi->type != I40E_VSI_SRIOV) {
1698                 if (!rte_intr_allow_others(intr_handle)) {
1699                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1700                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1701                         I40E_WRITE_REG(hw,
1702                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1703                                        0);
1704                 } else {
1705                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1706                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1707                         I40E_WRITE_REG(hw,
1708                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1709                                                        msix_vect - 1), 0);
1710                 }
1711         } else {
1712                 uint32_t reg;
1713                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1714                         vsi->user_param + (msix_vect - 1);
1715
1716                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1717                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1718         }
1719         I40E_WRITE_FLUSH(hw);
1720 }
1721
1722 static void
1723 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1724                        int base_queue, int nb_queue,
1725                        uint16_t itr_idx)
1726 {
1727         int i;
1728         uint32_t val;
1729         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1730         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1731
1732         /* Bind all RX queues to allocated MSIX interrupt */
1733         for (i = 0; i < nb_queue; i++) {
1734                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1735                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1736                         ((base_queue + i + 1) <<
1737                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1738                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1739                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1740
1741                 if (i == nb_queue - 1)
1742                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1743                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1744         }
1745
1746         /* Write first RX queue to Link list register as the head element */
1747         if (vsi->type != I40E_VSI_SRIOV) {
1748                 uint16_t interval =
1749                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL, 1,
1750                                                pf->support_multi_driver);
1751
1752                 if (msix_vect == I40E_MISC_VEC_ID) {
1753                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1754                                        (base_queue <<
1755                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1756                                        (0x0 <<
1757                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1758                         I40E_WRITE_REG(hw,
1759                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1760                                        interval);
1761                 } else {
1762                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1763                                        (base_queue <<
1764                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1765                                        (0x0 <<
1766                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1767                         I40E_WRITE_REG(hw,
1768                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1769                                                        msix_vect - 1),
1770                                        interval);
1771                 }
1772         } else {
1773                 uint32_t reg;
1774
1775                 if (msix_vect == I40E_MISC_VEC_ID) {
1776                         I40E_WRITE_REG(hw,
1777                                        I40E_VPINT_LNKLST0(vsi->user_param),
1778                                        (base_queue <<
1779                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1780                                        (0x0 <<
1781                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1782                 } else {
1783                         /* num_msix_vectors_vf needs to minus irq0 */
1784                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1785                                 vsi->user_param + (msix_vect - 1);
1786
1787                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1788                                        (base_queue <<
1789                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1790                                        (0x0 <<
1791                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1792                 }
1793         }
1794
1795         I40E_WRITE_FLUSH(hw);
1796 }
1797
1798 void
1799 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1800 {
1801         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1802         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1803         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1804         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1805         uint16_t msix_vect = vsi->msix_intr;
1806         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1807         uint16_t queue_idx = 0;
1808         int record = 0;
1809         int i;
1810
1811         for (i = 0; i < vsi->nb_qps; i++) {
1812                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1813                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1814         }
1815
1816         /* VF bind interrupt */
1817         if (vsi->type == I40E_VSI_SRIOV) {
1818                 __vsi_queues_bind_intr(vsi, msix_vect,
1819                                        vsi->base_queue, vsi->nb_qps,
1820                                        itr_idx);
1821                 return;
1822         }
1823
1824         /* PF & VMDq bind interrupt */
1825         if (rte_intr_dp_is_en(intr_handle)) {
1826                 if (vsi->type == I40E_VSI_MAIN) {
1827                         queue_idx = 0;
1828                         record = 1;
1829                 } else if (vsi->type == I40E_VSI_VMDQ2) {
1830                         struct i40e_vsi *main_vsi =
1831                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
1832                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
1833                         record = 1;
1834                 }
1835         }
1836
1837         for (i = 0; i < vsi->nb_used_qps; i++) {
1838                 if (nb_msix <= 1) {
1839                         if (!rte_intr_allow_others(intr_handle))
1840                                 /* allow to share MISC_VEC_ID */
1841                                 msix_vect = I40E_MISC_VEC_ID;
1842
1843                         /* no enough msix_vect, map all to one */
1844                         __vsi_queues_bind_intr(vsi, msix_vect,
1845                                                vsi->base_queue + i,
1846                                                vsi->nb_used_qps - i,
1847                                                itr_idx);
1848                         for (; !!record && i < vsi->nb_used_qps; i++)
1849                                 intr_handle->intr_vec[queue_idx + i] =
1850                                         msix_vect;
1851                         break;
1852                 }
1853                 /* 1:1 queue/msix_vect mapping */
1854                 __vsi_queues_bind_intr(vsi, msix_vect,
1855                                        vsi->base_queue + i, 1,
1856                                        itr_idx);
1857                 if (!!record)
1858                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1859
1860                 msix_vect++;
1861                 nb_msix--;
1862         }
1863 }
1864
1865 static void
1866 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
1867 {
1868         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1869         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1870         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1871         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1872         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1873         uint16_t msix_intr, i;
1874
1875         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1876                 for (i = 0; i < vsi->nb_msix; i++) {
1877                         msix_intr = vsi->msix_intr + i;
1878                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1879                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
1880                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
1881                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1882                 }
1883         else
1884                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1885                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
1886                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
1887                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1888
1889         I40E_WRITE_FLUSH(hw);
1890 }
1891
1892 static void
1893 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
1894 {
1895         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1896         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1897         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1898         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1899         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1900         uint16_t msix_intr, i;
1901
1902         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
1903                 for (i = 0; i < vsi->nb_msix; i++) {
1904                         msix_intr = vsi->msix_intr + i;
1905                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
1906                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
1907                 }
1908         else
1909                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
1910                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
1911
1912         I40E_WRITE_FLUSH(hw);
1913 }
1914
1915 static inline uint8_t
1916 i40e_parse_link_speeds(uint16_t link_speeds)
1917 {
1918         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
1919
1920         if (link_speeds & ETH_LINK_SPEED_40G)
1921                 link_speed |= I40E_LINK_SPEED_40GB;
1922         if (link_speeds & ETH_LINK_SPEED_25G)
1923                 link_speed |= I40E_LINK_SPEED_25GB;
1924         if (link_speeds & ETH_LINK_SPEED_20G)
1925                 link_speed |= I40E_LINK_SPEED_20GB;
1926         if (link_speeds & ETH_LINK_SPEED_10G)
1927                 link_speed |= I40E_LINK_SPEED_10GB;
1928         if (link_speeds & ETH_LINK_SPEED_1G)
1929                 link_speed |= I40E_LINK_SPEED_1GB;
1930         if (link_speeds & ETH_LINK_SPEED_100M)
1931                 link_speed |= I40E_LINK_SPEED_100MB;
1932
1933         return link_speed;
1934 }
1935
1936 static int
1937 i40e_phy_conf_link(struct i40e_hw *hw,
1938                    uint8_t abilities,
1939                    uint8_t force_speed,
1940                    bool is_up)
1941 {
1942         enum i40e_status_code status;
1943         struct i40e_aq_get_phy_abilities_resp phy_ab;
1944         struct i40e_aq_set_phy_config phy_conf;
1945         enum i40e_aq_phy_type cnt;
1946         uint32_t phy_type_mask = 0;
1947
1948         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
1949                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1950                         I40E_AQ_PHY_FLAG_PAUSE_RX |
1951                         I40E_AQ_PHY_FLAG_LOW_POWER;
1952         const uint8_t advt = I40E_LINK_SPEED_40GB |
1953                         I40E_LINK_SPEED_25GB |
1954                         I40E_LINK_SPEED_10GB |
1955                         I40E_LINK_SPEED_1GB |
1956                         I40E_LINK_SPEED_100MB;
1957         int ret = -ENOTSUP;
1958
1959
1960         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
1961                                               NULL);
1962         if (status)
1963                 return ret;
1964
1965         /* If link already up, no need to set up again */
1966         if (is_up && phy_ab.phy_type != 0)
1967                 return I40E_SUCCESS;
1968
1969         memset(&phy_conf, 0, sizeof(phy_conf));
1970
1971         /* bits 0-2 use the values from get_phy_abilities_resp */
1972         abilities &= ~mask;
1973         abilities |= phy_ab.abilities & mask;
1974
1975         /* update ablities and speed */
1976         if (abilities & I40E_AQ_PHY_AN_ENABLED)
1977                 phy_conf.link_speed = advt;
1978         else
1979                 phy_conf.link_speed = is_up ? force_speed : phy_ab.link_speed;
1980
1981         phy_conf.abilities = abilities;
1982
1983
1984
1985         /* To enable link, phy_type mask needs to include each type */
1986         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_MAX; cnt++)
1987                 phy_type_mask |= 1 << cnt;
1988
1989         /* use get_phy_abilities_resp value for the rest */
1990         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
1991         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
1992                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
1993                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
1994         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
1995         phy_conf.eee_capability = phy_ab.eee_capability;
1996         phy_conf.eeer = phy_ab.eeer_val;
1997         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
1998
1999         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2000                     phy_ab.abilities, phy_ab.link_speed);
2001         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2002                     phy_conf.abilities, phy_conf.link_speed);
2003
2004         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2005         if (status)
2006                 return ret;
2007
2008         return I40E_SUCCESS;
2009 }
2010
2011 static int
2012 i40e_apply_link_speed(struct rte_eth_dev *dev)
2013 {
2014         uint8_t speed;
2015         uint8_t abilities = 0;
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         struct rte_eth_conf *conf = &dev->data->dev_conf;
2018
2019         speed = i40e_parse_link_speeds(conf->link_speeds);
2020         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2021         if (!(conf->link_speeds & ETH_LINK_SPEED_FIXED))
2022                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2023         abilities |= I40E_AQ_PHY_LINK_ENABLED;
2024
2025         return i40e_phy_conf_link(hw, abilities, speed, true);
2026 }
2027
2028 static int
2029 i40e_dev_start(struct rte_eth_dev *dev)
2030 {
2031         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2032         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2033         struct i40e_vsi *main_vsi = pf->main_vsi;
2034         int ret, i;
2035         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2036         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2037         uint32_t intr_vector = 0;
2038         struct i40e_vsi *vsi;
2039
2040         hw->adapter_stopped = 0;
2041
2042         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2043                 PMD_INIT_LOG(ERR,
2044                 "Invalid link_speeds for port %u, autonegotiation disabled",
2045                               dev->data->port_id);
2046                 return -EINVAL;
2047         }
2048
2049         rte_intr_disable(intr_handle);
2050
2051         if ((rte_intr_cap_multiple(intr_handle) ||
2052              !RTE_ETH_DEV_SRIOV(dev).active) &&
2053             dev->data->dev_conf.intr_conf.rxq != 0) {
2054                 intr_vector = dev->data->nb_rx_queues;
2055                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2056                 if (ret)
2057                         return ret;
2058         }
2059
2060         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2061                 intr_handle->intr_vec =
2062                         rte_zmalloc("intr_vec",
2063                                     dev->data->nb_rx_queues * sizeof(int),
2064                                     0);
2065                 if (!intr_handle->intr_vec) {
2066                         PMD_INIT_LOG(ERR,
2067                                 "Failed to allocate %d rx_queues intr_vec",
2068                                 dev->data->nb_rx_queues);
2069                         return -ENOMEM;
2070                 }
2071         }
2072
2073         /* Initialize VSI */
2074         ret = i40e_dev_rxtx_init(pf);
2075         if (ret != I40E_SUCCESS) {
2076                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2077                 goto err_up;
2078         }
2079
2080         /* Map queues with MSIX interrupt */
2081         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2082                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2083         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2084         i40e_vsi_enable_queues_intr(main_vsi);
2085
2086         /* Map VMDQ VSI queues with MSIX interrupt */
2087         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2088                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2089                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2090                                           I40E_ITR_INDEX_DEFAULT);
2091                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2092         }
2093
2094         /* enable FDIR MSIX interrupt */
2095         if (pf->fdir.fdir_vsi) {
2096                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2097                                           I40E_ITR_INDEX_NONE);
2098                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2099         }
2100
2101         /* Enable all queues which have been configured */
2102         ret = i40e_dev_switch_queues(pf, TRUE);
2103         if (ret != I40E_SUCCESS) {
2104                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2105                 goto err_up;
2106         }
2107
2108         /* Enable receiving broadcast packets */
2109         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2110         if (ret != I40E_SUCCESS)
2111                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2112
2113         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2114                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2115                                                 true, NULL);
2116                 if (ret != I40E_SUCCESS)
2117                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2118         }
2119
2120         /* Enable the VLAN promiscuous mode. */
2121         if (pf->vfs) {
2122                 for (i = 0; i < pf->vf_num; i++) {
2123                         vsi = pf->vfs[i].vsi;
2124                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2125                                                      true, NULL);
2126                 }
2127         }
2128
2129         /* Enable mac loopback mode */
2130         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2131             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2132                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2133                 if (ret != I40E_SUCCESS) {
2134                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2135                         goto err_up;
2136                 }
2137         }
2138
2139         /* Apply link configure */
2140         if (dev->data->dev_conf.link_speeds & ~(ETH_LINK_SPEED_100M |
2141                                 ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G |
2142                                 ETH_LINK_SPEED_20G | ETH_LINK_SPEED_25G |
2143                                 ETH_LINK_SPEED_40G)) {
2144                 PMD_DRV_LOG(ERR, "Invalid link setting");
2145                 goto err_up;
2146         }
2147         ret = i40e_apply_link_speed(dev);
2148         if (I40E_SUCCESS != ret) {
2149                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2150                 goto err_up;
2151         }
2152
2153         if (!rte_intr_allow_others(intr_handle)) {
2154                 rte_intr_callback_unregister(intr_handle,
2155                                              i40e_dev_interrupt_handler,
2156                                              (void *)dev);
2157                 /* configure and enable device interrupt */
2158                 i40e_pf_config_irq0(hw, FALSE);
2159                 i40e_pf_enable_irq0(hw);
2160
2161                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2162                         PMD_INIT_LOG(INFO,
2163                                 "lsc won't enable because of no intr multiplex");
2164         } else {
2165                 ret = i40e_aq_set_phy_int_mask(hw,
2166                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2167                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2168                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2169                 if (ret != I40E_SUCCESS)
2170                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2171
2172                 /* Call get_link_info aq commond to enable/disable LSE */
2173                 i40e_dev_link_update(dev, 0);
2174         }
2175
2176         /* enable uio intr after callback register */
2177         rte_intr_enable(intr_handle);
2178
2179         i40e_filter_restore(pf);
2180
2181         if (pf->tm_conf.root && !pf->tm_conf.committed)
2182                 PMD_DRV_LOG(WARNING,
2183                             "please call hierarchy_commit() "
2184                             "before starting the port");
2185
2186         return I40E_SUCCESS;
2187
2188 err_up:
2189         i40e_dev_switch_queues(pf, FALSE);
2190         i40e_dev_clear_queues(dev);
2191
2192         return ret;
2193 }
2194
2195 static void
2196 i40e_dev_stop(struct rte_eth_dev *dev)
2197 {
2198         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2200         struct i40e_vsi *main_vsi = pf->main_vsi;
2201         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2202         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2203         int i;
2204
2205         if (hw->adapter_stopped == 1)
2206                 return;
2207         /* Disable all queues */
2208         i40e_dev_switch_queues(pf, FALSE);
2209
2210         /* un-map queues with interrupt registers */
2211         i40e_vsi_disable_queues_intr(main_vsi);
2212         i40e_vsi_queues_unbind_intr(main_vsi);
2213
2214         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2215                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2216                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2217         }
2218
2219         if (pf->fdir.fdir_vsi) {
2220                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2221                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2222         }
2223         /* Clear all queues and release memory */
2224         i40e_dev_clear_queues(dev);
2225
2226         /* Set link down */
2227         i40e_dev_set_link_down(dev);
2228
2229         if (!rte_intr_allow_others(intr_handle))
2230                 /* resume to the default handler */
2231                 rte_intr_callback_register(intr_handle,
2232                                            i40e_dev_interrupt_handler,
2233                                            (void *)dev);
2234
2235         /* Clean datapath event and queue/vec mapping */
2236         rte_intr_efd_disable(intr_handle);
2237         if (intr_handle->intr_vec) {
2238                 rte_free(intr_handle->intr_vec);
2239                 intr_handle->intr_vec = NULL;
2240         }
2241
2242         /* reset hierarchy commit */
2243         pf->tm_conf.committed = false;
2244
2245         hw->adapter_stopped = 1;
2246 }
2247
2248 static void
2249 i40e_dev_close(struct rte_eth_dev *dev)
2250 {
2251         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2252         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2253         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2254         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2255         struct i40e_mirror_rule *p_mirror;
2256         uint32_t reg;
2257         int i;
2258         int ret;
2259
2260         PMD_INIT_FUNC_TRACE();
2261
2262         i40e_dev_stop(dev);
2263
2264         /* Remove all mirror rules */
2265         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2266                 ret = i40e_aq_del_mirror_rule(hw,
2267                                               pf->main_vsi->veb->seid,
2268                                               p_mirror->rule_type,
2269                                               p_mirror->entries,
2270                                               p_mirror->num_entries,
2271                                               p_mirror->id);
2272                 if (ret < 0)
2273                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2274                                     "status = %d, aq_err = %d.", ret,
2275                                     hw->aq.asq_last_status);
2276
2277                 /* remove mirror software resource anyway */
2278                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2279                 rte_free(p_mirror);
2280                 pf->nb_mirror_rule--;
2281         }
2282
2283         i40e_dev_free_queues(dev);
2284
2285         /* Disable interrupt */
2286         i40e_pf_disable_irq0(hw);
2287         rte_intr_disable(intr_handle);
2288
2289         /* shutdown and destroy the HMC */
2290         i40e_shutdown_lan_hmc(hw);
2291
2292         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2293                 i40e_vsi_release(pf->vmdq[i].vsi);
2294                 pf->vmdq[i].vsi = NULL;
2295         }
2296         rte_free(pf->vmdq);
2297         pf->vmdq = NULL;
2298
2299         /* release all the existing VSIs and VEBs */
2300         i40e_fdir_teardown(pf);
2301         i40e_vsi_release(pf->main_vsi);
2302
2303         /* shutdown the adminq */
2304         i40e_aq_queue_shutdown(hw, true);
2305         i40e_shutdown_adminq(hw);
2306
2307         i40e_res_pool_destroy(&pf->qp_pool);
2308         i40e_res_pool_destroy(&pf->msix_pool);
2309
2310         /* Disable flexible payload in global configuration */
2311         if (!pf->support_multi_driver)
2312                 i40e_flex_payload_reg_set_default(hw);
2313
2314         /* force a PF reset to clean anything leftover */
2315         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2316         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2317                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2318         I40E_WRITE_FLUSH(hw);
2319 }
2320
2321 /*
2322  * Reset PF device only to re-initialize resources in PMD layer
2323  */
2324 static int
2325 i40e_dev_reset(struct rte_eth_dev *dev)
2326 {
2327         int ret;
2328
2329         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2330          * its VF to make them align with it. The detailed notification
2331          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2332          * To avoid unexpected behavior in VF, currently reset of PF with
2333          * SR-IOV activation is not supported. It might be supported later.
2334          */
2335         if (dev->data->sriov.active)
2336                 return -ENOTSUP;
2337
2338         ret = eth_i40e_dev_uninit(dev);
2339         if (ret)
2340                 return ret;
2341
2342         ret = eth_i40e_dev_init(dev);
2343
2344         return ret;
2345 }
2346
2347 static void
2348 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2349 {
2350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2351         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2352         struct i40e_vsi *vsi = pf->main_vsi;
2353         int status;
2354
2355         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2356                                                      true, NULL, true);
2357         if (status != I40E_SUCCESS)
2358                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2359
2360         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2361                                                         TRUE, NULL);
2362         if (status != I40E_SUCCESS)
2363                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2364
2365 }
2366
2367 static void
2368 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2369 {
2370         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2371         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2372         struct i40e_vsi *vsi = pf->main_vsi;
2373         int status;
2374
2375         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2376                                                      false, NULL, true);
2377         if (status != I40E_SUCCESS)
2378                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2379
2380         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2381                                                         false, NULL);
2382         if (status != I40E_SUCCESS)
2383                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2384 }
2385
2386 static void
2387 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2388 {
2389         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2390         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2391         struct i40e_vsi *vsi = pf->main_vsi;
2392         int ret;
2393
2394         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2395         if (ret != I40E_SUCCESS)
2396                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2397 }
2398
2399 static void
2400 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2401 {
2402         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2403         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2404         struct i40e_vsi *vsi = pf->main_vsi;
2405         int ret;
2406
2407         if (dev->data->promiscuous == 1)
2408                 return; /* must remain in all_multicast mode */
2409
2410         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2411                                 vsi->seid, FALSE, NULL);
2412         if (ret != I40E_SUCCESS)
2413                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2414 }
2415
2416 /*
2417  * Set device link up.
2418  */
2419 static int
2420 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2421 {
2422         /* re-apply link speed setting */
2423         return i40e_apply_link_speed(dev);
2424 }
2425
2426 /*
2427  * Set device link down.
2428  */
2429 static int
2430 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2431 {
2432         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2433         uint8_t abilities = 0;
2434         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2435
2436         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2437         return i40e_phy_conf_link(hw, abilities, speed, false);
2438 }
2439
2440 static __rte_always_inline void
2441 update_link_no_wait(struct i40e_hw *hw, struct rte_eth_link *link)
2442 {
2443 /* Link status registers and values*/
2444 #define I40E_PRTMAC_LINKSTA             0x001E2420
2445 #define I40E_REG_LINK_UP                0x40000080
2446 #define I40E_PRTMAC_MACC                0x001E24E0
2447 #define I40E_REG_MACC_25GB              0x00020000
2448 #define I40E_REG_SPEED_MASK             0x38000000
2449 #define I40E_REG_SPEED_100MB            0x00000000
2450 #define I40E_REG_SPEED_1GB              0x08000000
2451 #define I40E_REG_SPEED_10GB             0x10000000
2452 #define I40E_REG_SPEED_20GB             0x20000000
2453 #define I40E_REG_SPEED_25_40GB          0x18000000
2454         uint32_t link_speed;
2455         uint32_t reg_val;
2456
2457         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2458         link_speed = reg_val & I40E_REG_SPEED_MASK;
2459         reg_val &= I40E_REG_LINK_UP;
2460         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2461
2462         if (unlikely(link->link_status != 0))
2463                 return;
2464
2465         /* Parse the link status */
2466         switch (link_speed) {
2467         case I40E_REG_SPEED_100MB:
2468                 link->link_speed = ETH_SPEED_NUM_100M;
2469                 break;
2470         case I40E_REG_SPEED_1GB:
2471                 link->link_speed = ETH_SPEED_NUM_1G;
2472                 break;
2473         case I40E_REG_SPEED_10GB:
2474                 link->link_speed = ETH_SPEED_NUM_10G;
2475                 break;
2476         case I40E_REG_SPEED_20GB:
2477                 link->link_speed = ETH_SPEED_NUM_20G;
2478                 break;
2479         case I40E_REG_SPEED_25_40GB:
2480                 reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2481
2482                 if (reg_val & I40E_REG_MACC_25GB)
2483                         link->link_speed = ETH_SPEED_NUM_25G;
2484                 else
2485                         link->link_speed = ETH_SPEED_NUM_40G;
2486
2487                 break;
2488         default:
2489                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2490                 break;
2491         }
2492 }
2493
2494 static __rte_always_inline void
2495 update_link_wait(struct i40e_hw *hw, struct rte_eth_link *link,
2496         bool enable_lse)
2497 {
2498 #define CHECK_INTERVAL             100  /* 100ms */
2499 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2500         uint32_t rep_cnt = MAX_REPEAT_TIME;
2501         struct i40e_link_status link_status;
2502         int status;
2503
2504         memset(&link_status, 0, sizeof(link_status));
2505
2506         do {
2507                 /* Get link status information from hardware */
2508                 status = i40e_aq_get_link_info(hw, enable_lse,
2509                                                 &link_status, NULL);
2510                 if (unlikely(status != I40E_SUCCESS)) {
2511                         link->link_speed = ETH_SPEED_NUM_100M;
2512                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2513                         PMD_DRV_LOG(ERR, "Failed to get link info");
2514                         return;
2515                 }
2516
2517                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2518                 if (unlikely(link->link_status != 0))
2519                         return;
2520
2521                 rte_delay_ms(CHECK_INTERVAL);
2522         } while (--rep_cnt);
2523
2524         /* Parse the link status */
2525         switch (link_status.link_speed) {
2526         case I40E_LINK_SPEED_100MB:
2527                 link->link_speed = ETH_SPEED_NUM_100M;
2528                 break;
2529         case I40E_LINK_SPEED_1GB:
2530                 link->link_speed = ETH_SPEED_NUM_1G;
2531                 break;
2532         case I40E_LINK_SPEED_10GB:
2533                 link->link_speed = ETH_SPEED_NUM_10G;
2534                 break;
2535         case I40E_LINK_SPEED_20GB:
2536                 link->link_speed = ETH_SPEED_NUM_20G;
2537                 break;
2538         case I40E_LINK_SPEED_25GB:
2539                 link->link_speed = ETH_SPEED_NUM_25G;
2540                 break;
2541         case I40E_LINK_SPEED_40GB:
2542                 link->link_speed = ETH_SPEED_NUM_40G;
2543                 break;
2544         default:
2545                 link->link_speed = ETH_SPEED_NUM_100M;
2546                 break;
2547         }
2548 }
2549
2550 int
2551 i40e_dev_link_update(struct rte_eth_dev *dev,
2552                      int wait_to_complete)
2553 {
2554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2555         struct rte_eth_link link, old;
2556         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2557
2558         memset(&link, 0, sizeof(link));
2559         memset(&old, 0, sizeof(old));
2560
2561         rte_i40e_dev_atomic_read_link_status(dev, &old);
2562
2563         /* i40e uses full duplex only */
2564         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2565         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2566                         ETH_LINK_SPEED_FIXED);
2567
2568         if (!wait_to_complete)
2569                 update_link_no_wait(hw, &link);
2570         else
2571                 update_link_wait(hw, &link, enable_lse);
2572
2573         rte_i40e_dev_atomic_write_link_status(dev, &link);
2574         if (link.link_status == old.link_status)
2575                 return -1;
2576
2577         i40e_notify_all_vfs_link_status(dev);
2578
2579         return 0;
2580 }
2581
2582 /* Get all the statistics of a VSI */
2583 void
2584 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2585 {
2586         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2587         struct i40e_eth_stats *nes = &vsi->eth_stats;
2588         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2589         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2590
2591         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2592                             vsi->offset_loaded, &oes->rx_bytes,
2593                             &nes->rx_bytes);
2594         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2595                             vsi->offset_loaded, &oes->rx_unicast,
2596                             &nes->rx_unicast);
2597         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2598                             vsi->offset_loaded, &oes->rx_multicast,
2599                             &nes->rx_multicast);
2600         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2601                             vsi->offset_loaded, &oes->rx_broadcast,
2602                             &nes->rx_broadcast);
2603         /* exclude CRC bytes */
2604         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2605                 nes->rx_broadcast) * ETHER_CRC_LEN;
2606
2607         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2608                             &oes->rx_discards, &nes->rx_discards);
2609         /* GLV_REPC not supported */
2610         /* GLV_RMPC not supported */
2611         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2612                             &oes->rx_unknown_protocol,
2613                             &nes->rx_unknown_protocol);
2614         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2615                             vsi->offset_loaded, &oes->tx_bytes,
2616                             &nes->tx_bytes);
2617         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2618                             vsi->offset_loaded, &oes->tx_unicast,
2619                             &nes->tx_unicast);
2620         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2621                             vsi->offset_loaded, &oes->tx_multicast,
2622                             &nes->tx_multicast);
2623         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2624                             vsi->offset_loaded,  &oes->tx_broadcast,
2625                             &nes->tx_broadcast);
2626         /* GLV_TDPC not supported */
2627         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2628                             &oes->tx_errors, &nes->tx_errors);
2629         vsi->offset_loaded = true;
2630
2631         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2632                     vsi->vsi_id);
2633         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2634         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2635         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2636         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2637         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2638         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2639                     nes->rx_unknown_protocol);
2640         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2641         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2642         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2643         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2644         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2645         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2646         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2647                     vsi->vsi_id);
2648 }
2649
2650 static void
2651 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2652 {
2653         unsigned int i;
2654         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2655         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2656
2657         /* Get rx/tx bytes of internal transfer packets */
2658         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2659                         I40E_GLV_GORCL(hw->port),
2660                         pf->offset_loaded,
2661                         &pf->internal_stats_offset.rx_bytes,
2662                         &pf->internal_stats.rx_bytes);
2663
2664         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2665                         I40E_GLV_GOTCL(hw->port),
2666                         pf->offset_loaded,
2667                         &pf->internal_stats_offset.tx_bytes,
2668                         &pf->internal_stats.tx_bytes);
2669         /* Get total internal rx packet count */
2670         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2671                             I40E_GLV_UPRCL(hw->port),
2672                             pf->offset_loaded,
2673                             &pf->internal_stats_offset.rx_unicast,
2674                             &pf->internal_stats.rx_unicast);
2675         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2676                             I40E_GLV_MPRCL(hw->port),
2677                             pf->offset_loaded,
2678                             &pf->internal_stats_offset.rx_multicast,
2679                             &pf->internal_stats.rx_multicast);
2680         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2681                             I40E_GLV_BPRCL(hw->port),
2682                             pf->offset_loaded,
2683                             &pf->internal_stats_offset.rx_broadcast,
2684                             &pf->internal_stats.rx_broadcast);
2685         /* Get total internal tx packet count */
2686         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2687                             I40E_GLV_UPTCL(hw->port),
2688                             pf->offset_loaded,
2689                             &pf->internal_stats_offset.tx_unicast,
2690                             &pf->internal_stats.tx_unicast);
2691         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2692                             I40E_GLV_MPTCL(hw->port),
2693                             pf->offset_loaded,
2694                             &pf->internal_stats_offset.tx_multicast,
2695                             &pf->internal_stats.tx_multicast);
2696         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2697                             I40E_GLV_BPTCL(hw->port),
2698                             pf->offset_loaded,
2699                             &pf->internal_stats_offset.tx_broadcast,
2700                             &pf->internal_stats.tx_broadcast);
2701
2702         /* exclude CRC size */
2703         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2704                 pf->internal_stats.rx_multicast +
2705                 pf->internal_stats.rx_broadcast) * ETHER_CRC_LEN;
2706
2707         /* Get statistics of struct i40e_eth_stats */
2708         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2709                             I40E_GLPRT_GORCL(hw->port),
2710                             pf->offset_loaded, &os->eth.rx_bytes,
2711                             &ns->eth.rx_bytes);
2712         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2713                             I40E_GLPRT_UPRCL(hw->port),
2714                             pf->offset_loaded, &os->eth.rx_unicast,
2715                             &ns->eth.rx_unicast);
2716         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2717                             I40E_GLPRT_MPRCL(hw->port),
2718                             pf->offset_loaded, &os->eth.rx_multicast,
2719                             &ns->eth.rx_multicast);
2720         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2721                             I40E_GLPRT_BPRCL(hw->port),
2722                             pf->offset_loaded, &os->eth.rx_broadcast,
2723                             &ns->eth.rx_broadcast);
2724         /* Workaround: CRC size should not be included in byte statistics,
2725          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
2726          */
2727         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2728                 ns->eth.rx_broadcast) * ETHER_CRC_LEN;
2729
2730         /* exclude internal rx bytes
2731          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2732          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2733          * value.
2734          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2735          */
2736         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2737                 ns->eth.rx_bytes = 0;
2738         else
2739                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2740
2741         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2742                 ns->eth.rx_unicast = 0;
2743         else
2744                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2745
2746         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2747                 ns->eth.rx_multicast = 0;
2748         else
2749                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2750
2751         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2752                 ns->eth.rx_broadcast = 0;
2753         else
2754                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2755
2756         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2757                             pf->offset_loaded, &os->eth.rx_discards,
2758                             &ns->eth.rx_discards);
2759         /* GLPRT_REPC not supported */
2760         /* GLPRT_RMPC not supported */
2761         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2762                             pf->offset_loaded,
2763                             &os->eth.rx_unknown_protocol,
2764                             &ns->eth.rx_unknown_protocol);
2765         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2766                             I40E_GLPRT_GOTCL(hw->port),
2767                             pf->offset_loaded, &os->eth.tx_bytes,
2768                             &ns->eth.tx_bytes);
2769         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
2770                             I40E_GLPRT_UPTCL(hw->port),
2771                             pf->offset_loaded, &os->eth.tx_unicast,
2772                             &ns->eth.tx_unicast);
2773         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
2774                             I40E_GLPRT_MPTCL(hw->port),
2775                             pf->offset_loaded, &os->eth.tx_multicast,
2776                             &ns->eth.tx_multicast);
2777         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
2778                             I40E_GLPRT_BPTCL(hw->port),
2779                             pf->offset_loaded, &os->eth.tx_broadcast,
2780                             &ns->eth.tx_broadcast);
2781         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
2782                 ns->eth.tx_broadcast) * ETHER_CRC_LEN;
2783
2784         /* exclude internal tx bytes
2785          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
2786          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
2787          * value.
2788          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
2789          */
2790         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
2791                 ns->eth.tx_bytes = 0;
2792         else
2793                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
2794
2795         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
2796                 ns->eth.tx_unicast = 0;
2797         else
2798                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
2799
2800         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
2801                 ns->eth.tx_multicast = 0;
2802         else
2803                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
2804
2805         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
2806                 ns->eth.tx_broadcast = 0;
2807         else
2808                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
2809
2810         /* GLPRT_TEPC not supported */
2811
2812         /* additional port specific stats */
2813         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
2814                             pf->offset_loaded, &os->tx_dropped_link_down,
2815                             &ns->tx_dropped_link_down);
2816         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
2817                             pf->offset_loaded, &os->crc_errors,
2818                             &ns->crc_errors);
2819         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
2820                             pf->offset_loaded, &os->illegal_bytes,
2821                             &ns->illegal_bytes);
2822         /* GLPRT_ERRBC not supported */
2823         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
2824                             pf->offset_loaded, &os->mac_local_faults,
2825                             &ns->mac_local_faults);
2826         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
2827                             pf->offset_loaded, &os->mac_remote_faults,
2828                             &ns->mac_remote_faults);
2829         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
2830                             pf->offset_loaded, &os->rx_length_errors,
2831                             &ns->rx_length_errors);
2832         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
2833                             pf->offset_loaded, &os->link_xon_rx,
2834                             &ns->link_xon_rx);
2835         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
2836                             pf->offset_loaded, &os->link_xoff_rx,
2837                             &ns->link_xoff_rx);
2838         for (i = 0; i < 8; i++) {
2839                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
2840                                     pf->offset_loaded,
2841                                     &os->priority_xon_rx[i],
2842                                     &ns->priority_xon_rx[i]);
2843                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
2844                                     pf->offset_loaded,
2845                                     &os->priority_xoff_rx[i],
2846                                     &ns->priority_xoff_rx[i]);
2847         }
2848         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
2849                             pf->offset_loaded, &os->link_xon_tx,
2850                             &ns->link_xon_tx);
2851         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
2852                             pf->offset_loaded, &os->link_xoff_tx,
2853                             &ns->link_xoff_tx);
2854         for (i = 0; i < 8; i++) {
2855                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
2856                                     pf->offset_loaded,
2857                                     &os->priority_xon_tx[i],
2858                                     &ns->priority_xon_tx[i]);
2859                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
2860                                     pf->offset_loaded,
2861                                     &os->priority_xoff_tx[i],
2862                                     &ns->priority_xoff_tx[i]);
2863                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
2864                                     pf->offset_loaded,
2865                                     &os->priority_xon_2_xoff[i],
2866                                     &ns->priority_xon_2_xoff[i]);
2867         }
2868         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
2869                             I40E_GLPRT_PRC64L(hw->port),
2870                             pf->offset_loaded, &os->rx_size_64,
2871                             &ns->rx_size_64);
2872         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
2873                             I40E_GLPRT_PRC127L(hw->port),
2874                             pf->offset_loaded, &os->rx_size_127,
2875                             &ns->rx_size_127);
2876         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
2877                             I40E_GLPRT_PRC255L(hw->port),
2878                             pf->offset_loaded, &os->rx_size_255,
2879                             &ns->rx_size_255);
2880         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
2881                             I40E_GLPRT_PRC511L(hw->port),
2882                             pf->offset_loaded, &os->rx_size_511,
2883                             &ns->rx_size_511);
2884         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
2885                             I40E_GLPRT_PRC1023L(hw->port),
2886                             pf->offset_loaded, &os->rx_size_1023,
2887                             &ns->rx_size_1023);
2888         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
2889                             I40E_GLPRT_PRC1522L(hw->port),
2890                             pf->offset_loaded, &os->rx_size_1522,
2891                             &ns->rx_size_1522);
2892         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
2893                             I40E_GLPRT_PRC9522L(hw->port),
2894                             pf->offset_loaded, &os->rx_size_big,
2895                             &ns->rx_size_big);
2896         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
2897                             pf->offset_loaded, &os->rx_undersize,
2898                             &ns->rx_undersize);
2899         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
2900                             pf->offset_loaded, &os->rx_fragments,
2901                             &ns->rx_fragments);
2902         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
2903                             pf->offset_loaded, &os->rx_oversize,
2904                             &ns->rx_oversize);
2905         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
2906                             pf->offset_loaded, &os->rx_jabber,
2907                             &ns->rx_jabber);
2908         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
2909                             I40E_GLPRT_PTC64L(hw->port),
2910                             pf->offset_loaded, &os->tx_size_64,
2911                             &ns->tx_size_64);
2912         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
2913                             I40E_GLPRT_PTC127L(hw->port),
2914                             pf->offset_loaded, &os->tx_size_127,
2915                             &ns->tx_size_127);
2916         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
2917                             I40E_GLPRT_PTC255L(hw->port),
2918                             pf->offset_loaded, &os->tx_size_255,
2919                             &ns->tx_size_255);
2920         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
2921                             I40E_GLPRT_PTC511L(hw->port),
2922                             pf->offset_loaded, &os->tx_size_511,
2923                             &ns->tx_size_511);
2924         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
2925                             I40E_GLPRT_PTC1023L(hw->port),
2926                             pf->offset_loaded, &os->tx_size_1023,
2927                             &ns->tx_size_1023);
2928         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
2929                             I40E_GLPRT_PTC1522L(hw->port),
2930                             pf->offset_loaded, &os->tx_size_1522,
2931                             &ns->tx_size_1522);
2932         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
2933                             I40E_GLPRT_PTC9522L(hw->port),
2934                             pf->offset_loaded, &os->tx_size_big,
2935                             &ns->tx_size_big);
2936         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
2937                            pf->offset_loaded,
2938                            &os->fd_sb_match, &ns->fd_sb_match);
2939         /* GLPRT_MSPDC not supported */
2940         /* GLPRT_XEC not supported */
2941
2942         pf->offset_loaded = true;
2943
2944         if (pf->main_vsi)
2945                 i40e_update_vsi_stats(pf->main_vsi);
2946 }
2947
2948 /* Get all statistics of a port */
2949 static int
2950 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2951 {
2952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2953         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2954         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2955         unsigned i;
2956
2957         /* call read registers - updates values, now write them to struct */
2958         i40e_read_stats_registers(pf, hw);
2959
2960         stats->ipackets = ns->eth.rx_unicast +
2961                         ns->eth.rx_multicast +
2962                         ns->eth.rx_broadcast -
2963                         ns->eth.rx_discards -
2964                         pf->main_vsi->eth_stats.rx_discards;
2965         stats->opackets = ns->eth.tx_unicast +
2966                         ns->eth.tx_multicast +
2967                         ns->eth.tx_broadcast;
2968         stats->ibytes   = ns->eth.rx_bytes;
2969         stats->obytes   = ns->eth.tx_bytes;
2970         stats->oerrors  = ns->eth.tx_errors +
2971                         pf->main_vsi->eth_stats.tx_errors;
2972
2973         /* Rx Errors */
2974         stats->imissed  = ns->eth.rx_discards +
2975                         pf->main_vsi->eth_stats.rx_discards;
2976         stats->ierrors  = ns->crc_errors +
2977                         ns->rx_length_errors + ns->rx_undersize +
2978                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
2979
2980         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
2981         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
2982         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
2983         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
2984         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
2985         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
2986         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2987                     ns->eth.rx_unknown_protocol);
2988         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
2989         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
2990         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
2991         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
2992         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
2993         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
2994
2995         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
2996                     ns->tx_dropped_link_down);
2997         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
2998         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
2999                     ns->illegal_bytes);
3000         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3001         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3002                     ns->mac_local_faults);
3003         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3004                     ns->mac_remote_faults);
3005         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3006                     ns->rx_length_errors);
3007         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3008         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3009         for (i = 0; i < 8; i++) {
3010                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3011                                 i, ns->priority_xon_rx[i]);
3012                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3013                                 i, ns->priority_xoff_rx[i]);
3014         }
3015         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3016         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3017         for (i = 0; i < 8; i++) {
3018                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3019                                 i, ns->priority_xon_tx[i]);
3020                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3021                                 i, ns->priority_xoff_tx[i]);
3022                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3023                                 i, ns->priority_xon_2_xoff[i]);
3024         }
3025         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3026         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3027         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3028         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3029         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3030         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3031         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3032         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3033         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3034         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3035         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3036         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3037         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3038         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3039         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3040         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3041         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3042         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3043         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3044                         ns->mac_short_packet_dropped);
3045         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3046                     ns->checksum_error);
3047         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3048         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3049         return 0;
3050 }
3051
3052 /* Reset the statistics */
3053 static void
3054 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3055 {
3056         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3057         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3058
3059         /* Mark PF and VSI stats to update the offset, aka "reset" */
3060         pf->offset_loaded = false;
3061         if (pf->main_vsi)
3062                 pf->main_vsi->offset_loaded = false;
3063
3064         /* read the stats, reading current register values into offset */
3065         i40e_read_stats_registers(pf, hw);
3066 }
3067
3068 static uint32_t
3069 i40e_xstats_calc_num(void)
3070 {
3071         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3072                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3073                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3074 }
3075
3076 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3077                                      struct rte_eth_xstat_name *xstats_names,
3078                                      __rte_unused unsigned limit)
3079 {
3080         unsigned count = 0;
3081         unsigned i, prio;
3082
3083         if (xstats_names == NULL)
3084                 return i40e_xstats_calc_num();
3085
3086         /* Note: limit checked in rte_eth_xstats_names() */
3087
3088         /* Get stats from i40e_eth_stats struct */
3089         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3090                 snprintf(xstats_names[count].name,
3091                          sizeof(xstats_names[count].name),
3092                          "%s", rte_i40e_stats_strings[i].name);
3093                 count++;
3094         }
3095
3096         /* Get individiual stats from i40e_hw_port struct */
3097         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3098                 snprintf(xstats_names[count].name,
3099                         sizeof(xstats_names[count].name),
3100                          "%s", rte_i40e_hw_port_strings[i].name);
3101                 count++;
3102         }
3103
3104         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3105                 for (prio = 0; prio < 8; prio++) {
3106                         snprintf(xstats_names[count].name,
3107                                  sizeof(xstats_names[count].name),
3108                                  "rx_priority%u_%s", prio,
3109                                  rte_i40e_rxq_prio_strings[i].name);
3110                         count++;
3111                 }
3112         }
3113
3114         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3115                 for (prio = 0; prio < 8; prio++) {
3116                         snprintf(xstats_names[count].name,
3117                                  sizeof(xstats_names[count].name),
3118                                  "tx_priority%u_%s", prio,
3119                                  rte_i40e_txq_prio_strings[i].name);
3120                         count++;
3121                 }
3122         }
3123         return count;
3124 }
3125
3126 static int
3127 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3128                     unsigned n)
3129 {
3130         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3131         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3132         unsigned i, count, prio;
3133         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3134
3135         count = i40e_xstats_calc_num();
3136         if (n < count)
3137                 return count;
3138
3139         i40e_read_stats_registers(pf, hw);
3140
3141         if (xstats == NULL)
3142                 return 0;
3143
3144         count = 0;
3145
3146         /* Get stats from i40e_eth_stats struct */
3147         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3148                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3149                         rte_i40e_stats_strings[i].offset);
3150                 xstats[count].id = count;
3151                 count++;
3152         }
3153
3154         /* Get individiual stats from i40e_hw_port struct */
3155         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3156                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3157                         rte_i40e_hw_port_strings[i].offset);
3158                 xstats[count].id = count;
3159                 count++;
3160         }
3161
3162         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3163                 for (prio = 0; prio < 8; prio++) {
3164                         xstats[count].value =
3165                                 *(uint64_t *)(((char *)hw_stats) +
3166                                 rte_i40e_rxq_prio_strings[i].offset +
3167                                 (sizeof(uint64_t) * prio));
3168                         xstats[count].id = count;
3169                         count++;
3170                 }
3171         }
3172
3173         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3174                 for (prio = 0; prio < 8; prio++) {
3175                         xstats[count].value =
3176                                 *(uint64_t *)(((char *)hw_stats) +
3177                                 rte_i40e_txq_prio_strings[i].offset +
3178                                 (sizeof(uint64_t) * prio));
3179                         xstats[count].id = count;
3180                         count++;
3181                 }
3182         }
3183
3184         return count;
3185 }
3186
3187 static int
3188 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3189                                  __rte_unused uint16_t queue_id,
3190                                  __rte_unused uint8_t stat_idx,
3191                                  __rte_unused uint8_t is_rx)
3192 {
3193         PMD_INIT_FUNC_TRACE();
3194
3195         return -ENOSYS;
3196 }
3197
3198 static int
3199 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3200 {
3201         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3202         u32 full_ver;
3203         u8 ver, patch;
3204         u16 build;
3205         int ret;
3206
3207         full_ver = hw->nvm.oem_ver;
3208         ver = (u8)(full_ver >> 24);
3209         build = (u16)((full_ver >> 8) & 0xffff);
3210         patch = (u8)(full_ver & 0xff);
3211
3212         ret = snprintf(fw_version, fw_size,
3213                  "%d.%d%d 0x%08x %d.%d.%d",
3214                  ((hw->nvm.version >> 12) & 0xf),
3215                  ((hw->nvm.version >> 4) & 0xff),
3216                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3217                  ver, build, patch);
3218
3219         ret += 1; /* add the size of '\0' */
3220         if (fw_size < (u32)ret)
3221                 return ret;
3222         else
3223                 return 0;
3224 }
3225
3226 static void
3227 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3228 {
3229         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3230         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3231         struct i40e_vsi *vsi = pf->main_vsi;
3232         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3233
3234         dev_info->pci_dev = pci_dev;
3235         dev_info->max_rx_queues = vsi->nb_qps;
3236         dev_info->max_tx_queues = vsi->nb_qps;
3237         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3238         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3239         dev_info->max_mac_addrs = vsi->max_macaddrs;
3240         dev_info->max_vfs = pci_dev->max_vfs;
3241         dev_info->rx_offload_capa =
3242                 DEV_RX_OFFLOAD_VLAN_STRIP |
3243                 DEV_RX_OFFLOAD_QINQ_STRIP |
3244                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3245                 DEV_RX_OFFLOAD_UDP_CKSUM |
3246                 DEV_RX_OFFLOAD_TCP_CKSUM |
3247                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3248                 DEV_RX_OFFLOAD_CRC_STRIP;
3249         dev_info->tx_offload_capa =
3250                 DEV_TX_OFFLOAD_VLAN_INSERT |
3251                 DEV_TX_OFFLOAD_QINQ_INSERT |
3252                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3253                 DEV_TX_OFFLOAD_UDP_CKSUM |
3254                 DEV_TX_OFFLOAD_TCP_CKSUM |
3255                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3256                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3257                 DEV_TX_OFFLOAD_TCP_TSO |
3258                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3259                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3260                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3261                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO;
3262         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3263                                                 sizeof(uint32_t);
3264         dev_info->reta_size = pf->hash_lut_size;
3265         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3266
3267         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3268                 .rx_thresh = {
3269                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3270                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3271                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3272                 },
3273                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3274                 .rx_drop_en = 0,
3275         };
3276
3277         dev_info->default_txconf = (struct rte_eth_txconf) {
3278                 .tx_thresh = {
3279                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3280                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3281                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3282                 },
3283                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3284                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3285                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
3286                                 ETH_TXQ_FLAGS_NOOFFLOADS,
3287         };
3288
3289         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3290                 .nb_max = I40E_MAX_RING_DESC,
3291                 .nb_min = I40E_MIN_RING_DESC,
3292                 .nb_align = I40E_ALIGN_RING_DESC,
3293         };
3294
3295         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3296                 .nb_max = I40E_MAX_RING_DESC,
3297                 .nb_min = I40E_MIN_RING_DESC,
3298                 .nb_align = I40E_ALIGN_RING_DESC,
3299                 .nb_seg_max = I40E_TX_MAX_SEG,
3300                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3301         };
3302
3303         if (pf->flags & I40E_FLAG_VMDQ) {
3304                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3305                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3306                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3307                                                 pf->max_nb_vmdq_vsi;
3308                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3309                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3310                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3311         }
3312
3313         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types))
3314                 /* For XL710 */
3315                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3316         else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types))
3317                 /* For XXV710 */
3318                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3319         else
3320                 /* For X710 */
3321                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3322 }
3323
3324 static int
3325 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3326 {
3327         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3328         struct i40e_vsi *vsi = pf->main_vsi;
3329         PMD_INIT_FUNC_TRACE();
3330
3331         if (on)
3332                 return i40e_vsi_add_vlan(vsi, vlan_id);
3333         else
3334                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3335 }
3336
3337 static int
3338 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3339                                 enum rte_vlan_type vlan_type,
3340                                 uint16_t tpid, int qinq)
3341 {
3342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3343         uint64_t reg_r = 0;
3344         uint64_t reg_w = 0;
3345         uint16_t reg_id = 3;
3346         int ret;
3347
3348         if (qinq) {
3349                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3350                         reg_id = 2;
3351         }
3352
3353         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3354                                           &reg_r, NULL);
3355         if (ret != I40E_SUCCESS) {
3356                 PMD_DRV_LOG(ERR,
3357                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3358                            reg_id);
3359                 return -EIO;
3360         }
3361         PMD_DRV_LOG(DEBUG,
3362                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3363                     reg_id, reg_r);
3364
3365         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3366         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3367         if (reg_r == reg_w) {
3368                 PMD_DRV_LOG(DEBUG, "No need to write");
3369                 return 0;
3370         }
3371
3372         ret = i40e_aq_debug_write_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3373                                            reg_w, NULL);
3374         if (ret != I40E_SUCCESS) {
3375                 PMD_DRV_LOG(ERR,
3376                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3377                             reg_id);
3378                 return -EIO;
3379         }
3380         PMD_DRV_LOG(DEBUG,
3381                     "Global register 0x%08x is changed with value 0x%08x",
3382                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3383
3384         return 0;
3385 }
3386
3387 static int
3388 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3389                    enum rte_vlan_type vlan_type,
3390                    uint16_t tpid)
3391 {
3392         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3394         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
3395         int ret = 0;
3396
3397         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3398              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3399             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3400                 PMD_DRV_LOG(ERR,
3401                             "Unsupported vlan type.");
3402                 return -EINVAL;
3403         }
3404
3405         if (pf->support_multi_driver) {
3406                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3407                 return -ENOTSUP;
3408         }
3409
3410         /* 802.1ad frames ability is added in NVM API 1.7*/
3411         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3412                 if (qinq) {
3413                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3414                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3415                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3416                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3417                 } else {
3418                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3419                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3420                 }
3421                 ret = i40e_aq_set_switch_config(hw, 0, 0, NULL);
3422                 if (ret != I40E_SUCCESS) {
3423                         PMD_DRV_LOG(ERR,
3424                                     "Set switch config failed aq_err: %d",
3425                                     hw->aq.asq_last_status);
3426                         ret = -EIO;
3427                 }
3428         } else
3429                 /* If NVM API < 1.7, keep the register setting */
3430                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3431                                                       tpid, qinq);
3432         i40e_global_cfg_warning(I40E_WARNING_TPID);
3433
3434         return ret;
3435 }
3436
3437 static int
3438 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3439 {
3440         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3441         struct i40e_vsi *vsi = pf->main_vsi;
3442
3443         if (mask & ETH_VLAN_FILTER_MASK) {
3444                 if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3445                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3446                 else
3447                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3448         }
3449
3450         if (mask & ETH_VLAN_STRIP_MASK) {
3451                 /* Enable or disable VLAN stripping */
3452                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
3453                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3454                 else
3455                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3456         }
3457
3458         if (mask & ETH_VLAN_EXTEND_MASK) {
3459                 if (dev->data->dev_conf.rxmode.hw_vlan_extend) {
3460                         i40e_vsi_config_double_vlan(vsi, TRUE);
3461                         /* Set global registers with default ethertype. */
3462                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3463                                            ETHER_TYPE_VLAN);
3464                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3465                                            ETHER_TYPE_VLAN);
3466                 }
3467                 else
3468                         i40e_vsi_config_double_vlan(vsi, FALSE);
3469         }
3470
3471         return 0;
3472 }
3473
3474 static void
3475 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3476                           __rte_unused uint16_t queue,
3477                           __rte_unused int on)
3478 {
3479         PMD_INIT_FUNC_TRACE();
3480 }
3481
3482 static int
3483 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3484 {
3485         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3486         struct i40e_vsi *vsi = pf->main_vsi;
3487         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3488         struct i40e_vsi_vlan_pvid_info info;
3489
3490         memset(&info, 0, sizeof(info));
3491         info.on = on;
3492         if (info.on)
3493                 info.config.pvid = pvid;
3494         else {
3495                 info.config.reject.tagged =
3496                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3497                 info.config.reject.untagged =
3498                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3499         }
3500
3501         return i40e_vsi_vlan_pvid_set(vsi, &info);
3502 }
3503
3504 static int
3505 i40e_dev_led_on(struct rte_eth_dev *dev)
3506 {
3507         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3508         uint32_t mode = i40e_led_get(hw);
3509
3510         if (mode == 0)
3511                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3512
3513         return 0;
3514 }
3515
3516 static int
3517 i40e_dev_led_off(struct rte_eth_dev *dev)
3518 {
3519         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3520         uint32_t mode = i40e_led_get(hw);
3521
3522         if (mode != 0)
3523                 i40e_led_set(hw, 0, false);
3524
3525         return 0;
3526 }
3527
3528 static int
3529 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3530 {
3531         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3532         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3533
3534         fc_conf->pause_time = pf->fc_conf.pause_time;
3535
3536         /* read out from register, in case they are modified by other port */
3537         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3538                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3539         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3540                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3541
3542         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3543         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3544
3545          /* Return current mode according to actual setting*/
3546         switch (hw->fc.current_mode) {
3547         case I40E_FC_FULL:
3548                 fc_conf->mode = RTE_FC_FULL;
3549                 break;
3550         case I40E_FC_TX_PAUSE:
3551                 fc_conf->mode = RTE_FC_TX_PAUSE;
3552                 break;
3553         case I40E_FC_RX_PAUSE:
3554                 fc_conf->mode = RTE_FC_RX_PAUSE;
3555                 break;
3556         case I40E_FC_NONE:
3557         default:
3558                 fc_conf->mode = RTE_FC_NONE;
3559         };
3560
3561         return 0;
3562 }
3563
3564 static int
3565 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3566 {
3567         uint32_t mflcn_reg, fctrl_reg, reg;
3568         uint32_t max_high_water;
3569         uint8_t i, aq_failure;
3570         int err;
3571         struct i40e_hw *hw;
3572         struct i40e_pf *pf;
3573         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3574                 [RTE_FC_NONE] = I40E_FC_NONE,
3575                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3576                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3577                 [RTE_FC_FULL] = I40E_FC_FULL
3578         };
3579
3580         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3581
3582         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3583         if ((fc_conf->high_water > max_high_water) ||
3584                         (fc_conf->high_water < fc_conf->low_water)) {
3585                 PMD_INIT_LOG(ERR,
3586                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3587                         max_high_water);
3588                 return -EINVAL;
3589         }
3590
3591         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3592         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3593         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3594
3595         pf->fc_conf.pause_time = fc_conf->pause_time;
3596         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3597         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3598
3599         PMD_INIT_FUNC_TRACE();
3600
3601         /* All the link flow control related enable/disable register
3602          * configuration is handle by the F/W
3603          */
3604         err = i40e_set_fc(hw, &aq_failure, true);
3605         if (err < 0)
3606                 return -ENOSYS;
3607
3608         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3609                 /* Configure flow control refresh threshold,
3610                  * the value for stat_tx_pause_refresh_timer[8]
3611                  * is used for global pause operation.
3612                  */
3613
3614                 I40E_WRITE_REG(hw,
3615                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3616                                pf->fc_conf.pause_time);
3617
3618                 /* configure the timer value included in transmitted pause
3619                  * frame,
3620                  * the value for stat_tx_pause_quanta[8] is used for global
3621                  * pause operation
3622                  */
3623                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3624                                pf->fc_conf.pause_time);
3625
3626                 fctrl_reg = I40E_READ_REG(hw,
3627                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3628
3629                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3630                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3631                 else
3632                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3633
3634                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3635                                fctrl_reg);
3636         } else {
3637                 /* Configure pause time (2 TCs per register) */
3638                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3639                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3640                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3641
3642                 /* Configure flow control refresh threshold value */
3643                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3644                                pf->fc_conf.pause_time / 2);
3645
3646                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3647
3648                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3649                  *depending on configuration
3650                  */
3651                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3652                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3653                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3654                 } else {
3655                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3656                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3657                 }
3658
3659                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3660         }
3661
3662         if (!pf->support_multi_driver) {
3663                 /* config water marker both based on the packets and bytes */
3664                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3665                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3666                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3667                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3668                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3669                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3670                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3671                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3672                                   << I40E_KILOSHIFT);
3673                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3674                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3675                                    << I40E_KILOSHIFT);
3676                 i40e_global_cfg_warning(I40E_WARNING_FLOW_CTL);
3677         } else {
3678                 PMD_DRV_LOG(ERR,
3679                             "Water marker configuration is not supported.");
3680         }
3681
3682         I40E_WRITE_FLUSH(hw);
3683
3684         return 0;
3685 }
3686
3687 static int
3688 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
3689                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
3690 {
3691         PMD_INIT_FUNC_TRACE();
3692
3693         return -ENOSYS;
3694 }
3695
3696 /* Add a MAC address, and update filters */
3697 static int
3698 i40e_macaddr_add(struct rte_eth_dev *dev,
3699                  struct ether_addr *mac_addr,
3700                  __rte_unused uint32_t index,
3701                  uint32_t pool)
3702 {
3703         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3704         struct i40e_mac_filter_info mac_filter;
3705         struct i40e_vsi *vsi;
3706         int ret;
3707
3708         /* If VMDQ not enabled or configured, return */
3709         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
3710                           !pf->nb_cfg_vmdq_vsi)) {
3711                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
3712                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
3713                         pool);
3714                 return -ENOTSUP;
3715         }
3716
3717         if (pool > pf->nb_cfg_vmdq_vsi) {
3718                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
3719                                 pool, pf->nb_cfg_vmdq_vsi);
3720                 return -EINVAL;
3721         }
3722
3723         rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
3724         if (dev->data->dev_conf.rxmode.hw_vlan_filter)
3725                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3726         else
3727                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
3728
3729         if (pool == 0)
3730                 vsi = pf->main_vsi;
3731         else
3732                 vsi = pf->vmdq[pool - 1].vsi;
3733
3734         ret = i40e_vsi_add_mac(vsi, &mac_filter);
3735         if (ret != I40E_SUCCESS) {
3736                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3737                 return -ENODEV;
3738         }
3739         return 0;
3740 }
3741
3742 /* Remove a MAC address, and update filters */
3743 static void
3744 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3745 {
3746         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3747         struct i40e_vsi *vsi;
3748         struct rte_eth_dev_data *data = dev->data;
3749         struct ether_addr *macaddr;
3750         int ret;
3751         uint32_t i;
3752         uint64_t pool_sel;
3753
3754         macaddr = &(data->mac_addrs[index]);
3755
3756         pool_sel = dev->data->mac_pool_sel[index];
3757
3758         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
3759                 if (pool_sel & (1ULL << i)) {
3760                         if (i == 0)
3761                                 vsi = pf->main_vsi;
3762                         else {
3763                                 /* No VMDQ pool enabled or configured */
3764                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
3765                                         (i > pf->nb_cfg_vmdq_vsi)) {
3766                                         PMD_DRV_LOG(ERR,
3767                                                 "No VMDQ pool enabled/configured");
3768                                         return;
3769                                 }
3770                                 vsi = pf->vmdq[i - 1].vsi;
3771                         }
3772                         ret = i40e_vsi_delete_mac(vsi, macaddr);
3773
3774                         if (ret) {
3775                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
3776                                 return;
3777                         }
3778                 }
3779         }
3780 }
3781
3782 /* Set perfect match or hash match of MAC and VLAN for a VF */
3783 static int
3784 i40e_vf_mac_filter_set(struct i40e_pf *pf,
3785                  struct rte_eth_mac_filter *filter,
3786                  bool add)
3787 {
3788         struct i40e_hw *hw;
3789         struct i40e_mac_filter_info mac_filter;
3790         struct ether_addr old_mac;
3791         struct ether_addr *new_mac;
3792         struct i40e_pf_vf *vf = NULL;
3793         uint16_t vf_id;
3794         int ret;
3795
3796         if (pf == NULL) {
3797                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
3798                 return -EINVAL;
3799         }
3800         hw = I40E_PF_TO_HW(pf);
3801
3802         if (filter == NULL) {
3803                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
3804                 return -EINVAL;
3805         }
3806
3807         new_mac = &filter->mac_addr;
3808
3809         if (is_zero_ether_addr(new_mac)) {
3810                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
3811                 return -EINVAL;
3812         }
3813
3814         vf_id = filter->dst_id;
3815
3816         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
3817                 PMD_DRV_LOG(ERR, "Invalid argument.");
3818                 return -EINVAL;
3819         }
3820         vf = &pf->vfs[vf_id];
3821
3822         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
3823                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
3824                 return -EINVAL;
3825         }
3826
3827         if (add) {
3828                 rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
3829                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
3830                                 ETHER_ADDR_LEN);
3831                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
3832                                  ETHER_ADDR_LEN);
3833
3834                 mac_filter.filter_type = filter->filter_type;
3835                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
3836                 if (ret != I40E_SUCCESS) {
3837                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
3838                         return -1;
3839                 }
3840                 ether_addr_copy(new_mac, &pf->dev_addr);
3841         } else {
3842                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
3843                                 ETHER_ADDR_LEN);
3844                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
3845                 if (ret != I40E_SUCCESS) {
3846                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
3847                         return -1;
3848                 }
3849
3850                 /* Clear device address as it has been removed */
3851                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
3852                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
3853         }
3854
3855         return 0;
3856 }
3857
3858 /* MAC filter handle */
3859 static int
3860 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
3861                 void *arg)
3862 {
3863         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3864         struct rte_eth_mac_filter *filter;
3865         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3866         int ret = I40E_NOT_SUPPORTED;
3867
3868         filter = (struct rte_eth_mac_filter *)(arg);
3869
3870         switch (filter_op) {
3871         case RTE_ETH_FILTER_NOP:
3872                 ret = I40E_SUCCESS;
3873                 break;
3874         case RTE_ETH_FILTER_ADD:
3875                 i40e_pf_disable_irq0(hw);
3876                 if (filter->is_vf)
3877                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
3878                 i40e_pf_enable_irq0(hw);
3879                 break;
3880         case RTE_ETH_FILTER_DELETE:
3881                 i40e_pf_disable_irq0(hw);
3882                 if (filter->is_vf)
3883                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
3884                 i40e_pf_enable_irq0(hw);
3885                 break;
3886         default:
3887                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
3888                 ret = I40E_ERR_PARAM;
3889                 break;
3890         }
3891
3892         return ret;
3893 }
3894
3895 static int
3896 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3897 {
3898         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
3899         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3900         uint32_t reg;
3901         int ret;
3902
3903         if (!lut)
3904                 return -EINVAL;
3905
3906         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3907                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, TRUE,
3908                                           lut, lut_size);
3909                 if (ret) {
3910                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
3911                         return ret;
3912                 }
3913         } else {
3914                 uint32_t *lut_dw = (uint32_t *)lut;
3915                 uint16_t i, lut_size_dw = lut_size / 4;
3916
3917                 if (vsi->type == I40E_VSI_SRIOV) {
3918                         for (i = 0; i <= lut_size_dw; i++) {
3919                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
3920                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
3921                         }
3922                 } else {
3923                         for (i = 0; i < lut_size_dw; i++)
3924                                 lut_dw[i] = I40E_READ_REG(hw,
3925                                                           I40E_PFQF_HLUT(i));
3926                 }
3927         }
3928
3929         return 0;
3930 }
3931
3932 int
3933 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
3934 {
3935         struct i40e_pf *pf;
3936         struct i40e_hw *hw;
3937         int ret;
3938
3939         if (!vsi || !lut)
3940                 return -EINVAL;
3941
3942         pf = I40E_VSI_TO_PF(vsi);
3943         hw = I40E_VSI_TO_HW(vsi);
3944
3945         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
3946                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, TRUE,
3947                                           lut, lut_size);
3948                 if (ret) {
3949                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
3950                         return ret;
3951                 }
3952         } else {
3953                 uint32_t *lut_dw = (uint32_t *)lut;
3954                 uint16_t i, lut_size_dw = lut_size / 4;
3955
3956                 if (vsi->type == I40E_VSI_SRIOV) {
3957                         for (i = 0; i < lut_size_dw; i++)
3958                                 I40E_WRITE_REG(
3959                                         hw,
3960                                         I40E_VFQF_HLUT1(i, vsi->user_param),
3961                                         lut_dw[i]);
3962                 } else {
3963                         for (i = 0; i < lut_size_dw; i++)
3964                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
3965                                                lut_dw[i]);
3966                 }
3967                 I40E_WRITE_FLUSH(hw);
3968         }
3969
3970         return 0;
3971 }
3972
3973 static int
3974 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
3975                          struct rte_eth_rss_reta_entry64 *reta_conf,
3976                          uint16_t reta_size)
3977 {
3978         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3979         uint16_t i, lut_size = pf->hash_lut_size;
3980         uint16_t idx, shift;
3981         uint8_t *lut;
3982         int ret;
3983
3984         if (reta_size != lut_size ||
3985                 reta_size > ETH_RSS_RETA_SIZE_512) {
3986                 PMD_DRV_LOG(ERR,
3987                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
3988                         reta_size, lut_size);
3989                 return -EINVAL;
3990         }
3991
3992         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
3993         if (!lut) {
3994                 PMD_DRV_LOG(ERR, "No memory can be allocated");
3995                 return -ENOMEM;
3996         }
3997         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
3998         if (ret)
3999                 goto out;
4000         for (i = 0; i < reta_size; i++) {
4001                 idx = i / RTE_RETA_GROUP_SIZE;
4002                 shift = i % RTE_RETA_GROUP_SIZE;
4003                 if (reta_conf[idx].mask & (1ULL << shift))
4004                         lut[i] = reta_conf[idx].reta[shift];
4005         }
4006         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4007
4008 out:
4009         rte_free(lut);
4010
4011         return ret;
4012 }
4013
4014 static int
4015 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4016                         struct rte_eth_rss_reta_entry64 *reta_conf,
4017                         uint16_t reta_size)
4018 {
4019         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4020         uint16_t i, lut_size = pf->hash_lut_size;
4021         uint16_t idx, shift;
4022         uint8_t *lut;
4023         int ret;
4024
4025         if (reta_size != lut_size ||
4026                 reta_size > ETH_RSS_RETA_SIZE_512) {
4027                 PMD_DRV_LOG(ERR,
4028                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4029                         reta_size, lut_size);
4030                 return -EINVAL;
4031         }
4032
4033         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4034         if (!lut) {
4035                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4036                 return -ENOMEM;
4037         }
4038
4039         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4040         if (ret)
4041                 goto out;
4042         for (i = 0; i < reta_size; i++) {
4043                 idx = i / RTE_RETA_GROUP_SIZE;
4044                 shift = i % RTE_RETA_GROUP_SIZE;
4045                 if (reta_conf[idx].mask & (1ULL << shift))
4046                         reta_conf[idx].reta[shift] = lut[i];
4047         }
4048
4049 out:
4050         rte_free(lut);
4051
4052         return ret;
4053 }
4054
4055 /**
4056  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4057  * @hw:   pointer to the HW structure
4058  * @mem:  pointer to mem struct to fill out
4059  * @size: size of memory requested
4060  * @alignment: what to align the allocation to
4061  **/
4062 enum i40e_status_code
4063 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4064                         struct i40e_dma_mem *mem,
4065                         u64 size,
4066                         u32 alignment)
4067 {
4068         const struct rte_memzone *mz = NULL;
4069         char z_name[RTE_MEMZONE_NAMESIZE];
4070
4071         if (!mem)
4072                 return I40E_ERR_PARAM;
4073
4074         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4075         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
4076                                          alignment, RTE_PGSIZE_2M);
4077         if (!mz)
4078                 return I40E_ERR_NO_MEMORY;
4079
4080         mem->size = size;
4081         mem->va = mz->addr;
4082         mem->pa = mz->iova;
4083         mem->zone = (const void *)mz;
4084         PMD_DRV_LOG(DEBUG,
4085                 "memzone %s allocated with physical address: %"PRIu64,
4086                 mz->name, mem->pa);
4087
4088         return I40E_SUCCESS;
4089 }
4090
4091 /**
4092  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4093  * @hw:   pointer to the HW structure
4094  * @mem:  ptr to mem struct to free
4095  **/
4096 enum i40e_status_code
4097 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4098                     struct i40e_dma_mem *mem)
4099 {
4100         if (!mem)
4101                 return I40E_ERR_PARAM;
4102
4103         PMD_DRV_LOG(DEBUG,
4104                 "memzone %s to be freed with physical address: %"PRIu64,
4105                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4106         rte_memzone_free((const struct rte_memzone *)mem->zone);
4107         mem->zone = NULL;
4108         mem->va = NULL;
4109         mem->pa = (u64)0;
4110
4111         return I40E_SUCCESS;
4112 }
4113
4114 /**
4115  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4116  * @hw:   pointer to the HW structure
4117  * @mem:  pointer to mem struct to fill out
4118  * @size: size of memory requested
4119  **/
4120 enum i40e_status_code
4121 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4122                          struct i40e_virt_mem *mem,
4123                          u32 size)
4124 {
4125         if (!mem)
4126                 return I40E_ERR_PARAM;
4127
4128         mem->size = size;
4129         mem->va = rte_zmalloc("i40e", size, 0);
4130
4131         if (mem->va)
4132                 return I40E_SUCCESS;
4133         else
4134                 return I40E_ERR_NO_MEMORY;
4135 }
4136
4137 /**
4138  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4139  * @hw:   pointer to the HW structure
4140  * @mem:  pointer to mem struct to free
4141  **/
4142 enum i40e_status_code
4143 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4144                      struct i40e_virt_mem *mem)
4145 {
4146         if (!mem)
4147                 return I40E_ERR_PARAM;
4148
4149         rte_free(mem->va);
4150         mem->va = NULL;
4151
4152         return I40E_SUCCESS;
4153 }
4154
4155 void
4156 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4157 {
4158         rte_spinlock_init(&sp->spinlock);
4159 }
4160
4161 void
4162 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4163 {
4164         rte_spinlock_lock(&sp->spinlock);
4165 }
4166
4167 void
4168 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4169 {
4170         rte_spinlock_unlock(&sp->spinlock);
4171 }
4172
4173 void
4174 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4175 {
4176         return;
4177 }
4178
4179 /**
4180  * Get the hardware capabilities, which will be parsed
4181  * and saved into struct i40e_hw.
4182  */
4183 static int
4184 i40e_get_cap(struct i40e_hw *hw)
4185 {
4186         struct i40e_aqc_list_capabilities_element_resp *buf;
4187         uint16_t len, size = 0;
4188         int ret;
4189
4190         /* Calculate a huge enough buff for saving response data temporarily */
4191         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4192                                                 I40E_MAX_CAP_ELE_NUM;
4193         buf = rte_zmalloc("i40e", len, 0);
4194         if (!buf) {
4195                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4196                 return I40E_ERR_NO_MEMORY;
4197         }
4198
4199         /* Get, parse the capabilities and save it to hw */
4200         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4201                         i40e_aqc_opc_list_func_capabilities, NULL);
4202         if (ret != I40E_SUCCESS)
4203                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4204
4205         /* Free the temporary buffer after being used */
4206         rte_free(buf);
4207
4208         return ret;
4209 }
4210
4211 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4212 #define QUEUE_NUM_PER_VF_ARG                    "queue-num-per-vf"
4213
4214 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4215                 const char *value,
4216                 void *opaque)
4217 {
4218         struct i40e_pf *pf;
4219         unsigned long num;
4220         char *end;
4221
4222         pf = (struct i40e_pf *)opaque;
4223         RTE_SET_USED(key);
4224
4225         errno = 0;
4226         num = strtoul(value, &end, 0);
4227         if (errno != 0 || end == value || *end != 0) {
4228                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4229                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4230                 return -(EINVAL);
4231         }
4232
4233         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4234                 pf->vf_nb_qp_max = (uint16_t)num;
4235         else
4236                 /* here return 0 to make next valid same argument work */
4237                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4238                             "power of 2 and equal or less than 16 !, Now it is "
4239                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4240
4241         return 0;
4242 }
4243
4244 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4245 {
4246         static const char * const valid_keys[] = {QUEUE_NUM_PER_VF_ARG, NULL};
4247         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4248         struct rte_kvargs *kvlist;
4249
4250         /* set default queue number per VF as 4 */
4251         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4252
4253         if (dev->device->devargs == NULL)
4254                 return 0;
4255
4256         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4257         if (kvlist == NULL)
4258                 return -(EINVAL);
4259
4260         if (rte_kvargs_count(kvlist, QUEUE_NUM_PER_VF_ARG) > 1)
4261                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4262                             "the first invalid or last valid one is used !",
4263                             QUEUE_NUM_PER_VF_ARG);
4264
4265         rte_kvargs_process(kvlist, QUEUE_NUM_PER_VF_ARG,
4266                            i40e_pf_parse_vf_queue_number_handler, pf);
4267
4268         rte_kvargs_free(kvlist);
4269
4270         return 0;
4271 }
4272
4273 static int
4274 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4275 {
4276         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4277         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4278         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4279         uint16_t qp_count = 0, vsi_count = 0;
4280
4281         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4282                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4283                 return -EINVAL;
4284         }
4285
4286         i40e_pf_config_vf_rxq_number(dev);
4287
4288         /* Add the parameter init for LFC */
4289         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4290         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4291         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4292
4293         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4294         pf->max_num_vsi = hw->func_caps.num_vsis;
4295         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4296         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4297
4298         /* FDir queue/VSI allocation */
4299         pf->fdir_qp_offset = 0;
4300         if (hw->func_caps.fd) {
4301                 pf->flags |= I40E_FLAG_FDIR;
4302                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4303         } else {
4304                 pf->fdir_nb_qps = 0;
4305         }
4306         qp_count += pf->fdir_nb_qps;
4307         vsi_count += 1;
4308
4309         /* LAN queue/VSI allocation */
4310         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4311         if (!hw->func_caps.rss) {
4312                 pf->lan_nb_qps = 1;
4313         } else {
4314                 pf->flags |= I40E_FLAG_RSS;
4315                 if (hw->mac.type == I40E_MAC_X722)
4316                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4317                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4318         }
4319         qp_count += pf->lan_nb_qps;
4320         vsi_count += 1;
4321
4322         /* VF queue/VSI allocation */
4323         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4324         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4325                 pf->flags |= I40E_FLAG_SRIOV;
4326                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4327                 pf->vf_num = pci_dev->max_vfs;
4328                 PMD_DRV_LOG(DEBUG,
4329                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4330                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4331         } else {
4332                 pf->vf_nb_qps = 0;
4333                 pf->vf_num = 0;
4334         }
4335         qp_count += pf->vf_nb_qps * pf->vf_num;
4336         vsi_count += pf->vf_num;
4337
4338         /* VMDq queue/VSI allocation */
4339         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4340         pf->vmdq_nb_qps = 0;
4341         pf->max_nb_vmdq_vsi = 0;
4342         if (hw->func_caps.vmdq) {
4343                 if (qp_count < hw->func_caps.num_tx_qp &&
4344                         vsi_count < hw->func_caps.num_vsis) {
4345                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4346                                 qp_count) / pf->vmdq_nb_qp_max;
4347
4348                         /* Limit the maximum number of VMDq vsi to the maximum
4349                          * ethdev can support
4350                          */
4351                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4352                                 hw->func_caps.num_vsis - vsi_count);
4353                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4354                                 ETH_64_POOLS);
4355                         if (pf->max_nb_vmdq_vsi) {
4356                                 pf->flags |= I40E_FLAG_VMDQ;
4357                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4358                                 PMD_DRV_LOG(DEBUG,
4359                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4360                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4361                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4362                         } else {
4363                                 PMD_DRV_LOG(INFO,
4364                                         "No enough queues left for VMDq");
4365                         }
4366                 } else {
4367                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4368                 }
4369         }
4370         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4371         vsi_count += pf->max_nb_vmdq_vsi;
4372
4373         if (hw->func_caps.dcb)
4374                 pf->flags |= I40E_FLAG_DCB;
4375
4376         if (qp_count > hw->func_caps.num_tx_qp) {
4377                 PMD_DRV_LOG(ERR,
4378                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4379                         qp_count, hw->func_caps.num_tx_qp);
4380                 return -EINVAL;
4381         }
4382         if (vsi_count > hw->func_caps.num_vsis) {
4383                 PMD_DRV_LOG(ERR,
4384                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4385                         vsi_count, hw->func_caps.num_vsis);
4386                 return -EINVAL;
4387         }
4388
4389         return 0;
4390 }
4391
4392 static int
4393 i40e_pf_get_switch_config(struct i40e_pf *pf)
4394 {
4395         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4396         struct i40e_aqc_get_switch_config_resp *switch_config;
4397         struct i40e_aqc_switch_config_element_resp *element;
4398         uint16_t start_seid = 0, num_reported;
4399         int ret;
4400
4401         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4402                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4403         if (!switch_config) {
4404                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4405                 return -ENOMEM;
4406         }
4407
4408         /* Get the switch configurations */
4409         ret = i40e_aq_get_switch_config(hw, switch_config,
4410                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4411         if (ret != I40E_SUCCESS) {
4412                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4413                 goto fail;
4414         }
4415         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4416         if (num_reported != 1) { /* The number should be 1 */
4417                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4418                 goto fail;
4419         }
4420
4421         /* Parse the switch configuration elements */
4422         element = &(switch_config->element[0]);
4423         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4424                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4425                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4426         } else
4427                 PMD_DRV_LOG(INFO, "Unknown element type");
4428
4429 fail:
4430         rte_free(switch_config);
4431
4432         return ret;
4433 }
4434
4435 static int
4436 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4437                         uint32_t num)
4438 {
4439         struct pool_entry *entry;
4440
4441         if (pool == NULL || num == 0)
4442                 return -EINVAL;
4443
4444         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4445         if (entry == NULL) {
4446                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4447                 return -ENOMEM;
4448         }
4449
4450         /* queue heap initialize */
4451         pool->num_free = num;
4452         pool->num_alloc = 0;
4453         pool->base = base;
4454         LIST_INIT(&pool->alloc_list);
4455         LIST_INIT(&pool->free_list);
4456
4457         /* Initialize element  */
4458         entry->base = 0;
4459         entry->len = num;
4460
4461         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4462         return 0;
4463 }
4464
4465 static void
4466 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4467 {
4468         struct pool_entry *entry, *next_entry;
4469
4470         if (pool == NULL)
4471                 return;
4472
4473         for (entry = LIST_FIRST(&pool->alloc_list);
4474                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4475                         entry = next_entry) {
4476                 LIST_REMOVE(entry, next);
4477                 rte_free(entry);
4478         }
4479
4480         for (entry = LIST_FIRST(&pool->free_list);
4481                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4482                         entry = next_entry) {
4483                 LIST_REMOVE(entry, next);
4484                 rte_free(entry);
4485         }
4486
4487         pool->num_free = 0;
4488         pool->num_alloc = 0;
4489         pool->base = 0;
4490         LIST_INIT(&pool->alloc_list);
4491         LIST_INIT(&pool->free_list);
4492 }
4493
4494 static int
4495 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4496                        uint32_t base)
4497 {
4498         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4499         uint32_t pool_offset;
4500         int insert;
4501
4502         if (pool == NULL) {
4503                 PMD_DRV_LOG(ERR, "Invalid parameter");
4504                 return -EINVAL;
4505         }
4506
4507         pool_offset = base - pool->base;
4508         /* Lookup in alloc list */
4509         LIST_FOREACH(entry, &pool->alloc_list, next) {
4510                 if (entry->base == pool_offset) {
4511                         valid_entry = entry;
4512                         LIST_REMOVE(entry, next);
4513                         break;
4514                 }
4515         }
4516
4517         /* Not find, return */
4518         if (valid_entry == NULL) {
4519                 PMD_DRV_LOG(ERR, "Failed to find entry");
4520                 return -EINVAL;
4521         }
4522
4523         /**
4524          * Found it, move it to free list  and try to merge.
4525          * In order to make merge easier, always sort it by qbase.
4526          * Find adjacent prev and last entries.
4527          */
4528         prev = next = NULL;
4529         LIST_FOREACH(entry, &pool->free_list, next) {
4530                 if (entry->base > valid_entry->base) {
4531                         next = entry;
4532                         break;
4533                 }
4534                 prev = entry;
4535         }
4536
4537         insert = 0;
4538         /* Try to merge with next one*/
4539         if (next != NULL) {
4540                 /* Merge with next one */
4541                 if (valid_entry->base + valid_entry->len == next->base) {
4542                         next->base = valid_entry->base;
4543                         next->len += valid_entry->len;
4544                         rte_free(valid_entry);
4545                         valid_entry = next;
4546                         insert = 1;
4547                 }
4548         }
4549
4550         if (prev != NULL) {
4551                 /* Merge with previous one */
4552                 if (prev->base + prev->len == valid_entry->base) {
4553                         prev->len += valid_entry->len;
4554                         /* If it merge with next one, remove next node */
4555                         if (insert == 1) {
4556                                 LIST_REMOVE(valid_entry, next);
4557                                 rte_free(valid_entry);
4558                         } else {
4559                                 rte_free(valid_entry);
4560                                 insert = 1;
4561                         }
4562                 }
4563         }
4564
4565         /* Not find any entry to merge, insert */
4566         if (insert == 0) {
4567                 if (prev != NULL)
4568                         LIST_INSERT_AFTER(prev, valid_entry, next);
4569                 else if (next != NULL)
4570                         LIST_INSERT_BEFORE(next, valid_entry, next);
4571                 else /* It's empty list, insert to head */
4572                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4573         }
4574
4575         pool->num_free += valid_entry->len;
4576         pool->num_alloc -= valid_entry->len;
4577
4578         return 0;
4579 }
4580
4581 static int
4582 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4583                        uint16_t num)
4584 {
4585         struct pool_entry *entry, *valid_entry;
4586
4587         if (pool == NULL || num == 0) {
4588                 PMD_DRV_LOG(ERR, "Invalid parameter");
4589                 return -EINVAL;
4590         }
4591
4592         if (pool->num_free < num) {
4593                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4594                             num, pool->num_free);
4595                 return -ENOMEM;
4596         }
4597
4598         valid_entry = NULL;
4599         /* Lookup  in free list and find most fit one */
4600         LIST_FOREACH(entry, &pool->free_list, next) {
4601                 if (entry->len >= num) {
4602                         /* Find best one */
4603                         if (entry->len == num) {
4604                                 valid_entry = entry;
4605                                 break;
4606                         }
4607                         if (valid_entry == NULL || valid_entry->len > entry->len)
4608                                 valid_entry = entry;
4609                 }
4610         }
4611
4612         /* Not find one to satisfy the request, return */
4613         if (valid_entry == NULL) {
4614                 PMD_DRV_LOG(ERR, "No valid entry found");
4615                 return -ENOMEM;
4616         }
4617         /**
4618          * The entry have equal queue number as requested,
4619          * remove it from alloc_list.
4620          */
4621         if (valid_entry->len == num) {
4622                 LIST_REMOVE(valid_entry, next);
4623         } else {
4624                 /**
4625                  * The entry have more numbers than requested,
4626                  * create a new entry for alloc_list and minus its
4627                  * queue base and number in free_list.
4628                  */
4629                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4630                 if (entry == NULL) {
4631                         PMD_DRV_LOG(ERR,
4632                                 "Failed to allocate memory for resource pool");
4633                         return -ENOMEM;
4634                 }
4635                 entry->base = valid_entry->base;
4636                 entry->len = num;
4637                 valid_entry->base += num;
4638                 valid_entry->len -= num;
4639                 valid_entry = entry;
4640         }
4641
4642         /* Insert it into alloc list, not sorted */
4643         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4644
4645         pool->num_free -= valid_entry->len;
4646         pool->num_alloc += valid_entry->len;
4647
4648         return valid_entry->base + pool->base;
4649 }
4650
4651 /**
4652  * bitmap_is_subset - Check whether src2 is subset of src1
4653  **/
4654 static inline int
4655 bitmap_is_subset(uint8_t src1, uint8_t src2)
4656 {
4657         return !((src1 ^ src2) & src2);
4658 }
4659
4660 static enum i40e_status_code
4661 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4662 {
4663         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4664
4665         /* If DCB is not supported, only default TC is supported */
4666         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4667                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4668                 return I40E_NOT_SUPPORTED;
4669         }
4670
4671         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4672                 PMD_DRV_LOG(ERR,
4673                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4674                         hw->func_caps.enabled_tcmap, enabled_tcmap);
4675                 return I40E_NOT_SUPPORTED;
4676         }
4677         return I40E_SUCCESS;
4678 }
4679
4680 int
4681 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
4682                                 struct i40e_vsi_vlan_pvid_info *info)
4683 {
4684         struct i40e_hw *hw;
4685         struct i40e_vsi_context ctxt;
4686         uint8_t vlan_flags = 0;
4687         int ret;
4688
4689         if (vsi == NULL || info == NULL) {
4690                 PMD_DRV_LOG(ERR, "invalid parameters");
4691                 return I40E_ERR_PARAM;
4692         }
4693
4694         if (info->on) {
4695                 vsi->info.pvid = info->config.pvid;
4696                 /**
4697                  * If insert pvid is enabled, only tagged pkts are
4698                  * allowed to be sent out.
4699                  */
4700                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
4701                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4702         } else {
4703                 vsi->info.pvid = 0;
4704                 if (info->config.reject.tagged == 0)
4705                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
4706
4707                 if (info->config.reject.untagged == 0)
4708                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
4709         }
4710         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
4711                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
4712         vsi->info.port_vlan_flags |= vlan_flags;
4713         vsi->info.valid_sections =
4714                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
4715         memset(&ctxt, 0, sizeof(ctxt));
4716         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4717         ctxt.seid = vsi->seid;
4718
4719         hw = I40E_VSI_TO_HW(vsi);
4720         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
4721         if (ret != I40E_SUCCESS)
4722                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
4723
4724         return ret;
4725 }
4726
4727 static int
4728 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4729 {
4730         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4731         int i, ret;
4732         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
4733
4734         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4735         if (ret != I40E_SUCCESS)
4736                 return ret;
4737
4738         if (!vsi->seid) {
4739                 PMD_DRV_LOG(ERR, "seid not valid");
4740                 return -EINVAL;
4741         }
4742
4743         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
4744         tc_bw_data.tc_valid_bits = enabled_tcmap;
4745         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4746                 tc_bw_data.tc_bw_credits[i] =
4747                         (enabled_tcmap & (1 << i)) ? 1 : 0;
4748
4749         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
4750         if (ret != I40E_SUCCESS) {
4751                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
4752                 return ret;
4753         }
4754
4755         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
4756                                         sizeof(vsi->info.qs_handle));
4757         return I40E_SUCCESS;
4758 }
4759
4760 static enum i40e_status_code
4761 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
4762                                  struct i40e_aqc_vsi_properties_data *info,
4763                                  uint8_t enabled_tcmap)
4764 {
4765         enum i40e_status_code ret;
4766         int i, total_tc = 0;
4767         uint16_t qpnum_per_tc, bsf, qp_idx;
4768
4769         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
4770         if (ret != I40E_SUCCESS)
4771                 return ret;
4772
4773         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
4774                 if (enabled_tcmap & (1 << i))
4775                         total_tc++;
4776         if (total_tc == 0)
4777                 total_tc = 1;
4778         vsi->enabled_tc = enabled_tcmap;
4779
4780         /* Number of queues per enabled TC */
4781         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
4782         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
4783         bsf = rte_bsf32(qpnum_per_tc);
4784
4785         /* Adjust the queue number to actual queues that can be applied */
4786         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
4787                 vsi->nb_qps = qpnum_per_tc * total_tc;
4788
4789         /**
4790          * Configure TC and queue mapping parameters, for enabled TC,
4791          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
4792          * default queue will serve it.
4793          */
4794         qp_idx = 0;
4795         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4796                 if (vsi->enabled_tc & (1 << i)) {
4797                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
4798                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
4799                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
4800                         qp_idx += qpnum_per_tc;
4801                 } else
4802                         info->tc_mapping[i] = 0;
4803         }
4804
4805         /* Associate queue number with VSI */
4806         if (vsi->type == I40E_VSI_SRIOV) {
4807                 info->mapping_flags |=
4808                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
4809                 for (i = 0; i < vsi->nb_qps; i++)
4810                         info->queue_mapping[i] =
4811                                 rte_cpu_to_le_16(vsi->base_queue + i);
4812         } else {
4813                 info->mapping_flags |=
4814                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
4815                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
4816         }
4817         info->valid_sections |=
4818                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
4819
4820         return I40E_SUCCESS;
4821 }
4822
4823 static int
4824 i40e_veb_release(struct i40e_veb *veb)
4825 {
4826         struct i40e_vsi *vsi;
4827         struct i40e_hw *hw;
4828
4829         if (veb == NULL)
4830                 return -EINVAL;
4831
4832         if (!TAILQ_EMPTY(&veb->head)) {
4833                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
4834                 return -EACCES;
4835         }
4836         /* associate_vsi field is NULL for floating VEB */
4837         if (veb->associate_vsi != NULL) {
4838                 vsi = veb->associate_vsi;
4839                 hw = I40E_VSI_TO_HW(vsi);
4840
4841                 vsi->uplink_seid = veb->uplink_seid;
4842                 vsi->veb = NULL;
4843         } else {
4844                 veb->associate_pf->main_vsi->floating_veb = NULL;
4845                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
4846         }
4847
4848         i40e_aq_delete_element(hw, veb->seid, NULL);
4849         rte_free(veb);
4850         return I40E_SUCCESS;
4851 }
4852
4853 /* Setup a veb */
4854 static struct i40e_veb *
4855 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
4856 {
4857         struct i40e_veb *veb;
4858         int ret;
4859         struct i40e_hw *hw;
4860
4861         if (pf == NULL) {
4862                 PMD_DRV_LOG(ERR,
4863                             "veb setup failed, associated PF shouldn't null");
4864                 return NULL;
4865         }
4866         hw = I40E_PF_TO_HW(pf);
4867
4868         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
4869         if (!veb) {
4870                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
4871                 goto fail;
4872         }
4873
4874         veb->associate_vsi = vsi;
4875         veb->associate_pf = pf;
4876         TAILQ_INIT(&veb->head);
4877         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
4878
4879         /* create floating veb if vsi is NULL */
4880         if (vsi != NULL) {
4881                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
4882                                       I40E_DEFAULT_TCMAP, false,
4883                                       &veb->seid, false, NULL);
4884         } else {
4885                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
4886                                       true, &veb->seid, false, NULL);
4887         }
4888
4889         if (ret != I40E_SUCCESS) {
4890                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
4891                             hw->aq.asq_last_status);
4892                 goto fail;
4893         }
4894         veb->enabled_tc = I40E_DEFAULT_TCMAP;
4895
4896         /* get statistics index */
4897         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
4898                                 &veb->stats_idx, NULL, NULL, NULL);
4899         if (ret != I40E_SUCCESS) {
4900                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
4901                             hw->aq.asq_last_status);
4902                 goto fail;
4903         }
4904         /* Get VEB bandwidth, to be implemented */
4905         /* Now associated vsi binding to the VEB, set uplink to this VEB */
4906         if (vsi)
4907                 vsi->uplink_seid = veb->seid;
4908
4909         return veb;
4910 fail:
4911         rte_free(veb);
4912         return NULL;
4913 }
4914
4915 int
4916 i40e_vsi_release(struct i40e_vsi *vsi)
4917 {
4918         struct i40e_pf *pf;
4919         struct i40e_hw *hw;
4920         struct i40e_vsi_list *vsi_list;
4921         void *temp;
4922         int ret;
4923         struct i40e_mac_filter *f;
4924         uint16_t user_param;
4925
4926         if (!vsi)
4927                 return I40E_SUCCESS;
4928
4929         if (!vsi->adapter)
4930                 return -EFAULT;
4931
4932         user_param = vsi->user_param;
4933
4934         pf = I40E_VSI_TO_PF(vsi);
4935         hw = I40E_VSI_TO_HW(vsi);
4936
4937         /* VSI has child to attach, release child first */
4938         if (vsi->veb) {
4939                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
4940                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4941                                 return -1;
4942                 }
4943                 i40e_veb_release(vsi->veb);
4944         }
4945
4946         if (vsi->floating_veb) {
4947                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
4948                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
4949                                 return -1;
4950                 }
4951         }
4952
4953         /* Remove all macvlan filters of the VSI */
4954         i40e_vsi_remove_all_macvlan_filter(vsi);
4955         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
4956                 rte_free(f);
4957
4958         if (vsi->type != I40E_VSI_MAIN &&
4959             ((vsi->type != I40E_VSI_SRIOV) ||
4960             !pf->floating_veb_list[user_param])) {
4961                 /* Remove vsi from parent's sibling list */
4962                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
4963                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4964                         return I40E_ERR_PARAM;
4965                 }
4966                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
4967                                 &vsi->sib_vsi_list, list);
4968
4969                 /* Remove all switch element of the VSI */
4970                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4971                 if (ret != I40E_SUCCESS)
4972                         PMD_DRV_LOG(ERR, "Failed to delete element");
4973         }
4974
4975         if ((vsi->type == I40E_VSI_SRIOV) &&
4976             pf->floating_veb_list[user_param]) {
4977                 /* Remove vsi from parent's sibling list */
4978                 if (vsi->parent_vsi == NULL ||
4979                     vsi->parent_vsi->floating_veb == NULL) {
4980                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
4981                         return I40E_ERR_PARAM;
4982                 }
4983                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
4984                              &vsi->sib_vsi_list, list);
4985
4986                 /* Remove all switch element of the VSI */
4987                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
4988                 if (ret != I40E_SUCCESS)
4989                         PMD_DRV_LOG(ERR, "Failed to delete element");
4990         }
4991
4992         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
4993
4994         if (vsi->type != I40E_VSI_SRIOV)
4995                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
4996         rte_free(vsi);
4997
4998         return I40E_SUCCESS;
4999 }
5000
5001 static int
5002 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5003 {
5004         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5005         struct i40e_aqc_remove_macvlan_element_data def_filter;
5006         struct i40e_mac_filter_info filter;
5007         int ret;
5008
5009         if (vsi->type != I40E_VSI_MAIN)
5010                 return I40E_ERR_CONFIG;
5011         memset(&def_filter, 0, sizeof(def_filter));
5012         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5013                                         ETH_ADDR_LEN);
5014         def_filter.vlan_tag = 0;
5015         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5016                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5017         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5018         if (ret != I40E_SUCCESS) {
5019                 struct i40e_mac_filter *f;
5020                 struct ether_addr *mac;
5021
5022                 PMD_DRV_LOG(DEBUG,
5023                             "Cannot remove the default macvlan filter");
5024                 /* It needs to add the permanent mac into mac list */
5025                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5026                 if (f == NULL) {
5027                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5028                         return I40E_ERR_NO_MEMORY;
5029                 }
5030                 mac = &f->mac_info.mac_addr;
5031                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5032                                 ETH_ADDR_LEN);
5033                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5034                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5035                 vsi->mac_num++;
5036
5037                 return ret;
5038         }
5039         rte_memcpy(&filter.mac_addr,
5040                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5041         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5042         return i40e_vsi_add_mac(vsi, &filter);
5043 }
5044
5045 /*
5046  * i40e_vsi_get_bw_config - Query VSI BW Information
5047  * @vsi: the VSI to be queried
5048  *
5049  * Returns 0 on success, negative value on failure
5050  */
5051 static enum i40e_status_code
5052 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5053 {
5054         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5055         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5056         struct i40e_hw *hw = &vsi->adapter->hw;
5057         i40e_status ret;
5058         int i;
5059         uint32_t bw_max;
5060
5061         memset(&bw_config, 0, sizeof(bw_config));
5062         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5063         if (ret != I40E_SUCCESS) {
5064                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5065                             hw->aq.asq_last_status);
5066                 return ret;
5067         }
5068
5069         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5070         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5071                                         &ets_sla_config, NULL);
5072         if (ret != I40E_SUCCESS) {
5073                 PMD_DRV_LOG(ERR,
5074                         "VSI failed to get TC bandwdith configuration %u",
5075                         hw->aq.asq_last_status);
5076                 return ret;
5077         }
5078
5079         /* store and print out BW info */
5080         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5081         vsi->bw_info.bw_max = bw_config.max_bw;
5082         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5083         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5084         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5085                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5086                      I40E_16_BIT_WIDTH);
5087         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5088                 vsi->bw_info.bw_ets_share_credits[i] =
5089                                 ets_sla_config.share_credits[i];
5090                 vsi->bw_info.bw_ets_credits[i] =
5091                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5092                 /* 4 bits per TC, 4th bit is reserved */
5093                 vsi->bw_info.bw_ets_max[i] =
5094                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5095                                   RTE_LEN2MASK(3, uint8_t));
5096                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5097                             vsi->bw_info.bw_ets_share_credits[i]);
5098                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5099                             vsi->bw_info.bw_ets_credits[i]);
5100                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5101                             vsi->bw_info.bw_ets_max[i]);
5102         }
5103
5104         return I40E_SUCCESS;
5105 }
5106
5107 /* i40e_enable_pf_lb
5108  * @pf: pointer to the pf structure
5109  *
5110  * allow loopback on pf
5111  */
5112 static inline void
5113 i40e_enable_pf_lb(struct i40e_pf *pf)
5114 {
5115         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5116         struct i40e_vsi_context ctxt;
5117         int ret;
5118
5119         /* Use the FW API if FW >= v5.0 */
5120         if (hw->aq.fw_maj_ver < 5) {
5121                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5122                 return;
5123         }
5124
5125         memset(&ctxt, 0, sizeof(ctxt));
5126         ctxt.seid = pf->main_vsi_seid;
5127         ctxt.pf_num = hw->pf_id;
5128         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5129         if (ret) {
5130                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5131                             ret, hw->aq.asq_last_status);
5132                 return;
5133         }
5134         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5135         ctxt.info.valid_sections =
5136                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5137         ctxt.info.switch_id |=
5138                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5139
5140         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5141         if (ret)
5142                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5143                             hw->aq.asq_last_status);
5144 }
5145
5146 /* Setup a VSI */
5147 struct i40e_vsi *
5148 i40e_vsi_setup(struct i40e_pf *pf,
5149                enum i40e_vsi_type type,
5150                struct i40e_vsi *uplink_vsi,
5151                uint16_t user_param)
5152 {
5153         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5154         struct i40e_vsi *vsi;
5155         struct i40e_mac_filter_info filter;
5156         int ret;
5157         struct i40e_vsi_context ctxt;
5158         struct ether_addr broadcast =
5159                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5160
5161         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5162             uplink_vsi == NULL) {
5163                 PMD_DRV_LOG(ERR,
5164                         "VSI setup failed, VSI link shouldn't be NULL");
5165                 return NULL;
5166         }
5167
5168         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5169                 PMD_DRV_LOG(ERR,
5170                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5171                 return NULL;
5172         }
5173
5174         /* two situations
5175          * 1.type is not MAIN and uplink vsi is not NULL
5176          * If uplink vsi didn't setup VEB, create one first under veb field
5177          * 2.type is SRIOV and the uplink is NULL
5178          * If floating VEB is NULL, create one veb under floating veb field
5179          */
5180
5181         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5182             uplink_vsi->veb == NULL) {
5183                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5184
5185                 if (uplink_vsi->veb == NULL) {
5186                         PMD_DRV_LOG(ERR, "VEB setup failed");
5187                         return NULL;
5188                 }
5189                 /* set ALLOWLOOPBACk on pf, when veb is created */
5190                 i40e_enable_pf_lb(pf);
5191         }
5192
5193         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5194             pf->main_vsi->floating_veb == NULL) {
5195                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5196
5197                 if (pf->main_vsi->floating_veb == NULL) {
5198                         PMD_DRV_LOG(ERR, "VEB setup failed");
5199                         return NULL;
5200                 }
5201         }
5202
5203         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5204         if (!vsi) {
5205                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5206                 return NULL;
5207         }
5208         TAILQ_INIT(&vsi->mac_list);
5209         vsi->type = type;
5210         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5211         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5212         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5213         vsi->user_param = user_param;
5214         vsi->vlan_anti_spoof_on = 0;
5215         vsi->vlan_filter_on = 0;
5216         /* Allocate queues */
5217         switch (vsi->type) {
5218         case I40E_VSI_MAIN  :
5219                 vsi->nb_qps = pf->lan_nb_qps;
5220                 break;
5221         case I40E_VSI_SRIOV :
5222                 vsi->nb_qps = pf->vf_nb_qps;
5223                 break;
5224         case I40E_VSI_VMDQ2:
5225                 vsi->nb_qps = pf->vmdq_nb_qps;
5226                 break;
5227         case I40E_VSI_FDIR:
5228                 vsi->nb_qps = pf->fdir_nb_qps;
5229                 break;
5230         default:
5231                 goto fail_mem;
5232         }
5233         /*
5234          * The filter status descriptor is reported in rx queue 0,
5235          * while the tx queue for fdir filter programming has no
5236          * such constraints, can be non-zero queues.
5237          * To simplify it, choose FDIR vsi use queue 0 pair.
5238          * To make sure it will use queue 0 pair, queue allocation
5239          * need be done before this function is called
5240          */
5241         if (type != I40E_VSI_FDIR) {
5242                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5243                         if (ret < 0) {
5244                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5245                                                 vsi->seid, ret);
5246                                 goto fail_mem;
5247                         }
5248                         vsi->base_queue = ret;
5249         } else
5250                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5251
5252         /* VF has MSIX interrupt in VF range, don't allocate here */
5253         if (type == I40E_VSI_MAIN) {
5254                 if (pf->support_multi_driver) {
5255                         /* If support multi-driver, need to use INT0 instead of
5256                          * allocating from msix pool. The Msix pool is init from
5257                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5258                          * to 1 without calling i40e_res_pool_alloc.
5259                          */
5260                         vsi->msix_intr = 0;
5261                         vsi->nb_msix = 1;
5262                 } else {
5263                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5264                                                   RTE_MIN(vsi->nb_qps,
5265                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5266                         if (ret < 0) {
5267                                 PMD_DRV_LOG(ERR,
5268                                             "VSI MAIN %d get heap failed %d",
5269                                             vsi->seid, ret);
5270                                 goto fail_queue_alloc;
5271                         }
5272                         vsi->msix_intr = ret;
5273                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5274                                                RTE_MAX_RXTX_INTR_VEC_ID);
5275                 }
5276         } else if (type != I40E_VSI_SRIOV) {
5277                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5278                 if (ret < 0) {
5279                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5280                         goto fail_queue_alloc;
5281                 }
5282                 vsi->msix_intr = ret;
5283                 vsi->nb_msix = 1;
5284         } else {
5285                 vsi->msix_intr = 0;
5286                 vsi->nb_msix = 0;
5287         }
5288
5289         /* Add VSI */
5290         if (type == I40E_VSI_MAIN) {
5291                 /* For main VSI, no need to add since it's default one */
5292                 vsi->uplink_seid = pf->mac_seid;
5293                 vsi->seid = pf->main_vsi_seid;
5294                 /* Bind queues with specific MSIX interrupt */
5295                 /**
5296                  * Needs 2 interrupt at least, one for misc cause which will
5297                  * enabled from OS side, Another for queues binding the
5298                  * interrupt from device side only.
5299                  */
5300
5301                 /* Get default VSI parameters from hardware */
5302                 memset(&ctxt, 0, sizeof(ctxt));
5303                 ctxt.seid = vsi->seid;
5304                 ctxt.pf_num = hw->pf_id;
5305                 ctxt.uplink_seid = vsi->uplink_seid;
5306                 ctxt.vf_num = 0;
5307                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5308                 if (ret != I40E_SUCCESS) {
5309                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5310                         goto fail_msix_alloc;
5311                 }
5312                 rte_memcpy(&vsi->info, &ctxt.info,
5313                         sizeof(struct i40e_aqc_vsi_properties_data));
5314                 vsi->vsi_id = ctxt.vsi_number;
5315                 vsi->info.valid_sections = 0;
5316
5317                 /* Configure tc, enabled TC0 only */
5318                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5319                         I40E_SUCCESS) {
5320                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5321                         goto fail_msix_alloc;
5322                 }
5323
5324                 /* TC, queue mapping */
5325                 memset(&ctxt, 0, sizeof(ctxt));
5326                 vsi->info.valid_sections |=
5327                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5328                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5329                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5330                 rte_memcpy(&ctxt.info, &vsi->info,
5331                         sizeof(struct i40e_aqc_vsi_properties_data));
5332                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5333                                                 I40E_DEFAULT_TCMAP);
5334                 if (ret != I40E_SUCCESS) {
5335                         PMD_DRV_LOG(ERR,
5336                                 "Failed to configure TC queue mapping");
5337                         goto fail_msix_alloc;
5338                 }
5339                 ctxt.seid = vsi->seid;
5340                 ctxt.pf_num = hw->pf_id;
5341                 ctxt.uplink_seid = vsi->uplink_seid;
5342                 ctxt.vf_num = 0;
5343
5344                 /* Update VSI parameters */
5345                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5346                 if (ret != I40E_SUCCESS) {
5347                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5348                         goto fail_msix_alloc;
5349                 }
5350
5351                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5352                                                 sizeof(vsi->info.tc_mapping));
5353                 rte_memcpy(&vsi->info.queue_mapping,
5354                                 &ctxt.info.queue_mapping,
5355                         sizeof(vsi->info.queue_mapping));
5356                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5357                 vsi->info.valid_sections = 0;
5358
5359                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5360                                 ETH_ADDR_LEN);
5361
5362                 /**
5363                  * Updating default filter settings are necessary to prevent
5364                  * reception of tagged packets.
5365                  * Some old firmware configurations load a default macvlan
5366                  * filter which accepts both tagged and untagged packets.
5367                  * The updating is to use a normal filter instead if needed.
5368                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5369                  * The firmware with correct configurations load the default
5370                  * macvlan filter which is expected and cannot be removed.
5371                  */
5372                 i40e_update_default_filter_setting(vsi);
5373                 i40e_config_qinq(hw, vsi);
5374         } else if (type == I40E_VSI_SRIOV) {
5375                 memset(&ctxt, 0, sizeof(ctxt));
5376                 /**
5377                  * For other VSI, the uplink_seid equals to uplink VSI's
5378                  * uplink_seid since they share same VEB
5379                  */
5380                 if (uplink_vsi == NULL)
5381                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5382                 else
5383                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5384                 ctxt.pf_num = hw->pf_id;
5385                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5386                 ctxt.uplink_seid = vsi->uplink_seid;
5387                 ctxt.connection_type = 0x1;
5388                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5389
5390                 /* Use the VEB configuration if FW >= v5.0 */
5391                 if (hw->aq.fw_maj_ver >= 5) {
5392                         /* Configure switch ID */
5393                         ctxt.info.valid_sections |=
5394                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5395                         ctxt.info.switch_id =
5396                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5397                 }
5398
5399                 /* Configure port/vlan */
5400                 ctxt.info.valid_sections |=
5401                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5402                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5403                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5404                                                 hw->func_caps.enabled_tcmap);
5405                 if (ret != I40E_SUCCESS) {
5406                         PMD_DRV_LOG(ERR,
5407                                 "Failed to configure TC queue mapping");
5408                         goto fail_msix_alloc;
5409                 }
5410
5411                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5412                 ctxt.info.valid_sections |=
5413                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5414                 /**
5415                  * Since VSI is not created yet, only configure parameter,
5416                  * will add vsi below.
5417                  */
5418
5419                 i40e_config_qinq(hw, vsi);
5420         } else if (type == I40E_VSI_VMDQ2) {
5421                 memset(&ctxt, 0, sizeof(ctxt));
5422                 /*
5423                  * For other VSI, the uplink_seid equals to uplink VSI's
5424                  * uplink_seid since they share same VEB
5425                  */
5426                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5427                 ctxt.pf_num = hw->pf_id;
5428                 ctxt.vf_num = 0;
5429                 ctxt.uplink_seid = vsi->uplink_seid;
5430                 ctxt.connection_type = 0x1;
5431                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5432
5433                 ctxt.info.valid_sections |=
5434                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5435                 /* user_param carries flag to enable loop back */
5436                 if (user_param) {
5437                         ctxt.info.switch_id =
5438                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5439                         ctxt.info.switch_id |=
5440                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5441                 }
5442
5443                 /* Configure port/vlan */
5444                 ctxt.info.valid_sections |=
5445                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5446                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5447                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5448                                                 I40E_DEFAULT_TCMAP);
5449                 if (ret != I40E_SUCCESS) {
5450                         PMD_DRV_LOG(ERR,
5451                                 "Failed to configure TC queue mapping");
5452                         goto fail_msix_alloc;
5453                 }
5454                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5455                 ctxt.info.valid_sections |=
5456                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5457         } else if (type == I40E_VSI_FDIR) {
5458                 memset(&ctxt, 0, sizeof(ctxt));
5459                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5460                 ctxt.pf_num = hw->pf_id;
5461                 ctxt.vf_num = 0;
5462                 ctxt.uplink_seid = vsi->uplink_seid;
5463                 ctxt.connection_type = 0x1;     /* regular data port */
5464                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5465                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5466                                                 I40E_DEFAULT_TCMAP);
5467                 if (ret != I40E_SUCCESS) {
5468                         PMD_DRV_LOG(ERR,
5469                                 "Failed to configure TC queue mapping.");
5470                         goto fail_msix_alloc;
5471                 }
5472                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5473                 ctxt.info.valid_sections |=
5474                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5475         } else {
5476                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5477                 goto fail_msix_alloc;
5478         }
5479
5480         if (vsi->type != I40E_VSI_MAIN) {
5481                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5482                 if (ret != I40E_SUCCESS) {
5483                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5484                                     hw->aq.asq_last_status);
5485                         goto fail_msix_alloc;
5486                 }
5487                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5488                 vsi->info.valid_sections = 0;
5489                 vsi->seid = ctxt.seid;
5490                 vsi->vsi_id = ctxt.vsi_number;
5491                 vsi->sib_vsi_list.vsi = vsi;
5492                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5493                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5494                                           &vsi->sib_vsi_list, list);
5495                 } else {
5496                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5497                                           &vsi->sib_vsi_list, list);
5498                 }
5499         }
5500
5501         /* MAC/VLAN configuration */
5502         rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
5503         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5504
5505         ret = i40e_vsi_add_mac(vsi, &filter);
5506         if (ret != I40E_SUCCESS) {
5507                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5508                 goto fail_msix_alloc;
5509         }
5510
5511         /* Get VSI BW information */
5512         i40e_vsi_get_bw_config(vsi);
5513         return vsi;
5514 fail_msix_alloc:
5515         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5516 fail_queue_alloc:
5517         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5518 fail_mem:
5519         rte_free(vsi);
5520         return NULL;
5521 }
5522
5523 /* Configure vlan filter on or off */
5524 int
5525 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5526 {
5527         int i, num;
5528         struct i40e_mac_filter *f;
5529         void *temp;
5530         struct i40e_mac_filter_info *mac_filter;
5531         enum rte_mac_filter_type desired_filter;
5532         int ret = I40E_SUCCESS;
5533
5534         if (on) {
5535                 /* Filter to match MAC and VLAN */
5536                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5537         } else {
5538                 /* Filter to match only MAC */
5539                 desired_filter = RTE_MAC_PERFECT_MATCH;
5540         }
5541
5542         num = vsi->mac_num;
5543
5544         mac_filter = rte_zmalloc("mac_filter_info_data",
5545                                  num * sizeof(*mac_filter), 0);
5546         if (mac_filter == NULL) {
5547                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5548                 return I40E_ERR_NO_MEMORY;
5549         }
5550
5551         i = 0;
5552
5553         /* Remove all existing mac */
5554         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5555                 mac_filter[i] = f->mac_info;
5556                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5557                 if (ret) {
5558                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5559                                     on ? "enable" : "disable");
5560                         goto DONE;
5561                 }
5562                 i++;
5563         }
5564
5565         /* Override with new filter */
5566         for (i = 0; i < num; i++) {
5567                 mac_filter[i].filter_type = desired_filter;
5568                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5569                 if (ret) {
5570                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5571                                     on ? "enable" : "disable");
5572                         goto DONE;
5573                 }
5574         }
5575
5576 DONE:
5577         rte_free(mac_filter);
5578         return ret;
5579 }
5580
5581 /* Configure vlan stripping on or off */
5582 int
5583 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5584 {
5585         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5586         struct i40e_vsi_context ctxt;
5587         uint8_t vlan_flags;
5588         int ret = I40E_SUCCESS;
5589
5590         /* Check if it has been already on or off */
5591         if (vsi->info.valid_sections &
5592                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5593                 if (on) {
5594                         if ((vsi->info.port_vlan_flags &
5595                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5596                                 return 0; /* already on */
5597                 } else {
5598                         if ((vsi->info.port_vlan_flags &
5599                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5600                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5601                                 return 0; /* already off */
5602                 }
5603         }
5604
5605         if (on)
5606                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5607         else
5608                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5609         vsi->info.valid_sections =
5610                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5611         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5612         vsi->info.port_vlan_flags |= vlan_flags;
5613         ctxt.seid = vsi->seid;
5614         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5615         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5616         if (ret)
5617                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5618                             on ? "enable" : "disable");
5619
5620         return ret;
5621 }
5622
5623 static int
5624 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5625 {
5626         struct rte_eth_dev_data *data = dev->data;
5627         int ret;
5628         int mask = 0;
5629
5630         /* Apply vlan offload setting */
5631         mask = ETH_VLAN_STRIP_MASK |
5632                ETH_VLAN_FILTER_MASK |
5633                ETH_VLAN_EXTEND_MASK;
5634         ret = i40e_vlan_offload_set(dev, mask);
5635         if (ret) {
5636                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5637                 return ret;
5638         }
5639
5640         /* Apply pvid setting */
5641         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5642                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5643         if (ret)
5644                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5645
5646         return ret;
5647 }
5648
5649 static int
5650 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5651 {
5652         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5653
5654         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5655 }
5656
5657 static int
5658 i40e_update_flow_control(struct i40e_hw *hw)
5659 {
5660 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5661         struct i40e_link_status link_status;
5662         uint32_t rxfc = 0, txfc = 0, reg;
5663         uint8_t an_info;
5664         int ret;
5665
5666         memset(&link_status, 0, sizeof(link_status));
5667         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5668         if (ret != I40E_SUCCESS) {
5669                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5670                 goto write_reg; /* Disable flow control */
5671         }
5672
5673         an_info = hw->phy.link_info.an_info;
5674         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
5675                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
5676                 ret = I40E_ERR_NOT_READY;
5677                 goto write_reg; /* Disable flow control */
5678         }
5679         /**
5680          * If link auto negotiation is enabled, flow control needs to
5681          * be configured according to it
5682          */
5683         switch (an_info & I40E_LINK_PAUSE_RXTX) {
5684         case I40E_LINK_PAUSE_RXTX:
5685                 rxfc = 1;
5686                 txfc = 1;
5687                 hw->fc.current_mode = I40E_FC_FULL;
5688                 break;
5689         case I40E_AQ_LINK_PAUSE_RX:
5690                 rxfc = 1;
5691                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
5692                 break;
5693         case I40E_AQ_LINK_PAUSE_TX:
5694                 txfc = 1;
5695                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
5696                 break;
5697         default:
5698                 hw->fc.current_mode = I40E_FC_NONE;
5699                 break;
5700         }
5701
5702 write_reg:
5703         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
5704                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
5705         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
5706         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
5707         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
5708         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
5709
5710         return ret;
5711 }
5712
5713 /* PF setup */
5714 static int
5715 i40e_pf_setup(struct i40e_pf *pf)
5716 {
5717         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5718         struct i40e_filter_control_settings settings;
5719         struct i40e_vsi *vsi;
5720         int ret;
5721
5722         /* Clear all stats counters */
5723         pf->offset_loaded = FALSE;
5724         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
5725         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
5726         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
5727         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
5728
5729         ret = i40e_pf_get_switch_config(pf);
5730         if (ret != I40E_SUCCESS) {
5731                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
5732                 return ret;
5733         }
5734         if (pf->flags & I40E_FLAG_FDIR) {
5735                 /* make queue allocated first, let FDIR use queue pair 0*/
5736                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
5737                 if (ret != I40E_FDIR_QUEUE_ID) {
5738                         PMD_DRV_LOG(ERR,
5739                                 "queue allocation fails for FDIR: ret =%d",
5740                                 ret);
5741                         pf->flags &= ~I40E_FLAG_FDIR;
5742                 }
5743         }
5744         /*  main VSI setup */
5745         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
5746         if (!vsi) {
5747                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
5748                 return I40E_ERR_NOT_READY;
5749         }
5750         pf->main_vsi = vsi;
5751
5752         /* Configure filter control */
5753         memset(&settings, 0, sizeof(settings));
5754         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
5755                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
5756         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
5757                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
5758         else {
5759                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
5760                         hw->func_caps.rss_table_size);
5761                 return I40E_ERR_PARAM;
5762         }
5763         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
5764                 hw->func_caps.rss_table_size);
5765         pf->hash_lut_size = hw->func_caps.rss_table_size;
5766
5767         /* Enable ethtype and macvlan filters */
5768         settings.enable_ethtype = TRUE;
5769         settings.enable_macvlan = TRUE;
5770         ret = i40e_set_filter_control(hw, &settings);
5771         if (ret)
5772                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
5773                                                                 ret);
5774
5775         /* Update flow control according to the auto negotiation */
5776         i40e_update_flow_control(hw);
5777
5778         return I40E_SUCCESS;
5779 }
5780
5781 int
5782 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5783 {
5784         uint32_t reg;
5785         uint16_t j;
5786
5787         /**
5788          * Set or clear TX Queue Disable flags,
5789          * which is required by hardware.
5790          */
5791         i40e_pre_tx_queue_cfg(hw, q_idx, on);
5792         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
5793
5794         /* Wait until the request is finished */
5795         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5796                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5797                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5798                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5799                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
5800                                                         & 0x1))) {
5801                         break;
5802                 }
5803         }
5804         if (on) {
5805                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
5806                         return I40E_SUCCESS; /* already on, skip next steps */
5807
5808                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
5809                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
5810         } else {
5811                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5812                         return I40E_SUCCESS; /* already off, skip next steps */
5813                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
5814         }
5815         /* Write the register */
5816         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
5817         /* Check the result */
5818         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5819                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5820                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
5821                 if (on) {
5822                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5823                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
5824                                 break;
5825                 } else {
5826                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
5827                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
5828                                 break;
5829                 }
5830         }
5831         /* Check if it is timeout */
5832         if (j >= I40E_CHK_Q_ENA_COUNT) {
5833                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
5834                             (on ? "enable" : "disable"), q_idx);
5835                 return I40E_ERR_TIMEOUT;
5836         }
5837
5838         return I40E_SUCCESS;
5839 }
5840
5841 /* Swith on or off the tx queues */
5842 static int
5843 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
5844 {
5845         struct rte_eth_dev_data *dev_data = pf->dev_data;
5846         struct i40e_tx_queue *txq;
5847         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5848         uint16_t i;
5849         int ret;
5850
5851         for (i = 0; i < dev_data->nb_tx_queues; i++) {
5852                 txq = dev_data->tx_queues[i];
5853                 /* Don't operate the queue if not configured or
5854                  * if starting only per queue */
5855                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
5856                         continue;
5857                 if (on)
5858                         ret = i40e_dev_tx_queue_start(dev, i);
5859                 else
5860                         ret = i40e_dev_tx_queue_stop(dev, i);
5861                 if ( ret != I40E_SUCCESS)
5862                         return ret;
5863         }
5864
5865         return I40E_SUCCESS;
5866 }
5867
5868 int
5869 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
5870 {
5871         uint32_t reg;
5872         uint16_t j;
5873
5874         /* Wait until the request is finished */
5875         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5876                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5877                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5878                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
5879                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
5880                         break;
5881         }
5882
5883         if (on) {
5884                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
5885                         return I40E_SUCCESS; /* Already on, skip next steps */
5886                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
5887         } else {
5888                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5889                         return I40E_SUCCESS; /* Already off, skip next steps */
5890                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
5891         }
5892
5893         /* Write the register */
5894         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
5895         /* Check the result */
5896         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
5897                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
5898                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
5899                 if (on) {
5900                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5901                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
5902                                 break;
5903                 } else {
5904                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
5905                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
5906                                 break;
5907                 }
5908         }
5909
5910         /* Check if it is timeout */
5911         if (j >= I40E_CHK_Q_ENA_COUNT) {
5912                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
5913                             (on ? "enable" : "disable"), q_idx);
5914                 return I40E_ERR_TIMEOUT;
5915         }
5916
5917         return I40E_SUCCESS;
5918 }
5919 /* Switch on or off the rx queues */
5920 static int
5921 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
5922 {
5923         struct rte_eth_dev_data *dev_data = pf->dev_data;
5924         struct i40e_rx_queue *rxq;
5925         struct rte_eth_dev *dev = pf->adapter->eth_dev;
5926         uint16_t i;
5927         int ret;
5928
5929         for (i = 0; i < dev_data->nb_rx_queues; i++) {
5930                 rxq = dev_data->rx_queues[i];
5931                 /* Don't operate the queue if not configured or
5932                  * if starting only per queue */
5933                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
5934                         continue;
5935                 if (on)
5936                         ret = i40e_dev_rx_queue_start(dev, i);
5937                 else
5938                         ret = i40e_dev_rx_queue_stop(dev, i);
5939                 if (ret != I40E_SUCCESS)
5940                         return ret;
5941         }
5942
5943         return I40E_SUCCESS;
5944 }
5945
5946 /* Switch on or off all the rx/tx queues */
5947 int
5948 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
5949 {
5950         int ret;
5951
5952         if (on) {
5953                 /* enable rx queues before enabling tx queues */
5954                 ret = i40e_dev_switch_rx_queues(pf, on);
5955                 if (ret) {
5956                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
5957                         return ret;
5958                 }
5959                 ret = i40e_dev_switch_tx_queues(pf, on);
5960         } else {
5961                 /* Stop tx queues before stopping rx queues */
5962                 ret = i40e_dev_switch_tx_queues(pf, on);
5963                 if (ret) {
5964                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
5965                         return ret;
5966                 }
5967                 ret = i40e_dev_switch_rx_queues(pf, on);
5968         }
5969
5970         return ret;
5971 }
5972
5973 /* Initialize VSI for TX */
5974 static int
5975 i40e_dev_tx_init(struct i40e_pf *pf)
5976 {
5977         struct rte_eth_dev_data *data = pf->dev_data;
5978         uint16_t i;
5979         uint32_t ret = I40E_SUCCESS;
5980         struct i40e_tx_queue *txq;
5981
5982         for (i = 0; i < data->nb_tx_queues; i++) {
5983                 txq = data->tx_queues[i];
5984                 if (!txq || !txq->q_set)
5985                         continue;
5986                 ret = i40e_tx_queue_init(txq);
5987                 if (ret != I40E_SUCCESS)
5988                         break;
5989         }
5990         if (ret == I40E_SUCCESS)
5991                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
5992                                      ->eth_dev);
5993
5994         return ret;
5995 }
5996
5997 /* Initialize VSI for RX */
5998 static int
5999 i40e_dev_rx_init(struct i40e_pf *pf)
6000 {
6001         struct rte_eth_dev_data *data = pf->dev_data;
6002         int ret = I40E_SUCCESS;
6003         uint16_t i;
6004         struct i40e_rx_queue *rxq;
6005
6006         i40e_pf_config_mq_rx(pf);
6007         for (i = 0; i < data->nb_rx_queues; i++) {
6008                 rxq = data->rx_queues[i];
6009                 if (!rxq || !rxq->q_set)
6010                         continue;
6011
6012                 ret = i40e_rx_queue_init(rxq);
6013                 if (ret != I40E_SUCCESS) {
6014                         PMD_DRV_LOG(ERR,
6015                                 "Failed to do RX queue initialization");
6016                         break;
6017                 }
6018         }
6019         if (ret == I40E_SUCCESS)
6020                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6021                                      ->eth_dev);
6022
6023         return ret;
6024 }
6025
6026 static int
6027 i40e_dev_rxtx_init(struct i40e_pf *pf)
6028 {
6029         int err;
6030
6031         err = i40e_dev_tx_init(pf);
6032         if (err) {
6033                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6034                 return err;
6035         }
6036         err = i40e_dev_rx_init(pf);
6037         if (err) {
6038                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6039                 return err;
6040         }
6041
6042         return err;
6043 }
6044
6045 static int
6046 i40e_vmdq_setup(struct rte_eth_dev *dev)
6047 {
6048         struct rte_eth_conf *conf = &dev->data->dev_conf;
6049         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6050         int i, err, conf_vsis, j, loop;
6051         struct i40e_vsi *vsi;
6052         struct i40e_vmdq_info *vmdq_info;
6053         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6054         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6055
6056         /*
6057          * Disable interrupt to avoid message from VF. Furthermore, it will
6058          * avoid race condition in VSI creation/destroy.
6059          */
6060         i40e_pf_disable_irq0(hw);
6061
6062         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6063                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6064                 return -ENOTSUP;
6065         }
6066
6067         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6068         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6069                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6070                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6071                         pf->max_nb_vmdq_vsi);
6072                 return -ENOTSUP;
6073         }
6074
6075         if (pf->vmdq != NULL) {
6076                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6077                 return 0;
6078         }
6079
6080         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6081                                 sizeof(*vmdq_info) * conf_vsis, 0);
6082
6083         if (pf->vmdq == NULL) {
6084                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6085                 return -ENOMEM;
6086         }
6087
6088         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6089
6090         /* Create VMDQ VSI */
6091         for (i = 0; i < conf_vsis; i++) {
6092                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6093                                 vmdq_conf->enable_loop_back);
6094                 if (vsi == NULL) {
6095                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6096                         err = -1;
6097                         goto err_vsi_setup;
6098                 }
6099                 vmdq_info = &pf->vmdq[i];
6100                 vmdq_info->pf = pf;
6101                 vmdq_info->vsi = vsi;
6102         }
6103         pf->nb_cfg_vmdq_vsi = conf_vsis;
6104
6105         /* Configure Vlan */
6106         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6107         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6108                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6109                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6110                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6111                                         vmdq_conf->pool_map[i].vlan_id, j);
6112
6113                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6114                                                 vmdq_conf->pool_map[i].vlan_id);
6115                                 if (err) {
6116                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6117                                         err = -1;
6118                                         goto err_vsi_setup;
6119                                 }
6120                         }
6121                 }
6122         }
6123
6124         i40e_pf_enable_irq0(hw);
6125
6126         return 0;
6127
6128 err_vsi_setup:
6129         for (i = 0; i < conf_vsis; i++)
6130                 if (pf->vmdq[i].vsi == NULL)
6131                         break;
6132                 else
6133                         i40e_vsi_release(pf->vmdq[i].vsi);
6134
6135         rte_free(pf->vmdq);
6136         pf->vmdq = NULL;
6137         i40e_pf_enable_irq0(hw);
6138         return err;
6139 }
6140
6141 static void
6142 i40e_stat_update_32(struct i40e_hw *hw,
6143                    uint32_t reg,
6144                    bool offset_loaded,
6145                    uint64_t *offset,
6146                    uint64_t *stat)
6147 {
6148         uint64_t new_data;
6149
6150         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6151         if (!offset_loaded)
6152                 *offset = new_data;
6153
6154         if (new_data >= *offset)
6155                 *stat = (uint64_t)(new_data - *offset);
6156         else
6157                 *stat = (uint64_t)((new_data +
6158                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6159 }
6160
6161 static void
6162 i40e_stat_update_48(struct i40e_hw *hw,
6163                    uint32_t hireg,
6164                    uint32_t loreg,
6165                    bool offset_loaded,
6166                    uint64_t *offset,
6167                    uint64_t *stat)
6168 {
6169         uint64_t new_data;
6170
6171         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6172         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6173                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6174
6175         if (!offset_loaded)
6176                 *offset = new_data;
6177
6178         if (new_data >= *offset)
6179                 *stat = new_data - *offset;
6180         else
6181                 *stat = (uint64_t)((new_data +
6182                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6183
6184         *stat &= I40E_48_BIT_MASK;
6185 }
6186
6187 /* Disable IRQ0 */
6188 void
6189 i40e_pf_disable_irq0(struct i40e_hw *hw)
6190 {
6191         /* Disable all interrupt types */
6192         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6193                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6194         I40E_WRITE_FLUSH(hw);
6195 }
6196
6197 /* Enable IRQ0 */
6198 void
6199 i40e_pf_enable_irq0(struct i40e_hw *hw)
6200 {
6201         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6202                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6203                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6204                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6205         I40E_WRITE_FLUSH(hw);
6206 }
6207
6208 static void
6209 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6210 {
6211         /* read pending request and disable first */
6212         i40e_pf_disable_irq0(hw);
6213         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6214         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6215                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6216
6217         if (no_queue)
6218                 /* Link no queues with irq0 */
6219                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6220                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6221 }
6222
6223 static void
6224 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6225 {
6226         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6227         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6228         int i;
6229         uint16_t abs_vf_id;
6230         uint32_t index, offset, val;
6231
6232         if (!pf->vfs)
6233                 return;
6234         /**
6235          * Try to find which VF trigger a reset, use absolute VF id to access
6236          * since the reg is global register.
6237          */
6238         for (i = 0; i < pf->vf_num; i++) {
6239                 abs_vf_id = hw->func_caps.vf_base_id + i;
6240                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6241                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6242                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6243                 /* VFR event occurred */
6244                 if (val & (0x1 << offset)) {
6245                         int ret;
6246
6247                         /* Clear the event first */
6248                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6249                                                         (0x1 << offset));
6250                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6251                         /**
6252                          * Only notify a VF reset event occurred,
6253                          * don't trigger another SW reset
6254                          */
6255                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6256                         if (ret != I40E_SUCCESS)
6257                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6258                 }
6259         }
6260 }
6261
6262 static void
6263 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6264 {
6265         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6266         int i;
6267
6268         for (i = 0; i < pf->vf_num; i++)
6269                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6270 }
6271
6272 static void
6273 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6274 {
6275         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6276         struct i40e_arq_event_info info;
6277         uint16_t pending, opcode;
6278         int ret;
6279
6280         info.buf_len = I40E_AQ_BUF_SZ;
6281         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6282         if (!info.msg_buf) {
6283                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6284                 return;
6285         }
6286
6287         pending = 1;
6288         while (pending) {
6289                 ret = i40e_clean_arq_element(hw, &info, &pending);
6290
6291                 if (ret != I40E_SUCCESS) {
6292                         PMD_DRV_LOG(INFO,
6293                                 "Failed to read msg from AdminQ, aq_err: %u",
6294                                 hw->aq.asq_last_status);
6295                         break;
6296                 }
6297                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6298
6299                 switch (opcode) {
6300                 case i40e_aqc_opc_send_msg_to_pf:
6301                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6302                         i40e_pf_host_handle_vf_msg(dev,
6303                                         rte_le_to_cpu_16(info.desc.retval),
6304                                         rte_le_to_cpu_32(info.desc.cookie_high),
6305                                         rte_le_to_cpu_32(info.desc.cookie_low),
6306                                         info.msg_buf,
6307                                         info.msg_len);
6308                         break;
6309                 case i40e_aqc_opc_get_link_status:
6310                         ret = i40e_dev_link_update(dev, 0);
6311                         if (!ret)
6312                                 _rte_eth_dev_callback_process(dev,
6313                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6314                         break;
6315                 default:
6316                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6317                                     opcode);
6318                         break;
6319                 }
6320         }
6321         rte_free(info.msg_buf);
6322 }
6323
6324 /**
6325  * Interrupt handler triggered by NIC  for handling
6326  * specific interrupt.
6327  *
6328  * @param handle
6329  *  Pointer to interrupt handle.
6330  * @param param
6331  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6332  *
6333  * @return
6334  *  void
6335  */
6336 static void
6337 i40e_dev_interrupt_handler(void *param)
6338 {
6339         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6340         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6341         uint32_t icr0;
6342
6343         /* Disable interrupt */
6344         i40e_pf_disable_irq0(hw);
6345
6346         /* read out interrupt causes */
6347         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6348
6349         /* No interrupt event indicated */
6350         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6351                 PMD_DRV_LOG(INFO, "No interrupt event");
6352                 goto done;
6353         }
6354         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6355                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6356         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6357                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6358         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6359                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6360         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6361                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6362         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6363                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6364         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6365                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6366         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6367                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6368
6369         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6370                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6371                 i40e_dev_handle_vfr_event(dev);
6372         }
6373         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6374                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6375                 i40e_dev_handle_aq_msg(dev);
6376         }
6377
6378 done:
6379         /* Enable interrupt */
6380         i40e_pf_enable_irq0(hw);
6381         rte_intr_enable(dev->intr_handle);
6382 }
6383
6384 int
6385 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6386                          struct i40e_macvlan_filter *filter,
6387                          int total)
6388 {
6389         int ele_num, ele_buff_size;
6390         int num, actual_num, i;
6391         uint16_t flags;
6392         int ret = I40E_SUCCESS;
6393         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6394         struct i40e_aqc_add_macvlan_element_data *req_list;
6395
6396         if (filter == NULL  || total == 0)
6397                 return I40E_ERR_PARAM;
6398         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6399         ele_buff_size = hw->aq.asq_buf_size;
6400
6401         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6402         if (req_list == NULL) {
6403                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6404                 return I40E_ERR_NO_MEMORY;
6405         }
6406
6407         num = 0;
6408         do {
6409                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6410                 memset(req_list, 0, ele_buff_size);
6411
6412                 for (i = 0; i < actual_num; i++) {
6413                         rte_memcpy(req_list[i].mac_addr,
6414                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6415                         req_list[i].vlan_tag =
6416                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6417
6418                         switch (filter[num + i].filter_type) {
6419                         case RTE_MAC_PERFECT_MATCH:
6420                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6421                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6422                                 break;
6423                         case RTE_MACVLAN_PERFECT_MATCH:
6424                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6425                                 break;
6426                         case RTE_MAC_HASH_MATCH:
6427                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6428                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6429                                 break;
6430                         case RTE_MACVLAN_HASH_MATCH:
6431                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6432                                 break;
6433                         default:
6434                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6435                                 ret = I40E_ERR_PARAM;
6436                                 goto DONE;
6437                         }
6438
6439                         req_list[i].queue_number = 0;
6440
6441                         req_list[i].flags = rte_cpu_to_le_16(flags);
6442                 }
6443
6444                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6445                                                 actual_num, NULL);
6446                 if (ret != I40E_SUCCESS) {
6447                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6448                         goto DONE;
6449                 }
6450                 num += actual_num;
6451         } while (num < total);
6452
6453 DONE:
6454         rte_free(req_list);
6455         return ret;
6456 }
6457
6458 int
6459 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6460                             struct i40e_macvlan_filter *filter,
6461                             int total)
6462 {
6463         int ele_num, ele_buff_size;
6464         int num, actual_num, i;
6465         uint16_t flags;
6466         int ret = I40E_SUCCESS;
6467         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6468         struct i40e_aqc_remove_macvlan_element_data *req_list;
6469
6470         if (filter == NULL  || total == 0)
6471                 return I40E_ERR_PARAM;
6472
6473         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6474         ele_buff_size = hw->aq.asq_buf_size;
6475
6476         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6477         if (req_list == NULL) {
6478                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6479                 return I40E_ERR_NO_MEMORY;
6480         }
6481
6482         num = 0;
6483         do {
6484                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6485                 memset(req_list, 0, ele_buff_size);
6486
6487                 for (i = 0; i < actual_num; i++) {
6488                         rte_memcpy(req_list[i].mac_addr,
6489                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6490                         req_list[i].vlan_tag =
6491                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6492
6493                         switch (filter[num + i].filter_type) {
6494                         case RTE_MAC_PERFECT_MATCH:
6495                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6496                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6497                                 break;
6498                         case RTE_MACVLAN_PERFECT_MATCH:
6499                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6500                                 break;
6501                         case RTE_MAC_HASH_MATCH:
6502                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6503                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6504                                 break;
6505                         case RTE_MACVLAN_HASH_MATCH:
6506                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6507                                 break;
6508                         default:
6509                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6510                                 ret = I40E_ERR_PARAM;
6511                                 goto DONE;
6512                         }
6513                         req_list[i].flags = rte_cpu_to_le_16(flags);
6514                 }
6515
6516                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6517                                                 actual_num, NULL);
6518                 if (ret != I40E_SUCCESS) {
6519                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6520                         goto DONE;
6521                 }
6522                 num += actual_num;
6523         } while (num < total);
6524
6525 DONE:
6526         rte_free(req_list);
6527         return ret;
6528 }
6529
6530 /* Find out specific MAC filter */
6531 static struct i40e_mac_filter *
6532 i40e_find_mac_filter(struct i40e_vsi *vsi,
6533                          struct ether_addr *macaddr)
6534 {
6535         struct i40e_mac_filter *f;
6536
6537         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6538                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6539                         return f;
6540         }
6541
6542         return NULL;
6543 }
6544
6545 static bool
6546 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6547                          uint16_t vlan_id)
6548 {
6549         uint32_t vid_idx, vid_bit;
6550
6551         if (vlan_id > ETH_VLAN_ID_MAX)
6552                 return 0;
6553
6554         vid_idx = I40E_VFTA_IDX(vlan_id);
6555         vid_bit = I40E_VFTA_BIT(vlan_id);
6556
6557         if (vsi->vfta[vid_idx] & vid_bit)
6558                 return 1;
6559         else
6560                 return 0;
6561 }
6562
6563 static void
6564 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6565                        uint16_t vlan_id, bool on)
6566 {
6567         uint32_t vid_idx, vid_bit;
6568
6569         vid_idx = I40E_VFTA_IDX(vlan_id);
6570         vid_bit = I40E_VFTA_BIT(vlan_id);
6571
6572         if (on)
6573                 vsi->vfta[vid_idx] |= vid_bit;
6574         else
6575                 vsi->vfta[vid_idx] &= ~vid_bit;
6576 }
6577
6578 void
6579 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6580                      uint16_t vlan_id, bool on)
6581 {
6582         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6583         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6584         int ret;
6585
6586         if (vlan_id > ETH_VLAN_ID_MAX)
6587                 return;
6588
6589         i40e_store_vlan_filter(vsi, vlan_id, on);
6590
6591         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6592                 return;
6593
6594         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6595
6596         if (on) {
6597                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6598                                        &vlan_data, 1, NULL);
6599                 if (ret != I40E_SUCCESS)
6600                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6601         } else {
6602                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6603                                           &vlan_data, 1, NULL);
6604                 if (ret != I40E_SUCCESS)
6605                         PMD_DRV_LOG(ERR,
6606                                     "Failed to remove vlan filter");
6607         }
6608 }
6609
6610 /**
6611  * Find all vlan options for specific mac addr,
6612  * return with actual vlan found.
6613  */
6614 int
6615 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6616                            struct i40e_macvlan_filter *mv_f,
6617                            int num, struct ether_addr *addr)
6618 {
6619         int i;
6620         uint32_t j, k;
6621
6622         /**
6623          * Not to use i40e_find_vlan_filter to decrease the loop time,
6624          * although the code looks complex.
6625           */
6626         if (num < vsi->vlan_num)
6627                 return I40E_ERR_PARAM;
6628
6629         i = 0;
6630         for (j = 0; j < I40E_VFTA_SIZE; j++) {
6631                 if (vsi->vfta[j]) {
6632                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
6633                                 if (vsi->vfta[j] & (1 << k)) {
6634                                         if (i > num - 1) {
6635                                                 PMD_DRV_LOG(ERR,
6636                                                         "vlan number doesn't match");
6637                                                 return I40E_ERR_PARAM;
6638                                         }
6639                                         rte_memcpy(&mv_f[i].macaddr,
6640                                                         addr, ETH_ADDR_LEN);
6641                                         mv_f[i].vlan_id =
6642                                                 j * I40E_UINT32_BIT_SIZE + k;
6643                                         i++;
6644                                 }
6645                         }
6646                 }
6647         }
6648         return I40E_SUCCESS;
6649 }
6650
6651 static inline int
6652 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
6653                            struct i40e_macvlan_filter *mv_f,
6654                            int num,
6655                            uint16_t vlan)
6656 {
6657         int i = 0;
6658         struct i40e_mac_filter *f;
6659
6660         if (num < vsi->mac_num)
6661                 return I40E_ERR_PARAM;
6662
6663         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6664                 if (i > num - 1) {
6665                         PMD_DRV_LOG(ERR, "buffer number not match");
6666                         return I40E_ERR_PARAM;
6667                 }
6668                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6669                                 ETH_ADDR_LEN);
6670                 mv_f[i].vlan_id = vlan;
6671                 mv_f[i].filter_type = f->mac_info.filter_type;
6672                 i++;
6673         }
6674
6675         return I40E_SUCCESS;
6676 }
6677
6678 static int
6679 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
6680 {
6681         int i, j, num;
6682         struct i40e_mac_filter *f;
6683         struct i40e_macvlan_filter *mv_f;
6684         int ret = I40E_SUCCESS;
6685
6686         if (vsi == NULL || vsi->mac_num == 0)
6687                 return I40E_ERR_PARAM;
6688
6689         /* Case that no vlan is set */
6690         if (vsi->vlan_num == 0)
6691                 num = vsi->mac_num;
6692         else
6693                 num = vsi->mac_num * vsi->vlan_num;
6694
6695         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
6696         if (mv_f == NULL) {
6697                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6698                 return I40E_ERR_NO_MEMORY;
6699         }
6700
6701         i = 0;
6702         if (vsi->vlan_num == 0) {
6703                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6704                         rte_memcpy(&mv_f[i].macaddr,
6705                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
6706                         mv_f[i].filter_type = f->mac_info.filter_type;
6707                         mv_f[i].vlan_id = 0;
6708                         i++;
6709                 }
6710         } else {
6711                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
6712                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
6713                                         vsi->vlan_num, &f->mac_info.mac_addr);
6714                         if (ret != I40E_SUCCESS)
6715                                 goto DONE;
6716                         for (j = i; j < i + vsi->vlan_num; j++)
6717                                 mv_f[j].filter_type = f->mac_info.filter_type;
6718                         i += vsi->vlan_num;
6719                 }
6720         }
6721
6722         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
6723 DONE:
6724         rte_free(mv_f);
6725
6726         return ret;
6727 }
6728
6729 int
6730 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6731 {
6732         struct i40e_macvlan_filter *mv_f;
6733         int mac_num;
6734         int ret = I40E_SUCCESS;
6735
6736         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
6737                 return I40E_ERR_PARAM;
6738
6739         /* If it's already set, just return */
6740         if (i40e_find_vlan_filter(vsi,vlan))
6741                 return I40E_SUCCESS;
6742
6743         mac_num = vsi->mac_num;
6744
6745         if (mac_num == 0) {
6746                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6747                 return I40E_ERR_PARAM;
6748         }
6749
6750         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6751
6752         if (mv_f == NULL) {
6753                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6754                 return I40E_ERR_NO_MEMORY;
6755         }
6756
6757         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6758
6759         if (ret != I40E_SUCCESS)
6760                 goto DONE;
6761
6762         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6763
6764         if (ret != I40E_SUCCESS)
6765                 goto DONE;
6766
6767         i40e_set_vlan_filter(vsi, vlan, 1);
6768
6769         vsi->vlan_num++;
6770         ret = I40E_SUCCESS;
6771 DONE:
6772         rte_free(mv_f);
6773         return ret;
6774 }
6775
6776 int
6777 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
6778 {
6779         struct i40e_macvlan_filter *mv_f;
6780         int mac_num;
6781         int ret = I40E_SUCCESS;
6782
6783         /**
6784          * Vlan 0 is the generic filter for untagged packets
6785          * and can't be removed.
6786          */
6787         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
6788                 return I40E_ERR_PARAM;
6789
6790         /* If can't find it, just return */
6791         if (!i40e_find_vlan_filter(vsi, vlan))
6792                 return I40E_ERR_PARAM;
6793
6794         mac_num = vsi->mac_num;
6795
6796         if (mac_num == 0) {
6797                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
6798                 return I40E_ERR_PARAM;
6799         }
6800
6801         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
6802
6803         if (mv_f == NULL) {
6804                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6805                 return I40E_ERR_NO_MEMORY;
6806         }
6807
6808         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
6809
6810         if (ret != I40E_SUCCESS)
6811                 goto DONE;
6812
6813         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
6814
6815         if (ret != I40E_SUCCESS)
6816                 goto DONE;
6817
6818         /* This is last vlan to remove, replace all mac filter with vlan 0 */
6819         if (vsi->vlan_num == 1) {
6820                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
6821                 if (ret != I40E_SUCCESS)
6822                         goto DONE;
6823
6824                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
6825                 if (ret != I40E_SUCCESS)
6826                         goto DONE;
6827         }
6828
6829         i40e_set_vlan_filter(vsi, vlan, 0);
6830
6831         vsi->vlan_num--;
6832         ret = I40E_SUCCESS;
6833 DONE:
6834         rte_free(mv_f);
6835         return ret;
6836 }
6837
6838 int
6839 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
6840 {
6841         struct i40e_mac_filter *f;
6842         struct i40e_macvlan_filter *mv_f;
6843         int i, vlan_num = 0;
6844         int ret = I40E_SUCCESS;
6845
6846         /* If it's add and we've config it, return */
6847         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
6848         if (f != NULL)
6849                 return I40E_SUCCESS;
6850         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
6851                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
6852
6853                 /**
6854                  * If vlan_num is 0, that's the first time to add mac,
6855                  * set mask for vlan_id 0.
6856                  */
6857                 if (vsi->vlan_num == 0) {
6858                         i40e_set_vlan_filter(vsi, 0, 1);
6859                         vsi->vlan_num = 1;
6860                 }
6861                 vlan_num = vsi->vlan_num;
6862         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
6863                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
6864                 vlan_num = 1;
6865
6866         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6867         if (mv_f == NULL) {
6868                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6869                 return I40E_ERR_NO_MEMORY;
6870         }
6871
6872         for (i = 0; i < vlan_num; i++) {
6873                 mv_f[i].filter_type = mac_filter->filter_type;
6874                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
6875                                 ETH_ADDR_LEN);
6876         }
6877
6878         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6879                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
6880                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
6881                                         &mac_filter->mac_addr);
6882                 if (ret != I40E_SUCCESS)
6883                         goto DONE;
6884         }
6885
6886         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
6887         if (ret != I40E_SUCCESS)
6888                 goto DONE;
6889
6890         /* Add the mac addr into mac list */
6891         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
6892         if (f == NULL) {
6893                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6894                 ret = I40E_ERR_NO_MEMORY;
6895                 goto DONE;
6896         }
6897         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
6898                         ETH_ADDR_LEN);
6899         f->mac_info.filter_type = mac_filter->filter_type;
6900         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
6901         vsi->mac_num++;
6902
6903         ret = I40E_SUCCESS;
6904 DONE:
6905         rte_free(mv_f);
6906
6907         return ret;
6908 }
6909
6910 int
6911 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
6912 {
6913         struct i40e_mac_filter *f;
6914         struct i40e_macvlan_filter *mv_f;
6915         int i, vlan_num;
6916         enum rte_mac_filter_type filter_type;
6917         int ret = I40E_SUCCESS;
6918
6919         /* Can't find it, return an error */
6920         f = i40e_find_mac_filter(vsi, addr);
6921         if (f == NULL)
6922                 return I40E_ERR_PARAM;
6923
6924         vlan_num = vsi->vlan_num;
6925         filter_type = f->mac_info.filter_type;
6926         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6927                 filter_type == RTE_MACVLAN_HASH_MATCH) {
6928                 if (vlan_num == 0) {
6929                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
6930                         return I40E_ERR_PARAM;
6931                 }
6932         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
6933                         filter_type == RTE_MAC_HASH_MATCH)
6934                 vlan_num = 1;
6935
6936         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
6937         if (mv_f == NULL) {
6938                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6939                 return I40E_ERR_NO_MEMORY;
6940         }
6941
6942         for (i = 0; i < vlan_num; i++) {
6943                 mv_f[i].filter_type = filter_type;
6944                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
6945                                 ETH_ADDR_LEN);
6946         }
6947         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
6948                         filter_type == RTE_MACVLAN_HASH_MATCH) {
6949                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
6950                 if (ret != I40E_SUCCESS)
6951                         goto DONE;
6952         }
6953
6954         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
6955         if (ret != I40E_SUCCESS)
6956                 goto DONE;
6957
6958         /* Remove the mac addr into mac list */
6959         TAILQ_REMOVE(&vsi->mac_list, f, next);
6960         rte_free(f);
6961         vsi->mac_num--;
6962
6963         ret = I40E_SUCCESS;
6964 DONE:
6965         rte_free(mv_f);
6966         return ret;
6967 }
6968
6969 /* Configure hash enable flags for RSS */
6970 uint64_t
6971 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
6972 {
6973         uint64_t hena = 0;
6974         int i;
6975
6976         if (!flags)
6977                 return hena;
6978
6979         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6980                 if (flags & (1ULL << i))
6981                         hena |= adapter->pctypes_tbl[i];
6982         }
6983
6984         return hena;
6985 }
6986
6987 /* Parse the hash enable flags */
6988 uint64_t
6989 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
6990 {
6991         uint64_t rss_hf = 0;
6992
6993         if (!flags)
6994                 return rss_hf;
6995         int i;
6996
6997         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
6998                 if (flags & adapter->pctypes_tbl[i])
6999                         rss_hf |= (1ULL << i);
7000         }
7001         return rss_hf;
7002 }
7003
7004 /* Disable RSS */
7005 static void
7006 i40e_pf_disable_rss(struct i40e_pf *pf)
7007 {
7008         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7009
7010         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7011         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7012         I40E_WRITE_FLUSH(hw);
7013 }
7014
7015 int
7016 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7017 {
7018         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7019         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7020         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7021                            I40E_VFQF_HKEY_MAX_INDEX :
7022                            I40E_PFQF_HKEY_MAX_INDEX;
7023         int ret = 0;
7024
7025         if (!key || key_len == 0) {
7026                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7027                 return 0;
7028         } else if (key_len != (key_idx + 1) *
7029                 sizeof(uint32_t)) {
7030                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7031                 return -EINVAL;
7032         }
7033
7034         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7035                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7036                         (struct i40e_aqc_get_set_rss_key_data *)key;
7037
7038                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7039                 if (ret)
7040                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7041         } else {
7042                 uint32_t *hash_key = (uint32_t *)key;
7043                 uint16_t i;
7044
7045                 if (vsi->type == I40E_VSI_SRIOV) {
7046                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7047                                 I40E_WRITE_REG(
7048                                         hw,
7049                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7050                                         hash_key[i]);
7051
7052                 } else {
7053                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7054                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7055                                                hash_key[i]);
7056                 }
7057                 I40E_WRITE_FLUSH(hw);
7058         }
7059
7060         return ret;
7061 }
7062
7063 static int
7064 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7065 {
7066         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7067         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7068         uint32_t reg;
7069         int ret;
7070
7071         if (!key || !key_len)
7072                 return -EINVAL;
7073
7074         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7075                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7076                         (struct i40e_aqc_get_set_rss_key_data *)key);
7077                 if (ret) {
7078                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7079                         return ret;
7080                 }
7081         } else {
7082                 uint32_t *key_dw = (uint32_t *)key;
7083                 uint16_t i;
7084
7085                 if (vsi->type == I40E_VSI_SRIOV) {
7086                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7087                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7088                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7089                         }
7090                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7091                                    sizeof(uint32_t);
7092                 } else {
7093                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7094                                 reg = I40E_PFQF_HKEY(i);
7095                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7096                         }
7097                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7098                                    sizeof(uint32_t);
7099                 }
7100         }
7101         return 0;
7102 }
7103
7104 static int
7105 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7106 {
7107         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7108         uint64_t hena;
7109         int ret;
7110
7111         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7112                                rss_conf->rss_key_len);
7113         if (ret)
7114                 return ret;
7115
7116         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7117         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7118         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7119         I40E_WRITE_FLUSH(hw);
7120
7121         return 0;
7122 }
7123
7124 static int
7125 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7126                          struct rte_eth_rss_conf *rss_conf)
7127 {
7128         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7129         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7130         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7131         uint64_t hena;
7132
7133         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7134         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7135
7136         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7137                 if (rss_hf != 0) /* Enable RSS */
7138                         return -EINVAL;
7139                 return 0; /* Nothing to do */
7140         }
7141         /* RSS enabled */
7142         if (rss_hf == 0) /* Disable RSS */
7143                 return -EINVAL;
7144
7145         return i40e_hw_rss_hash_set(pf, rss_conf);
7146 }
7147
7148 static int
7149 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7150                            struct rte_eth_rss_conf *rss_conf)
7151 {
7152         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7153         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7154         uint64_t hena;
7155
7156         i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7157                          &rss_conf->rss_key_len);
7158
7159         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7160         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7161         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7162
7163         return 0;
7164 }
7165
7166 static int
7167 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7168 {
7169         switch (filter_type) {
7170         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7171                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7172                 break;
7173         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7174                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7175                 break;
7176         case RTE_TUNNEL_FILTER_IMAC_TENID:
7177                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7178                 break;
7179         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7180                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7181                 break;
7182         case ETH_TUNNEL_FILTER_IMAC:
7183                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7184                 break;
7185         case ETH_TUNNEL_FILTER_OIP:
7186                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7187                 break;
7188         case ETH_TUNNEL_FILTER_IIP:
7189                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7190                 break;
7191         default:
7192                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7193                 return -EINVAL;
7194         }
7195
7196         return 0;
7197 }
7198
7199 /* Convert tunnel filter structure */
7200 static int
7201 i40e_tunnel_filter_convert(
7202         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter,
7203         struct i40e_tunnel_filter *tunnel_filter)
7204 {
7205         ether_addr_copy((struct ether_addr *)&cld_filter->element.outer_mac,
7206                         (struct ether_addr *)&tunnel_filter->input.outer_mac);
7207         ether_addr_copy((struct ether_addr *)&cld_filter->element.inner_mac,
7208                         (struct ether_addr *)&tunnel_filter->input.inner_mac);
7209         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7210         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7211              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7212             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7213                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7214         else
7215                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7216         tunnel_filter->input.flags = cld_filter->element.flags;
7217         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7218         tunnel_filter->queue = cld_filter->element.queue_number;
7219         rte_memcpy(tunnel_filter->input.general_fields,
7220                    cld_filter->general_fields,
7221                    sizeof(cld_filter->general_fields));
7222
7223         return 0;
7224 }
7225
7226 /* Check if there exists the tunnel filter */
7227 struct i40e_tunnel_filter *
7228 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7229                              const struct i40e_tunnel_filter_input *input)
7230 {
7231         int ret;
7232
7233         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7234         if (ret < 0)
7235                 return NULL;
7236
7237         return tunnel_rule->hash_map[ret];
7238 }
7239
7240 /* Add a tunnel filter into the SW list */
7241 static int
7242 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7243                              struct i40e_tunnel_filter *tunnel_filter)
7244 {
7245         struct i40e_tunnel_rule *rule = &pf->tunnel;
7246         int ret;
7247
7248         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7249         if (ret < 0) {
7250                 PMD_DRV_LOG(ERR,
7251                             "Failed to insert tunnel filter to hash table %d!",
7252                             ret);
7253                 return ret;
7254         }
7255         rule->hash_map[ret] = tunnel_filter;
7256
7257         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7258
7259         return 0;
7260 }
7261
7262 /* Delete a tunnel filter from the SW list */
7263 int
7264 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7265                           struct i40e_tunnel_filter_input *input)
7266 {
7267         struct i40e_tunnel_rule *rule = &pf->tunnel;
7268         struct i40e_tunnel_filter *tunnel_filter;
7269         int ret;
7270
7271         ret = rte_hash_del_key(rule->hash_table, input);
7272         if (ret < 0) {
7273                 PMD_DRV_LOG(ERR,
7274                             "Failed to delete tunnel filter to hash table %d!",
7275                             ret);
7276                 return ret;
7277         }
7278         tunnel_filter = rule->hash_map[ret];
7279         rule->hash_map[ret] = NULL;
7280
7281         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7282         rte_free(tunnel_filter);
7283
7284         return 0;
7285 }
7286
7287 int
7288 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7289                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7290                         uint8_t add)
7291 {
7292         uint16_t ip_type;
7293         uint32_t ipv4_addr, ipv4_addr_le;
7294         uint8_t i, tun_type = 0;
7295         /* internal varialbe to convert ipv6 byte order */
7296         uint32_t convert_ipv6[4];
7297         int val, ret = 0;
7298         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7299         struct i40e_vsi *vsi = pf->main_vsi;
7300         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7301         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7302         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7303         struct i40e_tunnel_filter *tunnel, *node;
7304         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7305
7306         cld_filter = rte_zmalloc("tunnel_filter",
7307                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7308         0);
7309
7310         if (NULL == cld_filter) {
7311                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7312                 return -ENOMEM;
7313         }
7314         pfilter = cld_filter;
7315
7316         ether_addr_copy(&tunnel_filter->outer_mac,
7317                         (struct ether_addr *)&pfilter->element.outer_mac);
7318         ether_addr_copy(&tunnel_filter->inner_mac,
7319                         (struct ether_addr *)&pfilter->element.inner_mac);
7320
7321         pfilter->element.inner_vlan =
7322                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7323         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7324                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7325                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7326                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7327                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7328                                 &ipv4_addr_le,
7329                                 sizeof(pfilter->element.ipaddr.v4.data));
7330         } else {
7331                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7332                 for (i = 0; i < 4; i++) {
7333                         convert_ipv6[i] =
7334                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7335                 }
7336                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7337                            &convert_ipv6,
7338                            sizeof(pfilter->element.ipaddr.v6.data));
7339         }
7340
7341         /* check tunneled type */
7342         switch (tunnel_filter->tunnel_type) {
7343         case RTE_TUNNEL_TYPE_VXLAN:
7344                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7345                 break;
7346         case RTE_TUNNEL_TYPE_NVGRE:
7347                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7348                 break;
7349         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7350                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7351                 break;
7352         default:
7353                 /* Other tunnel types is not supported. */
7354                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7355                 rte_free(cld_filter);
7356                 return -EINVAL;
7357         }
7358
7359         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7360                                        &pfilter->element.flags);
7361         if (val < 0) {
7362                 rte_free(cld_filter);
7363                 return -EINVAL;
7364         }
7365
7366         pfilter->element.flags |= rte_cpu_to_le_16(
7367                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7368                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7369         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7370         pfilter->element.queue_number =
7371                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7372
7373         /* Check if there is the filter in SW list */
7374         memset(&check_filter, 0, sizeof(check_filter));
7375         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7376         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7377         if (add && node) {
7378                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7379                 rte_free(cld_filter);
7380                 return -EINVAL;
7381         }
7382
7383         if (!add && !node) {
7384                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7385                 rte_free(cld_filter);
7386                 return -EINVAL;
7387         }
7388
7389         if (add) {
7390                 ret = i40e_aq_add_cloud_filters(hw,
7391                                         vsi->seid, &cld_filter->element, 1);
7392                 if (ret < 0) {
7393                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7394                         rte_free(cld_filter);
7395                         return -ENOTSUP;
7396                 }
7397                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7398                 if (tunnel == NULL) {
7399                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7400                         rte_free(cld_filter);
7401                         return -ENOMEM;
7402                 }
7403
7404                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7405                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7406                 if (ret < 0)
7407                         rte_free(tunnel);
7408         } else {
7409                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7410                                                    &cld_filter->element, 1);
7411                 if (ret < 0) {
7412                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7413                         rte_free(cld_filter);
7414                         return -ENOTSUP;
7415                 }
7416                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7417         }
7418
7419         rte_free(cld_filter);
7420         return ret;
7421 }
7422
7423 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7424 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7425 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7426 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7427 #define I40E_TR_GRE_KEY_MASK                    0x400
7428 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7429 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7430
7431 static enum
7432 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7433 {
7434         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7435         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7436         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7437         enum i40e_status_code status = I40E_SUCCESS;
7438
7439         if (pf->support_multi_driver) {
7440                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7441                 return I40E_NOT_SUPPORTED;
7442         }
7443
7444         memset(&filter_replace, 0,
7445                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7446         memset(&filter_replace_buf, 0,
7447                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7448
7449         /* create L1 filter */
7450         filter_replace.old_filter_type =
7451                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7452         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7453         filter_replace.tr_bit = 0;
7454
7455         /* Prepare the buffer, 3 entries */
7456         filter_replace_buf.data[0] =
7457                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7458         filter_replace_buf.data[0] |=
7459                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7460         filter_replace_buf.data[2] = 0xFF;
7461         filter_replace_buf.data[3] = 0xFF;
7462         filter_replace_buf.data[4] =
7463                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7464         filter_replace_buf.data[4] |=
7465                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7466         filter_replace_buf.data[7] = 0xF0;
7467         filter_replace_buf.data[8]
7468                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7469         filter_replace_buf.data[8] |=
7470                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7471         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7472                 I40E_TR_GENEVE_KEY_MASK |
7473                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7474         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7475                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7476                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7477
7478         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7479                                                &filter_replace_buf);
7480         if (!status) {
7481                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7482                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7483                             "cloud l1 type is changed from 0x%x to 0x%x",
7484                             filter_replace.old_filter_type,
7485                             filter_replace.new_filter_type);
7486         }
7487         return status;
7488 }
7489
7490 static enum
7491 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7492 {
7493         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7494         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7495         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7496         enum i40e_status_code status = I40E_SUCCESS;
7497
7498         if (pf->support_multi_driver) {
7499                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7500                 return I40E_NOT_SUPPORTED;
7501         }
7502
7503         /* For MPLSoUDP */
7504         memset(&filter_replace, 0,
7505                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7506         memset(&filter_replace_buf, 0,
7507                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7508         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7509                 I40E_AQC_MIRROR_CLOUD_FILTER;
7510         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7511         filter_replace.new_filter_type =
7512                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7513         /* Prepare the buffer, 2 entries */
7514         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7515         filter_replace_buf.data[0] |=
7516                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7517         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7518         filter_replace_buf.data[4] |=
7519                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7520         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7521                                                &filter_replace_buf);
7522         if (status < 0)
7523                 return status;
7524         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7525                     "cloud filter type is changed from 0x%x to 0x%x",
7526                     filter_replace.old_filter_type,
7527                     filter_replace.new_filter_type);
7528
7529         /* For MPLSoGRE */
7530         memset(&filter_replace, 0,
7531                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7532         memset(&filter_replace_buf, 0,
7533                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7534
7535         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7536                 I40E_AQC_MIRROR_CLOUD_FILTER;
7537         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7538         filter_replace.new_filter_type =
7539                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7540         /* Prepare the buffer, 2 entries */
7541         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7542         filter_replace_buf.data[0] |=
7543                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7544         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7545         filter_replace_buf.data[4] |=
7546                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7547
7548         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7549                                                &filter_replace_buf);
7550         if (!status) {
7551                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7552                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7553                             "cloud filter type is changed from 0x%x to 0x%x",
7554                             filter_replace.old_filter_type,
7555                             filter_replace.new_filter_type);
7556         }
7557         return status;
7558 }
7559
7560 static enum i40e_status_code
7561 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7562 {
7563         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7564         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7565         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7566         enum i40e_status_code status = I40E_SUCCESS;
7567
7568         if (pf->support_multi_driver) {
7569                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7570                 return I40E_NOT_SUPPORTED;
7571         }
7572
7573         /* For GTP-C */
7574         memset(&filter_replace, 0,
7575                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7576         memset(&filter_replace_buf, 0,
7577                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7578         /* create L1 filter */
7579         filter_replace.old_filter_type =
7580                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7581         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7582         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7583                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7584         /* Prepare the buffer, 2 entries */
7585         filter_replace_buf.data[0] =
7586                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7587         filter_replace_buf.data[0] |=
7588                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7589         filter_replace_buf.data[2] = 0xFF;
7590         filter_replace_buf.data[3] = 0xFF;
7591         filter_replace_buf.data[4] =
7592                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7593         filter_replace_buf.data[4] |=
7594                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7595         filter_replace_buf.data[6] = 0xFF;
7596         filter_replace_buf.data[7] = 0xFF;
7597         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7598                                                &filter_replace_buf);
7599         if (status < 0)
7600                 return status;
7601         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7602                     "cloud l1 type is changed from 0x%x to 0x%x",
7603                     filter_replace.old_filter_type,
7604                     filter_replace.new_filter_type);
7605
7606         /* for GTP-U */
7607         memset(&filter_replace, 0,
7608                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7609         memset(&filter_replace_buf, 0,
7610                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7611         /* create L1 filter */
7612         filter_replace.old_filter_type =
7613                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
7614         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
7615         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
7616                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7617         /* Prepare the buffer, 2 entries */
7618         filter_replace_buf.data[0] =
7619                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7620         filter_replace_buf.data[0] |=
7621                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7622         filter_replace_buf.data[2] = 0xFF;
7623         filter_replace_buf.data[3] = 0xFF;
7624         filter_replace_buf.data[4] =
7625                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7626         filter_replace_buf.data[4] |=
7627                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7628         filter_replace_buf.data[6] = 0xFF;
7629         filter_replace_buf.data[7] = 0xFF;
7630
7631         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7632                                                &filter_replace_buf);
7633         if (!status) {
7634                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7635                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7636                             "cloud l1 type is changed from 0x%x to 0x%x",
7637                             filter_replace.old_filter_type,
7638                             filter_replace.new_filter_type);
7639         }
7640         return status;
7641 }
7642
7643 static enum
7644 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
7645 {
7646         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7647         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7648         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7649         enum i40e_status_code status = I40E_SUCCESS;
7650
7651         if (pf->support_multi_driver) {
7652                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7653                 return I40E_NOT_SUPPORTED;
7654         }
7655
7656         /* for GTP-C */
7657         memset(&filter_replace, 0,
7658                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7659         memset(&filter_replace_buf, 0,
7660                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7661         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7662         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7663         filter_replace.new_filter_type =
7664                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7665         /* Prepare the buffer, 2 entries */
7666         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
7667         filter_replace_buf.data[0] |=
7668                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7669         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7670         filter_replace_buf.data[4] |=
7671                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7672         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7673                                                &filter_replace_buf);
7674         if (status < 0)
7675                 return status;
7676         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7677                     "cloud filter type is changed from 0x%x to 0x%x",
7678                     filter_replace.old_filter_type,
7679                     filter_replace.new_filter_type);
7680
7681         /* for GTP-U */
7682         memset(&filter_replace, 0,
7683                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7684         memset(&filter_replace_buf, 0,
7685                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7686         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
7687         filter_replace.old_filter_type =
7688                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7689         filter_replace.new_filter_type =
7690                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7691         /* Prepare the buffer, 2 entries */
7692         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
7693         filter_replace_buf.data[0] |=
7694                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7695         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7696         filter_replace_buf.data[4] |=
7697                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7698
7699         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7700                                                &filter_replace_buf);
7701         if (!status) {
7702                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
7703                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
7704                             "cloud filter type is changed from 0x%x to 0x%x",
7705                             filter_replace.old_filter_type,
7706                             filter_replace.new_filter_type);
7707         }
7708         return status;
7709 }
7710
7711 int
7712 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
7713                       struct i40e_tunnel_filter_conf *tunnel_filter,
7714                       uint8_t add)
7715 {
7716         uint16_t ip_type;
7717         uint32_t ipv4_addr, ipv4_addr_le;
7718         uint8_t i, tun_type = 0;
7719         /* internal variable to convert ipv6 byte order */
7720         uint32_t convert_ipv6[4];
7721         int val, ret = 0;
7722         struct i40e_pf_vf *vf = NULL;
7723         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7724         struct i40e_vsi *vsi;
7725         struct i40e_aqc_add_rm_cloud_filt_elem_ext *cld_filter;
7726         struct i40e_aqc_add_rm_cloud_filt_elem_ext *pfilter;
7727         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7728         struct i40e_tunnel_filter *tunnel, *node;
7729         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7730         uint32_t teid_le;
7731         bool big_buffer = 0;
7732
7733         cld_filter = rte_zmalloc("tunnel_filter",
7734                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7735                          0);
7736
7737         if (cld_filter == NULL) {
7738                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7739                 return -ENOMEM;
7740         }
7741         pfilter = cld_filter;
7742
7743         ether_addr_copy(&tunnel_filter->outer_mac,
7744                         (struct ether_addr *)&pfilter->element.outer_mac);
7745         ether_addr_copy(&tunnel_filter->inner_mac,
7746                         (struct ether_addr *)&pfilter->element.inner_mac);
7747
7748         pfilter->element.inner_vlan =
7749                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7750         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
7751                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7752                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7753                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7754                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7755                                 &ipv4_addr_le,
7756                                 sizeof(pfilter->element.ipaddr.v4.data));
7757         } else {
7758                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7759                 for (i = 0; i < 4; i++) {
7760                         convert_ipv6[i] =
7761                         rte_cpu_to_le_32(rte_be_to_cpu_32(
7762                                          tunnel_filter->ip_addr.ipv6_addr[i]));
7763                 }
7764                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7765                            &convert_ipv6,
7766                            sizeof(pfilter->element.ipaddr.v6.data));
7767         }
7768
7769         /* check tunneled type */
7770         switch (tunnel_filter->tunnel_type) {
7771         case I40E_TUNNEL_TYPE_VXLAN:
7772                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7773                 break;
7774         case I40E_TUNNEL_TYPE_NVGRE:
7775                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7776                 break;
7777         case I40E_TUNNEL_TYPE_IP_IN_GRE:
7778                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7779                 break;
7780         case I40E_TUNNEL_TYPE_MPLSoUDP:
7781                 if (!pf->mpls_replace_flag) {
7782                         i40e_replace_mpls_l1_filter(pf);
7783                         i40e_replace_mpls_cloud_filter(pf);
7784                         pf->mpls_replace_flag = 1;
7785                 }
7786                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7787                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7788                         teid_le >> 4;
7789                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7790                         (teid_le & 0xF) << 12;
7791                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7792                         0x40;
7793                 big_buffer = 1;
7794                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
7795                 break;
7796         case I40E_TUNNEL_TYPE_MPLSoGRE:
7797                 if (!pf->mpls_replace_flag) {
7798                         i40e_replace_mpls_l1_filter(pf);
7799                         i40e_replace_mpls_cloud_filter(pf);
7800                         pf->mpls_replace_flag = 1;
7801                 }
7802                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7803                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
7804                         teid_le >> 4;
7805                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
7806                         (teid_le & 0xF) << 12;
7807                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
7808                         0x0;
7809                 big_buffer = 1;
7810                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
7811                 break;
7812         case I40E_TUNNEL_TYPE_GTPC:
7813                 if (!pf->gtp_replace_flag) {
7814                         i40e_replace_gtp_l1_filter(pf);
7815                         i40e_replace_gtp_cloud_filter(pf);
7816                         pf->gtp_replace_flag = 1;
7817                 }
7818                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7819                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
7820                         (teid_le >> 16) & 0xFFFF;
7821                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
7822                         teid_le & 0xFFFF;
7823                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
7824                         0x0;
7825                 big_buffer = 1;
7826                 break;
7827         case I40E_TUNNEL_TYPE_GTPU:
7828                 if (!pf->gtp_replace_flag) {
7829                         i40e_replace_gtp_l1_filter(pf);
7830                         i40e_replace_gtp_cloud_filter(pf);
7831                         pf->gtp_replace_flag = 1;
7832                 }
7833                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7834                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
7835                         (teid_le >> 16) & 0xFFFF;
7836                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
7837                         teid_le & 0xFFFF;
7838                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
7839                         0x0;
7840                 big_buffer = 1;
7841                 break;
7842         case I40E_TUNNEL_TYPE_QINQ:
7843                 if (!pf->qinq_replace_flag) {
7844                         ret = i40e_cloud_filter_qinq_create(pf);
7845                         if (ret < 0)
7846                                 PMD_DRV_LOG(DEBUG,
7847                                             "QinQ tunnel filter already created.");
7848                         pf->qinq_replace_flag = 1;
7849                 }
7850                 /*      Add in the General fields the values of
7851                  *      the Outer and Inner VLAN
7852                  *      Big Buffer should be set, see changes in
7853                  *      i40e_aq_add_cloud_filters
7854                  */
7855                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
7856                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
7857                 big_buffer = 1;
7858                 break;
7859         default:
7860                 /* Other tunnel types is not supported. */
7861                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7862                 rte_free(cld_filter);
7863                 return -EINVAL;
7864         }
7865
7866         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
7867                 pfilter->element.flags =
7868                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7869         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
7870                 pfilter->element.flags =
7871                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7872         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
7873                 pfilter->element.flags =
7874                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
7875         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
7876                 pfilter->element.flags =
7877                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
7878         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
7879                 pfilter->element.flags |=
7880                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
7881         else {
7882                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7883                                                 &pfilter->element.flags);
7884                 if (val < 0) {
7885                         rte_free(cld_filter);
7886                         return -EINVAL;
7887                 }
7888         }
7889
7890         pfilter->element.flags |= rte_cpu_to_le_16(
7891                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7892                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7893         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7894         pfilter->element.queue_number =
7895                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7896
7897         if (!tunnel_filter->is_to_vf)
7898                 vsi = pf->main_vsi;
7899         else {
7900                 if (tunnel_filter->vf_id >= pf->vf_num) {
7901                         PMD_DRV_LOG(ERR, "Invalid argument.");
7902                         rte_free(cld_filter);
7903                         return -EINVAL;
7904                 }
7905                 vf = &pf->vfs[tunnel_filter->vf_id];
7906                 vsi = vf->vsi;
7907         }
7908
7909         /* Check if there is the filter in SW list */
7910         memset(&check_filter, 0, sizeof(check_filter));
7911         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7912         check_filter.is_to_vf = tunnel_filter->is_to_vf;
7913         check_filter.vf_id = tunnel_filter->vf_id;
7914         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7915         if (add && node) {
7916                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7917                 rte_free(cld_filter);
7918                 return -EINVAL;
7919         }
7920
7921         if (!add && !node) {
7922                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7923                 rte_free(cld_filter);
7924                 return -EINVAL;
7925         }
7926
7927         if (add) {
7928                 if (big_buffer)
7929                         ret = i40e_aq_add_cloud_filters_big_buffer(hw,
7930                                                    vsi->seid, cld_filter, 1);
7931                 else
7932                         ret = i40e_aq_add_cloud_filters(hw,
7933                                         vsi->seid, &cld_filter->element, 1);
7934                 if (ret < 0) {
7935                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7936                         rte_free(cld_filter);
7937                         return -ENOTSUP;
7938                 }
7939                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7940                 if (tunnel == NULL) {
7941                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7942                         rte_free(cld_filter);
7943                         return -ENOMEM;
7944                 }
7945
7946                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7947                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7948                 if (ret < 0)
7949                         rte_free(tunnel);
7950         } else {
7951                 if (big_buffer)
7952                         ret = i40e_aq_remove_cloud_filters_big_buffer(
7953                                 hw, vsi->seid, cld_filter, 1);
7954                 else
7955                         ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
7956                                                    &cld_filter->element, 1);
7957                 if (ret < 0) {
7958                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7959                         rte_free(cld_filter);
7960                         return -ENOTSUP;
7961                 }
7962                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7963         }
7964
7965         rte_free(cld_filter);
7966         return ret;
7967 }
7968
7969 static int
7970 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
7971 {
7972         uint8_t i;
7973
7974         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
7975                 if (pf->vxlan_ports[i] == port)
7976                         return i;
7977         }
7978
7979         return -1;
7980 }
7981
7982 static int
7983 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
7984 {
7985         int  idx, ret;
7986         uint8_t filter_idx;
7987         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7988
7989         idx = i40e_get_vxlan_port_idx(pf, port);
7990
7991         /* Check if port already exists */
7992         if (idx >= 0) {
7993                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
7994                 return -EINVAL;
7995         }
7996
7997         /* Now check if there is space to add the new port */
7998         idx = i40e_get_vxlan_port_idx(pf, 0);
7999         if (idx < 0) {
8000                 PMD_DRV_LOG(ERR,
8001                         "Maximum number of UDP ports reached, not adding port %d",
8002                         port);
8003                 return -ENOSPC;
8004         }
8005
8006         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
8007                                         &filter_idx, NULL);
8008         if (ret < 0) {
8009                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8010                 return -1;
8011         }
8012
8013         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8014                          port,  filter_idx);
8015
8016         /* New port: add it and mark its index in the bitmap */
8017         pf->vxlan_ports[idx] = port;
8018         pf->vxlan_bitmap |= (1 << idx);
8019
8020         if (!(pf->flags & I40E_FLAG_VXLAN))
8021                 pf->flags |= I40E_FLAG_VXLAN;
8022
8023         return 0;
8024 }
8025
8026 static int
8027 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8028 {
8029         int idx;
8030         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8031
8032         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8033                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8034                 return -EINVAL;
8035         }
8036
8037         idx = i40e_get_vxlan_port_idx(pf, port);
8038
8039         if (idx < 0) {
8040                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8041                 return -EINVAL;
8042         }
8043
8044         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8045                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8046                 return -1;
8047         }
8048
8049         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8050                         port, idx);
8051
8052         pf->vxlan_ports[idx] = 0;
8053         pf->vxlan_bitmap &= ~(1 << idx);
8054
8055         if (!pf->vxlan_bitmap)
8056                 pf->flags &= ~I40E_FLAG_VXLAN;
8057
8058         return 0;
8059 }
8060
8061 /* Add UDP tunneling port */
8062 static int
8063 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8064                              struct rte_eth_udp_tunnel *udp_tunnel)
8065 {
8066         int ret = 0;
8067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8068
8069         if (udp_tunnel == NULL)
8070                 return -EINVAL;
8071
8072         switch (udp_tunnel->prot_type) {
8073         case RTE_TUNNEL_TYPE_VXLAN:
8074                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
8075                 break;
8076
8077         case RTE_TUNNEL_TYPE_GENEVE:
8078         case RTE_TUNNEL_TYPE_TEREDO:
8079                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8080                 ret = -1;
8081                 break;
8082
8083         default:
8084                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8085                 ret = -1;
8086                 break;
8087         }
8088
8089         return ret;
8090 }
8091
8092 /* Remove UDP tunneling port */
8093 static int
8094 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8095                              struct rte_eth_udp_tunnel *udp_tunnel)
8096 {
8097         int ret = 0;
8098         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8099
8100         if (udp_tunnel == NULL)
8101                 return -EINVAL;
8102
8103         switch (udp_tunnel->prot_type) {
8104         case RTE_TUNNEL_TYPE_VXLAN:
8105                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8106                 break;
8107         case RTE_TUNNEL_TYPE_GENEVE:
8108         case RTE_TUNNEL_TYPE_TEREDO:
8109                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8110                 ret = -1;
8111                 break;
8112         default:
8113                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8114                 ret = -1;
8115                 break;
8116         }
8117
8118         return ret;
8119 }
8120
8121 /* Calculate the maximum number of contiguous PF queues that are configured */
8122 static int
8123 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8124 {
8125         struct rte_eth_dev_data *data = pf->dev_data;
8126         int i, num;
8127         struct i40e_rx_queue *rxq;
8128
8129         num = 0;
8130         for (i = 0; i < pf->lan_nb_qps; i++) {
8131                 rxq = data->rx_queues[i];
8132                 if (rxq && rxq->q_set)
8133                         num++;
8134                 else
8135                         break;
8136         }
8137
8138         return num;
8139 }
8140
8141 /* Configure RSS */
8142 static int
8143 i40e_pf_config_rss(struct i40e_pf *pf)
8144 {
8145         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8146         struct rte_eth_rss_conf rss_conf;
8147         uint32_t i, lut = 0;
8148         uint16_t j, num;
8149
8150         /*
8151          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8152          * It's necessary to calculate the actual PF queues that are configured.
8153          */
8154         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8155                 num = i40e_pf_calc_configured_queues_num(pf);
8156         else
8157                 num = pf->dev_data->nb_rx_queues;
8158
8159         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8160         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8161                         num);
8162
8163         if (num == 0) {
8164                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8165                 return -ENOTSUP;
8166         }
8167
8168         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8169                 if (j == num)
8170                         j = 0;
8171                 lut = (lut << 8) | (j & ((0x1 <<
8172                         hw->func_caps.rss_table_entry_width) - 1));
8173                 if ((i & 3) == 3)
8174                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
8175         }
8176
8177         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8178         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8179                 i40e_pf_disable_rss(pf);
8180                 return 0;
8181         }
8182         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8183                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8184                 /* Random default keys */
8185                 static uint32_t rss_key_default[] = {0x6b793944,
8186                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8187                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8188                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8189
8190                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8191                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8192                                                         sizeof(uint32_t);
8193         }
8194
8195         return i40e_hw_rss_hash_set(pf, &rss_conf);
8196 }
8197
8198 static int
8199 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8200                                struct rte_eth_tunnel_filter_conf *filter)
8201 {
8202         if (pf == NULL || filter == NULL) {
8203                 PMD_DRV_LOG(ERR, "Invalid parameter");
8204                 return -EINVAL;
8205         }
8206
8207         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8208                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8209                 return -EINVAL;
8210         }
8211
8212         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
8213                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8214                 return -EINVAL;
8215         }
8216
8217         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8218                 (is_zero_ether_addr(&filter->outer_mac))) {
8219                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8220                 return -EINVAL;
8221         }
8222
8223         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8224                 (is_zero_ether_addr(&filter->inner_mac))) {
8225                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8226                 return -EINVAL;
8227         }
8228
8229         return 0;
8230 }
8231
8232 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8233 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8234 static int
8235 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8236 {
8237         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8238         uint32_t val, reg;
8239         int ret = -EINVAL;
8240
8241         if (pf->support_multi_driver) {
8242                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8243                 return -ENOTSUP;
8244         }
8245
8246         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8247         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8248
8249         if (len == 3) {
8250                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8251         } else if (len == 4) {
8252                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8253         } else {
8254                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8255                 return ret;
8256         }
8257
8258         if (reg != val) {
8259                 ret = i40e_aq_debug_write_register(hw, I40E_GL_PRS_FVBM(2),
8260                                                    reg, NULL);
8261                 if (ret != 0)
8262                         return ret;
8263                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8264                             "with value 0x%08x",
8265                             I40E_GL_PRS_FVBM(2), reg);
8266                 i40e_global_cfg_warning(I40E_WARNING_GRE_KEY_LEN);
8267         } else {
8268                 ret = 0;
8269         }
8270         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8271                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8272
8273         return ret;
8274 }
8275
8276 static int
8277 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8278 {
8279         int ret = -EINVAL;
8280
8281         if (!hw || !cfg)
8282                 return -EINVAL;
8283
8284         switch (cfg->cfg_type) {
8285         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8286                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8287                 break;
8288         default:
8289                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8290                 break;
8291         }
8292
8293         return ret;
8294 }
8295
8296 static int
8297 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8298                                enum rte_filter_op filter_op,
8299                                void *arg)
8300 {
8301         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8302         int ret = I40E_ERR_PARAM;
8303
8304         switch (filter_op) {
8305         case RTE_ETH_FILTER_SET:
8306                 ret = i40e_dev_global_config_set(hw,
8307                         (struct rte_eth_global_cfg *)arg);
8308                 break;
8309         default:
8310                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8311                 break;
8312         }
8313
8314         return ret;
8315 }
8316
8317 static int
8318 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8319                           enum rte_filter_op filter_op,
8320                           void *arg)
8321 {
8322         struct rte_eth_tunnel_filter_conf *filter;
8323         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8324         int ret = I40E_SUCCESS;
8325
8326         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8327
8328         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8329                 return I40E_ERR_PARAM;
8330
8331         switch (filter_op) {
8332         case RTE_ETH_FILTER_NOP:
8333                 if (!(pf->flags & I40E_FLAG_VXLAN))
8334                         ret = I40E_NOT_SUPPORTED;
8335                 break;
8336         case RTE_ETH_FILTER_ADD:
8337                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8338                 break;
8339         case RTE_ETH_FILTER_DELETE:
8340                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8341                 break;
8342         default:
8343                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8344                 ret = I40E_ERR_PARAM;
8345                 break;
8346         }
8347
8348         return ret;
8349 }
8350
8351 static int
8352 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8353 {
8354         int ret = 0;
8355         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8356
8357         /* RSS setup */
8358         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8359                 ret = i40e_pf_config_rss(pf);
8360         else
8361                 i40e_pf_disable_rss(pf);
8362
8363         return ret;
8364 }
8365
8366 /* Get the symmetric hash enable configurations per port */
8367 static void
8368 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8369 {
8370         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8371
8372         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8373 }
8374
8375 /* Set the symmetric hash enable configurations per port */
8376 static void
8377 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8378 {
8379         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8380
8381         if (enable > 0) {
8382                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8383                         PMD_DRV_LOG(INFO,
8384                                 "Symmetric hash has already been enabled");
8385                         return;
8386                 }
8387                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8388         } else {
8389                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8390                         PMD_DRV_LOG(INFO,
8391                                 "Symmetric hash has already been disabled");
8392                         return;
8393                 }
8394                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8395         }
8396         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8397         I40E_WRITE_FLUSH(hw);
8398 }
8399
8400 /*
8401  * Get global configurations of hash function type and symmetric hash enable
8402  * per flow type (pctype). Note that global configuration means it affects all
8403  * the ports on the same NIC.
8404  */
8405 static int
8406 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8407                                    struct rte_eth_hash_global_conf *g_cfg)
8408 {
8409         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8410         uint32_t reg;
8411         uint16_t i, j;
8412
8413         memset(g_cfg, 0, sizeof(*g_cfg));
8414         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8415         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8416                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8417         else
8418                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8419         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8420                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8421
8422         /*
8423          * As i40e supports less than 64 flow types, only first 64 bits need to
8424          * be checked.
8425          */
8426         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8427                 g_cfg->valid_bit_mask[i] = 0ULL;
8428                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8429         }
8430
8431         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8432
8433         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8434                 if (!adapter->pctypes_tbl[i])
8435                         continue;
8436                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8437                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8438                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8439                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8440                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8441                                         g_cfg->sym_hash_enable_mask[0] |=
8442                                                                 (1ULL << i);
8443                                 }
8444                         }
8445                 }
8446         }
8447
8448         return 0;
8449 }
8450
8451 static int
8452 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8453                               const struct rte_eth_hash_global_conf *g_cfg)
8454 {
8455         uint32_t i;
8456         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8457
8458         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8459                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8460                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8461                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8462                                                 g_cfg->hash_func);
8463                 return -EINVAL;
8464         }
8465
8466         /*
8467          * As i40e supports less than 64 flow types, only first 64 bits need to
8468          * be checked.
8469          */
8470         mask0 = g_cfg->valid_bit_mask[0];
8471         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8472                 if (i == 0) {
8473                         /* Check if any unsupported flow type configured */
8474                         if ((mask0 | i40e_mask) ^ i40e_mask)
8475                                 goto mask_err;
8476                 } else {
8477                         if (g_cfg->valid_bit_mask[i])
8478                                 goto mask_err;
8479                 }
8480         }
8481
8482         return 0;
8483
8484 mask_err:
8485         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8486
8487         return -EINVAL;
8488 }
8489
8490 /*
8491  * Set global configurations of hash function type and symmetric hash enable
8492  * per flow type (pctype). Note any modifying global configuration will affect
8493  * all the ports on the same NIC.
8494  */
8495 static int
8496 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8497                                    struct rte_eth_hash_global_conf *g_cfg)
8498 {
8499         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8500         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8501         int ret;
8502         uint16_t i, j;
8503         uint32_t reg;
8504         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8505
8506         if (pf->support_multi_driver) {
8507                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8508                 return -ENOTSUP;
8509         }
8510
8511         /* Check the input parameters */
8512         ret = i40e_hash_global_config_check(adapter, g_cfg);
8513         if (ret < 0)
8514                 return ret;
8515
8516         /*
8517          * As i40e supports less than 64 flow types, only first 64 bits need to
8518          * be configured.
8519          */
8520         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8521                 if (mask0 & (1UL << i)) {
8522                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8523                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8524
8525                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8526                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8527                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8528                                         i40e_write_global_rx_ctl(hw,
8529                                                           I40E_GLQF_HSYM(j),
8530                                                           reg);
8531                         }
8532                         i40e_global_cfg_warning(I40E_WARNING_HSYM);
8533                 }
8534         }
8535
8536         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8537         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8538                 /* Toeplitz */
8539                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8540                         PMD_DRV_LOG(DEBUG,
8541                                 "Hash function already set to Toeplitz");
8542                         goto out;
8543                 }
8544                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8545         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8546                 /* Simple XOR */
8547                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8548                         PMD_DRV_LOG(DEBUG,
8549                                 "Hash function already set to Simple XOR");
8550                         goto out;
8551                 }
8552                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8553         } else
8554                 /* Use the default, and keep it as it is */
8555                 goto out;
8556
8557         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8558         i40e_global_cfg_warning(I40E_WARNING_QF_CTL);
8559
8560 out:
8561         I40E_WRITE_FLUSH(hw);
8562
8563         return 0;
8564 }
8565
8566 /**
8567  * Valid input sets for hash and flow director filters per PCTYPE
8568  */
8569 static uint64_t
8570 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8571                 enum rte_filter_type filter)
8572 {
8573         uint64_t valid;
8574
8575         static const uint64_t valid_hash_inset_table[] = {
8576                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8577                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8578                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8579                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8580                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8581                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8582                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8583                         I40E_INSET_FLEX_PAYLOAD,
8584                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8585                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8586                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8587                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8588                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8589                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8590                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8591                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8592                         I40E_INSET_FLEX_PAYLOAD,
8593                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8594                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8595                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8596                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8597                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8598                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8599                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8600                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8601                         I40E_INSET_FLEX_PAYLOAD,
8602                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8603                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8604                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8605                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8606                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8607                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8608                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8609                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8610                         I40E_INSET_FLEX_PAYLOAD,
8611                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8612                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8613                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8614                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8615                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8616                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8617                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8618                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8619                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8620                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8621                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8622                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8623                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8624                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8625                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8626                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8627                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8628                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
8629                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8630                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8631                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8632                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8633                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8634                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8635                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8636                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8637                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
8638                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8639                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8640                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8641                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8642                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8643                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8644                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8645                         I40E_INSET_FLEX_PAYLOAD,
8646                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8647                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8648                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8649                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8650                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8651                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
8652                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
8653                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
8654                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8655                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8656                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8657                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8658                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8659                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8660                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8661                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
8662                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8663                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8664                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8665                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8666                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8667                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8668                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8669                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8670                         I40E_INSET_FLEX_PAYLOAD,
8671                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8672                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8673                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8674                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8675                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8676                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8677                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8678                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8679                         I40E_INSET_FLEX_PAYLOAD,
8680                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8681                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8682                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8683                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8684                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8685                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8686                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8687                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8688                         I40E_INSET_FLEX_PAYLOAD,
8689                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8690                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8691                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8692                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8693                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8694                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8695                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8696                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
8697                         I40E_INSET_FLEX_PAYLOAD,
8698                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8699                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8700                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8701                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8702                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8703                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8704                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
8705                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
8706                         I40E_INSET_FLEX_PAYLOAD,
8707                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8708                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8709                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8710                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
8711                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
8712                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
8713                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
8714                         I40E_INSET_FLEX_PAYLOAD,
8715                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8716                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8717                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8718                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
8719                         I40E_INSET_FLEX_PAYLOAD,
8720         };
8721
8722         /**
8723          * Flow director supports only fields defined in
8724          * union rte_eth_fdir_flow.
8725          */
8726         static const uint64_t valid_fdir_inset_table[] = {
8727                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8728                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8729                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8730                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8731                 I40E_INSET_IPV4_TTL,
8732                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8733                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8734                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8735                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8736                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8737                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8738                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8739                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8740                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8741                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8742                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8743                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8744                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8745                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8746                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8747                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8748                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8749                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8750                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8751                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8752                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8753                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8754                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8755                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8756                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8757                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8758                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8759                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8760                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
8761                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8762                 I40E_INSET_SCTP_VT,
8763                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8764                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8765                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8766                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
8767                 I40E_INSET_IPV4_TTL,
8768                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8769                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8770                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8771                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8772                 I40E_INSET_IPV6_HOP_LIMIT,
8773                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8774                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8775                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8776                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8777                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8778                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8779                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8780                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8781                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8782                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8783                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8784                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8785                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8786                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8787                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8788                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8789                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8790                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8791                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8792                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8793                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8794                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8795                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8796                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8797                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8798                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8799                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8800                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8801                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
8802                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8803                 I40E_INSET_SCTP_VT,
8804                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8805                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8806                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8807                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
8808                 I40E_INSET_IPV6_HOP_LIMIT,
8809                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8810                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8811                 I40E_INSET_LAST_ETHER_TYPE,
8812         };
8813
8814         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8815                 return 0;
8816         if (filter == RTE_ETH_FILTER_HASH)
8817                 valid = valid_hash_inset_table[pctype];
8818         else
8819                 valid = valid_fdir_inset_table[pctype];
8820
8821         return valid;
8822 }
8823
8824 /**
8825  * Validate if the input set is allowed for a specific PCTYPE
8826  */
8827 int
8828 i40e_validate_input_set(enum i40e_filter_pctype pctype,
8829                 enum rte_filter_type filter, uint64_t inset)
8830 {
8831         uint64_t valid;
8832
8833         valid = i40e_get_valid_input_set(pctype, filter);
8834         if (inset & (~valid))
8835                 return -EINVAL;
8836
8837         return 0;
8838 }
8839
8840 /* default input set fields combination per pctype */
8841 uint64_t
8842 i40e_get_default_input_set(uint16_t pctype)
8843 {
8844         static const uint64_t default_inset_table[] = {
8845                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8846                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8847                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8848                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8849                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8850                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
8851                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8852                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8853                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
8854                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8855                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8856                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
8857                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8858                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8859                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
8860                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8861                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8862                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
8863                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
8864                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8865                         I40E_INSET_SCTP_VT,
8866                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
8867                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
8868                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
8869                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8870                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
8871                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8872                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8873                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
8874                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8875                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8876                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
8877                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8878                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8879                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
8880                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8881                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8882                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
8883                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8884                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
8885                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
8886                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
8887                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
8888                         I40E_INSET_SCTP_VT,
8889                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
8890                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
8891                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
8892                         I40E_INSET_LAST_ETHER_TYPE,
8893         };
8894
8895         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
8896                 return 0;
8897
8898         return default_inset_table[pctype];
8899 }
8900
8901 /**
8902  * Parse the input set from index to logical bit masks
8903  */
8904 static int
8905 i40e_parse_input_set(uint64_t *inset,
8906                      enum i40e_filter_pctype pctype,
8907                      enum rte_eth_input_set_field *field,
8908                      uint16_t size)
8909 {
8910         uint16_t i, j;
8911         int ret = -EINVAL;
8912
8913         static const struct {
8914                 enum rte_eth_input_set_field field;
8915                 uint64_t inset;
8916         } inset_convert_table[] = {
8917                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
8918                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
8919                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
8920                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
8921                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
8922                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
8923                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
8924                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
8925                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
8926                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
8927                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
8928                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
8929                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
8930                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
8931                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
8932                         I40E_INSET_IPV6_NEXT_HDR},
8933                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
8934                         I40E_INSET_IPV6_HOP_LIMIT},
8935                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
8936                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
8937                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
8938                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
8939                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
8940                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
8941                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
8942                         I40E_INSET_SCTP_VT},
8943                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
8944                         I40E_INSET_TUNNEL_DMAC},
8945                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
8946                         I40E_INSET_VLAN_TUNNEL},
8947                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
8948                         I40E_INSET_TUNNEL_ID},
8949                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
8950                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
8951                         I40E_INSET_FLEX_PAYLOAD_W1},
8952                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
8953                         I40E_INSET_FLEX_PAYLOAD_W2},
8954                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
8955                         I40E_INSET_FLEX_PAYLOAD_W3},
8956                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
8957                         I40E_INSET_FLEX_PAYLOAD_W4},
8958                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
8959                         I40E_INSET_FLEX_PAYLOAD_W5},
8960                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
8961                         I40E_INSET_FLEX_PAYLOAD_W6},
8962                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
8963                         I40E_INSET_FLEX_PAYLOAD_W7},
8964                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
8965                         I40E_INSET_FLEX_PAYLOAD_W8},
8966         };
8967
8968         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
8969                 return ret;
8970
8971         /* Only one item allowed for default or all */
8972         if (size == 1) {
8973                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
8974                         *inset = i40e_get_default_input_set(pctype);
8975                         return 0;
8976                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
8977                         *inset = I40E_INSET_NONE;
8978                         return 0;
8979                 }
8980         }
8981
8982         for (i = 0, *inset = 0; i < size; i++) {
8983                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
8984                         if (field[i] == inset_convert_table[j].field) {
8985                                 *inset |= inset_convert_table[j].inset;
8986                                 break;
8987                         }
8988                 }
8989
8990                 /* It contains unsupported input set, return immediately */
8991                 if (j == RTE_DIM(inset_convert_table))
8992                         return ret;
8993         }
8994
8995         return 0;
8996 }
8997
8998 /**
8999  * Translate the input set from bit masks to register aware bit masks
9000  * and vice versa
9001  */
9002 uint64_t
9003 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9004 {
9005         uint64_t val = 0;
9006         uint16_t i;
9007
9008         struct inset_map {
9009                 uint64_t inset;
9010                 uint64_t inset_reg;
9011         };
9012
9013         static const struct inset_map inset_map_common[] = {
9014                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9015                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9016                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9017                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9018                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9019                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9020                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9021                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9022                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9023                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9024                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9025                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9026                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9027                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9028                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9029                 {I40E_INSET_TUNNEL_DMAC,
9030                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9031                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9032                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9033                 {I40E_INSET_TUNNEL_SRC_PORT,
9034                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9035                 {I40E_INSET_TUNNEL_DST_PORT,
9036                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9037                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9038                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9039                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9040                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9041                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9042                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9043                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9044                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9045                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9046         };
9047
9048     /* some different registers map in x722*/
9049         static const struct inset_map inset_map_diff_x722[] = {
9050                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9051                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9052                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9053                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9054         };
9055
9056         static const struct inset_map inset_map_diff_not_x722[] = {
9057                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9058                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9059                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9060                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9061         };
9062
9063         if (input == 0)
9064                 return val;
9065
9066         /* Translate input set to register aware inset */
9067         if (type == I40E_MAC_X722) {
9068                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9069                         if (input & inset_map_diff_x722[i].inset)
9070                                 val |= inset_map_diff_x722[i].inset_reg;
9071                 }
9072         } else {
9073                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9074                         if (input & inset_map_diff_not_x722[i].inset)
9075                                 val |= inset_map_diff_not_x722[i].inset_reg;
9076                 }
9077         }
9078
9079         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9080                 if (input & inset_map_common[i].inset)
9081                         val |= inset_map_common[i].inset_reg;
9082         }
9083
9084         return val;
9085 }
9086
9087 int
9088 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9089 {
9090         uint8_t i, idx = 0;
9091         uint64_t inset_need_mask = inset;
9092
9093         static const struct {
9094                 uint64_t inset;
9095                 uint32_t mask;
9096         } inset_mask_map[] = {
9097                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9098                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9099                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9100                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9101                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9102                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9103                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9104                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9105         };
9106
9107         if (!inset || !mask || !nb_elem)
9108                 return 0;
9109
9110         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9111                 /* Clear the inset bit, if no MASK is required,
9112                  * for example proto + ttl
9113                  */
9114                 if ((inset & inset_mask_map[i].inset) ==
9115                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9116                         inset_need_mask &= ~inset_mask_map[i].inset;
9117                 if (!inset_need_mask)
9118                         return 0;
9119         }
9120         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9121                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9122                     inset_mask_map[i].inset) {
9123                         if (idx >= nb_elem) {
9124                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9125                                 return -EINVAL;
9126                         }
9127                         mask[idx] = inset_mask_map[i].mask;
9128                         idx++;
9129                 }
9130         }
9131
9132         return idx;
9133 }
9134
9135 void
9136 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9137 {
9138         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9139
9140         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9141         if (reg != val)
9142                 i40e_write_rx_ctl(hw, addr, val);
9143         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9144                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9145 }
9146
9147 void
9148 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9149 {
9150         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9151
9152         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9153         if (reg != val)
9154                 i40e_write_global_rx_ctl(hw, addr, val);
9155         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9156                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9157 }
9158
9159 static void
9160 i40e_filter_input_set_init(struct i40e_pf *pf)
9161 {
9162         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9163         enum i40e_filter_pctype pctype;
9164         uint64_t input_set, inset_reg;
9165         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9166         int num, i;
9167         uint16_t flow_type;
9168
9169         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9170              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9171                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9172
9173                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9174                         continue;
9175
9176                 input_set = i40e_get_default_input_set(pctype);
9177
9178                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9179                                                    I40E_INSET_MASK_NUM_REG);
9180                 if (num < 0)
9181                         return;
9182                 if (pf->support_multi_driver && num > 0) {
9183                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9184                         return;
9185                 }
9186                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9187                                         input_set);
9188
9189                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9190                                       (uint32_t)(inset_reg & UINT32_MAX));
9191                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9192                                      (uint32_t)((inset_reg >>
9193                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9194                 if (!pf->support_multi_driver) {
9195                         i40e_check_write_global_reg(hw,
9196                                             I40E_GLQF_HASH_INSET(0, pctype),
9197                                             (uint32_t)(inset_reg & UINT32_MAX));
9198                         i40e_check_write_global_reg(hw,
9199                                              I40E_GLQF_HASH_INSET(1, pctype),
9200                                              (uint32_t)((inset_reg >>
9201                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9202
9203                         for (i = 0; i < num; i++) {
9204                                 i40e_check_write_global_reg(hw,
9205                                                     I40E_GLQF_FD_MSK(i, pctype),
9206                                                     mask_reg[i]);
9207                                 i40e_check_write_global_reg(hw,
9208                                                   I40E_GLQF_HASH_MSK(i, pctype),
9209                                                   mask_reg[i]);
9210                         }
9211                         /*clear unused mask registers of the pctype */
9212                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9213                                 i40e_check_write_global_reg(hw,
9214                                                     I40E_GLQF_FD_MSK(i, pctype),
9215                                                     0);
9216                                 i40e_check_write_global_reg(hw,
9217                                                   I40E_GLQF_HASH_MSK(i, pctype),
9218                                                   0);
9219                         }
9220                 } else {
9221                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9222                 }
9223                 I40E_WRITE_FLUSH(hw);
9224
9225                 /* store the default input set */
9226                 if (!pf->support_multi_driver)
9227                         pf->hash_input_set[pctype] = input_set;
9228                 pf->fdir.input_set[pctype] = input_set;
9229         }
9230
9231         if (!pf->support_multi_driver) {
9232                 i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9233                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9234                 i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9235         }
9236 }
9237
9238 int
9239 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9240                          struct rte_eth_input_set_conf *conf)
9241 {
9242         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9243         enum i40e_filter_pctype pctype;
9244         uint64_t input_set, inset_reg = 0;
9245         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9246         int ret, i, num;
9247
9248         if (!conf) {
9249                 PMD_DRV_LOG(ERR, "Invalid pointer");
9250                 return -EFAULT;
9251         }
9252         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9253             conf->op != RTE_ETH_INPUT_SET_ADD) {
9254                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9255                 return -EINVAL;
9256         }
9257
9258         if (pf->support_multi_driver) {
9259                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9260                 return -ENOTSUP;
9261         }
9262
9263         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9264         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9265                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9266                 return -EINVAL;
9267         }
9268
9269         if (hw->mac.type == I40E_MAC_X722) {
9270                 /* get translated pctype value in fd pctype register */
9271                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9272                         I40E_GLQF_FD_PCTYPES((int)pctype));
9273         }
9274
9275         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9276                                    conf->inset_size);
9277         if (ret) {
9278                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9279                 return -EINVAL;
9280         }
9281
9282         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9283                 /* get inset value in register */
9284                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9285                 inset_reg <<= I40E_32_BIT_WIDTH;
9286                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9287                 input_set |= pf->hash_input_set[pctype];
9288         }
9289         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9290                                            I40E_INSET_MASK_NUM_REG);
9291         if (num < 0)
9292                 return -EINVAL;
9293
9294         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9295
9296         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9297                                     (uint32_t)(inset_reg & UINT32_MAX));
9298         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9299                                     (uint32_t)((inset_reg >>
9300                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9301         i40e_global_cfg_warning(I40E_WARNING_HASH_INSET);
9302
9303         for (i = 0; i < num; i++)
9304                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9305                                             mask_reg[i]);
9306         /*clear unused mask registers of the pctype */
9307         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9308                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9309                                             0);
9310         i40e_global_cfg_warning(I40E_WARNING_HASH_MSK);
9311         I40E_WRITE_FLUSH(hw);
9312
9313         pf->hash_input_set[pctype] = input_set;
9314         return 0;
9315 }
9316
9317 int
9318 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9319                          struct rte_eth_input_set_conf *conf)
9320 {
9321         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9322         enum i40e_filter_pctype pctype;
9323         uint64_t input_set, inset_reg = 0;
9324         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9325         int ret, i, num;
9326
9327         if (!hw || !conf) {
9328                 PMD_DRV_LOG(ERR, "Invalid pointer");
9329                 return -EFAULT;
9330         }
9331         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9332             conf->op != RTE_ETH_INPUT_SET_ADD) {
9333                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9334                 return -EINVAL;
9335         }
9336
9337         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9338
9339         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9340                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9341                 return -EINVAL;
9342         }
9343
9344         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9345                                    conf->inset_size);
9346         if (ret) {
9347                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9348                 return -EINVAL;
9349         }
9350
9351         /* get inset value in register */
9352         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9353         inset_reg <<= I40E_32_BIT_WIDTH;
9354         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9355
9356         /* Can not change the inset reg for flex payload for fdir,
9357          * it is done by writing I40E_PRTQF_FD_FLXINSET
9358          * in i40e_set_flex_mask_on_pctype.
9359          */
9360         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9361                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9362         else
9363                 input_set |= pf->fdir.input_set[pctype];
9364         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9365                                            I40E_INSET_MASK_NUM_REG);
9366         if (num < 0)
9367                 return -EINVAL;
9368         if (pf->support_multi_driver && num > 0) {
9369                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9370                 return -ENOTSUP;
9371         }
9372
9373         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9374
9375         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9376                               (uint32_t)(inset_reg & UINT32_MAX));
9377         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9378                              (uint32_t)((inset_reg >>
9379                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9380
9381         if (!pf->support_multi_driver) {
9382                 for (i = 0; i < num; i++)
9383                         i40e_check_write_global_reg(hw,
9384                                                     I40E_GLQF_FD_MSK(i, pctype),
9385                                                     mask_reg[i]);
9386                 /*clear unused mask registers of the pctype */
9387                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9388                         i40e_check_write_global_reg(hw,
9389                                                     I40E_GLQF_FD_MSK(i, pctype),
9390                                                     0);
9391                 i40e_global_cfg_warning(I40E_WARNING_FD_MSK);
9392         } else {
9393                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9394         }
9395         I40E_WRITE_FLUSH(hw);
9396
9397         pf->fdir.input_set[pctype] = input_set;
9398         return 0;
9399 }
9400
9401 static int
9402 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9403 {
9404         int ret = 0;
9405
9406         if (!hw || !info) {
9407                 PMD_DRV_LOG(ERR, "Invalid pointer");
9408                 return -EFAULT;
9409         }
9410
9411         switch (info->info_type) {
9412         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9413                 i40e_get_symmetric_hash_enable_per_port(hw,
9414                                         &(info->info.enable));
9415                 break;
9416         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9417                 ret = i40e_get_hash_filter_global_config(hw,
9418                                 &(info->info.global_conf));
9419                 break;
9420         default:
9421                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9422                                                         info->info_type);
9423                 ret = -EINVAL;
9424                 break;
9425         }
9426
9427         return ret;
9428 }
9429
9430 static int
9431 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9432 {
9433         int ret = 0;
9434
9435         if (!hw || !info) {
9436                 PMD_DRV_LOG(ERR, "Invalid pointer");
9437                 return -EFAULT;
9438         }
9439
9440         switch (info->info_type) {
9441         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9442                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9443                 break;
9444         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9445                 ret = i40e_set_hash_filter_global_config(hw,
9446                                 &(info->info.global_conf));
9447                 break;
9448         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9449                 ret = i40e_hash_filter_inset_select(hw,
9450                                                &(info->info.input_set_conf));
9451                 break;
9452
9453         default:
9454                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9455                                                         info->info_type);
9456                 ret = -EINVAL;
9457                 break;
9458         }
9459
9460         return ret;
9461 }
9462
9463 /* Operations for hash function */
9464 static int
9465 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9466                       enum rte_filter_op filter_op,
9467                       void *arg)
9468 {
9469         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9470         int ret = 0;
9471
9472         switch (filter_op) {
9473         case RTE_ETH_FILTER_NOP:
9474                 break;
9475         case RTE_ETH_FILTER_GET:
9476                 ret = i40e_hash_filter_get(hw,
9477                         (struct rte_eth_hash_filter_info *)arg);
9478                 break;
9479         case RTE_ETH_FILTER_SET:
9480                 ret = i40e_hash_filter_set(hw,
9481                         (struct rte_eth_hash_filter_info *)arg);
9482                 break;
9483         default:
9484                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9485                                                                 filter_op);
9486                 ret = -ENOTSUP;
9487                 break;
9488         }
9489
9490         return ret;
9491 }
9492
9493 /* Convert ethertype filter structure */
9494 static int
9495 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9496                               struct i40e_ethertype_filter *filter)
9497 {
9498         rte_memcpy(&filter->input.mac_addr, &input->mac_addr, ETHER_ADDR_LEN);
9499         filter->input.ether_type = input->ether_type;
9500         filter->flags = input->flags;
9501         filter->queue = input->queue;
9502
9503         return 0;
9504 }
9505
9506 /* Check if there exists the ehtertype filter */
9507 struct i40e_ethertype_filter *
9508 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9509                                 const struct i40e_ethertype_filter_input *input)
9510 {
9511         int ret;
9512
9513         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9514         if (ret < 0)
9515                 return NULL;
9516
9517         return ethertype_rule->hash_map[ret];
9518 }
9519
9520 /* Add ethertype filter in SW list */
9521 static int
9522 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9523                                 struct i40e_ethertype_filter *filter)
9524 {
9525         struct i40e_ethertype_rule *rule = &pf->ethertype;
9526         int ret;
9527
9528         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9529         if (ret < 0) {
9530                 PMD_DRV_LOG(ERR,
9531                             "Failed to insert ethertype filter"
9532                             " to hash table %d!",
9533                             ret);
9534                 return ret;
9535         }
9536         rule->hash_map[ret] = filter;
9537
9538         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9539
9540         return 0;
9541 }
9542
9543 /* Delete ethertype filter in SW list */
9544 int
9545 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9546                              struct i40e_ethertype_filter_input *input)
9547 {
9548         struct i40e_ethertype_rule *rule = &pf->ethertype;
9549         struct i40e_ethertype_filter *filter;
9550         int ret;
9551
9552         ret = rte_hash_del_key(rule->hash_table, input);
9553         if (ret < 0) {
9554                 PMD_DRV_LOG(ERR,
9555                             "Failed to delete ethertype filter"
9556                             " to hash table %d!",
9557                             ret);
9558                 return ret;
9559         }
9560         filter = rule->hash_map[ret];
9561         rule->hash_map[ret] = NULL;
9562
9563         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9564         rte_free(filter);
9565
9566         return 0;
9567 }
9568
9569 /*
9570  * Configure ethertype filter, which can director packet by filtering
9571  * with mac address and ether_type or only ether_type
9572  */
9573 int
9574 i40e_ethertype_filter_set(struct i40e_pf *pf,
9575                         struct rte_eth_ethertype_filter *filter,
9576                         bool add)
9577 {
9578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9579         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9580         struct i40e_ethertype_filter *ethertype_filter, *node;
9581         struct i40e_ethertype_filter check_filter;
9582         struct i40e_control_filter_stats stats;
9583         uint16_t flags = 0;
9584         int ret;
9585
9586         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9587                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9588                 return -EINVAL;
9589         }
9590         if (filter->ether_type == ETHER_TYPE_IPv4 ||
9591                 filter->ether_type == ETHER_TYPE_IPv6) {
9592                 PMD_DRV_LOG(ERR,
9593                         "unsupported ether_type(0x%04x) in control packet filter.",
9594                         filter->ether_type);
9595                 return -EINVAL;
9596         }
9597         if (filter->ether_type == ETHER_TYPE_VLAN)
9598                 PMD_DRV_LOG(WARNING,
9599                         "filter vlan ether_type in first tag is not supported.");
9600
9601         /* Check if there is the filter in SW list */
9602         memset(&check_filter, 0, sizeof(check_filter));
9603         i40e_ethertype_filter_convert(filter, &check_filter);
9604         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
9605                                                &check_filter.input);
9606         if (add && node) {
9607                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
9608                 return -EINVAL;
9609         }
9610
9611         if (!add && !node) {
9612                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
9613                 return -EINVAL;
9614         }
9615
9616         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
9617                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
9618         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
9619                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
9620         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
9621
9622         memset(&stats, 0, sizeof(stats));
9623         ret = i40e_aq_add_rem_control_packet_filter(hw,
9624                         filter->mac_addr.addr_bytes,
9625                         filter->ether_type, flags,
9626                         pf->main_vsi->seid,
9627                         filter->queue, add, &stats, NULL);
9628
9629         PMD_DRV_LOG(INFO,
9630                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
9631                 ret, stats.mac_etype_used, stats.etype_used,
9632                 stats.mac_etype_free, stats.etype_free);
9633         if (ret < 0)
9634                 return -ENOSYS;
9635
9636         /* Add or delete a filter in SW list */
9637         if (add) {
9638                 ethertype_filter = rte_zmalloc("ethertype_filter",
9639                                        sizeof(*ethertype_filter), 0);
9640                 if (ethertype_filter == NULL) {
9641                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
9642                         return -ENOMEM;
9643                 }
9644
9645                 rte_memcpy(ethertype_filter, &check_filter,
9646                            sizeof(check_filter));
9647                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
9648                 if (ret < 0)
9649                         rte_free(ethertype_filter);
9650         } else {
9651                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
9652         }
9653
9654         return ret;
9655 }
9656
9657 /*
9658  * Handle operations for ethertype filter.
9659  */
9660 static int
9661 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
9662                                 enum rte_filter_op filter_op,
9663                                 void *arg)
9664 {
9665         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9666         int ret = 0;
9667
9668         if (filter_op == RTE_ETH_FILTER_NOP)
9669                 return ret;
9670
9671         if (arg == NULL) {
9672                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
9673                             filter_op);
9674                 return -EINVAL;
9675         }
9676
9677         switch (filter_op) {
9678         case RTE_ETH_FILTER_ADD:
9679                 ret = i40e_ethertype_filter_set(pf,
9680                         (struct rte_eth_ethertype_filter *)arg,
9681                         TRUE);
9682                 break;
9683         case RTE_ETH_FILTER_DELETE:
9684                 ret = i40e_ethertype_filter_set(pf,
9685                         (struct rte_eth_ethertype_filter *)arg,
9686                         FALSE);
9687                 break;
9688         default:
9689                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
9690                 ret = -ENOSYS;
9691                 break;
9692         }
9693         return ret;
9694 }
9695
9696 static int
9697 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
9698                      enum rte_filter_type filter_type,
9699                      enum rte_filter_op filter_op,
9700                      void *arg)
9701 {
9702         int ret = 0;
9703
9704         if (dev == NULL)
9705                 return -EINVAL;
9706
9707         switch (filter_type) {
9708         case RTE_ETH_FILTER_NONE:
9709                 /* For global configuration */
9710                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
9711                 break;
9712         case RTE_ETH_FILTER_HASH:
9713                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
9714                 break;
9715         case RTE_ETH_FILTER_MACVLAN:
9716                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
9717                 break;
9718         case RTE_ETH_FILTER_ETHERTYPE:
9719                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
9720                 break;
9721         case RTE_ETH_FILTER_TUNNEL:
9722                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
9723                 break;
9724         case RTE_ETH_FILTER_FDIR:
9725                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
9726                 break;
9727         case RTE_ETH_FILTER_GENERIC:
9728                 if (filter_op != RTE_ETH_FILTER_GET)
9729                         return -EINVAL;
9730                 *(const void **)arg = &i40e_flow_ops;
9731                 break;
9732         default:
9733                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
9734                                                         filter_type);
9735                 ret = -EINVAL;
9736                 break;
9737         }
9738
9739         return ret;
9740 }
9741
9742 /*
9743  * Check and enable Extended Tag.
9744  * Enabling Extended Tag is important for 40G performance.
9745  */
9746 static void
9747 i40e_enable_extended_tag(struct rte_eth_dev *dev)
9748 {
9749         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
9750         uint32_t buf = 0;
9751         int ret;
9752
9753         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9754                                       PCI_DEV_CAP_REG);
9755         if (ret < 0) {
9756                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9757                             PCI_DEV_CAP_REG);
9758                 return;
9759         }
9760         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
9761                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
9762                 return;
9763         }
9764
9765         buf = 0;
9766         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
9767                                       PCI_DEV_CTRL_REG);
9768         if (ret < 0) {
9769                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
9770                             PCI_DEV_CTRL_REG);
9771                 return;
9772         }
9773         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
9774                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
9775                 return;
9776         }
9777         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
9778         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
9779                                        PCI_DEV_CTRL_REG);
9780         if (ret < 0) {
9781                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
9782                             PCI_DEV_CTRL_REG);
9783                 return;
9784         }
9785 }
9786
9787 /*
9788  * As some registers wouldn't be reset unless a global hardware reset,
9789  * hardware initialization is needed to put those registers into an
9790  * expected initial state.
9791  */
9792 static void
9793 i40e_hw_init(struct rte_eth_dev *dev)
9794 {
9795         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9796
9797         i40e_enable_extended_tag(dev);
9798
9799         /* clear the PF Queue Filter control register */
9800         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
9801
9802         /* Disable symmetric hash per port */
9803         i40e_set_symmetric_hash_enable_per_port(hw, 0);
9804 }
9805
9806 /*
9807  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
9808  * however this function will return only one highest pctype index,
9809  * which is not quite correct. This is known problem of i40e driver
9810  * and needs to be fixed later.
9811  */
9812 enum i40e_filter_pctype
9813 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
9814 {
9815         int i;
9816         uint64_t pctype_mask;
9817
9818         if (flow_type < I40E_FLOW_TYPE_MAX) {
9819                 pctype_mask = adapter->pctypes_tbl[flow_type];
9820                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
9821                         if (pctype_mask & (1ULL << i))
9822                                 return (enum i40e_filter_pctype)i;
9823                 }
9824         }
9825         return I40E_FILTER_PCTYPE_INVALID;
9826 }
9827
9828 uint16_t
9829 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
9830                         enum i40e_filter_pctype pctype)
9831 {
9832         uint16_t flowtype;
9833         uint64_t pctype_mask = 1ULL << pctype;
9834
9835         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
9836              flowtype++) {
9837                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
9838                         return flowtype;
9839         }
9840
9841         return RTE_ETH_FLOW_UNKNOWN;
9842 }
9843
9844 /*
9845  * On X710, performance number is far from the expectation on recent firmware
9846  * versions; on XL710, performance number is also far from the expectation on
9847  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
9848  * mode is enabled and port MAC address is equal to the packet destination MAC
9849  * address. The fix for this issue may not be integrated in the following
9850  * firmware version. So the workaround in software driver is needed. It needs
9851  * to modify the initial values of 3 internal only registers for both X710 and
9852  * XL710. Note that the values for X710 or XL710 could be different, and the
9853  * workaround can be removed when it is fixed in firmware in the future.
9854  */
9855
9856 /* For both X710 and XL710 */
9857 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
9858 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
9859 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
9860
9861 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
9862 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
9863
9864 /* For X722 */
9865 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
9866 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
9867
9868 /* For X710 */
9869 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
9870 /* For XL710 */
9871 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
9872 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
9873
9874 static int
9875 i40e_dev_sync_phy_type(struct i40e_hw *hw)
9876 {
9877         enum i40e_status_code status;
9878         struct i40e_aq_get_phy_abilities_resp phy_ab;
9879         int ret = -ENOTSUP;
9880         int retries = 0;
9881
9882         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
9883                                               NULL);
9884
9885         while (status) {
9886                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
9887                         status);
9888                 retries++;
9889                 rte_delay_us(100000);
9890                 if  (retries < 5)
9891                         status = i40e_aq_get_phy_capabilities(hw, false,
9892                                         true, &phy_ab, NULL);
9893                 else
9894                         return ret;
9895         }
9896         return 0;
9897 }
9898
9899 static void
9900 i40e_configure_registers(struct i40e_hw *hw)
9901 {
9902         static struct {
9903                 uint32_t addr;
9904                 uint64_t val;
9905         } reg_table[] = {
9906                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
9907                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
9908                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
9909         };
9910         uint64_t reg;
9911         uint32_t i;
9912         int ret;
9913
9914         for (i = 0; i < RTE_DIM(reg_table); i++) {
9915                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
9916                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9917                                 reg_table[i].val =
9918                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
9919                         else /* For X710/XL710/XXV710 */
9920                                 if (hw->aq.fw_maj_ver < 6)
9921                                         reg_table[i].val =
9922                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
9923                                 else
9924                                         reg_table[i].val =
9925                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
9926                 }
9927
9928                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
9929                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
9930                                 reg_table[i].val =
9931                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9932                         else /* For X710/XL710/XXV710 */
9933                                 reg_table[i].val =
9934                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
9935                 }
9936
9937                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
9938                         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types) || /* For XL710 */
9939                             I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) /* For XXV710 */
9940                                 reg_table[i].val =
9941                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
9942                         else /* For X710 */
9943                                 reg_table[i].val =
9944                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
9945                 }
9946
9947                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
9948                                                         &reg, NULL);
9949                 if (ret < 0) {
9950                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
9951                                                         reg_table[i].addr);
9952                         break;
9953                 }
9954                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
9955                                                 reg_table[i].addr, reg);
9956                 if (reg == reg_table[i].val)
9957                         continue;
9958
9959                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
9960                                                 reg_table[i].val, NULL);
9961                 if (ret < 0) {
9962                         PMD_DRV_LOG(ERR,
9963                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
9964                                 reg_table[i].val, reg_table[i].addr);
9965                         break;
9966                 }
9967                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
9968                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
9969         }
9970 }
9971
9972 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
9973 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
9974 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
9975 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
9976 static int
9977 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
9978 {
9979         uint32_t reg;
9980         int ret;
9981
9982         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
9983                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
9984                 return -EINVAL;
9985         }
9986
9987         /* Configure for double VLAN RX stripping */
9988         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
9989         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
9990                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
9991                 ret = i40e_aq_debug_write_register(hw,
9992                                                    I40E_VSI_TSR(vsi->vsi_id),
9993                                                    reg, NULL);
9994                 if (ret < 0) {
9995                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
9996                                     vsi->vsi_id);
9997                         return I40E_ERR_CONFIG;
9998                 }
9999         }
10000
10001         /* Configure for double VLAN TX insertion */
10002         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10003         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10004                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10005                 ret = i40e_aq_debug_write_register(hw,
10006                                                    I40E_VSI_L2TAGSTXVALID(
10007                                                    vsi->vsi_id), reg, NULL);
10008                 if (ret < 0) {
10009                         PMD_DRV_LOG(ERR,
10010                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10011                                 vsi->vsi_id);
10012                         return I40E_ERR_CONFIG;
10013                 }
10014         }
10015
10016         return 0;
10017 }
10018
10019 /**
10020  * i40e_aq_add_mirror_rule
10021  * @hw: pointer to the hardware structure
10022  * @seid: VEB seid to add mirror rule to
10023  * @dst_id: destination vsi seid
10024  * @entries: Buffer which contains the entities to be mirrored
10025  * @count: number of entities contained in the buffer
10026  * @rule_id:the rule_id of the rule to be added
10027  *
10028  * Add a mirror rule for a given veb.
10029  *
10030  **/
10031 static enum i40e_status_code
10032 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10033                         uint16_t seid, uint16_t dst_id,
10034                         uint16_t rule_type, uint16_t *entries,
10035                         uint16_t count, uint16_t *rule_id)
10036 {
10037         struct i40e_aq_desc desc;
10038         struct i40e_aqc_add_delete_mirror_rule cmd;
10039         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10040                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10041                 &desc.params.raw;
10042         uint16_t buff_len;
10043         enum i40e_status_code status;
10044
10045         i40e_fill_default_direct_cmd_desc(&desc,
10046                                           i40e_aqc_opc_add_mirror_rule);
10047         memset(&cmd, 0, sizeof(cmd));
10048
10049         buff_len = sizeof(uint16_t) * count;
10050         desc.datalen = rte_cpu_to_le_16(buff_len);
10051         if (buff_len > 0)
10052                 desc.flags |= rte_cpu_to_le_16(
10053                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10054         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10055                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10056         cmd.num_entries = rte_cpu_to_le_16(count);
10057         cmd.seid = rte_cpu_to_le_16(seid);
10058         cmd.destination = rte_cpu_to_le_16(dst_id);
10059
10060         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10061         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10062         PMD_DRV_LOG(INFO,
10063                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10064                 hw->aq.asq_last_status, resp->rule_id,
10065                 resp->mirror_rules_used, resp->mirror_rules_free);
10066         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10067
10068         return status;
10069 }
10070
10071 /**
10072  * i40e_aq_del_mirror_rule
10073  * @hw: pointer to the hardware structure
10074  * @seid: VEB seid to add mirror rule to
10075  * @entries: Buffer which contains the entities to be mirrored
10076  * @count: number of entities contained in the buffer
10077  * @rule_id:the rule_id of the rule to be delete
10078  *
10079  * Delete a mirror rule for a given veb.
10080  *
10081  **/
10082 static enum i40e_status_code
10083 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10084                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10085                 uint16_t count, uint16_t rule_id)
10086 {
10087         struct i40e_aq_desc desc;
10088         struct i40e_aqc_add_delete_mirror_rule cmd;
10089         uint16_t buff_len = 0;
10090         enum i40e_status_code status;
10091         void *buff = NULL;
10092
10093         i40e_fill_default_direct_cmd_desc(&desc,
10094                                           i40e_aqc_opc_delete_mirror_rule);
10095         memset(&cmd, 0, sizeof(cmd));
10096         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10097                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10098                                                           I40E_AQ_FLAG_RD));
10099                 cmd.num_entries = count;
10100                 buff_len = sizeof(uint16_t) * count;
10101                 desc.datalen = rte_cpu_to_le_16(buff_len);
10102                 buff = (void *)entries;
10103         } else
10104                 /* rule id is filled in destination field for deleting mirror rule */
10105                 cmd.destination = rte_cpu_to_le_16(rule_id);
10106
10107         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10108                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10109         cmd.seid = rte_cpu_to_le_16(seid);
10110
10111         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10112         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10113
10114         return status;
10115 }
10116
10117 /**
10118  * i40e_mirror_rule_set
10119  * @dev: pointer to the hardware structure
10120  * @mirror_conf: mirror rule info
10121  * @sw_id: mirror rule's sw_id
10122  * @on: enable/disable
10123  *
10124  * set a mirror rule.
10125  *
10126  **/
10127 static int
10128 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10129                         struct rte_eth_mirror_conf *mirror_conf,
10130                         uint8_t sw_id, uint8_t on)
10131 {
10132         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10133         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10134         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10135         struct i40e_mirror_rule *parent = NULL;
10136         uint16_t seid, dst_seid, rule_id;
10137         uint16_t i, j = 0;
10138         int ret;
10139
10140         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10141
10142         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10143                 PMD_DRV_LOG(ERR,
10144                         "mirror rule can not be configured without veb or vfs.");
10145                 return -ENOSYS;
10146         }
10147         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10148                 PMD_DRV_LOG(ERR, "mirror table is full.");
10149                 return -ENOSPC;
10150         }
10151         if (mirror_conf->dst_pool > pf->vf_num) {
10152                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10153                                  mirror_conf->dst_pool);
10154                 return -EINVAL;
10155         }
10156
10157         seid = pf->main_vsi->veb->seid;
10158
10159         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10160                 if (sw_id <= it->index) {
10161                         mirr_rule = it;
10162                         break;
10163                 }
10164                 parent = it;
10165         }
10166         if (mirr_rule && sw_id == mirr_rule->index) {
10167                 if (on) {
10168                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10169                         return -EEXIST;
10170                 } else {
10171                         ret = i40e_aq_del_mirror_rule(hw, seid,
10172                                         mirr_rule->rule_type,
10173                                         mirr_rule->entries,
10174                                         mirr_rule->num_entries, mirr_rule->id);
10175                         if (ret < 0) {
10176                                 PMD_DRV_LOG(ERR,
10177                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10178                                         ret, hw->aq.asq_last_status);
10179                                 return -ENOSYS;
10180                         }
10181                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10182                         rte_free(mirr_rule);
10183                         pf->nb_mirror_rule--;
10184                         return 0;
10185                 }
10186         } else if (!on) {
10187                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10188                 return -ENOENT;
10189         }
10190
10191         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10192                                 sizeof(struct i40e_mirror_rule) , 0);
10193         if (!mirr_rule) {
10194                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10195                 return I40E_ERR_NO_MEMORY;
10196         }
10197         switch (mirror_conf->rule_type) {
10198         case ETH_MIRROR_VLAN:
10199                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10200                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10201                                 mirr_rule->entries[j] =
10202                                         mirror_conf->vlan.vlan_id[i];
10203                                 j++;
10204                         }
10205                 }
10206                 if (j == 0) {
10207                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10208                         rte_free(mirr_rule);
10209                         return -EINVAL;
10210                 }
10211                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10212                 break;
10213         case ETH_MIRROR_VIRTUAL_POOL_UP:
10214         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10215                 /* check if the specified pool bit is out of range */
10216                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10217                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10218                         rte_free(mirr_rule);
10219                         return -EINVAL;
10220                 }
10221                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10222                         if (mirror_conf->pool_mask & (1ULL << i)) {
10223                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10224                                 j++;
10225                         }
10226                 }
10227                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10228                         /* add pf vsi to entries */
10229                         mirr_rule->entries[j] = pf->main_vsi_seid;
10230                         j++;
10231                 }
10232                 if (j == 0) {
10233                         PMD_DRV_LOG(ERR, "pool is not specified.");
10234                         rte_free(mirr_rule);
10235                         return -EINVAL;
10236                 }
10237                 /* egress and ingress in aq commands means from switch but not port */
10238                 mirr_rule->rule_type =
10239                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10240                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10241                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10242                 break;
10243         case ETH_MIRROR_UPLINK_PORT:
10244                 /* egress and ingress in aq commands means from switch but not port*/
10245                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10246                 break;
10247         case ETH_MIRROR_DOWNLINK_PORT:
10248                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10249                 break;
10250         default:
10251                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10252                         mirror_conf->rule_type);
10253                 rte_free(mirr_rule);
10254                 return -EINVAL;
10255         }
10256
10257         /* If the dst_pool is equal to vf_num, consider it as PF */
10258         if (mirror_conf->dst_pool == pf->vf_num)
10259                 dst_seid = pf->main_vsi_seid;
10260         else
10261                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10262
10263         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10264                                       mirr_rule->rule_type, mirr_rule->entries,
10265                                       j, &rule_id);
10266         if (ret < 0) {
10267                 PMD_DRV_LOG(ERR,
10268                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10269                         ret, hw->aq.asq_last_status);
10270                 rte_free(mirr_rule);
10271                 return -ENOSYS;
10272         }
10273
10274         mirr_rule->index = sw_id;
10275         mirr_rule->num_entries = j;
10276         mirr_rule->id = rule_id;
10277         mirr_rule->dst_vsi_seid = dst_seid;
10278
10279         if (parent)
10280                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10281         else
10282                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10283
10284         pf->nb_mirror_rule++;
10285         return 0;
10286 }
10287
10288 /**
10289  * i40e_mirror_rule_reset
10290  * @dev: pointer to the device
10291  * @sw_id: mirror rule's sw_id
10292  *
10293  * reset a mirror rule.
10294  *
10295  **/
10296 static int
10297 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10298 {
10299         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10300         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10301         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10302         uint16_t seid;
10303         int ret;
10304
10305         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10306
10307         seid = pf->main_vsi->veb->seid;
10308
10309         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10310                 if (sw_id == it->index) {
10311                         mirr_rule = it;
10312                         break;
10313                 }
10314         }
10315         if (mirr_rule) {
10316                 ret = i40e_aq_del_mirror_rule(hw, seid,
10317                                 mirr_rule->rule_type,
10318                                 mirr_rule->entries,
10319                                 mirr_rule->num_entries, mirr_rule->id);
10320                 if (ret < 0) {
10321                         PMD_DRV_LOG(ERR,
10322                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10323                                 ret, hw->aq.asq_last_status);
10324                         return -ENOSYS;
10325                 }
10326                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10327                 rte_free(mirr_rule);
10328                 pf->nb_mirror_rule--;
10329         } else {
10330                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10331                 return -ENOENT;
10332         }
10333         return 0;
10334 }
10335
10336 static uint64_t
10337 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10338 {
10339         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10340         uint64_t systim_cycles;
10341
10342         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10343         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10344                         << 32;
10345
10346         return systim_cycles;
10347 }
10348
10349 static uint64_t
10350 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10351 {
10352         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10353         uint64_t rx_tstamp;
10354
10355         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10356         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10357                         << 32;
10358
10359         return rx_tstamp;
10360 }
10361
10362 static uint64_t
10363 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10364 {
10365         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10366         uint64_t tx_tstamp;
10367
10368         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10369         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10370                         << 32;
10371
10372         return tx_tstamp;
10373 }
10374
10375 static void
10376 i40e_start_timecounters(struct rte_eth_dev *dev)
10377 {
10378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10379         struct i40e_adapter *adapter =
10380                         (struct i40e_adapter *)dev->data->dev_private;
10381         struct rte_eth_link link;
10382         uint32_t tsync_inc_l;
10383         uint32_t tsync_inc_h;
10384
10385         /* Get current link speed. */
10386         memset(&link, 0, sizeof(link));
10387         i40e_dev_link_update(dev, 1);
10388         rte_i40e_dev_atomic_read_link_status(dev, &link);
10389
10390         switch (link.link_speed) {
10391         case ETH_SPEED_NUM_40G:
10392                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10393                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10394                 break;
10395         case ETH_SPEED_NUM_10G:
10396                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10397                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10398                 break;
10399         case ETH_SPEED_NUM_1G:
10400                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10401                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10402                 break;
10403         default:
10404                 tsync_inc_l = 0x0;
10405                 tsync_inc_h = 0x0;
10406         }
10407
10408         /* Set the timesync increment value. */
10409         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10410         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10411
10412         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10413         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10414         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10415
10416         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10417         adapter->systime_tc.cc_shift = 0;
10418         adapter->systime_tc.nsec_mask = 0;
10419
10420         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10421         adapter->rx_tstamp_tc.cc_shift = 0;
10422         adapter->rx_tstamp_tc.nsec_mask = 0;
10423
10424         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10425         adapter->tx_tstamp_tc.cc_shift = 0;
10426         adapter->tx_tstamp_tc.nsec_mask = 0;
10427 }
10428
10429 static int
10430 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10431 {
10432         struct i40e_adapter *adapter =
10433                         (struct i40e_adapter *)dev->data->dev_private;
10434
10435         adapter->systime_tc.nsec += delta;
10436         adapter->rx_tstamp_tc.nsec += delta;
10437         adapter->tx_tstamp_tc.nsec += delta;
10438
10439         return 0;
10440 }
10441
10442 static int
10443 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10444 {
10445         uint64_t ns;
10446         struct i40e_adapter *adapter =
10447                         (struct i40e_adapter *)dev->data->dev_private;
10448
10449         ns = rte_timespec_to_ns(ts);
10450
10451         /* Set the timecounters to a new value. */
10452         adapter->systime_tc.nsec = ns;
10453         adapter->rx_tstamp_tc.nsec = ns;
10454         adapter->tx_tstamp_tc.nsec = ns;
10455
10456         return 0;
10457 }
10458
10459 static int
10460 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10461 {
10462         uint64_t ns, systime_cycles;
10463         struct i40e_adapter *adapter =
10464                         (struct i40e_adapter *)dev->data->dev_private;
10465
10466         systime_cycles = i40e_read_systime_cyclecounter(dev);
10467         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10468         *ts = rte_ns_to_timespec(ns);
10469
10470         return 0;
10471 }
10472
10473 static int
10474 i40e_timesync_enable(struct rte_eth_dev *dev)
10475 {
10476         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10477         uint32_t tsync_ctl_l;
10478         uint32_t tsync_ctl_h;
10479
10480         /* Stop the timesync system time. */
10481         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10482         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10483         /* Reset the timesync system time value. */
10484         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10485         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10486
10487         i40e_start_timecounters(dev);
10488
10489         /* Clear timesync registers. */
10490         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10491         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10492         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10493         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10494         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10495         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10496
10497         /* Enable timestamping of PTP packets. */
10498         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10499         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10500
10501         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10502         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10503         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10504
10505         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10506         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10507
10508         return 0;
10509 }
10510
10511 static int
10512 i40e_timesync_disable(struct rte_eth_dev *dev)
10513 {
10514         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10515         uint32_t tsync_ctl_l;
10516         uint32_t tsync_ctl_h;
10517
10518         /* Disable timestamping of transmitted PTP packets. */
10519         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10520         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10521
10522         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10523         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10524
10525         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10526         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10527
10528         /* Reset the timesync increment value. */
10529         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10530         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10531
10532         return 0;
10533 }
10534
10535 static int
10536 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10537                                 struct timespec *timestamp, uint32_t flags)
10538 {
10539         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10540         struct i40e_adapter *adapter =
10541                 (struct i40e_adapter *)dev->data->dev_private;
10542
10543         uint32_t sync_status;
10544         uint32_t index = flags & 0x03;
10545         uint64_t rx_tstamp_cycles;
10546         uint64_t ns;
10547
10548         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
10549         if ((sync_status & (1 << index)) == 0)
10550                 return -EINVAL;
10551
10552         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
10553         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
10554         *timestamp = rte_ns_to_timespec(ns);
10555
10556         return 0;
10557 }
10558
10559 static int
10560 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
10561                                 struct timespec *timestamp)
10562 {
10563         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10564         struct i40e_adapter *adapter =
10565                 (struct i40e_adapter *)dev->data->dev_private;
10566
10567         uint32_t sync_status;
10568         uint64_t tx_tstamp_cycles;
10569         uint64_t ns;
10570
10571         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10572         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
10573                 return -EINVAL;
10574
10575         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
10576         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
10577         *timestamp = rte_ns_to_timespec(ns);
10578
10579         return 0;
10580 }
10581
10582 /*
10583  * i40e_parse_dcb_configure - parse dcb configure from user
10584  * @dev: the device being configured
10585  * @dcb_cfg: pointer of the result of parse
10586  * @*tc_map: bit map of enabled traffic classes
10587  *
10588  * Returns 0 on success, negative value on failure
10589  */
10590 static int
10591 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
10592                          struct i40e_dcbx_config *dcb_cfg,
10593                          uint8_t *tc_map)
10594 {
10595         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
10596         uint8_t i, tc_bw, bw_lf;
10597
10598         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
10599
10600         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
10601         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
10602                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
10603                 return -EINVAL;
10604         }
10605
10606         /* assume each tc has the same bw */
10607         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
10608         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10609                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
10610         /* to ensure the sum of tcbw is equal to 100 */
10611         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
10612         for (i = 0; i < bw_lf; i++)
10613                 dcb_cfg->etscfg.tcbwtable[i]++;
10614
10615         /* assume each tc has the same Transmission Selection Algorithm */
10616         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
10617                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
10618
10619         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
10620                 dcb_cfg->etscfg.prioritytable[i] =
10621                                 dcb_rx_conf->dcb_tc[i];
10622
10623         /* FW needs one App to configure HW */
10624         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
10625         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
10626         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
10627         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
10628
10629         if (dcb_rx_conf->nb_tcs == 0)
10630                 *tc_map = 1; /* tc0 only */
10631         else
10632                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
10633
10634         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
10635                 dcb_cfg->pfc.willing = 0;
10636                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
10637                 dcb_cfg->pfc.pfcenable = *tc_map;
10638         }
10639         return 0;
10640 }
10641
10642
10643 static enum i40e_status_code
10644 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
10645                               struct i40e_aqc_vsi_properties_data *info,
10646                               uint8_t enabled_tcmap)
10647 {
10648         enum i40e_status_code ret;
10649         int i, total_tc = 0;
10650         uint16_t qpnum_per_tc, bsf, qp_idx;
10651         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
10652         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
10653         uint16_t used_queues;
10654
10655         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
10656         if (ret != I40E_SUCCESS)
10657                 return ret;
10658
10659         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10660                 if (enabled_tcmap & (1 << i))
10661                         total_tc++;
10662         }
10663         if (total_tc == 0)
10664                 total_tc = 1;
10665         vsi->enabled_tc = enabled_tcmap;
10666
10667         /* different VSI has different queues assigned */
10668         if (vsi->type == I40E_VSI_MAIN)
10669                 used_queues = dev_data->nb_rx_queues -
10670                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10671         else if (vsi->type == I40E_VSI_VMDQ2)
10672                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
10673         else {
10674                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
10675                 return I40E_ERR_NO_AVAILABLE_VSI;
10676         }
10677
10678         qpnum_per_tc = used_queues / total_tc;
10679         /* Number of queues per enabled TC */
10680         if (qpnum_per_tc == 0) {
10681                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
10682                 return I40E_ERR_INVALID_QP_ID;
10683         }
10684         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
10685                                 I40E_MAX_Q_PER_TC);
10686         bsf = rte_bsf32(qpnum_per_tc);
10687
10688         /**
10689          * Configure TC and queue mapping parameters, for enabled TC,
10690          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
10691          * default queue will serve it.
10692          */
10693         qp_idx = 0;
10694         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10695                 if (vsi->enabled_tc & (1 << i)) {
10696                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
10697                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
10698                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
10699                         qp_idx += qpnum_per_tc;
10700                 } else
10701                         info->tc_mapping[i] = 0;
10702         }
10703
10704         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
10705         if (vsi->type == I40E_VSI_SRIOV) {
10706                 info->mapping_flags |=
10707                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
10708                 for (i = 0; i < vsi->nb_qps; i++)
10709                         info->queue_mapping[i] =
10710                                 rte_cpu_to_le_16(vsi->base_queue + i);
10711         } else {
10712                 info->mapping_flags |=
10713                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
10714                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
10715         }
10716         info->valid_sections |=
10717                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
10718
10719         return I40E_SUCCESS;
10720 }
10721
10722 /*
10723  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
10724  * @veb: VEB to be configured
10725  * @tc_map: enabled TC bitmap
10726  *
10727  * Returns 0 on success, negative value on failure
10728  */
10729 static enum i40e_status_code
10730 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
10731 {
10732         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
10733         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
10734         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
10735         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
10736         enum i40e_status_code ret = I40E_SUCCESS;
10737         int i;
10738         uint32_t bw_max;
10739
10740         /* Check if enabled_tc is same as existing or new TCs */
10741         if (veb->enabled_tc == tc_map)
10742                 return ret;
10743
10744         /* configure tc bandwidth */
10745         memset(&veb_bw, 0, sizeof(veb_bw));
10746         veb_bw.tc_valid_bits = tc_map;
10747         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10748         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10749                 if (tc_map & BIT_ULL(i))
10750                         veb_bw.tc_bw_share_credits[i] = 1;
10751         }
10752         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
10753                                                    &veb_bw, NULL);
10754         if (ret) {
10755                 PMD_INIT_LOG(ERR,
10756                         "AQ command Config switch_comp BW allocation per TC failed = %d",
10757                         hw->aq.asq_last_status);
10758                 return ret;
10759         }
10760
10761         memset(&ets_query, 0, sizeof(ets_query));
10762         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
10763                                                    &ets_query, NULL);
10764         if (ret != I40E_SUCCESS) {
10765                 PMD_DRV_LOG(ERR,
10766                         "Failed to get switch_comp ETS configuration %u",
10767                         hw->aq.asq_last_status);
10768                 return ret;
10769         }
10770         memset(&bw_query, 0, sizeof(bw_query));
10771         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
10772                                                   &bw_query, NULL);
10773         if (ret != I40E_SUCCESS) {
10774                 PMD_DRV_LOG(ERR,
10775                         "Failed to get switch_comp bandwidth configuration %u",
10776                         hw->aq.asq_last_status);
10777                 return ret;
10778         }
10779
10780         /* store and print out BW info */
10781         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
10782         veb->bw_info.bw_max = ets_query.tc_bw_max;
10783         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
10784         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
10785         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
10786                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
10787                      I40E_16_BIT_WIDTH);
10788         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10789                 veb->bw_info.bw_ets_share_credits[i] =
10790                                 bw_query.tc_bw_share_credits[i];
10791                 veb->bw_info.bw_ets_credits[i] =
10792                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
10793                 /* 4 bits per TC, 4th bit is reserved */
10794                 veb->bw_info.bw_ets_max[i] =
10795                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
10796                                   RTE_LEN2MASK(3, uint8_t));
10797                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
10798                             veb->bw_info.bw_ets_share_credits[i]);
10799                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
10800                             veb->bw_info.bw_ets_credits[i]);
10801                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
10802                             veb->bw_info.bw_ets_max[i]);
10803         }
10804
10805         veb->enabled_tc = tc_map;
10806
10807         return ret;
10808 }
10809
10810
10811 /*
10812  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
10813  * @vsi: VSI to be configured
10814  * @tc_map: enabled TC bitmap
10815  *
10816  * Returns 0 on success, negative value on failure
10817  */
10818 static enum i40e_status_code
10819 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
10820 {
10821         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
10822         struct i40e_vsi_context ctxt;
10823         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
10824         enum i40e_status_code ret = I40E_SUCCESS;
10825         int i;
10826
10827         /* Check if enabled_tc is same as existing or new TCs */
10828         if (vsi->enabled_tc == tc_map)
10829                 return ret;
10830
10831         /* configure tc bandwidth */
10832         memset(&bw_data, 0, sizeof(bw_data));
10833         bw_data.tc_valid_bits = tc_map;
10834         /* Enable ETS TCs with equal BW Share for now across all VSIs */
10835         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
10836                 if (tc_map & BIT_ULL(i))
10837                         bw_data.tc_bw_credits[i] = 1;
10838         }
10839         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
10840         if (ret) {
10841                 PMD_INIT_LOG(ERR,
10842                         "AQ command Config VSI BW allocation per TC failed = %d",
10843                         hw->aq.asq_last_status);
10844                 goto out;
10845         }
10846         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
10847                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
10848
10849         /* Update Queue Pairs Mapping for currently enabled UPs */
10850         ctxt.seid = vsi->seid;
10851         ctxt.pf_num = hw->pf_id;
10852         ctxt.vf_num = 0;
10853         ctxt.uplink_seid = vsi->uplink_seid;
10854         ctxt.info = vsi->info;
10855         i40e_get_cap(hw);
10856         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
10857         if (ret)
10858                 goto out;
10859
10860         /* Update the VSI after updating the VSI queue-mapping information */
10861         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
10862         if (ret) {
10863                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
10864                         hw->aq.asq_last_status);
10865                 goto out;
10866         }
10867         /* update the local VSI info with updated queue map */
10868         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
10869                                         sizeof(vsi->info.tc_mapping));
10870         rte_memcpy(&vsi->info.queue_mapping,
10871                         &ctxt.info.queue_mapping,
10872                 sizeof(vsi->info.queue_mapping));
10873         vsi->info.mapping_flags = ctxt.info.mapping_flags;
10874         vsi->info.valid_sections = 0;
10875
10876         /* query and update current VSI BW information */
10877         ret = i40e_vsi_get_bw_config(vsi);
10878         if (ret) {
10879                 PMD_INIT_LOG(ERR,
10880                          "Failed updating vsi bw info, err %s aq_err %s",
10881                          i40e_stat_str(hw, ret),
10882                          i40e_aq_str(hw, hw->aq.asq_last_status));
10883                 goto out;
10884         }
10885
10886         vsi->enabled_tc = tc_map;
10887
10888 out:
10889         return ret;
10890 }
10891
10892 /*
10893  * i40e_dcb_hw_configure - program the dcb setting to hw
10894  * @pf: pf the configuration is taken on
10895  * @new_cfg: new configuration
10896  * @tc_map: enabled TC bitmap
10897  *
10898  * Returns 0 on success, negative value on failure
10899  */
10900 static enum i40e_status_code
10901 i40e_dcb_hw_configure(struct i40e_pf *pf,
10902                       struct i40e_dcbx_config *new_cfg,
10903                       uint8_t tc_map)
10904 {
10905         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10906         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
10907         struct i40e_vsi *main_vsi = pf->main_vsi;
10908         struct i40e_vsi_list *vsi_list;
10909         enum i40e_status_code ret;
10910         int i;
10911         uint32_t val;
10912
10913         /* Use the FW API if FW > v4.4*/
10914         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
10915               (hw->aq.fw_maj_ver >= 5))) {
10916                 PMD_INIT_LOG(ERR,
10917                         "FW < v4.4, can not use FW LLDP API to configure DCB");
10918                 return I40E_ERR_FIRMWARE_API_VERSION;
10919         }
10920
10921         /* Check if need reconfiguration */
10922         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
10923                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
10924                 return I40E_SUCCESS;
10925         }
10926
10927         /* Copy the new config to the current config */
10928         *old_cfg = *new_cfg;
10929         old_cfg->etsrec = old_cfg->etscfg;
10930         ret = i40e_set_dcb_config(hw);
10931         if (ret) {
10932                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
10933                          i40e_stat_str(hw, ret),
10934                          i40e_aq_str(hw, hw->aq.asq_last_status));
10935                 return ret;
10936         }
10937         /* set receive Arbiter to RR mode and ETS scheme by default */
10938         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
10939                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
10940                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
10941                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
10942                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
10943                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
10944                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
10945                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
10946                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
10947                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
10948                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
10949                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
10950                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
10951         }
10952         /* get local mib to check whether it is configured correctly */
10953         /* IEEE mode */
10954         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
10955         /* Get Local DCB Config */
10956         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
10957                                      &hw->local_dcbx_config);
10958
10959         /* if Veb is created, need to update TC of it at first */
10960         if (main_vsi->veb) {
10961                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
10962                 if (ret)
10963                         PMD_INIT_LOG(WARNING,
10964                                  "Failed configuring TC for VEB seid=%d",
10965                                  main_vsi->veb->seid);
10966         }
10967         /* Update each VSI */
10968         i40e_vsi_config_tc(main_vsi, tc_map);
10969         if (main_vsi->veb) {
10970                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
10971                         /* Beside main VSI and VMDQ VSIs, only enable default
10972                          * TC for other VSIs
10973                          */
10974                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
10975                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10976                                                          tc_map);
10977                         else
10978                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
10979                                                          I40E_DEFAULT_TCMAP);
10980                         if (ret)
10981                                 PMD_INIT_LOG(WARNING,
10982                                         "Failed configuring TC for VSI seid=%d",
10983                                         vsi_list->vsi->seid);
10984                         /* continue */
10985                 }
10986         }
10987         return I40E_SUCCESS;
10988 }
10989
10990 /*
10991  * i40e_dcb_init_configure - initial dcb config
10992  * @dev: device being configured
10993  * @sw_dcb: indicate whether dcb is sw configured or hw offload
10994  *
10995  * Returns 0 on success, negative value on failure
10996  */
10997 int
10998 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
10999 {
11000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11001         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11002         int i, ret = 0;
11003
11004         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11005                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11006                 return -ENOTSUP;
11007         }
11008
11009         /* DCB initialization:
11010          * Update DCB configuration from the Firmware and configure
11011          * LLDP MIB change event.
11012          */
11013         if (sw_dcb == TRUE) {
11014                 ret = i40e_init_dcb(hw);
11015                 /* If lldp agent is stopped, the return value from
11016                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11017                  * adminq status. Otherwise, it should return success.
11018                  */
11019                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11020                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11021                         memset(&hw->local_dcbx_config, 0,
11022                                 sizeof(struct i40e_dcbx_config));
11023                         /* set dcb default configuration */
11024                         hw->local_dcbx_config.etscfg.willing = 0;
11025                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11026                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11027                         hw->local_dcbx_config.etscfg.tsatable[0] =
11028                                                 I40E_IEEE_TSA_ETS;
11029                         /* all UPs mapping to TC0 */
11030                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11031                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11032                         hw->local_dcbx_config.etsrec =
11033                                 hw->local_dcbx_config.etscfg;
11034                         hw->local_dcbx_config.pfc.willing = 0;
11035                         hw->local_dcbx_config.pfc.pfccap =
11036                                                 I40E_MAX_TRAFFIC_CLASS;
11037                         /* FW needs one App to configure HW */
11038                         hw->local_dcbx_config.numapps = 1;
11039                         hw->local_dcbx_config.app[0].selector =
11040                                                 I40E_APP_SEL_ETHTYPE;
11041                         hw->local_dcbx_config.app[0].priority = 3;
11042                         hw->local_dcbx_config.app[0].protocolid =
11043                                                 I40E_APP_PROTOID_FCOE;
11044                         ret = i40e_set_dcb_config(hw);
11045                         if (ret) {
11046                                 PMD_INIT_LOG(ERR,
11047                                         "default dcb config fails. err = %d, aq_err = %d.",
11048                                         ret, hw->aq.asq_last_status);
11049                                 return -ENOSYS;
11050                         }
11051                 } else {
11052                         PMD_INIT_LOG(ERR,
11053                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11054                                 ret, hw->aq.asq_last_status);
11055                         return -ENOTSUP;
11056                 }
11057         } else {
11058                 ret = i40e_aq_start_lldp(hw, NULL);
11059                 if (ret != I40E_SUCCESS)
11060                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11061
11062                 ret = i40e_init_dcb(hw);
11063                 if (!ret) {
11064                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11065                                 PMD_INIT_LOG(ERR,
11066                                         "HW doesn't support DCBX offload.");
11067                                 return -ENOTSUP;
11068                         }
11069                 } else {
11070                         PMD_INIT_LOG(ERR,
11071                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11072                                 ret, hw->aq.asq_last_status);
11073                         return -ENOTSUP;
11074                 }
11075         }
11076         return 0;
11077 }
11078
11079 /*
11080  * i40e_dcb_setup - setup dcb related config
11081  * @dev: device being configured
11082  *
11083  * Returns 0 on success, negative value on failure
11084  */
11085 static int
11086 i40e_dcb_setup(struct rte_eth_dev *dev)
11087 {
11088         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11089         struct i40e_dcbx_config dcb_cfg;
11090         uint8_t tc_map = 0;
11091         int ret = 0;
11092
11093         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11094                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11095                 return -ENOTSUP;
11096         }
11097
11098         if (pf->vf_num != 0)
11099                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11100
11101         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11102         if (ret) {
11103                 PMD_INIT_LOG(ERR, "invalid dcb config");
11104                 return -EINVAL;
11105         }
11106         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11107         if (ret) {
11108                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11109                 return -ENOSYS;
11110         }
11111
11112         return 0;
11113 }
11114
11115 static int
11116 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11117                       struct rte_eth_dcb_info *dcb_info)
11118 {
11119         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11120         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11121         struct i40e_vsi *vsi = pf->main_vsi;
11122         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11123         uint16_t bsf, tc_mapping;
11124         int i, j = 0;
11125
11126         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11127                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11128         else
11129                 dcb_info->nb_tcs = 1;
11130         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11131                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11132         for (i = 0; i < dcb_info->nb_tcs; i++)
11133                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11134
11135         /* get queue mapping if vmdq is disabled */
11136         if (!pf->nb_cfg_vmdq_vsi) {
11137                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11138                         if (!(vsi->enabled_tc & (1 << i)))
11139                                 continue;
11140                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11141                         dcb_info->tc_queue.tc_rxq[j][i].base =
11142                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11143                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11144                         dcb_info->tc_queue.tc_txq[j][i].base =
11145                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11146                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11147                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11148                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11149                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11150                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11151                 }
11152                 return 0;
11153         }
11154
11155         /* get queue mapping if vmdq is enabled */
11156         do {
11157                 vsi = pf->vmdq[j].vsi;
11158                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11159                         if (!(vsi->enabled_tc & (1 << i)))
11160                                 continue;
11161                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11162                         dcb_info->tc_queue.tc_rxq[j][i].base =
11163                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11164                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11165                         dcb_info->tc_queue.tc_txq[j][i].base =
11166                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11167                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11168                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11169                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11170                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11171                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11172                 }
11173                 j++;
11174         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11175         return 0;
11176 }
11177
11178 static int
11179 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11180 {
11181         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11182         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11183         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11184         uint16_t msix_intr;
11185
11186         msix_intr = intr_handle->intr_vec[queue_id];
11187         if (msix_intr == I40E_MISC_VEC_ID)
11188                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11189                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11190                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11191                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11192         else
11193                 I40E_WRITE_REG(hw,
11194                                I40E_PFINT_DYN_CTLN(msix_intr -
11195                                                    I40E_RX_VEC_START),
11196                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11197                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11198                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11199
11200         I40E_WRITE_FLUSH(hw);
11201         rte_intr_enable(&pci_dev->intr_handle);
11202
11203         return 0;
11204 }
11205
11206 static int
11207 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11208 {
11209         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11210         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11211         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11212         uint16_t msix_intr;
11213
11214         msix_intr = intr_handle->intr_vec[queue_id];
11215         if (msix_intr == I40E_MISC_VEC_ID)
11216                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11217                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11218         else
11219                 I40E_WRITE_REG(hw,
11220                                I40E_PFINT_DYN_CTLN(msix_intr -
11221                                                    I40E_RX_VEC_START),
11222                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11223         I40E_WRITE_FLUSH(hw);
11224
11225         return 0;
11226 }
11227
11228 static int i40e_get_regs(struct rte_eth_dev *dev,
11229                          struct rte_dev_reg_info *regs)
11230 {
11231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11232         uint32_t *ptr_data = regs->data;
11233         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11234         const struct i40e_reg_info *reg_info;
11235
11236         if (ptr_data == NULL) {
11237                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11238                 regs->width = sizeof(uint32_t);
11239                 return 0;
11240         }
11241
11242         /* The first few registers have to be read using AQ operations */
11243         reg_idx = 0;
11244         while (i40e_regs_adminq[reg_idx].name) {
11245                 reg_info = &i40e_regs_adminq[reg_idx++];
11246                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11247                         for (arr_idx2 = 0;
11248                                         arr_idx2 <= reg_info->count2;
11249                                         arr_idx2++) {
11250                                 reg_offset = arr_idx * reg_info->stride1 +
11251                                         arr_idx2 * reg_info->stride2;
11252                                 reg_offset += reg_info->base_addr;
11253                                 ptr_data[reg_offset >> 2] =
11254                                         i40e_read_rx_ctl(hw, reg_offset);
11255                         }
11256         }
11257
11258         /* The remaining registers can be read using primitives */
11259         reg_idx = 0;
11260         while (i40e_regs_others[reg_idx].name) {
11261                 reg_info = &i40e_regs_others[reg_idx++];
11262                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11263                         for (arr_idx2 = 0;
11264                                         arr_idx2 <= reg_info->count2;
11265                                         arr_idx2++) {
11266                                 reg_offset = arr_idx * reg_info->stride1 +
11267                                         arr_idx2 * reg_info->stride2;
11268                                 reg_offset += reg_info->base_addr;
11269                                 ptr_data[reg_offset >> 2] =
11270                                         I40E_READ_REG(hw, reg_offset);
11271                         }
11272         }
11273
11274         return 0;
11275 }
11276
11277 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11278 {
11279         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11280
11281         /* Convert word count to byte count */
11282         return hw->nvm.sr_size << 1;
11283 }
11284
11285 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11286                            struct rte_dev_eeprom_info *eeprom)
11287 {
11288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11289         uint16_t *data = eeprom->data;
11290         uint16_t offset, length, cnt_words;
11291         int ret_code;
11292
11293         offset = eeprom->offset >> 1;
11294         length = eeprom->length >> 1;
11295         cnt_words = length;
11296
11297         if (offset > hw->nvm.sr_size ||
11298                 offset + length > hw->nvm.sr_size) {
11299                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11300                 return -EINVAL;
11301         }
11302
11303         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11304
11305         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11306         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11307                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11308                 return -EIO;
11309         }
11310
11311         return 0;
11312 }
11313
11314 static void i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11315                                       struct ether_addr *mac_addr)
11316 {
11317         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11318         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11319         struct i40e_vsi *vsi = pf->main_vsi;
11320         struct i40e_mac_filter_info mac_filter;
11321         struct i40e_mac_filter *f;
11322         int ret;
11323
11324         if (!is_valid_assigned_ether_addr(mac_addr)) {
11325                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11326                 return;
11327         }
11328
11329         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11330                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
11331                         break;
11332         }
11333
11334         if (f == NULL) {
11335                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11336                 return;
11337         }
11338
11339         mac_filter = f->mac_info;
11340         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11341         if (ret != I40E_SUCCESS) {
11342                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11343                 return;
11344         }
11345         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11346         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11347         if (ret != I40E_SUCCESS) {
11348                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11349                 return;
11350         }
11351         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11352
11353         i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11354                                   mac_addr->addr_bytes, NULL);
11355 }
11356
11357 static int
11358 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11359 {
11360         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11361         struct rte_eth_dev_data *dev_data = pf->dev_data;
11362         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
11363         int ret = 0;
11364
11365         /* check if mtu is within the allowed range */
11366         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
11367                 return -EINVAL;
11368
11369         /* mtu setting is forbidden if port is start */
11370         if (dev_data->dev_started) {
11371                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
11372                             dev_data->port_id);
11373                 return -EBUSY;
11374         }
11375
11376         if (frame_size > ETHER_MAX_LEN)
11377                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
11378         else
11379                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
11380
11381         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
11382
11383         return ret;
11384 }
11385
11386 /* Restore ethertype filter */
11387 static void
11388 i40e_ethertype_filter_restore(struct i40e_pf *pf)
11389 {
11390         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11391         struct i40e_ethertype_filter_list
11392                 *ethertype_list = &pf->ethertype.ethertype_list;
11393         struct i40e_ethertype_filter *f;
11394         struct i40e_control_filter_stats stats;
11395         uint16_t flags;
11396
11397         TAILQ_FOREACH(f, ethertype_list, rules) {
11398                 flags = 0;
11399                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
11400                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
11401                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
11402                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
11403                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
11404
11405                 memset(&stats, 0, sizeof(stats));
11406                 i40e_aq_add_rem_control_packet_filter(hw,
11407                                             f->input.mac_addr.addr_bytes,
11408                                             f->input.ether_type,
11409                                             flags, pf->main_vsi->seid,
11410                                             f->queue, 1, &stats, NULL);
11411         }
11412         PMD_DRV_LOG(INFO, "Ethertype filter:"
11413                     " mac_etype_used = %u, etype_used = %u,"
11414                     " mac_etype_free = %u, etype_free = %u",
11415                     stats.mac_etype_used, stats.etype_used,
11416                     stats.mac_etype_free, stats.etype_free);
11417 }
11418
11419 /* Restore tunnel filter */
11420 static void
11421 i40e_tunnel_filter_restore(struct i40e_pf *pf)
11422 {
11423         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11424         struct i40e_vsi *vsi;
11425         struct i40e_pf_vf *vf;
11426         struct i40e_tunnel_filter_list
11427                 *tunnel_list = &pf->tunnel.tunnel_list;
11428         struct i40e_tunnel_filter *f;
11429         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
11430         bool big_buffer = 0;
11431
11432         TAILQ_FOREACH(f, tunnel_list, rules) {
11433                 if (!f->is_to_vf)
11434                         vsi = pf->main_vsi;
11435                 else {
11436                         vf = &pf->vfs[f->vf_id];
11437                         vsi = vf->vsi;
11438                 }
11439                 memset(&cld_filter, 0, sizeof(cld_filter));
11440                 ether_addr_copy((struct ether_addr *)&f->input.outer_mac,
11441                         (struct ether_addr *)&cld_filter.element.outer_mac);
11442                 ether_addr_copy((struct ether_addr *)&f->input.inner_mac,
11443                         (struct ether_addr *)&cld_filter.element.inner_mac);
11444                 cld_filter.element.inner_vlan = f->input.inner_vlan;
11445                 cld_filter.element.flags = f->input.flags;
11446                 cld_filter.element.tenant_id = f->input.tenant_id;
11447                 cld_filter.element.queue_number = f->queue;
11448                 rte_memcpy(cld_filter.general_fields,
11449                            f->input.general_fields,
11450                            sizeof(f->input.general_fields));
11451
11452                 if (((f->input.flags &
11453                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
11454                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
11455                     ((f->input.flags &
11456                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
11457                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
11458                     ((f->input.flags &
11459                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
11460                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
11461                         big_buffer = 1;
11462
11463                 if (big_buffer)
11464                         i40e_aq_add_cloud_filters_big_buffer(hw,
11465                                              vsi->seid, &cld_filter, 1);
11466                 else
11467                         i40e_aq_add_cloud_filters(hw, vsi->seid,
11468                                                   &cld_filter.element, 1);
11469         }
11470 }
11471
11472 /* Restore rss filter */
11473 static inline void
11474 i40e_rss_filter_restore(struct i40e_pf *pf)
11475 {
11476         struct i40e_rte_flow_rss_conf *conf =
11477                                         &pf->rss_info;
11478         if (conf->num)
11479                 i40e_config_rss_filter(pf, conf, TRUE);
11480 }
11481
11482 static void
11483 i40e_filter_restore(struct i40e_pf *pf)
11484 {
11485         i40e_ethertype_filter_restore(pf);
11486         i40e_tunnel_filter_restore(pf);
11487         i40e_fdir_filter_restore(pf);
11488         i40e_rss_filter_restore(pf);
11489 }
11490
11491 static bool
11492 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
11493 {
11494         if (strcmp(dev->device->driver->name, drv->driver.name))
11495                 return false;
11496
11497         return true;
11498 }
11499
11500 bool
11501 is_i40e_supported(struct rte_eth_dev *dev)
11502 {
11503         return is_device_supported(dev, &rte_i40e_pmd);
11504 }
11505
11506 struct i40e_customized_pctype*
11507 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
11508 {
11509         int i;
11510
11511         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
11512                 if (pf->customized_pctype[i].index == index)
11513                         return &pf->customized_pctype[i];
11514         }
11515         return NULL;
11516 }
11517
11518 static int
11519 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
11520                               uint32_t pkg_size, uint32_t proto_num,
11521                               struct rte_pmd_i40e_proto_info *proto)
11522 {
11523         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11524         uint32_t pctype_num;
11525         struct rte_pmd_i40e_ptype_info *pctype;
11526         uint32_t buff_size;
11527         struct i40e_customized_pctype *new_pctype = NULL;
11528         uint8_t proto_id;
11529         uint8_t pctype_value;
11530         char name[64];
11531         uint32_t i, j, n;
11532         int ret;
11533
11534         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11535                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
11536                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
11537         if (ret) {
11538                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
11539                 return -1;
11540         }
11541         if (!pctype_num) {
11542                 PMD_DRV_LOG(INFO, "No new pctype added");
11543                 return -1;
11544         }
11545
11546         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
11547         pctype = rte_zmalloc("new_pctype", buff_size, 0);
11548         if (!pctype) {
11549                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11550                 return -1;
11551         }
11552         /* get information about new pctype list */
11553         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11554                                         (uint8_t *)pctype, buff_size,
11555                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
11556         if (ret) {
11557                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
11558                 rte_free(pctype);
11559                 return -1;
11560         }
11561
11562         /* Update customized pctype. */
11563         for (i = 0; i < pctype_num; i++) {
11564                 pctype_value = pctype[i].ptype_id;
11565                 memset(name, 0, sizeof(name));
11566                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11567                         proto_id = pctype[i].protocols[j];
11568                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11569                                 continue;
11570                         for (n = 0; n < proto_num; n++) {
11571                                 if (proto[n].proto_id != proto_id)
11572                                         continue;
11573                                 strcat(name, proto[n].name);
11574                                 strcat(name, "_");
11575                                 break;
11576                         }
11577                 }
11578                 name[strlen(name) - 1] = '\0';
11579                 if (!strcmp(name, "GTPC"))
11580                         new_pctype =
11581                                 i40e_find_customized_pctype(pf,
11582                                                       I40E_CUSTOMIZED_GTPC);
11583                 else if (!strcmp(name, "GTPU_IPV4"))
11584                         new_pctype =
11585                                 i40e_find_customized_pctype(pf,
11586                                                    I40E_CUSTOMIZED_GTPU_IPV4);
11587                 else if (!strcmp(name, "GTPU_IPV6"))
11588                         new_pctype =
11589                                 i40e_find_customized_pctype(pf,
11590                                                    I40E_CUSTOMIZED_GTPU_IPV6);
11591                 else if (!strcmp(name, "GTPU"))
11592                         new_pctype =
11593                                 i40e_find_customized_pctype(pf,
11594                                                       I40E_CUSTOMIZED_GTPU);
11595                 if (new_pctype) {
11596                         new_pctype->pctype = pctype_value;
11597                         new_pctype->valid = true;
11598                 }
11599         }
11600
11601         rte_free(pctype);
11602         return 0;
11603 }
11604
11605 static int
11606 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
11607                                uint32_t pkg_size, uint32_t proto_num,
11608                                struct rte_pmd_i40e_proto_info *proto)
11609 {
11610         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
11611         uint16_t port_id = dev->data->port_id;
11612         uint32_t ptype_num;
11613         struct rte_pmd_i40e_ptype_info *ptype;
11614         uint32_t buff_size;
11615         uint8_t proto_id;
11616         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
11617         uint32_t i, j, n;
11618         bool in_tunnel;
11619         int ret;
11620
11621         /* get information about new ptype num */
11622         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11623                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
11624                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
11625         if (ret) {
11626                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
11627                 return ret;
11628         }
11629         if (!ptype_num) {
11630                 PMD_DRV_LOG(INFO, "No new ptype added");
11631                 return -1;
11632         }
11633
11634         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
11635         ptype = rte_zmalloc("new_ptype", buff_size, 0);
11636         if (!ptype) {
11637                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11638                 return -1;
11639         }
11640
11641         /* get information about new ptype list */
11642         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11643                                         (uint8_t *)ptype, buff_size,
11644                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
11645         if (ret) {
11646                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
11647                 rte_free(ptype);
11648                 return ret;
11649         }
11650
11651         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
11652         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
11653         if (!ptype_mapping) {
11654                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11655                 rte_free(ptype);
11656                 return -1;
11657         }
11658
11659         /* Update ptype mapping table. */
11660         for (i = 0; i < ptype_num; i++) {
11661                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
11662                 ptype_mapping[i].sw_ptype = 0;
11663                 in_tunnel = false;
11664                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
11665                         proto_id = ptype[i].protocols[j];
11666                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
11667                                 continue;
11668                         for (n = 0; n < proto_num; n++) {
11669                                 if (proto[n].proto_id != proto_id)
11670                                         continue;
11671                                 memset(name, 0, sizeof(name));
11672                                 strcpy(name, proto[n].name);
11673                                 if (!strncasecmp(name, "PPPOE", 5))
11674                                         ptype_mapping[i].sw_ptype |=
11675                                                 RTE_PTYPE_L2_ETHER_PPPOE;
11676                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11677                                          !in_tunnel) {
11678                                         ptype_mapping[i].sw_ptype |=
11679                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11680                                         ptype_mapping[i].sw_ptype |=
11681                                                 RTE_PTYPE_L4_FRAG;
11682                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
11683                                            in_tunnel) {
11684                                         ptype_mapping[i].sw_ptype |=
11685                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11686                                         ptype_mapping[i].sw_ptype |=
11687                                                 RTE_PTYPE_INNER_L4_FRAG;
11688                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
11689                                         ptype_mapping[i].sw_ptype |=
11690                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11691                                         in_tunnel = true;
11692                                 } else if (!strncasecmp(name, "IPV4", 4) &&
11693                                            !in_tunnel)
11694                                         ptype_mapping[i].sw_ptype |=
11695                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
11696                                 else if (!strncasecmp(name, "IPV4", 4) &&
11697                                          in_tunnel)
11698                                         ptype_mapping[i].sw_ptype |=
11699                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
11700                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11701                                          !in_tunnel) {
11702                                         ptype_mapping[i].sw_ptype |=
11703                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11704                                         ptype_mapping[i].sw_ptype |=
11705                                                 RTE_PTYPE_L4_FRAG;
11706                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
11707                                            in_tunnel) {
11708                                         ptype_mapping[i].sw_ptype |=
11709                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11710                                         ptype_mapping[i].sw_ptype |=
11711                                                 RTE_PTYPE_INNER_L4_FRAG;
11712                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
11713                                         ptype_mapping[i].sw_ptype |=
11714                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11715                                         in_tunnel = true;
11716                                 } else if (!strncasecmp(name, "IPV6", 4) &&
11717                                            !in_tunnel)
11718                                         ptype_mapping[i].sw_ptype |=
11719                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
11720                                 else if (!strncasecmp(name, "IPV6", 4) &&
11721                                          in_tunnel)
11722                                         ptype_mapping[i].sw_ptype |=
11723                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
11724                                 else if (!strncasecmp(name, "UDP", 3) &&
11725                                          !in_tunnel)
11726                                         ptype_mapping[i].sw_ptype |=
11727                                                 RTE_PTYPE_L4_UDP;
11728                                 else if (!strncasecmp(name, "UDP", 3) &&
11729                                          in_tunnel)
11730                                         ptype_mapping[i].sw_ptype |=
11731                                                 RTE_PTYPE_INNER_L4_UDP;
11732                                 else if (!strncasecmp(name, "TCP", 3) &&
11733                                          !in_tunnel)
11734                                         ptype_mapping[i].sw_ptype |=
11735                                                 RTE_PTYPE_L4_TCP;
11736                                 else if (!strncasecmp(name, "TCP", 3) &&
11737                                          in_tunnel)
11738                                         ptype_mapping[i].sw_ptype |=
11739                                                 RTE_PTYPE_INNER_L4_TCP;
11740                                 else if (!strncasecmp(name, "SCTP", 4) &&
11741                                          !in_tunnel)
11742                                         ptype_mapping[i].sw_ptype |=
11743                                                 RTE_PTYPE_L4_SCTP;
11744                                 else if (!strncasecmp(name, "SCTP", 4) &&
11745                                          in_tunnel)
11746                                         ptype_mapping[i].sw_ptype |=
11747                                                 RTE_PTYPE_INNER_L4_SCTP;
11748                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11749                                           !strncasecmp(name, "ICMPV6", 6)) &&
11750                                          !in_tunnel)
11751                                         ptype_mapping[i].sw_ptype |=
11752                                                 RTE_PTYPE_L4_ICMP;
11753                                 else if ((!strncasecmp(name, "ICMP", 4) ||
11754                                           !strncasecmp(name, "ICMPV6", 6)) &&
11755                                          in_tunnel)
11756                                         ptype_mapping[i].sw_ptype |=
11757                                                 RTE_PTYPE_INNER_L4_ICMP;
11758                                 else if (!strncasecmp(name, "GTPC", 4)) {
11759                                         ptype_mapping[i].sw_ptype |=
11760                                                 RTE_PTYPE_TUNNEL_GTPC;
11761                                         in_tunnel = true;
11762                                 } else if (!strncasecmp(name, "GTPU", 4)) {
11763                                         ptype_mapping[i].sw_ptype |=
11764                                                 RTE_PTYPE_TUNNEL_GTPU;
11765                                         in_tunnel = true;
11766                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
11767                                         ptype_mapping[i].sw_ptype |=
11768                                                 RTE_PTYPE_TUNNEL_GRENAT;
11769                                         in_tunnel = true;
11770                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9)) {
11771                                         ptype_mapping[i].sw_ptype |=
11772                                                 RTE_PTYPE_TUNNEL_L2TP;
11773                                         in_tunnel = true;
11774                                 }
11775
11776                                 break;
11777                         }
11778                 }
11779         }
11780
11781         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
11782                                                 ptype_num, 0);
11783         if (ret)
11784                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
11785
11786         rte_free(ptype_mapping);
11787         rte_free(ptype);
11788         return ret;
11789 }
11790
11791 void
11792 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
11793                               uint32_t pkg_size)
11794 {
11795         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11796         uint32_t proto_num;
11797         struct rte_pmd_i40e_proto_info *proto;
11798         uint32_t buff_size;
11799         uint32_t i;
11800         int ret;
11801
11802         /* get information about protocol number */
11803         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11804                                        (uint8_t *)&proto_num, sizeof(proto_num),
11805                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
11806         if (ret) {
11807                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
11808                 return;
11809         }
11810         if (!proto_num) {
11811                 PMD_DRV_LOG(INFO, "No new protocol added");
11812                 return;
11813         }
11814
11815         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
11816         proto = rte_zmalloc("new_proto", buff_size, 0);
11817         if (!proto) {
11818                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
11819                 return;
11820         }
11821
11822         /* get information about protocol list */
11823         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
11824                                         (uint8_t *)proto, buff_size,
11825                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
11826         if (ret) {
11827                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
11828                 rte_free(proto);
11829                 return;
11830         }
11831
11832         /* Check if GTP is supported. */
11833         for (i = 0; i < proto_num; i++) {
11834                 if (!strncmp(proto[i].name, "GTP", 3)) {
11835                         pf->gtp_support = true;
11836                         break;
11837                 }
11838         }
11839
11840         /* Update customized pctype info */
11841         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
11842                                             proto_num, proto);
11843         if (ret)
11844                 PMD_DRV_LOG(INFO, "No pctype is updated.");
11845
11846         /* Update customized ptype info */
11847         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
11848                                            proto_num, proto);
11849         if (ret)
11850                 PMD_DRV_LOG(INFO, "No ptype is updated.");
11851
11852         rte_free(proto);
11853 }
11854
11855 /* Create a QinQ cloud filter
11856  *
11857  * The Fortville NIC has limited resources for tunnel filters,
11858  * so we can only reuse existing filters.
11859  *
11860  * In step 1 we define which Field Vector fields can be used for
11861  * filter types.
11862  * As we do not have the inner tag defined as a field,
11863  * we have to define it first, by reusing one of L1 entries.
11864  *
11865  * In step 2 we are replacing one of existing filter types with
11866  * a new one for QinQ.
11867  * As we reusing L1 and replacing L2, some of the default filter
11868  * types will disappear,which depends on L1 and L2 entries we reuse.
11869  *
11870  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
11871  *
11872  * 1.   Create L1 filter of outer vlan (12b) which will be in use
11873  *              later when we define the cloud filter.
11874  *      a.      Valid_flags.replace_cloud = 0
11875  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
11876  *      c.      New_filter = 0x10
11877  *      d.      TR bit = 0xff (optional, not used here)
11878  *      e.      Buffer – 2 entries:
11879  *              i.      Byte 0 = 8 (outer vlan FV index).
11880  *                      Byte 1 = 0 (rsv)
11881  *                      Byte 2-3 = 0x0fff
11882  *              ii.     Byte 0 = 37 (inner vlan FV index).
11883  *                      Byte 1 =0 (rsv)
11884  *                      Byte 2-3 = 0x0fff
11885  *
11886  * Step 2:
11887  * 2.   Create cloud filter using two L1 filters entries: stag and
11888  *              new filter(outer vlan+ inner vlan)
11889  *      a.      Valid_flags.replace_cloud = 1
11890  *      b.      Old_filter = 1 (instead of outer IP)
11891  *      c.      New_filter = 0x10
11892  *      d.      Buffer – 2 entries:
11893  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
11894  *                      Byte 1-3 = 0 (rsv)
11895  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
11896  *                      Byte 9-11 = 0 (rsv)
11897  */
11898 static int
11899 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
11900 {
11901         int ret = -ENOTSUP;
11902         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
11903         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
11904         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11905
11906         if (pf->support_multi_driver) {
11907                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
11908                 return ret;
11909         }
11910
11911         /* Init */
11912         memset(&filter_replace, 0,
11913                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11914         memset(&filter_replace_buf, 0,
11915                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11916
11917         /* create L1 filter */
11918         filter_replace.old_filter_type =
11919                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
11920         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11921         filter_replace.tr_bit = 0;
11922
11923         /* Prepare the buffer, 2 entries */
11924         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
11925         filter_replace_buf.data[0] |=
11926                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11927         /* Field Vector 12b mask */
11928         filter_replace_buf.data[2] = 0xff;
11929         filter_replace_buf.data[3] = 0x0f;
11930         filter_replace_buf.data[4] =
11931                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
11932         filter_replace_buf.data[4] |=
11933                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11934         /* Field Vector 12b mask */
11935         filter_replace_buf.data[6] = 0xff;
11936         filter_replace_buf.data[7] = 0x0f;
11937         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11938                         &filter_replace_buf);
11939         if (ret != I40E_SUCCESS)
11940                 return ret;
11941         PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11942                     "cloud l1 type is changed from 0x%x to 0x%x",
11943                     filter_replace.old_filter_type,
11944                     filter_replace.new_filter_type);
11945
11946         /* Apply the second L2 cloud filter */
11947         memset(&filter_replace, 0,
11948                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
11949         memset(&filter_replace_buf, 0,
11950                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
11951
11952         /* create L2 filter, input for L2 filter will be L1 filter  */
11953         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
11954         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
11955         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11956
11957         /* Prepare the buffer, 2 entries */
11958         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
11959         filter_replace_buf.data[0] |=
11960                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11961         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
11962         filter_replace_buf.data[4] |=
11963                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
11964         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
11965                         &filter_replace_buf);
11966         if (!ret) {
11967                 i40e_global_cfg_warning(I40E_WARNING_RPL_CLD_FILTER);
11968                 PMD_DRV_LOG(DEBUG, "Global configuration modification: "
11969                             "cloud filter type is changed from 0x%x to 0x%x",
11970                             filter_replace.old_filter_type,
11971                             filter_replace.new_filter_type);
11972         }
11973         return ret;
11974 }
11975
11976 int
11977 i40e_config_rss_filter(struct i40e_pf *pf,
11978                 struct i40e_rte_flow_rss_conf *conf, bool add)
11979 {
11980         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11981         uint32_t i, lut = 0;
11982         uint16_t j, num;
11983         struct rte_eth_rss_conf rss_conf = conf->rss_conf;
11984         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
11985
11986         if (!add) {
11987                 if (memcmp(conf, rss_info,
11988                         sizeof(struct i40e_rte_flow_rss_conf)) == 0) {
11989                         i40e_pf_disable_rss(pf);
11990                         memset(rss_info, 0,
11991                                 sizeof(struct i40e_rte_flow_rss_conf));
11992                         return 0;
11993                 }
11994                 return -EINVAL;
11995         }
11996
11997         if (rss_info->num)
11998                 return -EINVAL;
11999
12000         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12001          * It's necessary to calculate the actual PF queues that are configured.
12002          */
12003         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12004                 num = i40e_pf_calc_configured_queues_num(pf);
12005         else
12006                 num = pf->dev_data->nb_rx_queues;
12007
12008         num = RTE_MIN(num, conf->num);
12009         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12010                         num);
12011
12012         if (num == 0) {
12013                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12014                 return -ENOTSUP;
12015         }
12016
12017         /* Fill in redirection table */
12018         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12019                 if (j == num)
12020                         j = 0;
12021                 lut = (lut << 8) | (conf->queue[j] & ((0x1 <<
12022                         hw->func_caps.rss_table_entry_width) - 1));
12023                 if ((i & 3) == 3)
12024                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12025         }
12026
12027         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12028                 i40e_pf_disable_rss(pf);
12029                 return 0;
12030         }
12031         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12032                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12033                 /* Random default keys */
12034                 static uint32_t rss_key_default[] = {0x6b793944,
12035                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12036                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12037                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12038
12039                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12040                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12041                                                         sizeof(uint32_t);
12042         }
12043
12044         i40e_hw_rss_hash_set(pf, &rss_conf);
12045
12046         rte_memcpy(rss_info,
12047                 conf, sizeof(struct i40e_rte_flow_rss_conf));
12048
12049         return 0;
12050 }
12051
12052 RTE_INIT(i40e_init_log);
12053 static void
12054 i40e_init_log(void)
12055 {
12056         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12057         if (i40e_logtype_init >= 0)
12058                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12059         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12060         if (i40e_logtype_driver >= 0)
12061                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12062 }
12063
12064 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12065                               QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12066                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1");