drivers/net/i40e/i40e_ethdev.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50 #include <rte_alarm.h>
  51 #include <rte_dev.h>
  52 #include <rte_eth_ctrl.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_adminq_cmd.h"
  57 #include "base/i40e_type.h"
  58 #include "base/i40e_register.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61 #include "i40e_pf.h"
  62
  63 /* Maximun number of MAC addresses */
  64 #define I40E_NUM_MACADDR_MAX       64
  65 #define I40E_CLEAR_PXE_WAIT_MS     200
  66
  67 /* Maximun number of capability elements */
  68 #define I40E_MAX_CAP_ELE_NUM       128
  69
  70 /* Wait count and inteval */
  71 #define I40E_CHK_Q_ENA_COUNT       1000
  72 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  73
  74 /* Maximun number of VSI */
  75 #define I40E_MAX_NUM_VSIS          (384UL)
  76
  77 /* Default queue interrupt throttling time in microseconds */
  78 #define I40E_ITR_INDEX_DEFAULT          0
  79 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
  80 #define I40E_QUEUE_ITR_INTERVAL_MAX     8160 /* 8160 us */
  81
  82 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  83
  84 /* Flow control default timer */
  85 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  86
  87 /* Flow control default high water */
  88 #define I40E_DEFAULT_HIGH_WATER (0x1C40/1024)
  89
  90 /* Flow control default low water */
  91 #define I40E_DEFAULT_LOW_WATER  (0x1A40/1024)
  92
  93 /* Flow control enable fwd bit */
  94 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  95
  96 /* Receive Packet Buffer size */
  97 #define I40E_RXPBSIZE (968 * 1024)
  98
  99 /* Kilobytes shift */
 100 #define I40E_KILOSHIFT 10
 101
 102 /* Receive Average Packet Size in Byte*/
 103 #define I40E_PACKET_AVERAGE_SIZE 128
 104
 105 /* Mask of PF interrupt causes */
 106 #define I40E_PFINT_ICR0_ENA_MASK ( \
 107                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
 108                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
 109                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
 110                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
 111                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
 112                 I40E_PFINT_ICR0_ENA_LINK_STAT_CHANGE_MASK | \
 113                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
 114                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
 115                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
 116                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
 117
 118 #define I40E_FLOW_TYPES ( \
 119         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
 120         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 121         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 122         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 123         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 124         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 125         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 126         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 127         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 128         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 129         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 130
 131 #define I40E_PTP_40GB_INCVAL  0x0199999999ULL
 132 #define I40E_PTP_10GB_INCVAL  0x0333333333ULL
 133 #define I40E_PTP_1GB_INCVAL   0x2000000000ULL
 134 #define I40E_PRTTSYN_TSYNENA  0x80000000
 135 #define I40E_PRTTSYN_TSYNTYPE 0x0e000000
 136
 137 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev);
 138 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 139 static int i40e_dev_configure(struct rte_eth_dev *dev);
 140 static int i40e_dev_start(struct rte_eth_dev *dev);
 141 static void i40e_dev_stop(struct rte_eth_dev *dev);
 142 static void i40e_dev_close(struct rte_eth_dev *dev);
 143 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 144 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 145 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 146 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 147 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 148 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 149 static void i40e_dev_stats_get(struct rte_eth_dev *dev,
 150                                struct rte_eth_stats *stats);
 151 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 152 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 153                                             uint16_t queue_id,
 154                                             uint8_t stat_idx,
 155                                             uint8_t is_rx);
 156 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 157                               struct rte_eth_dev_info *dev_info);
 158 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 159                                 uint16_t vlan_id,
 160                                 int on);
 161 static void i40e_vlan_tpid_set(struct rte_eth_dev *dev, uint16_t tpid);
 162 static void i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 163 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 164                                       uint16_t queue,
 165                                       int on);
 166 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 167 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 168 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 169 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 170                               struct rte_eth_fc_conf *fc_conf);
 171 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 172                               struct rte_eth_fc_conf *fc_conf);
 173 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 174                                        struct rte_eth_pfc_conf *pfc_conf);
 175 static void i40e_macaddr_add(struct rte_eth_dev *dev,
 176                           struct ether_addr *mac_addr,
 177                           uint32_t index,
 178                           uint32_t pool);
 179 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 180 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 181                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 182                                     uint16_t reta_size);
 183 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 184                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 185                                    uint16_t reta_size);
 186
 187 static int i40e_get_cap(struct i40e_hw *hw);
 188 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 189 static int i40e_pf_setup(struct i40e_pf *pf);
 190 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 191 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 192 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 193                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 194 static void i40e_stat_update_48(struct i40e_hw *hw,
 195                                uint32_t hireg,
 196                                uint32_t loreg,
 197                                bool offset_loaded,
 198                                uint64_t *offset,
 199                                uint64_t *stat);
 200 static void i40e_pf_config_irq0(struct i40e_hw *hw);
 201 static void i40e_dev_interrupt_handler(
 202                 __rte_unused struct rte_intr_handle *handle, void *param);
 203 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 204                                 uint32_t base, uint32_t num);
 205 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 206 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 207                         uint32_t base);
 208 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 209                         uint16_t num);
 210 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 211 static int i40e_veb_release(struct i40e_veb *veb);
 212 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 213                                                 struct i40e_vsi *vsi);
 214 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 215 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 216 static inline int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
 217                                              struct i40e_macvlan_filter *mv_f,
 218                                              int num,
 219                                              struct ether_addr *addr);
 220 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 221                                              struct i40e_macvlan_filter *mv_f,
 222                                              int num,
 223                                              uint16_t vlan);
 224 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 225 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 226                                     struct rte_eth_rss_conf *rss_conf);
 227 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 228                                       struct rte_eth_rss_conf *rss_conf);
 229 static int i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
 230                                 struct rte_eth_udp_tunnel *udp_tunnel);
 231 static int i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
 232                                 struct rte_eth_udp_tunnel *udp_tunnel);
 233 static int i40e_ethertype_filter_set(struct i40e_pf *pf,
 234                         struct rte_eth_ethertype_filter *filter,
 235                         bool add);
 236 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 237                                 enum rte_filter_op filter_op,
 238                                 void *arg);
 239 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 240                                 enum rte_filter_type filter_type,
 241                                 enum rte_filter_op filter_op,
 242                                 void *arg);
 243 static void i40e_configure_registers(struct i40e_hw *hw);
 244 static void i40e_hw_init(struct i40e_hw *hw);
 245 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 246 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 247                         struct rte_eth_mirror_conf *mirror_conf,
 248                         uint8_t sw_id, uint8_t on);
 249 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 250
 251 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 252 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 253 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 254                                            struct timespec *timestamp,
 255                                            uint32_t flags);
 256 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 257                                            struct timespec *timestamp);
 258
 259 static const struct rte_pci_id pci_id_i40e_map[] = {
 260 #define RTE_PCI_DEV_ID_DECL_I40E(vend, dev) {RTE_PCI_DEVICE(vend, dev)},
 261 #include "rte_pci_dev_ids.h"
 262 { .vendor_id = 0, /* sentinel */ },
 263 };
 264
 265 static const struct eth_dev_ops i40e_eth_dev_ops = {
 266         .dev_configure                = i40e_dev_configure,
 267         .dev_start                    = i40e_dev_start,
 268         .dev_stop                     = i40e_dev_stop,
 269         .dev_close                    = i40e_dev_close,
 270         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 271         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 272         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 273         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 274         .dev_set_link_up              = i40e_dev_set_link_up,
 275         .dev_set_link_down            = i40e_dev_set_link_down,
 276         .link_update                  = i40e_dev_link_update,
 277         .stats_get                    = i40e_dev_stats_get,
 278         .stats_reset                  = i40e_dev_stats_reset,
 279         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 280         .dev_infos_get                = i40e_dev_info_get,
 281         .vlan_filter_set              = i40e_vlan_filter_set,
 282         .vlan_tpid_set                = i40e_vlan_tpid_set,
 283         .vlan_offload_set             = i40e_vlan_offload_set,
 284         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 285         .vlan_pvid_set                = i40e_vlan_pvid_set,
 286         .rx_queue_start               = i40e_dev_rx_queue_start,
 287         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 288         .tx_queue_start               = i40e_dev_tx_queue_start,
 289         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 290         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 291         .rx_queue_release             = i40e_dev_rx_queue_release,
 292         .rx_queue_count               = i40e_dev_rx_queue_count,
 293         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 294         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 295         .tx_queue_release             = i40e_dev_tx_queue_release,
 296         .dev_led_on                   = i40e_dev_led_on,
 297         .dev_led_off                  = i40e_dev_led_off,
 298         .flow_ctrl_get                = i40e_flow_ctrl_get,
 299         .flow_ctrl_set                = i40e_flow_ctrl_set,
 300         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 301         .mac_addr_add                 = i40e_macaddr_add,
 302         .mac_addr_remove              = i40e_macaddr_remove,
 303         .reta_update                  = i40e_dev_rss_reta_update,
 304         .reta_query                   = i40e_dev_rss_reta_query,
 305         .rss_hash_update              = i40e_dev_rss_hash_update,
 306         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 307         .udp_tunnel_add               = i40e_dev_udp_tunnel_add,
 308         .udp_tunnel_del               = i40e_dev_udp_tunnel_del,
 309         .filter_ctrl                  = i40e_dev_filter_ctrl,
 310         .mirror_rule_set              = i40e_mirror_rule_set,
 311         .mirror_rule_reset            = i40e_mirror_rule_reset,
 312         .timesync_enable              = i40e_timesync_enable,
 313         .timesync_disable             = i40e_timesync_disable,
 314         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 315         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 316 };
 317
 318 static struct eth_driver rte_i40e_pmd = {
 319         .pci_drv = {
 320                 .name = "rte_i40e_pmd",
 321                 .id_table = pci_id_i40e_map,
 322                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 323                         RTE_PCI_DRV_DETACHABLE,
 324         },
 325         .eth_dev_init = eth_i40e_dev_init,
 326         .eth_dev_uninit = eth_i40e_dev_uninit,
 327         .dev_private_size = sizeof(struct i40e_adapter),
 328 };
 329
 330 static inline int
 331 rte_i40e_dev_atomic_read_link_status(struct rte_eth_dev *dev,
 332                                      struct rte_eth_link *link)
 333 {
 334         struct rte_eth_link *dst = link;
 335         struct rte_eth_link *src = &(dev->data->dev_link);
 336
 337         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 338                                         *(uint64_t *)src) == 0)
 339                 return -1;
 340
 341         return 0;
 342 }
 343
 344 static inline int
 345 rte_i40e_dev_atomic_write_link_status(struct rte_eth_dev *dev,
 346                                       struct rte_eth_link *link)
 347 {
 348         struct rte_eth_link *dst = &(dev->data->dev_link);
 349         struct rte_eth_link *src = link;
 350
 351         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
 352                                         *(uint64_t *)src) == 0)
 353                 return -1;
 354
 355         return 0;
 356 }
 357
 358 /*
 359  * Driver initialization routine.
 360  * Invoked once at EAL init time.
 361  * Register itself as the [Poll Mode] Driver of PCI IXGBE devices.
 362  */
 363 static int
 364 rte_i40e_pmd_init(const char *name __rte_unused,
 365                   const char *params __rte_unused)
 366 {
 367         PMD_INIT_FUNC_TRACE();
 368         rte_eth_driver_register(&rte_i40e_pmd);
 369
 370         return 0;
 371 }
 372
 373 static struct rte_driver rte_i40e_driver = {
 374         .type = PMD_PDEV,
 375         .init = rte_i40e_pmd_init,
 376 };
 377
 378 PMD_REGISTER_DRIVER(rte_i40e_driver);
 379
 380 /*
 381  * Initialize registers for flexible payload, which should be set by NVM.
 382  * This should be removed from code once it is fixed in NVM.
 383  */
 384 #ifndef I40E_GLQF_ORT
 385 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 386 #endif
 387 #ifndef I40E_GLQF_PIT
 388 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 389 #endif
 390
 391 static inline void i40e_flex_payload_reg_init(struct i40e_hw *hw)
 392 {
 393         I40E_WRITE_REG(hw, I40E_GLQF_ORT(18), 0x00000030);
 394         I40E_WRITE_REG(hw, I40E_GLQF_ORT(19), 0x00000030);
 395         I40E_WRITE_REG(hw, I40E_GLQF_ORT(26), 0x0000002B);
 396         I40E_WRITE_REG(hw, I40E_GLQF_ORT(30), 0x0000002B);
 397         I40E_WRITE_REG(hw, I40E_GLQF_ORT(33), 0x000000E0);
 398         I40E_WRITE_REG(hw, I40E_GLQF_ORT(34), 0x000000E3);
 399         I40E_WRITE_REG(hw, I40E_GLQF_ORT(35), 0x000000E6);
 400         I40E_WRITE_REG(hw, I40E_GLQF_ORT(20), 0x00000031);
 401         I40E_WRITE_REG(hw, I40E_GLQF_ORT(23), 0x00000031);
 402         I40E_WRITE_REG(hw, I40E_GLQF_ORT(63), 0x0000002D);
 403
 404         /* GLQF_PIT Registers */
 405         I40E_WRITE_REG(hw, I40E_GLQF_PIT(16), 0x00007480);
 406         I40E_WRITE_REG(hw, I40E_GLQF_PIT(17), 0x00007440);
 407 }
 408
 409 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 410
 411 /*
 412  * Add a ethertype filter to drop all flow control frames transmitted
 413  * from VSIs.
 414 */
 415 static void
 416 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 417 {
 418         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 419         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 420                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 421                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 422         int ret;
 423
 424         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 425                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 426                                 pf->main_vsi_seid, 0,
 427                                 TRUE, NULL, NULL);
 428         if (ret)
 429                 PMD_INIT_LOG(ERR, "Failed to add filter to drop flow control "
 430                                   " frames from VSIs.");
 431 }
 432
 433 static int
 434 eth_i40e_dev_init(struct rte_eth_dev *dev)
 435 {
 436         struct rte_pci_device *pci_dev;
 437         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 438         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 439         struct i40e_vsi *vsi;
 440         int ret;
 441         uint32_t len;
 442         uint8_t aq_fail = 0;
 443
 444         PMD_INIT_FUNC_TRACE();
 445
 446         dev->dev_ops = &i40e_eth_dev_ops;
 447         dev->rx_pkt_burst = i40e_recv_pkts;
 448         dev->tx_pkt_burst = i40e_xmit_pkts;
 449
 450         /* for secondary processes, we don't initialise any further as primary
 451          * has already done this work. Only check we don't need a different
 452          * RX function */
 453         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
 454                 if (dev->data->scattered_rx)
 455                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
 456                 return 0;
 457         }
 458         pci_dev = dev->pci_dev;
 459         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 460         pf->adapter->eth_dev = dev;
 461         pf->dev_data = dev->data;
 462
 463         hw->back = I40E_PF_TO_ADAPTER(pf);
 464         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
 465         if (!hw->hw_addr) {
 466                 PMD_INIT_LOG(ERR, "Hardware is not available, "
 467                              "as address is NULL");
 468                 return -ENODEV;
 469         }
 470
 471         hw->vendor_id = pci_dev->id.vendor_id;
 472         hw->device_id = pci_dev->id.device_id;
 473         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
 474         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
 475         hw->bus.device = pci_dev->addr.devid;
 476         hw->bus.func = pci_dev->addr.function;
 477         hw->adapter_stopped = 0;
 478
 479         /* Make sure all is clean before doing PF reset */
 480         i40e_clear_hw(hw);
 481
 482         /* Initialize the hardware */
 483         i40e_hw_init(hw);
 484
 485         /* Reset here to make sure all is clean for each PF */
 486         ret = i40e_pf_reset(hw);
 487         if (ret) {
 488                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
 489                 return ret;
 490         }
 491
 492         /* Initialize the shared code (base driver) */
 493         ret = i40e_init_shared_code(hw);
 494         if (ret) {
 495                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
 496                 return ret;
 497         }
 498
 499         /*
 500          * To work around the NVM issue,initialize registers
 501          * for flexible payload by software.
 502          * It should be removed once issues are fixed in NVM.
 503          */
 504         i40e_flex_payload_reg_init(hw);
 505
 506         /* Initialize the parameters for adminq */
 507         i40e_init_adminq_parameter(hw);
 508         ret = i40e_init_adminq(hw);
 509         if (ret != I40E_SUCCESS) {
 510                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
 511                 return -EIO;
 512         }
 513         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
 514                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
 515                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
 516                      ((hw->nvm.version >> 12) & 0xf),
 517                      ((hw->nvm.version >> 4) & 0xff),
 518                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
 519
 520         /* Disable LLDP */
 521         ret = i40e_aq_stop_lldp(hw, true, NULL);
 522         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 523                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 524
 525         /* Clear PXE mode */
 526         i40e_clear_pxe_mode(hw);
 527
 528         /*
 529          * On X710, performance number is far from the expectation on recent
 530          * firmware versions. The fix for this issue may not be integrated in
 531          * the following firmware version. So the workaround in software driver
 532          * is needed. It needs to modify the initial values of 3 internal only
 533          * registers. Note that the workaround can be removed when it is fixed
 534          * in firmware in the future.
 535          */
 536         i40e_configure_registers(hw);
 537
 538         /* Get hw capabilities */
 539         ret = i40e_get_cap(hw);
 540         if (ret != I40E_SUCCESS) {
 541                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
 542                 goto err_get_capabilities;
 543         }
 544
 545         /* Initialize parameters for PF */
 546         ret = i40e_pf_parameter_init(dev);
 547         if (ret != 0) {
 548                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
 549                 goto err_parameter_init;
 550         }
 551
 552         /* Initialize the queue management */
 553         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
 554         if (ret < 0) {
 555                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
 556                 goto err_qp_pool_init;
 557         }
 558         ret = i40e_res_pool_init(&pf->msix_pool, 1,
 559                                 hw->func_caps.num_msix_vectors - 1);
 560         if (ret < 0) {
 561                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
 562                 goto err_msix_pool_init;
 563         }
 564
 565         /* Initialize lan hmc */
 566         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
 567                                 hw->func_caps.num_rx_qp, 0, 0);
 568         if (ret != I40E_SUCCESS) {
 569                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
 570                 goto err_init_lan_hmc;
 571         }
 572
 573         /* Configure lan hmc */
 574         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
 575         if (ret != I40E_SUCCESS) {
 576                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
 577                 goto err_configure_lan_hmc;
 578         }
 579
 580         /* Get and check the mac address */
 581         i40e_get_mac_addr(hw, hw->mac.addr);
 582         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
 583                 PMD_INIT_LOG(ERR, "mac address is not valid");
 584                 ret = -EIO;
 585                 goto err_get_mac_addr;
 586         }
 587         /* Copy the permanent MAC address */
 588         ether_addr_copy((struct ether_addr *) hw->mac.addr,
 589                         (struct ether_addr *) hw->mac.perm_addr);
 590
 591         /* Disable flow control */
 592         hw->fc.requested_mode = I40E_FC_NONE;
 593         i40e_set_fc(hw, &aq_fail, TRUE);
 594
 595         /* PF setup, which includes VSI setup */
 596         ret = i40e_pf_setup(pf);
 597         if (ret) {
 598                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
 599                 goto err_setup_pf_switch;
 600         }
 601
 602         vsi = pf->main_vsi;
 603
 604         /* Disable double vlan by default */
 605         i40e_vsi_config_double_vlan(vsi, FALSE);
 606
 607         if (!vsi->max_macaddrs)
 608                 len = ETHER_ADDR_LEN;
 609         else
 610                 len = ETHER_ADDR_LEN * vsi->max_macaddrs;
 611
 612         /* Should be after VSI initialized */
 613         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
 614         if (!dev->data->mac_addrs) {
 615                 PMD_INIT_LOG(ERR, "Failed to allocated memory "
 616                                         "for storing mac address");
 617                 goto err_mac_alloc;
 618         }
 619         ether_addr_copy((struct ether_addr *)hw->mac.perm_addr,
 620                                         &dev->data->mac_addrs[0]);
 621
 622         /* initialize pf host driver to setup SRIOV resource if applicable */
 623         i40e_pf_host_init(dev);
 624
 625         /* register callback func to eal lib */
 626         rte_intr_callback_register(&(pci_dev->intr_handle),
 627                 i40e_dev_interrupt_handler, (void *)dev);
 628
 629         /* configure and enable device interrupt */
 630         i40e_pf_config_irq0(hw);
 631         i40e_pf_enable_irq0(hw);
 632
 633         /* enable uio intr after callback register */
 634         rte_intr_enable(&(pci_dev->intr_handle));
 635         /*
 636          * Add an ethertype filter to drop all flow control frames transmitted
 637          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
 638          * frames to wire.
 639          */
 640         i40e_add_tx_flow_control_drop_filter(pf);
 641
 642         /* initialize mirror rule list */
 643         TAILQ_INIT(&pf->mirror_list);
 644
 645         return 0;
 646
 647 err_mac_alloc:
 648         i40e_vsi_release(pf->main_vsi);
 649 err_setup_pf_switch:
 650 err_get_mac_addr:
 651 err_configure_lan_hmc:
 652         (void)i40e_shutdown_lan_hmc(hw);
 653 err_init_lan_hmc:
 654         i40e_res_pool_destroy(&pf->msix_pool);
 655 err_msix_pool_init:
 656         i40e_res_pool_destroy(&pf->qp_pool);
 657 err_qp_pool_init:
 658 err_parameter_init:
 659 err_get_capabilities:
 660         (void)i40e_shutdown_adminq(hw);
 661
 662         return ret;
 663 }
 664
 665 static int
 666 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
 667 {
 668         struct rte_pci_device *pci_dev;
 669         struct i40e_hw *hw;
 670         struct i40e_filter_control_settings settings;
 671         int ret;
 672         uint8_t aq_fail = 0;
 673
 674         PMD_INIT_FUNC_TRACE();
 675
 676         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
 677                 return 0;
 678
 679         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 680         pci_dev = dev->pci_dev;
 681
 682         if (hw->adapter_stopped == 0)
 683                 i40e_dev_close(dev);
 684
 685         dev->dev_ops = NULL;
 686         dev->rx_pkt_burst = NULL;
 687         dev->tx_pkt_burst = NULL;
 688
 689         /* Disable LLDP */
 690         ret = i40e_aq_stop_lldp(hw, true, NULL);
 691         if (ret != I40E_SUCCESS) /* Its failure can be ignored */
 692                 PMD_INIT_LOG(INFO, "Failed to stop lldp");
 693
 694         /* Clear PXE mode */
 695         i40e_clear_pxe_mode(hw);
 696
 697         /* Unconfigure filter control */
 698         memset(&settings, 0, sizeof(settings));
 699         ret = i40e_set_filter_control(hw, &settings);
 700         if (ret)
 701                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
 702                                         ret);
 703
 704         /* Disable flow control */
 705         hw->fc.requested_mode = I40E_FC_NONE;
 706         i40e_set_fc(hw, &aq_fail, TRUE);
 707
 708         /* uninitialize pf host driver */
 709         i40e_pf_host_uninit(dev);
 710
 711         rte_free(dev->data->mac_addrs);
 712         dev->data->mac_addrs = NULL;
 713
 714         /* disable uio intr before callback unregister */
 715         rte_intr_disable(&(pci_dev->intr_handle));
 716
 717         /* register callback func to eal lib */
 718         rte_intr_callback_unregister(&(pci_dev->intr_handle),
 719                 i40e_dev_interrupt_handler, (void *)dev);
 720
 721         return 0;
 722 }
 723
 724 static int
 725 i40e_dev_configure(struct rte_eth_dev *dev)
 726 {
 727         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 728         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
 729         int ret;
 730
 731         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
 732                 ret = i40e_fdir_setup(pf);
 733                 if (ret != I40E_SUCCESS) {
 734                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
 735                         return -ENOTSUP;
 736                 }
 737                 ret = i40e_fdir_configure(dev);
 738                 if (ret < 0) {
 739                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
 740                         goto err;
 741                 }
 742         } else
 743                 i40e_fdir_teardown(pf);
 744
 745         ret = i40e_dev_init_vlan(dev);
 746         if (ret < 0)
 747                 goto err;
 748
 749         /* VMDQ setup.
 750          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
 751          *  RSS setting have different requirements.
 752          *  General PMD driver call sequence are NIC init, configure,
 753          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
 754          *  will try to lookup the VSI that specific queue belongs to if VMDQ
 755          *  applicable. So, VMDQ setting has to be done before
 756          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
 757          *  For RSS setting, it will try to calculate actual configured RX queue
 758          *  number, which will be available after rx_queue_setup(). dev_start()
 759          *  function is good to place RSS setup.
 760          */
 761         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
 762                 ret = i40e_vmdq_setup(dev);
 763                 if (ret)
 764                         goto err;
 765         }
 766         return 0;
 767 err:
 768         i40e_fdir_teardown(pf);
 769         return ret;
 770 }
 771
 772 void
 773 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
 774 {
 775         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 776         uint16_t msix_vect = vsi->msix_intr;
 777         uint16_t i;
 778
 779         for (i = 0; i < vsi->nb_qps; i++) {
 780                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 781                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
 782                 rte_wmb();
 783         }
 784
 785         if (vsi->type != I40E_VSI_SRIOV) {
 786                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1), 0);
 787                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 788                                 msix_vect - 1), 0);
 789         } else {
 790                 uint32_t reg;
 791                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 792                         vsi->user_param + (msix_vect - 1);
 793
 794                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), 0);
 795         }
 796         I40E_WRITE_FLUSH(hw);
 797 }
 798
 799 static inline uint16_t
 800 i40e_calc_itr_interval(int16_t interval)
 801 {
 802         if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
 803                 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
 804
 805         /* Convert to hardware count, as writing each 1 represents 2 us */
 806         return (interval/2);
 807 }
 808
 809 void
 810 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi)
 811 {
 812         uint32_t val;
 813         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 814         uint16_t msix_vect = vsi->msix_intr;
 815         int i;
 816
 817         for (i = 0; i < vsi->nb_qps; i++)
 818                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
 819
 820         /* Bind all RX queues to allocated MSIX interrupt */
 821         for (i = 0; i < vsi->nb_qps; i++) {
 822                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
 823                         I40E_QINT_RQCTL_ITR_INDX_MASK |
 824                         ((vsi->base_queue + i + 1) <<
 825                         I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
 826                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
 827                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
 828
 829                 if (i == vsi->nb_qps - 1)
 830                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
 831                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), val);
 832         }
 833
 834         /* Write first RX queue to Link list register as the head element */
 835         if (vsi->type != I40E_VSI_SRIOV) {
 836                 uint16_t interval =
 837                         i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
 838
 839                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
 840                                                 (vsi->base_queue <<
 841                                 I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 842                         (0x0 << I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 843
 844                 I40E_WRITE_REG(hw, I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
 845                                                 msix_vect - 1), interval);
 846
 847 #ifndef I40E_GLINT_CTL
 848 #define I40E_GLINT_CTL                     0x0003F800
 849 #define I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK 0x4
 850 #endif
 851                 /* Disable auto-mask on enabling of all none-zero  interrupt */
 852                 I40E_WRITE_REG(hw, I40E_GLINT_CTL,
 853                         I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK);
 854         } else {
 855                 uint32_t reg;
 856
 857                 /* num_msix_vectors_vf needs to minus irq0 */
 858                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
 859                         vsi->user_param + (msix_vect - 1);
 860
 861                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg), (vsi->base_queue <<
 862                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
 863                                 (0x0 << I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
 864         }
 865
 866         I40E_WRITE_FLUSH(hw);
 867 }
 868
 869 static void
 870 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
 871 {
 872         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 873         uint16_t interval = i40e_calc_itr_interval(\
 874                         RTE_LIBRTE_I40E_ITR_INTERVAL);
 875
 876         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1),
 877                                         I40E_PFINT_DYN_CTLN_INTENA_MASK |
 878                                         I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
 879                                 (0 << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT) |
 880                         (interval << I40E_PFINT_DYN_CTLN_INTERVAL_SHIFT));
 881 }
 882
 883 static void
 884 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
 885 {
 886         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
 887
 888         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(vsi->msix_intr - 1), 0);
 889 }
 890
 891 static inline uint8_t
 892 i40e_parse_link_speed(uint16_t eth_link_speed)
 893 {
 894         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
 895
 896         switch (eth_link_speed) {
 897         case ETH_LINK_SPEED_40G:
 898                 link_speed = I40E_LINK_SPEED_40GB;
 899                 break;
 900         case ETH_LINK_SPEED_20G:
 901                 link_speed = I40E_LINK_SPEED_20GB;
 902                 break;
 903         case ETH_LINK_SPEED_10G:
 904                 link_speed = I40E_LINK_SPEED_10GB;
 905                 break;
 906         case ETH_LINK_SPEED_1000:
 907                 link_speed = I40E_LINK_SPEED_1GB;
 908                 break;
 909         case ETH_LINK_SPEED_100:
 910                 link_speed = I40E_LINK_SPEED_100MB;
 911                 break;
 912         }
 913
 914         return link_speed;
 915 }
 916
 917 static int
 918 i40e_phy_conf_link(struct i40e_hw *hw, uint8_t abilities, uint8_t force_speed)
 919 {
 920         enum i40e_status_code status;
 921         struct i40e_aq_get_phy_abilities_resp phy_ab;
 922         struct i40e_aq_set_phy_config phy_conf;
 923         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
 924                         I40E_AQ_PHY_FLAG_PAUSE_RX |
 925                         I40E_AQ_PHY_FLAG_LOW_POWER;
 926         const uint8_t advt = I40E_LINK_SPEED_40GB |
 927                         I40E_LINK_SPEED_10GB |
 928                         I40E_LINK_SPEED_1GB |
 929                         I40E_LINK_SPEED_100MB;
 930         int ret = -ENOTSUP;
 931
 932         /* Skip it on 40G interfaces, as a workaround for the link issue */
 933         if (i40e_is_40G_device(hw->device_id))
 934                 return I40E_SUCCESS;
 935
 936         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
 937                                               NULL);
 938         if (status)
 939                 return ret;
 940
 941         memset(&phy_conf, 0, sizeof(phy_conf));
 942
 943         /* bits 0-2 use the values from get_phy_abilities_resp */
 944         abilities &= ~mask;
 945         abilities |= phy_ab.abilities & mask;
 946
 947         /* update ablities and speed */
 948         if (abilities & I40E_AQ_PHY_AN_ENABLED)
 949                 phy_conf.link_speed = advt;
 950         else
 951                 phy_conf.link_speed = force_speed;
 952
 953         phy_conf.abilities = abilities;
 954
 955         /* use get_phy_abilities_resp value for the rest */
 956         phy_conf.phy_type = phy_ab.phy_type;
 957         phy_conf.eee_capability = phy_ab.eee_capability;
 958         phy_conf.eeer = phy_ab.eeer_val;
 959         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
 960
 961         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
 962                     phy_ab.abilities, phy_ab.link_speed);
 963         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
 964                     phy_conf.abilities, phy_conf.link_speed);
 965
 966         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
 967         if (status)
 968                 return ret;
 969
 970         return I40E_SUCCESS;
 971 }
 972
 973 static int
 974 i40e_apply_link_speed(struct rte_eth_dev *dev)
 975 {
 976         uint8_t speed;
 977         uint8_t abilities = 0;
 978         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 979         struct rte_eth_conf *conf = &dev->data->dev_conf;
 980
 981         speed = i40e_parse_link_speed(conf->link_speed);
 982         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
 983         if (conf->link_speed == ETH_LINK_SPEED_AUTONEG)
 984                 abilities |= I40E_AQ_PHY_AN_ENABLED;
 985         else
 986                 abilities |= I40E_AQ_PHY_LINK_ENABLED;
 987
 988         return i40e_phy_conf_link(hw, abilities, speed);
 989 }
 990
 991 static int
 992 i40e_dev_start(struct rte_eth_dev *dev)
 993 {
 994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 995         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 996         struct i40e_vsi *main_vsi = pf->main_vsi;
 997         int ret, i;
 998
 999         hw->adapter_stopped = 0;
1000
1001         if ((dev->data->dev_conf.link_duplex != ETH_LINK_AUTONEG_DUPLEX) &&
1002                 (dev->data->dev_conf.link_duplex != ETH_LINK_FULL_DUPLEX)) {
1003                 PMD_INIT_LOG(ERR, "Invalid link_duplex (%hu) for port %hhu",
1004                              dev->data->dev_conf.link_duplex,
1005                              dev->data->port_id);
1006                 return -EINVAL;
1007         }
1008
1009         /* Initialize VSI */
1010         ret = i40e_dev_rxtx_init(pf);
1011         if (ret != I40E_SUCCESS) {
1012                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
1013                 goto err_up;
1014         }
1015
1016         /* Map queues with MSIX interrupt */
1017         i40e_vsi_queues_bind_intr(main_vsi);
1018         i40e_vsi_enable_queues_intr(main_vsi);
1019
1020         /* Map VMDQ VSI queues with MSIX interrupt */
1021         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1022                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi);
1023                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
1024         }
1025
1026         /* enable FDIR MSIX interrupt */
1027         if (pf->fdir.fdir_vsi) {
1028                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1029                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1030         }
1031
1032         /* Enable all queues which have been configured */
1033         ret = i40e_dev_switch_queues(pf, TRUE);
1034         if (ret != I40E_SUCCESS) {
1035                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
1036                 goto err_up;
1037         }
1038
1039         /* Enable receiving broadcast packets */
1040         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
1041         if (ret != I40E_SUCCESS)
1042                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1043
1044         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1045                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
1046                                                 true, NULL);
1047                 if (ret != I40E_SUCCESS)
1048                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1049         }
1050
1051         /* Apply link configure */
1052         ret = i40e_apply_link_speed(dev);
1053         if (I40E_SUCCESS != ret) {
1054                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
1055                 goto err_up;
1056         }
1057
1058         return I40E_SUCCESS;
1059
1060 err_up:
1061         i40e_dev_switch_queues(pf, FALSE);
1062         i40e_dev_clear_queues(dev);
1063
1064         return ret;
1065 }
1066
1067 static void
1068 i40e_dev_stop(struct rte_eth_dev *dev)
1069 {
1070         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1071         struct i40e_vsi *main_vsi = pf->main_vsi;
1072         struct i40e_mirror_rule *p_mirror;
1073         int i;
1074
1075         /* Disable all queues */
1076         i40e_dev_switch_queues(pf, FALSE);
1077
1078         /* un-map queues with interrupt registers */
1079         i40e_vsi_disable_queues_intr(main_vsi);
1080         i40e_vsi_queues_unbind_intr(main_vsi);
1081
1082         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1083                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
1084                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
1085         }
1086
1087         if (pf->fdir.fdir_vsi) {
1088                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi);
1089                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
1090         }
1091         /* Clear all queues and release memory */
1092         i40e_dev_clear_queues(dev);
1093
1094         /* Set link down */
1095         i40e_dev_set_link_down(dev);
1096
1097         /* Remove all mirror rules */
1098         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
1099                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
1100                 rte_free(p_mirror);
1101         }
1102         pf->nb_mirror_rule = 0;
1103
1104 }
1105
1106 static void
1107 i40e_dev_close(struct rte_eth_dev *dev)
1108 {
1109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1110         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1111         uint32_t reg;
1112         int i;
1113
1114         PMD_INIT_FUNC_TRACE();
1115
1116         i40e_dev_stop(dev);
1117         hw->adapter_stopped = 1;
1118         i40e_dev_free_queues(dev);
1119
1120         /* Disable interrupt */
1121         i40e_pf_disable_irq0(hw);
1122         rte_intr_disable(&(dev->pci_dev->intr_handle));
1123
1124         /* shutdown and destroy the HMC */
1125         i40e_shutdown_lan_hmc(hw);
1126
1127         /* release all the existing VSIs and VEBs */
1128         i40e_fdir_teardown(pf);
1129         i40e_vsi_release(pf->main_vsi);
1130
1131         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1132                 i40e_vsi_release(pf->vmdq[i].vsi);
1133                 pf->vmdq[i].vsi = NULL;
1134         }
1135
1136         rte_free(pf->vmdq);
1137         pf->vmdq = NULL;
1138
1139         /* shutdown the adminq */
1140         i40e_aq_queue_shutdown(hw, true);
1141         i40e_shutdown_adminq(hw);
1142
1143         i40e_res_pool_destroy(&pf->qp_pool);
1144         i40e_res_pool_destroy(&pf->msix_pool);
1145
1146         /* force a PF reset to clean anything leftover */
1147         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
1148         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
1149                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
1150         I40E_WRITE_FLUSH(hw);
1151 }
1152
1153 static void
1154 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
1155 {
1156         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1157         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1158         struct i40e_vsi *vsi = pf->main_vsi;
1159         int status;
1160
1161         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1162                                                         true, NULL);
1163         if (status != I40E_SUCCESS)
1164                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
1165
1166         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1167                                                         TRUE, NULL);
1168         if (status != I40E_SUCCESS)
1169                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1170
1171 }
1172
1173 static void
1174 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
1175 {
1176         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1177         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1178         struct i40e_vsi *vsi = pf->main_vsi;
1179         int status;
1180
1181         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
1182                                                         false, NULL);
1183         if (status != I40E_SUCCESS)
1184                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
1185
1186         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
1187                                                         false, NULL);
1188         if (status != I40E_SUCCESS)
1189                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1190 }
1191
1192 static void
1193 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
1194 {
1195         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1196         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1197         struct i40e_vsi *vsi = pf->main_vsi;
1198         int ret;
1199
1200         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
1201         if (ret != I40E_SUCCESS)
1202                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
1203 }
1204
1205 static void
1206 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
1207 {
1208         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1209         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1210         struct i40e_vsi *vsi = pf->main_vsi;
1211         int ret;
1212
1213         if (dev->data->promiscuous == 1)
1214                 return; /* must remain in all_multicast mode */
1215
1216         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
1217                                 vsi->seid, FALSE, NULL);
1218         if (ret != I40E_SUCCESS)
1219                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
1220 }
1221
1222 /*
1223  * Set device link up.
1224  */
1225 static int
1226 i40e_dev_set_link_up(struct rte_eth_dev *dev)
1227 {
1228         /* re-apply link speed setting */
1229         return i40e_apply_link_speed(dev);
1230 }
1231
1232 /*
1233  * Set device link down.
1234  */
1235 static int
1236 i40e_dev_set_link_down(__rte_unused struct rte_eth_dev *dev)
1237 {
1238         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
1239         uint8_t abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
1240         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1241
1242         return i40e_phy_conf_link(hw, abilities, speed);
1243 }
1244
1245 int
1246 i40e_dev_link_update(struct rte_eth_dev *dev,
1247                      int wait_to_complete)
1248 {
1249 #define CHECK_INTERVAL 100  /* 100ms */
1250 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
1251         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1252         struct i40e_link_status link_status;
1253         struct rte_eth_link link, old;
1254         int status;
1255         unsigned rep_cnt = MAX_REPEAT_TIME;
1256
1257         memset(&link, 0, sizeof(link));
1258         memset(&old, 0, sizeof(old));
1259         memset(&link_status, 0, sizeof(link_status));
1260         rte_i40e_dev_atomic_read_link_status(dev, &old);
1261
1262         do {
1263                 /* Get link status information from hardware */
1264                 status = i40e_aq_get_link_info(hw, false, &link_status, NULL);
1265                 if (status != I40E_SUCCESS) {
1266                         link.link_speed = ETH_LINK_SPEED_100;
1267                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1268                         PMD_DRV_LOG(ERR, "Failed to get link info");
1269                         goto out;
1270                 }
1271
1272                 link.link_status = link_status.link_info & I40E_AQ_LINK_UP;
1273                 if (!wait_to_complete)
1274                         break;
1275
1276                 rte_delay_ms(CHECK_INTERVAL);
1277         } while (!link.link_status && rep_cnt--);
1278
1279         if (!link.link_status)
1280                 goto out;
1281
1282         /* i40e uses full duplex only */
1283         link.link_duplex = ETH_LINK_FULL_DUPLEX;
1284
1285         /* Parse the link status */
1286         switch (link_status.link_speed) {
1287         case I40E_LINK_SPEED_100MB:
1288                 link.link_speed = ETH_LINK_SPEED_100;
1289                 break;
1290         case I40E_LINK_SPEED_1GB:
1291                 link.link_speed = ETH_LINK_SPEED_1000;
1292                 break;
1293         case I40E_LINK_SPEED_10GB:
1294                 link.link_speed = ETH_LINK_SPEED_10G;
1295                 break;
1296         case I40E_LINK_SPEED_20GB:
1297                 link.link_speed = ETH_LINK_SPEED_20G;
1298                 break;
1299         case I40E_LINK_SPEED_40GB:
1300                 link.link_speed = ETH_LINK_SPEED_40G;
1301                 break;
1302         default:
1303                 link.link_speed = ETH_LINK_SPEED_100;
1304                 break;
1305         }
1306
1307 out:
1308         rte_i40e_dev_atomic_write_link_status(dev, &link);
1309         if (link.link_status == old.link_status)
1310                 return -1;
1311
1312         return 0;
1313 }
1314
1315 /* Get all the statistics of a VSI */
1316 void
1317 i40e_update_vsi_stats(struct i40e_vsi *vsi)
1318 {
1319         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
1320         struct i40e_eth_stats *nes = &vsi->eth_stats;
1321         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1322         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
1323
1324         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
1325                             vsi->offset_loaded, &oes->rx_bytes,
1326                             &nes->rx_bytes);
1327         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
1328                             vsi->offset_loaded, &oes->rx_unicast,
1329                             &nes->rx_unicast);
1330         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
1331                             vsi->offset_loaded, &oes->rx_multicast,
1332                             &nes->rx_multicast);
1333         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
1334                             vsi->offset_loaded, &oes->rx_broadcast,
1335                             &nes->rx_broadcast);
1336         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
1337                             &oes->rx_discards, &nes->rx_discards);
1338         /* GLV_REPC not supported */
1339         /* GLV_RMPC not supported */
1340         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
1341                             &oes->rx_unknown_protocol,
1342                             &nes->rx_unknown_protocol);
1343         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
1344                             vsi->offset_loaded, &oes->tx_bytes,
1345                             &nes->tx_bytes);
1346         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
1347                             vsi->offset_loaded, &oes->tx_unicast,
1348                             &nes->tx_unicast);
1349         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
1350                             vsi->offset_loaded, &oes->tx_multicast,
1351                             &nes->tx_multicast);
1352         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
1353                             vsi->offset_loaded,  &oes->tx_broadcast,
1354                             &nes->tx_broadcast);
1355         /* GLV_TDPC not supported */
1356         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
1357                             &oes->tx_errors, &nes->tx_errors);
1358         vsi->offset_loaded = true;
1359
1360         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
1361                     vsi->vsi_id);
1362         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
1363         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
1364         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
1365         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
1366         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
1367         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1368                     nes->rx_unknown_protocol);
1369         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
1370         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
1371         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
1372         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
1373         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
1374         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
1375         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
1376                     vsi->vsi_id);
1377 }
1378
1379 /* Get all statistics of a port */
1380 static void
1381 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
1382 {
1383         uint32_t i;
1384         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1385         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1386         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
1387         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
1388
1389         /* Get statistics of struct i40e_eth_stats */
1390         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
1391                             I40E_GLPRT_GORCL(hw->port),
1392                             pf->offset_loaded, &os->eth.rx_bytes,
1393                             &ns->eth.rx_bytes);
1394         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
1395                             I40E_GLPRT_UPRCL(hw->port),
1396                             pf->offset_loaded, &os->eth.rx_unicast,
1397                             &ns->eth.rx_unicast);
1398         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
1399                             I40E_GLPRT_MPRCL(hw->port),
1400                             pf->offset_loaded, &os->eth.rx_multicast,
1401                             &ns->eth.rx_multicast);
1402         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
1403                             I40E_GLPRT_BPRCL(hw->port),
1404                             pf->offset_loaded, &os->eth.rx_broadcast,
1405                             &ns->eth.rx_broadcast);
1406         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
1407                             pf->offset_loaded, &os->eth.rx_discards,
1408                             &ns->eth.rx_discards);
1409         /* GLPRT_REPC not supported */
1410         /* GLPRT_RMPC not supported */
1411         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
1412                             pf->offset_loaded,
1413                             &os->eth.rx_unknown_protocol,
1414                             &ns->eth.rx_unknown_protocol);
1415         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
1416                             I40E_GLPRT_GOTCL(hw->port),
1417                             pf->offset_loaded, &os->eth.tx_bytes,
1418                             &ns->eth.tx_bytes);
1419         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
1420                             I40E_GLPRT_UPTCL(hw->port),
1421                             pf->offset_loaded, &os->eth.tx_unicast,
1422                             &ns->eth.tx_unicast);
1423         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
1424                             I40E_GLPRT_MPTCL(hw->port),
1425                             pf->offset_loaded, &os->eth.tx_multicast,
1426                             &ns->eth.tx_multicast);
1427         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
1428                             I40E_GLPRT_BPTCL(hw->port),
1429                             pf->offset_loaded, &os->eth.tx_broadcast,
1430                             &ns->eth.tx_broadcast);
1431         /* GLPRT_TEPC not supported */
1432
1433         /* additional port specific stats */
1434         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
1435                             pf->offset_loaded, &os->tx_dropped_link_down,
1436                             &ns->tx_dropped_link_down);
1437         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
1438                             pf->offset_loaded, &os->crc_errors,
1439                             &ns->crc_errors);
1440         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
1441                             pf->offset_loaded, &os->illegal_bytes,
1442                             &ns->illegal_bytes);
1443         /* GLPRT_ERRBC not supported */
1444         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
1445                             pf->offset_loaded, &os->mac_local_faults,
1446                             &ns->mac_local_faults);
1447         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
1448                             pf->offset_loaded, &os->mac_remote_faults,
1449                             &ns->mac_remote_faults);
1450         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
1451                             pf->offset_loaded, &os->rx_length_errors,
1452                             &ns->rx_length_errors);
1453         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
1454                             pf->offset_loaded, &os->link_xon_rx,
1455                             &ns->link_xon_rx);
1456         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
1457                             pf->offset_loaded, &os->link_xoff_rx,
1458                             &ns->link_xoff_rx);
1459         for (i = 0; i < 8; i++) {
1460                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
1461                                     pf->offset_loaded,
1462                                     &os->priority_xon_rx[i],
1463                                     &ns->priority_xon_rx[i]);
1464                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
1465                                     pf->offset_loaded,
1466                                     &os->priority_xoff_rx[i],
1467                                     &ns->priority_xoff_rx[i]);
1468         }
1469         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
1470                             pf->offset_loaded, &os->link_xon_tx,
1471                             &ns->link_xon_tx);
1472         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
1473                             pf->offset_loaded, &os->link_xoff_tx,
1474                             &ns->link_xoff_tx);
1475         for (i = 0; i < 8; i++) {
1476                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
1477                                     pf->offset_loaded,
1478                                     &os->priority_xon_tx[i],
1479                                     &ns->priority_xon_tx[i]);
1480                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
1481                                     pf->offset_loaded,
1482                                     &os->priority_xoff_tx[i],
1483                                     &ns->priority_xoff_tx[i]);
1484                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
1485                                     pf->offset_loaded,
1486                                     &os->priority_xon_2_xoff[i],
1487                                     &ns->priority_xon_2_xoff[i]);
1488         }
1489         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
1490                             I40E_GLPRT_PRC64L(hw->port),
1491                             pf->offset_loaded, &os->rx_size_64,
1492                             &ns->rx_size_64);
1493         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
1494                             I40E_GLPRT_PRC127L(hw->port),
1495                             pf->offset_loaded, &os->rx_size_127,
1496                             &ns->rx_size_127);
1497         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
1498                             I40E_GLPRT_PRC255L(hw->port),
1499                             pf->offset_loaded, &os->rx_size_255,
1500                             &ns->rx_size_255);
1501         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
1502                             I40E_GLPRT_PRC511L(hw->port),
1503                             pf->offset_loaded, &os->rx_size_511,
1504                             &ns->rx_size_511);
1505         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
1506                             I40E_GLPRT_PRC1023L(hw->port),
1507                             pf->offset_loaded, &os->rx_size_1023,
1508                             &ns->rx_size_1023);
1509         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
1510                             I40E_GLPRT_PRC1522L(hw->port),
1511                             pf->offset_loaded, &os->rx_size_1522,
1512                             &ns->rx_size_1522);
1513         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
1514                             I40E_GLPRT_PRC9522L(hw->port),
1515                             pf->offset_loaded, &os->rx_size_big,
1516                             &ns->rx_size_big);
1517         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
1518                             pf->offset_loaded, &os->rx_undersize,
1519                             &ns->rx_undersize);
1520         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
1521                             pf->offset_loaded, &os->rx_fragments,
1522                             &ns->rx_fragments);
1523         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
1524                             pf->offset_loaded, &os->rx_oversize,
1525                             &ns->rx_oversize);
1526         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
1527                             pf->offset_loaded, &os->rx_jabber,
1528                             &ns->rx_jabber);
1529         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
1530                             I40E_GLPRT_PTC64L(hw->port),
1531                             pf->offset_loaded, &os->tx_size_64,
1532                             &ns->tx_size_64);
1533         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
1534                             I40E_GLPRT_PTC127L(hw->port),
1535                             pf->offset_loaded, &os->tx_size_127,
1536                             &ns->tx_size_127);
1537         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
1538                             I40E_GLPRT_PTC255L(hw->port),
1539                             pf->offset_loaded, &os->tx_size_255,
1540                             &ns->tx_size_255);
1541         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
1542                             I40E_GLPRT_PTC511L(hw->port),
1543                             pf->offset_loaded, &os->tx_size_511,
1544                             &ns->tx_size_511);
1545         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
1546                             I40E_GLPRT_PTC1023L(hw->port),
1547                             pf->offset_loaded, &os->tx_size_1023,
1548                             &ns->tx_size_1023);
1549         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
1550                             I40E_GLPRT_PTC1522L(hw->port),
1551                             pf->offset_loaded, &os->tx_size_1522,
1552                             &ns->tx_size_1522);
1553         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
1554                             I40E_GLPRT_PTC9522L(hw->port),
1555                             pf->offset_loaded, &os->tx_size_big,
1556                             &ns->tx_size_big);
1557         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
1558                            pf->offset_loaded,
1559                            &os->fd_sb_match, &ns->fd_sb_match);
1560         /* GLPRT_MSPDC not supported */
1561         /* GLPRT_XEC not supported */
1562
1563         pf->offset_loaded = true;
1564
1565         if (pf->main_vsi)
1566                 i40e_update_vsi_stats(pf->main_vsi);
1567
1568         stats->ipackets = ns->eth.rx_unicast + ns->eth.rx_multicast +
1569                                                 ns->eth.rx_broadcast;
1570         stats->opackets = ns->eth.tx_unicast + ns->eth.tx_multicast +
1571                                                 ns->eth.tx_broadcast;
1572         stats->ibytes   = ns->eth.rx_bytes;
1573         stats->obytes   = ns->eth.tx_bytes;
1574         stats->oerrors  = ns->eth.tx_errors;
1575         stats->imcasts  = ns->eth.rx_multicast;
1576         stats->fdirmatch = ns->fd_sb_match;
1577
1578         /* Rx Errors */
1579         stats->ibadcrc  = ns->crc_errors;
1580         stats->ibadlen  = ns->rx_length_errors + ns->rx_undersize +
1581                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
1582         stats->imissed  = ns->eth.rx_discards;
1583         stats->ierrors  = stats->ibadcrc + stats->ibadlen + stats->imissed;
1584
1585         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
1586         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
1587         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
1588         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
1589         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
1590         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
1591         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
1592                     ns->eth.rx_unknown_protocol);
1593         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
1594         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
1595         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
1596         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
1597         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
1598         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
1599
1600         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
1601                     ns->tx_dropped_link_down);
1602         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
1603         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
1604                     ns->illegal_bytes);
1605         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
1606         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
1607                     ns->mac_local_faults);
1608         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
1609                     ns->mac_remote_faults);
1610         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
1611                     ns->rx_length_errors);
1612         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
1613         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
1614         for (i = 0; i < 8; i++) {
1615                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
1616                                 i, ns->priority_xon_rx[i]);
1617                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
1618                                 i, ns->priority_xoff_rx[i]);
1619         }
1620         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
1621         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
1622         for (i = 0; i < 8; i++) {
1623                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
1624                                 i, ns->priority_xon_tx[i]);
1625                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
1626                                 i, ns->priority_xoff_tx[i]);
1627                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
1628                                 i, ns->priority_xon_2_xoff[i]);
1629         }
1630         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
1631         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
1632         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
1633         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
1634         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
1635         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
1636         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
1637         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
1638         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
1639         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
1640         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
1641         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
1642         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
1643         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
1644         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
1645         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
1646         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
1647         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
1648         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
1649                         ns->mac_short_packet_dropped);
1650         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
1651                     ns->checksum_error);
1652         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
1653         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
1654 }
1655
1656 /* Reset the statistics */
1657 static void
1658 i40e_dev_stats_reset(struct rte_eth_dev *dev)
1659 {
1660         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1661
1662         /* It results in reloading the start point of each counter */
1663         pf->offset_loaded = false;
1664 }
1665
1666 static int
1667 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
1668                                  __rte_unused uint16_t queue_id,
1669                                  __rte_unused uint8_t stat_idx,
1670                                  __rte_unused uint8_t is_rx)
1671 {
1672         PMD_INIT_FUNC_TRACE();
1673
1674         return -ENOSYS;
1675 }
1676
1677 static void
1678 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
1679 {
1680         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1681         struct i40e_vsi *vsi = pf->main_vsi;
1682
1683         dev_info->max_rx_queues = vsi->nb_qps;
1684         dev_info->max_tx_queues = vsi->nb_qps;
1685         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
1686         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
1687         dev_info->max_mac_addrs = vsi->max_macaddrs;
1688         dev_info->max_vfs = dev->pci_dev->max_vfs;
1689         dev_info->rx_offload_capa =
1690                 DEV_RX_OFFLOAD_VLAN_STRIP |
1691                 DEV_RX_OFFLOAD_QINQ_STRIP |
1692                 DEV_RX_OFFLOAD_IPV4_CKSUM |
1693                 DEV_RX_OFFLOAD_UDP_CKSUM |
1694                 DEV_RX_OFFLOAD_TCP_CKSUM;
1695         dev_info->tx_offload_capa =
1696                 DEV_TX_OFFLOAD_VLAN_INSERT |
1697                 DEV_TX_OFFLOAD_QINQ_INSERT |
1698                 DEV_TX_OFFLOAD_IPV4_CKSUM |
1699                 DEV_TX_OFFLOAD_UDP_CKSUM |
1700                 DEV_TX_OFFLOAD_TCP_CKSUM |
1701                 DEV_TX_OFFLOAD_SCTP_CKSUM |
1702                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
1703                 DEV_TX_OFFLOAD_TCP_TSO;
1704         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
1705                                                 sizeof(uint32_t);
1706         dev_info->reta_size = pf->hash_lut_size;
1707         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
1708
1709         dev_info->default_rxconf = (struct rte_eth_rxconf) {
1710                 .rx_thresh = {
1711                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
1712                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
1713                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
1714                 },
1715                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
1716                 .rx_drop_en = 0,
1717         };
1718
1719         dev_info->default_txconf = (struct rte_eth_txconf) {
1720                 .tx_thresh = {
1721                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
1722                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
1723                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
1724                 },
1725                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
1726                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
1727                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
1728                                 ETH_TXQ_FLAGS_NOOFFLOADS,
1729         };
1730
1731         if (pf->flags & I40E_FLAG_VMDQ) {
1732                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
1733                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
1734                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
1735                                                 pf->max_nb_vmdq_vsi;
1736                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
1737                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
1738                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
1739         }
1740 }
1741
1742 static int
1743 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1744 {
1745         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1746         struct i40e_vsi *vsi = pf->main_vsi;
1747         PMD_INIT_FUNC_TRACE();
1748
1749         if (on)
1750                 return i40e_vsi_add_vlan(vsi, vlan_id);
1751         else
1752                 return i40e_vsi_delete_vlan(vsi, vlan_id);
1753 }
1754
1755 static void
1756 i40e_vlan_tpid_set(__rte_unused struct rte_eth_dev *dev,
1757                    __rte_unused uint16_t tpid)
1758 {
1759         PMD_INIT_FUNC_TRACE();
1760 }
1761
1762 static void
1763 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1764 {
1765         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1766         struct i40e_vsi *vsi = pf->main_vsi;
1767
1768         if (mask & ETH_VLAN_STRIP_MASK) {
1769                 /* Enable or disable VLAN stripping */
1770                 if (dev->data->dev_conf.rxmode.hw_vlan_strip)
1771                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
1772                 else
1773                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
1774         }
1775
1776         if (mask & ETH_VLAN_EXTEND_MASK) {
1777                 if (dev->data->dev_conf.rxmode.hw_vlan_extend)
1778                         i40e_vsi_config_double_vlan(vsi, TRUE);
1779                 else
1780                         i40e_vsi_config_double_vlan(vsi, FALSE);
1781         }
1782 }
1783
1784 static void
1785 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
1786                           __rte_unused uint16_t queue,
1787                           __rte_unused int on)
1788 {
1789         PMD_INIT_FUNC_TRACE();
1790 }
1791
1792 static int
1793 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1794 {
1795         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1796         struct i40e_vsi *vsi = pf->main_vsi;
1797         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
1798         struct i40e_vsi_vlan_pvid_info info;
1799
1800         memset(&info, 0, sizeof(info));
1801         info.on = on;
1802         if (info.on)
1803                 info.config.pvid = pvid;
1804         else {
1805                 info.config.reject.tagged =
1806                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
1807                 info.config.reject.untagged =
1808                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
1809         }
1810
1811         return i40e_vsi_vlan_pvid_set(vsi, &info);
1812 }
1813
1814 static int
1815 i40e_dev_led_on(struct rte_eth_dev *dev)
1816 {
1817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818         uint32_t mode = i40e_led_get(hw);
1819
1820         if (mode == 0)
1821                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
1822
1823         return 0;
1824 }
1825
1826 static int
1827 i40e_dev_led_off(struct rte_eth_dev *dev)
1828 {
1829         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1830         uint32_t mode = i40e_led_get(hw);
1831
1832         if (mode != 0)
1833                 i40e_led_set(hw, 0, false);
1834
1835         return 0;
1836 }
1837
1838 static int
1839 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1840 {
1841         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1842         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1843
1844         fc_conf->pause_time = pf->fc_conf.pause_time;
1845         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
1846         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
1847
1848          /* Return current mode according to actual setting*/
1849         switch (hw->fc.current_mode) {
1850         case I40E_FC_FULL:
1851                 fc_conf->mode = RTE_FC_FULL;
1852                 break;
1853         case I40E_FC_TX_PAUSE:
1854                 fc_conf->mode = RTE_FC_TX_PAUSE;
1855                 break;
1856         case I40E_FC_RX_PAUSE:
1857                 fc_conf->mode = RTE_FC_RX_PAUSE;
1858                 break;
1859         case I40E_FC_NONE:
1860         default:
1861                 fc_conf->mode = RTE_FC_NONE;
1862         };
1863
1864         return 0;
1865 }
1866
1867 static int
1868 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
1869 {
1870         uint32_t mflcn_reg, fctrl_reg, reg;
1871         uint32_t max_high_water;
1872         uint8_t i, aq_failure;
1873         int err;
1874         struct i40e_hw *hw;
1875         struct i40e_pf *pf;
1876         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
1877                 [RTE_FC_NONE] = I40E_FC_NONE,
1878                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
1879                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
1880                 [RTE_FC_FULL] = I40E_FC_FULL
1881         };
1882
1883         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
1884
1885         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
1886         if ((fc_conf->high_water > max_high_water) ||
1887                         (fc_conf->high_water < fc_conf->low_water)) {
1888                 PMD_INIT_LOG(ERR, "Invalid high/low water setup value in KB, "
1889                         "High_water must <= %d.", max_high_water);
1890                 return -EINVAL;
1891         }
1892
1893         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1894         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1895         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
1896
1897         pf->fc_conf.pause_time = fc_conf->pause_time;
1898         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
1899         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
1900
1901         PMD_INIT_FUNC_TRACE();
1902
1903         /* All the link flow control related enable/disable register
1904          * configuration is handle by the F/W
1905          */
1906         err = i40e_set_fc(hw, &aq_failure, true);
1907         if (err < 0)
1908                 return -ENOSYS;
1909
1910         if (i40e_is_40G_device(hw->device_id)) {
1911                 /* Configure flow control refresh threshold,
1912                  * the value for stat_tx_pause_refresh_timer[8]
1913                  * is used for global pause operation.
1914                  */
1915
1916                 I40E_WRITE_REG(hw,
1917                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
1918                                pf->fc_conf.pause_time);
1919
1920                 /* configure the timer value included in transmitted pause
1921                  * frame,
1922                  * the value for stat_tx_pause_quanta[8] is used for global
1923                  * pause operation
1924                  */
1925                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
1926                                pf->fc_conf.pause_time);
1927
1928                 fctrl_reg = I40E_READ_REG(hw,
1929                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
1930
1931                 if (fc_conf->mac_ctrl_frame_fwd != 0)
1932                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
1933                 else
1934                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
1935
1936                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
1937                                fctrl_reg);
1938         } else {
1939                 /* Configure pause time (2 TCs per register) */
1940                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
1941                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
1942                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
1943
1944                 /* Configure flow control refresh threshold value */
1945                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
1946                                pf->fc_conf.pause_time / 2);
1947
1948                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
1949
1950                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
1951                  *depending on configuration
1952                  */
1953                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
1954                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
1955                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
1956                 } else {
1957                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
1958                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
1959                 }
1960
1961                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
1962         }
1963
1964         /* config the water marker both based on the packets and bytes */
1965         I40E_WRITE_REG(hw, I40E_GLRPB_PHW,
1966                        (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
1967                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
1968         I40E_WRITE_REG(hw, I40E_GLRPB_PLW,
1969                        (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
1970                        << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
1971         I40E_WRITE_REG(hw, I40E_GLRPB_GHW,
1972                        pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
1973                        << I40E_KILOSHIFT);
1974         I40E_WRITE_REG(hw, I40E_GLRPB_GLW,
1975                        pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
1976                        << I40E_KILOSHIFT);
1977
1978         I40E_WRITE_FLUSH(hw);
1979
1980         return 0;
1981 }
1982
1983 static int
1984 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
1985                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
1986 {
1987         PMD_INIT_FUNC_TRACE();
1988
1989         return -ENOSYS;
1990 }
1991
1992 /* Add a MAC address, and update filters */
1993 static void
1994 i40e_macaddr_add(struct rte_eth_dev *dev,
1995                  struct ether_addr *mac_addr,
1996                  __rte_unused uint32_t index,
1997                  uint32_t pool)
1998 {
1999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2000         struct i40e_mac_filter_info mac_filter;
2001         struct i40e_vsi *vsi;
2002         int ret;
2003
2004         /* If VMDQ not enabled or configured, return */
2005         if (pool != 0 && (!(pf->flags | I40E_FLAG_VMDQ) || !pf->nb_cfg_vmdq_vsi)) {
2006                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
2007                         pf->flags | I40E_FLAG_VMDQ ? "configured" : "enabled",
2008                         pool);
2009                 return;
2010         }
2011
2012         if (pool > pf->nb_cfg_vmdq_vsi) {
2013                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
2014                                 pool, pf->nb_cfg_vmdq_vsi);
2015                 return;
2016         }
2017
2018         (void)rte_memcpy(&mac_filter.mac_addr, mac_addr, ETHER_ADDR_LEN);
2019         mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
2020
2021         if (pool == 0)
2022                 vsi = pf->main_vsi;
2023         else
2024                 vsi = pf->vmdq[pool - 1].vsi;
2025
2026         ret = i40e_vsi_add_mac(vsi, &mac_filter);
2027         if (ret != I40E_SUCCESS) {
2028                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
2029                 return;
2030         }
2031 }
2032
2033 /* Remove a MAC address, and update filters */
2034 static void
2035 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2036 {
2037         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2038         struct i40e_vsi *vsi;
2039         struct rte_eth_dev_data *data = dev->data;
2040         struct ether_addr *macaddr;
2041         int ret;
2042         uint32_t i;
2043         uint64_t pool_sel;
2044
2045         macaddr = &(data->mac_addrs[index]);
2046
2047         pool_sel = dev->data->mac_pool_sel[index];
2048
2049         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
2050                 if (pool_sel & (1ULL << i)) {
2051                         if (i == 0)
2052                                 vsi = pf->main_vsi;
2053                         else {
2054                                 /* No VMDQ pool enabled or configured */
2055                                 if (!(pf->flags | I40E_FLAG_VMDQ) ||
2056                                         (i > pf->nb_cfg_vmdq_vsi)) {
2057                                         PMD_DRV_LOG(ERR, "No VMDQ pool enabled"
2058                                                         "/configured");
2059                                         return;
2060                                 }
2061                                 vsi = pf->vmdq[i - 1].vsi;
2062                         }
2063                         ret = i40e_vsi_delete_mac(vsi, macaddr);
2064
2065                         if (ret) {
2066                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
2067                                 return;
2068                         }
2069                 }
2070         }
2071 }
2072
2073 /* Set perfect match or hash match of MAC and VLAN for a VF */
2074 static int
2075 i40e_vf_mac_filter_set(struct i40e_pf *pf,
2076                  struct rte_eth_mac_filter *filter,
2077                  bool add)
2078 {
2079         struct i40e_hw *hw;
2080         struct i40e_mac_filter_info mac_filter;
2081         struct ether_addr old_mac;
2082         struct ether_addr *new_mac;
2083         struct i40e_pf_vf *vf = NULL;
2084         uint16_t vf_id;
2085         int ret;
2086
2087         if (pf == NULL) {
2088                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
2089                 return -EINVAL;
2090         }
2091         hw = I40E_PF_TO_HW(pf);
2092
2093         if (filter == NULL) {
2094                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
2095                 return -EINVAL;
2096         }
2097
2098         new_mac = &filter->mac_addr;
2099
2100         if (is_zero_ether_addr(new_mac)) {
2101                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
2102                 return -EINVAL;
2103         }
2104
2105         vf_id = filter->dst_id;
2106
2107         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
2108                 PMD_DRV_LOG(ERR, "Invalid argument.");
2109                 return -EINVAL;
2110         }
2111         vf = &pf->vfs[vf_id];
2112
2113         if (add && is_same_ether_addr(new_mac, &(pf->dev_addr))) {
2114                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
2115                 return -EINVAL;
2116         }
2117
2118         if (add) {
2119                 (void)rte_memcpy(&old_mac, hw->mac.addr, ETHER_ADDR_LEN);
2120                 (void)rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
2121                                 ETHER_ADDR_LEN);
2122                 (void)rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
2123                                  ETHER_ADDR_LEN);
2124
2125                 mac_filter.filter_type = filter->filter_type;
2126                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
2127                 if (ret != I40E_SUCCESS) {
2128                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
2129                         return -1;
2130                 }
2131                 ether_addr_copy(new_mac, &pf->dev_addr);
2132         } else {
2133                 (void)rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
2134                                 ETHER_ADDR_LEN);
2135                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
2136                 if (ret != I40E_SUCCESS) {
2137                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
2138                         return -1;
2139                 }
2140
2141                 /* Clear device address as it has been removed */
2142                 if (is_same_ether_addr(&(pf->dev_addr), new_mac))
2143                         memset(&pf->dev_addr, 0, sizeof(struct ether_addr));
2144         }
2145
2146         return 0;
2147 }
2148
2149 /* MAC filter handle */
2150 static int
2151 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
2152                 void *arg)
2153 {
2154         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2155         struct rte_eth_mac_filter *filter;
2156         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2157         int ret = I40E_NOT_SUPPORTED;
2158
2159         filter = (struct rte_eth_mac_filter *)(arg);
2160
2161         switch (filter_op) {
2162         case RTE_ETH_FILTER_NOP:
2163                 ret = I40E_SUCCESS;
2164                 break;
2165         case RTE_ETH_FILTER_ADD:
2166                 i40e_pf_disable_irq0(hw);
2167                 if (filter->is_vf)
2168                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
2169                 i40e_pf_enable_irq0(hw);
2170                 break;
2171         case RTE_ETH_FILTER_DELETE:
2172                 i40e_pf_disable_irq0(hw);
2173                 if (filter->is_vf)
2174                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
2175                 i40e_pf_enable_irq0(hw);
2176                 break;
2177         default:
2178                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
2179                 ret = I40E_ERR_PARAM;
2180                 break;
2181         }
2182
2183         return ret;
2184 }
2185
2186 static int
2187 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
2188                          struct rte_eth_rss_reta_entry64 *reta_conf,
2189                          uint16_t reta_size)
2190 {
2191         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2192         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2193         uint32_t lut, l;
2194         uint16_t i, j, lut_size = pf->hash_lut_size;
2195         uint16_t idx, shift;
2196         uint8_t mask;
2197
2198         if (reta_size != lut_size ||
2199                 reta_size > ETH_RSS_RETA_SIZE_512) {
2200                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2201                         "(%d) doesn't match the number hardware can supported "
2202                                         "(%d)\n", reta_size, lut_size);
2203                 return -EINVAL;
2204         }
2205
2206         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2207                 idx = i / RTE_RETA_GROUP_SIZE;
2208                 shift = i % RTE_RETA_GROUP_SIZE;
2209                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2210                                                 I40E_4_BIT_MASK);
2211                 if (!mask)
2212                         continue;
2213                 if (mask == I40E_4_BIT_MASK)
2214                         l = 0;
2215                 else
2216                         l = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2217                 for (j = 0, lut = 0; j < I40E_4_BIT_WIDTH; j++) {
2218                         if (mask & (0x1 << j))
2219                                 lut |= reta_conf[idx].reta[shift + j] <<
2220                                                         (CHAR_BIT * j);
2221                         else
2222                                 lut |= l & (I40E_8_BIT_MASK << (CHAR_BIT * j));
2223                 }
2224                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
2225         }
2226
2227         return 0;
2228 }
2229
2230 static int
2231 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
2232                         struct rte_eth_rss_reta_entry64 *reta_conf,
2233                         uint16_t reta_size)
2234 {
2235         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2237         uint32_t lut;
2238         uint16_t i, j, lut_size = pf->hash_lut_size;
2239         uint16_t idx, shift;
2240         uint8_t mask;
2241
2242         if (reta_size != lut_size ||
2243                 reta_size > ETH_RSS_RETA_SIZE_512) {
2244                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2245                         "(%d) doesn't match the number hardware can supported "
2246                                         "(%d)\n", reta_size, lut_size);
2247                 return -EINVAL;
2248         }
2249
2250         for (i = 0; i < reta_size; i += I40E_4_BIT_WIDTH) {
2251                 idx = i / RTE_RETA_GROUP_SIZE;
2252                 shift = i % RTE_RETA_GROUP_SIZE;
2253                 mask = (uint8_t)((reta_conf[idx].mask >> shift) &
2254                                                 I40E_4_BIT_MASK);
2255                 if (!mask)
2256                         continue;
2257
2258                 lut = I40E_READ_REG(hw, I40E_PFQF_HLUT(i >> 2));
2259                 for (j = 0; j < I40E_4_BIT_WIDTH; j++) {
2260                         if (mask & (0x1 << j))
2261                                 reta_conf[idx].reta[shift + j] = ((lut >>
2262                                         (CHAR_BIT * j)) & I40E_8_BIT_MASK);
2263                 }
2264         }
2265
2266         return 0;
2267 }
2268
2269 /**
2270  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
2271  * @hw:   pointer to the HW structure
2272  * @mem:  pointer to mem struct to fill out
2273  * @size: size of memory requested
2274  * @alignment: what to align the allocation to
2275  **/
2276 enum i40e_status_code
2277 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2278                         struct i40e_dma_mem *mem,
2279                         u64 size,
2280                         u32 alignment)
2281 {
2282         static uint64_t id = 0;
2283         const struct rte_memzone *mz = NULL;
2284         char z_name[RTE_MEMZONE_NAMESIZE];
2285
2286         if (!mem)
2287                 return I40E_ERR_PARAM;
2288
2289         id++;
2290         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, id);
2291 #ifdef RTE_LIBRTE_XEN_DOM0
2292         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY, 0,
2293                                          alignment, RTE_PGSIZE_2M);
2294 #else
2295         mz = rte_memzone_reserve_aligned(z_name, size, SOCKET_ID_ANY, 0,
2296                                          alignment);
2297 #endif
2298         if (!mz)
2299                 return I40E_ERR_NO_MEMORY;
2300
2301         mem->id = id;
2302         mem->size = size;
2303         mem->va = mz->addr;
2304 #ifdef RTE_LIBRTE_XEN_DOM0
2305         mem->pa = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
2306 #else
2307         mem->pa = mz->phys_addr;
2308 #endif
2309
2310         return I40E_SUCCESS;
2311 }
2312
2313 /**
2314  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
2315  * @hw:   pointer to the HW structure
2316  * @mem:  ptr to mem struct to free
2317  **/
2318 enum i40e_status_code
2319 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2320                     struct i40e_dma_mem *mem)
2321 {
2322         if (!mem || !mem->va)
2323                 return I40E_ERR_PARAM;
2324
2325         mem->va = NULL;
2326         mem->pa = (u64)0;
2327
2328         return I40E_SUCCESS;
2329 }
2330
2331 /**
2332  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
2333  * @hw:   pointer to the HW structure
2334  * @mem:  pointer to mem struct to fill out
2335  * @size: size of memory requested
2336  **/
2337 enum i40e_status_code
2338 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2339                          struct i40e_virt_mem *mem,
2340                          u32 size)
2341 {
2342         if (!mem)
2343                 return I40E_ERR_PARAM;
2344
2345         mem->size = size;
2346         mem->va = rte_zmalloc("i40e", size, 0);
2347
2348         if (mem->va)
2349                 return I40E_SUCCESS;
2350         else
2351                 return I40E_ERR_NO_MEMORY;
2352 }
2353
2354 /**
2355  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
2356  * @hw:   pointer to the HW structure
2357  * @mem:  pointer to mem struct to free
2358  **/
2359 enum i40e_status_code
2360 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
2361                      struct i40e_virt_mem *mem)
2362 {
2363         if (!mem)
2364                 return I40E_ERR_PARAM;
2365
2366         rte_free(mem->va);
2367         mem->va = NULL;
2368
2369         return I40E_SUCCESS;
2370 }
2371
2372 void
2373 i40e_init_spinlock_d(struct i40e_spinlock *sp)
2374 {
2375         rte_spinlock_init(&sp->spinlock);
2376 }
2377
2378 void
2379 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
2380 {
2381         rte_spinlock_lock(&sp->spinlock);
2382 }
2383
2384 void
2385 i40e_release_spinlock_d(struct i40e_spinlock *sp)
2386 {
2387         rte_spinlock_unlock(&sp->spinlock);
2388 }
2389
2390 void
2391 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
2392 {
2393         return;
2394 }
2395
2396 /**
2397  * Get the hardware capabilities, which will be parsed
2398  * and saved into struct i40e_hw.
2399  */
2400 static int
2401 i40e_get_cap(struct i40e_hw *hw)
2402 {
2403         struct i40e_aqc_list_capabilities_element_resp *buf;
2404         uint16_t len, size = 0;
2405         int ret;
2406
2407         /* Calculate a huge enough buff for saving response data temporarily */
2408         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
2409                                                 I40E_MAX_CAP_ELE_NUM;
2410         buf = rte_zmalloc("i40e", len, 0);
2411         if (!buf) {
2412                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
2413                 return I40E_ERR_NO_MEMORY;
2414         }
2415
2416         /* Get, parse the capabilities and save it to hw */
2417         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
2418                         i40e_aqc_opc_list_func_capabilities, NULL);
2419         if (ret != I40E_SUCCESS)
2420                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
2421
2422         /* Free the temporary buffer after being used */
2423         rte_free(buf);
2424
2425         return ret;
2426 }
2427
2428 static int
2429 i40e_pf_parameter_init(struct rte_eth_dev *dev)
2430 {
2431         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2432         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2433         uint16_t sum_queues = 0, sum_vsis, left_queues;
2434
2435         /* First check if FW support SRIOV */
2436         if (dev->pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
2437                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
2438                 return -EINVAL;
2439         }
2440         /* Add the parameter init for LFC */
2441         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
2442         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
2443         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
2444
2445         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
2446         pf->max_num_vsi = RTE_MIN(hw->func_caps.num_vsis, I40E_MAX_NUM_VSIS);
2447         PMD_INIT_LOG(INFO, "Max supported VSIs:%u", pf->max_num_vsi);
2448         /* Allocate queues for pf */
2449         if (hw->func_caps.rss) {
2450                 pf->flags |= I40E_FLAG_RSS;
2451                 pf->lan_nb_qps = RTE_MIN(hw->func_caps.num_tx_qp,
2452                         (uint32_t)(1 << hw->func_caps.rss_table_entry_width));
2453                 pf->lan_nb_qps = i40e_align_floor(pf->lan_nb_qps);
2454         } else
2455                 pf->lan_nb_qps = 1;
2456         sum_queues = pf->lan_nb_qps;
2457         /* Default VSI is not counted in */
2458         sum_vsis = 0;
2459         PMD_INIT_LOG(INFO, "PF queue pairs:%u", pf->lan_nb_qps);
2460
2461         if (hw->func_caps.sr_iov_1_1 && dev->pci_dev->max_vfs) {
2462                 pf->flags |= I40E_FLAG_SRIOV;
2463                 pf->vf_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
2464                 if (dev->pci_dev->max_vfs > hw->func_caps.num_vfs) {
2465                         PMD_INIT_LOG(ERR, "Config VF number %u, "
2466                                      "max supported %u.",
2467                                      dev->pci_dev->max_vfs,
2468                                      hw->func_caps.num_vfs);
2469                         return -EINVAL;
2470                 }
2471                 if (pf->vf_nb_qps > I40E_MAX_QP_NUM_PER_VF) {
2472                         PMD_INIT_LOG(ERR, "FVL VF queue %u, "
2473                                      "max support %u queues.",
2474                                      pf->vf_nb_qps, I40E_MAX_QP_NUM_PER_VF);
2475                         return -EINVAL;
2476                 }
2477                 pf->vf_num = dev->pci_dev->max_vfs;
2478                 sum_queues += pf->vf_nb_qps * pf->vf_num;
2479                 sum_vsis   += pf->vf_num;
2480                 PMD_INIT_LOG(INFO, "Max VF num:%u each has queue pairs:%u",
2481                              pf->vf_num, pf->vf_nb_qps);
2482         } else
2483                 pf->vf_num = 0;
2484
2485         if (hw->func_caps.vmdq) {
2486                 pf->flags |= I40E_FLAG_VMDQ;
2487                 pf->vmdq_nb_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2488                 pf->max_nb_vmdq_vsi = 1;
2489                 /*
2490                  * If VMDQ available, assume a single VSI can be created.  Will adjust
2491                  * later.
2492                  */
2493                 sum_queues += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
2494                 sum_vsis += pf->max_nb_vmdq_vsi;
2495         } else {
2496                 pf->vmdq_nb_qps = 0;
2497                 pf->max_nb_vmdq_vsi = 0;
2498         }
2499         pf->nb_cfg_vmdq_vsi = 0;
2500
2501         if (hw->func_caps.fd) {
2502                 pf->flags |= I40E_FLAG_FDIR;
2503                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
2504                 /**
2505                  * Each flow director consumes one VSI and one queue,
2506                  * but can't calculate out predictably here.
2507                  */
2508         }
2509
2510         if (sum_vsis > pf->max_num_vsi ||
2511                 sum_queues > hw->func_caps.num_rx_qp) {
2512                 PMD_INIT_LOG(ERR, "VSI/QUEUE setting can't be satisfied");
2513                 PMD_INIT_LOG(ERR, "Max VSIs: %u, asked:%u",
2514                              pf->max_num_vsi, sum_vsis);
2515                 PMD_INIT_LOG(ERR, "Total queue pairs:%u, asked:%u",
2516                              hw->func_caps.num_rx_qp, sum_queues);
2517                 return -EINVAL;
2518         }
2519
2520         /* Adjust VMDQ setting to support as many VMs as possible */
2521         if (pf->flags & I40E_FLAG_VMDQ) {
2522                 left_queues = hw->func_caps.num_rx_qp - sum_queues;
2523
2524                 pf->max_nb_vmdq_vsi += RTE_MIN(left_queues / pf->vmdq_nb_qps,
2525                                         pf->max_num_vsi - sum_vsis);
2526
2527                 /* Limit the max VMDQ number that rte_ether that can support  */
2528                 pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
2529                                         ETH_64_POOLS - 1);
2530
2531                 PMD_INIT_LOG(INFO, "Max VMDQ VSI num:%u",
2532                                 pf->max_nb_vmdq_vsi);
2533                 PMD_INIT_LOG(INFO, "VMDQ queue pairs:%u", pf->vmdq_nb_qps);
2534         }
2535
2536         /* Each VSI occupy 1 MSIX interrupt at least, plus IRQ0 for misc intr
2537          * cause */
2538         if (sum_vsis > hw->func_caps.num_msix_vectors - 1) {
2539                 PMD_INIT_LOG(ERR, "Too many VSIs(%u), MSIX intr(%u) not enough",
2540                              sum_vsis, hw->func_caps.num_msix_vectors);
2541                 return -EINVAL;
2542         }
2543         return I40E_SUCCESS;
2544 }
2545
2546 static int
2547 i40e_pf_get_switch_config(struct i40e_pf *pf)
2548 {
2549         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2550         struct i40e_aqc_get_switch_config_resp *switch_config;
2551         struct i40e_aqc_switch_config_element_resp *element;
2552         uint16_t start_seid = 0, num_reported;
2553         int ret;
2554
2555         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
2556                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
2557         if (!switch_config) {
2558                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
2559                 return -ENOMEM;
2560         }
2561
2562         /* Get the switch configurations */
2563         ret = i40e_aq_get_switch_config(hw, switch_config,
2564                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
2565         if (ret != I40E_SUCCESS) {
2566                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
2567                 goto fail;
2568         }
2569         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
2570         if (num_reported != 1) { /* The number should be 1 */
2571                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
2572                 goto fail;
2573         }
2574
2575         /* Parse the switch configuration elements */
2576         element = &(switch_config->element[0]);
2577         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
2578                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
2579                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
2580         } else
2581                 PMD_DRV_LOG(INFO, "Unknown element type");
2582
2583 fail:
2584         rte_free(switch_config);
2585
2586         return ret;
2587 }
2588
2589 static int
2590 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
2591                         uint32_t num)
2592 {
2593         struct pool_entry *entry;
2594
2595         if (pool == NULL || num == 0)
2596                 return -EINVAL;
2597
2598         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
2599         if (entry == NULL) {
2600                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
2601                 return -ENOMEM;
2602         }
2603
2604         /* queue heap initialize */
2605         pool->num_free = num;
2606         pool->num_alloc = 0;
2607         pool->base = base;
2608         LIST_INIT(&pool->alloc_list);
2609         LIST_INIT(&pool->free_list);
2610
2611         /* Initialize element  */
2612         entry->base = 0;
2613         entry->len = num;
2614
2615         LIST_INSERT_HEAD(&pool->free_list, entry, next);
2616         return 0;
2617 }
2618
2619 static void
2620 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
2621 {
2622         struct pool_entry *entry;
2623
2624         if (pool == NULL)
2625                 return;
2626
2627         LIST_FOREACH(entry, &pool->alloc_list, next) {
2628                 LIST_REMOVE(entry, next);
2629                 rte_free(entry);
2630         }
2631
2632         LIST_FOREACH(entry, &pool->free_list, next) {
2633                 LIST_REMOVE(entry, next);
2634                 rte_free(entry);
2635         }
2636
2637         pool->num_free = 0;
2638         pool->num_alloc = 0;
2639         pool->base = 0;
2640         LIST_INIT(&pool->alloc_list);
2641         LIST_INIT(&pool->free_list);
2642 }
2643
2644 static int
2645 i40e_res_pool_free(struct i40e_res_pool_info *pool,
2646                        uint32_t base)
2647 {
2648         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
2649         uint32_t pool_offset;
2650         int insert;
2651
2652         if (pool == NULL) {
2653                 PMD_DRV_LOG(ERR, "Invalid parameter");
2654                 return -EINVAL;
2655         }
2656
2657         pool_offset = base - pool->base;
2658         /* Lookup in alloc list */
2659         LIST_FOREACH(entry, &pool->alloc_list, next) {
2660                 if (entry->base == pool_offset) {
2661                         valid_entry = entry;
2662                         LIST_REMOVE(entry, next);
2663                         break;
2664                 }
2665         }
2666
2667         /* Not find, return */
2668         if (valid_entry == NULL) {
2669                 PMD_DRV_LOG(ERR, "Failed to find entry");
2670                 return -EINVAL;
2671         }
2672
2673         /**
2674          * Found it, move it to free list  and try to merge.
2675          * In order to make merge easier, always sort it by qbase.
2676          * Find adjacent prev and last entries.
2677          */
2678         prev = next = NULL;
2679         LIST_FOREACH(entry, &pool->free_list, next) {
2680                 if (entry->base > valid_entry->base) {
2681                         next = entry;
2682                         break;
2683                 }
2684                 prev = entry;
2685         }
2686
2687         insert = 0;
2688         /* Try to merge with next one*/
2689         if (next != NULL) {
2690                 /* Merge with next one */
2691                 if (valid_entry->base + valid_entry->len == next->base) {
2692                         next->base = valid_entry->base;
2693                         next->len += valid_entry->len;
2694                         rte_free(valid_entry);
2695                         valid_entry = next;
2696                         insert = 1;
2697                 }
2698         }
2699
2700         if (prev != NULL) {
2701                 /* Merge with previous one */
2702                 if (prev->base + prev->len == valid_entry->base) {
2703                         prev->len += valid_entry->len;
2704                         /* If it merge with next one, remove next node */
2705                         if (insert == 1) {
2706                                 LIST_REMOVE(valid_entry, next);
2707                                 rte_free(valid_entry);
2708                         } else {
2709                                 rte_free(valid_entry);
2710                                 insert = 1;
2711                         }
2712                 }
2713         }
2714
2715         /* Not find any entry to merge, insert */
2716         if (insert == 0) {
2717                 if (prev != NULL)
2718                         LIST_INSERT_AFTER(prev, valid_entry, next);
2719                 else if (next != NULL)
2720                         LIST_INSERT_BEFORE(next, valid_entry, next);
2721                 else /* It's empty list, insert to head */
2722                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
2723         }
2724
2725         pool->num_free += valid_entry->len;
2726         pool->num_alloc -= valid_entry->len;
2727
2728         return 0;
2729 }
2730
2731 static int
2732 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
2733                        uint16_t num)
2734 {
2735         struct pool_entry *entry, *valid_entry;
2736
2737         if (pool == NULL || num == 0) {
2738                 PMD_DRV_LOG(ERR, "Invalid parameter");
2739                 return -EINVAL;
2740         }
2741
2742         if (pool->num_free < num) {
2743                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
2744                             num, pool->num_free);
2745                 return -ENOMEM;
2746         }
2747
2748         valid_entry = NULL;
2749         /* Lookup  in free list and find most fit one */
2750         LIST_FOREACH(entry, &pool->free_list, next) {
2751                 if (entry->len >= num) {
2752                         /* Find best one */
2753                         if (entry->len == num) {
2754                                 valid_entry = entry;
2755                                 break;
2756                         }
2757                         if (valid_entry == NULL || valid_entry->len > entry->len)
2758                                 valid_entry = entry;
2759                 }
2760         }
2761
2762         /* Not find one to satisfy the request, return */
2763         if (valid_entry == NULL) {
2764                 PMD_DRV_LOG(ERR, "No valid entry found");
2765                 return -ENOMEM;
2766         }
2767         /**
2768          * The entry have equal queue number as requested,
2769          * remove it from alloc_list.
2770          */
2771         if (valid_entry->len == num) {
2772                 LIST_REMOVE(valid_entry, next);
2773         } else {
2774                 /**
2775                  * The entry have more numbers than requested,
2776                  * create a new entry for alloc_list and minus its
2777                  * queue base and number in free_list.
2778                  */
2779                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
2780                 if (entry == NULL) {
2781                         PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2782                                     "resource pool");
2783                         return -ENOMEM;
2784                 }
2785                 entry->base = valid_entry->base;
2786                 entry->len = num;
2787                 valid_entry->base += num;
2788                 valid_entry->len -= num;
2789                 valid_entry = entry;
2790         }
2791
2792         /* Insert it into alloc list, not sorted */
2793         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
2794
2795         pool->num_free -= valid_entry->len;
2796         pool->num_alloc += valid_entry->len;
2797
2798         return (valid_entry->base + pool->base);
2799 }
2800
2801 /**
2802  * bitmap_is_subset - Check whether src2 is subset of src1
2803  **/
2804 static inline int
2805 bitmap_is_subset(uint8_t src1, uint8_t src2)
2806 {
2807         return !((src1 ^ src2) & src2);
2808 }
2809
2810 static int
2811 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2812 {
2813         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2814
2815         /* If DCB is not supported, only default TC is supported */
2816         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
2817                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
2818                 return -EINVAL;
2819         }
2820
2821         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
2822                 PMD_DRV_LOG(ERR, "Enabled TC map 0x%x not applicable to "
2823                             "HW support 0x%x", hw->func_caps.enabled_tcmap,
2824                             enabled_tcmap);
2825                 return -EINVAL;
2826         }
2827         return I40E_SUCCESS;
2828 }
2829
2830 int
2831 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
2832                                 struct i40e_vsi_vlan_pvid_info *info)
2833 {
2834         struct i40e_hw *hw;
2835         struct i40e_vsi_context ctxt;
2836         uint8_t vlan_flags = 0;
2837         int ret;
2838
2839         if (vsi == NULL || info == NULL) {
2840                 PMD_DRV_LOG(ERR, "invalid parameters");
2841                 return I40E_ERR_PARAM;
2842         }
2843
2844         if (info->on) {
2845                 vsi->info.pvid = info->config.pvid;
2846                 /**
2847                  * If insert pvid is enabled, only tagged pkts are
2848                  * allowed to be sent out.
2849                  */
2850                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
2851                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2852         } else {
2853                 vsi->info.pvid = 0;
2854                 if (info->config.reject.tagged == 0)
2855                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
2856
2857                 if (info->config.reject.untagged == 0)
2858                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
2859         }
2860         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
2861                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
2862         vsi->info.port_vlan_flags |= vlan_flags;
2863         vsi->info.valid_sections =
2864                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
2865         memset(&ctxt, 0, sizeof(ctxt));
2866         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2867         ctxt.seid = vsi->seid;
2868
2869         hw = I40E_VSI_TO_HW(vsi);
2870         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
2871         if (ret != I40E_SUCCESS)
2872                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
2873
2874         return ret;
2875 }
2876
2877 static int
2878 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
2879 {
2880         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2881         int i, ret;
2882         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
2883
2884         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2885         if (ret != I40E_SUCCESS)
2886                 return ret;
2887
2888         if (!vsi->seid) {
2889                 PMD_DRV_LOG(ERR, "seid not valid");
2890                 return -EINVAL;
2891         }
2892
2893         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
2894         tc_bw_data.tc_valid_bits = enabled_tcmap;
2895         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2896                 tc_bw_data.tc_bw_credits[i] =
2897                         (enabled_tcmap & (1 << i)) ? 1 : 0;
2898
2899         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
2900         if (ret != I40E_SUCCESS) {
2901                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
2902                 return ret;
2903         }
2904
2905         (void)rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
2906                                         sizeof(vsi->info.qs_handle));
2907         return I40E_SUCCESS;
2908 }
2909
2910 static int
2911 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
2912                                  struct i40e_aqc_vsi_properties_data *info,
2913                                  uint8_t enabled_tcmap)
2914 {
2915         int ret, total_tc = 0, i;
2916         uint16_t qpnum_per_tc, bsf, qp_idx;
2917
2918         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
2919         if (ret != I40E_SUCCESS)
2920                 return ret;
2921
2922         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
2923                 if (enabled_tcmap & (1 << i))
2924                         total_tc++;
2925         vsi->enabled_tc = enabled_tcmap;
2926
2927         /* Number of queues per enabled TC */
2928         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
2929         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
2930         bsf = rte_bsf32(qpnum_per_tc);
2931
2932         /* Adjust the queue number to actual queues that can be applied */
2933         vsi->nb_qps = qpnum_per_tc * total_tc;
2934
2935         /**
2936          * Configure TC and queue mapping parameters, for enabled TC,
2937          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
2938          * default queue will serve it.
2939          */
2940         qp_idx = 0;
2941         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2942                 if (vsi->enabled_tc & (1 << i)) {
2943                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
2944                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
2945                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
2946                         qp_idx += qpnum_per_tc;
2947                 } else
2948                         info->tc_mapping[i] = 0;
2949         }
2950
2951         /* Associate queue number with VSI */
2952         if (vsi->type == I40E_VSI_SRIOV) {
2953                 info->mapping_flags |=
2954                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
2955                 for (i = 0; i < vsi->nb_qps; i++)
2956                         info->queue_mapping[i] =
2957                                 rte_cpu_to_le_16(vsi->base_queue + i);
2958         } else {
2959                 info->mapping_flags |=
2960                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
2961                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
2962         }
2963         info->valid_sections |=
2964                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
2965
2966         return I40E_SUCCESS;
2967 }
2968
2969 static int
2970 i40e_veb_release(struct i40e_veb *veb)
2971 {
2972         struct i40e_vsi *vsi;
2973         struct i40e_hw *hw;
2974
2975         if (veb == NULL || veb->associate_vsi == NULL)
2976                 return -EINVAL;
2977
2978         if (!TAILQ_EMPTY(&veb->head)) {
2979                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
2980                 return -EACCES;
2981         }
2982
2983         vsi = veb->associate_vsi;
2984         hw = I40E_VSI_TO_HW(vsi);
2985
2986         vsi->uplink_seid = veb->uplink_seid;
2987         i40e_aq_delete_element(hw, veb->seid, NULL);
2988         rte_free(veb);
2989         vsi->veb = NULL;
2990         return I40E_SUCCESS;
2991 }
2992
2993 /* Setup a veb */
2994 static struct i40e_veb *
2995 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
2996 {
2997         struct i40e_veb *veb;
2998         int ret;
2999         struct i40e_hw *hw;
3000
3001         if (NULL == pf || vsi == NULL) {
3002                 PMD_DRV_LOG(ERR, "veb setup failed, "
3003                             "associated VSI shouldn't null");
3004                 return NULL;
3005         }
3006         hw = I40E_PF_TO_HW(pf);
3007
3008         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
3009         if (!veb) {
3010                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
3011                 goto fail;
3012         }
3013
3014         veb->associate_vsi = vsi;
3015         TAILQ_INIT(&veb->head);
3016         veb->uplink_seid = vsi->uplink_seid;
3017
3018         ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
3019                 I40E_DEFAULT_TCMAP, false, false, &veb->seid, NULL);
3020
3021         if (ret != I40E_SUCCESS) {
3022                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
3023                             hw->aq.asq_last_status);
3024                 goto fail;
3025         }
3026
3027         /* get statistics index */
3028         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
3029                                 &veb->stats_idx, NULL, NULL, NULL);
3030         if (ret != I40E_SUCCESS) {
3031                 PMD_DRV_LOG(ERR, "Get veb statics index failed, aq_err: %d",
3032                             hw->aq.asq_last_status);
3033                 goto fail;
3034         }
3035
3036         /* Get VEB bandwidth, to be implemented */
3037         /* Now associated vsi binding to the VEB, set uplink to this VEB */
3038         vsi->uplink_seid = veb->seid;
3039
3040         return veb;
3041 fail:
3042         rte_free(veb);
3043         return NULL;
3044 }
3045
3046 int
3047 i40e_vsi_release(struct i40e_vsi *vsi)
3048 {
3049         struct i40e_pf *pf;
3050         struct i40e_hw *hw;
3051         struct i40e_vsi_list *vsi_list;
3052         int ret;
3053         struct i40e_mac_filter *f;
3054
3055         if (!vsi)
3056                 return I40E_SUCCESS;
3057
3058         pf = I40E_VSI_TO_PF(vsi);
3059         hw = I40E_VSI_TO_HW(vsi);
3060
3061         /* VSI has child to attach, release child first */
3062         if (vsi->veb) {
3063                 TAILQ_FOREACH(vsi_list, &vsi->veb->head, list) {
3064                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
3065                                 return -1;
3066                         TAILQ_REMOVE(&vsi->veb->head, vsi_list, list);
3067                 }
3068                 i40e_veb_release(vsi->veb);
3069         }
3070
3071         /* Remove all macvlan filters of the VSI */
3072         i40e_vsi_remove_all_macvlan_filter(vsi);
3073         TAILQ_FOREACH(f, &vsi->mac_list, next)
3074                 rte_free(f);
3075
3076         if (vsi->type != I40E_VSI_MAIN) {
3077                 /* Remove vsi from parent's sibling list */
3078                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
3079                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
3080                         return I40E_ERR_PARAM;
3081                 }
3082                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
3083                                 &vsi->sib_vsi_list, list);
3084
3085                 /* Remove all switch element of the VSI */
3086                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
3087                 if (ret != I40E_SUCCESS)
3088                         PMD_DRV_LOG(ERR, "Failed to delete element");
3089         }
3090         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
3091
3092         if (vsi->type != I40E_VSI_SRIOV)
3093                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
3094         rte_free(vsi);
3095
3096         return I40E_SUCCESS;
3097 }
3098
3099 static int
3100 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
3101 {
3102         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3103         struct i40e_aqc_remove_macvlan_element_data def_filter;
3104         struct i40e_mac_filter_info filter;
3105         int ret;
3106
3107         if (vsi->type != I40E_VSI_MAIN)
3108                 return I40E_ERR_CONFIG;
3109         memset(&def_filter, 0, sizeof(def_filter));
3110         (void)rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
3111                                         ETH_ADDR_LEN);
3112         def_filter.vlan_tag = 0;
3113         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
3114                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
3115         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
3116         if (ret != I40E_SUCCESS) {
3117                 struct i40e_mac_filter *f;
3118                 struct ether_addr *mac;
3119
3120                 PMD_DRV_LOG(WARNING, "Cannot remove the default "
3121                             "macvlan filter");
3122                 /* It needs to add the permanent mac into mac list */
3123                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
3124                 if (f == NULL) {
3125                         PMD_DRV_LOG(ERR, "failed to allocate memory");
3126                         return I40E_ERR_NO_MEMORY;
3127                 }
3128                 mac = &f->mac_info.mac_addr;
3129                 (void)rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
3130                                 ETH_ADDR_LEN);
3131                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3132                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
3133                 vsi->mac_num++;
3134
3135                 return ret;
3136         }
3137         (void)rte_memcpy(&filter.mac_addr,
3138                 (struct ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
3139         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3140         return i40e_vsi_add_mac(vsi, &filter);
3141 }
3142
3143 static int
3144 i40e_vsi_dump_bw_config(struct i40e_vsi *vsi)
3145 {
3146         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
3147         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
3148         struct i40e_hw *hw = &vsi->adapter->hw;
3149         i40e_status ret;
3150         int i;
3151
3152         memset(&bw_config, 0, sizeof(bw_config));
3153         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
3154         if (ret != I40E_SUCCESS) {
3155                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
3156                             hw->aq.asq_last_status);
3157                 return ret;
3158         }
3159
3160         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
3161         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
3162                                         &ets_sla_config, NULL);
3163         if (ret != I40E_SUCCESS) {
3164                 PMD_DRV_LOG(ERR, "VSI failed to get TC bandwdith "
3165                             "configuration %u", hw->aq.asq_last_status);
3166                 return ret;
3167         }
3168
3169         /* Not store the info yet, just print out */
3170         PMD_DRV_LOG(INFO, "VSI bw limit:%u", bw_config.port_bw_limit);
3171         PMD_DRV_LOG(INFO, "VSI max_bw:%u", bw_config.max_bw);
3172         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
3173                 PMD_DRV_LOG(INFO, "\tVSI TC%u:share credits %u", i,
3174                             ets_sla_config.share_credits[i]);
3175                 PMD_DRV_LOG(INFO, "\tVSI TC%u:credits %u", i,
3176                             rte_le_to_cpu_16(ets_sla_config.credits[i]));
3177                 PMD_DRV_LOG(INFO, "\tVSI TC%u: max credits: %u", i,
3178                             rte_le_to_cpu_16(ets_sla_config.credits[i / 4]) >>
3179                             (i * 4));
3180         }
3181
3182         return 0;
3183 }
3184
3185 /* Setup a VSI */
3186 struct i40e_vsi *
3187 i40e_vsi_setup(struct i40e_pf *pf,
3188                enum i40e_vsi_type type,
3189                struct i40e_vsi *uplink_vsi,
3190                uint16_t user_param)
3191 {
3192         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3193         struct i40e_vsi *vsi;
3194         struct i40e_mac_filter_info filter;
3195         int ret;
3196         struct i40e_vsi_context ctxt;
3197         struct ether_addr broadcast =
3198                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
3199
3200         if (type != I40E_VSI_MAIN && uplink_vsi == NULL) {
3201                 PMD_DRV_LOG(ERR, "VSI setup failed, "
3202                             "VSI link shouldn't be NULL");
3203                 return NULL;
3204         }
3205
3206         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
3207                 PMD_DRV_LOG(ERR, "VSI setup failed, MAIN VSI "
3208                             "uplink VSI should be NULL");
3209                 return NULL;
3210         }
3211
3212         /* If uplink vsi didn't setup VEB, create one first */
3213         if (type != I40E_VSI_MAIN && uplink_vsi->veb == NULL) {
3214                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
3215
3216                 if (NULL == uplink_vsi->veb) {
3217                         PMD_DRV_LOG(ERR, "VEB setup failed");
3218                         return NULL;
3219                 }
3220         }
3221
3222         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
3223         if (!vsi) {
3224                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
3225                 return NULL;
3226         }
3227         TAILQ_INIT(&vsi->mac_list);
3228         vsi->type = type;
3229         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
3230         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
3231         vsi->parent_vsi = uplink_vsi;
3232         vsi->user_param = user_param;
3233         /* Allocate queues */
3234         switch (vsi->type) {
3235         case I40E_VSI_MAIN  :
3236                 vsi->nb_qps = pf->lan_nb_qps;
3237                 break;
3238         case I40E_VSI_SRIOV :
3239                 vsi->nb_qps = pf->vf_nb_qps;
3240                 break;
3241         case I40E_VSI_VMDQ2:
3242                 vsi->nb_qps = pf->vmdq_nb_qps;
3243                 break;
3244         case I40E_VSI_FDIR:
3245                 vsi->nb_qps = pf->fdir_nb_qps;
3246                 break;
3247         default:
3248                 goto fail_mem;
3249         }
3250         /*
3251          * The filter status descriptor is reported in rx queue 0,
3252          * while the tx queue for fdir filter programming has no
3253          * such constraints, can be non-zero queues.
3254          * To simplify it, choose FDIR vsi use queue 0 pair.
3255          * To make sure it will use queue 0 pair, queue allocation
3256          * need be done before this function is called
3257          */
3258         if (type != I40E_VSI_FDIR) {
3259                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
3260                         if (ret < 0) {
3261                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
3262                                                 vsi->seid, ret);
3263                                 goto fail_mem;
3264                         }
3265                         vsi->base_queue = ret;
3266         } else
3267                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
3268
3269         /* VF has MSIX interrupt in VF range, don't allocate here */
3270         if (type != I40E_VSI_SRIOV) {
3271                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
3272                 if (ret < 0) {
3273                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
3274                         goto fail_queue_alloc;
3275                 }
3276                 vsi->msix_intr = ret;
3277         } else
3278                 vsi->msix_intr = 0;
3279         /* Add VSI */
3280         if (type == I40E_VSI_MAIN) {
3281                 /* For main VSI, no need to add since it's default one */
3282                 vsi->uplink_seid = pf->mac_seid;
3283                 vsi->seid = pf->main_vsi_seid;
3284                 /* Bind queues with specific MSIX interrupt */
3285                 /**
3286                  * Needs 2 interrupt at least, one for misc cause which will
3287                  * enabled from OS side, Another for queues binding the
3288                  * interrupt from device side only.
3289                  */
3290
3291                 /* Get default VSI parameters from hardware */
3292                 memset(&ctxt, 0, sizeof(ctxt));
3293                 ctxt.seid = vsi->seid;
3294                 ctxt.pf_num = hw->pf_id;
3295                 ctxt.uplink_seid = vsi->uplink_seid;
3296                 ctxt.vf_num = 0;
3297                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
3298                 if (ret != I40E_SUCCESS) {
3299                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
3300                         goto fail_msix_alloc;
3301                 }
3302                 (void)rte_memcpy(&vsi->info, &ctxt.info,
3303                         sizeof(struct i40e_aqc_vsi_properties_data));
3304                 vsi->vsi_id = ctxt.vsi_number;
3305                 vsi->info.valid_sections = 0;
3306
3307                 /* Configure tc, enabled TC0 only */
3308                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
3309                         I40E_SUCCESS) {
3310                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
3311                         goto fail_msix_alloc;
3312                 }
3313
3314                 /* TC, queue mapping */
3315                 memset(&ctxt, 0, sizeof(ctxt));
3316                 vsi->info.valid_sections |=
3317                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3318                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
3319                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3320                 (void)rte_memcpy(&ctxt.info, &vsi->info,
3321                         sizeof(struct i40e_aqc_vsi_properties_data));
3322                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3323                                                 I40E_DEFAULT_TCMAP);
3324                 if (ret != I40E_SUCCESS) {
3325                         PMD_DRV_LOG(ERR, "Failed to configure "
3326                                     "TC queue mapping");
3327                         goto fail_msix_alloc;
3328                 }
3329                 ctxt.seid = vsi->seid;
3330                 ctxt.pf_num = hw->pf_id;
3331                 ctxt.uplink_seid = vsi->uplink_seid;
3332                 ctxt.vf_num = 0;
3333
3334                 /* Update VSI parameters */
3335                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3336                 if (ret != I40E_SUCCESS) {
3337                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
3338                         goto fail_msix_alloc;
3339                 }
3340
3341                 (void)rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
3342                                                 sizeof(vsi->info.tc_mapping));
3343                 (void)rte_memcpy(&vsi->info.queue_mapping,
3344                                 &ctxt.info.queue_mapping,
3345                         sizeof(vsi->info.queue_mapping));
3346                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
3347                 vsi->info.valid_sections = 0;
3348
3349                 (void)rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
3350                                 ETH_ADDR_LEN);
3351
3352                 /**
3353                  * Updating default filter settings are necessary to prevent
3354                  * reception of tagged packets.
3355                  * Some old firmware configurations load a default macvlan
3356                  * filter which accepts both tagged and untagged packets.
3357                  * The updating is to use a normal filter instead if needed.
3358                  * For NVM 4.2.2 or after, the updating is not needed anymore.
3359                  * The firmware with correct configurations load the default
3360                  * macvlan filter which is expected and cannot be removed.
3361                  */
3362                 i40e_update_default_filter_setting(vsi);
3363                 i40e_config_qinq(hw, vsi);
3364         } else if (type == I40E_VSI_SRIOV) {
3365                 memset(&ctxt, 0, sizeof(ctxt));
3366                 /**
3367                  * For other VSI, the uplink_seid equals to uplink VSI's
3368                  * uplink_seid since they share same VEB
3369                  */
3370                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3371                 ctxt.pf_num = hw->pf_id;
3372                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
3373                 ctxt.uplink_seid = vsi->uplink_seid;
3374                 ctxt.connection_type = 0x1;
3375                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
3376
3377                 /**
3378                  * Do not configure switch ID to enable VEB switch by
3379                  * I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB. Because in Fortville,
3380                  * if the source mac address of packet sent from VF is not
3381                  * listed in the VEB's mac table, the VEB will switch the
3382                  * packet back to the VF. Need to enable it when HW issue
3383                  * is fixed.
3384                  */
3385
3386                 /* Configure port/vlan */
3387                 ctxt.info.valid_sections |=
3388                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3389                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3390                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3391                                                 I40E_DEFAULT_TCMAP);
3392                 if (ret != I40E_SUCCESS) {
3393                         PMD_DRV_LOG(ERR, "Failed to configure "
3394                                     "TC queue mapping");
3395                         goto fail_msix_alloc;
3396                 }
3397                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3398                 ctxt.info.valid_sections |=
3399                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3400                 /**
3401                  * Since VSI is not created yet, only configure parameter,
3402                  * will add vsi below.
3403                  */
3404
3405                 i40e_config_qinq(hw, vsi);
3406         } else if (type == I40E_VSI_VMDQ2) {
3407                 memset(&ctxt, 0, sizeof(ctxt));
3408                 /*
3409                  * For other VSI, the uplink_seid equals to uplink VSI's
3410                  * uplink_seid since they share same VEB
3411                  */
3412                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3413                 ctxt.pf_num = hw->pf_id;
3414                 ctxt.vf_num = 0;
3415                 ctxt.uplink_seid = vsi->uplink_seid;
3416                 ctxt.connection_type = 0x1;
3417                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
3418
3419                 ctxt.info.valid_sections |=
3420                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
3421                 /* user_param carries flag to enable loop back */
3422                 if (user_param) {
3423                         ctxt.info.switch_id =
3424                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
3425                         ctxt.info.switch_id |=
3426                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
3427                 }
3428
3429                 /* Configure port/vlan */
3430                 ctxt.info.valid_sections |=
3431                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3432                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
3433                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3434                                                 I40E_DEFAULT_TCMAP);
3435                 if (ret != I40E_SUCCESS) {
3436                         PMD_DRV_LOG(ERR, "Failed to configure "
3437                                         "TC queue mapping");
3438                         goto fail_msix_alloc;
3439                 }
3440                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3441                 ctxt.info.valid_sections |=
3442                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3443         } else if (type == I40E_VSI_FDIR) {
3444                 memset(&ctxt, 0, sizeof(ctxt));
3445                 vsi->uplink_seid = uplink_vsi->uplink_seid;
3446                 ctxt.pf_num = hw->pf_id;
3447                 ctxt.vf_num = 0;
3448                 ctxt.uplink_seid = vsi->uplink_seid;
3449                 ctxt.connection_type = 0x1;     /* regular data port */
3450                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
3451                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
3452                                                 I40E_DEFAULT_TCMAP);
3453                 if (ret != I40E_SUCCESS) {
3454                         PMD_DRV_LOG(ERR, "Failed to configure "
3455                                         "TC queue mapping.");
3456                         goto fail_msix_alloc;
3457                 }
3458                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
3459                 ctxt.info.valid_sections |=
3460                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
3461         } else {
3462                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
3463                 goto fail_msix_alloc;
3464         }
3465
3466         if (vsi->type != I40E_VSI_MAIN) {
3467                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
3468                 if (ret != I40E_SUCCESS) {
3469                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
3470                                     hw->aq.asq_last_status);
3471                         goto fail_msix_alloc;
3472                 }
3473                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
3474                 vsi->info.valid_sections = 0;
3475                 vsi->seid = ctxt.seid;
3476                 vsi->vsi_id = ctxt.vsi_number;
3477                 vsi->sib_vsi_list.vsi = vsi;
3478                 TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
3479                                 &vsi->sib_vsi_list, list);
3480         }
3481
3482         /* MAC/VLAN configuration */
3483         (void)rte_memcpy(&filter.mac_addr, &broadcast, ETHER_ADDR_LEN);
3484         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
3485
3486         ret = i40e_vsi_add_mac(vsi, &filter);
3487         if (ret != I40E_SUCCESS) {
3488                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
3489                 goto fail_msix_alloc;
3490         }
3491
3492         /* Get VSI BW information */
3493         i40e_vsi_dump_bw_config(vsi);
3494         return vsi;
3495 fail_msix_alloc:
3496         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
3497 fail_queue_alloc:
3498         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
3499 fail_mem:
3500         rte_free(vsi);
3501         return NULL;
3502 }
3503
3504 /* Configure vlan stripping on or off */
3505 int
3506 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
3507 {
3508         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3509         struct i40e_vsi_context ctxt;
3510         uint8_t vlan_flags;
3511         int ret = I40E_SUCCESS;
3512
3513         /* Check if it has been already on or off */
3514         if (vsi->info.valid_sections &
3515                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
3516                 if (on) {
3517                         if ((vsi->info.port_vlan_flags &
3518                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
3519                                 return 0; /* already on */
3520                 } else {
3521                         if ((vsi->info.port_vlan_flags &
3522                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
3523                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
3524                                 return 0; /* already off */
3525                 }
3526         }
3527
3528         if (on)
3529                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
3530         else
3531                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
3532         vsi->info.valid_sections =
3533                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
3534         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
3535         vsi->info.port_vlan_flags |= vlan_flags;
3536         ctxt.seid = vsi->seid;
3537         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3538         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
3539         if (ret)
3540                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
3541                             on ? "enable" : "disable");
3542
3543         return ret;
3544 }
3545
3546 static int
3547 i40e_dev_init_vlan(struct rte_eth_dev *dev)
3548 {
3549         struct rte_eth_dev_data *data = dev->data;
3550         int ret;
3551
3552         /* Apply vlan offload setting */
3553         i40e_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
3554
3555         /* Apply double-vlan setting, not implemented yet */
3556
3557         /* Apply pvid setting */
3558         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
3559                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
3560         if (ret)
3561                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
3562
3563         return ret;
3564 }
3565
3566 static int
3567 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
3568 {
3569         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
3570
3571         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
3572 }
3573
3574 static int
3575 i40e_update_flow_control(struct i40e_hw *hw)
3576 {
3577 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
3578         struct i40e_link_status link_status;
3579         uint32_t rxfc = 0, txfc = 0, reg;
3580         uint8_t an_info;
3581         int ret;
3582
3583         memset(&link_status, 0, sizeof(link_status));
3584         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
3585         if (ret != I40E_SUCCESS) {
3586                 PMD_DRV_LOG(ERR, "Failed to get link status information");
3587                 goto write_reg; /* Disable flow control */
3588         }
3589
3590         an_info = hw->phy.link_info.an_info;
3591         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
3592                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
3593                 ret = I40E_ERR_NOT_READY;
3594                 goto write_reg; /* Disable flow control */
3595         }
3596         /**
3597          * If link auto negotiation is enabled, flow control needs to
3598          * be configured according to it
3599          */
3600         switch (an_info & I40E_LINK_PAUSE_RXTX) {
3601         case I40E_LINK_PAUSE_RXTX:
3602                 rxfc = 1;
3603                 txfc = 1;
3604                 hw->fc.current_mode = I40E_FC_FULL;
3605                 break;
3606         case I40E_AQ_LINK_PAUSE_RX:
3607                 rxfc = 1;
3608                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
3609                 break;
3610         case I40E_AQ_LINK_PAUSE_TX:
3611                 txfc = 1;
3612                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
3613                 break;
3614         default:
3615                 hw->fc.current_mode = I40E_FC_NONE;
3616                 break;
3617         }
3618
3619 write_reg:
3620         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
3621                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
3622         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3623         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
3624         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
3625         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
3626
3627         return ret;
3628 }
3629
3630 /* PF setup */
3631 static int
3632 i40e_pf_setup(struct i40e_pf *pf)
3633 {
3634         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3635         struct i40e_filter_control_settings settings;
3636         struct i40e_vsi *vsi;
3637         int ret;
3638
3639         /* Clear all stats counters */
3640         pf->offset_loaded = FALSE;
3641         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
3642         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
3643
3644         ret = i40e_pf_get_switch_config(pf);
3645         if (ret != I40E_SUCCESS) {
3646                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
3647                 return ret;
3648         }
3649         if (pf->flags & I40E_FLAG_FDIR) {
3650                 /* make queue allocated first, let FDIR use queue pair 0*/
3651                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
3652                 if (ret != I40E_FDIR_QUEUE_ID) {
3653                         PMD_DRV_LOG(ERR, "queue allocation fails for FDIR :"
3654                                     " ret =%d", ret);
3655                         pf->flags &= ~I40E_FLAG_FDIR;
3656                 }
3657         }
3658         /*  main VSI setup */
3659         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
3660         if (!vsi) {
3661                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
3662                 return I40E_ERR_NOT_READY;
3663         }
3664         pf->main_vsi = vsi;
3665
3666         /* Configure filter control */
3667         memset(&settings, 0, sizeof(settings));
3668         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
3669                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
3670         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
3671                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
3672         else {
3673                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported\n",
3674                                                 hw->func_caps.rss_table_size);
3675                 return I40E_ERR_PARAM;
3676         }
3677         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table "
3678                         "size: %u\n", hw->func_caps.rss_table_size);
3679         pf->hash_lut_size = hw->func_caps.rss_table_size;
3680
3681         /* Enable ethtype and macvlan filters */
3682         settings.enable_ethtype = TRUE;
3683         settings.enable_macvlan = TRUE;
3684         ret = i40e_set_filter_control(hw, &settings);
3685         if (ret)
3686                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
3687                                                                 ret);
3688
3689         /* Update flow control according to the auto negotiation */
3690         i40e_update_flow_control(hw);
3691
3692         return I40E_SUCCESS;
3693 }
3694
3695 int
3696 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3697 {
3698         uint32_t reg;
3699         uint16_t j;
3700
3701         /**
3702          * Set or clear TX Queue Disable flags,
3703          * which is required by hardware.
3704          */
3705         i40e_pre_tx_queue_cfg(hw, q_idx, on);
3706         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
3707
3708         /* Wait until the request is finished */
3709         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3710                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3711                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3712                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3713                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
3714                                                         & 0x1))) {
3715                         break;
3716                 }
3717         }
3718         if (on) {
3719                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
3720                         return I40E_SUCCESS; /* already on, skip next steps */
3721
3722                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
3723                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
3724         } else {
3725                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3726                         return I40E_SUCCESS; /* already off, skip next steps */
3727                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
3728         }
3729         /* Write the register */
3730         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
3731         /* Check the result */
3732         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3733                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3734                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
3735                 if (on) {
3736                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3737                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
3738                                 break;
3739                 } else {
3740                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
3741                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
3742                                 break;
3743                 }
3744         }
3745         /* Check if it is timeout */
3746         if (j >= I40E_CHK_Q_ENA_COUNT) {
3747                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
3748                             (on ? "enable" : "disable"), q_idx);
3749                 return I40E_ERR_TIMEOUT;
3750         }
3751
3752         return I40E_SUCCESS;
3753 }
3754
3755 /* Swith on or off the tx queues */
3756 static int
3757 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
3758 {
3759         struct rte_eth_dev_data *dev_data = pf->dev_data;
3760         struct i40e_tx_queue *txq;
3761         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3762         uint16_t i;
3763         int ret;
3764
3765         for (i = 0; i < dev_data->nb_tx_queues; i++) {
3766                 txq = dev_data->tx_queues[i];
3767                 /* Don't operate the queue if not configured or
3768                  * if starting only per queue */
3769                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
3770                         continue;
3771                 if (on)
3772                         ret = i40e_dev_tx_queue_start(dev, i);
3773                 else
3774                         ret = i40e_dev_tx_queue_stop(dev, i);
3775                 if ( ret != I40E_SUCCESS)
3776                         return ret;
3777         }
3778
3779         return I40E_SUCCESS;
3780 }
3781
3782 int
3783 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
3784 {
3785         uint32_t reg;
3786         uint16_t j;
3787
3788         /* Wait until the request is finished */
3789         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3790                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3791                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3792                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
3793                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
3794                         break;
3795         }
3796
3797         if (on) {
3798                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
3799                         return I40E_SUCCESS; /* Already on, skip next steps */
3800                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
3801         } else {
3802                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3803                         return I40E_SUCCESS; /* Already off, skip next steps */
3804                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
3805         }
3806
3807         /* Write the register */
3808         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
3809         /* Check the result */
3810         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
3811                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
3812                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
3813                 if (on) {
3814                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3815                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
3816                                 break;
3817                 } else {
3818                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
3819                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
3820                                 break;
3821                 }
3822         }
3823
3824         /* Check if it is timeout */
3825         if (j >= I40E_CHK_Q_ENA_COUNT) {
3826                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
3827                             (on ? "enable" : "disable"), q_idx);
3828                 return I40E_ERR_TIMEOUT;
3829         }
3830
3831         return I40E_SUCCESS;
3832 }
3833 /* Switch on or off the rx queues */
3834 static int
3835 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
3836 {
3837         struct rte_eth_dev_data *dev_data = pf->dev_data;
3838         struct i40e_rx_queue *rxq;
3839         struct rte_eth_dev *dev = pf->adapter->eth_dev;
3840         uint16_t i;
3841         int ret;
3842
3843         for (i = 0; i < dev_data->nb_rx_queues; i++) {
3844                 rxq = dev_data->rx_queues[i];
3845                 /* Don't operate the queue if not configured or
3846                  * if starting only per queue */
3847                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
3848                         continue;
3849                 if (on)
3850                         ret = i40e_dev_rx_queue_start(dev, i);
3851                 else
3852                         ret = i40e_dev_rx_queue_stop(dev, i);
3853                 if (ret != I40E_SUCCESS)
3854                         return ret;
3855         }
3856
3857         return I40E_SUCCESS;
3858 }
3859
3860 /* Switch on or off all the rx/tx queues */
3861 int
3862 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
3863 {
3864         int ret;
3865
3866         if (on) {
3867                 /* enable rx queues before enabling tx queues */
3868                 ret = i40e_dev_switch_rx_queues(pf, on);
3869                 if (ret) {
3870                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
3871                         return ret;
3872                 }
3873                 ret = i40e_dev_switch_tx_queues(pf, on);
3874         } else {
3875                 /* Stop tx queues before stopping rx queues */
3876                 ret = i40e_dev_switch_tx_queues(pf, on);
3877                 if (ret) {
3878                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
3879                         return ret;
3880                 }
3881                 ret = i40e_dev_switch_rx_queues(pf, on);
3882         }
3883
3884         return ret;
3885 }
3886
3887 /* Initialize VSI for TX */
3888 static int
3889 i40e_dev_tx_init(struct i40e_pf *pf)
3890 {
3891         struct rte_eth_dev_data *data = pf->dev_data;
3892         uint16_t i;
3893         uint32_t ret = I40E_SUCCESS;
3894         struct i40e_tx_queue *txq;
3895
3896         for (i = 0; i < data->nb_tx_queues; i++) {
3897                 txq = data->tx_queues[i];
3898                 if (!txq || !txq->q_set)
3899                         continue;
3900                 ret = i40e_tx_queue_init(txq);
3901                 if (ret != I40E_SUCCESS)
3902                         break;
3903         }
3904
3905         return ret;
3906 }
3907
3908 /* Initialize VSI for RX */
3909 static int
3910 i40e_dev_rx_init(struct i40e_pf *pf)
3911 {
3912         struct rte_eth_dev_data *data = pf->dev_data;
3913         int ret = I40E_SUCCESS;
3914         uint16_t i;
3915         struct i40e_rx_queue *rxq;
3916
3917         i40e_pf_config_mq_rx(pf);
3918         for (i = 0; i < data->nb_rx_queues; i++) {
3919                 rxq = data->rx_queues[i];
3920                 if (!rxq || !rxq->q_set)
3921                         continue;
3922
3923                 ret = i40e_rx_queue_init(rxq);
3924                 if (ret != I40E_SUCCESS) {
3925                         PMD_DRV_LOG(ERR, "Failed to do RX queue "
3926                                     "initialization");
3927                         break;
3928                 }
3929         }
3930
3931         return ret;
3932 }
3933
3934 static int
3935 i40e_dev_rxtx_init(struct i40e_pf *pf)
3936 {
3937         int err;
3938
3939         err = i40e_dev_tx_init(pf);
3940         if (err) {
3941                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
3942                 return err;
3943         }
3944         err = i40e_dev_rx_init(pf);
3945         if (err) {
3946                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
3947                 return err;
3948         }
3949
3950         return err;
3951 }
3952
3953 static int
3954 i40e_vmdq_setup(struct rte_eth_dev *dev)
3955 {
3956         struct rte_eth_conf *conf = &dev->data->dev_conf;
3957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3958         int i, err, conf_vsis, j, loop;
3959         struct i40e_vsi *vsi;
3960         struct i40e_vmdq_info *vmdq_info;
3961         struct rte_eth_vmdq_rx_conf *vmdq_conf;
3962         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
3963
3964         /*
3965          * Disable interrupt to avoid message from VF. Furthermore, it will
3966          * avoid race condition in VSI creation/destroy.
3967          */
3968         i40e_pf_disable_irq0(hw);
3969
3970         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
3971                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
3972                 return -ENOTSUP;
3973         }
3974
3975         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
3976         if (conf_vsis > pf->max_nb_vmdq_vsi) {
3977                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
3978                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
3979                         pf->max_nb_vmdq_vsi);
3980                 return -ENOTSUP;
3981         }
3982
3983         if (pf->vmdq != NULL) {
3984                 PMD_INIT_LOG(INFO, "VMDQ already configured");
3985                 return 0;
3986         }
3987
3988         pf->vmdq = rte_zmalloc("vmdq_info_struct",
3989                                 sizeof(*vmdq_info) * conf_vsis, 0);
3990
3991         if (pf->vmdq == NULL) {
3992                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
3993                 return -ENOMEM;
3994         }
3995
3996         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
3997
3998         /* Create VMDQ VSI */
3999         for (i = 0; i < conf_vsis; i++) {
4000                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
4001                                 vmdq_conf->enable_loop_back);
4002                 if (vsi == NULL) {
4003                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
4004                         err = -1;
4005                         goto err_vsi_setup;
4006                 }
4007                 vmdq_info = &pf->vmdq[i];
4008                 vmdq_info->pf = pf;
4009                 vmdq_info->vsi = vsi;
4010         }
4011         pf->nb_cfg_vmdq_vsi = conf_vsis;
4012
4013         /* Configure Vlan */
4014         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
4015         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
4016                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
4017                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
4018                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
4019                                         vmdq_conf->pool_map[i].vlan_id, j);
4020
4021                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
4022                                                 vmdq_conf->pool_map[i].vlan_id);
4023                                 if (err) {
4024                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
4025                                         err = -1;
4026                                         goto err_vsi_setup;
4027                                 }
4028                         }
4029                 }
4030         }
4031
4032         i40e_pf_enable_irq0(hw);
4033
4034         return 0;
4035
4036 err_vsi_setup:
4037         for (i = 0; i < conf_vsis; i++)
4038                 if (pf->vmdq[i].vsi == NULL)
4039                         break;
4040                 else
4041                         i40e_vsi_release(pf->vmdq[i].vsi);
4042
4043         rte_free(pf->vmdq);
4044         pf->vmdq = NULL;
4045         i40e_pf_enable_irq0(hw);
4046         return err;
4047 }
4048
4049 static void
4050 i40e_stat_update_32(struct i40e_hw *hw,
4051                    uint32_t reg,
4052                    bool offset_loaded,
4053                    uint64_t *offset,
4054                    uint64_t *stat)
4055 {
4056         uint64_t new_data;
4057
4058         new_data = (uint64_t)I40E_READ_REG(hw, reg);
4059         if (!offset_loaded)
4060                 *offset = new_data;
4061
4062         if (new_data >= *offset)
4063                 *stat = (uint64_t)(new_data - *offset);
4064         else
4065                 *stat = (uint64_t)((new_data +
4066                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
4067 }
4068
4069 static void
4070 i40e_stat_update_48(struct i40e_hw *hw,
4071                    uint32_t hireg,
4072                    uint32_t loreg,
4073                    bool offset_loaded,
4074                    uint64_t *offset,
4075                    uint64_t *stat)
4076 {
4077         uint64_t new_data;
4078
4079         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
4080         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
4081                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
4082
4083         if (!offset_loaded)
4084                 *offset = new_data;
4085
4086         if (new_data >= *offset)
4087                 *stat = new_data - *offset;
4088         else
4089                 *stat = (uint64_t)((new_data +
4090                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
4091
4092         *stat &= I40E_48_BIT_MASK;
4093 }
4094
4095 /* Disable IRQ0 */
4096 void
4097 i40e_pf_disable_irq0(struct i40e_hw *hw)
4098 {
4099         /* Disable all interrupt types */
4100         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0, 0);
4101         I40E_WRITE_FLUSH(hw);
4102 }
4103
4104 /* Enable IRQ0 */
4105 void
4106 i40e_pf_enable_irq0(struct i40e_hw *hw)
4107 {
4108         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
4109                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
4110                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
4111                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
4112         I40E_WRITE_FLUSH(hw);
4113 }
4114
4115 static void
4116 i40e_pf_config_irq0(struct i40e_hw *hw)
4117 {
4118         /* read pending request and disable first */
4119         i40e_pf_disable_irq0(hw);
4120         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
4121         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
4122                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
4123
4124         /* Link no queues with irq0 */
4125         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
4126                 I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
4127 }
4128
4129 static void
4130 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
4131 {
4132         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4133         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4134         int i;
4135         uint16_t abs_vf_id;
4136         uint32_t index, offset, val;
4137
4138         if (!pf->vfs)
4139                 return;
4140         /**
4141          * Try to find which VF trigger a reset, use absolute VF id to access
4142          * since the reg is global register.
4143          */
4144         for (i = 0; i < pf->vf_num; i++) {
4145                 abs_vf_id = hw->func_caps.vf_base_id + i;
4146                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
4147                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
4148                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
4149                 /* VFR event occured */
4150                 if (val & (0x1 << offset)) {
4151                         int ret;
4152
4153                         /* Clear the event first */
4154                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
4155                                                         (0x1 << offset));
4156                         PMD_DRV_LOG(INFO, "VF %u reset occured", abs_vf_id);
4157                         /**
4158                          * Only notify a VF reset event occured,
4159                          * don't trigger another SW reset
4160                          */
4161                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
4162                         if (ret != I40E_SUCCESS)
4163                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
4164                 }
4165         }
4166 }
4167
4168 static void
4169 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
4170 {
4171         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4172         struct i40e_arq_event_info info;
4173         uint16_t pending, opcode;
4174         int ret;
4175
4176         info.buf_len = I40E_AQ_BUF_SZ;
4177         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
4178         if (!info.msg_buf) {
4179                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
4180                 return;
4181         }
4182
4183         pending = 1;
4184         while (pending) {
4185                 ret = i40e_clean_arq_element(hw, &info, &pending);
4186
4187                 if (ret != I40E_SUCCESS) {
4188                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ, "
4189                                     "aq_err: %u", hw->aq.asq_last_status);
4190                         break;
4191                 }
4192                 opcode = rte_le_to_cpu_16(info.desc.opcode);
4193
4194                 switch (opcode) {
4195                 case i40e_aqc_opc_send_msg_to_pf:
4196                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
4197                         i40e_pf_host_handle_vf_msg(dev,
4198                                         rte_le_to_cpu_16(info.desc.retval),
4199                                         rte_le_to_cpu_32(info.desc.cookie_high),
4200                                         rte_le_to_cpu_32(info.desc.cookie_low),
4201                                         info.msg_buf,
4202                                         info.msg_len);
4203                         break;
4204                 default:
4205                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
4206                                     opcode);
4207                         break;
4208                 }
4209         }
4210         rte_free(info.msg_buf);
4211 }
4212
4213 /*
4214  * Interrupt handler is registered as the alarm callback for handling LSC
4215  * interrupt in a definite of time, in order to wait the NIC into a stable
4216  * state. Currently it waits 1 sec in i40e for the link up interrupt, and
4217  * no need for link down interrupt.
4218  */
4219 static void
4220 i40e_dev_interrupt_delayed_handler(void *param)
4221 {
4222         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4223         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4224         uint32_t icr0;
4225
4226         /* read interrupt causes again */
4227         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4228
4229 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4230         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4231                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error\n");
4232         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4233                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected\n");
4234         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4235                 PMD_DRV_LOG(INFO, "ICR0: global reset requested\n");
4236         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4237                 PMD_DRV_LOG(INFO, "ICR0: PCI exception\n activated\n");
4238         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4239                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control "
4240                                                                 "state\n");
4241         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4242                 PMD_DRV_LOG(ERR, "ICR0: HMC error\n");
4243         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4244                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error\n");
4245 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4246
4247         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4248                 PMD_DRV_LOG(INFO, "INT:VF reset detected\n");
4249                 i40e_dev_handle_vfr_event(dev);
4250         }
4251         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4252                 PMD_DRV_LOG(INFO, "INT:ADMINQ event\n");
4253                 i40e_dev_handle_aq_msg(dev);
4254         }
4255
4256         /* handle the link up interrupt in an alarm callback */
4257         i40e_dev_link_update(dev, 0);
4258         _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_LSC);
4259
4260         i40e_pf_enable_irq0(hw);
4261         rte_intr_enable(&(dev->pci_dev->intr_handle));
4262 }
4263
4264 /**
4265  * Interrupt handler triggered by NIC  for handling
4266  * specific interrupt.
4267  *
4268  * @param handle
4269  *  Pointer to interrupt handle.
4270  * @param param
4271  *  The address of parameter (struct rte_eth_dev *) regsitered before.
4272  *
4273  * @return
4274  *  void
4275  */
4276 static void
4277 i40e_dev_interrupt_handler(__rte_unused struct rte_intr_handle *handle,
4278                            void *param)
4279 {
4280         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
4281         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4282         uint32_t icr0;
4283
4284         /* Disable interrupt */
4285         i40e_pf_disable_irq0(hw);
4286
4287         /* read out interrupt causes */
4288         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
4289
4290         /* No interrupt event indicated */
4291         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
4292                 PMD_DRV_LOG(INFO, "No interrupt event");
4293                 goto done;
4294         }
4295 #ifdef RTE_LIBRTE_I40E_DEBUG_DRIVER
4296         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
4297                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
4298         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
4299                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
4300         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
4301                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
4302         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
4303                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
4304         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
4305                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
4306         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
4307                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
4308         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
4309                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
4310 #endif /* RTE_LIBRTE_I40E_DEBUG_DRIVER */
4311
4312         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
4313                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
4314                 i40e_dev_handle_vfr_event(dev);
4315         }
4316         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
4317                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
4318                 i40e_dev_handle_aq_msg(dev);
4319         }
4320
4321         /* Link Status Change interrupt */
4322         if (icr0 & I40E_PFINT_ICR0_LINK_STAT_CHANGE_MASK) {
4323 #define I40E_US_PER_SECOND 1000000
4324                 struct rte_eth_link link;
4325
4326                 PMD_DRV_LOG(INFO, "ICR0: link status changed\n");
4327                 memset(&link, 0, sizeof(link));
4328                 rte_i40e_dev_atomic_read_link_status(dev, &link);
4329                 i40e_dev_link_update(dev, 0);
4330
4331                 /*
4332                  * For link up interrupt, it needs to wait 1 second to let the
4333                  * hardware be a stable state. Otherwise several consecutive
4334                  * interrupts can be observed.
4335                  * For link down interrupt, no need to wait.
4336                  */
4337                 if (!link.link_status && rte_eal_alarm_set(I40E_US_PER_SECOND,
4338                         i40e_dev_interrupt_delayed_handler, (void *)dev) >= 0)
4339                         return;
4340                 else
4341                         _rte_eth_dev_callback_process(dev,
4342                                 RTE_ETH_EVENT_INTR_LSC);
4343         }
4344
4345 done:
4346         /* Enable interrupt */
4347         i40e_pf_enable_irq0(hw);
4348         rte_intr_enable(&(dev->pci_dev->intr_handle));
4349 }
4350
4351 static int
4352 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
4353                          struct i40e_macvlan_filter *filter,
4354                          int total)
4355 {
4356         int ele_num, ele_buff_size;
4357         int num, actual_num, i;
4358         uint16_t flags;
4359         int ret = I40E_SUCCESS;
4360         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4361         struct i40e_aqc_add_macvlan_element_data *req_list;
4362
4363         if (filter == NULL  || total == 0)
4364                 return I40E_ERR_PARAM;
4365         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4366         ele_buff_size = hw->aq.asq_buf_size;
4367
4368         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
4369         if (req_list == NULL) {
4370                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4371                 return I40E_ERR_NO_MEMORY;
4372         }
4373
4374         num = 0;
4375         do {
4376                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4377                 memset(req_list, 0, ele_buff_size);
4378
4379                 for (i = 0; i < actual_num; i++) {
4380                         (void)rte_memcpy(req_list[i].mac_addr,
4381                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4382                         req_list[i].vlan_tag =
4383                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4384
4385                         switch (filter[num + i].filter_type) {
4386                         case RTE_MAC_PERFECT_MATCH:
4387                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
4388                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4389                                 break;
4390                         case RTE_MACVLAN_PERFECT_MATCH:
4391                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
4392                                 break;
4393                         case RTE_MAC_HASH_MATCH:
4394                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
4395                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
4396                                 break;
4397                         case RTE_MACVLAN_HASH_MATCH:
4398                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
4399                                 break;
4400                         default:
4401                                 PMD_DRV_LOG(ERR, "Invalid MAC match type\n");
4402                                 ret = I40E_ERR_PARAM;
4403                                 goto DONE;
4404                         }
4405
4406                         req_list[i].queue_number = 0;
4407
4408                         req_list[i].flags = rte_cpu_to_le_16(flags);
4409                 }
4410
4411                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
4412                                                 actual_num, NULL);
4413                 if (ret != I40E_SUCCESS) {
4414                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
4415                         goto DONE;
4416                 }
4417                 num += actual_num;
4418         } while (num < total);
4419
4420 DONE:
4421         rte_free(req_list);
4422         return ret;
4423 }
4424
4425 static int
4426 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
4427                             struct i40e_macvlan_filter *filter,
4428                             int total)
4429 {
4430         int ele_num, ele_buff_size;
4431         int num, actual_num, i;
4432         uint16_t flags;
4433         int ret = I40E_SUCCESS;
4434         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4435         struct i40e_aqc_remove_macvlan_element_data *req_list;
4436
4437         if (filter == NULL  || total == 0)
4438                 return I40E_ERR_PARAM;
4439
4440         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
4441         ele_buff_size = hw->aq.asq_buf_size;
4442
4443         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
4444         if (req_list == NULL) {
4445                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
4446                 return I40E_ERR_NO_MEMORY;
4447         }
4448
4449         num = 0;
4450         do {
4451                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
4452                 memset(req_list, 0, ele_buff_size);
4453
4454                 for (i = 0; i < actual_num; i++) {
4455                         (void)rte_memcpy(req_list[i].mac_addr,
4456                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
4457                         req_list[i].vlan_tag =
4458                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
4459
4460                         switch (filter[num + i].filter_type) {
4461                         case RTE_MAC_PERFECT_MATCH:
4462                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
4463                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4464                                 break;
4465                         case RTE_MACVLAN_PERFECT_MATCH:
4466                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
4467                                 break;
4468                         case RTE_MAC_HASH_MATCH:
4469                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
4470                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
4471                                 break;
4472                         case RTE_MACVLAN_HASH_MATCH:
4473                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
4474                                 break;
4475                         default:
4476                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type\n");
4477                                 ret = I40E_ERR_PARAM;
4478                                 goto DONE;
4479                         }
4480                         req_list[i].flags = rte_cpu_to_le_16(flags);
4481                 }
4482
4483                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
4484                                                 actual_num, NULL);
4485                 if (ret != I40E_SUCCESS) {
4486                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
4487                         goto DONE;
4488                 }
4489                 num += actual_num;
4490         } while (num < total);
4491
4492 DONE:
4493         rte_free(req_list);
4494         return ret;
4495 }
4496
4497 /* Find out specific MAC filter */
4498 static struct i40e_mac_filter *
4499 i40e_find_mac_filter(struct i40e_vsi *vsi,
4500                          struct ether_addr *macaddr)
4501 {
4502         struct i40e_mac_filter *f;
4503
4504         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4505                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
4506                         return f;
4507         }
4508
4509         return NULL;
4510 }
4511
4512 static bool
4513 i40e_find_vlan_filter(struct i40e_vsi *vsi,
4514                          uint16_t vlan_id)
4515 {
4516         uint32_t vid_idx, vid_bit;
4517
4518         if (vlan_id > ETH_VLAN_ID_MAX)
4519                 return 0;
4520
4521         vid_idx = I40E_VFTA_IDX(vlan_id);
4522         vid_bit = I40E_VFTA_BIT(vlan_id);
4523
4524         if (vsi->vfta[vid_idx] & vid_bit)
4525                 return 1;
4526         else
4527                 return 0;
4528 }
4529
4530 static void
4531 i40e_set_vlan_filter(struct i40e_vsi *vsi,
4532                          uint16_t vlan_id, bool on)
4533 {
4534         uint32_t vid_idx, vid_bit;
4535
4536         if (vlan_id > ETH_VLAN_ID_MAX)
4537                 return;
4538
4539         vid_idx = I40E_VFTA_IDX(vlan_id);
4540         vid_bit = I40E_VFTA_BIT(vlan_id);
4541
4542         if (on)
4543                 vsi->vfta[vid_idx] |= vid_bit;
4544         else
4545                 vsi->vfta[vid_idx] &= ~vid_bit;
4546 }
4547
4548 /**
4549  * Find all vlan options for specific mac addr,
4550  * return with actual vlan found.
4551  */
4552 static inline int
4553 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
4554                            struct i40e_macvlan_filter *mv_f,
4555                            int num, struct ether_addr *addr)
4556 {
4557         int i;
4558         uint32_t j, k;
4559
4560         /**
4561          * Not to use i40e_find_vlan_filter to decrease the loop time,
4562          * although the code looks complex.
4563           */
4564         if (num < vsi->vlan_num)
4565                 return I40E_ERR_PARAM;
4566
4567         i = 0;
4568         for (j = 0; j < I40E_VFTA_SIZE; j++) {
4569                 if (vsi->vfta[j]) {
4570                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
4571                                 if (vsi->vfta[j] & (1 << k)) {
4572                                         if (i > num - 1) {
4573                                                 PMD_DRV_LOG(ERR, "vlan number "
4574                                                             "not match");
4575                                                 return I40E_ERR_PARAM;
4576                                         }
4577                                         (void)rte_memcpy(&mv_f[i].macaddr,
4578                                                         addr, ETH_ADDR_LEN);
4579                                         mv_f[i].vlan_id =
4580                                                 j * I40E_UINT32_BIT_SIZE + k;
4581                                         i++;
4582                                 }
4583                         }
4584                 }
4585         }
4586         return I40E_SUCCESS;
4587 }
4588
4589 static inline int
4590 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
4591                            struct i40e_macvlan_filter *mv_f,
4592                            int num,
4593                            uint16_t vlan)
4594 {
4595         int i = 0;
4596         struct i40e_mac_filter *f;
4597
4598         if (num < vsi->mac_num)
4599                 return I40E_ERR_PARAM;
4600
4601         TAILQ_FOREACH(f, &vsi->mac_list, next) {
4602                 if (i > num - 1) {
4603                         PMD_DRV_LOG(ERR, "buffer number not match");
4604                         return I40E_ERR_PARAM;
4605                 }
4606                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4607                                 ETH_ADDR_LEN);
4608                 mv_f[i].vlan_id = vlan;
4609                 mv_f[i].filter_type = f->mac_info.filter_type;
4610                 i++;
4611         }
4612
4613         return I40E_SUCCESS;
4614 }
4615
4616 static int
4617 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
4618 {
4619         int i, num;
4620         struct i40e_mac_filter *f;
4621         struct i40e_macvlan_filter *mv_f;
4622         int ret = I40E_SUCCESS;
4623
4624         if (vsi == NULL || vsi->mac_num == 0)
4625                 return I40E_ERR_PARAM;
4626
4627         /* Case that no vlan is set */
4628         if (vsi->vlan_num == 0)
4629                 num = vsi->mac_num;
4630         else
4631                 num = vsi->mac_num * vsi->vlan_num;
4632
4633         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
4634         if (mv_f == NULL) {
4635                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4636                 return I40E_ERR_NO_MEMORY;
4637         }
4638
4639         i = 0;
4640         if (vsi->vlan_num == 0) {
4641                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4642                         (void)rte_memcpy(&mv_f[i].macaddr,
4643                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
4644                         mv_f[i].vlan_id = 0;
4645                         i++;
4646                 }
4647         } else {
4648                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
4649                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
4650                                         vsi->vlan_num, &f->mac_info.mac_addr);
4651                         if (ret != I40E_SUCCESS)
4652                                 goto DONE;
4653                         i += vsi->vlan_num;
4654                 }
4655         }
4656
4657         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
4658 DONE:
4659         rte_free(mv_f);
4660
4661         return ret;
4662 }
4663
4664 int
4665 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4666 {
4667         struct i40e_macvlan_filter *mv_f;
4668         int mac_num;
4669         int ret = I40E_SUCCESS;
4670
4671         if (!vsi || vlan > ETHER_MAX_VLAN_ID)
4672                 return I40E_ERR_PARAM;
4673
4674         /* If it's already set, just return */
4675         if (i40e_find_vlan_filter(vsi,vlan))
4676                 return I40E_SUCCESS;
4677
4678         mac_num = vsi->mac_num;
4679
4680         if (mac_num == 0) {
4681                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4682                 return I40E_ERR_PARAM;
4683         }
4684
4685         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4686
4687         if (mv_f == NULL) {
4688                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4689                 return I40E_ERR_NO_MEMORY;
4690         }
4691
4692         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4693
4694         if (ret != I40E_SUCCESS)
4695                 goto DONE;
4696
4697         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4698
4699         if (ret != I40E_SUCCESS)
4700                 goto DONE;
4701
4702         i40e_set_vlan_filter(vsi, vlan, 1);
4703
4704         vsi->vlan_num++;
4705         ret = I40E_SUCCESS;
4706 DONE:
4707         rte_free(mv_f);
4708         return ret;
4709 }
4710
4711 int
4712 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
4713 {
4714         struct i40e_macvlan_filter *mv_f;
4715         int mac_num;
4716         int ret = I40E_SUCCESS;
4717
4718         /**
4719          * Vlan 0 is the generic filter for untagged packets
4720          * and can't be removed.
4721          */
4722         if (!vsi || vlan == 0 || vlan > ETHER_MAX_VLAN_ID)
4723                 return I40E_ERR_PARAM;
4724
4725         /* If can't find it, just return */
4726         if (!i40e_find_vlan_filter(vsi, vlan))
4727                 return I40E_ERR_PARAM;
4728
4729         mac_num = vsi->mac_num;
4730
4731         if (mac_num == 0) {
4732                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
4733                 return I40E_ERR_PARAM;
4734         }
4735
4736         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
4737
4738         if (mv_f == NULL) {
4739                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4740                 return I40E_ERR_NO_MEMORY;
4741         }
4742
4743         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
4744
4745         if (ret != I40E_SUCCESS)
4746                 goto DONE;
4747
4748         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
4749
4750         if (ret != I40E_SUCCESS)
4751                 goto DONE;
4752
4753         /* This is last vlan to remove, replace all mac filter with vlan 0 */
4754         if (vsi->vlan_num == 1) {
4755                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
4756                 if (ret != I40E_SUCCESS)
4757                         goto DONE;
4758
4759                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
4760                 if (ret != I40E_SUCCESS)
4761                         goto DONE;
4762         }
4763
4764         i40e_set_vlan_filter(vsi, vlan, 0);
4765
4766         vsi->vlan_num--;
4767         ret = I40E_SUCCESS;
4768 DONE:
4769         rte_free(mv_f);
4770         return ret;
4771 }
4772
4773 int
4774 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
4775 {
4776         struct i40e_mac_filter *f;
4777         struct i40e_macvlan_filter *mv_f;
4778         int i, vlan_num = 0;
4779         int ret = I40E_SUCCESS;
4780
4781         /* If it's add and we've config it, return */
4782         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
4783         if (f != NULL)
4784                 return I40E_SUCCESS;
4785         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
4786                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
4787
4788                 /**
4789                  * If vlan_num is 0, that's the first time to add mac,
4790                  * set mask for vlan_id 0.
4791                  */
4792                 if (vsi->vlan_num == 0) {
4793                         i40e_set_vlan_filter(vsi, 0, 1);
4794                         vsi->vlan_num = 1;
4795                 }
4796                 vlan_num = vsi->vlan_num;
4797         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
4798                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
4799                 vlan_num = 1;
4800
4801         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4802         if (mv_f == NULL) {
4803                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4804                 return I40E_ERR_NO_MEMORY;
4805         }
4806
4807         for (i = 0; i < vlan_num; i++) {
4808                 mv_f[i].filter_type = mac_filter->filter_type;
4809                 (void)rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
4810                                 ETH_ADDR_LEN);
4811         }
4812
4813         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4814                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
4815                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
4816                                         &mac_filter->mac_addr);
4817                 if (ret != I40E_SUCCESS)
4818                         goto DONE;
4819         }
4820
4821         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
4822         if (ret != I40E_SUCCESS)
4823                 goto DONE;
4824
4825         /* Add the mac addr into mac list */
4826         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
4827         if (f == NULL) {
4828                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4829                 ret = I40E_ERR_NO_MEMORY;
4830                 goto DONE;
4831         }
4832         (void)rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
4833                         ETH_ADDR_LEN);
4834         f->mac_info.filter_type = mac_filter->filter_type;
4835         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
4836         vsi->mac_num++;
4837
4838         ret = I40E_SUCCESS;
4839 DONE:
4840         rte_free(mv_f);
4841
4842         return ret;
4843 }
4844
4845 int
4846 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr)
4847 {
4848         struct i40e_mac_filter *f;
4849         struct i40e_macvlan_filter *mv_f;
4850         int i, vlan_num;
4851         enum rte_mac_filter_type filter_type;
4852         int ret = I40E_SUCCESS;
4853
4854         /* Can't find it, return an error */
4855         f = i40e_find_mac_filter(vsi, addr);
4856         if (f == NULL)
4857                 return I40E_ERR_PARAM;
4858
4859         vlan_num = vsi->vlan_num;
4860         filter_type = f->mac_info.filter_type;
4861         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4862                 filter_type == RTE_MACVLAN_HASH_MATCH) {
4863                 if (vlan_num == 0) {
4864                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0\n");
4865                         return I40E_ERR_PARAM;
4866                 }
4867         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
4868                         filter_type == RTE_MAC_HASH_MATCH)
4869                 vlan_num = 1;
4870
4871         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
4872         if (mv_f == NULL) {
4873                 PMD_DRV_LOG(ERR, "failed to allocate memory");
4874                 return I40E_ERR_NO_MEMORY;
4875         }
4876
4877         for (i = 0; i < vlan_num; i++) {
4878                 mv_f[i].filter_type = filter_type;
4879                 (void)rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
4880                                 ETH_ADDR_LEN);
4881         }
4882         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
4883                         filter_type == RTE_MACVLAN_HASH_MATCH) {
4884                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
4885                 if (ret != I40E_SUCCESS)
4886                         goto DONE;
4887         }
4888
4889         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
4890         if (ret != I40E_SUCCESS)
4891                 goto DONE;
4892
4893         /* Remove the mac addr into mac list */
4894         TAILQ_REMOVE(&vsi->mac_list, f, next);
4895         rte_free(f);
4896         vsi->mac_num--;
4897
4898         ret = I40E_SUCCESS;
4899 DONE:
4900         rte_free(mv_f);
4901         return ret;
4902 }
4903
4904 /* Configure hash enable flags for RSS */
4905 uint64_t
4906 i40e_config_hena(uint64_t flags)
4907 {
4908         uint64_t hena = 0;
4909
4910         if (!flags)
4911                 return hena;
4912
4913         if (flags & ETH_RSS_FRAG_IPV4)
4914                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4;
4915         if (flags & ETH_RSS_NONFRAG_IPV4_TCP)
4916                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
4917         if (flags & ETH_RSS_NONFRAG_IPV4_UDP)
4918                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4919         if (flags & ETH_RSS_NONFRAG_IPV4_SCTP)
4920                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
4921         if (flags & ETH_RSS_NONFRAG_IPV4_OTHER)
4922                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
4923         if (flags & ETH_RSS_FRAG_IPV6)
4924                 hena |= 1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6;
4925         if (flags & ETH_RSS_NONFRAG_IPV6_TCP)
4926                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
4927         if (flags & ETH_RSS_NONFRAG_IPV6_UDP)
4928                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
4929         if (flags & ETH_RSS_NONFRAG_IPV6_SCTP)
4930                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
4931         if (flags & ETH_RSS_NONFRAG_IPV6_OTHER)
4932                 hena |= 1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
4933         if (flags & ETH_RSS_L2_PAYLOAD)
4934                 hena |= 1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD;
4935
4936         return hena;
4937 }
4938
4939 /* Parse the hash enable flags */
4940 uint64_t
4941 i40e_parse_hena(uint64_t flags)
4942 {
4943         uint64_t rss_hf = 0;
4944
4945         if (!flags)
4946                 return rss_hf;
4947         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4))
4948                 rss_hf |= ETH_RSS_FRAG_IPV4;
4949         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP))
4950                 rss_hf |= ETH_RSS_NONFRAG_IPV4_TCP;
4951         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP))
4952                 rss_hf |= ETH_RSS_NONFRAG_IPV4_UDP;
4953         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP))
4954                 rss_hf |= ETH_RSS_NONFRAG_IPV4_SCTP;
4955         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER))
4956                 rss_hf |= ETH_RSS_NONFRAG_IPV4_OTHER;
4957         if (flags & (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6))
4958                 rss_hf |= ETH_RSS_FRAG_IPV6;
4959         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP))
4960                 rss_hf |= ETH_RSS_NONFRAG_IPV6_TCP;
4961         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP))
4962                 rss_hf |= ETH_RSS_NONFRAG_IPV6_UDP;
4963         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP))
4964                 rss_hf |= ETH_RSS_NONFRAG_IPV6_SCTP;
4965         if (flags & (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER))
4966                 rss_hf |= ETH_RSS_NONFRAG_IPV6_OTHER;
4967         if (flags & (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
4968                 rss_hf |= ETH_RSS_L2_PAYLOAD;
4969
4970         return rss_hf;
4971 }
4972
4973 /* Disable RSS */
4974 static void
4975 i40e_pf_disable_rss(struct i40e_pf *pf)
4976 {
4977         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4978         uint64_t hena;
4979
4980         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
4981         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
4982         hena &= ~I40E_RSS_HENA_ALL;
4983         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
4984         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
4985         I40E_WRITE_FLUSH(hw);
4986 }
4987
4988 static int
4989 i40e_hw_rss_hash_set(struct i40e_hw *hw, struct rte_eth_rss_conf *rss_conf)
4990 {
4991         uint32_t *hash_key;
4992         uint8_t hash_key_len;
4993         uint64_t rss_hf;
4994         uint16_t i;
4995         uint64_t hena;
4996
4997         hash_key = (uint32_t *)(rss_conf->rss_key);
4998         hash_key_len = rss_conf->rss_key_len;
4999         if (hash_key != NULL && hash_key_len >=
5000                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5001                 /* Fill in RSS hash key */
5002                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5003                         I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i), hash_key[i]);
5004         }
5005
5006         rss_hf = rss_conf->rss_hf;
5007         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5008         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5009         hena &= ~I40E_RSS_HENA_ALL;
5010         hena |= i40e_config_hena(rss_hf);
5011         I40E_WRITE_REG(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
5012         I40E_WRITE_REG(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
5013         I40E_WRITE_FLUSH(hw);
5014
5015         return 0;
5016 }
5017
5018 static int
5019 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
5020                          struct rte_eth_rss_conf *rss_conf)
5021 {
5022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5023         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
5024         uint64_t hena;
5025
5026         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5027         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5028         if (!(hena & I40E_RSS_HENA_ALL)) { /* RSS disabled */
5029                 if (rss_hf != 0) /* Enable RSS */
5030                         return -EINVAL;
5031                 return 0; /* Nothing to do */
5032         }
5033         /* RSS enabled */
5034         if (rss_hf == 0) /* Disable RSS */
5035                 return -EINVAL;
5036
5037         return i40e_hw_rss_hash_set(hw, rss_conf);
5038 }
5039
5040 static int
5041 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
5042                            struct rte_eth_rss_conf *rss_conf)
5043 {
5044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5045         uint32_t *hash_key = (uint32_t *)(rss_conf->rss_key);
5046         uint64_t hena;
5047         uint16_t i;
5048
5049         if (hash_key != NULL) {
5050                 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
5051                         hash_key[i] = I40E_READ_REG(hw, I40E_PFQF_HKEY(i));
5052                 rss_conf->rss_key_len = i * sizeof(uint32_t);
5053         }
5054         hena = (uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(0));
5055         hena |= ((uint64_t)I40E_READ_REG(hw, I40E_PFQF_HENA(1))) << 32;
5056         rss_conf->rss_hf = i40e_parse_hena(hena);
5057
5058         return 0;
5059 }
5060
5061 static int
5062 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
5063 {
5064         switch (filter_type) {
5065         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
5066                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
5067                 break;
5068         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
5069                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
5070                 break;
5071         case RTE_TUNNEL_FILTER_IMAC_TENID:
5072                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
5073                 break;
5074         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
5075                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
5076                 break;
5077         case ETH_TUNNEL_FILTER_IMAC:
5078                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
5079                 break;
5080         default:
5081                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
5082                 return -EINVAL;
5083         }
5084
5085         return 0;
5086 }
5087
5088 static int
5089 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
5090                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
5091                         uint8_t add)
5092 {
5093         uint16_t ip_type;
5094         uint8_t tun_type = 0;
5095         int val, ret = 0;
5096         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5097         struct i40e_vsi *vsi = pf->main_vsi;
5098         struct i40e_aqc_add_remove_cloud_filters_element_data  *cld_filter;
5099         struct i40e_aqc_add_remove_cloud_filters_element_data  *pfilter;
5100
5101         cld_filter = rte_zmalloc("tunnel_filter",
5102                 sizeof(struct i40e_aqc_add_remove_cloud_filters_element_data),
5103                 0);
5104
5105         if (NULL == cld_filter) {
5106                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
5107                 return -EINVAL;
5108         }
5109         pfilter = cld_filter;
5110
5111         (void)rte_memcpy(&pfilter->outer_mac, tunnel_filter->outer_mac,
5112                         sizeof(struct ether_addr));
5113         (void)rte_memcpy(&pfilter->inner_mac, tunnel_filter->inner_mac,
5114                         sizeof(struct ether_addr));
5115
5116         pfilter->inner_vlan = tunnel_filter->inner_vlan;
5117         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
5118                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
5119                 (void)rte_memcpy(&pfilter->ipaddr.v4.data,
5120                                 &tunnel_filter->ip_addr,
5121                                 sizeof(pfilter->ipaddr.v4.data));
5122         } else {
5123                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
5124                 (void)rte_memcpy(&pfilter->ipaddr.v6.data,
5125                                 &tunnel_filter->ip_addr,
5126                                 sizeof(pfilter->ipaddr.v6.data));
5127         }
5128
5129         /* check tunneled type */
5130         switch (tunnel_filter->tunnel_type) {
5131         case RTE_TUNNEL_TYPE_VXLAN:
5132                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN;
5133                 break;
5134         case RTE_TUNNEL_TYPE_NVGRE:
5135                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
5136                 break;
5137         default:
5138                 /* Other tunnel types is not supported. */
5139                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
5140                 rte_free(cld_filter);
5141                 return -EINVAL;
5142         }
5143
5144         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
5145                                                 &pfilter->flags);
5146         if (val < 0) {
5147                 rte_free(cld_filter);
5148                 return -EINVAL;
5149         }
5150
5151         pfilter->flags |= I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE | ip_type |
5152                 (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
5153         pfilter->tenant_id = tunnel_filter->tenant_id;
5154         pfilter->queue_number = tunnel_filter->queue_id;
5155
5156         if (add)
5157                 ret = i40e_aq_add_cloud_filters(hw, vsi->seid, cld_filter, 1);
5158         else
5159                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
5160                                                 cld_filter, 1);
5161
5162         rte_free(cld_filter);
5163         return ret;
5164 }
5165
5166 static int
5167 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
5168 {
5169         uint8_t i;
5170
5171         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
5172                 if (pf->vxlan_ports[i] == port)
5173                         return i;
5174         }
5175
5176         return -1;
5177 }
5178
5179 static int
5180 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port)
5181 {
5182         int  idx, ret;
5183         uint8_t filter_idx;
5184         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5185
5186         idx = i40e_get_vxlan_port_idx(pf, port);
5187
5188         /* Check if port already exists */
5189         if (idx >= 0) {
5190                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
5191                 return -EINVAL;
5192         }
5193
5194         /* Now check if there is space to add the new port */
5195         idx = i40e_get_vxlan_port_idx(pf, 0);
5196         if (idx < 0) {
5197                 PMD_DRV_LOG(ERR, "Maximum number of UDP ports reached,"
5198                         "not adding port %d", port);
5199                 return -ENOSPC;
5200         }
5201
5202         ret =  i40e_aq_add_udp_tunnel(hw, port, I40E_AQC_TUNNEL_TYPE_VXLAN,
5203                                         &filter_idx, NULL);
5204         if (ret < 0) {
5205                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
5206                 return -1;
5207         }
5208
5209         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
5210                          port,  filter_idx);
5211
5212         /* New port: add it and mark its index in the bitmap */
5213         pf->vxlan_ports[idx] = port;
5214         pf->vxlan_bitmap |= (1 << idx);
5215
5216         if (!(pf->flags & I40E_FLAG_VXLAN))
5217                 pf->flags |= I40E_FLAG_VXLAN;
5218
5219         return 0;
5220 }
5221
5222 static int
5223 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
5224 {
5225         int idx;
5226         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5227
5228         if (!(pf->flags & I40E_FLAG_VXLAN)) {
5229                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
5230                 return -EINVAL;
5231         }
5232
5233         idx = i40e_get_vxlan_port_idx(pf, port);
5234
5235         if (idx < 0) {
5236                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
5237                 return -EINVAL;
5238         }
5239
5240         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
5241                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
5242                 return -1;
5243         }
5244
5245         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
5246                         port, idx);
5247
5248         pf->vxlan_ports[idx] = 0;
5249         pf->vxlan_bitmap &= ~(1 << idx);
5250
5251         if (!pf->vxlan_bitmap)
5252                 pf->flags &= ~I40E_FLAG_VXLAN;
5253
5254         return 0;
5255 }
5256
5257 /* Add UDP tunneling port */
5258 static int
5259 i40e_dev_udp_tunnel_add(struct rte_eth_dev *dev,
5260                         struct rte_eth_udp_tunnel *udp_tunnel)
5261 {
5262         int ret = 0;
5263         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5264
5265         if (udp_tunnel == NULL)
5266                 return -EINVAL;
5267
5268         switch (udp_tunnel->prot_type) {
5269         case RTE_TUNNEL_TYPE_VXLAN:
5270                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port);
5271                 break;
5272
5273         case RTE_TUNNEL_TYPE_GENEVE:
5274         case RTE_TUNNEL_TYPE_TEREDO:
5275                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5276                 ret = -1;
5277                 break;
5278
5279         default:
5280                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5281                 ret = -1;
5282                 break;
5283         }
5284
5285         return ret;
5286 }
5287
5288 /* Remove UDP tunneling port */
5289 static int
5290 i40e_dev_udp_tunnel_del(struct rte_eth_dev *dev,
5291                         struct rte_eth_udp_tunnel *udp_tunnel)
5292 {
5293         int ret = 0;
5294         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5295
5296         if (udp_tunnel == NULL)
5297                 return -EINVAL;
5298
5299         switch (udp_tunnel->prot_type) {
5300         case RTE_TUNNEL_TYPE_VXLAN:
5301                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
5302                 break;
5303         case RTE_TUNNEL_TYPE_GENEVE:
5304         case RTE_TUNNEL_TYPE_TEREDO:
5305                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
5306                 ret = -1;
5307                 break;
5308         default:
5309                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5310                 ret = -1;
5311                 break;
5312         }
5313
5314         return ret;
5315 }
5316
5317 /* Calculate the maximum number of contiguous PF queues that are configured */
5318 static int
5319 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
5320 {
5321         struct rte_eth_dev_data *data = pf->dev_data;
5322         int i, num;
5323         struct i40e_rx_queue *rxq;
5324
5325         num = 0;
5326         for (i = 0; i < pf->lan_nb_qps; i++) {
5327                 rxq = data->rx_queues[i];
5328                 if (rxq && rxq->q_set)
5329                         num++;
5330                 else
5331                         break;
5332         }
5333
5334         return num;
5335 }
5336
5337 /* Configure RSS */
5338 static int
5339 i40e_pf_config_rss(struct i40e_pf *pf)
5340 {
5341         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5342         struct rte_eth_rss_conf rss_conf;
5343         uint32_t i, lut = 0;
5344         uint16_t j, num;
5345
5346         /*
5347          * If both VMDQ and RSS enabled, not all of PF queues are configured.
5348          * It's necessary to calulate the actual PF queues that are configured.
5349          */
5350         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
5351                 num = i40e_pf_calc_configured_queues_num(pf);
5352                 num = i40e_align_floor(num);
5353         } else
5354                 num = i40e_align_floor(pf->dev_data->nb_rx_queues);
5355
5356         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
5357                         num);
5358
5359         if (num == 0) {
5360                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
5361                 return -ENOTSUP;
5362         }
5363
5364         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
5365                 if (j == num)
5366                         j = 0;
5367                 lut = (lut << 8) | (j & ((0x1 <<
5368                         hw->func_caps.rss_table_entry_width) - 1));
5369                 if ((i & 3) == 3)
5370                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
5371         }
5372
5373         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
5374         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
5375                 i40e_pf_disable_rss(pf);
5376                 return 0;
5377         }
5378         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
5379                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
5380                 /* Random default keys */
5381                 static uint32_t rss_key_default[] = {0x6b793944,
5382                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
5383                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
5384                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
5385
5386                 rss_conf.rss_key = (uint8_t *)rss_key_default;
5387                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
5388                                                         sizeof(uint32_t);
5389         }
5390
5391         return i40e_hw_rss_hash_set(hw, &rss_conf);
5392 }
5393
5394 static int
5395 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
5396                         struct rte_eth_tunnel_filter_conf *filter)
5397 {
5398         if (pf == NULL || filter == NULL) {
5399                 PMD_DRV_LOG(ERR, "Invalid parameter");
5400                 return -EINVAL;
5401         }
5402
5403         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
5404                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5405                 return -EINVAL;
5406         }
5407
5408         if (filter->inner_vlan > ETHER_MAX_VLAN_ID) {
5409                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
5410                 return -EINVAL;
5411         }
5412
5413         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
5414                 (is_zero_ether_addr(filter->outer_mac))) {
5415                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
5416                 return -EINVAL;
5417         }
5418
5419         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
5420                 (is_zero_ether_addr(filter->inner_mac))) {
5421                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
5422                 return -EINVAL;
5423         }
5424
5425         return 0;
5426 }
5427
5428 static int
5429 i40e_tunnel_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
5430                         void *arg)
5431 {
5432         struct rte_eth_tunnel_filter_conf *filter;
5433         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5434         int ret = I40E_SUCCESS;
5435
5436         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
5437
5438         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
5439                 return I40E_ERR_PARAM;
5440
5441         switch (filter_op) {
5442         case RTE_ETH_FILTER_NOP:
5443                 if (!(pf->flags & I40E_FLAG_VXLAN))
5444                         ret = I40E_NOT_SUPPORTED;
5445         case RTE_ETH_FILTER_ADD:
5446                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
5447                 break;
5448         case RTE_ETH_FILTER_DELETE:
5449                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
5450                 break;
5451         default:
5452                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
5453                 ret = I40E_ERR_PARAM;
5454                 break;
5455         }
5456
5457         return ret;
5458 }
5459
5460 static int
5461 i40e_pf_config_mq_rx(struct i40e_pf *pf)
5462 {
5463         int ret = 0;
5464         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
5465
5466         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
5467                 PMD_INIT_LOG(ERR, "i40e doesn't support DCB yet");
5468                 return -ENOTSUP;
5469         }
5470
5471         /* RSS setup */
5472         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
5473                 ret = i40e_pf_config_rss(pf);
5474         else
5475                 i40e_pf_disable_rss(pf);
5476
5477         return ret;
5478 }
5479
5480 /* Get the symmetric hash enable configurations per port */
5481 static void
5482 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
5483 {
5484         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5485
5486         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
5487 }
5488
5489 /* Set the symmetric hash enable configurations per port */
5490 static void
5491 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
5492 {
5493         uint32_t reg = I40E_READ_REG(hw, I40E_PRTQF_CTL_0);
5494
5495         if (enable > 0) {
5496                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
5497                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5498                                                         "been enabled");
5499                         return;
5500                 }
5501                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5502         } else {
5503                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
5504                         PMD_DRV_LOG(INFO, "Symmetric hash has already "
5505                                                         "been disabled");
5506                         return;
5507                 }
5508                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
5509         }
5510         I40E_WRITE_REG(hw, I40E_PRTQF_CTL_0, reg);
5511         I40E_WRITE_FLUSH(hw);
5512 }
5513
5514 /*
5515  * Get global configurations of hash function type and symmetric hash enable
5516  * per flow type (pctype). Note that global configuration means it affects all
5517  * the ports on the same NIC.
5518  */
5519 static int
5520 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
5521                                    struct rte_eth_hash_global_conf *g_cfg)
5522 {
5523         uint32_t reg, mask = I40E_FLOW_TYPES;
5524         uint16_t i;
5525         enum i40e_filter_pctype pctype;
5526
5527         memset(g_cfg, 0, sizeof(*g_cfg));
5528         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5529         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
5530                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
5531         else
5532                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
5533         PMD_DRV_LOG(DEBUG, "Hash function is %s",
5534                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
5535
5536         for (i = 0; mask && i < RTE_ETH_FLOW_MAX; i++) {
5537                 if (!(mask & (1UL << i)))
5538                         continue;
5539                 mask &= ~(1UL << i);
5540                 /* Bit set indicats the coresponding flow type is supported */
5541                 g_cfg->valid_bit_mask[0] |= (1UL << i);
5542                 pctype = i40e_flowtype_to_pctype(i);
5543                 reg = I40E_READ_REG(hw, I40E_GLQF_HSYM(pctype));
5544                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK)
5545                         g_cfg->sym_hash_enable_mask[0] |= (1UL << i);
5546         }
5547
5548         return 0;
5549 }
5550
5551 static int
5552 i40e_hash_global_config_check(struct rte_eth_hash_global_conf *g_cfg)
5553 {
5554         uint32_t i;
5555         uint32_t mask0, i40e_mask = I40E_FLOW_TYPES;
5556
5557         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
5558                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
5559                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
5560                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
5561                                                 g_cfg->hash_func);
5562                 return -EINVAL;
5563         }
5564
5565         /*
5566          * As i40e supports less than 32 flow types, only first 32 bits need to
5567          * be checked.
5568          */
5569         mask0 = g_cfg->valid_bit_mask[0];
5570         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
5571                 if (i == 0) {
5572                         /* Check if any unsupported flow type configured */
5573                         if ((mask0 | i40e_mask) ^ i40e_mask)
5574                                 goto mask_err;
5575                 } else {
5576                         if (g_cfg->valid_bit_mask[i])
5577                                 goto mask_err;
5578                 }
5579         }
5580
5581         return 0;
5582
5583 mask_err:
5584         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
5585
5586         return -EINVAL;
5587 }
5588
5589 /*
5590  * Set global configurations of hash function type and symmetric hash enable
5591  * per flow type (pctype). Note any modifying global configuration will affect
5592  * all the ports on the same NIC.
5593  */
5594 static int
5595 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
5596                                    struct rte_eth_hash_global_conf *g_cfg)
5597 {
5598         int ret;
5599         uint16_t i;
5600         uint32_t reg;
5601         uint32_t mask0 = g_cfg->valid_bit_mask[0];
5602         enum i40e_filter_pctype pctype;
5603
5604         /* Check the input parameters */
5605         ret = i40e_hash_global_config_check(g_cfg);
5606         if (ret < 0)
5607                 return ret;
5608
5609         for (i = 0; mask0 && i < UINT32_BIT; i++) {
5610                 if (!(mask0 & (1UL << i)))
5611                         continue;
5612                 mask0 &= ~(1UL << i);
5613                 pctype = i40e_flowtype_to_pctype(i);
5614                 reg = (g_cfg->sym_hash_enable_mask[0] & (1UL << i)) ?
5615                                 I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
5616                 I40E_WRITE_REG(hw, I40E_GLQF_HSYM(pctype), reg);
5617         }
5618
5619         reg = I40E_READ_REG(hw, I40E_GLQF_CTL);
5620         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
5621                 /* Toeplitz */
5622                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
5623                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5624                                                                 "Toeplitz");
5625                         goto out;
5626                 }
5627                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
5628         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
5629                 /* Simple XOR */
5630                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
5631                         PMD_DRV_LOG(DEBUG, "Hash function already set to "
5632                                                         "Simple XOR");
5633                         goto out;
5634                 }
5635                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
5636         } else
5637                 /* Use the default, and keep it as it is */
5638                 goto out;
5639
5640         I40E_WRITE_REG(hw, I40E_GLQF_CTL, reg);
5641
5642 out:
5643         I40E_WRITE_FLUSH(hw);
5644
5645         return 0;
5646 }
5647
5648 static int
5649 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5650 {
5651         int ret = 0;
5652
5653         if (!hw || !info) {
5654                 PMD_DRV_LOG(ERR, "Invalid pointer");
5655                 return -EFAULT;
5656         }
5657
5658         switch (info->info_type) {
5659         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5660                 i40e_get_symmetric_hash_enable_per_port(hw,
5661                                         &(info->info.enable));
5662                 break;
5663         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5664                 ret = i40e_get_hash_filter_global_config(hw,
5665                                 &(info->info.global_conf));
5666                 break;
5667         default:
5668                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5669                                                         info->info_type);
5670                 ret = -EINVAL;
5671                 break;
5672         }
5673
5674         return ret;
5675 }
5676
5677 static int
5678 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
5679 {
5680         int ret = 0;
5681
5682         if (!hw || !info) {
5683                 PMD_DRV_LOG(ERR, "Invalid pointer");
5684                 return -EFAULT;
5685         }
5686
5687         switch (info->info_type) {
5688         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
5689                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
5690                 break;
5691         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
5692                 ret = i40e_set_hash_filter_global_config(hw,
5693                                 &(info->info.global_conf));
5694                 break;
5695         default:
5696                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
5697                                                         info->info_type);
5698                 ret = -EINVAL;
5699                 break;
5700         }
5701
5702         return ret;
5703 }
5704
5705 /* Operations for hash function */
5706 static int
5707 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
5708                       enum rte_filter_op filter_op,
5709                       void *arg)
5710 {
5711         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5712         int ret = 0;
5713
5714         switch (filter_op) {
5715         case RTE_ETH_FILTER_NOP:
5716                 break;
5717         case RTE_ETH_FILTER_GET:
5718                 ret = i40e_hash_filter_get(hw,
5719                         (struct rte_eth_hash_filter_info *)arg);
5720                 break;
5721         case RTE_ETH_FILTER_SET:
5722                 ret = i40e_hash_filter_set(hw,
5723                         (struct rte_eth_hash_filter_info *)arg);
5724                 break;
5725         default:
5726                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
5727                                                                 filter_op);
5728                 ret = -ENOTSUP;
5729                 break;
5730         }
5731
5732         return ret;
5733 }
5734
5735 /*
5736  * Configure ethertype filter, which can director packet by filtering
5737  * with mac address and ether_type or only ether_type
5738  */
5739 static int
5740 i40e_ethertype_filter_set(struct i40e_pf *pf,
5741                         struct rte_eth_ethertype_filter *filter,
5742                         bool add)
5743 {
5744         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5745         struct i40e_control_filter_stats stats;
5746         uint16_t flags = 0;
5747         int ret;
5748
5749         if (filter->queue >= pf->dev_data->nb_rx_queues) {
5750                 PMD_DRV_LOG(ERR, "Invalid queue ID");
5751                 return -EINVAL;
5752         }
5753         if (filter->ether_type == ETHER_TYPE_IPv4 ||
5754                 filter->ether_type == ETHER_TYPE_IPv6) {
5755                 PMD_DRV_LOG(ERR, "unsupported ether_type(0x%04x) in"
5756                         " control packet filter.", filter->ether_type);
5757                 return -EINVAL;
5758         }
5759         if (filter->ether_type == ETHER_TYPE_VLAN)
5760                 PMD_DRV_LOG(WARNING, "filter vlan ether_type in first tag is"
5761                         " not supported.");
5762
5763         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
5764                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
5765         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
5766                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
5767         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
5768
5769         memset(&stats, 0, sizeof(stats));
5770         ret = i40e_aq_add_rem_control_packet_filter(hw,
5771                         filter->mac_addr.addr_bytes,
5772                         filter->ether_type, flags,
5773                         pf->main_vsi->seid,
5774                         filter->queue, add, &stats, NULL);
5775
5776         PMD_DRV_LOG(INFO, "add/rem control packet filter, return %d,"
5777                          " mac_etype_used = %u, etype_used = %u,"
5778                          " mac_etype_free = %u, etype_free = %u\n",
5779                          ret, stats.mac_etype_used, stats.etype_used,
5780                          stats.mac_etype_free, stats.etype_free);
5781         if (ret < 0)
5782                 return -ENOSYS;
5783         return 0;
5784 }
5785
5786 /*
5787  * Handle operations for ethertype filter.
5788  */
5789 static int
5790 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
5791                                 enum rte_filter_op filter_op,
5792                                 void *arg)
5793 {
5794         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5795         int ret = 0;
5796
5797         if (filter_op == RTE_ETH_FILTER_NOP)
5798                 return ret;
5799
5800         if (arg == NULL) {
5801                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
5802                             filter_op);
5803                 return -EINVAL;
5804         }
5805
5806         switch (filter_op) {
5807         case RTE_ETH_FILTER_ADD:
5808                 ret = i40e_ethertype_filter_set(pf,
5809                         (struct rte_eth_ethertype_filter *)arg,
5810                         TRUE);
5811                 break;
5812         case RTE_ETH_FILTER_DELETE:
5813                 ret = i40e_ethertype_filter_set(pf,
5814                         (struct rte_eth_ethertype_filter *)arg,
5815                         FALSE);
5816                 break;
5817         default:
5818                 PMD_DRV_LOG(ERR, "unsupported operation %u\n", filter_op);
5819                 ret = -ENOSYS;
5820                 break;
5821         }
5822         return ret;
5823 }
5824
5825 static int
5826 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
5827                      enum rte_filter_type filter_type,
5828                      enum rte_filter_op filter_op,
5829                      void *arg)
5830 {
5831         int ret = 0;
5832
5833         if (dev == NULL)
5834                 return -EINVAL;
5835
5836         switch (filter_type) {
5837         case RTE_ETH_FILTER_HASH:
5838                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
5839                 break;
5840         case RTE_ETH_FILTER_MACVLAN:
5841                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
5842                 break;
5843         case RTE_ETH_FILTER_ETHERTYPE:
5844                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
5845                 break;
5846         case RTE_ETH_FILTER_TUNNEL:
5847                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
5848                 break;
5849         case RTE_ETH_FILTER_FDIR:
5850                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
5851                 break;
5852         default:
5853                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
5854                                                         filter_type);
5855                 ret = -EINVAL;
5856                 break;
5857         }
5858
5859         return ret;
5860 }
5861
5862 /*
5863  * As some registers wouldn't be reset unless a global hardware reset,
5864  * hardware initialization is needed to put those registers into an
5865  * expected initial state.
5866  */
5867 static void
5868 i40e_hw_init(struct i40e_hw *hw)
5869 {
5870         /* clear the PF Queue Filter control register */
5871         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, 0);
5872
5873         /* Disable symmetric hash per port */
5874         i40e_set_symmetric_hash_enable_per_port(hw, 0);
5875 }
5876
5877 enum i40e_filter_pctype
5878 i40e_flowtype_to_pctype(uint16_t flow_type)
5879 {
5880         static const enum i40e_filter_pctype pctype_table[] = {
5881                 [RTE_ETH_FLOW_FRAG_IPV4] = I40E_FILTER_PCTYPE_FRAG_IPV4,
5882                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
5883                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
5884                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
5885                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
5886                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
5887                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
5888                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
5889                         I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
5890                 [RTE_ETH_FLOW_FRAG_IPV6] = I40E_FILTER_PCTYPE_FRAG_IPV6,
5891                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
5892                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP,
5893                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
5894                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP,
5895                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
5896                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP,
5897                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
5898                         I40E_FILTER_PCTYPE_NONF_IPV6_OTHER,
5899                 [RTE_ETH_FLOW_L2_PAYLOAD] = I40E_FILTER_PCTYPE_L2_PAYLOAD,
5900         };
5901
5902         return pctype_table[flow_type];
5903 }
5904
5905 uint16_t
5906 i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype)
5907 {
5908         static const uint16_t flowtype_table[] = {
5909                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = RTE_ETH_FLOW_FRAG_IPV4,
5910                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
5911                         RTE_ETH_FLOW_NONFRAG_IPV4_UDP,
5912                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
5913                         RTE_ETH_FLOW_NONFRAG_IPV4_TCP,
5914                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
5915                         RTE_ETH_FLOW_NONFRAG_IPV4_SCTP,
5916                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
5917                         RTE_ETH_FLOW_NONFRAG_IPV4_OTHER,
5918                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = RTE_ETH_FLOW_FRAG_IPV6,
5919                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
5920                         RTE_ETH_FLOW_NONFRAG_IPV6_UDP,
5921                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
5922                         RTE_ETH_FLOW_NONFRAG_IPV6_TCP,
5923                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
5924                         RTE_ETH_FLOW_NONFRAG_IPV6_SCTP,
5925                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
5926                         RTE_ETH_FLOW_NONFRAG_IPV6_OTHER,
5927                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] = RTE_ETH_FLOW_L2_PAYLOAD,
5928         };
5929
5930         return flowtype_table[pctype];
5931 }
5932
5933 /*
5934  * On X710, performance number is far from the expectation on recent firmware
5935  * versions; on XL710, performance number is also far from the expectation on
5936  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
5937  * mode is enabled and port MAC address is equal to the packet destination MAC
5938  * address. The fix for this issue may not be integrated in the following
5939  * firmware version. So the workaround in software driver is needed. It needs
5940  * to modify the initial values of 3 internal only registers for both X710 and
5941  * XL710. Note that the values for X710 or XL710 could be different, and the
5942  * workaround can be removed when it is fixed in firmware in the future.
5943  */
5944
5945 /* For both X710 and XL710 */
5946 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x10000200
5947 #define I40E_GL_SWR_PRI_JOIN_MAP_0       0x26CE00
5948
5949 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
5950 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
5951
5952 /* For X710 */
5953 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
5954 /* For XL710 */
5955 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
5956 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
5957
5958 static void
5959 i40e_configure_registers(struct i40e_hw *hw)
5960 {
5961         static struct {
5962                 uint32_t addr;
5963                 uint64_t val;
5964         } reg_table[] = {
5965                 {I40E_GL_SWR_PRI_JOIN_MAP_0, I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE},
5966                 {I40E_GL_SWR_PRI_JOIN_MAP_2, I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE},
5967                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
5968         };
5969         uint64_t reg;
5970         uint32_t i;
5971         int ret;
5972
5973         for (i = 0; i < RTE_DIM(reg_table); i++) {
5974                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
5975                         if (i40e_is_40G_device(hw->device_id)) /* For XL710 */
5976                                 reg_table[i].val =
5977                                         I40E_GL_SWR_PM_UP_THR_SF_VALUE;
5978                         else /* For X710 */
5979                                 reg_table[i].val =
5980                                         I40E_GL_SWR_PM_UP_THR_EF_VALUE;
5981                 }
5982
5983                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
5984                                                         &reg, NULL);
5985                 if (ret < 0) {
5986                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
5987                                                         reg_table[i].addr);
5988                         break;
5989                 }
5990                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
5991                                                 reg_table[i].addr, reg);
5992                 if (reg == reg_table[i].val)
5993                         continue;
5994
5995                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
5996                                                 reg_table[i].val, NULL);
5997                 if (ret < 0) {
5998                         PMD_DRV_LOG(ERR, "Failed to write 0x%"PRIx64" to the "
5999                                 "address of 0x%"PRIx32, reg_table[i].val,
6000                                                         reg_table[i].addr);
6001                         break;
6002                 }
6003                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
6004                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
6005         }
6006 }
6007
6008 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
6009 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
6010 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
6011 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
6012 static int
6013 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
6014 {
6015         uint32_t reg;
6016         int ret;
6017
6018         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
6019                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
6020                 return -EINVAL;
6021         }
6022
6023         /* Configure for double VLAN RX stripping */
6024         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
6025         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
6026                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
6027                 ret = i40e_aq_debug_write_register(hw,
6028                                                    I40E_VSI_TSR(vsi->vsi_id),
6029                                                    reg, NULL);
6030                 if (ret < 0) {
6031                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
6032                                     vsi->vsi_id);
6033                         return I40E_ERR_CONFIG;
6034                 }
6035         }
6036
6037         /* Configure for double VLAN TX insertion */
6038         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
6039         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
6040                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
6041                 ret = i40e_aq_debug_write_register(hw,
6042                                                    I40E_VSI_L2TAGSTXVALID(
6043                                                    vsi->vsi_id), reg, NULL);
6044                 if (ret < 0) {
6045                         PMD_DRV_LOG(ERR, "Failed to update "
6046                                 "VSI_L2TAGSTXVALID[%d]", vsi->vsi_id);
6047                         return I40E_ERR_CONFIG;
6048                 }
6049         }
6050
6051         return 0;
6052 }
6053
6054 /**
6055  * i40e_aq_add_mirror_rule
6056  * @hw: pointer to the hardware structure
6057  * @seid: VEB seid to add mirror rule to
6058  * @dst_id: destination vsi seid
6059  * @entries: Buffer which contains the entities to be mirrored
6060  * @count: number of entities contained in the buffer
6061  * @rule_id:the rule_id of the rule to be added
6062  *
6063  * Add a mirror rule for a given veb.
6064  *
6065  **/
6066 static enum i40e_status_code
6067 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
6068                         uint16_t seid, uint16_t dst_id,
6069                         uint16_t rule_type, uint16_t *entries,
6070                         uint16_t count, uint16_t *rule_id)
6071 {
6072         struct i40e_aq_desc desc;
6073         struct i40e_aqc_add_delete_mirror_rule cmd;
6074         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
6075                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
6076                 &desc.params.raw;
6077         uint16_t buff_len;
6078         enum i40e_status_code status;
6079
6080         i40e_fill_default_direct_cmd_desc(&desc,
6081                                           i40e_aqc_opc_add_mirror_rule);
6082         memset(&cmd, 0, sizeof(cmd));
6083
6084         buff_len = sizeof(uint16_t) * count;
6085         desc.datalen = rte_cpu_to_le_16(buff_len);
6086         if (buff_len > 0)
6087                 desc.flags |= rte_cpu_to_le_16(
6088                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
6089         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6090                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6091         cmd.num_entries = rte_cpu_to_le_16(count);
6092         cmd.seid = rte_cpu_to_le_16(seid);
6093         cmd.destination = rte_cpu_to_le_16(dst_id);
6094
6095         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6096         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
6097         PMD_DRV_LOG(INFO, "i40e_aq_add_mirror_rule, aq_status %d,"
6098                          "rule_id = %u"
6099                          " mirror_rules_used = %u, mirror_rules_free = %u,",
6100                          hw->aq.asq_last_status, resp->rule_id,
6101                          resp->mirror_rules_used, resp->mirror_rules_free);
6102         *rule_id = rte_le_to_cpu_16(resp->rule_id);
6103
6104         return status;
6105 }
6106
6107 /**
6108  * i40e_aq_del_mirror_rule
6109  * @hw: pointer to the hardware structure
6110  * @seid: VEB seid to add mirror rule to
6111  * @entries: Buffer which contains the entities to be mirrored
6112  * @count: number of entities contained in the buffer
6113  * @rule_id:the rule_id of the rule to be delete
6114  *
6115  * Delete a mirror rule for a given veb.
6116  *
6117  **/
6118 static enum i40e_status_code
6119 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
6120                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
6121                 uint16_t count, uint16_t rule_id)
6122 {
6123         struct i40e_aq_desc desc;
6124         struct i40e_aqc_add_delete_mirror_rule cmd;
6125         uint16_t buff_len = 0;
6126         enum i40e_status_code status;
6127         void *buff = NULL;
6128
6129         i40e_fill_default_direct_cmd_desc(&desc,
6130                                           i40e_aqc_opc_delete_mirror_rule);
6131         memset(&cmd, 0, sizeof(cmd));
6132         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
6133                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
6134                                                           I40E_AQ_FLAG_RD));
6135                 cmd.num_entries = count;
6136                 buff_len = sizeof(uint16_t) * count;
6137                 desc.datalen = rte_cpu_to_le_16(buff_len);
6138                 buff = (void *)entries;
6139         } else
6140                 /* rule id is filled in destination field for deleting mirror rule */
6141                 cmd.destination = rte_cpu_to_le_16(rule_id);
6142
6143         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
6144                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
6145         cmd.seid = rte_cpu_to_le_16(seid);
6146
6147         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
6148         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
6149
6150         return status;
6151 }
6152
6153 /**
6154  * i40e_mirror_rule_set
6155  * @dev: pointer to the hardware structure
6156  * @mirror_conf: mirror rule info
6157  * @sw_id: mirror rule's sw_id
6158  * @on: enable/disable
6159  *
6160  * set a mirror rule.
6161  *
6162  **/
6163 static int
6164 i40e_mirror_rule_set(struct rte_eth_dev *dev,
6165                         struct rte_eth_mirror_conf *mirror_conf,
6166                         uint8_t sw_id, uint8_t on)
6167 {
6168         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6169         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6170         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6171         struct i40e_mirror_rule *parent = NULL;
6172         uint16_t seid, dst_seid, rule_id;
6173         uint16_t i, j = 0;
6174         int ret;
6175
6176         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
6177
6178         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
6179                 PMD_DRV_LOG(ERR, "mirror rule can not be configured"
6180                         " without veb or vfs.");
6181                 return -ENOSYS;
6182         }
6183         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
6184                 PMD_DRV_LOG(ERR, "mirror table is full.");
6185                 return -ENOSPC;
6186         }
6187         if (mirror_conf->dst_pool > pf->vf_num) {
6188                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
6189                                  mirror_conf->dst_pool);
6190                 return -EINVAL;
6191         }
6192
6193         seid = pf->main_vsi->veb->seid;
6194
6195         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6196                 if (sw_id <= it->index) {
6197                         mirr_rule = it;
6198                         break;
6199                 }
6200                 parent = it;
6201         }
6202         if (mirr_rule && sw_id == mirr_rule->index) {
6203                 if (on) {
6204                         PMD_DRV_LOG(ERR, "mirror rule exists.");
6205                         return -EEXIST;
6206                 } else {
6207                         ret = i40e_aq_del_mirror_rule(hw, seid,
6208                                         mirr_rule->rule_type,
6209                                         mirr_rule->entries,
6210                                         mirr_rule->num_entries, mirr_rule->id);
6211                         if (ret < 0) {
6212                                 PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6213                                                    " ret = %d, aq_err = %d.",
6214                                                    ret, hw->aq.asq_last_status);
6215                                 return -ENOSYS;
6216                         }
6217                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6218                         rte_free(mirr_rule);
6219                         pf->nb_mirror_rule--;
6220                         return 0;
6221                 }
6222         } else if (!on) {
6223                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6224                 return -ENOENT;
6225         }
6226
6227         mirr_rule = rte_zmalloc("i40e_mirror_rule",
6228                                 sizeof(struct i40e_mirror_rule) , 0);
6229         if (!mirr_rule) {
6230                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6231                 return I40E_ERR_NO_MEMORY;
6232         }
6233         switch (mirror_conf->rule_type) {
6234         case ETH_MIRROR_VLAN:
6235                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
6236                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
6237                                 mirr_rule->entries[j] =
6238                                         mirror_conf->vlan.vlan_id[i];
6239                                 j++;
6240                         }
6241                 }
6242                 if (j == 0) {
6243                         PMD_DRV_LOG(ERR, "vlan is not specified.");
6244                         rte_free(mirr_rule);
6245                         return -EINVAL;
6246                 }
6247                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
6248                 break;
6249         case ETH_MIRROR_VIRTUAL_POOL_UP:
6250         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
6251                 /* check if the specified pool bit is out of range */
6252                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
6253                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
6254                         rte_free(mirr_rule);
6255                         return -EINVAL;
6256                 }
6257                 for (i = 0, j = 0; i < pf->vf_num; i++) {
6258                         if (mirror_conf->pool_mask & (1ULL << i)) {
6259                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
6260                                 j++;
6261                         }
6262                 }
6263                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
6264                         /* add pf vsi to entries */
6265                         mirr_rule->entries[j] = pf->main_vsi_seid;
6266                         j++;
6267                 }
6268                 if (j == 0) {
6269                         PMD_DRV_LOG(ERR, "pool is not specified.");
6270                         rte_free(mirr_rule);
6271                         return -EINVAL;
6272                 }
6273                 /* egress and ingress in aq commands means from switch but not port */
6274                 mirr_rule->rule_type =
6275                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
6276                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
6277                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
6278                 break;
6279         case ETH_MIRROR_UPLINK_PORT:
6280                 /* egress and ingress in aq commands means from switch but not port*/
6281                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
6282                 break;
6283         case ETH_MIRROR_DOWNLINK_PORT:
6284                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
6285                 break;
6286         default:
6287                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
6288                         mirror_conf->rule_type);
6289                 rte_free(mirr_rule);
6290                 return -EINVAL;
6291         }
6292
6293         /* If the dst_pool is equal to vf_num, consider it as PF */
6294         if (mirror_conf->dst_pool == pf->vf_num)
6295                 dst_seid = pf->main_vsi_seid;
6296         else
6297                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
6298
6299         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
6300                                       mirr_rule->rule_type, mirr_rule->entries,
6301                                       j, &rule_id);
6302         if (ret < 0) {
6303                 PMD_DRV_LOG(ERR, "failed to add mirror rule:"
6304                                    " ret = %d, aq_err = %d.",
6305                                    ret, hw->aq.asq_last_status);
6306                 rte_free(mirr_rule);
6307                 return -ENOSYS;
6308         }
6309
6310         mirr_rule->index = sw_id;
6311         mirr_rule->num_entries = j;
6312         mirr_rule->id = rule_id;
6313         mirr_rule->dst_vsi_seid = dst_seid;
6314
6315         if (parent)
6316                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
6317         else
6318                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
6319
6320         pf->nb_mirror_rule++;
6321         return 0;
6322 }
6323
6324 /**
6325  * i40e_mirror_rule_reset
6326  * @dev: pointer to the device
6327  * @sw_id: mirror rule's sw_id
6328  *
6329  * reset a mirror rule.
6330  *
6331  **/
6332 static int
6333 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
6334 {
6335         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6337         struct i40e_mirror_rule *it, *mirr_rule = NULL;
6338         uint16_t seid;
6339         int ret;
6340
6341         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
6342
6343         seid = pf->main_vsi->veb->seid;
6344
6345         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
6346                 if (sw_id == it->index) {
6347                         mirr_rule = it;
6348                         break;
6349                 }
6350         }
6351         if (mirr_rule) {
6352                 ret = i40e_aq_del_mirror_rule(hw, seid,
6353                                 mirr_rule->rule_type,
6354                                 mirr_rule->entries,
6355                                 mirr_rule->num_entries, mirr_rule->id);
6356                 if (ret < 0) {
6357                         PMD_DRV_LOG(ERR, "failed to remove mirror rule:"
6358                                            " status = %d, aq_err = %d.",
6359                                            ret, hw->aq.asq_last_status);
6360                         return -ENOSYS;
6361                 }
6362                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
6363                 rte_free(mirr_rule);
6364                 pf->nb_mirror_rule--;
6365         } else {
6366                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
6367                 return -ENOENT;
6368         }
6369         return 0;
6370 }
6371
6372 static int
6373 i40e_timesync_enable(struct rte_eth_dev *dev)
6374 {
6375         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6376         struct rte_eth_link *link = &dev->data->dev_link;
6377         uint32_t tsync_ctl_l;
6378         uint32_t tsync_ctl_h;
6379         uint32_t tsync_inc_l;
6380         uint32_t tsync_inc_h;
6381
6382         switch (link->link_speed) {
6383         case ETH_LINK_SPEED_40G:
6384                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
6385                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
6386                 break;
6387         case ETH_LINK_SPEED_10G:
6388                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
6389                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
6390                 break;
6391         case ETH_LINK_SPEED_1000:
6392                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
6393                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
6394                 break;
6395         default:
6396                 tsync_inc_l = 0x0;
6397                 tsync_inc_h = 0x0;
6398         }
6399
6400         /* Clear timesync registers. */
6401         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6402         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6403         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(0));
6404         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(1));
6405         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(2));
6406         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(3));
6407         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6408
6409         /* Set the timesync increment value. */
6410         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
6411         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
6412
6413         /* Enable timestamping of PTP packets. */
6414         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6415         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
6416
6417         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6418         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
6419         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
6420
6421         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6422         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6423
6424         return 0;
6425 }
6426
6427 static int
6428 i40e_timesync_disable(struct rte_eth_dev *dev)
6429 {
6430         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6431         uint32_t tsync_ctl_l;
6432         uint32_t tsync_ctl_h;
6433
6434         /* Disable timestamping of transmitted PTP packets. */
6435         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
6436         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
6437
6438         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
6439         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
6440
6441         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
6442         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
6443
6444         /* Set the timesync increment value. */
6445         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
6446         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
6447
6448         return 0;
6449 }
6450
6451 static int
6452 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
6453                                 struct timespec *timestamp, uint32_t flags)
6454 {
6455         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6456         uint32_t sync_status;
6457         uint32_t rx_stmpl;
6458         uint32_t rx_stmph;
6459         uint32_t index = flags & 0x03;
6460
6461         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
6462         if ((sync_status & (1 << index)) == 0)
6463                 return -EINVAL;
6464
6465         rx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
6466         rx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index));
6467
6468         timestamp->tv_sec = (uint64_t)(((uint64_t)rx_stmph << 32) | rx_stmpl);
6469         timestamp->tv_nsec = 0;
6470
6471         return  0;
6472 }
6473
6474 static int
6475 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
6476                                 struct timespec *timestamp)
6477 {
6478         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6479         uint32_t sync_status;
6480         uint32_t tx_stmpl;
6481         uint32_t tx_stmph;
6482
6483         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
6484         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
6485                 return -EINVAL;
6486
6487         tx_stmpl = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
6488         tx_stmph = I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
6489
6490         timestamp->tv_sec = (uint64_t)(((uint64_t)tx_stmph << 32) | tx_stmpl);
6491         timestamp->tv_nsec = 0;
6492
6493         return  0;
6494 }