drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29 #include <rte_bitmap.h>
  30
  31 #include "i40e_logs.h"
  32 #include "base/i40e_prototype.h"
  33 #include "base/i40e_adminq_cmd.h"
  34 #include "base/i40e_type.h"
  35 #include "base/i40e_register.h"
  36 #include "base/i40e_dcb.h"
  37 #include "i40e_ethdev.h"
  38 #include "i40e_rxtx.h"
  39 #include "i40e_pf.h"
  40 #include "i40e_regs.h"
  41 #include "rte_pmd_i40e.h"
  42
  43 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  44 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  45 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  46 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  47 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  48 #define ETH_I40E_VF_MSG_CFG             "vf_msg_cfg"
  49
  50 #define I40E_CLEAR_PXE_WAIT_MS     200
  51
  52 /* Maximun number of capability elements */
  53 #define I40E_MAX_CAP_ELE_NUM       128
  54
  55 /* Wait count and interval */
  56 #define I40E_CHK_Q_ENA_COUNT       1000
  57 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  58
  59 /* Maximun number of VSI */
  60 #define I40E_MAX_NUM_VSIS          (384UL)
  61
  62 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  63
  64 /* Flow control default timer */
  65 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  66
  67 /* Flow control enable fwd bit */
  68 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  69
  70 /* Receive Packet Buffer size */
  71 #define I40E_RXPBSIZE (968 * 1024)
  72
  73 /* Kilobytes shift */
  74 #define I40E_KILOSHIFT 10
  75
  76 /* Flow control default high water */
  77 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  78
  79 /* Flow control default low water */
  80 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  81
  82 /* Receive Average Packet Size in Byte*/
  83 #define I40E_PACKET_AVERAGE_SIZE 128
  84
  85 /* Mask of PF interrupt causes */
  86 #define I40E_PFINT_ICR0_ENA_MASK ( \
  87                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  88                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  89                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  90                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  91                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  92                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  94                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  95                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  96
  97 #define I40E_FLOW_TYPES ( \
  98         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 103         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 107         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 108         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 109
 110 /* Additional timesync values. */
 111 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 112 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 113 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 114 #define I40E_PRTTSYN_TSYNENA     0x80000000
 115 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 116 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 117
 118 /**
 119  * Below are values for writing un-exposed registers suggested
 120  * by silicon experts
 121  */
 122 /* Destination MAC address */
 123 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 124 /* Source MAC address */
 125 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 126 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 128 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 129 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 130 /* Single VLAN tag in the inner L2 header */
 131 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 132 /* Source IPv4 address */
 133 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 134 /* Destination IPv4 address */
 135 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 136 /* Source IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 138 /* Destination IPv4 address for X722 */
 139 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 140 /* IPv4 Protocol for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 142 /* IPv4 Time to Live for X722 */
 143 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 144 /* IPv4 Type of Service (TOS) */
 145 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 146 /* IPv4 Protocol */
 147 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 148 /* IPv4 Time to Live */
 149 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 150 /* Source IPv6 address */
 151 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 152 /* Destination IPv6 address */
 153 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 154 /* IPv6 Traffic Class (TC) */
 155 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 156 /* IPv6 Next Header */
 157 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 158 /* IPv6 Hop Limit */
 159 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 160 /* Source L4 port */
 161 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 162 /* Destination L4 port */
 163 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 164 /* SCTP verification tag */
 165 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 166 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 167 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 168 /* Source port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 170 /* Destination port of tunneling UDP */
 171 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 172 /* UDP Tunneling ID, NVGRE/GRE key */
 173 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 174 /* Last ether type */
 175 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 176 /* Tunneling outer destination IPv4 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 178 /* Tunneling outer destination IPv6 address */
 179 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 180 /* 1st word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 182 /* 2nd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 184 /* 3rd word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 186 /* 4th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 188 /* 5th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 190 /* 6th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 192 /* 7th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 194 /* 8th word of flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 196 /* all 8 words flex payload */
 197 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 198 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 199
 200 #define I40E_TRANSLATE_INSET 0
 201 #define I40E_TRANSLATE_REG   1
 202
 203 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 204 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 205 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 206 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 207 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 208 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 209
 210 /* PCI offset for querying capability */
 211 #define PCI_DEV_CAP_REG            0xA4
 212 /* PCI offset for enabling/disabling Extended Tag */
 213 #define PCI_DEV_CTRL_REG           0xA8
 214 /* Bit mask of Extended Tag capability */
 215 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 216 /* Bit shift of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 218 /* Bit mask of Extended Tag enable/disable */
 219 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 220
 221 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 222 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 223 static int i40e_dev_configure(struct rte_eth_dev *dev);
 224 static int i40e_dev_start(struct rte_eth_dev *dev);
 225 static void i40e_dev_stop(struct rte_eth_dev *dev);
 226 static void i40e_dev_close(struct rte_eth_dev *dev);
 227 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 228 static int i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 229 static int i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 231 static int i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 232 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 233 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 234 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_stats *stats);
 236 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 237                                struct rte_eth_xstat *xstats, unsigned n);
 238 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 239                                      struct rte_eth_xstat_name *xstats_names,
 240                                      unsigned limit);
 241 static int i40e_dev_stats_reset(struct rte_eth_dev *dev);
 242 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 243                                 char *fw_version, size_t fw_size);
 244 static int i40e_dev_info_get(struct rte_eth_dev *dev,
 245                              struct rte_eth_dev_info *dev_info);
 246 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 247                                 uint16_t vlan_id,
 248                                 int on);
 249 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 250                               enum rte_vlan_type vlan_type,
 251                               uint16_t tpid);
 252 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 253 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 254                                       uint16_t queue,
 255                                       int on);
 256 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 257 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 258 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 259 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 260                               struct rte_eth_fc_conf *fc_conf);
 261 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 264                                        struct rte_eth_pfc_conf *pfc_conf);
 265 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 266                             struct rte_ether_addr *mac_addr,
 267                             uint32_t index,
 268                             uint32_t pool);
 269 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 270 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 271                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 272                                     uint16_t reta_size);
 273 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 274                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 275                                    uint16_t reta_size);
 276
 277 static int i40e_get_cap(struct i40e_hw *hw);
 278 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 279 static int i40e_pf_setup(struct i40e_pf *pf);
 280 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 281 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 282 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 283 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 284                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 285 static void i40e_stat_update_48(struct i40e_hw *hw,
 286                                uint32_t hireg,
 287                                uint32_t loreg,
 288                                bool offset_loaded,
 289                                uint64_t *offset,
 290                                uint64_t *stat);
 291 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 292 static void i40e_dev_interrupt_handler(void *param);
 293 static void i40e_dev_alarm_handler(void *param);
 294 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 295                                 uint32_t base, uint32_t num);
 296 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 297 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 298                         uint32_t base);
 299 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 300                         uint16_t num);
 301 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 302 static int i40e_veb_release(struct i40e_veb *veb);
 303 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 304                                                 struct i40e_vsi *vsi);
 305 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 306 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 307 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 308                                              struct i40e_macvlan_filter *mv_f,
 309                                              int num,
 310                                              uint16_t vlan);
 311 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 312 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 313                                     struct rte_eth_rss_conf *rss_conf);
 314 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 315                                       struct rte_eth_rss_conf *rss_conf);
 316 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 317                                         struct rte_eth_udp_tunnel *udp_tunnel);
 318 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 319                                         struct rte_eth_udp_tunnel *udp_tunnel);
 320 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 321 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 322                                 enum rte_filter_op filter_op,
 323                                 void *arg);
 324 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 325                                 enum rte_filter_type filter_type,
 326                                 enum rte_filter_op filter_op,
 327                                 void *arg);
 328 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 329                                   struct rte_eth_dcb_info *dcb_info);
 330 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 331 static void i40e_configure_registers(struct i40e_hw *hw);
 332 static void i40e_hw_init(struct rte_eth_dev *dev);
 333 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 334 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 335                                                      uint16_t seid,
 336                                                      uint16_t rule_type,
 337                                                      uint16_t *entries,
 338                                                      uint16_t count,
 339                                                      uint16_t rule_id);
 340 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 341                         struct rte_eth_mirror_conf *mirror_conf,
 342                         uint8_t sw_id, uint8_t on);
 343 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 344
 345 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 346 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 347 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 348                                            struct timespec *timestamp,
 349                                            uint32_t flags);
 350 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 351                                            struct timespec *timestamp);
 352 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 353
 354 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 355
 356 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 357                                    struct timespec *timestamp);
 358 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 359                                     const struct timespec *timestamp);
 360
 361 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 362                                          uint16_t queue_id);
 363 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 364                                           uint16_t queue_id);
 365
 366 static int i40e_get_regs(struct rte_eth_dev *dev,
 367                          struct rte_dev_reg_info *regs);
 368
 369 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 370
 371 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 372                            struct rte_dev_eeprom_info *eeprom);
 373
 374 static int i40e_get_module_info(struct rte_eth_dev *dev,
 375                                 struct rte_eth_dev_module_info *modinfo);
 376 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 377                                   struct rte_dev_eeprom_info *info);
 378
 379 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 380                                       struct rte_ether_addr *mac_addr);
 381
 382 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 383
 384 static int i40e_ethertype_filter_convert(
 385         const struct rte_eth_ethertype_filter *input,
 386         struct i40e_ethertype_filter *filter);
 387 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 388                                    struct i40e_ethertype_filter *filter);
 389
 390 static int i40e_tunnel_filter_convert(
 391         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 392         struct i40e_tunnel_filter *tunnel_filter);
 393 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 394                                 struct i40e_tunnel_filter *tunnel_filter);
 395 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 396
 397 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 398 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 399 static void i40e_filter_restore(struct i40e_pf *pf);
 400 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 401
 402 static const char *const valid_keys[] = {
 403         ETH_I40E_FLOATING_VEB_ARG,
 404         ETH_I40E_FLOATING_VEB_LIST_ARG,
 405         ETH_I40E_SUPPORT_MULTI_DRIVER,
 406         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 407         ETH_I40E_USE_LATEST_VEC,
 408         ETH_I40E_VF_MSG_CFG,
 409         NULL};
 410
 411 static const struct rte_pci_id pci_id_i40e_map[] = {
 412         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 413         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 414         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 415         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_5G_BASE_T_BC) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_B) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_SFP) },
 438         { .vendor_id = 0, /* sentinel */ },
 439 };
 440
 441 static const struct eth_dev_ops i40e_eth_dev_ops = {
 442         .dev_configure                = i40e_dev_configure,
 443         .dev_start                    = i40e_dev_start,
 444         .dev_stop                     = i40e_dev_stop,
 445         .dev_close                    = i40e_dev_close,
 446         .dev_reset                    = i40e_dev_reset,
 447         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 448         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 449         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 450         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 451         .dev_set_link_up              = i40e_dev_set_link_up,
 452         .dev_set_link_down            = i40e_dev_set_link_down,
 453         .link_update                  = i40e_dev_link_update,
 454         .stats_get                    = i40e_dev_stats_get,
 455         .xstats_get                   = i40e_dev_xstats_get,
 456         .xstats_get_names             = i40e_dev_xstats_get_names,
 457         .stats_reset                  = i40e_dev_stats_reset,
 458         .xstats_reset                 = i40e_dev_stats_reset,
 459         .fw_version_get               = i40e_fw_version_get,
 460         .dev_infos_get                = i40e_dev_info_get,
 461         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 462         .vlan_filter_set              = i40e_vlan_filter_set,
 463         .vlan_tpid_set                = i40e_vlan_tpid_set,
 464         .vlan_offload_set             = i40e_vlan_offload_set,
 465         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 466         .vlan_pvid_set                = i40e_vlan_pvid_set,
 467         .rx_queue_start               = i40e_dev_rx_queue_start,
 468         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 469         .tx_queue_start               = i40e_dev_tx_queue_start,
 470         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 471         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 472         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 473         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 474         .rx_queue_release             = i40e_dev_rx_queue_release,
 475         .rx_queue_count               = i40e_dev_rx_queue_count,
 476         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 477         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 478         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 479         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 480         .tx_queue_release             = i40e_dev_tx_queue_release,
 481         .dev_led_on                   = i40e_dev_led_on,
 482         .dev_led_off                  = i40e_dev_led_off,
 483         .flow_ctrl_get                = i40e_flow_ctrl_get,
 484         .flow_ctrl_set                = i40e_flow_ctrl_set,
 485         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 486         .mac_addr_add                 = i40e_macaddr_add,
 487         .mac_addr_remove              = i40e_macaddr_remove,
 488         .reta_update                  = i40e_dev_rss_reta_update,
 489         .reta_query                   = i40e_dev_rss_reta_query,
 490         .rss_hash_update              = i40e_dev_rss_hash_update,
 491         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 492         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 493         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 494         .filter_ctrl                  = i40e_dev_filter_ctrl,
 495         .rxq_info_get                 = i40e_rxq_info_get,
 496         .txq_info_get                 = i40e_txq_info_get,
 497         .rx_burst_mode_get            = i40e_rx_burst_mode_get,
 498         .tx_burst_mode_get            = i40e_tx_burst_mode_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .get_module_info              = i40e_get_module_info,
 513         .get_module_eeprom            = i40e_get_module_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515         .mtu_set                      = i40e_dev_mtu_set,
 516         .tm_ops_get                   = i40e_tm_ops_get,
 517         .tx_done_cleanup              = i40e_tx_done_cleanup,
 518 };
 519
 520 /* store statistics names and its offset in stats structure */
 521 struct rte_i40e_xstats_name_off {
 522         char name[RTE_ETH_XSTATS_NAME_SIZE];
 523         unsigned offset;
 524 };
 525
 526 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 527         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 528         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 529         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 530         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 531         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 532                 rx_unknown_protocol)},
 533         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 534         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 535         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 536         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 537 };
 538
 539 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 540                 sizeof(rte_i40e_stats_strings[0]))
 541
 542 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 543         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 544                 tx_dropped_link_down)},
 545         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 546         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 547                 illegal_bytes)},
 548         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 549         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 550                 mac_local_faults)},
 551         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 552                 mac_remote_faults)},
 553         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 554                 rx_length_errors)},
 555         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 556         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 557         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 558         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 559         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 560         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 561                 rx_size_127)},
 562         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 563                 rx_size_255)},
 564         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 565                 rx_size_511)},
 566         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 567                 rx_size_1023)},
 568         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 569                 rx_size_1522)},
 570         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 571                 rx_size_big)},
 572         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 573                 rx_undersize)},
 574         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 575                 rx_oversize)},
 576         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 577                 mac_short_packet_dropped)},
 578         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 579                 rx_fragments)},
 580         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 581         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 582         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 583                 tx_size_127)},
 584         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 585                 tx_size_255)},
 586         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 587                 tx_size_511)},
 588         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 589                 tx_size_1023)},
 590         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 591                 tx_size_1522)},
 592         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 593                 tx_size_big)},
 594         {"rx_flow_director_atr_match_packets",
 595                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 596         {"rx_flow_director_sb_match_packets",
 597                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 598         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 599                 tx_lpi_status)},
 600         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 601                 rx_lpi_status)},
 602         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 603                 tx_lpi_count)},
 604         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 605                 rx_lpi_count)},
 606 };
 607
 608 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 609                 sizeof(rte_i40e_hw_port_strings[0]))
 610
 611 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 612         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 613                 priority_xon_rx)},
 614         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 615                 priority_xoff_rx)},
 616 };
 617
 618 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 619                 sizeof(rte_i40e_rxq_prio_strings[0]))
 620
 621 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 622         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 623                 priority_xon_tx)},
 624         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 625                 priority_xoff_tx)},
 626         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 627                 priority_xon_2_xoff)},
 628 };
 629
 630 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 631                 sizeof(rte_i40e_txq_prio_strings[0]))
 632
 633 static int
 634 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 635         struct rte_pci_device *pci_dev)
 636 {
 637         char name[RTE_ETH_NAME_MAX_LEN];
 638         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 639         int i, retval;
 640
 641         if (pci_dev->device.devargs) {
 642                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 643                                 &eth_da);
 644                 if (retval)
 645                         return retval;
 646         }
 647
 648         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 649                 sizeof(struct i40e_adapter),
 650                 eth_dev_pci_specific_init, pci_dev,
 651                 eth_i40e_dev_init, NULL);
 652
 653         if (retval || eth_da.nb_representor_ports < 1)
 654                 return retval;
 655
 656         /* probe VF representor ports */
 657         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 658                 pci_dev->device.name);
 659
 660         if (pf_ethdev == NULL)
 661                 return -ENODEV;
 662
 663         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 664                 struct i40e_vf_representor representor = {
 665                         .vf_id = eth_da.representor_ports[i],
 666                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 667                                 pf_ethdev->data->dev_private)->switch_domain_id,
 668                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 669                                 pf_ethdev->data->dev_private)
 670                 };
 671
 672                 /* representor port net_bdf_port */
 673                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 674                         pci_dev->device.name, eth_da.representor_ports[i]);
 675
 676                 retval = rte_eth_dev_create(&pci_dev->device, name,
 677                         sizeof(struct i40e_vf_representor), NULL, NULL,
 678                         i40e_vf_representor_init, &representor);
 679
 680                 if (retval)
 681                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 682                                 "representor %s.", name);
 683         }
 684
 685         return 0;
 686 }
 687
 688 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 689 {
 690         struct rte_eth_dev *ethdev;
 691
 692         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 693         if (!ethdev)
 694                 return 0;
 695
 696         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 697                 return rte_eth_dev_pci_generic_remove(pci_dev,
 698                                         i40e_vf_representor_uninit);
 699         else
 700                 return rte_eth_dev_pci_generic_remove(pci_dev,
 701                                                 eth_i40e_dev_uninit);
 702 }
 703
 704 static struct rte_pci_driver rte_i40e_pmd = {
 705         .id_table = pci_id_i40e_map,
 706         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
 707         .probe = eth_i40e_pci_probe,
 708         .remove = eth_i40e_pci_remove,
 709 };
 710
 711 static inline void
 712 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 713                          uint32_t reg_val)
 714 {
 715         uint32_t ori_reg_val;
 716         struct rte_eth_dev *dev;
 717
 718         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 719         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 720         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 721         if (ori_reg_val != reg_val)
 722                 PMD_DRV_LOG(WARNING,
 723                             "i40e device %s changed global register [0x%08x]."
 724                             " original: 0x%08x, new: 0x%08x",
 725                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 726 }
 727
 728 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 729 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 730 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 731
 732 #ifndef I40E_GLQF_ORT
 733 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 734 #endif
 735 #ifndef I40E_GLQF_PIT
 736 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 737 #endif
 738 #ifndef I40E_GLQF_L3_MAP
 739 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 740 #endif
 741
 742 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 743 {
 744         /*
 745          * Initialize registers for parsing packet type of QinQ
 746          * This should be removed from code once proper
 747          * configuration API is added to avoid configuration conflicts
 748          * between ports of the same device.
 749          */
 750         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 751         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 752 }
 753
 754 static inline void i40e_config_automask(struct i40e_pf *pf)
 755 {
 756         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 757         uint32_t val;
 758
 759         /* INTENA flag is not auto-cleared for interrupt */
 760         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 761         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 762                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 763
 764         /* If support multi-driver, PF will use INT0. */
 765         if (!pf->support_multi_driver)
 766                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 767
 768         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 769 }
 770
 771 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 772
 773 /*
 774  * Add a ethertype filter to drop all flow control frames transmitted
 775  * from VSIs.
 776 */
 777 static void
 778 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 779 {
 780         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 781         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 782                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 783                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 784         int ret;
 785
 786         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 787                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 788                                 pf->main_vsi_seid, 0,
 789                                 TRUE, NULL, NULL);
 790         if (ret)
 791                 PMD_INIT_LOG(ERR,
 792                         "Failed to add filter to drop flow control frames from VSIs.");
 793 }
 794
 795 static int
 796 floating_veb_list_handler(__rte_unused const char *key,
 797                           const char *floating_veb_value,
 798                           void *opaque)
 799 {
 800         int idx = 0;
 801         unsigned int count = 0;
 802         char *end = NULL;
 803         int min, max;
 804         bool *vf_floating_veb = opaque;
 805
 806         while (isblank(*floating_veb_value))
 807                 floating_veb_value++;
 808
 809         /* Reset floating VEB configuration for VFs */
 810         for (idx = 0; idx < I40E_MAX_VF; idx++)
 811                 vf_floating_veb[idx] = false;
 812
 813         min = I40E_MAX_VF;
 814         do {
 815                 while (isblank(*floating_veb_value))
 816                         floating_veb_value++;
 817                 if (*floating_veb_value == '\0')
 818                         return -1;
 819                 errno = 0;
 820                 idx = strtoul(floating_veb_value, &end, 10);
 821                 if (errno || end == NULL)
 822                         return -1;
 823                 while (isblank(*end))
 824                         end++;
 825                 if (*end == '-') {
 826                         min = idx;
 827                 } else if ((*end == ';') || (*end == '\0')) {
 828                         max = idx;
 829                         if (min == I40E_MAX_VF)
 830                                 min = idx;
 831                         if (max >= I40E_MAX_VF)
 832                                 max = I40E_MAX_VF - 1;
 833                         for (idx = min; idx <= max; idx++) {
 834                                 vf_floating_veb[idx] = true;
 835                                 count++;
 836                         }
 837                         min = I40E_MAX_VF;
 838                 } else {
 839                         return -1;
 840                 }
 841                 floating_veb_value = end + 1;
 842         } while (*end != '\0');
 843
 844         if (count == 0)
 845                 return -1;
 846
 847         return 0;
 848 }
 849
 850 static void
 851 config_vf_floating_veb(struct rte_devargs *devargs,
 852                        uint16_t floating_veb,
 853                        bool *vf_floating_veb)
 854 {
 855         struct rte_kvargs *kvlist;
 856         int i;
 857         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 858
 859         if (!floating_veb)
 860                 return;
 861         /* All the VFs attach to the floating VEB by default
 862          * when the floating VEB is enabled.
 863          */
 864         for (i = 0; i < I40E_MAX_VF; i++)
 865                 vf_floating_veb[i] = true;
 866
 867         if (devargs == NULL)
 868                 return;
 869
 870         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 871         if (kvlist == NULL)
 872                 return;
 873
 874         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 875                 rte_kvargs_free(kvlist);
 876                 return;
 877         }
 878         /* When the floating_veb_list parameter exists, all the VFs
 879          * will attach to the legacy VEB firstly, then configure VFs
 880          * to the floating VEB according to the floating_veb_list.
 881          */
 882         if (rte_kvargs_process(kvlist, floating_veb_list,
 883                                floating_veb_list_handler,
 884                                vf_floating_veb) < 0) {
 885                 rte_kvargs_free(kvlist);
 886                 return;
 887         }
 888         rte_kvargs_free(kvlist);
 889 }
 890
 891 static int
 892 i40e_check_floating_handler(__rte_unused const char *key,
 893                             const char *value,
 894                             __rte_unused void *opaque)
 895 {
 896         if (strcmp(value, "1"))
 897                 return -1;
 898
 899         return 0;
 900 }
 901
 902 static int
 903 is_floating_veb_supported(struct rte_devargs *devargs)
 904 {
 905         struct rte_kvargs *kvlist;
 906         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 907
 908         if (devargs == NULL)
 909                 return 0;
 910
 911         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 912         if (kvlist == NULL)
 913                 return 0;
 914
 915         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 916                 rte_kvargs_free(kvlist);
 917                 return 0;
 918         }
 919         /* Floating VEB is enabled when there's key-value:
 920          * enable_floating_veb=1
 921          */
 922         if (rte_kvargs_process(kvlist, floating_veb_key,
 923                                i40e_check_floating_handler, NULL) < 0) {
 924                 rte_kvargs_free(kvlist);
 925                 return 0;
 926         }
 927         rte_kvargs_free(kvlist);
 928
 929         return 1;
 930 }
 931
 932 static void
 933 config_floating_veb(struct rte_eth_dev *dev)
 934 {
 935         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 936         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 938
 939         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 940
 941         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 942                 pf->floating_veb =
 943                         is_floating_veb_supported(pci_dev->device.devargs);
 944                 config_vf_floating_veb(pci_dev->device.devargs,
 945                                        pf->floating_veb,
 946                                        pf->floating_veb_list);
 947         } else {
 948                 pf->floating_veb = false;
 949         }
 950 }
 951
 952 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 953 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 954
 955 static int
 956 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 957 {
 958         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 959         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 960         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 961         int ret;
 962
 963         struct rte_hash_parameters ethertype_hash_params = {
 964                 .name = ethertype_hash_name,
 965                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 966                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 967                 .hash_func = rte_hash_crc,
 968                 .hash_func_init_val = 0,
 969                 .socket_id = rte_socket_id(),
 970         };
 971
 972         /* Initialize ethertype filter rule list and hash */
 973         TAILQ_INIT(&ethertype_rule->ethertype_list);
 974         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 975                  "ethertype_%s", dev->device->name);
 976         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 977         if (!ethertype_rule->hash_table) {
 978                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 979                 return -EINVAL;
 980         }
 981         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 982                                        sizeof(struct i40e_ethertype_filter *) *
 983                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 984                                        0);
 985         if (!ethertype_rule->hash_map) {
 986                 PMD_INIT_LOG(ERR,
 987                              "Failed to allocate memory for ethertype hash map!");
 988                 ret = -ENOMEM;
 989                 goto err_ethertype_hash_map_alloc;
 990         }
 991
 992         return 0;
 993
 994 err_ethertype_hash_map_alloc:
 995         rte_hash_free(ethertype_rule->hash_table);
 996
 997         return ret;
 998 }
 999
1000 static int
1001 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1002 {
1003         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1004         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1005         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1006         int ret;
1007
1008         struct rte_hash_parameters tunnel_hash_params = {
1009                 .name = tunnel_hash_name,
1010                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1011                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1012                 .hash_func = rte_hash_crc,
1013                 .hash_func_init_val = 0,
1014                 .socket_id = rte_socket_id(),
1015         };
1016
1017         /* Initialize tunnel filter rule list and hash */
1018         TAILQ_INIT(&tunnel_rule->tunnel_list);
1019         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1020                  "tunnel_%s", dev->device->name);
1021         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1022         if (!tunnel_rule->hash_table) {
1023                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1024                 return -EINVAL;
1025         }
1026         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1027                                     sizeof(struct i40e_tunnel_filter *) *
1028                                     I40E_MAX_TUNNEL_FILTER_NUM,
1029                                     0);
1030         if (!tunnel_rule->hash_map) {
1031                 PMD_INIT_LOG(ERR,
1032                              "Failed to allocate memory for tunnel hash map!");
1033                 ret = -ENOMEM;
1034                 goto err_tunnel_hash_map_alloc;
1035         }
1036
1037         return 0;
1038
1039 err_tunnel_hash_map_alloc:
1040         rte_hash_free(tunnel_rule->hash_table);
1041
1042         return ret;
1043 }
1044
1045 static int
1046 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1047 {
1048         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1049         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1050         struct i40e_fdir_info *fdir_info = &pf->fdir;
1051         char fdir_hash_name[RTE_HASH_NAMESIZE];
1052         uint32_t alloc = hw->func_caps.fd_filters_guaranteed;
1053         uint32_t best = hw->func_caps.fd_filters_best_effort;
1054         int ret;
1055
1056         struct rte_hash_parameters fdir_hash_params = {
1057                 .name = fdir_hash_name,
1058                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1059                 .key_len = sizeof(struct i40e_fdir_input),
1060                 .hash_func = rte_hash_crc,
1061                 .hash_func_init_val = 0,
1062                 .socket_id = rte_socket_id(),
1063         };
1064
1065         /* Initialize flow director filter rule list and hash */
1066         TAILQ_INIT(&fdir_info->fdir_list);
1067         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1068                  "fdir_%s", dev->device->name);
1069         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1070         if (!fdir_info->hash_table) {
1071                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1072                 return -EINVAL;
1073         }
1074
1075         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1076                                           sizeof(struct i40e_fdir_filter *) *
1077                                           I40E_MAX_FDIR_FILTER_NUM,
1078                                           0);
1079         if (!fdir_info->hash_map) {
1080                 PMD_INIT_LOG(ERR,
1081                              "Failed to allocate memory for fdir hash map!");
1082                 ret = -ENOMEM;
1083                 goto err_fdir_hash_map_alloc;
1084         }
1085
1086         fdir_info->fdir_space_size = alloc + best;
1087         fdir_info->fdir_actual_cnt = 0;
1088         fdir_info->fdir_guarantee_total_space = alloc;
1089         fdir_info->fdir_guarantee_free_space =
1090                 fdir_info->fdir_guarantee_total_space;
1091
1092         PMD_DRV_LOG(INFO, "FDIR guarantee space: %u, best_effort space %u.", alloc, best);
1093
1094         return 0;
1095
1096 err_fdir_hash_map_alloc:
1097         rte_hash_free(fdir_info->hash_table);
1098
1099         return ret;
1100 }
1101
1102 static void
1103 i40e_init_customized_info(struct i40e_pf *pf)
1104 {
1105         int i;
1106
1107         /* Initialize customized pctype */
1108         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1109                 pf->customized_pctype[i].index = i;
1110                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1111                 pf->customized_pctype[i].valid = false;
1112         }
1113
1114         pf->gtp_support = false;
1115         pf->esp_support = false;
1116 }
1117
1118 static void
1119 i40e_init_filter_invalidation(struct i40e_pf *pf)
1120 {
1121         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1122         struct i40e_fdir_info *fdir_info = &pf->fdir;
1123         uint32_t glqf_ctl_reg = 0;
1124
1125         glqf_ctl_reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
1126         if (!pf->support_multi_driver) {
1127                 fdir_info->fdir_invalprio = 1;
1128                 glqf_ctl_reg |= I40E_GLQF_CTL_INVALPRIO_MASK;
1129                 PMD_DRV_LOG(INFO, "FDIR INVALPRIO set to guaranteed first");
1130                 i40e_write_rx_ctl(hw, I40E_GLQF_CTL, glqf_ctl_reg);
1131         } else {
1132                 if (glqf_ctl_reg & I40E_GLQF_CTL_INVALPRIO_MASK) {
1133                         fdir_info->fdir_invalprio = 1;
1134                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: guaranteed first");
1135                 } else {
1136                         fdir_info->fdir_invalprio = 0;
1137                         PMD_DRV_LOG(INFO, "FDIR INVALPRIO is: shared first");
1138                 }
1139         }
1140 }
1141
1142 void
1143 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1144 {
1145         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1146         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1147         struct i40e_queue_regions *info = &pf->queue_region;
1148         uint16_t i;
1149
1150         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1151                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1152
1153         memset(info, 0, sizeof(struct i40e_queue_regions));
1154 }
1155
1156 static int
1157 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1158                                const char *value,
1159                                void *opaque)
1160 {
1161         struct i40e_pf *pf;
1162         unsigned long support_multi_driver;
1163         char *end;
1164
1165         pf = (struct i40e_pf *)opaque;
1166
1167         errno = 0;
1168         support_multi_driver = strtoul(value, &end, 10);
1169         if (errno != 0 || end == value || *end != 0) {
1170                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1171                 return -(EINVAL);
1172         }
1173
1174         if (support_multi_driver == 1 || support_multi_driver == 0)
1175                 pf->support_multi_driver = (bool)support_multi_driver;
1176         else
1177                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1178                             "enable global configuration by default."
1179                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1180         return 0;
1181 }
1182
1183 static int
1184 i40e_support_multi_driver(struct rte_eth_dev *dev)
1185 {
1186         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1187         struct rte_kvargs *kvlist;
1188         int kvargs_count;
1189
1190         /* Enable global configuration by default */
1191         pf->support_multi_driver = false;
1192
1193         if (!dev->device->devargs)
1194                 return 0;
1195
1196         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1197         if (!kvlist)
1198                 return -EINVAL;
1199
1200         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1201         if (!kvargs_count) {
1202                 rte_kvargs_free(kvlist);
1203                 return 0;
1204         }
1205
1206         if (kvargs_count > 1)
1207                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1208                             "the first invalid or last valid one is used !",
1209                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1210
1211         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1212                                i40e_parse_multi_drv_handler, pf) < 0) {
1213                 rte_kvargs_free(kvlist);
1214                 return -EINVAL;
1215         }
1216
1217         rte_kvargs_free(kvlist);
1218         return 0;
1219 }
1220
1221 static int
1222 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1223                                     uint32_t reg_addr, uint64_t reg_val,
1224                                     struct i40e_asq_cmd_details *cmd_details)
1225 {
1226         uint64_t ori_reg_val;
1227         struct rte_eth_dev *dev;
1228         int ret;
1229
1230         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1231         if (ret != I40E_SUCCESS) {
1232                 PMD_DRV_LOG(ERR,
1233                             "Fail to debug read from 0x%08x",
1234                             reg_addr);
1235                 return -EIO;
1236         }
1237         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1238
1239         if (ori_reg_val != reg_val)
1240                 PMD_DRV_LOG(WARNING,
1241                             "i40e device %s changed global register [0x%08x]."
1242                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1243                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1244
1245         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1246 }
1247
1248 static int
1249 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1250                                 const char *value,
1251                                 void *opaque)
1252 {
1253         struct i40e_adapter *ad = opaque;
1254         int use_latest_vec;
1255
1256         use_latest_vec = atoi(value);
1257
1258         if (use_latest_vec != 0 && use_latest_vec != 1)
1259                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1260
1261         ad->use_latest_vec = (uint8_t)use_latest_vec;
1262
1263         return 0;
1264 }
1265
1266 static int
1267 i40e_use_latest_vec(struct rte_eth_dev *dev)
1268 {
1269         struct i40e_adapter *ad =
1270                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1271         struct rte_kvargs *kvlist;
1272         int kvargs_count;
1273
1274         ad->use_latest_vec = false;
1275
1276         if (!dev->device->devargs)
1277                 return 0;
1278
1279         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1280         if (!kvlist)
1281                 return -EINVAL;
1282
1283         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1284         if (!kvargs_count) {
1285                 rte_kvargs_free(kvlist);
1286                 return 0;
1287         }
1288
1289         if (kvargs_count > 1)
1290                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1291                             "the first invalid or last valid one is used !",
1292                             ETH_I40E_USE_LATEST_VEC);
1293
1294         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1295                                 i40e_parse_latest_vec_handler, ad) < 0) {
1296                 rte_kvargs_free(kvlist);
1297                 return -EINVAL;
1298         }
1299
1300         rte_kvargs_free(kvlist);
1301         return 0;
1302 }
1303
1304 static int
1305 read_vf_msg_config(__rte_unused const char *key,
1306                                const char *value,
1307                                void *opaque)
1308 {
1309         struct i40e_vf_msg_cfg *cfg = opaque;
1310
1311         if (sscanf(value, "%u@%u:%u", &cfg->max_msg, &cfg->period,
1312                         &cfg->ignore_second) != 3) {
1313                 memset(cfg, 0, sizeof(*cfg));
1314                 PMD_DRV_LOG(ERR, "format error! example: "
1315                                 "%s=60@120:180", ETH_I40E_VF_MSG_CFG);
1316                 return -EINVAL;
1317         }
1318
1319         /*
1320          * If the message validation function been enabled, the 'period'
1321          * and 'ignore_second' must greater than 0.
1322          */
1323         if (cfg->max_msg && (!cfg->period || !cfg->ignore_second)) {
1324                 memset(cfg, 0, sizeof(*cfg));
1325                 PMD_DRV_LOG(ERR, "%s error! the second and third"
1326                                 " number must be greater than 0!",
1327                                 ETH_I40E_VF_MSG_CFG);
1328                 return -EINVAL;
1329         }
1330
1331         return 0;
1332 }
1333
1334 static int
1335 i40e_parse_vf_msg_config(struct rte_eth_dev *dev,
1336                 struct i40e_vf_msg_cfg *msg_cfg)
1337 {
1338         struct rte_kvargs *kvlist;
1339         int kvargs_count;
1340         int ret = 0;
1341
1342         memset(msg_cfg, 0, sizeof(*msg_cfg));
1343
1344         if (!dev->device->devargs)
1345                 return ret;
1346
1347         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1348         if (!kvlist)
1349                 return -EINVAL;
1350
1351         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_VF_MSG_CFG);
1352         if (!kvargs_count)
1353                 goto free_end;
1354
1355         if (kvargs_count > 1) {
1356                 PMD_DRV_LOG(ERR, "More than one argument \"%s\"!",
1357                                 ETH_I40E_VF_MSG_CFG);
1358                 ret = -EINVAL;
1359                 goto free_end;
1360         }
1361
1362         if (rte_kvargs_process(kvlist, ETH_I40E_VF_MSG_CFG,
1363                         read_vf_msg_config, msg_cfg) < 0)
1364                 ret = -EINVAL;
1365
1366 free_end:
1367         rte_kvargs_free(kvlist);
1368         return ret;
1369 }
1370
1371 #define I40E_ALARM_INTERVAL 50000 /* us */
1372
1373 static int
1374 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1375 {
1376         struct rte_pci_device *pci_dev;
1377         struct rte_intr_handle *intr_handle;
1378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1380         struct i40e_vsi *vsi;
1381         int ret;
1382         uint32_t len, val;
1383         uint8_t aq_fail = 0;
1384
1385         PMD_INIT_FUNC_TRACE();
1386
1387         dev->dev_ops = &i40e_eth_dev_ops;
1388         dev->rx_pkt_burst = i40e_recv_pkts;
1389         dev->tx_pkt_burst = i40e_xmit_pkts;
1390         dev->tx_pkt_prepare = i40e_prep_pkts;
1391
1392         /* for secondary processes, we don't initialise any further as primary
1393          * has already done this work. Only check we don't need a different
1394          * RX function */
1395         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1396                 i40e_set_rx_function(dev);
1397                 i40e_set_tx_function(dev);
1398                 return 0;
1399         }
1400         i40e_set_default_ptype_table(dev);
1401         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1402         intr_handle = &pci_dev->intr_handle;
1403
1404         rte_eth_copy_pci_info(dev, pci_dev);
1405
1406         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1407         pf->adapter->eth_dev = dev;
1408         pf->dev_data = dev->data;
1409
1410         hw->back = I40E_PF_TO_ADAPTER(pf);
1411         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1412         if (!hw->hw_addr) {
1413                 PMD_INIT_LOG(ERR,
1414                         "Hardware is not available, as address is NULL");
1415                 return -ENODEV;
1416         }
1417
1418         hw->vendor_id = pci_dev->id.vendor_id;
1419         hw->device_id = pci_dev->id.device_id;
1420         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1421         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1422         hw->bus.device = pci_dev->addr.devid;
1423         hw->bus.func = pci_dev->addr.function;
1424         hw->adapter_stopped = 0;
1425         hw->adapter_closed = 0;
1426
1427         /* Init switch device pointer */
1428         hw->switch_dev = NULL;
1429
1430         /*
1431          * Switch Tag value should not be identical to either the First Tag
1432          * or Second Tag values. So set something other than common Ethertype
1433          * for internal switching.
1434          */
1435         hw->switch_tag = 0xffff;
1436
1437         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1438         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1439                 PMD_INIT_LOG(ERR, "\nERROR: "
1440                         "Firmware recovery mode detected. Limiting functionality.\n"
1441                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1442                         "User Guide for details on firmware recovery mode.");
1443                 return -EIO;
1444         }
1445
1446         i40e_parse_vf_msg_config(dev, &pf->vf_msg_cfg);
1447         /* Check if need to support multi-driver */
1448         i40e_support_multi_driver(dev);
1449         /* Check if users want the latest supported vec path */
1450         i40e_use_latest_vec(dev);
1451
1452         /* Make sure all is clean before doing PF reset */
1453         i40e_clear_hw(hw);
1454
1455         /* Reset here to make sure all is clean for each PF */
1456         ret = i40e_pf_reset(hw);
1457         if (ret) {
1458                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1459                 return ret;
1460         }
1461
1462         /* Initialize the shared code (base driver) */
1463         ret = i40e_init_shared_code(hw);
1464         if (ret) {
1465                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1466                 return ret;
1467         }
1468
1469         /* Initialize the parameters for adminq */
1470         i40e_init_adminq_parameter(hw);
1471         ret = i40e_init_adminq(hw);
1472         if (ret != I40E_SUCCESS) {
1473                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1474                 return -EIO;
1475         }
1476         /* Firmware of SFP x722 does not support adminq option */
1477         if (hw->device_id == I40E_DEV_ID_SFP_X722)
1478                 hw->flags &= ~I40E_HW_FLAG_802_1AD_CAPABLE;
1479
1480         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1481                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1482                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1483                      ((hw->nvm.version >> 12) & 0xf),
1484                      ((hw->nvm.version >> 4) & 0xff),
1485                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1486
1487         /* Initialize the hardware */
1488         i40e_hw_init(dev);
1489
1490         i40e_config_automask(pf);
1491
1492         i40e_set_default_pctype_table(dev);
1493
1494         /*
1495          * To work around the NVM issue, initialize registers
1496          * for packet type of QinQ by software.
1497          * It should be removed once issues are fixed in NVM.
1498          */
1499         if (!pf->support_multi_driver)
1500                 i40e_GLQF_reg_init(hw);
1501
1502         /* Initialize the input set for filters (hash and fd) to default value */
1503         i40e_filter_input_set_init(pf);
1504
1505         /* initialise the L3_MAP register */
1506         if (!pf->support_multi_driver) {
1507                 ret = i40e_aq_debug_write_global_register(hw,
1508                                                    I40E_GLQF_L3_MAP(40),
1509                                                    0x00000028,  NULL);
1510                 if (ret)
1511                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1512                                      ret);
1513                 PMD_INIT_LOG(DEBUG,
1514                              "Global register 0x%08x is changed with 0x28",
1515                              I40E_GLQF_L3_MAP(40));
1516         }
1517
1518         /* Need the special FW version to support floating VEB */
1519         config_floating_veb(dev);
1520         /* Clear PXE mode */
1521         i40e_clear_pxe_mode(hw);
1522         i40e_dev_sync_phy_type(hw);
1523
1524         /*
1525          * On X710, performance number is far from the expectation on recent
1526          * firmware versions. The fix for this issue may not be integrated in
1527          * the following firmware version. So the workaround in software driver
1528          * is needed. It needs to modify the initial values of 3 internal only
1529          * registers. Note that the workaround can be removed when it is fixed
1530          * in firmware in the future.
1531          */
1532         i40e_configure_registers(hw);
1533
1534         /* Get hw capabilities */
1535         ret = i40e_get_cap(hw);
1536         if (ret != I40E_SUCCESS) {
1537                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1538                 goto err_get_capabilities;
1539         }
1540
1541         /* Initialize parameters for PF */
1542         ret = i40e_pf_parameter_init(dev);
1543         if (ret != 0) {
1544                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1545                 goto err_parameter_init;
1546         }
1547
1548         /* Initialize the queue management */
1549         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1550         if (ret < 0) {
1551                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1552                 goto err_qp_pool_init;
1553         }
1554         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1555                                 hw->func_caps.num_msix_vectors - 1);
1556         if (ret < 0) {
1557                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1558                 goto err_msix_pool_init;
1559         }
1560
1561         /* Initialize lan hmc */
1562         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1563                                 hw->func_caps.num_rx_qp, 0, 0);
1564         if (ret != I40E_SUCCESS) {
1565                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1566                 goto err_init_lan_hmc;
1567         }
1568
1569         /* Configure lan hmc */
1570         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1571         if (ret != I40E_SUCCESS) {
1572                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1573                 goto err_configure_lan_hmc;
1574         }
1575
1576         /* Get and check the mac address */
1577         i40e_get_mac_addr(hw, hw->mac.addr);
1578         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1579                 PMD_INIT_LOG(ERR, "mac address is not valid");
1580                 ret = -EIO;
1581                 goto err_get_mac_addr;
1582         }
1583         /* Copy the permanent MAC address */
1584         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1585                         (struct rte_ether_addr *)hw->mac.perm_addr);
1586
1587         /* Disable flow control */
1588         hw->fc.requested_mode = I40E_FC_NONE;
1589         i40e_set_fc(hw, &aq_fail, TRUE);
1590
1591         /* Set the global registers with default ether type value */
1592         if (!pf->support_multi_driver) {
1593                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1594                                          RTE_ETHER_TYPE_VLAN);
1595                 if (ret != I40E_SUCCESS) {
1596                         PMD_INIT_LOG(ERR,
1597                                      "Failed to set the default outer "
1598                                      "VLAN ether type");
1599                         goto err_setup_pf_switch;
1600                 }
1601         }
1602
1603         /* PF setup, which includes VSI setup */
1604         ret = i40e_pf_setup(pf);
1605         if (ret) {
1606                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1607                 goto err_setup_pf_switch;
1608         }
1609
1610         vsi = pf->main_vsi;
1611
1612         /* Disable double vlan by default */
1613         i40e_vsi_config_double_vlan(vsi, FALSE);
1614
1615         /* Disable S-TAG identification when floating_veb is disabled */
1616         if (!pf->floating_veb) {
1617                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1618                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1619                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1620                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1621                 }
1622         }
1623
1624         if (!vsi->max_macaddrs)
1625                 len = RTE_ETHER_ADDR_LEN;
1626         else
1627                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1628
1629         /* Should be after VSI initialized */
1630         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1631         if (!dev->data->mac_addrs) {
1632                 PMD_INIT_LOG(ERR,
1633                         "Failed to allocated memory for storing mac address");
1634                 goto err_mac_alloc;
1635         }
1636         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1637                                         &dev->data->mac_addrs[0]);
1638
1639         /* Pass the information to the rte_eth_dev_close() that it should also
1640          * release the private port resources.
1641          */
1642         dev->data->dev_flags |= RTE_ETH_DEV_CLOSE_REMOVE;
1643
1644         /* Init dcb to sw mode by default */
1645         ret = i40e_dcb_init_configure(dev, TRUE);
1646         if (ret != I40E_SUCCESS) {
1647                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1648                 pf->flags &= ~I40E_FLAG_DCB;
1649         }
1650         /* Update HW struct after DCB configuration */
1651         i40e_get_cap(hw);
1652
1653         /* initialize pf host driver to setup SRIOV resource if applicable */
1654         i40e_pf_host_init(dev);
1655
1656         /* register callback func to eal lib */
1657         rte_intr_callback_register(intr_handle,
1658                                    i40e_dev_interrupt_handler, dev);
1659
1660         /* configure and enable device interrupt */
1661         i40e_pf_config_irq0(hw, TRUE);
1662         i40e_pf_enable_irq0(hw);
1663
1664         /* enable uio intr after callback register */
1665         rte_intr_enable(intr_handle);
1666
1667         /* By default disable flexible payload in global configuration */
1668         if (!pf->support_multi_driver)
1669                 i40e_flex_payload_reg_set_default(hw);
1670
1671         /*
1672          * Add an ethertype filter to drop all flow control frames transmitted
1673          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1674          * frames to wire.
1675          */
1676         i40e_add_tx_flow_control_drop_filter(pf);
1677
1678         /* Set the max frame size to 0x2600 by default,
1679          * in case other drivers changed the default value.
1680          */
1681         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, false, 0, NULL);
1682
1683         /* initialize mirror rule list */
1684         TAILQ_INIT(&pf->mirror_list);
1685
1686         /* initialize RSS rule list */
1687         TAILQ_INIT(&pf->rss_config_list);
1688
1689         /* initialize Traffic Manager configuration */
1690         i40e_tm_conf_init(dev);
1691
1692         /* Initialize customized information */
1693         i40e_init_customized_info(pf);
1694
1695         /* Initialize the filter invalidation configuration */
1696         i40e_init_filter_invalidation(pf);
1697
1698         ret = i40e_init_ethtype_filter_list(dev);
1699         if (ret < 0)
1700                 goto err_init_ethtype_filter_list;
1701         ret = i40e_init_tunnel_filter_list(dev);
1702         if (ret < 0)
1703                 goto err_init_tunnel_filter_list;
1704         ret = i40e_init_fdir_filter_list(dev);
1705         if (ret < 0)
1706                 goto err_init_fdir_filter_list;
1707
1708         /* initialize queue region configuration */
1709         i40e_init_queue_region_conf(dev);
1710
1711         /* initialize RSS configuration from rte_flow */
1712         memset(&pf->rss_info, 0,
1713                 sizeof(struct i40e_rte_flow_rss_conf));
1714
1715         /* reset all stats of the device, including pf and main vsi */
1716         i40e_dev_stats_reset(dev);
1717
1718         return 0;
1719
1720 err_init_fdir_filter_list:
1721         rte_free(pf->tunnel.hash_table);
1722         rte_free(pf->tunnel.hash_map);
1723 err_init_tunnel_filter_list:
1724         rte_free(pf->ethertype.hash_table);
1725         rte_free(pf->ethertype.hash_map);
1726 err_init_ethtype_filter_list:
1727         rte_free(dev->data->mac_addrs);
1728         dev->data->mac_addrs = NULL;
1729 err_mac_alloc:
1730         i40e_vsi_release(pf->main_vsi);
1731 err_setup_pf_switch:
1732 err_get_mac_addr:
1733 err_configure_lan_hmc:
1734         (void)i40e_shutdown_lan_hmc(hw);
1735 err_init_lan_hmc:
1736         i40e_res_pool_destroy(&pf->msix_pool);
1737 err_msix_pool_init:
1738         i40e_res_pool_destroy(&pf->qp_pool);
1739 err_qp_pool_init:
1740 err_parameter_init:
1741 err_get_capabilities:
1742         (void)i40e_shutdown_adminq(hw);
1743
1744         return ret;
1745 }
1746
1747 static void
1748 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1749 {
1750         struct i40e_ethertype_filter *p_ethertype;
1751         struct i40e_ethertype_rule *ethertype_rule;
1752
1753         ethertype_rule = &pf->ethertype;
1754         /* Remove all ethertype filter rules and hash */
1755         if (ethertype_rule->hash_map)
1756                 rte_free(ethertype_rule->hash_map);
1757         if (ethertype_rule->hash_table)
1758                 rte_hash_free(ethertype_rule->hash_table);
1759
1760         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1761                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1762                              p_ethertype, rules);
1763                 rte_free(p_ethertype);
1764         }
1765 }
1766
1767 static void
1768 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1769 {
1770         struct i40e_tunnel_filter *p_tunnel;
1771         struct i40e_tunnel_rule *tunnel_rule;
1772
1773         tunnel_rule = &pf->tunnel;
1774         /* Remove all tunnel director rules and hash */
1775         if (tunnel_rule->hash_map)
1776                 rte_free(tunnel_rule->hash_map);
1777         if (tunnel_rule->hash_table)
1778                 rte_hash_free(tunnel_rule->hash_table);
1779
1780         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1781                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1782                 rte_free(p_tunnel);
1783         }
1784 }
1785
1786 static void
1787 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1788 {
1789         struct i40e_fdir_filter *p_fdir;
1790         struct i40e_fdir_info *fdir_info;
1791
1792         fdir_info = &pf->fdir;
1793         /* Remove all flow director rules and hash */
1794         if (fdir_info->hash_map)
1795                 rte_free(fdir_info->hash_map);
1796         if (fdir_info->hash_table)
1797                 rte_hash_free(fdir_info->hash_table);
1798
1799         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1800                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1801                 rte_free(p_fdir);
1802         }
1803 }
1804
1805 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1806 {
1807         /*
1808          * Disable by default flexible payload
1809          * for corresponding L2/L3/L4 layers.
1810          */
1811         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1812         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1813         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1814 }
1815
1816 static int
1817 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1818 {
1819         struct i40e_hw *hw;
1820
1821         PMD_INIT_FUNC_TRACE();
1822
1823         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1824                 return 0;
1825
1826         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827
1828         if (hw->adapter_closed == 0)
1829                 i40e_dev_close(dev);
1830
1831         return 0;
1832 }
1833
1834 static int
1835 i40e_dev_configure(struct rte_eth_dev *dev)
1836 {
1837         struct i40e_adapter *ad =
1838                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1839         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1840         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1841         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1842         int i, ret;
1843
1844         ret = i40e_dev_sync_phy_type(hw);
1845         if (ret)
1846                 return ret;
1847
1848         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1849          * bulk allocation or vector Rx preconditions we will reset it.
1850          */
1851         ad->rx_bulk_alloc_allowed = true;
1852         ad->rx_vec_allowed = true;
1853         ad->tx_simple_allowed = true;
1854         ad->tx_vec_allowed = true;
1855
1856         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
1857                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
1858
1859         /* Only legacy filter API needs the following fdir config. So when the
1860          * legacy filter API is deprecated, the following codes should also be
1861          * removed.
1862          */
1863         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1864                 ret = i40e_fdir_setup(pf);
1865                 if (ret != I40E_SUCCESS) {
1866                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1867                         return -ENOTSUP;
1868                 }
1869                 ret = i40e_fdir_configure(dev);
1870                 if (ret < 0) {
1871                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1872                         goto err;
1873                 }
1874         } else
1875                 i40e_fdir_teardown(pf);
1876
1877         ret = i40e_dev_init_vlan(dev);
1878         if (ret < 0)
1879                 goto err;
1880
1881         /* VMDQ setup.
1882          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1883          *  RSS setting have different requirements.
1884          *  General PMD driver call sequence are NIC init, configure,
1885          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1886          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1887          *  applicable. So, VMDQ setting has to be done before
1888          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1889          *  For RSS setting, it will try to calculate actual configured RX queue
1890          *  number, which will be available after rx_queue_setup(). dev_start()
1891          *  function is good to place RSS setup.
1892          */
1893         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1894                 ret = i40e_vmdq_setup(dev);
1895                 if (ret)
1896                         goto err;
1897         }
1898
1899         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1900                 ret = i40e_dcb_setup(dev);
1901                 if (ret) {
1902                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1903                         goto err_dcb;
1904                 }
1905         }
1906
1907         TAILQ_INIT(&pf->flow_list);
1908
1909         return 0;
1910
1911 err_dcb:
1912         /* need to release vmdq resource if exists */
1913         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1914                 i40e_vsi_release(pf->vmdq[i].vsi);
1915                 pf->vmdq[i].vsi = NULL;
1916         }
1917         rte_free(pf->vmdq);
1918         pf->vmdq = NULL;
1919 err:
1920         /* Need to release fdir resource if exists.
1921          * Only legacy filter API needs the following fdir config. So when the
1922          * legacy filter API is deprecated, the following code should also be
1923          * removed.
1924          */
1925         i40e_fdir_teardown(pf);
1926         return ret;
1927 }
1928
1929 void
1930 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1931 {
1932         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1933         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1934         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1935         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1936         uint16_t msix_vect = vsi->msix_intr;
1937         uint16_t i;
1938
1939         for (i = 0; i < vsi->nb_qps; i++) {
1940                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1941                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1942                 rte_wmb();
1943         }
1944
1945         if (vsi->type != I40E_VSI_SRIOV) {
1946                 if (!rte_intr_allow_others(intr_handle)) {
1947                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1948                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1949                         I40E_WRITE_REG(hw,
1950                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1951                                        0);
1952                 } else {
1953                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1954                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1955                         I40E_WRITE_REG(hw,
1956                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1957                                                        msix_vect - 1), 0);
1958                 }
1959         } else {
1960                 uint32_t reg;
1961                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1962                         vsi->user_param + (msix_vect - 1);
1963
1964                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1965                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1966         }
1967         I40E_WRITE_FLUSH(hw);
1968 }
1969
1970 static void
1971 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1972                        int base_queue, int nb_queue,
1973                        uint16_t itr_idx)
1974 {
1975         int i;
1976         uint32_t val;
1977         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1978         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1979
1980         /* Bind all RX queues to allocated MSIX interrupt */
1981         for (i = 0; i < nb_queue; i++) {
1982                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1983                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1984                         ((base_queue + i + 1) <<
1985                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1986                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1987                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1988
1989                 if (i == nb_queue - 1)
1990                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1991                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1992         }
1993
1994         /* Write first RX queue to Link list register as the head element */
1995         if (vsi->type != I40E_VSI_SRIOV) {
1996                 uint16_t interval =
1997                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1998
1999                 if (msix_vect == I40E_MISC_VEC_ID) {
2000                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
2001                                        (base_queue <<
2002                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2003                                        (0x0 <<
2004                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2005                         I40E_WRITE_REG(hw,
2006                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
2007                                        interval);
2008                 } else {
2009                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
2010                                        (base_queue <<
2011                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2012                                        (0x0 <<
2013                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2014                         I40E_WRITE_REG(hw,
2015                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
2016                                                        msix_vect - 1),
2017                                        interval);
2018                 }
2019         } else {
2020                 uint32_t reg;
2021
2022                 if (msix_vect == I40E_MISC_VEC_ID) {
2023                         I40E_WRITE_REG(hw,
2024                                        I40E_VPINT_LNKLST0(vsi->user_param),
2025                                        (base_queue <<
2026                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
2027                                        (0x0 <<
2028                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
2029                 } else {
2030                         /* num_msix_vectors_vf needs to minus irq0 */
2031                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
2032                                 vsi->user_param + (msix_vect - 1);
2033
2034                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
2035                                        (base_queue <<
2036                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
2037                                        (0x0 <<
2038                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
2039                 }
2040         }
2041
2042         I40E_WRITE_FLUSH(hw);
2043 }
2044
2045 void
2046 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
2047 {
2048         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2049         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2050         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2051         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2052         uint16_t msix_vect = vsi->msix_intr;
2053         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
2054         uint16_t queue_idx = 0;
2055         int record = 0;
2056         int i;
2057
2058         for (i = 0; i < vsi->nb_qps; i++) {
2059                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
2060                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
2061         }
2062
2063         /* VF bind interrupt */
2064         if (vsi->type == I40E_VSI_SRIOV) {
2065                 __vsi_queues_bind_intr(vsi, msix_vect,
2066                                        vsi->base_queue, vsi->nb_qps,
2067                                        itr_idx);
2068                 return;
2069         }
2070
2071         /* PF & VMDq bind interrupt */
2072         if (rte_intr_dp_is_en(intr_handle)) {
2073                 if (vsi->type == I40E_VSI_MAIN) {
2074                         queue_idx = 0;
2075                         record = 1;
2076                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2077                         struct i40e_vsi *main_vsi =
2078                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2079                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2080                         record = 1;
2081                 }
2082         }
2083
2084         for (i = 0; i < vsi->nb_used_qps; i++) {
2085                 if (nb_msix <= 1) {
2086                         if (!rte_intr_allow_others(intr_handle))
2087                                 /* allow to share MISC_VEC_ID */
2088                                 msix_vect = I40E_MISC_VEC_ID;
2089
2090                         /* no enough msix_vect, map all to one */
2091                         __vsi_queues_bind_intr(vsi, msix_vect,
2092                                                vsi->base_queue + i,
2093                                                vsi->nb_used_qps - i,
2094                                                itr_idx);
2095                         for (; !!record && i < vsi->nb_used_qps; i++)
2096                                 intr_handle->intr_vec[queue_idx + i] =
2097                                         msix_vect;
2098                         break;
2099                 }
2100                 /* 1:1 queue/msix_vect mapping */
2101                 __vsi_queues_bind_intr(vsi, msix_vect,
2102                                        vsi->base_queue + i, 1,
2103                                        itr_idx);
2104                 if (!!record)
2105                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2106
2107                 msix_vect++;
2108                 nb_msix--;
2109         }
2110 }
2111
2112 static void
2113 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2114 {
2115         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2116         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2117         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2118         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2119         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2120         uint16_t msix_intr, i;
2121
2122         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2123                 for (i = 0; i < vsi->nb_msix; i++) {
2124                         msix_intr = vsi->msix_intr + i;
2125                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2126                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2127                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2128                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2129                 }
2130         else
2131                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2132                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2133                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2134                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2135
2136         I40E_WRITE_FLUSH(hw);
2137 }
2138
2139 static void
2140 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2141 {
2142         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2143         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2144         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2145         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2146         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2147         uint16_t msix_intr, i;
2148
2149         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2150                 for (i = 0; i < vsi->nb_msix; i++) {
2151                         msix_intr = vsi->msix_intr + i;
2152                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2153                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2154                 }
2155         else
2156                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2157                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2158
2159         I40E_WRITE_FLUSH(hw);
2160 }
2161
2162 static inline uint8_t
2163 i40e_parse_link_speeds(uint16_t link_speeds)
2164 {
2165         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2166
2167         if (link_speeds & ETH_LINK_SPEED_40G)
2168                 link_speed |= I40E_LINK_SPEED_40GB;
2169         if (link_speeds & ETH_LINK_SPEED_25G)
2170                 link_speed |= I40E_LINK_SPEED_25GB;
2171         if (link_speeds & ETH_LINK_SPEED_20G)
2172                 link_speed |= I40E_LINK_SPEED_20GB;
2173         if (link_speeds & ETH_LINK_SPEED_10G)
2174                 link_speed |= I40E_LINK_SPEED_10GB;
2175         if (link_speeds & ETH_LINK_SPEED_1G)
2176                 link_speed |= I40E_LINK_SPEED_1GB;
2177         if (link_speeds & ETH_LINK_SPEED_100M)
2178                 link_speed |= I40E_LINK_SPEED_100MB;
2179
2180         return link_speed;
2181 }
2182
2183 static int
2184 i40e_phy_conf_link(struct i40e_hw *hw,
2185                    uint8_t abilities,
2186                    uint8_t force_speed,
2187                    bool is_up)
2188 {
2189         enum i40e_status_code status;
2190         struct i40e_aq_get_phy_abilities_resp phy_ab;
2191         struct i40e_aq_set_phy_config phy_conf;
2192         enum i40e_aq_phy_type cnt;
2193         uint8_t avail_speed;
2194         uint32_t phy_type_mask = 0;
2195
2196         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2197                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2198                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2199                         I40E_AQ_PHY_FLAG_LOW_POWER;
2200         int ret = -ENOTSUP;
2201
2202         /* To get phy capabilities of available speeds. */
2203         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2204                                               NULL);
2205         if (status) {
2206                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2207                                 status);
2208                 return ret;
2209         }
2210         avail_speed = phy_ab.link_speed;
2211
2212         /* To get the current phy config. */
2213         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2214                                               NULL);
2215         if (status) {
2216                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2217                                 status);
2218                 return ret;
2219         }
2220
2221         /* If link needs to go up and it is in autoneg mode the speed is OK,
2222          * no need to set up again.
2223          */
2224         if (is_up && phy_ab.phy_type != 0 &&
2225                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2226                      phy_ab.link_speed != 0)
2227                 return I40E_SUCCESS;
2228
2229         memset(&phy_conf, 0, sizeof(phy_conf));
2230
2231         /* bits 0-2 use the values from get_phy_abilities_resp */
2232         abilities &= ~mask;
2233         abilities |= phy_ab.abilities & mask;
2234
2235         phy_conf.abilities = abilities;
2236
2237         /* If link needs to go up, but the force speed is not supported,
2238          * Warn users and config the default available speeds.
2239          */
2240         if (is_up && !(force_speed & avail_speed)) {
2241                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2242                 phy_conf.link_speed = avail_speed;
2243         } else {
2244                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2245         }
2246
2247         /* PHY type mask needs to include each type except PHY type extension */
2248         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2249                 phy_type_mask |= 1 << cnt;
2250
2251         /* use get_phy_abilities_resp value for the rest */
2252         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2253         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2254                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2255                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2256         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2257         phy_conf.eee_capability = phy_ab.eee_capability;
2258         phy_conf.eeer = phy_ab.eeer_val;
2259         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2260
2261         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2262                     phy_ab.abilities, phy_ab.link_speed);
2263         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2264                     phy_conf.abilities, phy_conf.link_speed);
2265
2266         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2267         if (status)
2268                 return ret;
2269
2270         return I40E_SUCCESS;
2271 }
2272
2273 static int
2274 i40e_apply_link_speed(struct rte_eth_dev *dev)
2275 {
2276         uint8_t speed;
2277         uint8_t abilities = 0;
2278         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2279         struct rte_eth_conf *conf = &dev->data->dev_conf;
2280
2281         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2282                      I40E_AQ_PHY_LINK_ENABLED;
2283
2284         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2285                 conf->link_speeds = ETH_LINK_SPEED_40G |
2286                                     ETH_LINK_SPEED_25G |
2287                                     ETH_LINK_SPEED_20G |
2288                                     ETH_LINK_SPEED_10G |
2289                                     ETH_LINK_SPEED_1G |
2290                                     ETH_LINK_SPEED_100M;
2291
2292                 abilities |= I40E_AQ_PHY_AN_ENABLED;
2293         } else {
2294                 abilities &= ~I40E_AQ_PHY_AN_ENABLED;
2295         }
2296         speed = i40e_parse_link_speeds(conf->link_speeds);
2297
2298         return i40e_phy_conf_link(hw, abilities, speed, true);
2299 }
2300
2301 static int
2302 i40e_dev_start(struct rte_eth_dev *dev)
2303 {
2304         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306         struct i40e_vsi *main_vsi = pf->main_vsi;
2307         int ret, i;
2308         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2309         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2310         uint32_t intr_vector = 0;
2311         struct i40e_vsi *vsi;
2312         uint16_t nb_rxq, nb_txq;
2313
2314         hw->adapter_stopped = 0;
2315
2316         rte_intr_disable(intr_handle);
2317
2318         if ((rte_intr_cap_multiple(intr_handle) ||
2319              !RTE_ETH_DEV_SRIOV(dev).active) &&
2320             dev->data->dev_conf.intr_conf.rxq != 0) {
2321                 intr_vector = dev->data->nb_rx_queues;
2322                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2323                 if (ret)
2324                         return ret;
2325         }
2326
2327         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2328                 intr_handle->intr_vec =
2329                         rte_zmalloc("intr_vec",
2330                                     dev->data->nb_rx_queues * sizeof(int),
2331                                     0);
2332                 if (!intr_handle->intr_vec) {
2333                         PMD_INIT_LOG(ERR,
2334                                 "Failed to allocate %d rx_queues intr_vec",
2335                                 dev->data->nb_rx_queues);
2336                         return -ENOMEM;
2337                 }
2338         }
2339
2340         /* Initialize VSI */
2341         ret = i40e_dev_rxtx_init(pf);
2342         if (ret != I40E_SUCCESS) {
2343                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2344                 return ret;
2345         }
2346
2347         /* Map queues with MSIX interrupt */
2348         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2349                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2350         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2351         i40e_vsi_enable_queues_intr(main_vsi);
2352
2353         /* Map VMDQ VSI queues with MSIX interrupt */
2354         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2355                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2356                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2357                                           I40E_ITR_INDEX_DEFAULT);
2358                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2359         }
2360
2361         /* enable FDIR MSIX interrupt */
2362         if (pf->fdir.fdir_vsi) {
2363                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2364                                           I40E_ITR_INDEX_NONE);
2365                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2366         }
2367
2368         /* Enable all queues which have been configured */
2369         for (nb_rxq = 0; nb_rxq < dev->data->nb_rx_queues; nb_rxq++) {
2370                 ret = i40e_dev_rx_queue_start(dev, nb_rxq);
2371                 if (ret)
2372                         goto rx_err;
2373         }
2374
2375         for (nb_txq = 0; nb_txq < dev->data->nb_tx_queues; nb_txq++) {
2376                 ret = i40e_dev_tx_queue_start(dev, nb_txq);
2377                 if (ret)
2378                         goto tx_err;
2379         }
2380
2381         /* Enable receiving broadcast packets */
2382         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2383         if (ret != I40E_SUCCESS)
2384                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2385
2386         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2387                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2388                                                 true, NULL);
2389                 if (ret != I40E_SUCCESS)
2390                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2391         }
2392
2393         /* Enable the VLAN promiscuous mode. */
2394         if (pf->vfs) {
2395                 for (i = 0; i < pf->vf_num; i++) {
2396                         vsi = pf->vfs[i].vsi;
2397                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2398                                                      true, NULL);
2399                 }
2400         }
2401
2402         /* Enable mac loopback mode */
2403         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2404             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2405                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2406                 if (ret != I40E_SUCCESS) {
2407                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2408                         goto tx_err;
2409                 }
2410         }
2411
2412         /* Apply link configure */
2413         ret = i40e_apply_link_speed(dev);
2414         if (I40E_SUCCESS != ret) {
2415                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2416                 goto tx_err;
2417         }
2418
2419         if (!rte_intr_allow_others(intr_handle)) {
2420                 rte_intr_callback_unregister(intr_handle,
2421                                              i40e_dev_interrupt_handler,
2422                                              (void *)dev);
2423                 /* configure and enable device interrupt */
2424                 i40e_pf_config_irq0(hw, FALSE);
2425                 i40e_pf_enable_irq0(hw);
2426
2427                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2428                         PMD_INIT_LOG(INFO,
2429                                 "lsc won't enable because of no intr multiplex");
2430         } else {
2431                 ret = i40e_aq_set_phy_int_mask(hw,
2432                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2433                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2434                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2435                 if (ret != I40E_SUCCESS)
2436                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2437
2438                 /* Call get_link_info aq commond to enable/disable LSE */
2439                 i40e_dev_link_update(dev, 0);
2440         }
2441
2442         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2443                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2444                                   i40e_dev_alarm_handler, dev);
2445         } else {
2446                 /* enable uio intr after callback register */
2447                 rte_intr_enable(intr_handle);
2448         }
2449
2450         i40e_filter_restore(pf);
2451
2452         if (pf->tm_conf.root && !pf->tm_conf.committed)
2453                 PMD_DRV_LOG(WARNING,
2454                             "please call hierarchy_commit() "
2455                             "before starting the port");
2456
2457         return I40E_SUCCESS;
2458
2459 tx_err:
2460         for (i = 0; i < nb_txq; i++)
2461                 i40e_dev_tx_queue_stop(dev, i);
2462 rx_err:
2463         for (i = 0; i < nb_rxq; i++)
2464                 i40e_dev_rx_queue_stop(dev, i);
2465
2466         return ret;
2467 }
2468
2469 static void
2470 i40e_dev_stop(struct rte_eth_dev *dev)
2471 {
2472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2473         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2474         struct i40e_vsi *main_vsi = pf->main_vsi;
2475         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2476         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2477         int i;
2478
2479         if (hw->adapter_stopped == 1)
2480                 return;
2481
2482         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2483                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2484                 rte_intr_enable(intr_handle);
2485         }
2486
2487         /* Disable all queues */
2488         for (i = 0; i < dev->data->nb_tx_queues; i++)
2489                 i40e_dev_tx_queue_stop(dev, i);
2490
2491         for (i = 0; i < dev->data->nb_rx_queues; i++)
2492                 i40e_dev_rx_queue_stop(dev, i);
2493
2494         /* un-map queues with interrupt registers */
2495         i40e_vsi_disable_queues_intr(main_vsi);
2496         i40e_vsi_queues_unbind_intr(main_vsi);
2497
2498         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2499                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2500                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2501         }
2502
2503         if (pf->fdir.fdir_vsi) {
2504                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2505                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2506         }
2507         /* Clear all queues and release memory */
2508         i40e_dev_clear_queues(dev);
2509
2510         /* Set link down */
2511         i40e_dev_set_link_down(dev);
2512
2513         if (!rte_intr_allow_others(intr_handle))
2514                 /* resume to the default handler */
2515                 rte_intr_callback_register(intr_handle,
2516                                            i40e_dev_interrupt_handler,
2517                                            (void *)dev);
2518
2519         /* Clean datapath event and queue/vec mapping */
2520         rte_intr_efd_disable(intr_handle);
2521         if (intr_handle->intr_vec) {
2522                 rte_free(intr_handle->intr_vec);
2523                 intr_handle->intr_vec = NULL;
2524         }
2525
2526         /* reset hierarchy commit */
2527         pf->tm_conf.committed = false;
2528
2529         hw->adapter_stopped = 1;
2530
2531         pf->adapter->rss_reta_updated = 0;
2532 }
2533
2534 static void
2535 i40e_dev_close(struct rte_eth_dev *dev)
2536 {
2537         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2538         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2539         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2540         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2541         struct i40e_mirror_rule *p_mirror;
2542         struct i40e_filter_control_settings settings;
2543         struct rte_flow *p_flow;
2544         uint32_t reg;
2545         int i;
2546         int ret;
2547         uint8_t aq_fail = 0;
2548         int retries = 0;
2549
2550         PMD_INIT_FUNC_TRACE();
2551
2552         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
2553         if (ret)
2554                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
2555
2556
2557         i40e_dev_stop(dev);
2558
2559         /* Remove all mirror rules */
2560         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2561                 ret = i40e_aq_del_mirror_rule(hw,
2562                                               pf->main_vsi->veb->seid,
2563                                               p_mirror->rule_type,
2564                                               p_mirror->entries,
2565                                               p_mirror->num_entries,
2566                                               p_mirror->id);
2567                 if (ret < 0)
2568                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2569                                     "status = %d, aq_err = %d.", ret,
2570                                     hw->aq.asq_last_status);
2571
2572                 /* remove mirror software resource anyway */
2573                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2574                 rte_free(p_mirror);
2575                 pf->nb_mirror_rule--;
2576         }
2577
2578         i40e_dev_free_queues(dev);
2579
2580         /* Disable interrupt */
2581         i40e_pf_disable_irq0(hw);
2582         rte_intr_disable(intr_handle);
2583
2584         /*
2585          * Only legacy filter API needs the following fdir config. So when the
2586          * legacy filter API is deprecated, the following code should also be
2587          * removed.
2588          */
2589         i40e_fdir_teardown(pf);
2590
2591         /* shutdown and destroy the HMC */
2592         i40e_shutdown_lan_hmc(hw);
2593
2594         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2595                 i40e_vsi_release(pf->vmdq[i].vsi);
2596                 pf->vmdq[i].vsi = NULL;
2597         }
2598         rte_free(pf->vmdq);
2599         pf->vmdq = NULL;
2600
2601         /* release all the existing VSIs and VEBs */
2602         i40e_vsi_release(pf->main_vsi);
2603
2604         /* shutdown the adminq */
2605         i40e_aq_queue_shutdown(hw, true);
2606         i40e_shutdown_adminq(hw);
2607
2608         i40e_res_pool_destroy(&pf->qp_pool);
2609         i40e_res_pool_destroy(&pf->msix_pool);
2610
2611         /* Disable flexible payload in global configuration */
2612         if (!pf->support_multi_driver)
2613                 i40e_flex_payload_reg_set_default(hw);
2614
2615         /* force a PF reset to clean anything leftover */
2616         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2617         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2618                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2619         I40E_WRITE_FLUSH(hw);
2620
2621         dev->dev_ops = NULL;
2622         dev->rx_pkt_burst = NULL;
2623         dev->tx_pkt_burst = NULL;
2624
2625         /* Clear PXE mode */
2626         i40e_clear_pxe_mode(hw);
2627
2628         /* Unconfigure filter control */
2629         memset(&settings, 0, sizeof(settings));
2630         ret = i40e_set_filter_control(hw, &settings);
2631         if (ret)
2632                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
2633                                         ret);
2634
2635         /* Disable flow control */
2636         hw->fc.requested_mode = I40E_FC_NONE;
2637         i40e_set_fc(hw, &aq_fail, TRUE);
2638
2639         /* uninitialize pf host driver */
2640         i40e_pf_host_uninit(dev);
2641
2642         do {
2643                 ret = rte_intr_callback_unregister(intr_handle,
2644                                 i40e_dev_interrupt_handler, dev);
2645                 if (ret >= 0 || ret == -ENOENT) {
2646                         break;
2647                 } else if (ret != -EAGAIN) {
2648                         PMD_INIT_LOG(ERR,
2649                                  "intr callback unregister failed: %d",
2650                                  ret);
2651                 }
2652                 i40e_msec_delay(500);
2653         } while (retries++ < 5);
2654
2655         i40e_rm_ethtype_filter_list(pf);
2656         i40e_rm_tunnel_filter_list(pf);
2657         i40e_rm_fdir_filter_list(pf);
2658
2659         /* Remove all flows */
2660         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
2661                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
2662                 rte_free(p_flow);
2663         }
2664
2665         /* Remove all Traffic Manager configuration */
2666         i40e_tm_conf_uninit(dev);
2667
2668         hw->adapter_closed = 1;
2669 }
2670
2671 /*
2672  * Reset PF device only to re-initialize resources in PMD layer
2673  */
2674 static int
2675 i40e_dev_reset(struct rte_eth_dev *dev)
2676 {
2677         int ret;
2678
2679         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2680          * its VF to make them align with it. The detailed notification
2681          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2682          * To avoid unexpected behavior in VF, currently reset of PF with
2683          * SR-IOV activation is not supported. It might be supported later.
2684          */
2685         if (dev->data->sriov.active)
2686                 return -ENOTSUP;
2687
2688         ret = eth_i40e_dev_uninit(dev);
2689         if (ret)
2690                 return ret;
2691
2692         ret = eth_i40e_dev_init(dev, NULL);
2693
2694         return ret;
2695 }
2696
2697 static int
2698 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2699 {
2700         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2702         struct i40e_vsi *vsi = pf->main_vsi;
2703         int status;
2704
2705         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2706                                                      true, NULL, true);
2707         if (status != I40E_SUCCESS) {
2708                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2709                 return -EAGAIN;
2710         }
2711
2712         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2713                                                         TRUE, NULL);
2714         if (status != I40E_SUCCESS) {
2715                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2716                 /* Rollback unicast promiscuous mode */
2717                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2718                                                     false, NULL, true);
2719                 return -EAGAIN;
2720         }
2721
2722         return 0;
2723 }
2724
2725 static int
2726 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2727 {
2728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2729         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2730         struct i40e_vsi *vsi = pf->main_vsi;
2731         int status;
2732
2733         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2734                                                      false, NULL, true);
2735         if (status != I40E_SUCCESS) {
2736                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2737                 return -EAGAIN;
2738         }
2739
2740         /* must remain in all_multicast mode */
2741         if (dev->data->all_multicast == 1)
2742                 return 0;
2743
2744         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2745                                                         false, NULL);
2746         if (status != I40E_SUCCESS) {
2747                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2748                 /* Rollback unicast promiscuous mode */
2749                 i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2750                                                     true, NULL, true);
2751                 return -EAGAIN;
2752         }
2753
2754         return 0;
2755 }
2756
2757 static int
2758 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2759 {
2760         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2761         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2762         struct i40e_vsi *vsi = pf->main_vsi;
2763         int ret;
2764
2765         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2766         if (ret != I40E_SUCCESS) {
2767                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2768                 return -EAGAIN;
2769         }
2770
2771         return 0;
2772 }
2773
2774 static int
2775 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2776 {
2777         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2778         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2779         struct i40e_vsi *vsi = pf->main_vsi;
2780         int ret;
2781
2782         if (dev->data->promiscuous == 1)
2783                 return 0; /* must remain in all_multicast mode */
2784
2785         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2786                                 vsi->seid, FALSE, NULL);
2787         if (ret != I40E_SUCCESS) {
2788                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2789                 return -EAGAIN;
2790         }
2791
2792         return 0;
2793 }
2794
2795 /*
2796  * Set device link up.
2797  */
2798 static int
2799 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2800 {
2801         /* re-apply link speed setting */
2802         return i40e_apply_link_speed(dev);
2803 }
2804
2805 /*
2806  * Set device link down.
2807  */
2808 static int
2809 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2810 {
2811         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2812         uint8_t abilities = 0;
2813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2814
2815         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2816         return i40e_phy_conf_link(hw, abilities, speed, false);
2817 }
2818
2819 static __rte_always_inline void
2820 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2821 {
2822 /* Link status registers and values*/
2823 #define I40E_PRTMAC_LINKSTA             0x001E2420
2824 #define I40E_REG_LINK_UP                0x40000080
2825 #define I40E_PRTMAC_MACC                0x001E24E0
2826 #define I40E_REG_MACC_25GB              0x00020000
2827 #define I40E_REG_SPEED_MASK             0x38000000
2828 #define I40E_REG_SPEED_0                0x00000000
2829 #define I40E_REG_SPEED_1                0x08000000
2830 #define I40E_REG_SPEED_2                0x10000000
2831 #define I40E_REG_SPEED_3                0x18000000
2832 #define I40E_REG_SPEED_4                0x20000000
2833         uint32_t link_speed;
2834         uint32_t reg_val;
2835
2836         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2837         link_speed = reg_val & I40E_REG_SPEED_MASK;
2838         reg_val &= I40E_REG_LINK_UP;
2839         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2840
2841         if (unlikely(link->link_status == 0))
2842                 return;
2843
2844         /* Parse the link status */
2845         switch (link_speed) {
2846         case I40E_REG_SPEED_0:
2847                 link->link_speed = ETH_SPEED_NUM_100M;
2848                 break;
2849         case I40E_REG_SPEED_1:
2850                 link->link_speed = ETH_SPEED_NUM_1G;
2851                 break;
2852         case I40E_REG_SPEED_2:
2853                 if (hw->mac.type == I40E_MAC_X722)
2854                         link->link_speed = ETH_SPEED_NUM_2_5G;
2855                 else
2856                         link->link_speed = ETH_SPEED_NUM_10G;
2857                 break;
2858         case I40E_REG_SPEED_3:
2859                 if (hw->mac.type == I40E_MAC_X722) {
2860                         link->link_speed = ETH_SPEED_NUM_5G;
2861                 } else {
2862                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2863
2864                         if (reg_val & I40E_REG_MACC_25GB)
2865                                 link->link_speed = ETH_SPEED_NUM_25G;
2866                         else
2867                                 link->link_speed = ETH_SPEED_NUM_40G;
2868                 }
2869                 break;
2870         case I40E_REG_SPEED_4:
2871                 if (hw->mac.type == I40E_MAC_X722)
2872                         link->link_speed = ETH_SPEED_NUM_10G;
2873                 else
2874                         link->link_speed = ETH_SPEED_NUM_20G;
2875                 break;
2876         default:
2877                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2878                 break;
2879         }
2880 }
2881
2882 static __rte_always_inline void
2883 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2884         bool enable_lse, int wait_to_complete)
2885 {
2886 #define CHECK_INTERVAL             100  /* 100ms */
2887 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2888         uint32_t rep_cnt = MAX_REPEAT_TIME;
2889         struct i40e_link_status link_status;
2890         int status;
2891
2892         memset(&link_status, 0, sizeof(link_status));
2893
2894         do {
2895                 memset(&link_status, 0, sizeof(link_status));
2896
2897                 /* Get link status information from hardware */
2898                 status = i40e_aq_get_link_info(hw, enable_lse,
2899                                                 &link_status, NULL);
2900                 if (unlikely(status != I40E_SUCCESS)) {
2901                         link->link_speed = ETH_SPEED_NUM_NONE;
2902                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2903                         PMD_DRV_LOG(ERR, "Failed to get link info");
2904                         return;
2905                 }
2906
2907                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2908                 if (!wait_to_complete || link->link_status)
2909                         break;
2910
2911                 rte_delay_ms(CHECK_INTERVAL);
2912         } while (--rep_cnt);
2913
2914         /* Parse the link status */
2915         switch (link_status.link_speed) {
2916         case I40E_LINK_SPEED_100MB:
2917                 link->link_speed = ETH_SPEED_NUM_100M;
2918                 break;
2919         case I40E_LINK_SPEED_1GB:
2920                 link->link_speed = ETH_SPEED_NUM_1G;
2921                 break;
2922         case I40E_LINK_SPEED_10GB:
2923                 link->link_speed = ETH_SPEED_NUM_10G;
2924                 break;
2925         case I40E_LINK_SPEED_20GB:
2926                 link->link_speed = ETH_SPEED_NUM_20G;
2927                 break;
2928         case I40E_LINK_SPEED_25GB:
2929                 link->link_speed = ETH_SPEED_NUM_25G;
2930                 break;
2931         case I40E_LINK_SPEED_40GB:
2932                 link->link_speed = ETH_SPEED_NUM_40G;
2933                 break;
2934         default:
2935                 link->link_speed = ETH_SPEED_NUM_NONE;
2936                 break;
2937         }
2938 }
2939
2940 int
2941 i40e_dev_link_update(struct rte_eth_dev *dev,
2942                      int wait_to_complete)
2943 {
2944         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2945         struct rte_eth_link link;
2946         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2947         int ret;
2948
2949         memset(&link, 0, sizeof(link));
2950
2951         /* i40e uses full duplex only */
2952         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2953         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2954                         ETH_LINK_SPEED_FIXED);
2955
2956         if (!wait_to_complete && !enable_lse)
2957                 update_link_reg(hw, &link);
2958         else
2959                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2960
2961         if (hw->switch_dev)
2962                 rte_eth_linkstatus_get(hw->switch_dev, &link);
2963
2964         ret = rte_eth_linkstatus_set(dev, &link);
2965         i40e_notify_all_vfs_link_status(dev);
2966
2967         return ret;
2968 }
2969
2970 /* Get all the statistics of a VSI */
2971 void
2972 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2973 {
2974         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2975         struct i40e_eth_stats *nes = &vsi->eth_stats;
2976         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2977         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2978
2979         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2980                             vsi->offset_loaded, &oes->rx_bytes,
2981                             &nes->rx_bytes);
2982         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2983                             vsi->offset_loaded, &oes->rx_unicast,
2984                             &nes->rx_unicast);
2985         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2986                             vsi->offset_loaded, &oes->rx_multicast,
2987                             &nes->rx_multicast);
2988         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2989                             vsi->offset_loaded, &oes->rx_broadcast,
2990                             &nes->rx_broadcast);
2991         /* exclude CRC bytes */
2992         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2993                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2994
2995         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2996                             &oes->rx_discards, &nes->rx_discards);
2997         /* GLV_REPC not supported */
2998         /* GLV_RMPC not supported */
2999         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
3000                             &oes->rx_unknown_protocol,
3001                             &nes->rx_unknown_protocol);
3002         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
3003                             vsi->offset_loaded, &oes->tx_bytes,
3004                             &nes->tx_bytes);
3005         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
3006                             vsi->offset_loaded, &oes->tx_unicast,
3007                             &nes->tx_unicast);
3008         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
3009                             vsi->offset_loaded, &oes->tx_multicast,
3010                             &nes->tx_multicast);
3011         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
3012                             vsi->offset_loaded,  &oes->tx_broadcast,
3013                             &nes->tx_broadcast);
3014         /* GLV_TDPC not supported */
3015         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
3016                             &oes->tx_errors, &nes->tx_errors);
3017         vsi->offset_loaded = true;
3018
3019         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
3020                     vsi->vsi_id);
3021         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3022         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3023         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3024         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3025         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3026         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3027                     nes->rx_unknown_protocol);
3028         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3029         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3030         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3031         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3032         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3033         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3034         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
3035                     vsi->vsi_id);
3036 }
3037
3038 static void
3039 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
3040 {
3041         unsigned int i;
3042         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3043         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
3044
3045         /* Get rx/tx bytes of internal transfer packets */
3046         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
3047                         I40E_GLV_GORCL(hw->port),
3048                         pf->offset_loaded,
3049                         &pf->internal_stats_offset.rx_bytes,
3050                         &pf->internal_stats.rx_bytes);
3051
3052         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
3053                         I40E_GLV_GOTCL(hw->port),
3054                         pf->offset_loaded,
3055                         &pf->internal_stats_offset.tx_bytes,
3056                         &pf->internal_stats.tx_bytes);
3057         /* Get total internal rx packet count */
3058         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
3059                             I40E_GLV_UPRCL(hw->port),
3060                             pf->offset_loaded,
3061                             &pf->internal_stats_offset.rx_unicast,
3062                             &pf->internal_stats.rx_unicast);
3063         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
3064                             I40E_GLV_MPRCL(hw->port),
3065                             pf->offset_loaded,
3066                             &pf->internal_stats_offset.rx_multicast,
3067                             &pf->internal_stats.rx_multicast);
3068         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
3069                             I40E_GLV_BPRCL(hw->port),
3070                             pf->offset_loaded,
3071                             &pf->internal_stats_offset.rx_broadcast,
3072                             &pf->internal_stats.rx_broadcast);
3073         /* Get total internal tx packet count */
3074         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
3075                             I40E_GLV_UPTCL(hw->port),
3076                             pf->offset_loaded,
3077                             &pf->internal_stats_offset.tx_unicast,
3078                             &pf->internal_stats.tx_unicast);
3079         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
3080                             I40E_GLV_MPTCL(hw->port),
3081                             pf->offset_loaded,
3082                             &pf->internal_stats_offset.tx_multicast,
3083                             &pf->internal_stats.tx_multicast);
3084         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
3085                             I40E_GLV_BPTCL(hw->port),
3086                             pf->offset_loaded,
3087                             &pf->internal_stats_offset.tx_broadcast,
3088                             &pf->internal_stats.tx_broadcast);
3089
3090         /* exclude CRC size */
3091         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
3092                 pf->internal_stats.rx_multicast +
3093                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
3094
3095         /* Get statistics of struct i40e_eth_stats */
3096         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
3097                             I40E_GLPRT_GORCL(hw->port),
3098                             pf->offset_loaded, &os->eth.rx_bytes,
3099                             &ns->eth.rx_bytes);
3100         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
3101                             I40E_GLPRT_UPRCL(hw->port),
3102                             pf->offset_loaded, &os->eth.rx_unicast,
3103                             &ns->eth.rx_unicast);
3104         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
3105                             I40E_GLPRT_MPRCL(hw->port),
3106                             pf->offset_loaded, &os->eth.rx_multicast,
3107                             &ns->eth.rx_multicast);
3108         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
3109                             I40E_GLPRT_BPRCL(hw->port),
3110                             pf->offset_loaded, &os->eth.rx_broadcast,
3111                             &ns->eth.rx_broadcast);
3112         /* Workaround: CRC size should not be included in byte statistics,
3113          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
3114          * packet.
3115          */
3116         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3117                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
3118
3119         /* exclude internal rx bytes
3120          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
3121          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
3122          * value.
3123          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
3124          */
3125         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
3126                 ns->eth.rx_bytes = 0;
3127         else
3128                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
3129
3130         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
3131                 ns->eth.rx_unicast = 0;
3132         else
3133                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
3134
3135         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
3136                 ns->eth.rx_multicast = 0;
3137         else
3138                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
3139
3140         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
3141                 ns->eth.rx_broadcast = 0;
3142         else
3143                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
3144
3145         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
3146                             pf->offset_loaded, &os->eth.rx_discards,
3147                             &ns->eth.rx_discards);
3148         /* GLPRT_REPC not supported */
3149         /* GLPRT_RMPC not supported */
3150         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
3151                             pf->offset_loaded,
3152                             &os->eth.rx_unknown_protocol,
3153                             &ns->eth.rx_unknown_protocol);
3154         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
3155                             I40E_GLPRT_GOTCL(hw->port),
3156                             pf->offset_loaded, &os->eth.tx_bytes,
3157                             &ns->eth.tx_bytes);
3158         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3159                             I40E_GLPRT_UPTCL(hw->port),
3160                             pf->offset_loaded, &os->eth.tx_unicast,
3161                             &ns->eth.tx_unicast);
3162         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3163                             I40E_GLPRT_MPTCL(hw->port),
3164                             pf->offset_loaded, &os->eth.tx_multicast,
3165                             &ns->eth.tx_multicast);
3166         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3167                             I40E_GLPRT_BPTCL(hw->port),
3168                             pf->offset_loaded, &os->eth.tx_broadcast,
3169                             &ns->eth.tx_broadcast);
3170         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3171                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3172
3173         /* exclude internal tx bytes
3174          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3175          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3176          * value.
3177          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3178          */
3179         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3180                 ns->eth.tx_bytes = 0;
3181         else
3182                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3183
3184         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3185                 ns->eth.tx_unicast = 0;
3186         else
3187                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3188
3189         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3190                 ns->eth.tx_multicast = 0;
3191         else
3192                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3193
3194         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3195                 ns->eth.tx_broadcast = 0;
3196         else
3197                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3198
3199         /* GLPRT_TEPC not supported */
3200
3201         /* additional port specific stats */
3202         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3203                             pf->offset_loaded, &os->tx_dropped_link_down,
3204                             &ns->tx_dropped_link_down);
3205         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3206                             pf->offset_loaded, &os->crc_errors,
3207                             &ns->crc_errors);
3208         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3209                             pf->offset_loaded, &os->illegal_bytes,
3210                             &ns->illegal_bytes);
3211         /* GLPRT_ERRBC not supported */
3212         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3213                             pf->offset_loaded, &os->mac_local_faults,
3214                             &ns->mac_local_faults);
3215         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3216                             pf->offset_loaded, &os->mac_remote_faults,
3217                             &ns->mac_remote_faults);
3218         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3219                             pf->offset_loaded, &os->rx_length_errors,
3220                             &ns->rx_length_errors);
3221         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3222                             pf->offset_loaded, &os->link_xon_rx,
3223                             &ns->link_xon_rx);
3224         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3225                             pf->offset_loaded, &os->link_xoff_rx,
3226                             &ns->link_xoff_rx);
3227         for (i = 0; i < 8; i++) {
3228                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3229                                     pf->offset_loaded,
3230                                     &os->priority_xon_rx[i],
3231                                     &ns->priority_xon_rx[i]);
3232                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3233                                     pf->offset_loaded,
3234                                     &os->priority_xoff_rx[i],
3235                                     &ns->priority_xoff_rx[i]);
3236         }
3237         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3238                             pf->offset_loaded, &os->link_xon_tx,
3239                             &ns->link_xon_tx);
3240         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3241                             pf->offset_loaded, &os->link_xoff_tx,
3242                             &ns->link_xoff_tx);
3243         for (i = 0; i < 8; i++) {
3244                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3245                                     pf->offset_loaded,
3246                                     &os->priority_xon_tx[i],
3247                                     &ns->priority_xon_tx[i]);
3248                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3249                                     pf->offset_loaded,
3250                                     &os->priority_xoff_tx[i],
3251                                     &ns->priority_xoff_tx[i]);
3252                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3253                                     pf->offset_loaded,
3254                                     &os->priority_xon_2_xoff[i],
3255                                     &ns->priority_xon_2_xoff[i]);
3256         }
3257         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3258                             I40E_GLPRT_PRC64L(hw->port),
3259                             pf->offset_loaded, &os->rx_size_64,
3260                             &ns->rx_size_64);
3261         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3262                             I40E_GLPRT_PRC127L(hw->port),
3263                             pf->offset_loaded, &os->rx_size_127,
3264                             &ns->rx_size_127);
3265         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3266                             I40E_GLPRT_PRC255L(hw->port),
3267                             pf->offset_loaded, &os->rx_size_255,
3268                             &ns->rx_size_255);
3269         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3270                             I40E_GLPRT_PRC511L(hw->port),
3271                             pf->offset_loaded, &os->rx_size_511,
3272                             &ns->rx_size_511);
3273         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3274                             I40E_GLPRT_PRC1023L(hw->port),
3275                             pf->offset_loaded, &os->rx_size_1023,
3276                             &ns->rx_size_1023);
3277         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3278                             I40E_GLPRT_PRC1522L(hw->port),
3279                             pf->offset_loaded, &os->rx_size_1522,
3280                             &ns->rx_size_1522);
3281         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3282                             I40E_GLPRT_PRC9522L(hw->port),
3283                             pf->offset_loaded, &os->rx_size_big,
3284                             &ns->rx_size_big);
3285         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3286                             pf->offset_loaded, &os->rx_undersize,
3287                             &ns->rx_undersize);
3288         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3289                             pf->offset_loaded, &os->rx_fragments,
3290                             &ns->rx_fragments);
3291         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3292                             pf->offset_loaded, &os->rx_oversize,
3293                             &ns->rx_oversize);
3294         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3295                             pf->offset_loaded, &os->rx_jabber,
3296                             &ns->rx_jabber);
3297         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3298                             I40E_GLPRT_PTC64L(hw->port),
3299                             pf->offset_loaded, &os->tx_size_64,
3300                             &ns->tx_size_64);
3301         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3302                             I40E_GLPRT_PTC127L(hw->port),
3303                             pf->offset_loaded, &os->tx_size_127,
3304                             &ns->tx_size_127);
3305         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3306                             I40E_GLPRT_PTC255L(hw->port),
3307                             pf->offset_loaded, &os->tx_size_255,
3308                             &ns->tx_size_255);
3309         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3310                             I40E_GLPRT_PTC511L(hw->port),
3311                             pf->offset_loaded, &os->tx_size_511,
3312                             &ns->tx_size_511);
3313         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3314                             I40E_GLPRT_PTC1023L(hw->port),
3315                             pf->offset_loaded, &os->tx_size_1023,
3316                             &ns->tx_size_1023);
3317         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3318                             I40E_GLPRT_PTC1522L(hw->port),
3319                             pf->offset_loaded, &os->tx_size_1522,
3320                             &ns->tx_size_1522);
3321         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3322                             I40E_GLPRT_PTC9522L(hw->port),
3323                             pf->offset_loaded, &os->tx_size_big,
3324                             &ns->tx_size_big);
3325         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3326                            pf->offset_loaded,
3327                            &os->fd_sb_match, &ns->fd_sb_match);
3328         /* GLPRT_MSPDC not supported */
3329         /* GLPRT_XEC not supported */
3330
3331         pf->offset_loaded = true;
3332
3333         if (pf->main_vsi)
3334                 i40e_update_vsi_stats(pf->main_vsi);
3335 }
3336
3337 /* Get all statistics of a port */
3338 static int
3339 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3340 {
3341         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3342         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3343         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3344         struct i40e_vsi *vsi;
3345         unsigned i;
3346
3347         /* call read registers - updates values, now write them to struct */
3348         i40e_read_stats_registers(pf, hw);
3349
3350         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3351                         pf->main_vsi->eth_stats.rx_multicast +
3352                         pf->main_vsi->eth_stats.rx_broadcast -
3353                         pf->main_vsi->eth_stats.rx_discards;
3354         stats->opackets = ns->eth.tx_unicast +
3355                         ns->eth.tx_multicast +
3356                         ns->eth.tx_broadcast;
3357         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3358         stats->obytes   = ns->eth.tx_bytes;
3359         stats->oerrors  = ns->eth.tx_errors +
3360                         pf->main_vsi->eth_stats.tx_errors;
3361
3362         /* Rx Errors */
3363         stats->imissed  = ns->eth.rx_discards +
3364                         pf->main_vsi->eth_stats.rx_discards;
3365         stats->ierrors  = ns->crc_errors +
3366                         ns->rx_length_errors + ns->rx_undersize +
3367                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3368
3369         if (pf->vfs) {
3370                 for (i = 0; i < pf->vf_num; i++) {
3371                         vsi = pf->vfs[i].vsi;
3372                         i40e_update_vsi_stats(vsi);
3373
3374                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3375                                         vsi->eth_stats.rx_multicast +
3376                                         vsi->eth_stats.rx_broadcast -
3377                                         vsi->eth_stats.rx_discards);
3378                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3379                         stats->oerrors  += vsi->eth_stats.tx_errors;
3380                         stats->imissed  += vsi->eth_stats.rx_discards;
3381                 }
3382         }
3383
3384         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3385         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3386         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3387         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3388         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3389         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3390         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3391                     ns->eth.rx_unknown_protocol);
3392         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3393         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3394         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3395         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3396         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3397         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3398
3399         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3400                     ns->tx_dropped_link_down);
3401         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3402         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3403                     ns->illegal_bytes);
3404         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3405         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3406                     ns->mac_local_faults);
3407         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3408                     ns->mac_remote_faults);
3409         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3410                     ns->rx_length_errors);
3411         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3412         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3413         for (i = 0; i < 8; i++) {
3414                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3415                                 i, ns->priority_xon_rx[i]);
3416                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3417                                 i, ns->priority_xoff_rx[i]);
3418         }
3419         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3420         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3421         for (i = 0; i < 8; i++) {
3422                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3423                                 i, ns->priority_xon_tx[i]);
3424                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3425                                 i, ns->priority_xoff_tx[i]);
3426                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3427                                 i, ns->priority_xon_2_xoff[i]);
3428         }
3429         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3430         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3431         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3432         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3433         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3434         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3435         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3436         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3437         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3438         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3439         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3440         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3441         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3442         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3443         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3444         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3445         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3446         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3447         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3448                         ns->mac_short_packet_dropped);
3449         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3450                     ns->checksum_error);
3451         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3452         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3453         return 0;
3454 }
3455
3456 /* Reset the statistics */
3457 static int
3458 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3459 {
3460         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3462
3463         /* Mark PF and VSI stats to update the offset, aka "reset" */
3464         pf->offset_loaded = false;
3465         if (pf->main_vsi)
3466                 pf->main_vsi->offset_loaded = false;
3467
3468         /* read the stats, reading current register values into offset */
3469         i40e_read_stats_registers(pf, hw);
3470
3471         return 0;
3472 }
3473
3474 static uint32_t
3475 i40e_xstats_calc_num(void)
3476 {
3477         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3478                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3479                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3480 }
3481
3482 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3483                                      struct rte_eth_xstat_name *xstats_names,
3484                                      __rte_unused unsigned limit)
3485 {
3486         unsigned count = 0;
3487         unsigned i, prio;
3488
3489         if (xstats_names == NULL)
3490                 return i40e_xstats_calc_num();
3491
3492         /* Note: limit checked in rte_eth_xstats_names() */
3493
3494         /* Get stats from i40e_eth_stats struct */
3495         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3496                 strlcpy(xstats_names[count].name,
3497                         rte_i40e_stats_strings[i].name,
3498                         sizeof(xstats_names[count].name));
3499                 count++;
3500         }
3501
3502         /* Get individiual stats from i40e_hw_port struct */
3503         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3504                 strlcpy(xstats_names[count].name,
3505                         rte_i40e_hw_port_strings[i].name,
3506                         sizeof(xstats_names[count].name));
3507                 count++;
3508         }
3509
3510         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3511                 for (prio = 0; prio < 8; prio++) {
3512                         snprintf(xstats_names[count].name,
3513                                  sizeof(xstats_names[count].name),
3514                                  "rx_priority%u_%s", prio,
3515                                  rte_i40e_rxq_prio_strings[i].name);
3516                         count++;
3517                 }
3518         }
3519
3520         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3521                 for (prio = 0; prio < 8; prio++) {
3522                         snprintf(xstats_names[count].name,
3523                                  sizeof(xstats_names[count].name),
3524                                  "tx_priority%u_%s", prio,
3525                                  rte_i40e_txq_prio_strings[i].name);
3526                         count++;
3527                 }
3528         }
3529         return count;
3530 }
3531
3532 static int
3533 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3534                     unsigned n)
3535 {
3536         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3538         unsigned i, count, prio;
3539         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3540
3541         count = i40e_xstats_calc_num();
3542         if (n < count)
3543                 return count;
3544
3545         i40e_read_stats_registers(pf, hw);
3546
3547         if (xstats == NULL)
3548                 return 0;
3549
3550         count = 0;
3551
3552         /* Get stats from i40e_eth_stats struct */
3553         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3554                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3555                         rte_i40e_stats_strings[i].offset);
3556                 xstats[count].id = count;
3557                 count++;
3558         }
3559
3560         /* Get individiual stats from i40e_hw_port struct */
3561         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3562                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3563                         rte_i40e_hw_port_strings[i].offset);
3564                 xstats[count].id = count;
3565                 count++;
3566         }
3567
3568         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3569                 for (prio = 0; prio < 8; prio++) {
3570                         xstats[count].value =
3571                                 *(uint64_t *)(((char *)hw_stats) +
3572                                 rte_i40e_rxq_prio_strings[i].offset +
3573                                 (sizeof(uint64_t) * prio));
3574                         xstats[count].id = count;
3575                         count++;
3576                 }
3577         }
3578
3579         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3580                 for (prio = 0; prio < 8; prio++) {
3581                         xstats[count].value =
3582                                 *(uint64_t *)(((char *)hw_stats) +
3583                                 rte_i40e_txq_prio_strings[i].offset +
3584                                 (sizeof(uint64_t) * prio));
3585                         xstats[count].id = count;
3586                         count++;
3587                 }
3588         }
3589
3590         return count;
3591 }
3592
3593 static int
3594 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3595 {
3596         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3597         u32 full_ver;
3598         u8 ver, patch;
3599         u16 build;
3600         int ret;
3601
3602         full_ver = hw->nvm.oem_ver;
3603         ver = (u8)(full_ver >> 24);
3604         build = (u16)((full_ver >> 8) & 0xffff);
3605         patch = (u8)(full_ver & 0xff);
3606
3607         ret = snprintf(fw_version, fw_size,
3608                  "%d.%d%d 0x%08x %d.%d.%d",
3609                  ((hw->nvm.version >> 12) & 0xf),
3610                  ((hw->nvm.version >> 4) & 0xff),
3611                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3612                  ver, build, patch);
3613
3614         ret += 1; /* add the size of '\0' */
3615         if (fw_size < (u32)ret)
3616                 return ret;
3617         else
3618                 return 0;
3619 }
3620
3621 /*
3622  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3623  * the Rx data path does not hang if the FW LLDP is stopped.
3624  * return true if lldp need to stop
3625  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3626  */
3627 static bool
3628 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3629 {
3630         double nvm_ver;
3631         char ver_str[64] = {0};
3632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3633
3634         i40e_fw_version_get(dev, ver_str, 64);
3635         nvm_ver = atof(ver_str);
3636         if ((hw->mac.type == I40E_MAC_X722 ||
3637              hw->mac.type == I40E_MAC_X722_VF) &&
3638              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3639                 return true;
3640         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3641                 return true;
3642
3643         return false;
3644 }
3645
3646 static int
3647 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3648 {
3649         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3651         struct i40e_vsi *vsi = pf->main_vsi;
3652         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3653
3654         dev_info->max_rx_queues = vsi->nb_qps;
3655         dev_info->max_tx_queues = vsi->nb_qps;
3656         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3657         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3658         dev_info->max_mac_addrs = vsi->max_macaddrs;
3659         dev_info->max_vfs = pci_dev->max_vfs;
3660         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3661         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3662         dev_info->rx_queue_offload_capa = 0;
3663         dev_info->rx_offload_capa =
3664                 DEV_RX_OFFLOAD_VLAN_STRIP |
3665                 DEV_RX_OFFLOAD_QINQ_STRIP |
3666                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3667                 DEV_RX_OFFLOAD_UDP_CKSUM |
3668                 DEV_RX_OFFLOAD_TCP_CKSUM |
3669                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3670                 DEV_RX_OFFLOAD_KEEP_CRC |
3671                 DEV_RX_OFFLOAD_SCATTER |
3672                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3673                 DEV_RX_OFFLOAD_VLAN_FILTER |
3674                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3675                 DEV_RX_OFFLOAD_RSS_HASH;
3676
3677         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3678         dev_info->tx_offload_capa =
3679                 DEV_TX_OFFLOAD_VLAN_INSERT |
3680                 DEV_TX_OFFLOAD_QINQ_INSERT |
3681                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3682                 DEV_TX_OFFLOAD_UDP_CKSUM |
3683                 DEV_TX_OFFLOAD_TCP_CKSUM |
3684                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3685                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3686                 DEV_TX_OFFLOAD_TCP_TSO |
3687                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3688                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3689                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3690                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3691                 DEV_TX_OFFLOAD_MULTI_SEGS |
3692                 dev_info->tx_queue_offload_capa;
3693         dev_info->dev_capa =
3694                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3695                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3696
3697         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3698                                                 sizeof(uint32_t);
3699         dev_info->reta_size = pf->hash_lut_size;
3700         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3701
3702         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3703                 .rx_thresh = {
3704                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3705                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3706                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3707                 },
3708                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3709                 .rx_drop_en = 0,
3710                 .offloads = 0,
3711         };
3712
3713         dev_info->default_txconf = (struct rte_eth_txconf) {
3714                 .tx_thresh = {
3715                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3716                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3717                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3718                 },
3719                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3720                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3721                 .offloads = 0,
3722         };
3723
3724         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3725                 .nb_max = I40E_MAX_RING_DESC,
3726                 .nb_min = I40E_MIN_RING_DESC,
3727                 .nb_align = I40E_ALIGN_RING_DESC,
3728         };
3729
3730         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3731                 .nb_max = I40E_MAX_RING_DESC,
3732                 .nb_min = I40E_MIN_RING_DESC,
3733                 .nb_align = I40E_ALIGN_RING_DESC,
3734                 .nb_seg_max = I40E_TX_MAX_SEG,
3735                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3736         };
3737
3738         if (pf->flags & I40E_FLAG_VMDQ) {
3739                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3740                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3741                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3742                                                 pf->max_nb_vmdq_vsi;
3743                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3744                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3745                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3746         }
3747
3748         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3749                 /* For XL710 */
3750                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3751                 dev_info->default_rxportconf.nb_queues = 2;
3752                 dev_info->default_txportconf.nb_queues = 2;
3753                 if (dev->data->nb_rx_queues == 1)
3754                         dev_info->default_rxportconf.ring_size = 2048;
3755                 else
3756                         dev_info->default_rxportconf.ring_size = 1024;
3757                 if (dev->data->nb_tx_queues == 1)
3758                         dev_info->default_txportconf.ring_size = 1024;
3759                 else
3760                         dev_info->default_txportconf.ring_size = 512;
3761
3762         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3763                 /* For XXV710 */
3764                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3765                 dev_info->default_rxportconf.nb_queues = 1;
3766                 dev_info->default_txportconf.nb_queues = 1;
3767                 dev_info->default_rxportconf.ring_size = 256;
3768                 dev_info->default_txportconf.ring_size = 256;
3769         } else {
3770                 /* For X710 */
3771                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3772                 dev_info->default_rxportconf.nb_queues = 1;
3773                 dev_info->default_txportconf.nb_queues = 1;
3774                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3775                         dev_info->default_rxportconf.ring_size = 512;
3776                         dev_info->default_txportconf.ring_size = 256;
3777                 } else {
3778                         dev_info->default_rxportconf.ring_size = 256;
3779                         dev_info->default_txportconf.ring_size = 256;
3780                 }
3781         }
3782         dev_info->default_rxportconf.burst_size = 32;
3783         dev_info->default_txportconf.burst_size = 32;
3784
3785         return 0;
3786 }
3787
3788 static int
3789 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3790 {
3791         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3792         struct i40e_vsi *vsi = pf->main_vsi;
3793         PMD_INIT_FUNC_TRACE();
3794
3795         if (on)
3796                 return i40e_vsi_add_vlan(vsi, vlan_id);
3797         else
3798                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3799 }
3800
3801 static int
3802 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3803                                 enum rte_vlan_type vlan_type,
3804                                 uint16_t tpid, int qinq)
3805 {
3806         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3807         uint64_t reg_r = 0;
3808         uint64_t reg_w = 0;
3809         uint16_t reg_id = 3;
3810         int ret;
3811
3812         if (qinq) {
3813                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3814                         reg_id = 2;
3815         }
3816
3817         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3818                                           &reg_r, NULL);
3819         if (ret != I40E_SUCCESS) {
3820                 PMD_DRV_LOG(ERR,
3821                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3822                            reg_id);
3823                 return -EIO;
3824         }
3825         PMD_DRV_LOG(DEBUG,
3826                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3827                     reg_id, reg_r);
3828
3829         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3830         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3831         if (reg_r == reg_w) {
3832                 PMD_DRV_LOG(DEBUG, "No need to write");
3833                 return 0;
3834         }
3835
3836         ret = i40e_aq_debug_write_global_register(hw,
3837                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3838                                            reg_w, NULL);
3839         if (ret != I40E_SUCCESS) {
3840                 PMD_DRV_LOG(ERR,
3841                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3842                             reg_id);
3843                 return -EIO;
3844         }
3845         PMD_DRV_LOG(DEBUG,
3846                     "Global register 0x%08x is changed with value 0x%08x",
3847                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3848
3849         return 0;
3850 }
3851
3852 static int
3853 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3854                    enum rte_vlan_type vlan_type,
3855                    uint16_t tpid)
3856 {
3857         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3858         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3859         int qinq = dev->data->dev_conf.rxmode.offloads &
3860                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3861         int ret = 0;
3862
3863         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3864              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3865             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3866                 PMD_DRV_LOG(ERR,
3867                             "Unsupported vlan type.");
3868                 return -EINVAL;
3869         }
3870
3871         if (pf->support_multi_driver) {
3872                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3873                 return -ENOTSUP;
3874         }
3875
3876         /* 802.1ad frames ability is added in NVM API 1.7*/
3877         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3878                 if (qinq) {
3879                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3880                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3881                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3882                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3883                 } else {
3884                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3885                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3886                 }
3887                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3888                 if (ret != I40E_SUCCESS) {
3889                         PMD_DRV_LOG(ERR,
3890                                     "Set switch config failed aq_err: %d",
3891                                     hw->aq.asq_last_status);
3892                         ret = -EIO;
3893                 }
3894         } else
3895                 /* If NVM API < 1.7, keep the register setting */
3896                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3897                                                       tpid, qinq);
3898
3899         return ret;
3900 }
3901
3902 static int
3903 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3904 {
3905         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3906         struct i40e_vsi *vsi = pf->main_vsi;
3907         struct rte_eth_rxmode *rxmode;
3908
3909         rxmode = &dev->data->dev_conf.rxmode;
3910         if (mask & ETH_VLAN_FILTER_MASK) {
3911                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3912                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3913                 else
3914                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3915         }
3916
3917         if (mask & ETH_VLAN_STRIP_MASK) {
3918                 /* Enable or disable VLAN stripping */
3919                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3920                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3921                 else
3922                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3923         }
3924
3925         if (mask & ETH_VLAN_EXTEND_MASK) {
3926                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3927                         i40e_vsi_config_double_vlan(vsi, TRUE);
3928                         /* Set global registers with default ethertype. */
3929                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3930                                            RTE_ETHER_TYPE_VLAN);
3931                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3932                                            RTE_ETHER_TYPE_VLAN);
3933                 }
3934                 else
3935                         i40e_vsi_config_double_vlan(vsi, FALSE);
3936         }
3937
3938         return 0;
3939 }
3940
3941 static void
3942 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3943                           __rte_unused uint16_t queue,
3944                           __rte_unused int on)
3945 {
3946         PMD_INIT_FUNC_TRACE();
3947 }
3948
3949 static int
3950 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3951 {
3952         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3953         struct i40e_vsi *vsi = pf->main_vsi;
3954         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3955         struct i40e_vsi_vlan_pvid_info info;
3956
3957         memset(&info, 0, sizeof(info));
3958         info.on = on;
3959         if (info.on)
3960                 info.config.pvid = pvid;
3961         else {
3962                 info.config.reject.tagged =
3963                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3964                 info.config.reject.untagged =
3965                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3966         }
3967
3968         return i40e_vsi_vlan_pvid_set(vsi, &info);
3969 }
3970
3971 static int
3972 i40e_dev_led_on(struct rte_eth_dev *dev)
3973 {
3974         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3975         uint32_t mode = i40e_led_get(hw);
3976
3977         if (mode == 0)
3978                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3979
3980         return 0;
3981 }
3982
3983 static int
3984 i40e_dev_led_off(struct rte_eth_dev *dev)
3985 {
3986         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3987         uint32_t mode = i40e_led_get(hw);
3988
3989         if (mode != 0)
3990                 i40e_led_set(hw, 0, false);
3991
3992         return 0;
3993 }
3994
3995 static int
3996 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3997 {
3998         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3999         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4000
4001         fc_conf->pause_time = pf->fc_conf.pause_time;
4002
4003         /* read out from register, in case they are modified by other port */
4004         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
4005                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
4006         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
4007                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
4008
4009         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
4010         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
4011
4012          /* Return current mode according to actual setting*/
4013         switch (hw->fc.current_mode) {
4014         case I40E_FC_FULL:
4015                 fc_conf->mode = RTE_FC_FULL;
4016                 break;
4017         case I40E_FC_TX_PAUSE:
4018                 fc_conf->mode = RTE_FC_TX_PAUSE;
4019                 break;
4020         case I40E_FC_RX_PAUSE:
4021                 fc_conf->mode = RTE_FC_RX_PAUSE;
4022                 break;
4023         case I40E_FC_NONE:
4024         default:
4025                 fc_conf->mode = RTE_FC_NONE;
4026         };
4027
4028         return 0;
4029 }
4030
4031 static int
4032 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
4033 {
4034         uint32_t mflcn_reg, fctrl_reg, reg;
4035         uint32_t max_high_water;
4036         uint8_t i, aq_failure;
4037         int err;
4038         struct i40e_hw *hw;
4039         struct i40e_pf *pf;
4040         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
4041                 [RTE_FC_NONE] = I40E_FC_NONE,
4042                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
4043                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
4044                 [RTE_FC_FULL] = I40E_FC_FULL
4045         };
4046
4047         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
4048
4049         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
4050         if ((fc_conf->high_water > max_high_water) ||
4051                         (fc_conf->high_water < fc_conf->low_water)) {
4052                 PMD_INIT_LOG(ERR,
4053                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
4054                         max_high_water);
4055                 return -EINVAL;
4056         }
4057
4058         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4059         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4060         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
4061
4062         pf->fc_conf.pause_time = fc_conf->pause_time;
4063         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
4064         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
4065
4066         PMD_INIT_FUNC_TRACE();
4067
4068         /* All the link flow control related enable/disable register
4069          * configuration is handle by the F/W
4070          */
4071         err = i40e_set_fc(hw, &aq_failure, true);
4072         if (err < 0)
4073                 return -ENOSYS;
4074
4075         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
4076                 /* Configure flow control refresh threshold,
4077                  * the value for stat_tx_pause_refresh_timer[8]
4078                  * is used for global pause operation.
4079                  */
4080
4081                 I40E_WRITE_REG(hw,
4082                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
4083                                pf->fc_conf.pause_time);
4084
4085                 /* configure the timer value included in transmitted pause
4086                  * frame,
4087                  * the value for stat_tx_pause_quanta[8] is used for global
4088                  * pause operation
4089                  */
4090                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
4091                                pf->fc_conf.pause_time);
4092
4093                 fctrl_reg = I40E_READ_REG(hw,
4094                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
4095
4096                 if (fc_conf->mac_ctrl_frame_fwd != 0)
4097                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
4098                 else
4099                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
4100
4101                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
4102                                fctrl_reg);
4103         } else {
4104                 /* Configure pause time (2 TCs per register) */
4105                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
4106                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
4107                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
4108
4109                 /* Configure flow control refresh threshold value */
4110                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
4111                                pf->fc_conf.pause_time / 2);
4112
4113                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
4114
4115                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
4116                  *depending on configuration
4117                  */
4118                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
4119                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
4120                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
4121                 } else {
4122                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
4123                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
4124                 }
4125
4126                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
4127         }
4128
4129         if (!pf->support_multi_driver) {
4130                 /* config water marker both based on the packets and bytes */
4131                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
4132                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4133                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4134                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
4135                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4136                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
4137                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
4138                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
4139                                   << I40E_KILOSHIFT);
4140                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
4141                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
4142                                    << I40E_KILOSHIFT);
4143         } else {
4144                 PMD_DRV_LOG(ERR,
4145                             "Water marker configuration is not supported.");
4146         }
4147
4148         I40E_WRITE_FLUSH(hw);
4149
4150         return 0;
4151 }
4152
4153 static int
4154 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4155                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4156 {
4157         PMD_INIT_FUNC_TRACE();
4158
4159         return -ENOSYS;
4160 }
4161
4162 /* Add a MAC address, and update filters */
4163 static int
4164 i40e_macaddr_add(struct rte_eth_dev *dev,
4165                  struct rte_ether_addr *mac_addr,
4166                  __rte_unused uint32_t index,
4167                  uint32_t pool)
4168 {
4169         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4170         struct i40e_mac_filter_info mac_filter;
4171         struct i40e_vsi *vsi;
4172         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4173         int ret;
4174
4175         /* If VMDQ not enabled or configured, return */
4176         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4177                           !pf->nb_cfg_vmdq_vsi)) {
4178                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4179                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4180                         pool);
4181                 return -ENOTSUP;
4182         }
4183
4184         if (pool > pf->nb_cfg_vmdq_vsi) {
4185                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4186                                 pool, pf->nb_cfg_vmdq_vsi);
4187                 return -EINVAL;
4188         }
4189
4190         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4191         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4192                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4193         else
4194                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4195
4196         if (pool == 0)
4197                 vsi = pf->main_vsi;
4198         else
4199                 vsi = pf->vmdq[pool - 1].vsi;
4200
4201         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4202         if (ret != I40E_SUCCESS) {
4203                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4204                 return -ENODEV;
4205         }
4206         return 0;
4207 }
4208
4209 /* Remove a MAC address, and update filters */
4210 static void
4211 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4212 {
4213         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4214         struct i40e_vsi *vsi;
4215         struct rte_eth_dev_data *data = dev->data;
4216         struct rte_ether_addr *macaddr;
4217         int ret;
4218         uint32_t i;
4219         uint64_t pool_sel;
4220
4221         macaddr = &(data->mac_addrs[index]);
4222
4223         pool_sel = dev->data->mac_pool_sel[index];
4224
4225         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4226                 if (pool_sel & (1ULL << i)) {
4227                         if (i == 0)
4228                                 vsi = pf->main_vsi;
4229                         else {
4230                                 /* No VMDQ pool enabled or configured */
4231                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4232                                         (i > pf->nb_cfg_vmdq_vsi)) {
4233                                         PMD_DRV_LOG(ERR,
4234                                                 "No VMDQ pool enabled/configured");
4235                                         return;
4236                                 }
4237                                 vsi = pf->vmdq[i - 1].vsi;
4238                         }
4239                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4240
4241                         if (ret) {
4242                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4243                                 return;
4244                         }
4245                 }
4246         }
4247 }
4248
4249 /* Set perfect match or hash match of MAC and VLAN for a VF */
4250 static int
4251 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4252                  struct rte_eth_mac_filter *filter,
4253                  bool add)
4254 {
4255         struct i40e_hw *hw;
4256         struct i40e_mac_filter_info mac_filter;
4257         struct rte_ether_addr old_mac;
4258         struct rte_ether_addr *new_mac;
4259         struct i40e_pf_vf *vf = NULL;
4260         uint16_t vf_id;
4261         int ret;
4262
4263         if (pf == NULL) {
4264                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4265                 return -EINVAL;
4266         }
4267         hw = I40E_PF_TO_HW(pf);
4268
4269         if (filter == NULL) {
4270                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4271                 return -EINVAL;
4272         }
4273
4274         new_mac = &filter->mac_addr;
4275
4276         if (rte_is_zero_ether_addr(new_mac)) {
4277                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4278                 return -EINVAL;
4279         }
4280
4281         vf_id = filter->dst_id;
4282
4283         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4284                 PMD_DRV_LOG(ERR, "Invalid argument.");
4285                 return -EINVAL;
4286         }
4287         vf = &pf->vfs[vf_id];
4288
4289         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4290                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4291                 return -EINVAL;
4292         }
4293
4294         if (add) {
4295                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4296                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4297                                 RTE_ETHER_ADDR_LEN);
4298                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4299                                  RTE_ETHER_ADDR_LEN);
4300
4301                 mac_filter.filter_type = filter->filter_type;
4302                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4303                 if (ret != I40E_SUCCESS) {
4304                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4305                         return -1;
4306                 }
4307                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4308         } else {
4309                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4310                                 RTE_ETHER_ADDR_LEN);
4311                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4312                 if (ret != I40E_SUCCESS) {
4313                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4314                         return -1;
4315                 }
4316
4317                 /* Clear device address as it has been removed */
4318                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4319                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4320         }
4321
4322         return 0;
4323 }
4324
4325 /* MAC filter handle */
4326 static int
4327 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4328                 void *arg)
4329 {
4330         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4331         struct rte_eth_mac_filter *filter;
4332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4333         int ret = I40E_NOT_SUPPORTED;
4334
4335         filter = (struct rte_eth_mac_filter *)(arg);
4336
4337         switch (filter_op) {
4338         case RTE_ETH_FILTER_NOP:
4339                 ret = I40E_SUCCESS;
4340                 break;
4341         case RTE_ETH_FILTER_ADD:
4342                 i40e_pf_disable_irq0(hw);
4343                 if (filter->is_vf)
4344                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4345                 i40e_pf_enable_irq0(hw);
4346                 break;
4347         case RTE_ETH_FILTER_DELETE:
4348                 i40e_pf_disable_irq0(hw);
4349                 if (filter->is_vf)
4350                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4351                 i40e_pf_enable_irq0(hw);
4352                 break;
4353         default:
4354                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4355                 ret = I40E_ERR_PARAM;
4356                 break;
4357         }
4358
4359         return ret;
4360 }
4361
4362 static int
4363 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4364 {
4365         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4366         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4367         uint32_t reg;
4368         int ret;
4369
4370         if (!lut)
4371                 return -EINVAL;
4372
4373         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4374                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4375                                           vsi->type != I40E_VSI_SRIOV,
4376                                           lut, lut_size);
4377                 if (ret) {
4378                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4379                         return ret;
4380                 }
4381         } else {
4382                 uint32_t *lut_dw = (uint32_t *)lut;
4383                 uint16_t i, lut_size_dw = lut_size / 4;
4384
4385                 if (vsi->type == I40E_VSI_SRIOV) {
4386                         for (i = 0; i <= lut_size_dw; i++) {
4387                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4388                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4389                         }
4390                 } else {
4391                         for (i = 0; i < lut_size_dw; i++)
4392                                 lut_dw[i] = I40E_READ_REG(hw,
4393                                                           I40E_PFQF_HLUT(i));
4394                 }
4395         }
4396
4397         return 0;
4398 }
4399
4400 int
4401 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4402 {
4403         struct i40e_pf *pf;
4404         struct i40e_hw *hw;
4405         int ret;
4406
4407         if (!vsi || !lut)
4408                 return -EINVAL;
4409
4410         pf = I40E_VSI_TO_PF(vsi);
4411         hw = I40E_VSI_TO_HW(vsi);
4412
4413         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4414                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4415                                           vsi->type != I40E_VSI_SRIOV,
4416                                           lut, lut_size);
4417                 if (ret) {
4418                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4419                         return ret;
4420                 }
4421         } else {
4422                 uint32_t *lut_dw = (uint32_t *)lut;
4423                 uint16_t i, lut_size_dw = lut_size / 4;
4424
4425                 if (vsi->type == I40E_VSI_SRIOV) {
4426                         for (i = 0; i < lut_size_dw; i++)
4427                                 I40E_WRITE_REG(
4428                                         hw,
4429                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4430                                         lut_dw[i]);
4431                 } else {
4432                         for (i = 0; i < lut_size_dw; i++)
4433                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4434                                                lut_dw[i]);
4435                 }
4436                 I40E_WRITE_FLUSH(hw);
4437         }
4438
4439         return 0;
4440 }
4441
4442 static int
4443 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4444                          struct rte_eth_rss_reta_entry64 *reta_conf,
4445                          uint16_t reta_size)
4446 {
4447         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4448         uint16_t i, lut_size = pf->hash_lut_size;
4449         uint16_t idx, shift;
4450         uint8_t *lut;
4451         int ret;
4452
4453         if (reta_size != lut_size ||
4454                 reta_size > ETH_RSS_RETA_SIZE_512) {
4455                 PMD_DRV_LOG(ERR,
4456                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4457                         reta_size, lut_size);
4458                 return -EINVAL;
4459         }
4460
4461         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4462         if (!lut) {
4463                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4464                 return -ENOMEM;
4465         }
4466         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4467         if (ret)
4468                 goto out;
4469         for (i = 0; i < reta_size; i++) {
4470                 idx = i / RTE_RETA_GROUP_SIZE;
4471                 shift = i % RTE_RETA_GROUP_SIZE;
4472                 if (reta_conf[idx].mask & (1ULL << shift))
4473                         lut[i] = reta_conf[idx].reta[shift];
4474         }
4475         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4476
4477         pf->adapter->rss_reta_updated = 1;
4478
4479 out:
4480         rte_free(lut);
4481
4482         return ret;
4483 }
4484
4485 static int
4486 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4487                         struct rte_eth_rss_reta_entry64 *reta_conf,
4488                         uint16_t reta_size)
4489 {
4490         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4491         uint16_t i, lut_size = pf->hash_lut_size;
4492         uint16_t idx, shift;
4493         uint8_t *lut;
4494         int ret;
4495
4496         if (reta_size != lut_size ||
4497                 reta_size > ETH_RSS_RETA_SIZE_512) {
4498                 PMD_DRV_LOG(ERR,
4499                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4500                         reta_size, lut_size);
4501                 return -EINVAL;
4502         }
4503
4504         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4505         if (!lut) {
4506                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4507                 return -ENOMEM;
4508         }
4509
4510         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4511         if (ret)
4512                 goto out;
4513         for (i = 0; i < reta_size; i++) {
4514                 idx = i / RTE_RETA_GROUP_SIZE;
4515                 shift = i % RTE_RETA_GROUP_SIZE;
4516                 if (reta_conf[idx].mask & (1ULL << shift))
4517                         reta_conf[idx].reta[shift] = lut[i];
4518         }
4519
4520 out:
4521         rte_free(lut);
4522
4523         return ret;
4524 }
4525
4526 /**
4527  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4528  * @hw:   pointer to the HW structure
4529  * @mem:  pointer to mem struct to fill out
4530  * @size: size of memory requested
4531  * @alignment: what to align the allocation to
4532  **/
4533 enum i40e_status_code
4534 i40e_allocate_dma_mem_d(__rte_unused struct i40e_hw *hw,
4535                         struct i40e_dma_mem *mem,
4536                         u64 size,
4537                         u32 alignment)
4538 {
4539         const struct rte_memzone *mz = NULL;
4540         char z_name[RTE_MEMZONE_NAMESIZE];
4541
4542         if (!mem)
4543                 return I40E_ERR_PARAM;
4544
4545         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4546         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4547                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4548         if (!mz)
4549                 return I40E_ERR_NO_MEMORY;
4550
4551         mem->size = size;
4552         mem->va = mz->addr;
4553         mem->pa = mz->iova;
4554         mem->zone = (const void *)mz;
4555         PMD_DRV_LOG(DEBUG,
4556                 "memzone %s allocated with physical address: %"PRIu64,
4557                 mz->name, mem->pa);
4558
4559         return I40E_SUCCESS;
4560 }
4561
4562 /**
4563  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4564  * @hw:   pointer to the HW structure
4565  * @mem:  ptr to mem struct to free
4566  **/
4567 enum i40e_status_code
4568 i40e_free_dma_mem_d(__rte_unused struct i40e_hw *hw,
4569                     struct i40e_dma_mem *mem)
4570 {
4571         if (!mem)
4572                 return I40E_ERR_PARAM;
4573
4574         PMD_DRV_LOG(DEBUG,
4575                 "memzone %s to be freed with physical address: %"PRIu64,
4576                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4577         rte_memzone_free((const struct rte_memzone *)mem->zone);
4578         mem->zone = NULL;
4579         mem->va = NULL;
4580         mem->pa = (u64)0;
4581
4582         return I40E_SUCCESS;
4583 }
4584
4585 /**
4586  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4587  * @hw:   pointer to the HW structure
4588  * @mem:  pointer to mem struct to fill out
4589  * @size: size of memory requested
4590  **/
4591 enum i40e_status_code
4592 i40e_allocate_virt_mem_d(__rte_unused struct i40e_hw *hw,
4593                          struct i40e_virt_mem *mem,
4594                          u32 size)
4595 {
4596         if (!mem)
4597                 return I40E_ERR_PARAM;
4598
4599         mem->size = size;
4600         mem->va = rte_zmalloc("i40e", size, 0);
4601
4602         if (mem->va)
4603                 return I40E_SUCCESS;
4604         else
4605                 return I40E_ERR_NO_MEMORY;
4606 }
4607
4608 /**
4609  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4610  * @hw:   pointer to the HW structure
4611  * @mem:  pointer to mem struct to free
4612  **/
4613 enum i40e_status_code
4614 i40e_free_virt_mem_d(__rte_unused struct i40e_hw *hw,
4615                      struct i40e_virt_mem *mem)
4616 {
4617         if (!mem)
4618                 return I40E_ERR_PARAM;
4619
4620         rte_free(mem->va);
4621         mem->va = NULL;
4622
4623         return I40E_SUCCESS;
4624 }
4625
4626 void
4627 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4628 {
4629         rte_spinlock_init(&sp->spinlock);
4630 }
4631
4632 void
4633 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4634 {
4635         rte_spinlock_lock(&sp->spinlock);
4636 }
4637
4638 void
4639 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4640 {
4641         rte_spinlock_unlock(&sp->spinlock);
4642 }
4643
4644 void
4645 i40e_destroy_spinlock_d(__rte_unused struct i40e_spinlock *sp)
4646 {
4647         return;
4648 }
4649
4650 /**
4651  * Get the hardware capabilities, which will be parsed
4652  * and saved into struct i40e_hw.
4653  */
4654 static int
4655 i40e_get_cap(struct i40e_hw *hw)
4656 {
4657         struct i40e_aqc_list_capabilities_element_resp *buf;
4658         uint16_t len, size = 0;
4659         int ret;
4660
4661         /* Calculate a huge enough buff for saving response data temporarily */
4662         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4663                                                 I40E_MAX_CAP_ELE_NUM;
4664         buf = rte_zmalloc("i40e", len, 0);
4665         if (!buf) {
4666                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4667                 return I40E_ERR_NO_MEMORY;
4668         }
4669
4670         /* Get, parse the capabilities and save it to hw */
4671         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4672                         i40e_aqc_opc_list_func_capabilities, NULL);
4673         if (ret != I40E_SUCCESS)
4674                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4675
4676         /* Free the temporary buffer after being used */
4677         rte_free(buf);
4678
4679         return ret;
4680 }
4681
4682 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4683
4684 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4685                 const char *value,
4686                 void *opaque)
4687 {
4688         struct i40e_pf *pf;
4689         unsigned long num;
4690         char *end;
4691
4692         pf = (struct i40e_pf *)opaque;
4693         RTE_SET_USED(key);
4694
4695         errno = 0;
4696         num = strtoul(value, &end, 0);
4697         if (errno != 0 || end == value || *end != 0) {
4698                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4699                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4700                 return -(EINVAL);
4701         }
4702
4703         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4704                 pf->vf_nb_qp_max = (uint16_t)num;
4705         else
4706                 /* here return 0 to make next valid same argument work */
4707                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4708                             "power of 2 and equal or less than 16 !, Now it is "
4709                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4710
4711         return 0;
4712 }
4713
4714 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4715 {
4716         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4717         struct rte_kvargs *kvlist;
4718         int kvargs_count;
4719
4720         /* set default queue number per VF as 4 */
4721         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4722
4723         if (dev->device->devargs == NULL)
4724                 return 0;
4725
4726         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4727         if (kvlist == NULL)
4728                 return -(EINVAL);
4729
4730         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4731         if (!kvargs_count) {
4732                 rte_kvargs_free(kvlist);
4733                 return 0;
4734         }
4735
4736         if (kvargs_count > 1)
4737                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4738                             "the first invalid or last valid one is used !",
4739                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4740
4741         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4742                            i40e_pf_parse_vf_queue_number_handler, pf);
4743
4744         rte_kvargs_free(kvlist);
4745
4746         return 0;
4747 }
4748
4749 static int
4750 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4751 {
4752         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4753         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4754         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4755         uint16_t qp_count = 0, vsi_count = 0;
4756
4757         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4758                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4759                 return -EINVAL;
4760         }
4761
4762         i40e_pf_config_vf_rxq_number(dev);
4763
4764         /* Add the parameter init for LFC */
4765         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4766         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4767         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4768
4769         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4770         pf->max_num_vsi = hw->func_caps.num_vsis;
4771         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4772         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4773
4774         /* FDir queue/VSI allocation */
4775         pf->fdir_qp_offset = 0;
4776         if (hw->func_caps.fd) {
4777                 pf->flags |= I40E_FLAG_FDIR;
4778                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4779         } else {
4780                 pf->fdir_nb_qps = 0;
4781         }
4782         qp_count += pf->fdir_nb_qps;
4783         vsi_count += 1;
4784
4785         /* LAN queue/VSI allocation */
4786         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4787         if (!hw->func_caps.rss) {
4788                 pf->lan_nb_qps = 1;
4789         } else {
4790                 pf->flags |= I40E_FLAG_RSS;
4791                 if (hw->mac.type == I40E_MAC_X722)
4792                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4793                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4794         }
4795         qp_count += pf->lan_nb_qps;
4796         vsi_count += 1;
4797
4798         /* VF queue/VSI allocation */
4799         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4800         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4801                 pf->flags |= I40E_FLAG_SRIOV;
4802                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4803                 pf->vf_num = pci_dev->max_vfs;
4804                 PMD_DRV_LOG(DEBUG,
4805                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4806                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4807         } else {
4808                 pf->vf_nb_qps = 0;
4809                 pf->vf_num = 0;
4810         }
4811         qp_count += pf->vf_nb_qps * pf->vf_num;
4812         vsi_count += pf->vf_num;
4813
4814         /* VMDq queue/VSI allocation */
4815         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4816         pf->vmdq_nb_qps = 0;
4817         pf->max_nb_vmdq_vsi = 0;
4818         if (hw->func_caps.vmdq) {
4819                 if (qp_count < hw->func_caps.num_tx_qp &&
4820                         vsi_count < hw->func_caps.num_vsis) {
4821                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4822                                 qp_count) / pf->vmdq_nb_qp_max;
4823
4824                         /* Limit the maximum number of VMDq vsi to the maximum
4825                          * ethdev can support
4826                          */
4827                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4828                                 hw->func_caps.num_vsis - vsi_count);
4829                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4830                                 ETH_64_POOLS);
4831                         if (pf->max_nb_vmdq_vsi) {
4832                                 pf->flags |= I40E_FLAG_VMDQ;
4833                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4834                                 PMD_DRV_LOG(DEBUG,
4835                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4836                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4837                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4838                         } else {
4839                                 PMD_DRV_LOG(INFO,
4840                                         "No enough queues left for VMDq");
4841                         }
4842                 } else {
4843                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4844                 }
4845         }
4846         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4847         vsi_count += pf->max_nb_vmdq_vsi;
4848
4849         if (hw->func_caps.dcb)
4850                 pf->flags |= I40E_FLAG_DCB;
4851
4852         if (qp_count > hw->func_caps.num_tx_qp) {
4853                 PMD_DRV_LOG(ERR,
4854                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4855                         qp_count, hw->func_caps.num_tx_qp);
4856                 return -EINVAL;
4857         }
4858         if (vsi_count > hw->func_caps.num_vsis) {
4859                 PMD_DRV_LOG(ERR,
4860                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4861                         vsi_count, hw->func_caps.num_vsis);
4862                 return -EINVAL;
4863         }
4864
4865         return 0;
4866 }
4867
4868 static int
4869 i40e_pf_get_switch_config(struct i40e_pf *pf)
4870 {
4871         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4872         struct i40e_aqc_get_switch_config_resp *switch_config;
4873         struct i40e_aqc_switch_config_element_resp *element;
4874         uint16_t start_seid = 0, num_reported;
4875         int ret;
4876
4877         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4878                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4879         if (!switch_config) {
4880                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4881                 return -ENOMEM;
4882         }
4883
4884         /* Get the switch configurations */
4885         ret = i40e_aq_get_switch_config(hw, switch_config,
4886                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4887         if (ret != I40E_SUCCESS) {
4888                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4889                 goto fail;
4890         }
4891         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4892         if (num_reported != 1) { /* The number should be 1 */
4893                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4894                 goto fail;
4895         }
4896
4897         /* Parse the switch configuration elements */
4898         element = &(switch_config->element[0]);
4899         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4900                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4901                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4902         } else
4903                 PMD_DRV_LOG(INFO, "Unknown element type");
4904
4905 fail:
4906         rte_free(switch_config);
4907
4908         return ret;
4909 }
4910
4911 static int
4912 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4913                         uint32_t num)
4914 {
4915         struct pool_entry *entry;
4916
4917         if (pool == NULL || num == 0)
4918                 return -EINVAL;
4919
4920         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4921         if (entry == NULL) {
4922                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4923                 return -ENOMEM;
4924         }
4925
4926         /* queue heap initialize */
4927         pool->num_free = num;
4928         pool->num_alloc = 0;
4929         pool->base = base;
4930         LIST_INIT(&pool->alloc_list);
4931         LIST_INIT(&pool->free_list);
4932
4933         /* Initialize element  */
4934         entry->base = 0;
4935         entry->len = num;
4936
4937         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4938         return 0;
4939 }
4940
4941 static void
4942 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4943 {
4944         struct pool_entry *entry, *next_entry;
4945
4946         if (pool == NULL)
4947                 return;
4948
4949         for (entry = LIST_FIRST(&pool->alloc_list);
4950                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4951                         entry = next_entry) {
4952                 LIST_REMOVE(entry, next);
4953                 rte_free(entry);
4954         }
4955
4956         for (entry = LIST_FIRST(&pool->free_list);
4957                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4958                         entry = next_entry) {
4959                 LIST_REMOVE(entry, next);
4960                 rte_free(entry);
4961         }
4962
4963         pool->num_free = 0;
4964         pool->num_alloc = 0;
4965         pool->base = 0;
4966         LIST_INIT(&pool->alloc_list);
4967         LIST_INIT(&pool->free_list);
4968 }
4969
4970 static int
4971 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4972                        uint32_t base)
4973 {
4974         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4975         uint32_t pool_offset;
4976         uint16_t len;
4977         int insert;
4978
4979         if (pool == NULL) {
4980                 PMD_DRV_LOG(ERR, "Invalid parameter");
4981                 return -EINVAL;
4982         }
4983
4984         pool_offset = base - pool->base;
4985         /* Lookup in alloc list */
4986         LIST_FOREACH(entry, &pool->alloc_list, next) {
4987                 if (entry->base == pool_offset) {
4988                         valid_entry = entry;
4989                         LIST_REMOVE(entry, next);
4990                         break;
4991                 }
4992         }
4993
4994         /* Not find, return */
4995         if (valid_entry == NULL) {
4996                 PMD_DRV_LOG(ERR, "Failed to find entry");
4997                 return -EINVAL;
4998         }
4999
5000         /**
5001          * Found it, move it to free list  and try to merge.
5002          * In order to make merge easier, always sort it by qbase.
5003          * Find adjacent prev and last entries.
5004          */
5005         prev = next = NULL;
5006         LIST_FOREACH(entry, &pool->free_list, next) {
5007                 if (entry->base > valid_entry->base) {
5008                         next = entry;
5009                         break;
5010                 }
5011                 prev = entry;
5012         }
5013
5014         insert = 0;
5015         len = valid_entry->len;
5016         /* Try to merge with next one*/
5017         if (next != NULL) {
5018                 /* Merge with next one */
5019                 if (valid_entry->base + len == next->base) {
5020                         next->base = valid_entry->base;
5021                         next->len += len;
5022                         rte_free(valid_entry);
5023                         valid_entry = next;
5024                         insert = 1;
5025                 }
5026         }
5027
5028         if (prev != NULL) {
5029                 /* Merge with previous one */
5030                 if (prev->base + prev->len == valid_entry->base) {
5031                         prev->len += len;
5032                         /* If it merge with next one, remove next node */
5033                         if (insert == 1) {
5034                                 LIST_REMOVE(valid_entry, next);
5035                                 rte_free(valid_entry);
5036                                 valid_entry = NULL;
5037                         } else {
5038                                 rte_free(valid_entry);
5039                                 valid_entry = NULL;
5040                                 insert = 1;
5041                         }
5042                 }
5043         }
5044
5045         /* Not find any entry to merge, insert */
5046         if (insert == 0) {
5047                 if (prev != NULL)
5048                         LIST_INSERT_AFTER(prev, valid_entry, next);
5049                 else if (next != NULL)
5050                         LIST_INSERT_BEFORE(next, valid_entry, next);
5051                 else /* It's empty list, insert to head */
5052                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
5053         }
5054
5055         pool->num_free += len;
5056         pool->num_alloc -= len;
5057
5058         return 0;
5059 }
5060
5061 static int
5062 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
5063                        uint16_t num)
5064 {
5065         struct pool_entry *entry, *valid_entry;
5066
5067         if (pool == NULL || num == 0) {
5068                 PMD_DRV_LOG(ERR, "Invalid parameter");
5069                 return -EINVAL;
5070         }
5071
5072         if (pool->num_free < num) {
5073                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
5074                             num, pool->num_free);
5075                 return -ENOMEM;
5076         }
5077
5078         valid_entry = NULL;
5079         /* Lookup  in free list and find most fit one */
5080         LIST_FOREACH(entry, &pool->free_list, next) {
5081                 if (entry->len >= num) {
5082                         /* Find best one */
5083                         if (entry->len == num) {
5084                                 valid_entry = entry;
5085                                 break;
5086                         }
5087                         if (valid_entry == NULL || valid_entry->len > entry->len)
5088                                 valid_entry = entry;
5089                 }
5090         }
5091
5092         /* Not find one to satisfy the request, return */
5093         if (valid_entry == NULL) {
5094                 PMD_DRV_LOG(ERR, "No valid entry found");
5095                 return -ENOMEM;
5096         }
5097         /**
5098          * The entry have equal queue number as requested,
5099          * remove it from alloc_list.
5100          */
5101         if (valid_entry->len == num) {
5102                 LIST_REMOVE(valid_entry, next);
5103         } else {
5104                 /**
5105                  * The entry have more numbers than requested,
5106                  * create a new entry for alloc_list and minus its
5107                  * queue base and number in free_list.
5108                  */
5109                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
5110                 if (entry == NULL) {
5111                         PMD_DRV_LOG(ERR,
5112                                 "Failed to allocate memory for resource pool");
5113                         return -ENOMEM;
5114                 }
5115                 entry->base = valid_entry->base;
5116                 entry->len = num;
5117                 valid_entry->base += num;
5118                 valid_entry->len -= num;
5119                 valid_entry = entry;
5120         }
5121
5122         /* Insert it into alloc list, not sorted */
5123         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
5124
5125         pool->num_free -= valid_entry->len;
5126         pool->num_alloc += valid_entry->len;
5127
5128         return valid_entry->base + pool->base;
5129 }
5130
5131 /**
5132  * bitmap_is_subset - Check whether src2 is subset of src1
5133  **/
5134 static inline int
5135 bitmap_is_subset(uint8_t src1, uint8_t src2)
5136 {
5137         return !((src1 ^ src2) & src2);
5138 }
5139
5140 static enum i40e_status_code
5141 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5142 {
5143         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5144
5145         /* If DCB is not supported, only default TC is supported */
5146         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
5147                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
5148                 return I40E_NOT_SUPPORTED;
5149         }
5150
5151         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
5152                 PMD_DRV_LOG(ERR,
5153                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
5154                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5155                 return I40E_NOT_SUPPORTED;
5156         }
5157         return I40E_SUCCESS;
5158 }
5159
5160 int
5161 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5162                                 struct i40e_vsi_vlan_pvid_info *info)
5163 {
5164         struct i40e_hw *hw;
5165         struct i40e_vsi_context ctxt;
5166         uint8_t vlan_flags = 0;
5167         int ret;
5168
5169         if (vsi == NULL || info == NULL) {
5170                 PMD_DRV_LOG(ERR, "invalid parameters");
5171                 return I40E_ERR_PARAM;
5172         }
5173
5174         if (info->on) {
5175                 vsi->info.pvid = info->config.pvid;
5176                 /**
5177                  * If insert pvid is enabled, only tagged pkts are
5178                  * allowed to be sent out.
5179                  */
5180                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5181                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5182         } else {
5183                 vsi->info.pvid = 0;
5184                 if (info->config.reject.tagged == 0)
5185                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5186
5187                 if (info->config.reject.untagged == 0)
5188                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5189         }
5190         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5191                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5192         vsi->info.port_vlan_flags |= vlan_flags;
5193         vsi->info.valid_sections =
5194                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5195         memset(&ctxt, 0, sizeof(ctxt));
5196         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5197         ctxt.seid = vsi->seid;
5198
5199         hw = I40E_VSI_TO_HW(vsi);
5200         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5201         if (ret != I40E_SUCCESS)
5202                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5203
5204         return ret;
5205 }
5206
5207 static int
5208 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5209 {
5210         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5211         int i, ret;
5212         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5213
5214         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5215         if (ret != I40E_SUCCESS)
5216                 return ret;
5217
5218         if (!vsi->seid) {
5219                 PMD_DRV_LOG(ERR, "seid not valid");
5220                 return -EINVAL;
5221         }
5222
5223         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5224         tc_bw_data.tc_valid_bits = enabled_tcmap;
5225         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5226                 tc_bw_data.tc_bw_credits[i] =
5227                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5228
5229         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5230         if (ret != I40E_SUCCESS) {
5231                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5232                 return ret;
5233         }
5234
5235         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5236                                         sizeof(vsi->info.qs_handle));
5237         return I40E_SUCCESS;
5238 }
5239
5240 static enum i40e_status_code
5241 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5242                                  struct i40e_aqc_vsi_properties_data *info,
5243                                  uint8_t enabled_tcmap)
5244 {
5245         enum i40e_status_code ret;
5246         int i, total_tc = 0;
5247         uint16_t qpnum_per_tc, bsf, qp_idx;
5248
5249         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5250         if (ret != I40E_SUCCESS)
5251                 return ret;
5252
5253         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5254                 if (enabled_tcmap & (1 << i))
5255                         total_tc++;
5256         if (total_tc == 0)
5257                 total_tc = 1;
5258         vsi->enabled_tc = enabled_tcmap;
5259
5260         /* Number of queues per enabled TC */
5261         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5262         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5263         bsf = rte_bsf32(qpnum_per_tc);
5264
5265         /* Adjust the queue number to actual queues that can be applied */
5266         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5267                 vsi->nb_qps = qpnum_per_tc * total_tc;
5268
5269         /**
5270          * Configure TC and queue mapping parameters, for enabled TC,
5271          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5272          * default queue will serve it.
5273          */
5274         qp_idx = 0;
5275         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5276                 if (vsi->enabled_tc & (1 << i)) {
5277                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5278                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5279                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5280                         qp_idx += qpnum_per_tc;
5281                 } else
5282                         info->tc_mapping[i] = 0;
5283         }
5284
5285         /* Associate queue number with VSI */
5286         if (vsi->type == I40E_VSI_SRIOV) {
5287                 info->mapping_flags |=
5288                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5289                 for (i = 0; i < vsi->nb_qps; i++)
5290                         info->queue_mapping[i] =
5291                                 rte_cpu_to_le_16(vsi->base_queue + i);
5292         } else {
5293                 info->mapping_flags |=
5294                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5295                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5296         }
5297         info->valid_sections |=
5298                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5299
5300         return I40E_SUCCESS;
5301 }
5302
5303 static int
5304 i40e_veb_release(struct i40e_veb *veb)
5305 {
5306         struct i40e_vsi *vsi;
5307         struct i40e_hw *hw;
5308
5309         if (veb == NULL)
5310                 return -EINVAL;
5311
5312         if (!TAILQ_EMPTY(&veb->head)) {
5313                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5314                 return -EACCES;
5315         }
5316         /* associate_vsi field is NULL for floating VEB */
5317         if (veb->associate_vsi != NULL) {
5318                 vsi = veb->associate_vsi;
5319                 hw = I40E_VSI_TO_HW(vsi);
5320
5321                 vsi->uplink_seid = veb->uplink_seid;
5322                 vsi->veb = NULL;
5323         } else {
5324                 veb->associate_pf->main_vsi->floating_veb = NULL;
5325                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5326         }
5327
5328         i40e_aq_delete_element(hw, veb->seid, NULL);
5329         rte_free(veb);
5330         return I40E_SUCCESS;
5331 }
5332
5333 /* Setup a veb */
5334 static struct i40e_veb *
5335 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5336 {
5337         struct i40e_veb *veb;
5338         int ret;
5339         struct i40e_hw *hw;
5340
5341         if (pf == NULL) {
5342                 PMD_DRV_LOG(ERR,
5343                             "veb setup failed, associated PF shouldn't null");
5344                 return NULL;
5345         }
5346         hw = I40E_PF_TO_HW(pf);
5347
5348         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5349         if (!veb) {
5350                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5351                 goto fail;
5352         }
5353
5354         veb->associate_vsi = vsi;
5355         veb->associate_pf = pf;
5356         TAILQ_INIT(&veb->head);
5357         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5358
5359         /* create floating veb if vsi is NULL */
5360         if (vsi != NULL) {
5361                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5362                                       I40E_DEFAULT_TCMAP, false,
5363                                       &veb->seid, false, NULL);
5364         } else {
5365                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5366                                       true, &veb->seid, false, NULL);
5367         }
5368
5369         if (ret != I40E_SUCCESS) {
5370                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5371                             hw->aq.asq_last_status);
5372                 goto fail;
5373         }
5374         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5375
5376         /* get statistics index */
5377         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5378                                 &veb->stats_idx, NULL, NULL, NULL);
5379         if (ret != I40E_SUCCESS) {
5380                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5381                             hw->aq.asq_last_status);
5382                 goto fail;
5383         }
5384         /* Get VEB bandwidth, to be implemented */
5385         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5386         if (vsi)
5387                 vsi->uplink_seid = veb->seid;
5388
5389         return veb;
5390 fail:
5391         rte_free(veb);
5392         return NULL;
5393 }
5394
5395 int
5396 i40e_vsi_release(struct i40e_vsi *vsi)
5397 {
5398         struct i40e_pf *pf;
5399         struct i40e_hw *hw;
5400         struct i40e_vsi_list *vsi_list;
5401         void *temp;
5402         int ret;
5403         struct i40e_mac_filter *f;
5404         uint16_t user_param;
5405
5406         if (!vsi)
5407                 return I40E_SUCCESS;
5408
5409         if (!vsi->adapter)
5410                 return -EFAULT;
5411
5412         user_param = vsi->user_param;
5413
5414         pf = I40E_VSI_TO_PF(vsi);
5415         hw = I40E_VSI_TO_HW(vsi);
5416
5417         /* VSI has child to attach, release child first */
5418         if (vsi->veb) {
5419                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5420                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5421                                 return -1;
5422                 }
5423                 i40e_veb_release(vsi->veb);
5424         }
5425
5426         if (vsi->floating_veb) {
5427                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5428                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5429                                 return -1;
5430                 }
5431         }
5432
5433         /* Remove all macvlan filters of the VSI */
5434         i40e_vsi_remove_all_macvlan_filter(vsi);
5435         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5436                 rte_free(f);
5437
5438         if (vsi->type != I40E_VSI_MAIN &&
5439             ((vsi->type != I40E_VSI_SRIOV) ||
5440             !pf->floating_veb_list[user_param])) {
5441                 /* Remove vsi from parent's sibling list */
5442                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5443                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5444                         return I40E_ERR_PARAM;
5445                 }
5446                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5447                                 &vsi->sib_vsi_list, list);
5448
5449                 /* Remove all switch element of the VSI */
5450                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5451                 if (ret != I40E_SUCCESS)
5452                         PMD_DRV_LOG(ERR, "Failed to delete element");
5453         }
5454
5455         if ((vsi->type == I40E_VSI_SRIOV) &&
5456             pf->floating_veb_list[user_param]) {
5457                 /* Remove vsi from parent's sibling list */
5458                 if (vsi->parent_vsi == NULL ||
5459                     vsi->parent_vsi->floating_veb == NULL) {
5460                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5461                         return I40E_ERR_PARAM;
5462                 }
5463                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5464                              &vsi->sib_vsi_list, list);
5465
5466                 /* Remove all switch element of the VSI */
5467                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5468                 if (ret != I40E_SUCCESS)
5469                         PMD_DRV_LOG(ERR, "Failed to delete element");
5470         }
5471
5472         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5473
5474         if (vsi->type != I40E_VSI_SRIOV)
5475                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5476         rte_free(vsi);
5477
5478         return I40E_SUCCESS;
5479 }
5480
5481 static int
5482 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5483 {
5484         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5485         struct i40e_aqc_remove_macvlan_element_data def_filter;
5486         struct i40e_mac_filter_info filter;
5487         int ret;
5488
5489         if (vsi->type != I40E_VSI_MAIN)
5490                 return I40E_ERR_CONFIG;
5491         memset(&def_filter, 0, sizeof(def_filter));
5492         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5493                                         ETH_ADDR_LEN);
5494         def_filter.vlan_tag = 0;
5495         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5496                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5497         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5498         if (ret != I40E_SUCCESS) {
5499                 struct i40e_mac_filter *f;
5500                 struct rte_ether_addr *mac;
5501
5502                 PMD_DRV_LOG(DEBUG,
5503                             "Cannot remove the default macvlan filter");
5504                 /* It needs to add the permanent mac into mac list */
5505                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5506                 if (f == NULL) {
5507                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5508                         return I40E_ERR_NO_MEMORY;
5509                 }
5510                 mac = &f->mac_info.mac_addr;
5511                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5512                                 ETH_ADDR_LEN);
5513                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5514                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5515                 vsi->mac_num++;
5516
5517                 return ret;
5518         }
5519         rte_memcpy(&filter.mac_addr,
5520                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5521         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5522         return i40e_vsi_add_mac(vsi, &filter);
5523 }
5524
5525 /*
5526  * i40e_vsi_get_bw_config - Query VSI BW Information
5527  * @vsi: the VSI to be queried
5528  *
5529  * Returns 0 on success, negative value on failure
5530  */
5531 static enum i40e_status_code
5532 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5533 {
5534         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5535         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5536         struct i40e_hw *hw = &vsi->adapter->hw;
5537         i40e_status ret;
5538         int i;
5539         uint32_t bw_max;
5540
5541         memset(&bw_config, 0, sizeof(bw_config));
5542         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5543         if (ret != I40E_SUCCESS) {
5544                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5545                             hw->aq.asq_last_status);
5546                 return ret;
5547         }
5548
5549         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5550         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5551                                         &ets_sla_config, NULL);
5552         if (ret != I40E_SUCCESS) {
5553                 PMD_DRV_LOG(ERR,
5554                         "VSI failed to get TC bandwdith configuration %u",
5555                         hw->aq.asq_last_status);
5556                 return ret;
5557         }
5558
5559         /* store and print out BW info */
5560         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5561         vsi->bw_info.bw_max = bw_config.max_bw;
5562         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5563         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5564         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5565                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5566                      I40E_16_BIT_WIDTH);
5567         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5568                 vsi->bw_info.bw_ets_share_credits[i] =
5569                                 ets_sla_config.share_credits[i];
5570                 vsi->bw_info.bw_ets_credits[i] =
5571                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5572                 /* 4 bits per TC, 4th bit is reserved */
5573                 vsi->bw_info.bw_ets_max[i] =
5574                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5575                                   RTE_LEN2MASK(3, uint8_t));
5576                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5577                             vsi->bw_info.bw_ets_share_credits[i]);
5578                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5579                             vsi->bw_info.bw_ets_credits[i]);
5580                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5581                             vsi->bw_info.bw_ets_max[i]);
5582         }
5583
5584         return I40E_SUCCESS;
5585 }
5586
5587 /* i40e_enable_pf_lb
5588  * @pf: pointer to the pf structure
5589  *
5590  * allow loopback on pf
5591  */
5592 static inline void
5593 i40e_enable_pf_lb(struct i40e_pf *pf)
5594 {
5595         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5596         struct i40e_vsi_context ctxt;
5597         int ret;
5598
5599         /* Use the FW API if FW >= v5.0 */
5600         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5601                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5602                 return;
5603         }
5604
5605         memset(&ctxt, 0, sizeof(ctxt));
5606         ctxt.seid = pf->main_vsi_seid;
5607         ctxt.pf_num = hw->pf_id;
5608         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5609         if (ret) {
5610                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5611                             ret, hw->aq.asq_last_status);
5612                 return;
5613         }
5614         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5615         ctxt.info.valid_sections =
5616                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5617         ctxt.info.switch_id |=
5618                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5619
5620         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5621         if (ret)
5622                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5623                             hw->aq.asq_last_status);
5624 }
5625
5626 /* Setup a VSI */
5627 struct i40e_vsi *
5628 i40e_vsi_setup(struct i40e_pf *pf,
5629                enum i40e_vsi_type type,
5630                struct i40e_vsi *uplink_vsi,
5631                uint16_t user_param)
5632 {
5633         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5634         struct i40e_vsi *vsi;
5635         struct i40e_mac_filter_info filter;
5636         int ret;
5637         struct i40e_vsi_context ctxt;
5638         struct rte_ether_addr broadcast =
5639                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5640
5641         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5642             uplink_vsi == NULL) {
5643                 PMD_DRV_LOG(ERR,
5644                         "VSI setup failed, VSI link shouldn't be NULL");
5645                 return NULL;
5646         }
5647
5648         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5649                 PMD_DRV_LOG(ERR,
5650                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5651                 return NULL;
5652         }
5653
5654         /* two situations
5655          * 1.type is not MAIN and uplink vsi is not NULL
5656          * If uplink vsi didn't setup VEB, create one first under veb field
5657          * 2.type is SRIOV and the uplink is NULL
5658          * If floating VEB is NULL, create one veb under floating veb field
5659          */
5660
5661         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5662             uplink_vsi->veb == NULL) {
5663                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5664
5665                 if (uplink_vsi->veb == NULL) {
5666                         PMD_DRV_LOG(ERR, "VEB setup failed");
5667                         return NULL;
5668                 }
5669                 /* set ALLOWLOOPBACk on pf, when veb is created */
5670                 i40e_enable_pf_lb(pf);
5671         }
5672
5673         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5674             pf->main_vsi->floating_veb == NULL) {
5675                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5676
5677                 if (pf->main_vsi->floating_veb == NULL) {
5678                         PMD_DRV_LOG(ERR, "VEB setup failed");
5679                         return NULL;
5680                 }
5681         }
5682
5683         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5684         if (!vsi) {
5685                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5686                 return NULL;
5687         }
5688         TAILQ_INIT(&vsi->mac_list);
5689         vsi->type = type;
5690         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5691         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5692         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5693         vsi->user_param = user_param;
5694         vsi->vlan_anti_spoof_on = 0;
5695         vsi->vlan_filter_on = 0;
5696         /* Allocate queues */
5697         switch (vsi->type) {
5698         case I40E_VSI_MAIN  :
5699                 vsi->nb_qps = pf->lan_nb_qps;
5700                 break;
5701         case I40E_VSI_SRIOV :
5702                 vsi->nb_qps = pf->vf_nb_qps;
5703                 break;
5704         case I40E_VSI_VMDQ2:
5705                 vsi->nb_qps = pf->vmdq_nb_qps;
5706                 break;
5707         case I40E_VSI_FDIR:
5708                 vsi->nb_qps = pf->fdir_nb_qps;
5709                 break;
5710         default:
5711                 goto fail_mem;
5712         }
5713         /*
5714          * The filter status descriptor is reported in rx queue 0,
5715          * while the tx queue for fdir filter programming has no
5716          * such constraints, can be non-zero queues.
5717          * To simplify it, choose FDIR vsi use queue 0 pair.
5718          * To make sure it will use queue 0 pair, queue allocation
5719          * need be done before this function is called
5720          */
5721         if (type != I40E_VSI_FDIR) {
5722                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5723                         if (ret < 0) {
5724                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5725                                                 vsi->seid, ret);
5726                                 goto fail_mem;
5727                         }
5728                         vsi->base_queue = ret;
5729         } else
5730                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5731
5732         /* VF has MSIX interrupt in VF range, don't allocate here */
5733         if (type == I40E_VSI_MAIN) {
5734                 if (pf->support_multi_driver) {
5735                         /* If support multi-driver, need to use INT0 instead of
5736                          * allocating from msix pool. The Msix pool is init from
5737                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5738                          * to 1 without calling i40e_res_pool_alloc.
5739                          */
5740                         vsi->msix_intr = 0;
5741                         vsi->nb_msix = 1;
5742                 } else {
5743                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5744                                                   RTE_MIN(vsi->nb_qps,
5745                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5746                         if (ret < 0) {
5747                                 PMD_DRV_LOG(ERR,
5748                                             "VSI MAIN %d get heap failed %d",
5749                                             vsi->seid, ret);
5750                                 goto fail_queue_alloc;
5751                         }
5752                         vsi->msix_intr = ret;
5753                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5754                                                RTE_MAX_RXTX_INTR_VEC_ID);
5755                 }
5756         } else if (type != I40E_VSI_SRIOV) {
5757                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5758                 if (ret < 0) {
5759                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5760                         goto fail_queue_alloc;
5761                 }
5762                 vsi->msix_intr = ret;
5763                 vsi->nb_msix = 1;
5764         } else {
5765                 vsi->msix_intr = 0;
5766                 vsi->nb_msix = 0;
5767         }
5768
5769         /* Add VSI */
5770         if (type == I40E_VSI_MAIN) {
5771                 /* For main VSI, no need to add since it's default one */
5772                 vsi->uplink_seid = pf->mac_seid;
5773                 vsi->seid = pf->main_vsi_seid;
5774                 /* Bind queues with specific MSIX interrupt */
5775                 /**
5776                  * Needs 2 interrupt at least, one for misc cause which will
5777                  * enabled from OS side, Another for queues binding the
5778                  * interrupt from device side only.
5779                  */
5780
5781                 /* Get default VSI parameters from hardware */
5782                 memset(&ctxt, 0, sizeof(ctxt));
5783                 ctxt.seid = vsi->seid;
5784                 ctxt.pf_num = hw->pf_id;
5785                 ctxt.uplink_seid = vsi->uplink_seid;
5786                 ctxt.vf_num = 0;
5787                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5788                 if (ret != I40E_SUCCESS) {
5789                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5790                         goto fail_msix_alloc;
5791                 }
5792                 rte_memcpy(&vsi->info, &ctxt.info,
5793                         sizeof(struct i40e_aqc_vsi_properties_data));
5794                 vsi->vsi_id = ctxt.vsi_number;
5795                 vsi->info.valid_sections = 0;
5796
5797                 /* Configure tc, enabled TC0 only */
5798                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5799                         I40E_SUCCESS) {
5800                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5801                         goto fail_msix_alloc;
5802                 }
5803
5804                 /* TC, queue mapping */
5805                 memset(&ctxt, 0, sizeof(ctxt));
5806                 vsi->info.valid_sections |=
5807                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5808                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5809                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5810                 rte_memcpy(&ctxt.info, &vsi->info,
5811                         sizeof(struct i40e_aqc_vsi_properties_data));
5812                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5813                                                 I40E_DEFAULT_TCMAP);
5814                 if (ret != I40E_SUCCESS) {
5815                         PMD_DRV_LOG(ERR,
5816                                 "Failed to configure TC queue mapping");
5817                         goto fail_msix_alloc;
5818                 }
5819                 ctxt.seid = vsi->seid;
5820                 ctxt.pf_num = hw->pf_id;
5821                 ctxt.uplink_seid = vsi->uplink_seid;
5822                 ctxt.vf_num = 0;
5823
5824                 /* Update VSI parameters */
5825                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5826                 if (ret != I40E_SUCCESS) {
5827                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5828                         goto fail_msix_alloc;
5829                 }
5830
5831                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5832                                                 sizeof(vsi->info.tc_mapping));
5833                 rte_memcpy(&vsi->info.queue_mapping,
5834                                 &ctxt.info.queue_mapping,
5835                         sizeof(vsi->info.queue_mapping));
5836                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5837                 vsi->info.valid_sections = 0;
5838
5839                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5840                                 ETH_ADDR_LEN);
5841
5842                 /**
5843                  * Updating default filter settings are necessary to prevent
5844                  * reception of tagged packets.
5845                  * Some old firmware configurations load a default macvlan
5846                  * filter which accepts both tagged and untagged packets.
5847                  * The updating is to use a normal filter instead if needed.
5848                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5849                  * The firmware with correct configurations load the default
5850                  * macvlan filter which is expected and cannot be removed.
5851                  */
5852                 i40e_update_default_filter_setting(vsi);
5853                 i40e_config_qinq(hw, vsi);
5854         } else if (type == I40E_VSI_SRIOV) {
5855                 memset(&ctxt, 0, sizeof(ctxt));
5856                 /**
5857                  * For other VSI, the uplink_seid equals to uplink VSI's
5858                  * uplink_seid since they share same VEB
5859                  */
5860                 if (uplink_vsi == NULL)
5861                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5862                 else
5863                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5864                 ctxt.pf_num = hw->pf_id;
5865                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5866                 ctxt.uplink_seid = vsi->uplink_seid;
5867                 ctxt.connection_type = 0x1;
5868                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5869
5870                 /* Use the VEB configuration if FW >= v5.0 */
5871                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5872                         /* Configure switch ID */
5873                         ctxt.info.valid_sections |=
5874                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5875                         ctxt.info.switch_id =
5876                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5877                 }
5878
5879                 /* Configure port/vlan */
5880                 ctxt.info.valid_sections |=
5881                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5882                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5883                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5884                                                 hw->func_caps.enabled_tcmap);
5885                 if (ret != I40E_SUCCESS) {
5886                         PMD_DRV_LOG(ERR,
5887                                 "Failed to configure TC queue mapping");
5888                         goto fail_msix_alloc;
5889                 }
5890
5891                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5892                 ctxt.info.valid_sections |=
5893                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5894                 /**
5895                  * Since VSI is not created yet, only configure parameter,
5896                  * will add vsi below.
5897                  */
5898
5899                 i40e_config_qinq(hw, vsi);
5900         } else if (type == I40E_VSI_VMDQ2) {
5901                 memset(&ctxt, 0, sizeof(ctxt));
5902                 /*
5903                  * For other VSI, the uplink_seid equals to uplink VSI's
5904                  * uplink_seid since they share same VEB
5905                  */
5906                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5907                 ctxt.pf_num = hw->pf_id;
5908                 ctxt.vf_num = 0;
5909                 ctxt.uplink_seid = vsi->uplink_seid;
5910                 ctxt.connection_type = 0x1;
5911                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5912
5913                 ctxt.info.valid_sections |=
5914                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5915                 /* user_param carries flag to enable loop back */
5916                 if (user_param) {
5917                         ctxt.info.switch_id =
5918                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5919                         ctxt.info.switch_id |=
5920                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5921                 }
5922
5923                 /* Configure port/vlan */
5924                 ctxt.info.valid_sections |=
5925                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5926                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5927                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5928                                                 I40E_DEFAULT_TCMAP);
5929                 if (ret != I40E_SUCCESS) {
5930                         PMD_DRV_LOG(ERR,
5931                                 "Failed to configure TC queue mapping");
5932                         goto fail_msix_alloc;
5933                 }
5934                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5935                 ctxt.info.valid_sections |=
5936                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5937         } else if (type == I40E_VSI_FDIR) {
5938                 memset(&ctxt, 0, sizeof(ctxt));
5939                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5940                 ctxt.pf_num = hw->pf_id;
5941                 ctxt.vf_num = 0;
5942                 ctxt.uplink_seid = vsi->uplink_seid;
5943                 ctxt.connection_type = 0x1;     /* regular data port */
5944                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5945                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5946                                                 I40E_DEFAULT_TCMAP);
5947                 if (ret != I40E_SUCCESS) {
5948                         PMD_DRV_LOG(ERR,
5949                                 "Failed to configure TC queue mapping.");
5950                         goto fail_msix_alloc;
5951                 }
5952                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5953                 ctxt.info.valid_sections |=
5954                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5955         } else {
5956                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5957                 goto fail_msix_alloc;
5958         }
5959
5960         if (vsi->type != I40E_VSI_MAIN) {
5961                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5962                 if (ret != I40E_SUCCESS) {
5963                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5964                                     hw->aq.asq_last_status);
5965                         goto fail_msix_alloc;
5966                 }
5967                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5968                 vsi->info.valid_sections = 0;
5969                 vsi->seid = ctxt.seid;
5970                 vsi->vsi_id = ctxt.vsi_number;
5971                 vsi->sib_vsi_list.vsi = vsi;
5972                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5973                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5974                                           &vsi->sib_vsi_list, list);
5975                 } else {
5976                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5977                                           &vsi->sib_vsi_list, list);
5978                 }
5979         }
5980
5981         /* MAC/VLAN configuration */
5982         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5983         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5984
5985         ret = i40e_vsi_add_mac(vsi, &filter);
5986         if (ret != I40E_SUCCESS) {
5987                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5988                 goto fail_msix_alloc;
5989         }
5990
5991         /* Get VSI BW information */
5992         i40e_vsi_get_bw_config(vsi);
5993         return vsi;
5994 fail_msix_alloc:
5995         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5996 fail_queue_alloc:
5997         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5998 fail_mem:
5999         rte_free(vsi);
6000         return NULL;
6001 }
6002
6003 /* Configure vlan filter on or off */
6004 int
6005 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
6006 {
6007         int i, num;
6008         struct i40e_mac_filter *f;
6009         void *temp;
6010         struct i40e_mac_filter_info *mac_filter;
6011         enum rte_mac_filter_type desired_filter;
6012         int ret = I40E_SUCCESS;
6013
6014         if (on) {
6015                 /* Filter to match MAC and VLAN */
6016                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
6017         } else {
6018                 /* Filter to match only MAC */
6019                 desired_filter = RTE_MAC_PERFECT_MATCH;
6020         }
6021
6022         num = vsi->mac_num;
6023
6024         mac_filter = rte_zmalloc("mac_filter_info_data",
6025                                  num * sizeof(*mac_filter), 0);
6026         if (mac_filter == NULL) {
6027                 PMD_DRV_LOG(ERR, "failed to allocate memory");
6028                 return I40E_ERR_NO_MEMORY;
6029         }
6030
6031         i = 0;
6032
6033         /* Remove all existing mac */
6034         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
6035                 mac_filter[i] = f->mac_info;
6036                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
6037                 if (ret) {
6038                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6039                                     on ? "enable" : "disable");
6040                         goto DONE;
6041                 }
6042                 i++;
6043         }
6044
6045         /* Override with new filter */
6046         for (i = 0; i < num; i++) {
6047                 mac_filter[i].filter_type = desired_filter;
6048                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
6049                 if (ret) {
6050                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
6051                                     on ? "enable" : "disable");
6052                         goto DONE;
6053                 }
6054         }
6055
6056 DONE:
6057         rte_free(mac_filter);
6058         return ret;
6059 }
6060
6061 /* Configure vlan stripping on or off */
6062 int
6063 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
6064 {
6065         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6066         struct i40e_vsi_context ctxt;
6067         uint8_t vlan_flags;
6068         int ret = I40E_SUCCESS;
6069
6070         /* Check if it has been already on or off */
6071         if (vsi->info.valid_sections &
6072                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
6073                 if (on) {
6074                         if ((vsi->info.port_vlan_flags &
6075                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
6076                                 return 0; /* already on */
6077                 } else {
6078                         if ((vsi->info.port_vlan_flags &
6079                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
6080                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
6081                                 return 0; /* already off */
6082                 }
6083         }
6084
6085         if (on)
6086                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
6087         else
6088                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
6089         vsi->info.valid_sections =
6090                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
6091         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
6092         vsi->info.port_vlan_flags |= vlan_flags;
6093         ctxt.seid = vsi->seid;
6094         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
6095         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
6096         if (ret)
6097                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
6098                             on ? "enable" : "disable");
6099
6100         return ret;
6101 }
6102
6103 static int
6104 i40e_dev_init_vlan(struct rte_eth_dev *dev)
6105 {
6106         struct rte_eth_dev_data *data = dev->data;
6107         int ret;
6108         int mask = 0;
6109
6110         /* Apply vlan offload setting */
6111         mask = ETH_VLAN_STRIP_MASK |
6112                ETH_VLAN_FILTER_MASK |
6113                ETH_VLAN_EXTEND_MASK;
6114         ret = i40e_vlan_offload_set(dev, mask);
6115         if (ret) {
6116                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
6117                 return ret;
6118         }
6119
6120         /* Apply pvid setting */
6121         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
6122                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
6123         if (ret)
6124                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
6125
6126         return ret;
6127 }
6128
6129 static int
6130 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
6131 {
6132         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6133
6134         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
6135 }
6136
6137 static int
6138 i40e_update_flow_control(struct i40e_hw *hw)
6139 {
6140 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
6141         struct i40e_link_status link_status;
6142         uint32_t rxfc = 0, txfc = 0, reg;
6143         uint8_t an_info;
6144         int ret;
6145
6146         memset(&link_status, 0, sizeof(link_status));
6147         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
6148         if (ret != I40E_SUCCESS) {
6149                 PMD_DRV_LOG(ERR, "Failed to get link status information");
6150                 goto write_reg; /* Disable flow control */
6151         }
6152
6153         an_info = hw->phy.link_info.an_info;
6154         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6155                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6156                 ret = I40E_ERR_NOT_READY;
6157                 goto write_reg; /* Disable flow control */
6158         }
6159         /**
6160          * If link auto negotiation is enabled, flow control needs to
6161          * be configured according to it
6162          */
6163         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6164         case I40E_LINK_PAUSE_RXTX:
6165                 rxfc = 1;
6166                 txfc = 1;
6167                 hw->fc.current_mode = I40E_FC_FULL;
6168                 break;
6169         case I40E_AQ_LINK_PAUSE_RX:
6170                 rxfc = 1;
6171                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6172                 break;
6173         case I40E_AQ_LINK_PAUSE_TX:
6174                 txfc = 1;
6175                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6176                 break;
6177         default:
6178                 hw->fc.current_mode = I40E_FC_NONE;
6179                 break;
6180         }
6181
6182 write_reg:
6183         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6184                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6185         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6186         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6187         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6188         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6189
6190         return ret;
6191 }
6192
6193 /* PF setup */
6194 static int
6195 i40e_pf_setup(struct i40e_pf *pf)
6196 {
6197         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6198         struct i40e_filter_control_settings settings;
6199         struct i40e_vsi *vsi;
6200         int ret;
6201
6202         /* Clear all stats counters */
6203         pf->offset_loaded = FALSE;
6204         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6205         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6206         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6207         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6208
6209         ret = i40e_pf_get_switch_config(pf);
6210         if (ret != I40E_SUCCESS) {
6211                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6212                 return ret;
6213         }
6214
6215         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6216         if (ret)
6217                 PMD_INIT_LOG(WARNING,
6218                         "failed to allocate switch domain for device %d", ret);
6219
6220         if (pf->flags & I40E_FLAG_FDIR) {
6221                 /* make queue allocated first, let FDIR use queue pair 0*/
6222                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6223                 if (ret != I40E_FDIR_QUEUE_ID) {
6224                         PMD_DRV_LOG(ERR,
6225                                 "queue allocation fails for FDIR: ret =%d",
6226                                 ret);
6227                         pf->flags &= ~I40E_FLAG_FDIR;
6228                 }
6229         }
6230         /*  main VSI setup */
6231         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6232         if (!vsi) {
6233                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6234                 return I40E_ERR_NOT_READY;
6235         }
6236         pf->main_vsi = vsi;
6237
6238         /* Configure filter control */
6239         memset(&settings, 0, sizeof(settings));
6240         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6241                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6242         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6243                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6244         else {
6245                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6246                         hw->func_caps.rss_table_size);
6247                 return I40E_ERR_PARAM;
6248         }
6249         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6250                 hw->func_caps.rss_table_size);
6251         pf->hash_lut_size = hw->func_caps.rss_table_size;
6252
6253         /* Enable ethtype and macvlan filters */
6254         settings.enable_ethtype = TRUE;
6255         settings.enable_macvlan = TRUE;
6256         ret = i40e_set_filter_control(hw, &settings);
6257         if (ret)
6258                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6259                                                                 ret);
6260
6261         /* Update flow control according to the auto negotiation */
6262         i40e_update_flow_control(hw);
6263
6264         return I40E_SUCCESS;
6265 }
6266
6267 int
6268 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6269 {
6270         uint32_t reg;
6271         uint16_t j;
6272
6273         /**
6274          * Set or clear TX Queue Disable flags,
6275          * which is required by hardware.
6276          */
6277         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6278         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6279
6280         /* Wait until the request is finished */
6281         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6282                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6283                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6284                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6285                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6286                                                         & 0x1))) {
6287                         break;
6288                 }
6289         }
6290         if (on) {
6291                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6292                         return I40E_SUCCESS; /* already on, skip next steps */
6293
6294                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6295                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6296         } else {
6297                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6298                         return I40E_SUCCESS; /* already off, skip next steps */
6299                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6300         }
6301         /* Write the register */
6302         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6303         /* Check the result */
6304         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6305                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6306                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6307                 if (on) {
6308                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6309                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6310                                 break;
6311                 } else {
6312                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6313                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6314                                 break;
6315                 }
6316         }
6317         /* Check if it is timeout */
6318         if (j >= I40E_CHK_Q_ENA_COUNT) {
6319                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6320                             (on ? "enable" : "disable"), q_idx);
6321                 return I40E_ERR_TIMEOUT;
6322         }
6323
6324         return I40E_SUCCESS;
6325 }
6326
6327 int
6328 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6329 {
6330         uint32_t reg;
6331         uint16_t j;
6332
6333         /* Wait until the request is finished */
6334         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6335                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6336                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6337                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6338                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6339                         break;
6340         }
6341
6342         if (on) {
6343                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6344                         return I40E_SUCCESS; /* Already on, skip next steps */
6345                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6346         } else {
6347                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6348                         return I40E_SUCCESS; /* Already off, skip next steps */
6349                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6350         }
6351
6352         /* Write the register */
6353         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6354         /* Check the result */
6355         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6356                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6357                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6358                 if (on) {
6359                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6360                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6361                                 break;
6362                 } else {
6363                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6364                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6365                                 break;
6366                 }
6367         }
6368
6369         /* Check if it is timeout */
6370         if (j >= I40E_CHK_Q_ENA_COUNT) {
6371                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6372                             (on ? "enable" : "disable"), q_idx);
6373                 return I40E_ERR_TIMEOUT;
6374         }
6375
6376         return I40E_SUCCESS;
6377 }
6378
6379 /* Initialize VSI for TX */
6380 static int
6381 i40e_dev_tx_init(struct i40e_pf *pf)
6382 {
6383         struct rte_eth_dev_data *data = pf->dev_data;
6384         uint16_t i;
6385         uint32_t ret = I40E_SUCCESS;
6386         struct i40e_tx_queue *txq;
6387
6388         for (i = 0; i < data->nb_tx_queues; i++) {
6389                 txq = data->tx_queues[i];
6390                 if (!txq || !txq->q_set)
6391                         continue;
6392                 ret = i40e_tx_queue_init(txq);
6393                 if (ret != I40E_SUCCESS)
6394                         break;
6395         }
6396         if (ret == I40E_SUCCESS)
6397                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6398                                      ->eth_dev);
6399
6400         return ret;
6401 }
6402
6403 /* Initialize VSI for RX */
6404 static int
6405 i40e_dev_rx_init(struct i40e_pf *pf)
6406 {
6407         struct rte_eth_dev_data *data = pf->dev_data;
6408         int ret = I40E_SUCCESS;
6409         uint16_t i;
6410         struct i40e_rx_queue *rxq;
6411
6412         i40e_pf_config_mq_rx(pf);
6413         for (i = 0; i < data->nb_rx_queues; i++) {
6414                 rxq = data->rx_queues[i];
6415                 if (!rxq || !rxq->q_set)
6416                         continue;
6417
6418                 ret = i40e_rx_queue_init(rxq);
6419                 if (ret != I40E_SUCCESS) {
6420                         PMD_DRV_LOG(ERR,
6421                                 "Failed to do RX queue initialization");
6422                         break;
6423                 }
6424         }
6425         if (ret == I40E_SUCCESS)
6426                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6427                                      ->eth_dev);
6428
6429         return ret;
6430 }
6431
6432 static int
6433 i40e_dev_rxtx_init(struct i40e_pf *pf)
6434 {
6435         int err;
6436
6437         err = i40e_dev_tx_init(pf);
6438         if (err) {
6439                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6440                 return err;
6441         }
6442         err = i40e_dev_rx_init(pf);
6443         if (err) {
6444                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6445                 return err;
6446         }
6447
6448         return err;
6449 }
6450
6451 static int
6452 i40e_vmdq_setup(struct rte_eth_dev *dev)
6453 {
6454         struct rte_eth_conf *conf = &dev->data->dev_conf;
6455         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6456         int i, err, conf_vsis, j, loop;
6457         struct i40e_vsi *vsi;
6458         struct i40e_vmdq_info *vmdq_info;
6459         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6460         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6461
6462         /*
6463          * Disable interrupt to avoid message from VF. Furthermore, it will
6464          * avoid race condition in VSI creation/destroy.
6465          */
6466         i40e_pf_disable_irq0(hw);
6467
6468         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6469                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6470                 return -ENOTSUP;
6471         }
6472
6473         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6474         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6475                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6476                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6477                         pf->max_nb_vmdq_vsi);
6478                 return -ENOTSUP;
6479         }
6480
6481         if (pf->vmdq != NULL) {
6482                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6483                 return 0;
6484         }
6485
6486         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6487                                 sizeof(*vmdq_info) * conf_vsis, 0);
6488
6489         if (pf->vmdq == NULL) {
6490                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6491                 return -ENOMEM;
6492         }
6493
6494         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6495
6496         /* Create VMDQ VSI */
6497         for (i = 0; i < conf_vsis; i++) {
6498                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6499                                 vmdq_conf->enable_loop_back);
6500                 if (vsi == NULL) {
6501                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6502                         err = -1;
6503                         goto err_vsi_setup;
6504                 }
6505                 vmdq_info = &pf->vmdq[i];
6506                 vmdq_info->pf = pf;
6507                 vmdq_info->vsi = vsi;
6508         }
6509         pf->nb_cfg_vmdq_vsi = conf_vsis;
6510
6511         /* Configure Vlan */
6512         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6513         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6514                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6515                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6516                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6517                                         vmdq_conf->pool_map[i].vlan_id, j);
6518
6519                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6520                                                 vmdq_conf->pool_map[i].vlan_id);
6521                                 if (err) {
6522                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6523                                         err = -1;
6524                                         goto err_vsi_setup;
6525                                 }
6526                         }
6527                 }
6528         }
6529
6530         i40e_pf_enable_irq0(hw);
6531
6532         return 0;
6533
6534 err_vsi_setup:
6535         for (i = 0; i < conf_vsis; i++)
6536                 if (pf->vmdq[i].vsi == NULL)
6537                         break;
6538                 else
6539                         i40e_vsi_release(pf->vmdq[i].vsi);
6540
6541         rte_free(pf->vmdq);
6542         pf->vmdq = NULL;
6543         i40e_pf_enable_irq0(hw);
6544         return err;
6545 }
6546
6547 static void
6548 i40e_stat_update_32(struct i40e_hw *hw,
6549                    uint32_t reg,
6550                    bool offset_loaded,
6551                    uint64_t *offset,
6552                    uint64_t *stat)
6553 {
6554         uint64_t new_data;
6555
6556         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6557         if (!offset_loaded)
6558                 *offset = new_data;
6559
6560         if (new_data >= *offset)
6561                 *stat = (uint64_t)(new_data - *offset);
6562         else
6563                 *stat = (uint64_t)((new_data +
6564                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6565 }
6566
6567 static void
6568 i40e_stat_update_48(struct i40e_hw *hw,
6569                    uint32_t hireg,
6570                    uint32_t loreg,
6571                    bool offset_loaded,
6572                    uint64_t *offset,
6573                    uint64_t *stat)
6574 {
6575         uint64_t new_data;
6576
6577         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6578         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6579                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6580
6581         if (!offset_loaded)
6582                 *offset = new_data;
6583
6584         if (new_data >= *offset)
6585                 *stat = new_data - *offset;
6586         else
6587                 *stat = (uint64_t)((new_data +
6588                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6589
6590         *stat &= I40E_48_BIT_MASK;
6591 }
6592
6593 /* Disable IRQ0 */
6594 void
6595 i40e_pf_disable_irq0(struct i40e_hw *hw)
6596 {
6597         /* Disable all interrupt types */
6598         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6599                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6600         I40E_WRITE_FLUSH(hw);
6601 }
6602
6603 /* Enable IRQ0 */
6604 void
6605 i40e_pf_enable_irq0(struct i40e_hw *hw)
6606 {
6607         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6608                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6609                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6610                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6611         I40E_WRITE_FLUSH(hw);
6612 }
6613
6614 static void
6615 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6616 {
6617         /* read pending request and disable first */
6618         i40e_pf_disable_irq0(hw);
6619         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6620         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6621                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6622
6623         if (no_queue)
6624                 /* Link no queues with irq0 */
6625                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6626                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6627 }
6628
6629 static void
6630 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6631 {
6632         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6633         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6634         int i;
6635         uint16_t abs_vf_id;
6636         uint32_t index, offset, val;
6637
6638         if (!pf->vfs)
6639                 return;
6640         /**
6641          * Try to find which VF trigger a reset, use absolute VF id to access
6642          * since the reg is global register.
6643          */
6644         for (i = 0; i < pf->vf_num; i++) {
6645                 abs_vf_id = hw->func_caps.vf_base_id + i;
6646                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6647                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6648                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6649                 /* VFR event occurred */
6650                 if (val & (0x1 << offset)) {
6651                         int ret;
6652
6653                         /* Clear the event first */
6654                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6655                                                         (0x1 << offset));
6656                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6657                         /**
6658                          * Only notify a VF reset event occurred,
6659                          * don't trigger another SW reset
6660                          */
6661                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6662                         if (ret != I40E_SUCCESS)
6663                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6664                 }
6665         }
6666 }
6667
6668 static void
6669 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6670 {
6671         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6672         int i;
6673
6674         for (i = 0; i < pf->vf_num; i++)
6675                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6676 }
6677
6678 static void
6679 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6680 {
6681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6682         struct i40e_arq_event_info info;
6683         uint16_t pending, opcode;
6684         int ret;
6685
6686         info.buf_len = I40E_AQ_BUF_SZ;
6687         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6688         if (!info.msg_buf) {
6689                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6690                 return;
6691         }
6692
6693         pending = 1;
6694         while (pending) {
6695                 ret = i40e_clean_arq_element(hw, &info, &pending);
6696
6697                 if (ret != I40E_SUCCESS) {
6698                         PMD_DRV_LOG(INFO,
6699                                 "Failed to read msg from AdminQ, aq_err: %u",
6700                                 hw->aq.asq_last_status);
6701                         break;
6702                 }
6703                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6704
6705                 switch (opcode) {
6706                 case i40e_aqc_opc_send_msg_to_pf:
6707                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6708                         i40e_pf_host_handle_vf_msg(dev,
6709                                         rte_le_to_cpu_16(info.desc.retval),
6710                                         rte_le_to_cpu_32(info.desc.cookie_high),
6711                                         rte_le_to_cpu_32(info.desc.cookie_low),
6712                                         info.msg_buf,
6713                                         info.msg_len);
6714                         break;
6715                 case i40e_aqc_opc_get_link_status:
6716                         ret = i40e_dev_link_update(dev, 0);
6717                         if (!ret)
6718                                 _rte_eth_dev_callback_process(dev,
6719                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6720                         break;
6721                 default:
6722                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6723                                     opcode);
6724                         break;
6725                 }
6726         }
6727         rte_free(info.msg_buf);
6728 }
6729
6730 static void
6731 i40e_handle_mdd_event(struct rte_eth_dev *dev)
6732 {
6733 #define I40E_MDD_CLEAR32 0xFFFFFFFF
6734 #define I40E_MDD_CLEAR16 0xFFFF
6735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6737         bool mdd_detected = false;
6738         struct i40e_pf_vf *vf;
6739         uint32_t reg;
6740         int i;
6741
6742         /* find what triggered the MDD event */
6743         reg = I40E_READ_REG(hw, I40E_GL_MDET_TX);
6744         if (reg & I40E_GL_MDET_TX_VALID_MASK) {
6745                 uint8_t pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
6746                                 I40E_GL_MDET_TX_PF_NUM_SHIFT;
6747                 uint16_t vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
6748                                 I40E_GL_MDET_TX_VF_NUM_SHIFT;
6749                 uint8_t event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
6750                                 I40E_GL_MDET_TX_EVENT_SHIFT;
6751                 uint16_t queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
6752                                 I40E_GL_MDET_TX_QUEUE_SHIFT) -
6753                                         hw->func_caps.base_queue;
6754                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on TX "
6755                         "queue %d PF number 0x%02x VF number 0x%02x device %s\n",
6756                                 event, queue, pf_num, vf_num, dev->data->name);
6757                 I40E_WRITE_REG(hw, I40E_GL_MDET_TX, I40E_MDD_CLEAR32);
6758                 mdd_detected = true;
6759         }
6760         reg = I40E_READ_REG(hw, I40E_GL_MDET_RX);
6761         if (reg & I40E_GL_MDET_RX_VALID_MASK) {
6762                 uint8_t func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
6763                                 I40E_GL_MDET_RX_FUNCTION_SHIFT;
6764                 uint8_t event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
6765                                 I40E_GL_MDET_RX_EVENT_SHIFT;
6766                 uint16_t queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
6767                                 I40E_GL_MDET_RX_QUEUE_SHIFT) -
6768                                         hw->func_caps.base_queue;
6769
6770                 PMD_DRV_LOG(WARNING, "Malicious Driver Detection event 0x%02x on RX "
6771                                 "queue %d of function 0x%02x device %s\n",
6772                                         event, queue, func, dev->data->name);
6773                 I40E_WRITE_REG(hw, I40E_GL_MDET_RX, I40E_MDD_CLEAR32);
6774                 mdd_detected = true;
6775         }
6776
6777         if (mdd_detected) {
6778                 reg = I40E_READ_REG(hw, I40E_PF_MDET_TX);
6779                 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
6780                         I40E_WRITE_REG(hw, I40E_PF_MDET_TX, I40E_MDD_CLEAR16);
6781                         PMD_DRV_LOG(WARNING, "TX driver issue detected on PF\n");
6782                 }
6783                 reg = I40E_READ_REG(hw, I40E_PF_MDET_RX);
6784                 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
6785                         I40E_WRITE_REG(hw, I40E_PF_MDET_RX,
6786                                         I40E_MDD_CLEAR16);
6787                         PMD_DRV_LOG(WARNING, "RX driver issue detected on PF\n");
6788                 }
6789         }
6790
6791         /* see if one of the VFs needs its hand slapped */
6792         for (i = 0; i < pf->vf_num && mdd_detected; i++) {
6793                 vf = &pf->vfs[i];
6794                 reg = I40E_READ_REG(hw, I40E_VP_MDET_TX(i));
6795                 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
6796                         I40E_WRITE_REG(hw, I40E_VP_MDET_TX(i),
6797                                         I40E_MDD_CLEAR16);
6798                         vf->num_mdd_events++;
6799                         PMD_DRV_LOG(WARNING, "TX driver issue detected on VF %d %-"
6800                                         PRIu64 "times\n",
6801                                         i, vf->num_mdd_events);
6802                 }
6803
6804                 reg = I40E_READ_REG(hw, I40E_VP_MDET_RX(i));
6805                 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
6806                         I40E_WRITE_REG(hw, I40E_VP_MDET_RX(i),
6807                                         I40E_MDD_CLEAR16);
6808                         vf->num_mdd_events++;
6809                         PMD_DRV_LOG(WARNING, "RX driver issue detected on VF %d %-"
6810                                         PRIu64 "times\n",
6811                                         i, vf->num_mdd_events);
6812                 }
6813         }
6814 }
6815
6816 /**
6817  * Interrupt handler triggered by NIC  for handling
6818  * specific interrupt.
6819  *
6820  * @param handle
6821  *  Pointer to interrupt handle.
6822  * @param param
6823  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6824  *
6825  * @return
6826  *  void
6827  */
6828 static void
6829 i40e_dev_interrupt_handler(void *param)
6830 {
6831         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6832         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6833         uint32_t icr0;
6834
6835         /* Disable interrupt */
6836         i40e_pf_disable_irq0(hw);
6837
6838         /* read out interrupt causes */
6839         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6840
6841         /* No interrupt event indicated */
6842         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6843                 PMD_DRV_LOG(INFO, "No interrupt event");
6844                 goto done;
6845         }
6846         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6847                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6848         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6849                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6850                 i40e_handle_mdd_event(dev);
6851         }
6852         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6853                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6854         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6855                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6856         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6857                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6858         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6859                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6860         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6861                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6862
6863         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6864                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6865                 i40e_dev_handle_vfr_event(dev);
6866         }
6867         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6868                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6869                 i40e_dev_handle_aq_msg(dev);
6870         }
6871
6872 done:
6873         /* Enable interrupt */
6874         i40e_pf_enable_irq0(hw);
6875 }
6876
6877 static void
6878 i40e_dev_alarm_handler(void *param)
6879 {
6880         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6881         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6882         uint32_t icr0;
6883
6884         /* Disable interrupt */
6885         i40e_pf_disable_irq0(hw);
6886
6887         /* read out interrupt causes */
6888         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6889
6890         /* No interrupt event indicated */
6891         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6892                 goto done;
6893         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6894                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6895         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
6896                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6897                 i40e_handle_mdd_event(dev);
6898         }
6899         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6900                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6901         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6902                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6903         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6904                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6905         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6906                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6907         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6908                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6909
6910         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6911                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6912                 i40e_dev_handle_vfr_event(dev);
6913         }
6914         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6915                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6916                 i40e_dev_handle_aq_msg(dev);
6917         }
6918
6919 done:
6920         /* Enable interrupt */
6921         i40e_pf_enable_irq0(hw);
6922         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6923                           i40e_dev_alarm_handler, dev);
6924 }
6925
6926 int
6927 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6928                          struct i40e_macvlan_filter *filter,
6929                          int total)
6930 {
6931         int ele_num, ele_buff_size;
6932         int num, actual_num, i;
6933         uint16_t flags;
6934         int ret = I40E_SUCCESS;
6935         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6936         struct i40e_aqc_add_macvlan_element_data *req_list;
6937
6938         if (filter == NULL  || total == 0)
6939                 return I40E_ERR_PARAM;
6940         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6941         ele_buff_size = hw->aq.asq_buf_size;
6942
6943         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6944         if (req_list == NULL) {
6945                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6946                 return I40E_ERR_NO_MEMORY;
6947         }
6948
6949         num = 0;
6950         do {
6951                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6952                 memset(req_list, 0, ele_buff_size);
6953
6954                 for (i = 0; i < actual_num; i++) {
6955                         rte_memcpy(req_list[i].mac_addr,
6956                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6957                         req_list[i].vlan_tag =
6958                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6959
6960                         switch (filter[num + i].filter_type) {
6961                         case RTE_MAC_PERFECT_MATCH:
6962                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6963                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6964                                 break;
6965                         case RTE_MACVLAN_PERFECT_MATCH:
6966                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6967                                 break;
6968                         case RTE_MAC_HASH_MATCH:
6969                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6970                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6971                                 break;
6972                         case RTE_MACVLAN_HASH_MATCH:
6973                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6974                                 break;
6975                         default:
6976                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6977                                 ret = I40E_ERR_PARAM;
6978                                 goto DONE;
6979                         }
6980
6981                         req_list[i].queue_number = 0;
6982
6983                         req_list[i].flags = rte_cpu_to_le_16(flags);
6984                 }
6985
6986                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6987                                                 actual_num, NULL);
6988                 if (ret != I40E_SUCCESS) {
6989                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6990                         goto DONE;
6991                 }
6992                 num += actual_num;
6993         } while (num < total);
6994
6995 DONE:
6996         rte_free(req_list);
6997         return ret;
6998 }
6999
7000 int
7001 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
7002                             struct i40e_macvlan_filter *filter,
7003                             int total)
7004 {
7005         int ele_num, ele_buff_size;
7006         int num, actual_num, i;
7007         uint16_t flags;
7008         int ret = I40E_SUCCESS;
7009         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7010         struct i40e_aqc_remove_macvlan_element_data *req_list;
7011
7012         if (filter == NULL  || total == 0)
7013                 return I40E_ERR_PARAM;
7014
7015         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
7016         ele_buff_size = hw->aq.asq_buf_size;
7017
7018         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
7019         if (req_list == NULL) {
7020                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
7021                 return I40E_ERR_NO_MEMORY;
7022         }
7023
7024         num = 0;
7025         do {
7026                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
7027                 memset(req_list, 0, ele_buff_size);
7028
7029                 for (i = 0; i < actual_num; i++) {
7030                         rte_memcpy(req_list[i].mac_addr,
7031                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
7032                         req_list[i].vlan_tag =
7033                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
7034
7035                         switch (filter[num + i].filter_type) {
7036                         case RTE_MAC_PERFECT_MATCH:
7037                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
7038                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7039                                 break;
7040                         case RTE_MACVLAN_PERFECT_MATCH:
7041                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
7042                                 break;
7043                         case RTE_MAC_HASH_MATCH:
7044                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
7045                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
7046                                 break;
7047                         case RTE_MACVLAN_HASH_MATCH:
7048                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
7049                                 break;
7050                         default:
7051                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
7052                                 ret = I40E_ERR_PARAM;
7053                                 goto DONE;
7054                         }
7055                         req_list[i].flags = rte_cpu_to_le_16(flags);
7056                 }
7057
7058                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
7059                                                 actual_num, NULL);
7060                 if (ret != I40E_SUCCESS) {
7061                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
7062                         goto DONE;
7063                 }
7064                 num += actual_num;
7065         } while (num < total);
7066
7067 DONE:
7068         rte_free(req_list);
7069         return ret;
7070 }
7071
7072 /* Find out specific MAC filter */
7073 static struct i40e_mac_filter *
7074 i40e_find_mac_filter(struct i40e_vsi *vsi,
7075                          struct rte_ether_addr *macaddr)
7076 {
7077         struct i40e_mac_filter *f;
7078
7079         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7080                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
7081                         return f;
7082         }
7083
7084         return NULL;
7085 }
7086
7087 static bool
7088 i40e_find_vlan_filter(struct i40e_vsi *vsi,
7089                          uint16_t vlan_id)
7090 {
7091         uint32_t vid_idx, vid_bit;
7092
7093         if (vlan_id > ETH_VLAN_ID_MAX)
7094                 return 0;
7095
7096         vid_idx = I40E_VFTA_IDX(vlan_id);
7097         vid_bit = I40E_VFTA_BIT(vlan_id);
7098
7099         if (vsi->vfta[vid_idx] & vid_bit)
7100                 return 1;
7101         else
7102                 return 0;
7103 }
7104
7105 static void
7106 i40e_store_vlan_filter(struct i40e_vsi *vsi,
7107                        uint16_t vlan_id, bool on)
7108 {
7109         uint32_t vid_idx, vid_bit;
7110
7111         vid_idx = I40E_VFTA_IDX(vlan_id);
7112         vid_bit = I40E_VFTA_BIT(vlan_id);
7113
7114         if (on)
7115                 vsi->vfta[vid_idx] |= vid_bit;
7116         else
7117                 vsi->vfta[vid_idx] &= ~vid_bit;
7118 }
7119
7120 void
7121 i40e_set_vlan_filter(struct i40e_vsi *vsi,
7122                      uint16_t vlan_id, bool on)
7123 {
7124         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7125         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
7126         int ret;
7127
7128         if (vlan_id > ETH_VLAN_ID_MAX)
7129                 return;
7130
7131         i40e_store_vlan_filter(vsi, vlan_id, on);
7132
7133         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
7134                 return;
7135
7136         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
7137
7138         if (on) {
7139                 ret = i40e_aq_add_vlan(hw, vsi->seid,
7140                                        &vlan_data, 1, NULL);
7141                 if (ret != I40E_SUCCESS)
7142                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
7143         } else {
7144                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
7145                                           &vlan_data, 1, NULL);
7146                 if (ret != I40E_SUCCESS)
7147                         PMD_DRV_LOG(ERR,
7148                                     "Failed to remove vlan filter");
7149         }
7150 }
7151
7152 /**
7153  * Find all vlan options for specific mac addr,
7154  * return with actual vlan found.
7155  */
7156 int
7157 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
7158                            struct i40e_macvlan_filter *mv_f,
7159                            int num, struct rte_ether_addr *addr)
7160 {
7161         int i;
7162         uint32_t j, k;
7163
7164         /**
7165          * Not to use i40e_find_vlan_filter to decrease the loop time,
7166          * although the code looks complex.
7167           */
7168         if (num < vsi->vlan_num)
7169                 return I40E_ERR_PARAM;
7170
7171         i = 0;
7172         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7173                 if (vsi->vfta[j]) {
7174                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7175                                 if (vsi->vfta[j] & (1 << k)) {
7176                                         if (i > num - 1) {
7177                                                 PMD_DRV_LOG(ERR,
7178                                                         "vlan number doesn't match");
7179                                                 return I40E_ERR_PARAM;
7180                                         }
7181                                         rte_memcpy(&mv_f[i].macaddr,
7182                                                         addr, ETH_ADDR_LEN);
7183                                         mv_f[i].vlan_id =
7184                                                 j * I40E_UINT32_BIT_SIZE + k;
7185                                         i++;
7186                                 }
7187                         }
7188                 }
7189         }
7190         return I40E_SUCCESS;
7191 }
7192
7193 static inline int
7194 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7195                            struct i40e_macvlan_filter *mv_f,
7196                            int num,
7197                            uint16_t vlan)
7198 {
7199         int i = 0;
7200         struct i40e_mac_filter *f;
7201
7202         if (num < vsi->mac_num)
7203                 return I40E_ERR_PARAM;
7204
7205         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7206                 if (i > num - 1) {
7207                         PMD_DRV_LOG(ERR, "buffer number not match");
7208                         return I40E_ERR_PARAM;
7209                 }
7210                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7211                                 ETH_ADDR_LEN);
7212                 mv_f[i].vlan_id = vlan;
7213                 mv_f[i].filter_type = f->mac_info.filter_type;
7214                 i++;
7215         }
7216
7217         return I40E_SUCCESS;
7218 }
7219
7220 static int
7221 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7222 {
7223         int i, j, num;
7224         struct i40e_mac_filter *f;
7225         struct i40e_macvlan_filter *mv_f;
7226         int ret = I40E_SUCCESS;
7227
7228         if (vsi == NULL || vsi->mac_num == 0)
7229                 return I40E_ERR_PARAM;
7230
7231         /* Case that no vlan is set */
7232         if (vsi->vlan_num == 0)
7233                 num = vsi->mac_num;
7234         else
7235                 num = vsi->mac_num * vsi->vlan_num;
7236
7237         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7238         if (mv_f == NULL) {
7239                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7240                 return I40E_ERR_NO_MEMORY;
7241         }
7242
7243         i = 0;
7244         if (vsi->vlan_num == 0) {
7245                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7246                         rte_memcpy(&mv_f[i].macaddr,
7247                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7248                         mv_f[i].filter_type = f->mac_info.filter_type;
7249                         mv_f[i].vlan_id = 0;
7250                         i++;
7251                 }
7252         } else {
7253                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7254                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7255                                         vsi->vlan_num, &f->mac_info.mac_addr);
7256                         if (ret != I40E_SUCCESS)
7257                                 goto DONE;
7258                         for (j = i; j < i + vsi->vlan_num; j++)
7259                                 mv_f[j].filter_type = f->mac_info.filter_type;
7260                         i += vsi->vlan_num;
7261                 }
7262         }
7263
7264         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7265 DONE:
7266         rte_free(mv_f);
7267
7268         return ret;
7269 }
7270
7271 int
7272 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7273 {
7274         struct i40e_macvlan_filter *mv_f;
7275         int mac_num;
7276         int ret = I40E_SUCCESS;
7277
7278         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7279                 return I40E_ERR_PARAM;
7280
7281         /* If it's already set, just return */
7282         if (i40e_find_vlan_filter(vsi,vlan))
7283                 return I40E_SUCCESS;
7284
7285         mac_num = vsi->mac_num;
7286
7287         if (mac_num == 0) {
7288                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7289                 return I40E_ERR_PARAM;
7290         }
7291
7292         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7293
7294         if (mv_f == NULL) {
7295                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7296                 return I40E_ERR_NO_MEMORY;
7297         }
7298
7299         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7300
7301         if (ret != I40E_SUCCESS)
7302                 goto DONE;
7303
7304         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7305
7306         if (ret != I40E_SUCCESS)
7307                 goto DONE;
7308
7309         i40e_set_vlan_filter(vsi, vlan, 1);
7310
7311         vsi->vlan_num++;
7312         ret = I40E_SUCCESS;
7313 DONE:
7314         rte_free(mv_f);
7315         return ret;
7316 }
7317
7318 int
7319 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7320 {
7321         struct i40e_macvlan_filter *mv_f;
7322         int mac_num;
7323         int ret = I40E_SUCCESS;
7324
7325         /**
7326          * Vlan 0 is the generic filter for untagged packets
7327          * and can't be removed.
7328          */
7329         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7330                 return I40E_ERR_PARAM;
7331
7332         /* If can't find it, just return */
7333         if (!i40e_find_vlan_filter(vsi, vlan))
7334                 return I40E_ERR_PARAM;
7335
7336         mac_num = vsi->mac_num;
7337
7338         if (mac_num == 0) {
7339                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7340                 return I40E_ERR_PARAM;
7341         }
7342
7343         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7344
7345         if (mv_f == NULL) {
7346                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7347                 return I40E_ERR_NO_MEMORY;
7348         }
7349
7350         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7351
7352         if (ret != I40E_SUCCESS)
7353                 goto DONE;
7354
7355         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7356
7357         if (ret != I40E_SUCCESS)
7358                 goto DONE;
7359
7360         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7361         if (vsi->vlan_num == 1) {
7362                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7363                 if (ret != I40E_SUCCESS)
7364                         goto DONE;
7365
7366                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7367                 if (ret != I40E_SUCCESS)
7368                         goto DONE;
7369         }
7370
7371         i40e_set_vlan_filter(vsi, vlan, 0);
7372
7373         vsi->vlan_num--;
7374         ret = I40E_SUCCESS;
7375 DONE:
7376         rte_free(mv_f);
7377         return ret;
7378 }
7379
7380 int
7381 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7382 {
7383         struct i40e_mac_filter *f;
7384         struct i40e_macvlan_filter *mv_f;
7385         int i, vlan_num = 0;
7386         int ret = I40E_SUCCESS;
7387
7388         /* If it's add and we've config it, return */
7389         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7390         if (f != NULL)
7391                 return I40E_SUCCESS;
7392         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7393                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7394
7395                 /**
7396                  * If vlan_num is 0, that's the first time to add mac,
7397                  * set mask for vlan_id 0.
7398                  */
7399                 if (vsi->vlan_num == 0) {
7400                         i40e_set_vlan_filter(vsi, 0, 1);
7401                         vsi->vlan_num = 1;
7402                 }
7403                 vlan_num = vsi->vlan_num;
7404         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7405                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7406                 vlan_num = 1;
7407
7408         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7409         if (mv_f == NULL) {
7410                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7411                 return I40E_ERR_NO_MEMORY;
7412         }
7413
7414         for (i = 0; i < vlan_num; i++) {
7415                 mv_f[i].filter_type = mac_filter->filter_type;
7416                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7417                                 ETH_ADDR_LEN);
7418         }
7419
7420         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7421                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7422                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7423                                         &mac_filter->mac_addr);
7424                 if (ret != I40E_SUCCESS)
7425                         goto DONE;
7426         }
7427
7428         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7429         if (ret != I40E_SUCCESS)
7430                 goto DONE;
7431
7432         /* Add the mac addr into mac list */
7433         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7434         if (f == NULL) {
7435                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7436                 ret = I40E_ERR_NO_MEMORY;
7437                 goto DONE;
7438         }
7439         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7440                         ETH_ADDR_LEN);
7441         f->mac_info.filter_type = mac_filter->filter_type;
7442         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7443         vsi->mac_num++;
7444
7445         ret = I40E_SUCCESS;
7446 DONE:
7447         rte_free(mv_f);
7448
7449         return ret;
7450 }
7451
7452 int
7453 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7454 {
7455         struct i40e_mac_filter *f;
7456         struct i40e_macvlan_filter *mv_f;
7457         int i, vlan_num;
7458         enum rte_mac_filter_type filter_type;
7459         int ret = I40E_SUCCESS;
7460
7461         /* Can't find it, return an error */
7462         f = i40e_find_mac_filter(vsi, addr);
7463         if (f == NULL)
7464                 return I40E_ERR_PARAM;
7465
7466         vlan_num = vsi->vlan_num;
7467         filter_type = f->mac_info.filter_type;
7468         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7469                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7470                 if (vlan_num == 0) {
7471                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7472                         return I40E_ERR_PARAM;
7473                 }
7474         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7475                         filter_type == RTE_MAC_HASH_MATCH)
7476                 vlan_num = 1;
7477
7478         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7479         if (mv_f == NULL) {
7480                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7481                 return I40E_ERR_NO_MEMORY;
7482         }
7483
7484         for (i = 0; i < vlan_num; i++) {
7485                 mv_f[i].filter_type = filter_type;
7486                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7487                                 ETH_ADDR_LEN);
7488         }
7489         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7490                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7491                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7492                 if (ret != I40E_SUCCESS)
7493                         goto DONE;
7494         }
7495
7496         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7497         if (ret != I40E_SUCCESS)
7498                 goto DONE;
7499
7500         /* Remove the mac addr into mac list */
7501         TAILQ_REMOVE(&vsi->mac_list, f, next);
7502         rte_free(f);
7503         vsi->mac_num--;
7504
7505         ret = I40E_SUCCESS;
7506 DONE:
7507         rte_free(mv_f);
7508         return ret;
7509 }
7510
7511 /* Configure hash enable flags for RSS */
7512 uint64_t
7513 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7514 {
7515         uint64_t hena = 0;
7516         int i;
7517
7518         if (!flags)
7519                 return hena;
7520
7521         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7522                 if (flags & (1ULL << i))
7523                         hena |= adapter->pctypes_tbl[i];
7524         }
7525
7526         return hena;
7527 }
7528
7529 /* Parse the hash enable flags */
7530 uint64_t
7531 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7532 {
7533         uint64_t rss_hf = 0;
7534
7535         if (!flags)
7536                 return rss_hf;
7537         int i;
7538
7539         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7540                 if (flags & adapter->pctypes_tbl[i])
7541                         rss_hf |= (1ULL << i);
7542         }
7543         return rss_hf;
7544 }
7545
7546 /* Disable RSS */
7547 static void
7548 i40e_pf_disable_rss(struct i40e_pf *pf)
7549 {
7550         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7551
7552         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7553         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7554         I40E_WRITE_FLUSH(hw);
7555 }
7556
7557 int
7558 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7559 {
7560         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7561         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7562         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7563                            I40E_VFQF_HKEY_MAX_INDEX :
7564                            I40E_PFQF_HKEY_MAX_INDEX;
7565         int ret = 0;
7566
7567         if (!key || key_len == 0) {
7568                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7569                 return 0;
7570         } else if (key_len != (key_idx + 1) *
7571                 sizeof(uint32_t)) {
7572                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7573                 return -EINVAL;
7574         }
7575
7576         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7577                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7578                         (struct i40e_aqc_get_set_rss_key_data *)key;
7579
7580                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7581                 if (ret)
7582                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7583         } else {
7584                 uint32_t *hash_key = (uint32_t *)key;
7585                 uint16_t i;
7586
7587                 if (vsi->type == I40E_VSI_SRIOV) {
7588                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7589                                 I40E_WRITE_REG(
7590                                         hw,
7591                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7592                                         hash_key[i]);
7593
7594                 } else {
7595                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7596                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7597                                                hash_key[i]);
7598                 }
7599                 I40E_WRITE_FLUSH(hw);
7600         }
7601
7602         return ret;
7603 }
7604
7605 static int
7606 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7607 {
7608         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7609         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7610         uint32_t reg;
7611         int ret;
7612
7613         if (!key || !key_len)
7614                 return 0;
7615
7616         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7617                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7618                         (struct i40e_aqc_get_set_rss_key_data *)key);
7619                 if (ret) {
7620                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7621                         return ret;
7622                 }
7623         } else {
7624                 uint32_t *key_dw = (uint32_t *)key;
7625                 uint16_t i;
7626
7627                 if (vsi->type == I40E_VSI_SRIOV) {
7628                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7629                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7630                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7631                         }
7632                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7633                                    sizeof(uint32_t);
7634                 } else {
7635                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7636                                 reg = I40E_PFQF_HKEY(i);
7637                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7638                         }
7639                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7640                                    sizeof(uint32_t);
7641                 }
7642         }
7643         return 0;
7644 }
7645
7646 static int
7647 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7648 {
7649         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7650         uint64_t hena;
7651         int ret;
7652
7653         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7654                                rss_conf->rss_key_len);
7655         if (ret)
7656                 return ret;
7657
7658         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7659         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7660         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7661         I40E_WRITE_FLUSH(hw);
7662
7663         return 0;
7664 }
7665
7666 static int
7667 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7668                          struct rte_eth_rss_conf *rss_conf)
7669 {
7670         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7672         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7673         uint64_t hena;
7674
7675         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7676         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7677
7678         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7679                 if (rss_hf != 0) /* Enable RSS */
7680                         return -EINVAL;
7681                 return 0; /* Nothing to do */
7682         }
7683         /* RSS enabled */
7684         if (rss_hf == 0) /* Disable RSS */
7685                 return -EINVAL;
7686
7687         return i40e_hw_rss_hash_set(pf, rss_conf);
7688 }
7689
7690 static int
7691 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7692                            struct rte_eth_rss_conf *rss_conf)
7693 {
7694         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7696         uint64_t hena;
7697         int ret;
7698
7699         if (!rss_conf)
7700                 return -EINVAL;
7701
7702         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7703                          &rss_conf->rss_key_len);
7704         if (ret)
7705                 return ret;
7706
7707         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7708         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7709         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7710
7711         return 0;
7712 }
7713
7714 static int
7715 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7716 {
7717         switch (filter_type) {
7718         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7719                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7720                 break;
7721         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7722                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7723                 break;
7724         case RTE_TUNNEL_FILTER_IMAC_TENID:
7725                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7726                 break;
7727         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7728                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7729                 break;
7730         case ETH_TUNNEL_FILTER_IMAC:
7731                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7732                 break;
7733         case ETH_TUNNEL_FILTER_OIP:
7734                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7735                 break;
7736         case ETH_TUNNEL_FILTER_IIP:
7737                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7738                 break;
7739         default:
7740                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7741                 return -EINVAL;
7742         }
7743
7744         return 0;
7745 }
7746
7747 /* Convert tunnel filter structure */
7748 static int
7749 i40e_tunnel_filter_convert(
7750         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7751         struct i40e_tunnel_filter *tunnel_filter)
7752 {
7753         rte_ether_addr_copy((struct rte_ether_addr *)
7754                         &cld_filter->element.outer_mac,
7755                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7756         rte_ether_addr_copy((struct rte_ether_addr *)
7757                         &cld_filter->element.inner_mac,
7758                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7759         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7760         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7761              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7762             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7763                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7764         else
7765                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7766         tunnel_filter->input.flags = cld_filter->element.flags;
7767         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7768         tunnel_filter->queue = cld_filter->element.queue_number;
7769         rte_memcpy(tunnel_filter->input.general_fields,
7770                    cld_filter->general_fields,
7771                    sizeof(cld_filter->general_fields));
7772
7773         return 0;
7774 }
7775
7776 /* Check if there exists the tunnel filter */
7777 struct i40e_tunnel_filter *
7778 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7779                              const struct i40e_tunnel_filter_input *input)
7780 {
7781         int ret;
7782
7783         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7784         if (ret < 0)
7785                 return NULL;
7786
7787         return tunnel_rule->hash_map[ret];
7788 }
7789
7790 /* Add a tunnel filter into the SW list */
7791 static int
7792 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7793                              struct i40e_tunnel_filter *tunnel_filter)
7794 {
7795         struct i40e_tunnel_rule *rule = &pf->tunnel;
7796         int ret;
7797
7798         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7799         if (ret < 0) {
7800                 PMD_DRV_LOG(ERR,
7801                             "Failed to insert tunnel filter to hash table %d!",
7802                             ret);
7803                 return ret;
7804         }
7805         rule->hash_map[ret] = tunnel_filter;
7806
7807         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7808
7809         return 0;
7810 }
7811
7812 /* Delete a tunnel filter from the SW list */
7813 int
7814 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7815                           struct i40e_tunnel_filter_input *input)
7816 {
7817         struct i40e_tunnel_rule *rule = &pf->tunnel;
7818         struct i40e_tunnel_filter *tunnel_filter;
7819         int ret;
7820
7821         ret = rte_hash_del_key(rule->hash_table, input);
7822         if (ret < 0) {
7823                 PMD_DRV_LOG(ERR,
7824                             "Failed to delete tunnel filter to hash table %d!",
7825                             ret);
7826                 return ret;
7827         }
7828         tunnel_filter = rule->hash_map[ret];
7829         rule->hash_map[ret] = NULL;
7830
7831         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7832         rte_free(tunnel_filter);
7833
7834         return 0;
7835 }
7836
7837 int
7838 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7839                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7840                         uint8_t add)
7841 {
7842         uint16_t ip_type;
7843         uint32_t ipv4_addr, ipv4_addr_le;
7844         uint8_t i, tun_type = 0;
7845         /* internal varialbe to convert ipv6 byte order */
7846         uint32_t convert_ipv6[4];
7847         int val, ret = 0;
7848         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7849         struct i40e_vsi *vsi = pf->main_vsi;
7850         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7851         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7852         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7853         struct i40e_tunnel_filter *tunnel, *node;
7854         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7855
7856         cld_filter = rte_zmalloc("tunnel_filter",
7857                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7858         0);
7859
7860         if (NULL == cld_filter) {
7861                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7862                 return -ENOMEM;
7863         }
7864         pfilter = cld_filter;
7865
7866         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7867                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7868         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7869                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7870
7871         pfilter->element.inner_vlan =
7872                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7873         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7874                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7875                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7876                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7877                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7878                                 &ipv4_addr_le,
7879                                 sizeof(pfilter->element.ipaddr.v4.data));
7880         } else {
7881                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7882                 for (i = 0; i < 4; i++) {
7883                         convert_ipv6[i] =
7884                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7885                 }
7886                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7887                            &convert_ipv6,
7888                            sizeof(pfilter->element.ipaddr.v6.data));
7889         }
7890
7891         /* check tunneled type */
7892         switch (tunnel_filter->tunnel_type) {
7893         case RTE_TUNNEL_TYPE_VXLAN:
7894                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7895                 break;
7896         case RTE_TUNNEL_TYPE_NVGRE:
7897                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7898                 break;
7899         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7900                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7901                 break;
7902         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7903                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7904                 break;
7905         default:
7906                 /* Other tunnel types is not supported. */
7907                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7908                 rte_free(cld_filter);
7909                 return -EINVAL;
7910         }
7911
7912         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7913                                        &pfilter->element.flags);
7914         if (val < 0) {
7915                 rte_free(cld_filter);
7916                 return -EINVAL;
7917         }
7918
7919         pfilter->element.flags |= rte_cpu_to_le_16(
7920                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7921                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7922         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7923         pfilter->element.queue_number =
7924                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7925
7926         /* Check if there is the filter in SW list */
7927         memset(&check_filter, 0, sizeof(check_filter));
7928         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7929         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7930         if (add && node) {
7931                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7932                 rte_free(cld_filter);
7933                 return -EINVAL;
7934         }
7935
7936         if (!add && !node) {
7937                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7938                 rte_free(cld_filter);
7939                 return -EINVAL;
7940         }
7941
7942         if (add) {
7943                 ret = i40e_aq_add_cloud_filters(hw,
7944                                         vsi->seid, &cld_filter->element, 1);
7945                 if (ret < 0) {
7946                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7947                         rte_free(cld_filter);
7948                         return -ENOTSUP;
7949                 }
7950                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7951                 if (tunnel == NULL) {
7952                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7953                         rte_free(cld_filter);
7954                         return -ENOMEM;
7955                 }
7956
7957                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7958                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7959                 if (ret < 0)
7960                         rte_free(tunnel);
7961         } else {
7962                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7963                                                    &cld_filter->element, 1);
7964                 if (ret < 0) {
7965                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7966                         rte_free(cld_filter);
7967                         return -ENOTSUP;
7968                 }
7969                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7970         }
7971
7972         rte_free(cld_filter);
7973         return ret;
7974 }
7975
7976 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7977 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7978 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7979 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7980 #define I40E_TR_GRE_KEY_MASK                    0x400
7981 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7982 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7983 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0 0x49
7984 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0 0x41
7985 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0 0x80
7986 #define I40E_DIRECTION_INGRESS_KEY              0x8000
7987 #define I40E_TR_L4_TYPE_TCP                     0x2
7988 #define I40E_TR_L4_TYPE_UDP                     0x4
7989 #define I40E_TR_L4_TYPE_SCTP                    0x8
7990
7991 static enum
7992 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7993 {
7994         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7995         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7996         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7997         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7998         enum i40e_status_code status = I40E_SUCCESS;
7999
8000         if (pf->support_multi_driver) {
8001                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8002                 return I40E_NOT_SUPPORTED;
8003         }
8004
8005         memset(&filter_replace, 0,
8006                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8007         memset(&filter_replace_buf, 0,
8008                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8009
8010         /* create L1 filter */
8011         filter_replace.old_filter_type =
8012                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8013         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8014         filter_replace.tr_bit = 0;
8015
8016         /* Prepare the buffer, 3 entries */
8017         filter_replace_buf.data[0] =
8018                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8019         filter_replace_buf.data[0] |=
8020                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8021         filter_replace_buf.data[2] = 0xFF;
8022         filter_replace_buf.data[3] = 0xFF;
8023         filter_replace_buf.data[4] =
8024                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8025         filter_replace_buf.data[4] |=
8026                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8027         filter_replace_buf.data[7] = 0xF0;
8028         filter_replace_buf.data[8]
8029                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
8030         filter_replace_buf.data[8] |=
8031                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8032         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
8033                 I40E_TR_GENEVE_KEY_MASK |
8034                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
8035         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
8036                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
8037                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
8038
8039         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8040                                                &filter_replace_buf);
8041         if (!status && (filter_replace.old_filter_type !=
8042                         filter_replace.new_filter_type))
8043                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8044                             " original: 0x%x, new: 0x%x",
8045                             dev->device->name,
8046                             filter_replace.old_filter_type,
8047                             filter_replace.new_filter_type);
8048
8049         return status;
8050 }
8051
8052 static enum
8053 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
8054 {
8055         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8056         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8057         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8058         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8059         enum i40e_status_code status = I40E_SUCCESS;
8060
8061         if (pf->support_multi_driver) {
8062                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8063                 return I40E_NOT_SUPPORTED;
8064         }
8065
8066         /* For MPLSoUDP */
8067         memset(&filter_replace, 0,
8068                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8069         memset(&filter_replace_buf, 0,
8070                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8071         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8072                 I40E_AQC_MIRROR_CLOUD_FILTER;
8073         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8074         filter_replace.new_filter_type =
8075                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8076         /* Prepare the buffer, 2 entries */
8077         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8078         filter_replace_buf.data[0] |=
8079                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8080         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8081         filter_replace_buf.data[4] |=
8082                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8083         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8084                                                &filter_replace_buf);
8085         if (status < 0)
8086                 return status;
8087         if (filter_replace.old_filter_type !=
8088             filter_replace.new_filter_type)
8089                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8090                             " original: 0x%x, new: 0x%x",
8091                             dev->device->name,
8092                             filter_replace.old_filter_type,
8093                             filter_replace.new_filter_type);
8094
8095         /* For MPLSoGRE */
8096         memset(&filter_replace, 0,
8097                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8098         memset(&filter_replace_buf, 0,
8099                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8100
8101         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
8102                 I40E_AQC_MIRROR_CLOUD_FILTER;
8103         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
8104         filter_replace.new_filter_type =
8105                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8106         /* Prepare the buffer, 2 entries */
8107         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8108         filter_replace_buf.data[0] |=
8109                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8110         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
8111         filter_replace_buf.data[4] |=
8112                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8113
8114         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8115                                                &filter_replace_buf);
8116         if (!status && (filter_replace.old_filter_type !=
8117                         filter_replace.new_filter_type))
8118                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8119                             " original: 0x%x, new: 0x%x",
8120                             dev->device->name,
8121                             filter_replace.old_filter_type,
8122                             filter_replace.new_filter_type);
8123
8124         return status;
8125 }
8126
8127 static enum i40e_status_code
8128 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
8129 {
8130         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8131         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8132         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8133         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8134         enum i40e_status_code status = I40E_SUCCESS;
8135
8136         if (pf->support_multi_driver) {
8137                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8138                 return I40E_NOT_SUPPORTED;
8139         }
8140
8141         /* For GTP-C */
8142         memset(&filter_replace, 0,
8143                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8144         memset(&filter_replace_buf, 0,
8145                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8146         /* create L1 filter */
8147         filter_replace.old_filter_type =
8148                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
8149         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
8150         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
8151                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8152         /* Prepare the buffer, 2 entries */
8153         filter_replace_buf.data[0] =
8154                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8155         filter_replace_buf.data[0] |=
8156                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8157         filter_replace_buf.data[2] = 0xFF;
8158         filter_replace_buf.data[3] = 0xFF;
8159         filter_replace_buf.data[4] =
8160                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8161         filter_replace_buf.data[4] |=
8162                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8163         filter_replace_buf.data[6] = 0xFF;
8164         filter_replace_buf.data[7] = 0xFF;
8165         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8166                                                &filter_replace_buf);
8167         if (status < 0)
8168                 return status;
8169         if (filter_replace.old_filter_type !=
8170             filter_replace.new_filter_type)
8171                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8172                             " original: 0x%x, new: 0x%x",
8173                             dev->device->name,
8174                             filter_replace.old_filter_type,
8175                             filter_replace.new_filter_type);
8176
8177         /* for GTP-U */
8178         memset(&filter_replace, 0,
8179                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8180         memset(&filter_replace_buf, 0,
8181                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8182         /* create L1 filter */
8183         filter_replace.old_filter_type =
8184                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8185         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8186         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8187                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8188         /* Prepare the buffer, 2 entries */
8189         filter_replace_buf.data[0] =
8190                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8191         filter_replace_buf.data[0] |=
8192                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8193         filter_replace_buf.data[2] = 0xFF;
8194         filter_replace_buf.data[3] = 0xFF;
8195         filter_replace_buf.data[4] =
8196                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8197         filter_replace_buf.data[4] |=
8198                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8199         filter_replace_buf.data[6] = 0xFF;
8200         filter_replace_buf.data[7] = 0xFF;
8201
8202         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8203                                                &filter_replace_buf);
8204         if (!status && (filter_replace.old_filter_type !=
8205                         filter_replace.new_filter_type))
8206                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8207                             " original: 0x%x, new: 0x%x",
8208                             dev->device->name,
8209                             filter_replace.old_filter_type,
8210                             filter_replace.new_filter_type);
8211
8212         return status;
8213 }
8214
8215 static enum
8216 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8217 {
8218         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8219         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8220         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8221         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8222         enum i40e_status_code status = I40E_SUCCESS;
8223
8224         if (pf->support_multi_driver) {
8225                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8226                 return I40E_NOT_SUPPORTED;
8227         }
8228
8229         /* for GTP-C */
8230         memset(&filter_replace, 0,
8231                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8232         memset(&filter_replace_buf, 0,
8233                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8234         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8235         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8236         filter_replace.new_filter_type =
8237                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8238         /* Prepare the buffer, 2 entries */
8239         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8240         filter_replace_buf.data[0] |=
8241                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8242         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8243         filter_replace_buf.data[4] |=
8244                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8245         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8246                                                &filter_replace_buf);
8247         if (status < 0)
8248                 return status;
8249         if (filter_replace.old_filter_type !=
8250             filter_replace.new_filter_type)
8251                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8252                             " original: 0x%x, new: 0x%x",
8253                             dev->device->name,
8254                             filter_replace.old_filter_type,
8255                             filter_replace.new_filter_type);
8256
8257         /* for GTP-U */
8258         memset(&filter_replace, 0,
8259                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8260         memset(&filter_replace_buf, 0,
8261                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8262         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8263         filter_replace.old_filter_type =
8264                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8265         filter_replace.new_filter_type =
8266                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8267         /* Prepare the buffer, 2 entries */
8268         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8269         filter_replace_buf.data[0] |=
8270                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8271         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8272         filter_replace_buf.data[4] |=
8273                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8274
8275         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8276                                                &filter_replace_buf);
8277         if (!status && (filter_replace.old_filter_type !=
8278                         filter_replace.new_filter_type))
8279                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8280                             " original: 0x%x, new: 0x%x",
8281                             dev->device->name,
8282                             filter_replace.old_filter_type,
8283                             filter_replace.new_filter_type);
8284
8285         return status;
8286 }
8287
8288 static enum i40e_status_code
8289 i40e_replace_port_l1_filter(struct i40e_pf *pf,
8290                             enum i40e_l4_port_type l4_port_type)
8291 {
8292         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8293         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8294         enum i40e_status_code status = I40E_SUCCESS;
8295         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8296         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8297
8298         if (pf->support_multi_driver) {
8299                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
8300                 return I40E_NOT_SUPPORTED;
8301         }
8302
8303         memset(&filter_replace, 0,
8304                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8305         memset(&filter_replace_buf, 0,
8306                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8307
8308         /* create L1 filter */
8309         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8310                 filter_replace.old_filter_type =
8311                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8312                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
8313                 filter_replace_buf.data[8] =
8314                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_SRC_PORT;
8315         } else {
8316                 filter_replace.old_filter_type =
8317                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
8318                 filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X10;
8319                 filter_replace_buf.data[8] =
8320                         I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_DST_PORT;
8321         }
8322
8323         filter_replace.tr_bit = 0;
8324         /* Prepare the buffer, 3 entries */
8325         filter_replace_buf.data[0] =
8326                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_DIRECTION_WORD0;
8327         filter_replace_buf.data[0] |=
8328                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8329         filter_replace_buf.data[2] = 0x00;
8330         filter_replace_buf.data[3] =
8331                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_INGRESS_WORD0;
8332         filter_replace_buf.data[4] =
8333                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_PORT_TR_WORD0;
8334         filter_replace_buf.data[4] |=
8335                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8336         filter_replace_buf.data[5] = 0x00;
8337         filter_replace_buf.data[6] = I40E_TR_L4_TYPE_UDP |
8338                 I40E_TR_L4_TYPE_TCP |
8339                 I40E_TR_L4_TYPE_SCTP;
8340         filter_replace_buf.data[7] = 0x00;
8341         filter_replace_buf.data[8] |=
8342                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8343         filter_replace_buf.data[9] = 0x00;
8344         filter_replace_buf.data[10] = 0xFF;
8345         filter_replace_buf.data[11] = 0xFF;
8346
8347         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8348                                                &filter_replace_buf);
8349         if (!status && filter_replace.old_filter_type !=
8350             filter_replace.new_filter_type)
8351                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8352                             " original: 0x%x, new: 0x%x",
8353                             dev->device->name,
8354                             filter_replace.old_filter_type,
8355                             filter_replace.new_filter_type);
8356
8357         return status;
8358 }
8359
8360 static enum i40e_status_code
8361 i40e_replace_port_cloud_filter(struct i40e_pf *pf,
8362                                enum i40e_l4_port_type l4_port_type)
8363 {
8364         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8365         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8366         enum i40e_status_code status = I40E_SUCCESS;
8367         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8368         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8369
8370         if (pf->support_multi_driver) {
8371                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8372                 return I40E_NOT_SUPPORTED;
8373         }
8374
8375         memset(&filter_replace, 0,
8376                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8377         memset(&filter_replace_buf, 0,
8378                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8379
8380         if (l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8381                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
8382                 filter_replace.new_filter_type =
8383                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8384                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X11;
8385         } else {
8386                 filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
8387                 filter_replace.new_filter_type =
8388                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8389                 filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
8390         }
8391
8392         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8393         filter_replace.tr_bit = 0;
8394         /* Prepare the buffer, 2 entries */
8395         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8396         filter_replace_buf.data[0] |=
8397                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8398         filter_replace_buf.data[4] |=
8399                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8400         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8401                                                &filter_replace_buf);
8402
8403         if (!status && filter_replace.old_filter_type !=
8404             filter_replace.new_filter_type)
8405                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8406                             " original: 0x%x, new: 0x%x",
8407                             dev->device->name,
8408                             filter_replace.old_filter_type,
8409                             filter_replace.new_filter_type);
8410
8411         return status;
8412 }
8413
8414 int
8415 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8416                       struct i40e_tunnel_filter_conf *tunnel_filter,
8417                       uint8_t add)
8418 {
8419         uint16_t ip_type;
8420         uint32_t ipv4_addr, ipv4_addr_le;
8421         uint8_t i, tun_type = 0;
8422         /* internal variable to convert ipv6 byte order */
8423         uint32_t convert_ipv6[4];
8424         int val, ret = 0;
8425         struct i40e_pf_vf *vf = NULL;
8426         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8427         struct i40e_vsi *vsi;
8428         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8429         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8430         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8431         struct i40e_tunnel_filter *tunnel, *node;
8432         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8433         uint32_t teid_le;
8434         bool big_buffer = 0;
8435
8436         cld_filter = rte_zmalloc("tunnel_filter",
8437                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8438                          0);
8439
8440         if (cld_filter == NULL) {
8441                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8442                 return -ENOMEM;
8443         }
8444         pfilter = cld_filter;
8445
8446         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8447                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8448         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8449                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8450
8451         pfilter->element.inner_vlan =
8452                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8453         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8454                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8455                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8456                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8457                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8458                                 &ipv4_addr_le,
8459                                 sizeof(pfilter->element.ipaddr.v4.data));
8460         } else {
8461                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8462                 for (i = 0; i < 4; i++) {
8463                         convert_ipv6[i] =
8464                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8465                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8466                 }
8467                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8468                            &convert_ipv6,
8469                            sizeof(pfilter->element.ipaddr.v6.data));
8470         }
8471
8472         /* check tunneled type */
8473         switch (tunnel_filter->tunnel_type) {
8474         case I40E_TUNNEL_TYPE_VXLAN:
8475                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8476                 break;
8477         case I40E_TUNNEL_TYPE_NVGRE:
8478                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8479                 break;
8480         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8481                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8482                 break;
8483         case I40E_TUNNEL_TYPE_MPLSoUDP:
8484                 if (!pf->mpls_replace_flag) {
8485                         i40e_replace_mpls_l1_filter(pf);
8486                         i40e_replace_mpls_cloud_filter(pf);
8487                         pf->mpls_replace_flag = 1;
8488                 }
8489                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8490                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8491                         teid_le >> 4;
8492                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8493                         (teid_le & 0xF) << 12;
8494                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8495                         0x40;
8496                 big_buffer = 1;
8497                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8498                 break;
8499         case I40E_TUNNEL_TYPE_MPLSoGRE:
8500                 if (!pf->mpls_replace_flag) {
8501                         i40e_replace_mpls_l1_filter(pf);
8502                         i40e_replace_mpls_cloud_filter(pf);
8503                         pf->mpls_replace_flag = 1;
8504                 }
8505                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8506                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8507                         teid_le >> 4;
8508                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8509                         (teid_le & 0xF) << 12;
8510                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8511                         0x0;
8512                 big_buffer = 1;
8513                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8514                 break;
8515         case I40E_TUNNEL_TYPE_GTPC:
8516                 if (!pf->gtp_replace_flag) {
8517                         i40e_replace_gtp_l1_filter(pf);
8518                         i40e_replace_gtp_cloud_filter(pf);
8519                         pf->gtp_replace_flag = 1;
8520                 }
8521                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8522                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8523                         (teid_le >> 16) & 0xFFFF;
8524                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8525                         teid_le & 0xFFFF;
8526                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8527                         0x0;
8528                 big_buffer = 1;
8529                 break;
8530         case I40E_TUNNEL_TYPE_GTPU:
8531                 if (!pf->gtp_replace_flag) {
8532                         i40e_replace_gtp_l1_filter(pf);
8533                         i40e_replace_gtp_cloud_filter(pf);
8534                         pf->gtp_replace_flag = 1;
8535                 }
8536                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8537                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8538                         (teid_le >> 16) & 0xFFFF;
8539                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8540                         teid_le & 0xFFFF;
8541                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8542                         0x0;
8543                 big_buffer = 1;
8544                 break;
8545         case I40E_TUNNEL_TYPE_QINQ:
8546                 if (!pf->qinq_replace_flag) {
8547                         ret = i40e_cloud_filter_qinq_create(pf);
8548                         if (ret < 0)
8549                                 PMD_DRV_LOG(DEBUG,
8550                                             "QinQ tunnel filter already created.");
8551                         pf->qinq_replace_flag = 1;
8552                 }
8553                 /*      Add in the General fields the values of
8554                  *      the Outer and Inner VLAN
8555                  *      Big Buffer should be set, see changes in
8556                  *      i40e_aq_add_cloud_filters
8557                  */
8558                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8559                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8560                 big_buffer = 1;
8561                 break;
8562         case I40E_CLOUD_TYPE_UDP:
8563         case I40E_CLOUD_TYPE_TCP:
8564         case I40E_CLOUD_TYPE_SCTP:
8565                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC) {
8566                         if (!pf->sport_replace_flag) {
8567                                 i40e_replace_port_l1_filter(pf,
8568                                                 tunnel_filter->l4_port_type);
8569                                 i40e_replace_port_cloud_filter(pf,
8570                                                 tunnel_filter->l4_port_type);
8571                                 pf->sport_replace_flag = 1;
8572                         }
8573                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8574                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8575                                 I40E_DIRECTION_INGRESS_KEY;
8576
8577                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8578                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8579                                         I40E_TR_L4_TYPE_UDP;
8580                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8581                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8582                                         I40E_TR_L4_TYPE_TCP;
8583                         else
8584                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8585                                         I40E_TR_L4_TYPE_SCTP;
8586
8587                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8588                                 (teid_le >> 16) & 0xFFFF;
8589                         big_buffer = 1;
8590                 } else {
8591                         if (!pf->dport_replace_flag) {
8592                                 i40e_replace_port_l1_filter(pf,
8593                                                 tunnel_filter->l4_port_type);
8594                                 i40e_replace_port_cloud_filter(pf,
8595                                                 tunnel_filter->l4_port_type);
8596                                 pf->dport_replace_flag = 1;
8597                         }
8598                         teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8599                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0] =
8600                                 I40E_DIRECTION_INGRESS_KEY;
8601
8602                         if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP)
8603                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8604                                         I40E_TR_L4_TYPE_UDP;
8605                         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP)
8606                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8607                                         I40E_TR_L4_TYPE_TCP;
8608                         else
8609                                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1] =
8610                                         I40E_TR_L4_TYPE_SCTP;
8611
8612                         pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2] =
8613                                 (teid_le >> 16) & 0xFFFF;
8614                         big_buffer = 1;
8615                 }
8616
8617                 break;
8618         default:
8619                 /* Other tunnel types is not supported. */
8620                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8621                 rte_free(cld_filter);
8622                 return -EINVAL;
8623         }
8624
8625         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8626                 pfilter->element.flags =
8627                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8628         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8629                 pfilter->element.flags =
8630                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8631         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8632                 pfilter->element.flags =
8633                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8634         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8635                 pfilter->element.flags =
8636                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8637         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8638                 pfilter->element.flags |=
8639                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8640         else if (tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_UDP ||
8641                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_TCP ||
8642                  tunnel_filter->tunnel_type == I40E_CLOUD_TYPE_SCTP) {
8643                 if (tunnel_filter->l4_port_type == I40E_L4_PORT_TYPE_SRC)
8644                         pfilter->element.flags |=
8645                                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8646                 else
8647                         pfilter->element.flags |=
8648                                 I40E_AQC_ADD_CLOUD_FILTER_0X10;
8649         } else {
8650                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8651                                                 &pfilter->element.flags);
8652                 if (val < 0) {
8653                         rte_free(cld_filter);
8654                         return -EINVAL;
8655                 }
8656         }
8657
8658         pfilter->element.flags |= rte_cpu_to_le_16(
8659                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8660                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8661         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8662         pfilter->element.queue_number =
8663                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8664
8665         if (!tunnel_filter->is_to_vf)
8666                 vsi = pf->main_vsi;
8667         else {
8668                 if (tunnel_filter->vf_id >= pf->vf_num) {
8669                         PMD_DRV_LOG(ERR, "Invalid argument.");
8670                         rte_free(cld_filter);
8671                         return -EINVAL;
8672                 }
8673                 vf = &pf->vfs[tunnel_filter->vf_id];
8674                 vsi = vf->vsi;
8675         }
8676
8677         /* Check if there is the filter in SW list */
8678         memset(&check_filter, 0, sizeof(check_filter));
8679         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8680         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8681         check_filter.vf_id = tunnel_filter->vf_id;
8682         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8683         if (add && node) {
8684                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8685                 rte_free(cld_filter);
8686                 return -EINVAL;
8687         }
8688
8689         if (!add && !node) {
8690                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8691                 rte_free(cld_filter);
8692                 return -EINVAL;
8693         }
8694
8695         if (add) {
8696                 if (big_buffer)
8697                         ret = i40e_aq_add_cloud_filters_bb(hw,
8698                                                    vsi->seid, cld_filter, 1);
8699                 else
8700                         ret = i40e_aq_add_cloud_filters(hw,
8701                                         vsi->seid, &cld_filter->element, 1);
8702                 if (ret < 0) {
8703                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8704                         rte_free(cld_filter);
8705                         return -ENOTSUP;
8706                 }
8707                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8708                 if (tunnel == NULL) {
8709                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8710                         rte_free(cld_filter);
8711                         return -ENOMEM;
8712                 }
8713
8714                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8715                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8716                 if (ret < 0)
8717                         rte_free(tunnel);
8718         } else {
8719                 if (big_buffer)
8720                         ret = i40e_aq_rem_cloud_filters_bb(
8721                                 hw, vsi->seid, cld_filter, 1);
8722                 else
8723                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8724                                                 &cld_filter->element, 1);
8725                 if (ret < 0) {
8726                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8727                         rte_free(cld_filter);
8728                         return -ENOTSUP;
8729                 }
8730                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8731         }
8732
8733         rte_free(cld_filter);
8734         return ret;
8735 }
8736
8737 static int
8738 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8739 {
8740         uint8_t i;
8741
8742         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8743                 if (pf->vxlan_ports[i] == port)
8744                         return i;
8745         }
8746
8747         return -1;
8748 }
8749
8750 static int
8751 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8752 {
8753         int  idx, ret;
8754         uint8_t filter_idx = 0;
8755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8756
8757         idx = i40e_get_vxlan_port_idx(pf, port);
8758
8759         /* Check if port already exists */
8760         if (idx >= 0) {
8761                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8762                 return -EINVAL;
8763         }
8764
8765         /* Now check if there is space to add the new port */
8766         idx = i40e_get_vxlan_port_idx(pf, 0);
8767         if (idx < 0) {
8768                 PMD_DRV_LOG(ERR,
8769                         "Maximum number of UDP ports reached, not adding port %d",
8770                         port);
8771                 return -ENOSPC;
8772         }
8773
8774         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8775                                         &filter_idx, NULL);
8776         if (ret < 0) {
8777                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8778                 return -1;
8779         }
8780
8781         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8782                          port,  filter_idx);
8783
8784         /* New port: add it and mark its index in the bitmap */
8785         pf->vxlan_ports[idx] = port;
8786         pf->vxlan_bitmap |= (1 << idx);
8787
8788         if (!(pf->flags & I40E_FLAG_VXLAN))
8789                 pf->flags |= I40E_FLAG_VXLAN;
8790
8791         return 0;
8792 }
8793
8794 static int
8795 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8796 {
8797         int idx;
8798         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8799
8800         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8801                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8802                 return -EINVAL;
8803         }
8804
8805         idx = i40e_get_vxlan_port_idx(pf, port);
8806
8807         if (idx < 0) {
8808                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8809                 return -EINVAL;
8810         }
8811
8812         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8813                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8814                 return -1;
8815         }
8816
8817         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8818                         port, idx);
8819
8820         pf->vxlan_ports[idx] = 0;
8821         pf->vxlan_bitmap &= ~(1 << idx);
8822
8823         if (!pf->vxlan_bitmap)
8824                 pf->flags &= ~I40E_FLAG_VXLAN;
8825
8826         return 0;
8827 }
8828
8829 /* Add UDP tunneling port */
8830 static int
8831 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8832                              struct rte_eth_udp_tunnel *udp_tunnel)
8833 {
8834         int ret = 0;
8835         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8836
8837         if (udp_tunnel == NULL)
8838                 return -EINVAL;
8839
8840         switch (udp_tunnel->prot_type) {
8841         case RTE_TUNNEL_TYPE_VXLAN:
8842                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8843                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8844                 break;
8845         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8846                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8847                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8848                 break;
8849         case RTE_TUNNEL_TYPE_GENEVE:
8850         case RTE_TUNNEL_TYPE_TEREDO:
8851                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8852                 ret = -1;
8853                 break;
8854
8855         default:
8856                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8857                 ret = -1;
8858                 break;
8859         }
8860
8861         return ret;
8862 }
8863
8864 /* Remove UDP tunneling port */
8865 static int
8866 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8867                              struct rte_eth_udp_tunnel *udp_tunnel)
8868 {
8869         int ret = 0;
8870         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8871
8872         if (udp_tunnel == NULL)
8873                 return -EINVAL;
8874
8875         switch (udp_tunnel->prot_type) {
8876         case RTE_TUNNEL_TYPE_VXLAN:
8877         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8878                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8879                 break;
8880         case RTE_TUNNEL_TYPE_GENEVE:
8881         case RTE_TUNNEL_TYPE_TEREDO:
8882                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8883                 ret = -1;
8884                 break;
8885         default:
8886                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8887                 ret = -1;
8888                 break;
8889         }
8890
8891         return ret;
8892 }
8893
8894 /* Calculate the maximum number of contiguous PF queues that are configured */
8895 static int
8896 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8897 {
8898         struct rte_eth_dev_data *data = pf->dev_data;
8899         int i, num;
8900         struct i40e_rx_queue *rxq;
8901
8902         num = 0;
8903         for (i = 0; i < pf->lan_nb_qps; i++) {
8904                 rxq = data->rx_queues[i];
8905                 if (rxq && rxq->q_set)
8906                         num++;
8907                 else
8908                         break;
8909         }
8910
8911         return num;
8912 }
8913
8914 /* Configure RSS */
8915 static int
8916 i40e_pf_config_rss(struct i40e_pf *pf)
8917 {
8918         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8919         struct rte_eth_rss_conf rss_conf;
8920         uint32_t i, lut = 0;
8921         uint16_t j, num;
8922
8923         /*
8924          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8925          * It's necessary to calculate the actual PF queues that are configured.
8926          */
8927         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8928                 num = i40e_pf_calc_configured_queues_num(pf);
8929         else
8930                 num = pf->dev_data->nb_rx_queues;
8931
8932         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8933         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8934                         num);
8935
8936         if (num == 0) {
8937                 PMD_INIT_LOG(ERR,
8938                         "No PF queues are configured to enable RSS for port %u",
8939                         pf->dev_data->port_id);
8940                 return -ENOTSUP;
8941         }
8942
8943         if (pf->adapter->rss_reta_updated == 0) {
8944                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8945                         if (j == num)
8946                                 j = 0;
8947                         lut = (lut << 8) | (j & ((0x1 <<
8948                                 hw->func_caps.rss_table_entry_width) - 1));
8949                         if ((i & 3) == 3)
8950                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8951                                                rte_bswap32(lut));
8952                 }
8953         }
8954
8955         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8956         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8957                 i40e_pf_disable_rss(pf);
8958                 return 0;
8959         }
8960         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8961                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8962                 /* Random default keys */
8963                 static uint32_t rss_key_default[] = {0x6b793944,
8964                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8965                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8966                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8967
8968                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8969                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8970                                                         sizeof(uint32_t);
8971         }
8972
8973         return i40e_hw_rss_hash_set(pf, &rss_conf);
8974 }
8975
8976 static int
8977 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8978                                struct rte_eth_tunnel_filter_conf *filter)
8979 {
8980         if (pf == NULL || filter == NULL) {
8981                 PMD_DRV_LOG(ERR, "Invalid parameter");
8982                 return -EINVAL;
8983         }
8984
8985         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8986                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8987                 return -EINVAL;
8988         }
8989
8990         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8991                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8992                 return -EINVAL;
8993         }
8994
8995         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8996                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8997                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8998                 return -EINVAL;
8999         }
9000
9001         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
9002                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
9003                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
9004                 return -EINVAL;
9005         }
9006
9007         return 0;
9008 }
9009
9010 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
9011 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
9012 int
9013 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
9014 {
9015         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9016         uint32_t val, reg;
9017         int ret = -EINVAL;
9018
9019         if (pf->support_multi_driver) {
9020                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
9021                 return -ENOTSUP;
9022         }
9023
9024         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
9025         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
9026
9027         if (len == 3) {
9028                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
9029         } else if (len == 4) {
9030                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
9031         } else {
9032                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
9033                 return ret;
9034         }
9035
9036         if (reg != val) {
9037                 ret = i40e_aq_debug_write_global_register(hw,
9038                                                    I40E_GL_PRS_FVBM(2),
9039                                                    reg, NULL);
9040                 if (ret != 0)
9041                         return ret;
9042                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
9043                             "with value 0x%08x",
9044                             I40E_GL_PRS_FVBM(2), reg);
9045         } else {
9046                 ret = 0;
9047         }
9048         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
9049                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
9050
9051         return ret;
9052 }
9053
9054 static int
9055 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
9056 {
9057         int ret = -EINVAL;
9058
9059         if (!hw || !cfg)
9060                 return -EINVAL;
9061
9062         switch (cfg->cfg_type) {
9063         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
9064                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
9065                 break;
9066         default:
9067                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
9068                 break;
9069         }
9070
9071         return ret;
9072 }
9073
9074 static int
9075 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
9076                                enum rte_filter_op filter_op,
9077                                void *arg)
9078 {
9079         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9080         int ret = I40E_ERR_PARAM;
9081
9082         switch (filter_op) {
9083         case RTE_ETH_FILTER_SET:
9084                 ret = i40e_dev_global_config_set(hw,
9085                         (struct rte_eth_global_cfg *)arg);
9086                 break;
9087         default:
9088                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9089                 break;
9090         }
9091
9092         return ret;
9093 }
9094
9095 static int
9096 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
9097                           enum rte_filter_op filter_op,
9098                           void *arg)
9099 {
9100         struct rte_eth_tunnel_filter_conf *filter;
9101         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
9102         int ret = I40E_SUCCESS;
9103
9104         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
9105
9106         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
9107                 return I40E_ERR_PARAM;
9108
9109         switch (filter_op) {
9110         case RTE_ETH_FILTER_NOP:
9111                 if (!(pf->flags & I40E_FLAG_VXLAN))
9112                         ret = I40E_NOT_SUPPORTED;
9113                 break;
9114         case RTE_ETH_FILTER_ADD:
9115                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
9116                 break;
9117         case RTE_ETH_FILTER_DELETE:
9118                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
9119                 break;
9120         default:
9121                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
9122                 ret = I40E_ERR_PARAM;
9123                 break;
9124         }
9125
9126         return ret;
9127 }
9128
9129 static int
9130 i40e_pf_config_mq_rx(struct i40e_pf *pf)
9131 {
9132         int ret = 0;
9133         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
9134
9135         /* RSS setup */
9136         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
9137                 ret = i40e_pf_config_rss(pf);
9138         else
9139                 i40e_pf_disable_rss(pf);
9140
9141         return ret;
9142 }
9143
9144 /* Get the symmetric hash enable configurations per port */
9145 static void
9146 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
9147 {
9148         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9149
9150         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
9151 }
9152
9153 /* Set the symmetric hash enable configurations per port */
9154 static void
9155 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
9156 {
9157         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
9158
9159         if (enable > 0) {
9160                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
9161                         PMD_DRV_LOG(INFO,
9162                                 "Symmetric hash has already been enabled");
9163                         return;
9164                 }
9165                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9166         } else {
9167                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
9168                         PMD_DRV_LOG(INFO,
9169                                 "Symmetric hash has already been disabled");
9170                         return;
9171                 }
9172                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
9173         }
9174         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
9175         I40E_WRITE_FLUSH(hw);
9176 }
9177
9178 /*
9179  * Get global configurations of hash function type and symmetric hash enable
9180  * per flow type (pctype). Note that global configuration means it affects all
9181  * the ports on the same NIC.
9182  */
9183 static int
9184 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
9185                                    struct rte_eth_hash_global_conf *g_cfg)
9186 {
9187         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9188         uint32_t reg;
9189         uint16_t i, j;
9190
9191         memset(g_cfg, 0, sizeof(*g_cfg));
9192         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9193         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
9194                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
9195         else
9196                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
9197         PMD_DRV_LOG(DEBUG, "Hash function is %s",
9198                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
9199
9200         /*
9201          * As i40e supports less than 64 flow types, only first 64 bits need to
9202          * be checked.
9203          */
9204         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9205                 g_cfg->valid_bit_mask[i] = 0ULL;
9206                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
9207         }
9208
9209         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
9210
9211         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
9212                 if (!adapter->pctypes_tbl[i])
9213                         continue;
9214                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9215                      j < I40E_FILTER_PCTYPE_MAX; j++) {
9216                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
9217                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
9218                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
9219                                         g_cfg->sym_hash_enable_mask[0] |=
9220                                                                 (1ULL << i);
9221                                 }
9222                         }
9223                 }
9224         }
9225
9226         return 0;
9227 }
9228
9229 static int
9230 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
9231                               const struct rte_eth_hash_global_conf *g_cfg)
9232 {
9233         uint32_t i;
9234         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
9235
9236         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
9237                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
9238                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
9239                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
9240                                                 g_cfg->hash_func);
9241                 return -EINVAL;
9242         }
9243
9244         /*
9245          * As i40e supports less than 64 flow types, only first 64 bits need to
9246          * be checked.
9247          */
9248         mask0 = g_cfg->valid_bit_mask[0];
9249         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
9250                 if (i == 0) {
9251                         /* Check if any unsupported flow type configured */
9252                         if ((mask0 | i40e_mask) ^ i40e_mask)
9253                                 goto mask_err;
9254                 } else {
9255                         if (g_cfg->valid_bit_mask[i])
9256                                 goto mask_err;
9257                 }
9258         }
9259
9260         return 0;
9261
9262 mask_err:
9263         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
9264
9265         return -EINVAL;
9266 }
9267
9268 /*
9269  * Set global configurations of hash function type and symmetric hash enable
9270  * per flow type (pctype). Note any modifying global configuration will affect
9271  * all the ports on the same NIC.
9272  */
9273 static int
9274 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
9275                                    struct rte_eth_hash_global_conf *g_cfg)
9276 {
9277         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
9278         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9279         int ret;
9280         uint16_t i, j;
9281         uint32_t reg;
9282         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
9283
9284         if (pf->support_multi_driver) {
9285                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
9286                 return -ENOTSUP;
9287         }
9288
9289         /* Check the input parameters */
9290         ret = i40e_hash_global_config_check(adapter, g_cfg);
9291         if (ret < 0)
9292                 return ret;
9293
9294         /*
9295          * As i40e supports less than 64 flow types, only first 64 bits need to
9296          * be configured.
9297          */
9298         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
9299                 if (mask0 & (1UL << i)) {
9300                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
9301                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
9302
9303                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
9304                              j < I40E_FILTER_PCTYPE_MAX; j++) {
9305                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
9306                                         i40e_write_global_rx_ctl(hw,
9307                                                           I40E_GLQF_HSYM(j),
9308                                                           reg);
9309                         }
9310                 }
9311         }
9312
9313         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
9314         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
9315                 /* Toeplitz */
9316                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
9317                         PMD_DRV_LOG(DEBUG,
9318                                 "Hash function already set to Toeplitz");
9319                         goto out;
9320                 }
9321                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
9322         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
9323                 /* Simple XOR */
9324                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
9325                         PMD_DRV_LOG(DEBUG,
9326                                 "Hash function already set to Simple XOR");
9327                         goto out;
9328                 }
9329                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
9330         } else
9331                 /* Use the default, and keep it as it is */
9332                 goto out;
9333
9334         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
9335
9336 out:
9337         I40E_WRITE_FLUSH(hw);
9338
9339         return 0;
9340 }
9341
9342 /**
9343  * Valid input sets for hash and flow director filters per PCTYPE
9344  */
9345 static uint64_t
9346 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
9347                 enum rte_filter_type filter)
9348 {
9349         uint64_t valid;
9350
9351         static const uint64_t valid_hash_inset_table[] = {
9352                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9353                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9354                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9355                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
9356                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
9357                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9358                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9359                         I40E_INSET_FLEX_PAYLOAD,
9360                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9361                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9362                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9363                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9364                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9365                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9366                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9367                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9368                         I40E_INSET_FLEX_PAYLOAD,
9369                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9370                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9371                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9372                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9373                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9374                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9375                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9376                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9377                         I40E_INSET_FLEX_PAYLOAD,
9378                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9379                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9380                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9381                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9382                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9383                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9384                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9385                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9386                         I40E_INSET_FLEX_PAYLOAD,
9387                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9388                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9389                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9390                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9391                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9392                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9393                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9394                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9395                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9396                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9397                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9398                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9399                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9400                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9401                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9402                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9403                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9404                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9405                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9406                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9407                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9408                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9409                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9410                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9411                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9412                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9413                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9414                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9415                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9416                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9417                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9418                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9419                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9420                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9421                         I40E_INSET_FLEX_PAYLOAD,
9422                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9423                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9424                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9425                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9426                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9427                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9428                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9429                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9430                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9431                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9432                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9433                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9434                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9435                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9436                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9437                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9438                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9439                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9440                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9441                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9442                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9443                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9444                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9445                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9446                         I40E_INSET_FLEX_PAYLOAD,
9447                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9448                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9449                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9450                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9451                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9452                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9453                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9454                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9455                         I40E_INSET_FLEX_PAYLOAD,
9456                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9457                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9458                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9459                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9460                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9461                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9462                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9463                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9464                         I40E_INSET_FLEX_PAYLOAD,
9465                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9466                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9467                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9468                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9469                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9470                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9471                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9472                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9473                         I40E_INSET_FLEX_PAYLOAD,
9474                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9475                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9476                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9477                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9478                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9479                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9480                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9481                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9482                         I40E_INSET_FLEX_PAYLOAD,
9483                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9484                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9485                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9486                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9487                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9488                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9489                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9490                         I40E_INSET_FLEX_PAYLOAD,
9491                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9492                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9493                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9494                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9495                         I40E_INSET_FLEX_PAYLOAD,
9496         };
9497
9498         /**
9499          * Flow director supports only fields defined in
9500          * union rte_eth_fdir_flow.
9501          */
9502         static const uint64_t valid_fdir_inset_table[] = {
9503                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9504                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9505                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9506                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9507                 I40E_INSET_IPV4_TTL,
9508                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9509                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9510                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9511                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9512                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9513                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9514                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9515                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9516                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9517                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9518                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9519                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9520                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9521                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9522                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9523                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9524                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9525                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9526                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9527                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9528                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9529                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9530                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9531                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9532                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9533                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9534                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9535                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9536                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9537                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9538                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9539                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9540                 I40E_INSET_SCTP_VT,
9541                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9542                 I40E_INSET_DMAC | I40E_INSET_SMAC |
9543                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9544                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9545                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9546                 I40E_INSET_IPV4_TTL,
9547                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9548                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9549                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9550                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9551                 I40E_INSET_IPV6_HOP_LIMIT,
9552                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9553                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9554                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9555                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9556                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9557                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9558                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9559                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9560                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9561                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9562                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9563                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9564                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9565                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9566                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9567                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9568                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9569                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9570                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9571                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9572                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9573                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9574                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9575                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9576                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9577                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9578                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9579                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9580                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9581                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9582                 I40E_INSET_SCTP_VT,
9583                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9584                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9585                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9586                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9587                 I40E_INSET_IPV6_HOP_LIMIT,
9588                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9589                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9590                 I40E_INSET_LAST_ETHER_TYPE,
9591         };
9592
9593         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9594                 return 0;
9595         if (filter == RTE_ETH_FILTER_HASH)
9596                 valid = valid_hash_inset_table[pctype];
9597         else
9598                 valid = valid_fdir_inset_table[pctype];
9599
9600         return valid;
9601 }
9602
9603 /**
9604  * Validate if the input set is allowed for a specific PCTYPE
9605  */
9606 int
9607 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9608                 enum rte_filter_type filter, uint64_t inset)
9609 {
9610         uint64_t valid;
9611
9612         valid = i40e_get_valid_input_set(pctype, filter);
9613         if (inset & (~valid))
9614                 return -EINVAL;
9615
9616         return 0;
9617 }
9618
9619 /* default input set fields combination per pctype */
9620 uint64_t
9621 i40e_get_default_input_set(uint16_t pctype)
9622 {
9623         static const uint64_t default_inset_table[] = {
9624                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9625                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9626                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9627                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9628                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9629                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9630                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9631                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9632                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9633                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9634                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9635                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9636                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9637                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9638                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9639                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9640                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9641                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9642                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9643                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9644                         I40E_INSET_SCTP_VT,
9645                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9646                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9647                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9648                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9649                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9650                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9651                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9652                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9653                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9654                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9655                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9656                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9657                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9658                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9659                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9660                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9661                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9662                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9663                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9664                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9665                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9666                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9667                         I40E_INSET_SCTP_VT,
9668                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9669                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9670                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9671                         I40E_INSET_LAST_ETHER_TYPE,
9672         };
9673
9674         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9675                 return 0;
9676
9677         return default_inset_table[pctype];
9678 }
9679
9680 /**
9681  * Parse the input set from index to logical bit masks
9682  */
9683 static int
9684 i40e_parse_input_set(uint64_t *inset,
9685                      enum i40e_filter_pctype pctype,
9686                      enum rte_eth_input_set_field *field,
9687                      uint16_t size)
9688 {
9689         uint16_t i, j;
9690         int ret = -EINVAL;
9691
9692         static const struct {
9693                 enum rte_eth_input_set_field field;
9694                 uint64_t inset;
9695         } inset_convert_table[] = {
9696                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9697                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9698                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9699                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9700                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9701                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9702                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9703                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9704                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9705                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9706                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9707                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9708                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9709                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9710                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9711                         I40E_INSET_IPV6_NEXT_HDR},
9712                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9713                         I40E_INSET_IPV6_HOP_LIMIT},
9714                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9715                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9716                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9717                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9718                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9719                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9720                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9721                         I40E_INSET_SCTP_VT},
9722                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9723                         I40E_INSET_TUNNEL_DMAC},
9724                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9725                         I40E_INSET_VLAN_TUNNEL},
9726                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9727                         I40E_INSET_TUNNEL_ID},
9728                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9729                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9730                         I40E_INSET_FLEX_PAYLOAD_W1},
9731                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9732                         I40E_INSET_FLEX_PAYLOAD_W2},
9733                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9734                         I40E_INSET_FLEX_PAYLOAD_W3},
9735                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9736                         I40E_INSET_FLEX_PAYLOAD_W4},
9737                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9738                         I40E_INSET_FLEX_PAYLOAD_W5},
9739                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9740                         I40E_INSET_FLEX_PAYLOAD_W6},
9741                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9742                         I40E_INSET_FLEX_PAYLOAD_W7},
9743                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9744                         I40E_INSET_FLEX_PAYLOAD_W8},
9745         };
9746
9747         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9748                 return ret;
9749
9750         /* Only one item allowed for default or all */
9751         if (size == 1) {
9752                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9753                         *inset = i40e_get_default_input_set(pctype);
9754                         return 0;
9755                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9756                         *inset = I40E_INSET_NONE;
9757                         return 0;
9758                 }
9759         }
9760
9761         for (i = 0, *inset = 0; i < size; i++) {
9762                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9763                         if (field[i] == inset_convert_table[j].field) {
9764                                 *inset |= inset_convert_table[j].inset;
9765                                 break;
9766                         }
9767                 }
9768
9769                 /* It contains unsupported input set, return immediately */
9770                 if (j == RTE_DIM(inset_convert_table))
9771                         return ret;
9772         }
9773
9774         return 0;
9775 }
9776
9777 /**
9778  * Translate the input set from bit masks to register aware bit masks
9779  * and vice versa
9780  */
9781 uint64_t
9782 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9783 {
9784         uint64_t val = 0;
9785         uint16_t i;
9786
9787         struct inset_map {
9788                 uint64_t inset;
9789                 uint64_t inset_reg;
9790         };
9791
9792         static const struct inset_map inset_map_common[] = {
9793                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9794                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9795                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9796                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9797                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9798                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9799                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9800                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9801                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9802                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9803                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9804                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9805                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9806                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9807                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9808                 {I40E_INSET_TUNNEL_DMAC,
9809                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9810                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9811                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9812                 {I40E_INSET_TUNNEL_SRC_PORT,
9813                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9814                 {I40E_INSET_TUNNEL_DST_PORT,
9815                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9816                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9817                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9818                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9819                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9820                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9821                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9822                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9823                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9824                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9825         };
9826
9827     /* some different registers map in x722*/
9828         static const struct inset_map inset_map_diff_x722[] = {
9829                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9830                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9831                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9832                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9833         };
9834
9835         static const struct inset_map inset_map_diff_not_x722[] = {
9836                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9837                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9838                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9839                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9840         };
9841
9842         if (input == 0)
9843                 return val;
9844
9845         /* Translate input set to register aware inset */
9846         if (type == I40E_MAC_X722) {
9847                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9848                         if (input & inset_map_diff_x722[i].inset)
9849                                 val |= inset_map_diff_x722[i].inset_reg;
9850                 }
9851         } else {
9852                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9853                         if (input & inset_map_diff_not_x722[i].inset)
9854                                 val |= inset_map_diff_not_x722[i].inset_reg;
9855                 }
9856         }
9857
9858         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9859                 if (input & inset_map_common[i].inset)
9860                         val |= inset_map_common[i].inset_reg;
9861         }
9862
9863         return val;
9864 }
9865
9866 int
9867 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9868 {
9869         uint8_t i, idx = 0;
9870         uint64_t inset_need_mask = inset;
9871
9872         static const struct {
9873                 uint64_t inset;
9874                 uint32_t mask;
9875         } inset_mask_map[] = {
9876                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9877                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9878                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9879                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9880                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9881                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9882                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9883                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9884         };
9885
9886         if (!inset || !mask || !nb_elem)
9887                 return 0;
9888
9889         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9890                 /* Clear the inset bit, if no MASK is required,
9891                  * for example proto + ttl
9892                  */
9893                 if ((inset & inset_mask_map[i].inset) ==
9894                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9895                         inset_need_mask &= ~inset_mask_map[i].inset;
9896                 if (!inset_need_mask)
9897                         return 0;
9898         }
9899         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9900                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9901                     inset_mask_map[i].inset) {
9902                         if (idx >= nb_elem) {
9903                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9904                                 return -EINVAL;
9905                         }
9906                         mask[idx] = inset_mask_map[i].mask;
9907                         idx++;
9908                 }
9909         }
9910
9911         return idx;
9912 }
9913
9914 void
9915 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9916 {
9917         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9918
9919         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9920         if (reg != val)
9921                 i40e_write_rx_ctl(hw, addr, val);
9922         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9923                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9924 }
9925
9926 void
9927 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9928 {
9929         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9930         struct rte_eth_dev *dev;
9931
9932         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9933         if (reg != val) {
9934                 i40e_write_rx_ctl(hw, addr, val);
9935                 PMD_DRV_LOG(WARNING,
9936                             "i40e device %s changed global register [0x%08x]."
9937                             " original: 0x%08x, new: 0x%08x",
9938                             dev->device->name, addr, reg,
9939                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9940         }
9941 }
9942
9943 static void
9944 i40e_filter_input_set_init(struct i40e_pf *pf)
9945 {
9946         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9947         enum i40e_filter_pctype pctype;
9948         uint64_t input_set, inset_reg;
9949         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9950         int num, i;
9951         uint16_t flow_type;
9952
9953         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9954              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9955                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9956
9957                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9958                         continue;
9959
9960                 input_set = i40e_get_default_input_set(pctype);
9961
9962                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9963                                                    I40E_INSET_MASK_NUM_REG);
9964                 if (num < 0)
9965                         return;
9966                 if (pf->support_multi_driver && num > 0) {
9967                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9968                         return;
9969                 }
9970                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9971                                         input_set);
9972
9973                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9974                                       (uint32_t)(inset_reg & UINT32_MAX));
9975                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9976                                      (uint32_t)((inset_reg >>
9977                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9978                 if (!pf->support_multi_driver) {
9979                         i40e_check_write_global_reg(hw,
9980                                             I40E_GLQF_HASH_INSET(0, pctype),
9981                                             (uint32_t)(inset_reg & UINT32_MAX));
9982                         i40e_check_write_global_reg(hw,
9983                                              I40E_GLQF_HASH_INSET(1, pctype),
9984                                              (uint32_t)((inset_reg >>
9985                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9986
9987                         for (i = 0; i < num; i++) {
9988                                 i40e_check_write_global_reg(hw,
9989                                                     I40E_GLQF_FD_MSK(i, pctype),
9990                                                     mask_reg[i]);
9991                                 i40e_check_write_global_reg(hw,
9992                                                   I40E_GLQF_HASH_MSK(i, pctype),
9993                                                   mask_reg[i]);
9994                         }
9995                         /*clear unused mask registers of the pctype */
9996                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9997                                 i40e_check_write_global_reg(hw,
9998                                                     I40E_GLQF_FD_MSK(i, pctype),
9999                                                     0);
10000                                 i40e_check_write_global_reg(hw,
10001                                                   I40E_GLQF_HASH_MSK(i, pctype),
10002                                                   0);
10003                         }
10004                 } else {
10005                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
10006                 }
10007                 I40E_WRITE_FLUSH(hw);
10008
10009                 /* store the default input set */
10010                 if (!pf->support_multi_driver)
10011                         pf->hash_input_set[pctype] = input_set;
10012                 pf->fdir.input_set[pctype] = input_set;
10013         }
10014 }
10015
10016 int
10017 i40e_hash_filter_inset_select(struct i40e_hw *hw,
10018                          struct rte_eth_input_set_conf *conf)
10019 {
10020         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
10021         enum i40e_filter_pctype pctype;
10022         uint64_t input_set, inset_reg = 0;
10023         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10024         int ret, i, num;
10025
10026         if (!conf) {
10027                 PMD_DRV_LOG(ERR, "Invalid pointer");
10028                 return -EFAULT;
10029         }
10030         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10031             conf->op != RTE_ETH_INPUT_SET_ADD) {
10032                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10033                 return -EINVAL;
10034         }
10035
10036         if (pf->support_multi_driver) {
10037                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
10038                 return -ENOTSUP;
10039         }
10040
10041         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10042         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10043                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10044                 return -EINVAL;
10045         }
10046
10047         if (hw->mac.type == I40E_MAC_X722) {
10048                 /* get translated pctype value in fd pctype register */
10049                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
10050                         I40E_GLQF_FD_PCTYPES((int)pctype));
10051         }
10052
10053         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10054                                    conf->inset_size);
10055         if (ret) {
10056                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10057                 return -EINVAL;
10058         }
10059
10060         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
10061                 /* get inset value in register */
10062                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
10063                 inset_reg <<= I40E_32_BIT_WIDTH;
10064                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
10065                 input_set |= pf->hash_input_set[pctype];
10066         }
10067         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10068                                            I40E_INSET_MASK_NUM_REG);
10069         if (num < 0)
10070                 return -EINVAL;
10071
10072         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10073
10074         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
10075                                     (uint32_t)(inset_reg & UINT32_MAX));
10076         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
10077                                     (uint32_t)((inset_reg >>
10078                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
10079
10080         for (i = 0; i < num; i++)
10081                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10082                                             mask_reg[i]);
10083         /*clear unused mask registers of the pctype */
10084         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10085                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
10086                                             0);
10087         I40E_WRITE_FLUSH(hw);
10088
10089         pf->hash_input_set[pctype] = input_set;
10090         return 0;
10091 }
10092
10093 int
10094 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
10095                          struct rte_eth_input_set_conf *conf)
10096 {
10097         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10098         enum i40e_filter_pctype pctype;
10099         uint64_t input_set, inset_reg = 0;
10100         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
10101         int ret, i, num;
10102
10103         if (!hw || !conf) {
10104                 PMD_DRV_LOG(ERR, "Invalid pointer");
10105                 return -EFAULT;
10106         }
10107         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
10108             conf->op != RTE_ETH_INPUT_SET_ADD) {
10109                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
10110                 return -EINVAL;
10111         }
10112
10113         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
10114
10115         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
10116                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
10117                 return -EINVAL;
10118         }
10119
10120         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
10121                                    conf->inset_size);
10122         if (ret) {
10123                 PMD_DRV_LOG(ERR, "Failed to parse input set");
10124                 return -EINVAL;
10125         }
10126
10127         /* get inset value in register */
10128         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
10129         inset_reg <<= I40E_32_BIT_WIDTH;
10130         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
10131
10132         /* Can not change the inset reg for flex payload for fdir,
10133          * it is done by writing I40E_PRTQF_FD_FLXINSET
10134          * in i40e_set_flex_mask_on_pctype.
10135          */
10136         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
10137                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
10138         else
10139                 input_set |= pf->fdir.input_set[pctype];
10140         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
10141                                            I40E_INSET_MASK_NUM_REG);
10142         if (num < 0)
10143                 return -EINVAL;
10144         if (pf->support_multi_driver && num > 0) {
10145                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10146                 return -ENOTSUP;
10147         }
10148
10149         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
10150
10151         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
10152                               (uint32_t)(inset_reg & UINT32_MAX));
10153         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
10154                              (uint32_t)((inset_reg >>
10155                              I40E_32_BIT_WIDTH) & UINT32_MAX));
10156
10157         if (!pf->support_multi_driver) {
10158                 for (i = 0; i < num; i++)
10159                         i40e_check_write_global_reg(hw,
10160                                                     I40E_GLQF_FD_MSK(i, pctype),
10161                                                     mask_reg[i]);
10162                 /*clear unused mask registers of the pctype */
10163                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
10164                         i40e_check_write_global_reg(hw,
10165                                                     I40E_GLQF_FD_MSK(i, pctype),
10166                                                     0);
10167         } else {
10168                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
10169         }
10170         I40E_WRITE_FLUSH(hw);
10171
10172         pf->fdir.input_set[pctype] = input_set;
10173         return 0;
10174 }
10175
10176 static int
10177 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10178 {
10179         int ret = 0;
10180
10181         if (!hw || !info) {
10182                 PMD_DRV_LOG(ERR, "Invalid pointer");
10183                 return -EFAULT;
10184         }
10185
10186         switch (info->info_type) {
10187         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10188                 i40e_get_symmetric_hash_enable_per_port(hw,
10189                                         &(info->info.enable));
10190                 break;
10191         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10192                 ret = i40e_get_hash_filter_global_config(hw,
10193                                 &(info->info.global_conf));
10194                 break;
10195         default:
10196                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10197                                                         info->info_type);
10198                 ret = -EINVAL;
10199                 break;
10200         }
10201
10202         return ret;
10203 }
10204
10205 static int
10206 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
10207 {
10208         int ret = 0;
10209
10210         if (!hw || !info) {
10211                 PMD_DRV_LOG(ERR, "Invalid pointer");
10212                 return -EFAULT;
10213         }
10214
10215         switch (info->info_type) {
10216         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
10217                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
10218                 break;
10219         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
10220                 ret = i40e_set_hash_filter_global_config(hw,
10221                                 &(info->info.global_conf));
10222                 break;
10223         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
10224                 ret = i40e_hash_filter_inset_select(hw,
10225                                                &(info->info.input_set_conf));
10226                 break;
10227
10228         default:
10229                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
10230                                                         info->info_type);
10231                 ret = -EINVAL;
10232                 break;
10233         }
10234
10235         return ret;
10236 }
10237
10238 /* Operations for hash function */
10239 static int
10240 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
10241                       enum rte_filter_op filter_op,
10242                       void *arg)
10243 {
10244         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10245         int ret = 0;
10246
10247         switch (filter_op) {
10248         case RTE_ETH_FILTER_NOP:
10249                 break;
10250         case RTE_ETH_FILTER_GET:
10251                 ret = i40e_hash_filter_get(hw,
10252                         (struct rte_eth_hash_filter_info *)arg);
10253                 break;
10254         case RTE_ETH_FILTER_SET:
10255                 ret = i40e_hash_filter_set(hw,
10256                         (struct rte_eth_hash_filter_info *)arg);
10257                 break;
10258         default:
10259                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
10260                                                                 filter_op);
10261                 ret = -ENOTSUP;
10262                 break;
10263         }
10264
10265         return ret;
10266 }
10267
10268 /* Convert ethertype filter structure */
10269 static int
10270 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
10271                               struct i40e_ethertype_filter *filter)
10272 {
10273         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
10274                 RTE_ETHER_ADDR_LEN);
10275         filter->input.ether_type = input->ether_type;
10276         filter->flags = input->flags;
10277         filter->queue = input->queue;
10278
10279         return 0;
10280 }
10281
10282 /* Check if there exists the ehtertype filter */
10283 struct i40e_ethertype_filter *
10284 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
10285                                 const struct i40e_ethertype_filter_input *input)
10286 {
10287         int ret;
10288
10289         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
10290         if (ret < 0)
10291                 return NULL;
10292
10293         return ethertype_rule->hash_map[ret];
10294 }
10295
10296 /* Add ethertype filter in SW list */
10297 static int
10298 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
10299                                 struct i40e_ethertype_filter *filter)
10300 {
10301         struct i40e_ethertype_rule *rule = &pf->ethertype;
10302         int ret;
10303
10304         ret = rte_hash_add_key(rule->hash_table, &filter->input);
10305         if (ret < 0) {
10306                 PMD_DRV_LOG(ERR,
10307                             "Failed to insert ethertype filter"
10308                             " to hash table %d!",
10309                             ret);
10310                 return ret;
10311         }
10312         rule->hash_map[ret] = filter;
10313
10314         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
10315
10316         return 0;
10317 }
10318
10319 /* Delete ethertype filter in SW list */
10320 int
10321 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
10322                              struct i40e_ethertype_filter_input *input)
10323 {
10324         struct i40e_ethertype_rule *rule = &pf->ethertype;
10325         struct i40e_ethertype_filter *filter;
10326         int ret;
10327
10328         ret = rte_hash_del_key(rule->hash_table, input);
10329         if (ret < 0) {
10330                 PMD_DRV_LOG(ERR,
10331                             "Failed to delete ethertype filter"
10332                             " to hash table %d!",
10333                             ret);
10334                 return ret;
10335         }
10336         filter = rule->hash_map[ret];
10337         rule->hash_map[ret] = NULL;
10338
10339         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
10340         rte_free(filter);
10341
10342         return 0;
10343 }
10344
10345 /*
10346  * Configure ethertype filter, which can director packet by filtering
10347  * with mac address and ether_type or only ether_type
10348  */
10349 int
10350 i40e_ethertype_filter_set(struct i40e_pf *pf,
10351                         struct rte_eth_ethertype_filter *filter,
10352                         bool add)
10353 {
10354         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
10355         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
10356         struct i40e_ethertype_filter *ethertype_filter, *node;
10357         struct i40e_ethertype_filter check_filter;
10358         struct i40e_control_filter_stats stats;
10359         uint16_t flags = 0;
10360         int ret;
10361
10362         if (filter->queue >= pf->dev_data->nb_rx_queues) {
10363                 PMD_DRV_LOG(ERR, "Invalid queue ID");
10364                 return -EINVAL;
10365         }
10366         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
10367                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10368                 PMD_DRV_LOG(ERR,
10369                         "unsupported ether_type(0x%04x) in control packet filter.",
10370                         filter->ether_type);
10371                 return -EINVAL;
10372         }
10373         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10374                 PMD_DRV_LOG(WARNING,
10375                         "filter vlan ether_type in first tag is not supported.");
10376
10377         /* Check if there is the filter in SW list */
10378         memset(&check_filter, 0, sizeof(check_filter));
10379         i40e_ethertype_filter_convert(filter, &check_filter);
10380         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10381                                                &check_filter.input);
10382         if (add && node) {
10383                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10384                 return -EINVAL;
10385         }
10386
10387         if (!add && !node) {
10388                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10389                 return -EINVAL;
10390         }
10391
10392         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10393                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10394         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10395                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10396         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10397
10398         memset(&stats, 0, sizeof(stats));
10399         ret = i40e_aq_add_rem_control_packet_filter(hw,
10400                         filter->mac_addr.addr_bytes,
10401                         filter->ether_type, flags,
10402                         pf->main_vsi->seid,
10403                         filter->queue, add, &stats, NULL);
10404
10405         PMD_DRV_LOG(INFO,
10406                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10407                 ret, stats.mac_etype_used, stats.etype_used,
10408                 stats.mac_etype_free, stats.etype_free);
10409         if (ret < 0)
10410                 return -ENOSYS;
10411
10412         /* Add or delete a filter in SW list */
10413         if (add) {
10414                 ethertype_filter = rte_zmalloc("ethertype_filter",
10415                                        sizeof(*ethertype_filter), 0);
10416                 if (ethertype_filter == NULL) {
10417                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10418                         return -ENOMEM;
10419                 }
10420
10421                 rte_memcpy(ethertype_filter, &check_filter,
10422                            sizeof(check_filter));
10423                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10424                 if (ret < 0)
10425                         rte_free(ethertype_filter);
10426         } else {
10427                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10428         }
10429
10430         return ret;
10431 }
10432
10433 /*
10434  * Handle operations for ethertype filter.
10435  */
10436 static int
10437 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10438                                 enum rte_filter_op filter_op,
10439                                 void *arg)
10440 {
10441         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10442         int ret = 0;
10443
10444         if (filter_op == RTE_ETH_FILTER_NOP)
10445                 return ret;
10446
10447         if (arg == NULL) {
10448                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10449                             filter_op);
10450                 return -EINVAL;
10451         }
10452
10453         switch (filter_op) {
10454         case RTE_ETH_FILTER_ADD:
10455                 ret = i40e_ethertype_filter_set(pf,
10456                         (struct rte_eth_ethertype_filter *)arg,
10457                         TRUE);
10458                 break;
10459         case RTE_ETH_FILTER_DELETE:
10460                 ret = i40e_ethertype_filter_set(pf,
10461                         (struct rte_eth_ethertype_filter *)arg,
10462                         FALSE);
10463                 break;
10464         default:
10465                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10466                 ret = -ENOSYS;
10467                 break;
10468         }
10469         return ret;
10470 }
10471
10472 static int
10473 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10474                      enum rte_filter_type filter_type,
10475                      enum rte_filter_op filter_op,
10476                      void *arg)
10477 {
10478         int ret = 0;
10479
10480         if (dev == NULL)
10481                 return -EINVAL;
10482
10483         switch (filter_type) {
10484         case RTE_ETH_FILTER_NONE:
10485                 /* For global configuration */
10486                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10487                 break;
10488         case RTE_ETH_FILTER_HASH:
10489                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10490                 break;
10491         case RTE_ETH_FILTER_MACVLAN:
10492                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10493                 break;
10494         case RTE_ETH_FILTER_ETHERTYPE:
10495                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10496                 break;
10497         case RTE_ETH_FILTER_TUNNEL:
10498                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10499                 break;
10500         case RTE_ETH_FILTER_FDIR:
10501                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10502                 break;
10503         case RTE_ETH_FILTER_GENERIC:
10504                 if (filter_op != RTE_ETH_FILTER_GET)
10505                         return -EINVAL;
10506                 *(const void **)arg = &i40e_flow_ops;
10507                 break;
10508         default:
10509                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10510                                                         filter_type);
10511                 ret = -EINVAL;
10512                 break;
10513         }
10514
10515         return ret;
10516 }
10517
10518 /*
10519  * Check and enable Extended Tag.
10520  * Enabling Extended Tag is important for 40G performance.
10521  */
10522 static void
10523 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10524 {
10525         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10526         uint32_t buf = 0;
10527         int ret;
10528
10529         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10530                                       PCI_DEV_CAP_REG);
10531         if (ret < 0) {
10532                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10533                             PCI_DEV_CAP_REG);
10534                 return;
10535         }
10536         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10537                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10538                 return;
10539         }
10540
10541         buf = 0;
10542         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10543                                       PCI_DEV_CTRL_REG);
10544         if (ret < 0) {
10545                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10546                             PCI_DEV_CTRL_REG);
10547                 return;
10548         }
10549         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10550                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10551                 return;
10552         }
10553         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10554         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10555                                        PCI_DEV_CTRL_REG);
10556         if (ret < 0) {
10557                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10558                             PCI_DEV_CTRL_REG);
10559                 return;
10560         }
10561 }
10562
10563 /*
10564  * As some registers wouldn't be reset unless a global hardware reset,
10565  * hardware initialization is needed to put those registers into an
10566  * expected initial state.
10567  */
10568 static void
10569 i40e_hw_init(struct rte_eth_dev *dev)
10570 {
10571         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10572
10573         i40e_enable_extended_tag(dev);
10574
10575         /* clear the PF Queue Filter control register */
10576         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10577
10578         /* Disable symmetric hash per port */
10579         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10580 }
10581
10582 /*
10583  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10584  * however this function will return only one highest pctype index,
10585  * which is not quite correct. This is known problem of i40e driver
10586  * and needs to be fixed later.
10587  */
10588 enum i40e_filter_pctype
10589 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10590 {
10591         int i;
10592         uint64_t pctype_mask;
10593
10594         if (flow_type < I40E_FLOW_TYPE_MAX) {
10595                 pctype_mask = adapter->pctypes_tbl[flow_type];
10596                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10597                         if (pctype_mask & (1ULL << i))
10598                                 return (enum i40e_filter_pctype)i;
10599                 }
10600         }
10601         return I40E_FILTER_PCTYPE_INVALID;
10602 }
10603
10604 uint16_t
10605 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10606                         enum i40e_filter_pctype pctype)
10607 {
10608         uint16_t flowtype;
10609         uint64_t pctype_mask = 1ULL << pctype;
10610
10611         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10612              flowtype++) {
10613                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10614                         return flowtype;
10615         }
10616
10617         return RTE_ETH_FLOW_UNKNOWN;
10618 }
10619
10620 /*
10621  * On X710, performance number is far from the expectation on recent firmware
10622  * versions; on XL710, performance number is also far from the expectation on
10623  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10624  * mode is enabled and port MAC address is equal to the packet destination MAC
10625  * address. The fix for this issue may not be integrated in the following
10626  * firmware version. So the workaround in software driver is needed. It needs
10627  * to modify the initial values of 3 internal only registers for both X710 and
10628  * XL710. Note that the values for X710 or XL710 could be different, and the
10629  * workaround can be removed when it is fixed in firmware in the future.
10630  */
10631
10632 /* For both X710 and XL710 */
10633 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10634 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10635 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10636
10637 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10638 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10639
10640 /* For X722 */
10641 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10642 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10643
10644 /* For X710 */
10645 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10646 /* For XL710 */
10647 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10648 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10649
10650 /*
10651  * GL_SWR_PM_UP_THR:
10652  * The value is not impacted from the link speed, its value is set according
10653  * to the total number of ports for a better pipe-monitor configuration.
10654  */
10655 static bool
10656 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10657 {
10658 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10659                 .device_id = (dev),   \
10660                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10661
10662 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10663                 .device_id = (dev),   \
10664                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10665
10666         static const struct {
10667                 uint16_t device_id;
10668                 uint32_t val;
10669         } swr_pm_table[] = {
10670                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10671                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10672                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10673                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10674                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_X722) },
10675
10676                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10677                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10678                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10679                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10680                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10681                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10682                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10683         };
10684         uint32_t i;
10685
10686         if (value == NULL) {
10687                 PMD_DRV_LOG(ERR, "value is NULL");
10688                 return false;
10689         }
10690
10691         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10692                 if (hw->device_id == swr_pm_table[i].device_id) {
10693                         *value = swr_pm_table[i].val;
10694
10695                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10696                                     "value - 0x%08x",
10697                                     hw->device_id, *value);
10698                         return true;
10699                 }
10700         }
10701
10702         return false;
10703 }
10704
10705 static int
10706 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10707 {
10708         enum i40e_status_code status;
10709         struct i40e_aq_get_phy_abilities_resp phy_ab;
10710         int ret = -ENOTSUP;
10711         int retries = 0;
10712
10713         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10714                                               NULL);
10715
10716         while (status) {
10717                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10718                         status);
10719                 retries++;
10720                 rte_delay_us(100000);
10721                 if  (retries < 5)
10722                         status = i40e_aq_get_phy_capabilities(hw, false,
10723                                         true, &phy_ab, NULL);
10724                 else
10725                         return ret;
10726         }
10727         return 0;
10728 }
10729
10730 static void
10731 i40e_configure_registers(struct i40e_hw *hw)
10732 {
10733         static struct {
10734                 uint32_t addr;
10735                 uint64_t val;
10736         } reg_table[] = {
10737                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10738                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10739                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10740         };
10741         uint64_t reg;
10742         uint32_t i;
10743         int ret;
10744
10745         for (i = 0; i < RTE_DIM(reg_table); i++) {
10746                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10747                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10748                                 reg_table[i].val =
10749                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10750                         else /* For X710/XL710/XXV710 */
10751                                 if (hw->aq.fw_maj_ver < 6)
10752                                         reg_table[i].val =
10753                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10754                                 else
10755                                         reg_table[i].val =
10756                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10757                 }
10758
10759                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10760                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10761                                 reg_table[i].val =
10762                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10763                         else /* For X710/XL710/XXV710 */
10764                                 reg_table[i].val =
10765                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10766                 }
10767
10768                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10769                         uint32_t cfg_val;
10770
10771                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10772                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10773                                             "GL_SWR_PM_UP_THR value fixup",
10774                                             hw->device_id);
10775                                 continue;
10776                         }
10777
10778                         reg_table[i].val = cfg_val;
10779                 }
10780
10781                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10782                                                         &reg, NULL);
10783                 if (ret < 0) {
10784                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10785                                                         reg_table[i].addr);
10786                         break;
10787                 }
10788                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10789                                                 reg_table[i].addr, reg);
10790                 if (reg == reg_table[i].val)
10791                         continue;
10792
10793                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10794                                                 reg_table[i].val, NULL);
10795                 if (ret < 0) {
10796                         PMD_DRV_LOG(ERR,
10797                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10798                                 reg_table[i].val, reg_table[i].addr);
10799                         break;
10800                 }
10801                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10802                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10803         }
10804 }
10805
10806 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10807 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10808 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10809 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10810 static int
10811 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10812 {
10813         uint32_t reg;
10814         int ret;
10815
10816         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10817                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10818                 return -EINVAL;
10819         }
10820
10821         /* Configure for double VLAN RX stripping */
10822         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10823         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10824                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10825                 ret = i40e_aq_debug_write_register(hw,
10826                                                    I40E_VSI_TSR(vsi->vsi_id),
10827                                                    reg, NULL);
10828                 if (ret < 0) {
10829                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10830                                     vsi->vsi_id);
10831                         return I40E_ERR_CONFIG;
10832                 }
10833         }
10834
10835         /* Configure for double VLAN TX insertion */
10836         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10837         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10838                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10839                 ret = i40e_aq_debug_write_register(hw,
10840                                                    I40E_VSI_L2TAGSTXVALID(
10841                                                    vsi->vsi_id), reg, NULL);
10842                 if (ret < 0) {
10843                         PMD_DRV_LOG(ERR,
10844                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10845                                 vsi->vsi_id);
10846                         return I40E_ERR_CONFIG;
10847                 }
10848         }
10849
10850         return 0;
10851 }
10852
10853 /**
10854  * i40e_aq_add_mirror_rule
10855  * @hw: pointer to the hardware structure
10856  * @seid: VEB seid to add mirror rule to
10857  * @dst_id: destination vsi seid
10858  * @entries: Buffer which contains the entities to be mirrored
10859  * @count: number of entities contained in the buffer
10860  * @rule_id:the rule_id of the rule to be added
10861  *
10862  * Add a mirror rule for a given veb.
10863  *
10864  **/
10865 static enum i40e_status_code
10866 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10867                         uint16_t seid, uint16_t dst_id,
10868                         uint16_t rule_type, uint16_t *entries,
10869                         uint16_t count, uint16_t *rule_id)
10870 {
10871         struct i40e_aq_desc desc;
10872         struct i40e_aqc_add_delete_mirror_rule cmd;
10873         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10874                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10875                 &desc.params.raw;
10876         uint16_t buff_len;
10877         enum i40e_status_code status;
10878
10879         i40e_fill_default_direct_cmd_desc(&desc,
10880                                           i40e_aqc_opc_add_mirror_rule);
10881         memset(&cmd, 0, sizeof(cmd));
10882
10883         buff_len = sizeof(uint16_t) * count;
10884         desc.datalen = rte_cpu_to_le_16(buff_len);
10885         if (buff_len > 0)
10886                 desc.flags |= rte_cpu_to_le_16(
10887                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10888         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10889                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10890         cmd.num_entries = rte_cpu_to_le_16(count);
10891         cmd.seid = rte_cpu_to_le_16(seid);
10892         cmd.destination = rte_cpu_to_le_16(dst_id);
10893
10894         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10895         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10896         PMD_DRV_LOG(INFO,
10897                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10898                 hw->aq.asq_last_status, resp->rule_id,
10899                 resp->mirror_rules_used, resp->mirror_rules_free);
10900         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10901
10902         return status;
10903 }
10904
10905 /**
10906  * i40e_aq_del_mirror_rule
10907  * @hw: pointer to the hardware structure
10908  * @seid: VEB seid to add mirror rule to
10909  * @entries: Buffer which contains the entities to be mirrored
10910  * @count: number of entities contained in the buffer
10911  * @rule_id:the rule_id of the rule to be delete
10912  *
10913  * Delete a mirror rule for a given veb.
10914  *
10915  **/
10916 static enum i40e_status_code
10917 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10918                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10919                 uint16_t count, uint16_t rule_id)
10920 {
10921         struct i40e_aq_desc desc;
10922         struct i40e_aqc_add_delete_mirror_rule cmd;
10923         uint16_t buff_len = 0;
10924         enum i40e_status_code status;
10925         void *buff = NULL;
10926
10927         i40e_fill_default_direct_cmd_desc(&desc,
10928                                           i40e_aqc_opc_delete_mirror_rule);
10929         memset(&cmd, 0, sizeof(cmd));
10930         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10931                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10932                                                           I40E_AQ_FLAG_RD));
10933                 cmd.num_entries = count;
10934                 buff_len = sizeof(uint16_t) * count;
10935                 desc.datalen = rte_cpu_to_le_16(buff_len);
10936                 buff = (void *)entries;
10937         } else
10938                 /* rule id is filled in destination field for deleting mirror rule */
10939                 cmd.destination = rte_cpu_to_le_16(rule_id);
10940
10941         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10942                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10943         cmd.seid = rte_cpu_to_le_16(seid);
10944
10945         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10946         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10947
10948         return status;
10949 }
10950
10951 /**
10952  * i40e_mirror_rule_set
10953  * @dev: pointer to the hardware structure
10954  * @mirror_conf: mirror rule info
10955  * @sw_id: mirror rule's sw_id
10956  * @on: enable/disable
10957  *
10958  * set a mirror rule.
10959  *
10960  **/
10961 static int
10962 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10963                         struct rte_eth_mirror_conf *mirror_conf,
10964                         uint8_t sw_id, uint8_t on)
10965 {
10966         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10967         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10968         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10969         struct i40e_mirror_rule *parent = NULL;
10970         uint16_t seid, dst_seid, rule_id;
10971         uint16_t i, j = 0;
10972         int ret;
10973
10974         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10975
10976         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10977                 PMD_DRV_LOG(ERR,
10978                         "mirror rule can not be configured without veb or vfs.");
10979                 return -ENOSYS;
10980         }
10981         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10982                 PMD_DRV_LOG(ERR, "mirror table is full.");
10983                 return -ENOSPC;
10984         }
10985         if (mirror_conf->dst_pool > pf->vf_num) {
10986                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10987                                  mirror_conf->dst_pool);
10988                 return -EINVAL;
10989         }
10990
10991         seid = pf->main_vsi->veb->seid;
10992
10993         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10994                 if (sw_id <= it->index) {
10995                         mirr_rule = it;
10996                         break;
10997                 }
10998                 parent = it;
10999         }
11000         if (mirr_rule && sw_id == mirr_rule->index) {
11001                 if (on) {
11002                         PMD_DRV_LOG(ERR, "mirror rule exists.");
11003                         return -EEXIST;
11004                 } else {
11005                         ret = i40e_aq_del_mirror_rule(hw, seid,
11006                                         mirr_rule->rule_type,
11007                                         mirr_rule->entries,
11008                                         mirr_rule->num_entries, mirr_rule->id);
11009                         if (ret < 0) {
11010                                 PMD_DRV_LOG(ERR,
11011                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
11012                                         ret, hw->aq.asq_last_status);
11013                                 return -ENOSYS;
11014                         }
11015                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11016                         rte_free(mirr_rule);
11017                         pf->nb_mirror_rule--;
11018                         return 0;
11019                 }
11020         } else if (!on) {
11021                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11022                 return -ENOENT;
11023         }
11024
11025         mirr_rule = rte_zmalloc("i40e_mirror_rule",
11026                                 sizeof(struct i40e_mirror_rule) , 0);
11027         if (!mirr_rule) {
11028                 PMD_DRV_LOG(ERR, "failed to allocate memory");
11029                 return I40E_ERR_NO_MEMORY;
11030         }
11031         switch (mirror_conf->rule_type) {
11032         case ETH_MIRROR_VLAN:
11033                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
11034                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
11035                                 mirr_rule->entries[j] =
11036                                         mirror_conf->vlan.vlan_id[i];
11037                                 j++;
11038                         }
11039                 }
11040                 if (j == 0) {
11041                         PMD_DRV_LOG(ERR, "vlan is not specified.");
11042                         rte_free(mirr_rule);
11043                         return -EINVAL;
11044                 }
11045                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
11046                 break;
11047         case ETH_MIRROR_VIRTUAL_POOL_UP:
11048         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
11049                 /* check if the specified pool bit is out of range */
11050                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
11051                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
11052                         rte_free(mirr_rule);
11053                         return -EINVAL;
11054                 }
11055                 for (i = 0, j = 0; i < pf->vf_num; i++) {
11056                         if (mirror_conf->pool_mask & (1ULL << i)) {
11057                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
11058                                 j++;
11059                         }
11060                 }
11061                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
11062                         /* add pf vsi to entries */
11063                         mirr_rule->entries[j] = pf->main_vsi_seid;
11064                         j++;
11065                 }
11066                 if (j == 0) {
11067                         PMD_DRV_LOG(ERR, "pool is not specified.");
11068                         rte_free(mirr_rule);
11069                         return -EINVAL;
11070                 }
11071                 /* egress and ingress in aq commands means from switch but not port */
11072                 mirr_rule->rule_type =
11073                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
11074                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
11075                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
11076                 break;
11077         case ETH_MIRROR_UPLINK_PORT:
11078                 /* egress and ingress in aq commands means from switch but not port*/
11079                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
11080                 break;
11081         case ETH_MIRROR_DOWNLINK_PORT:
11082                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
11083                 break;
11084         default:
11085                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
11086                         mirror_conf->rule_type);
11087                 rte_free(mirr_rule);
11088                 return -EINVAL;
11089         }
11090
11091         /* If the dst_pool is equal to vf_num, consider it as PF */
11092         if (mirror_conf->dst_pool == pf->vf_num)
11093                 dst_seid = pf->main_vsi_seid;
11094         else
11095                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
11096
11097         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
11098                                       mirr_rule->rule_type, mirr_rule->entries,
11099                                       j, &rule_id);
11100         if (ret < 0) {
11101                 PMD_DRV_LOG(ERR,
11102                         "failed to add mirror rule: ret = %d, aq_err = %d.",
11103                         ret, hw->aq.asq_last_status);
11104                 rte_free(mirr_rule);
11105                 return -ENOSYS;
11106         }
11107
11108         mirr_rule->index = sw_id;
11109         mirr_rule->num_entries = j;
11110         mirr_rule->id = rule_id;
11111         mirr_rule->dst_vsi_seid = dst_seid;
11112
11113         if (parent)
11114                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
11115         else
11116                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
11117
11118         pf->nb_mirror_rule++;
11119         return 0;
11120 }
11121
11122 /**
11123  * i40e_mirror_rule_reset
11124  * @dev: pointer to the device
11125  * @sw_id: mirror rule's sw_id
11126  *
11127  * reset a mirror rule.
11128  *
11129  **/
11130 static int
11131 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
11132 {
11133         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11134         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11135         struct i40e_mirror_rule *it, *mirr_rule = NULL;
11136         uint16_t seid;
11137         int ret;
11138
11139         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
11140
11141         seid = pf->main_vsi->veb->seid;
11142
11143         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
11144                 if (sw_id == it->index) {
11145                         mirr_rule = it;
11146                         break;
11147                 }
11148         }
11149         if (mirr_rule) {
11150                 ret = i40e_aq_del_mirror_rule(hw, seid,
11151                                 mirr_rule->rule_type,
11152                                 mirr_rule->entries,
11153                                 mirr_rule->num_entries, mirr_rule->id);
11154                 if (ret < 0) {
11155                         PMD_DRV_LOG(ERR,
11156                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
11157                                 ret, hw->aq.asq_last_status);
11158                         return -ENOSYS;
11159                 }
11160                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
11161                 rte_free(mirr_rule);
11162                 pf->nb_mirror_rule--;
11163         } else {
11164                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
11165                 return -ENOENT;
11166         }
11167         return 0;
11168 }
11169
11170 static uint64_t
11171 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
11172 {
11173         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11174         uint64_t systim_cycles;
11175
11176         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
11177         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
11178                         << 32;
11179
11180         return systim_cycles;
11181 }
11182
11183 static uint64_t
11184 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
11185 {
11186         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11187         uint64_t rx_tstamp;
11188
11189         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
11190         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
11191                         << 32;
11192
11193         return rx_tstamp;
11194 }
11195
11196 static uint64_t
11197 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
11198 {
11199         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11200         uint64_t tx_tstamp;
11201
11202         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
11203         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
11204                         << 32;
11205
11206         return tx_tstamp;
11207 }
11208
11209 static void
11210 i40e_start_timecounters(struct rte_eth_dev *dev)
11211 {
11212         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11213         struct i40e_adapter *adapter = dev->data->dev_private;
11214         struct rte_eth_link link;
11215         uint32_t tsync_inc_l;
11216         uint32_t tsync_inc_h;
11217
11218         /* Get current link speed. */
11219         i40e_dev_link_update(dev, 1);
11220         rte_eth_linkstatus_get(dev, &link);
11221
11222         switch (link.link_speed) {
11223         case ETH_SPEED_NUM_40G:
11224         case ETH_SPEED_NUM_25G:
11225                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
11226                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
11227                 break;
11228         case ETH_SPEED_NUM_10G:
11229                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
11230                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
11231                 break;
11232         case ETH_SPEED_NUM_1G:
11233                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
11234                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
11235                 break;
11236         default:
11237                 tsync_inc_l = 0x0;
11238                 tsync_inc_h = 0x0;
11239         }
11240
11241         /* Set the timesync increment value. */
11242         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
11243         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
11244
11245         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
11246         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11247         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
11248
11249         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11250         adapter->systime_tc.cc_shift = 0;
11251         adapter->systime_tc.nsec_mask = 0;
11252
11253         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11254         adapter->rx_tstamp_tc.cc_shift = 0;
11255         adapter->rx_tstamp_tc.nsec_mask = 0;
11256
11257         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
11258         adapter->tx_tstamp_tc.cc_shift = 0;
11259         adapter->tx_tstamp_tc.nsec_mask = 0;
11260 }
11261
11262 static int
11263 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
11264 {
11265         struct i40e_adapter *adapter = dev->data->dev_private;
11266
11267         adapter->systime_tc.nsec += delta;
11268         adapter->rx_tstamp_tc.nsec += delta;
11269         adapter->tx_tstamp_tc.nsec += delta;
11270
11271         return 0;
11272 }
11273
11274 static int
11275 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
11276 {
11277         uint64_t ns;
11278         struct i40e_adapter *adapter = dev->data->dev_private;
11279
11280         ns = rte_timespec_to_ns(ts);
11281
11282         /* Set the timecounters to a new value. */
11283         adapter->systime_tc.nsec = ns;
11284         adapter->rx_tstamp_tc.nsec = ns;
11285         adapter->tx_tstamp_tc.nsec = ns;
11286
11287         return 0;
11288 }
11289
11290 static int
11291 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
11292 {
11293         uint64_t ns, systime_cycles;
11294         struct i40e_adapter *adapter = dev->data->dev_private;
11295
11296         systime_cycles = i40e_read_systime_cyclecounter(dev);
11297         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
11298         *ts = rte_ns_to_timespec(ns);
11299
11300         return 0;
11301 }
11302
11303 static int
11304 i40e_timesync_enable(struct rte_eth_dev *dev)
11305 {
11306         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11307         uint32_t tsync_ctl_l;
11308         uint32_t tsync_ctl_h;
11309
11310         /* Stop the timesync system time. */
11311         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11312         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11313         /* Reset the timesync system time value. */
11314         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
11315         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
11316
11317         i40e_start_timecounters(dev);
11318
11319         /* Clear timesync registers. */
11320         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11321         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
11322         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
11323         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
11324         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
11325         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
11326
11327         /* Enable timestamping of PTP packets. */
11328         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11329         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
11330
11331         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11332         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
11333         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
11334
11335         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11336         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11337
11338         return 0;
11339 }
11340
11341 static int
11342 i40e_timesync_disable(struct rte_eth_dev *dev)
11343 {
11344         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11345         uint32_t tsync_ctl_l;
11346         uint32_t tsync_ctl_h;
11347
11348         /* Disable timestamping of transmitted PTP packets. */
11349         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
11350         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
11351
11352         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
11353         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
11354
11355         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
11356         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
11357
11358         /* Reset the timesync increment value. */
11359         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
11360         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
11361
11362         return 0;
11363 }
11364
11365 static int
11366 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
11367                                 struct timespec *timestamp, uint32_t flags)
11368 {
11369         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11370         struct i40e_adapter *adapter = dev->data->dev_private;
11371         uint32_t sync_status;
11372         uint32_t index = flags & 0x03;
11373         uint64_t rx_tstamp_cycles;
11374         uint64_t ns;
11375
11376         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11377         if ((sync_status & (1 << index)) == 0)
11378                 return -EINVAL;
11379
11380         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11381         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11382         *timestamp = rte_ns_to_timespec(ns);
11383
11384         return 0;
11385 }
11386
11387 static int
11388 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11389                                 struct timespec *timestamp)
11390 {
11391         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11392         struct i40e_adapter *adapter = dev->data->dev_private;
11393         uint32_t sync_status;
11394         uint64_t tx_tstamp_cycles;
11395         uint64_t ns;
11396
11397         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11398         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11399                 return -EINVAL;
11400
11401         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11402         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11403         *timestamp = rte_ns_to_timespec(ns);
11404
11405         return 0;
11406 }
11407
11408 /*
11409  * i40e_parse_dcb_configure - parse dcb configure from user
11410  * @dev: the device being configured
11411  * @dcb_cfg: pointer of the result of parse
11412  * @*tc_map: bit map of enabled traffic classes
11413  *
11414  * Returns 0 on success, negative value on failure
11415  */
11416 static int
11417 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11418                          struct i40e_dcbx_config *dcb_cfg,
11419                          uint8_t *tc_map)
11420 {
11421         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11422         uint8_t i, tc_bw, bw_lf;
11423
11424         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11425
11426         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11427         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11428                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11429                 return -EINVAL;
11430         }
11431
11432         /* assume each tc has the same bw */
11433         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11434         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11435                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11436         /* to ensure the sum of tcbw is equal to 100 */
11437         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11438         for (i = 0; i < bw_lf; i++)
11439                 dcb_cfg->etscfg.tcbwtable[i]++;
11440
11441         /* assume each tc has the same Transmission Selection Algorithm */
11442         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11443                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11444
11445         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11446                 dcb_cfg->etscfg.prioritytable[i] =
11447                                 dcb_rx_conf->dcb_tc[i];
11448
11449         /* FW needs one App to configure HW */
11450         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11451         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11452         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11453         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11454
11455         if (dcb_rx_conf->nb_tcs == 0)
11456                 *tc_map = 1; /* tc0 only */
11457         else
11458                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11459
11460         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11461                 dcb_cfg->pfc.willing = 0;
11462                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11463                 dcb_cfg->pfc.pfcenable = *tc_map;
11464         }
11465         return 0;
11466 }
11467
11468
11469 static enum i40e_status_code
11470 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11471                               struct i40e_aqc_vsi_properties_data *info,
11472                               uint8_t enabled_tcmap)
11473 {
11474         enum i40e_status_code ret;
11475         int i, total_tc = 0;
11476         uint16_t qpnum_per_tc, bsf, qp_idx;
11477         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11478         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11479         uint16_t used_queues;
11480
11481         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11482         if (ret != I40E_SUCCESS)
11483                 return ret;
11484
11485         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11486                 if (enabled_tcmap & (1 << i))
11487                         total_tc++;
11488         }
11489         if (total_tc == 0)
11490                 total_tc = 1;
11491         vsi->enabled_tc = enabled_tcmap;
11492
11493         /* different VSI has different queues assigned */
11494         if (vsi->type == I40E_VSI_MAIN)
11495                 used_queues = dev_data->nb_rx_queues -
11496                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11497         else if (vsi->type == I40E_VSI_VMDQ2)
11498                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11499         else {
11500                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11501                 return I40E_ERR_NO_AVAILABLE_VSI;
11502         }
11503
11504         qpnum_per_tc = used_queues / total_tc;
11505         /* Number of queues per enabled TC */
11506         if (qpnum_per_tc == 0) {
11507                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11508                 return I40E_ERR_INVALID_QP_ID;
11509         }
11510         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11511                                 I40E_MAX_Q_PER_TC);
11512         bsf = rte_bsf32(qpnum_per_tc);
11513
11514         /**
11515          * Configure TC and queue mapping parameters, for enabled TC,
11516          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11517          * default queue will serve it.
11518          */
11519         qp_idx = 0;
11520         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11521                 if (vsi->enabled_tc & (1 << i)) {
11522                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11523                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11524                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11525                         qp_idx += qpnum_per_tc;
11526                 } else
11527                         info->tc_mapping[i] = 0;
11528         }
11529
11530         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11531         if (vsi->type == I40E_VSI_SRIOV) {
11532                 info->mapping_flags |=
11533                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11534                 for (i = 0; i < vsi->nb_qps; i++)
11535                         info->queue_mapping[i] =
11536                                 rte_cpu_to_le_16(vsi->base_queue + i);
11537         } else {
11538                 info->mapping_flags |=
11539                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11540                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11541         }
11542         info->valid_sections |=
11543                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11544
11545         return I40E_SUCCESS;
11546 }
11547
11548 /*
11549  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11550  * @veb: VEB to be configured
11551  * @tc_map: enabled TC bitmap
11552  *
11553  * Returns 0 on success, negative value on failure
11554  */
11555 static enum i40e_status_code
11556 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11557 {
11558         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11559         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11560         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11561         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11562         enum i40e_status_code ret = I40E_SUCCESS;
11563         int i;
11564         uint32_t bw_max;
11565
11566         /* Check if enabled_tc is same as existing or new TCs */
11567         if (veb->enabled_tc == tc_map)
11568                 return ret;
11569
11570         /* configure tc bandwidth */
11571         memset(&veb_bw, 0, sizeof(veb_bw));
11572         veb_bw.tc_valid_bits = tc_map;
11573         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11574         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11575                 if (tc_map & BIT_ULL(i))
11576                         veb_bw.tc_bw_share_credits[i] = 1;
11577         }
11578         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11579                                                    &veb_bw, NULL);
11580         if (ret) {
11581                 PMD_INIT_LOG(ERR,
11582                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11583                         hw->aq.asq_last_status);
11584                 return ret;
11585         }
11586
11587         memset(&ets_query, 0, sizeof(ets_query));
11588         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11589                                                    &ets_query, NULL);
11590         if (ret != I40E_SUCCESS) {
11591                 PMD_DRV_LOG(ERR,
11592                         "Failed to get switch_comp ETS configuration %u",
11593                         hw->aq.asq_last_status);
11594                 return ret;
11595         }
11596         memset(&bw_query, 0, sizeof(bw_query));
11597         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11598                                                   &bw_query, NULL);
11599         if (ret != I40E_SUCCESS) {
11600                 PMD_DRV_LOG(ERR,
11601                         "Failed to get switch_comp bandwidth configuration %u",
11602                         hw->aq.asq_last_status);
11603                 return ret;
11604         }
11605
11606         /* store and print out BW info */
11607         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11608         veb->bw_info.bw_max = ets_query.tc_bw_max;
11609         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11610         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11611         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11612                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11613                      I40E_16_BIT_WIDTH);
11614         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11615                 veb->bw_info.bw_ets_share_credits[i] =
11616                                 bw_query.tc_bw_share_credits[i];
11617                 veb->bw_info.bw_ets_credits[i] =
11618                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11619                 /* 4 bits per TC, 4th bit is reserved */
11620                 veb->bw_info.bw_ets_max[i] =
11621                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11622                                   RTE_LEN2MASK(3, uint8_t));
11623                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11624                             veb->bw_info.bw_ets_share_credits[i]);
11625                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11626                             veb->bw_info.bw_ets_credits[i]);
11627                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11628                             veb->bw_info.bw_ets_max[i]);
11629         }
11630
11631         veb->enabled_tc = tc_map;
11632
11633         return ret;
11634 }
11635
11636
11637 /*
11638  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11639  * @vsi: VSI to be configured
11640  * @tc_map: enabled TC bitmap
11641  *
11642  * Returns 0 on success, negative value on failure
11643  */
11644 static enum i40e_status_code
11645 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11646 {
11647         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11648         struct i40e_vsi_context ctxt;
11649         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11650         enum i40e_status_code ret = I40E_SUCCESS;
11651         int i;
11652
11653         /* Check if enabled_tc is same as existing or new TCs */
11654         if (vsi->enabled_tc == tc_map)
11655                 return ret;
11656
11657         /* configure tc bandwidth */
11658         memset(&bw_data, 0, sizeof(bw_data));
11659         bw_data.tc_valid_bits = tc_map;
11660         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11661         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11662                 if (tc_map & BIT_ULL(i))
11663                         bw_data.tc_bw_credits[i] = 1;
11664         }
11665         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11666         if (ret) {
11667                 PMD_INIT_LOG(ERR,
11668                         "AQ command Config VSI BW allocation per TC failed = %d",
11669                         hw->aq.asq_last_status);
11670                 goto out;
11671         }
11672         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11673                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11674
11675         /* Update Queue Pairs Mapping for currently enabled UPs */
11676         ctxt.seid = vsi->seid;
11677         ctxt.pf_num = hw->pf_id;
11678         ctxt.vf_num = 0;
11679         ctxt.uplink_seid = vsi->uplink_seid;
11680         ctxt.info = vsi->info;
11681         i40e_get_cap(hw);
11682         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11683         if (ret)
11684                 goto out;
11685
11686         /* Update the VSI after updating the VSI queue-mapping information */
11687         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11688         if (ret) {
11689                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11690                         hw->aq.asq_last_status);
11691                 goto out;
11692         }
11693         /* update the local VSI info with updated queue map */
11694         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11695                                         sizeof(vsi->info.tc_mapping));
11696         rte_memcpy(&vsi->info.queue_mapping,
11697                         &ctxt.info.queue_mapping,
11698                 sizeof(vsi->info.queue_mapping));
11699         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11700         vsi->info.valid_sections = 0;
11701
11702         /* query and update current VSI BW information */
11703         ret = i40e_vsi_get_bw_config(vsi);
11704         if (ret) {
11705                 PMD_INIT_LOG(ERR,
11706                          "Failed updating vsi bw info, err %s aq_err %s",
11707                          i40e_stat_str(hw, ret),
11708                          i40e_aq_str(hw, hw->aq.asq_last_status));
11709                 goto out;
11710         }
11711
11712         vsi->enabled_tc = tc_map;
11713
11714 out:
11715         return ret;
11716 }
11717
11718 /*
11719  * i40e_dcb_hw_configure - program the dcb setting to hw
11720  * @pf: pf the configuration is taken on
11721  * @new_cfg: new configuration
11722  * @tc_map: enabled TC bitmap
11723  *
11724  * Returns 0 on success, negative value on failure
11725  */
11726 static enum i40e_status_code
11727 i40e_dcb_hw_configure(struct i40e_pf *pf,
11728                       struct i40e_dcbx_config *new_cfg,
11729                       uint8_t tc_map)
11730 {
11731         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11732         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11733         struct i40e_vsi *main_vsi = pf->main_vsi;
11734         struct i40e_vsi_list *vsi_list;
11735         enum i40e_status_code ret;
11736         int i;
11737         uint32_t val;
11738
11739         /* Use the FW API if FW > v4.4*/
11740         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11741               (hw->aq.fw_maj_ver >= 5))) {
11742                 PMD_INIT_LOG(ERR,
11743                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11744                 return I40E_ERR_FIRMWARE_API_VERSION;
11745         }
11746
11747         /* Check if need reconfiguration */
11748         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11749                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11750                 return I40E_SUCCESS;
11751         }
11752
11753         /* Copy the new config to the current config */
11754         *old_cfg = *new_cfg;
11755         old_cfg->etsrec = old_cfg->etscfg;
11756         ret = i40e_set_dcb_config(hw);
11757         if (ret) {
11758                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11759                          i40e_stat_str(hw, ret),
11760                          i40e_aq_str(hw, hw->aq.asq_last_status));
11761                 return ret;
11762         }
11763         /* set receive Arbiter to RR mode and ETS scheme by default */
11764         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11765                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11766                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11767                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11768                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11769                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11770                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11771                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11772                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11773                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11774                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11775                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11776                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11777         }
11778         /* get local mib to check whether it is configured correctly */
11779         /* IEEE mode */
11780         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11781         /* Get Local DCB Config */
11782         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11783                                      &hw->local_dcbx_config);
11784
11785         /* if Veb is created, need to update TC of it at first */
11786         if (main_vsi->veb) {
11787                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11788                 if (ret)
11789                         PMD_INIT_LOG(WARNING,
11790                                  "Failed configuring TC for VEB seid=%d",
11791                                  main_vsi->veb->seid);
11792         }
11793         /* Update each VSI */
11794         i40e_vsi_config_tc(main_vsi, tc_map);
11795         if (main_vsi->veb) {
11796                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11797                         /* Beside main VSI and VMDQ VSIs, only enable default
11798                          * TC for other VSIs
11799                          */
11800                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11801                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11802                                                          tc_map);
11803                         else
11804                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11805                                                          I40E_DEFAULT_TCMAP);
11806                         if (ret)
11807                                 PMD_INIT_LOG(WARNING,
11808                                         "Failed configuring TC for VSI seid=%d",
11809                                         vsi_list->vsi->seid);
11810                         /* continue */
11811                 }
11812         }
11813         return I40E_SUCCESS;
11814 }
11815
11816 /*
11817  * i40e_dcb_init_configure - initial dcb config
11818  * @dev: device being configured
11819  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11820  *
11821  * Returns 0 on success, negative value on failure
11822  */
11823 int
11824 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11825 {
11826         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11827         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11828         int i, ret = 0;
11829
11830         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11831                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11832                 return -ENOTSUP;
11833         }
11834
11835         /* DCB initialization:
11836          * Update DCB configuration from the Firmware and configure
11837          * LLDP MIB change event.
11838          */
11839         if (sw_dcb == TRUE) {
11840                 /* Stopping lldp is necessary for DPDK, but it will cause
11841                  * DCB init failed. For i40e_init_dcb(), the prerequisite
11842                  * for successful initialization of DCB is that LLDP is
11843                  * enabled. So it is needed to start lldp before DCB init
11844                  * and stop it after initialization.
11845                  */
11846                 ret = i40e_aq_start_lldp(hw, true, NULL);
11847                 if (ret != I40E_SUCCESS)
11848                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11849
11850                 ret = i40e_init_dcb(hw, true);
11851                 /* If lldp agent is stopped, the return value from
11852                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11853                  * adminq status. Otherwise, it should return success.
11854                  */
11855                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11856                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11857                         memset(&hw->local_dcbx_config, 0,
11858                                 sizeof(struct i40e_dcbx_config));
11859                         /* set dcb default configuration */
11860                         hw->local_dcbx_config.etscfg.willing = 0;
11861                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11862                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11863                         hw->local_dcbx_config.etscfg.tsatable[0] =
11864                                                 I40E_IEEE_TSA_ETS;
11865                         /* all UPs mapping to TC0 */
11866                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11867                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11868                         hw->local_dcbx_config.etsrec =
11869                                 hw->local_dcbx_config.etscfg;
11870                         hw->local_dcbx_config.pfc.willing = 0;
11871                         hw->local_dcbx_config.pfc.pfccap =
11872                                                 I40E_MAX_TRAFFIC_CLASS;
11873                         /* FW needs one App to configure HW */
11874                         hw->local_dcbx_config.numapps = 1;
11875                         hw->local_dcbx_config.app[0].selector =
11876                                                 I40E_APP_SEL_ETHTYPE;
11877                         hw->local_dcbx_config.app[0].priority = 3;
11878                         hw->local_dcbx_config.app[0].protocolid =
11879                                                 I40E_APP_PROTOID_FCOE;
11880                         ret = i40e_set_dcb_config(hw);
11881                         if (ret) {
11882                                 PMD_INIT_LOG(ERR,
11883                                         "default dcb config fails. err = %d, aq_err = %d.",
11884                                         ret, hw->aq.asq_last_status);
11885                                 return -ENOSYS;
11886                         }
11887                 } else {
11888                         PMD_INIT_LOG(ERR,
11889                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11890                                 ret, hw->aq.asq_last_status);
11891                         return -ENOTSUP;
11892                 }
11893
11894                 if (i40e_need_stop_lldp(dev)) {
11895                         ret = i40e_aq_stop_lldp(hw, true, true, NULL);
11896                         if (ret != I40E_SUCCESS)
11897                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11898                 }
11899         } else {
11900                 ret = i40e_aq_start_lldp(hw, true, NULL);
11901                 if (ret != I40E_SUCCESS)
11902                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11903
11904                 ret = i40e_init_dcb(hw, true);
11905                 if (!ret) {
11906                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11907                                 PMD_INIT_LOG(ERR,
11908                                         "HW doesn't support DCBX offload.");
11909                                 return -ENOTSUP;
11910                         }
11911                 } else {
11912                         PMD_INIT_LOG(ERR,
11913                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11914                                 ret, hw->aq.asq_last_status);
11915                         return -ENOTSUP;
11916                 }
11917         }
11918         return 0;
11919 }
11920
11921 /*
11922  * i40e_dcb_setup - setup dcb related config
11923  * @dev: device being configured
11924  *
11925  * Returns 0 on success, negative value on failure
11926  */
11927 static int
11928 i40e_dcb_setup(struct rte_eth_dev *dev)
11929 {
11930         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11931         struct i40e_dcbx_config dcb_cfg;
11932         uint8_t tc_map = 0;
11933         int ret = 0;
11934
11935         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11936                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11937                 return -ENOTSUP;
11938         }
11939
11940         if (pf->vf_num != 0)
11941                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11942
11943         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11944         if (ret) {
11945                 PMD_INIT_LOG(ERR, "invalid dcb config");
11946                 return -EINVAL;
11947         }
11948         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11949         if (ret) {
11950                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11951                 return -ENOSYS;
11952         }
11953
11954         return 0;
11955 }
11956
11957 static int
11958 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11959                       struct rte_eth_dcb_info *dcb_info)
11960 {
11961         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11962         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11963         struct i40e_vsi *vsi = pf->main_vsi;
11964         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11965         uint16_t bsf, tc_mapping;
11966         int i, j = 0;
11967
11968         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11969                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11970         else
11971                 dcb_info->nb_tcs = 1;
11972         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11973                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11974         for (i = 0; i < dcb_info->nb_tcs; i++)
11975                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11976
11977         /* get queue mapping if vmdq is disabled */
11978         if (!pf->nb_cfg_vmdq_vsi) {
11979                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11980                         if (!(vsi->enabled_tc & (1 << i)))
11981                                 continue;
11982                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11983                         dcb_info->tc_queue.tc_rxq[j][i].base =
11984                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11985                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11986                         dcb_info->tc_queue.tc_txq[j][i].base =
11987                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11988                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11989                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11990                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11991                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11992                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11993                 }
11994                 return 0;
11995         }
11996
11997         /* get queue mapping if vmdq is enabled */
11998         do {
11999                 vsi = pf->vmdq[j].vsi;
12000                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12001                         if (!(vsi->enabled_tc & (1 << i)))
12002                                 continue;
12003                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
12004                         dcb_info->tc_queue.tc_rxq[j][i].base =
12005                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
12006                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
12007                         dcb_info->tc_queue.tc_txq[j][i].base =
12008                                 dcb_info->tc_queue.tc_rxq[j][i].base;
12009                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
12010                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
12011                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
12012                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
12013                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
12014                 }
12015                 j++;
12016         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
12017         return 0;
12018 }
12019
12020 static int
12021 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
12022 {
12023         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12024         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12025         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12026         uint16_t msix_intr;
12027
12028         msix_intr = intr_handle->intr_vec[queue_id];
12029         if (msix_intr == I40E_MISC_VEC_ID)
12030                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12031                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
12032                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
12033                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12034         else
12035                 I40E_WRITE_REG(hw,
12036                                I40E_PFINT_DYN_CTLN(msix_intr -
12037                                                    I40E_RX_VEC_START),
12038                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
12039                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
12040                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12041
12042         I40E_WRITE_FLUSH(hw);
12043         rte_intr_ack(&pci_dev->intr_handle);
12044
12045         return 0;
12046 }
12047
12048 static int
12049 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
12050 {
12051         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
12052         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
12053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12054         uint16_t msix_intr;
12055
12056         msix_intr = intr_handle->intr_vec[queue_id];
12057         if (msix_intr == I40E_MISC_VEC_ID)
12058                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
12059                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
12060         else
12061                 I40E_WRITE_REG(hw,
12062                                I40E_PFINT_DYN_CTLN(msix_intr -
12063                                                    I40E_RX_VEC_START),
12064                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
12065         I40E_WRITE_FLUSH(hw);
12066
12067         return 0;
12068 }
12069
12070 /**
12071  * This function is used to check if the register is valid.
12072  * Below is the valid registers list for X722 only:
12073  * 0x2b800--0x2bb00
12074  * 0x38700--0x38a00
12075  * 0x3d800--0x3db00
12076  * 0x208e00--0x209000
12077  * 0x20be00--0x20c000
12078  * 0x263c00--0x264000
12079  * 0x265c00--0x266000
12080  */
12081 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
12082 {
12083         if ((type != I40E_MAC_X722) &&
12084             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
12085              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
12086              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
12087              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
12088              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
12089              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
12090              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
12091                 return 0;
12092         else
12093                 return 1;
12094 }
12095
12096 static int i40e_get_regs(struct rte_eth_dev *dev,
12097                          struct rte_dev_reg_info *regs)
12098 {
12099         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12100         uint32_t *ptr_data = regs->data;
12101         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
12102         const struct i40e_reg_info *reg_info;
12103
12104         if (ptr_data == NULL) {
12105                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
12106                 regs->width = sizeof(uint32_t);
12107                 return 0;
12108         }
12109
12110         /* The first few registers have to be read using AQ operations */
12111         reg_idx = 0;
12112         while (i40e_regs_adminq[reg_idx].name) {
12113                 reg_info = &i40e_regs_adminq[reg_idx++];
12114                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12115                         for (arr_idx2 = 0;
12116                                         arr_idx2 <= reg_info->count2;
12117                                         arr_idx2++) {
12118                                 reg_offset = arr_idx * reg_info->stride1 +
12119                                         arr_idx2 * reg_info->stride2;
12120                                 reg_offset += reg_info->base_addr;
12121                                 ptr_data[reg_offset >> 2] =
12122                                         i40e_read_rx_ctl(hw, reg_offset);
12123                         }
12124         }
12125
12126         /* The remaining registers can be read using primitives */
12127         reg_idx = 0;
12128         while (i40e_regs_others[reg_idx].name) {
12129                 reg_info = &i40e_regs_others[reg_idx++];
12130                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
12131                         for (arr_idx2 = 0;
12132                                         arr_idx2 <= reg_info->count2;
12133                                         arr_idx2++) {
12134                                 reg_offset = arr_idx * reg_info->stride1 +
12135                                         arr_idx2 * reg_info->stride2;
12136                                 reg_offset += reg_info->base_addr;
12137                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
12138                                         ptr_data[reg_offset >> 2] = 0;
12139                                 else
12140                                         ptr_data[reg_offset >> 2] =
12141                                                 I40E_READ_REG(hw, reg_offset);
12142                         }
12143         }
12144
12145         return 0;
12146 }
12147
12148 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
12149 {
12150         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12151
12152         /* Convert word count to byte count */
12153         return hw->nvm.sr_size << 1;
12154 }
12155
12156 static int i40e_get_eeprom(struct rte_eth_dev *dev,
12157                            struct rte_dev_eeprom_info *eeprom)
12158 {
12159         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12160         uint16_t *data = eeprom->data;
12161         uint16_t offset, length, cnt_words;
12162         int ret_code;
12163
12164         offset = eeprom->offset >> 1;
12165         length = eeprom->length >> 1;
12166         cnt_words = length;
12167
12168         if (offset > hw->nvm.sr_size ||
12169                 offset + length > hw->nvm.sr_size) {
12170                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
12171                 return -EINVAL;
12172         }
12173
12174         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
12175
12176         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
12177         if (ret_code != I40E_SUCCESS || cnt_words != length) {
12178                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
12179                 return -EIO;
12180         }
12181
12182         return 0;
12183 }
12184
12185 static int i40e_get_module_info(struct rte_eth_dev *dev,
12186                                 struct rte_eth_dev_module_info *modinfo)
12187 {
12188         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12189         uint32_t sff8472_comp = 0;
12190         uint32_t sff8472_swap = 0;
12191         uint32_t sff8636_rev = 0;
12192         i40e_status status;
12193         uint32_t type = 0;
12194
12195         /* Check if firmware supports reading module EEPROM. */
12196         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
12197                 PMD_DRV_LOG(ERR,
12198                             "Module EEPROM memory read not supported. "
12199                             "Please update the NVM image.\n");
12200                 return -EINVAL;
12201         }
12202
12203         status = i40e_update_link_info(hw);
12204         if (status)
12205                 return -EIO;
12206
12207         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
12208                 PMD_DRV_LOG(ERR,
12209                             "Cannot read module EEPROM memory. "
12210                             "No module connected.\n");
12211                 return -EINVAL;
12212         }
12213
12214         type = hw->phy.link_info.module_type[0];
12215
12216         switch (type) {
12217         case I40E_MODULE_TYPE_SFP:
12218                 status = i40e_aq_get_phy_register(hw,
12219                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12220                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12221                                 I40E_MODULE_SFF_8472_COMP,
12222                                 &sff8472_comp, NULL);
12223                 if (status)
12224                         return -EIO;
12225
12226                 status = i40e_aq_get_phy_register(hw,
12227                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12228                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
12229                                 I40E_MODULE_SFF_8472_SWAP,
12230                                 &sff8472_swap, NULL);
12231                 if (status)
12232                         return -EIO;
12233
12234                 /* Check if the module requires address swap to access
12235                  * the other EEPROM memory page.
12236                  */
12237                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
12238                         PMD_DRV_LOG(WARNING,
12239                                     "Module address swap to access "
12240                                     "page 0xA2 is not supported.\n");
12241                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12242                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12243                 } else if (sff8472_comp == 0x00) {
12244                         /* Module is not SFF-8472 compliant */
12245                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
12246                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
12247                 } else {
12248                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
12249                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
12250                 }
12251                 break;
12252         case I40E_MODULE_TYPE_QSFP_PLUS:
12253                 /* Read from memory page 0. */
12254                 status = i40e_aq_get_phy_register(hw,
12255                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12256                                 0, 1,
12257                                 I40E_MODULE_REVISION_ADDR,
12258                                 &sff8636_rev, NULL);
12259                 if (status)
12260                         return -EIO;
12261                 /* Determine revision compliance byte */
12262                 if (sff8636_rev > 0x02) {
12263                         /* Module is SFF-8636 compliant */
12264                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
12265                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12266                 } else {
12267                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
12268                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12269                 }
12270                 break;
12271         case I40E_MODULE_TYPE_QSFP28:
12272                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
12273                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
12274                 break;
12275         default:
12276                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
12277                 return -EINVAL;
12278         }
12279         return 0;
12280 }
12281
12282 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
12283                                   struct rte_dev_eeprom_info *info)
12284 {
12285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12286         bool is_sfp = false;
12287         i40e_status status;
12288         uint8_t *data;
12289         uint32_t value = 0;
12290         uint32_t i;
12291
12292         if (!info || !info->length || !info->data)
12293                 return -EINVAL;
12294
12295         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
12296                 is_sfp = true;
12297
12298         data = info->data;
12299         for (i = 0; i < info->length; i++) {
12300                 u32 offset = i + info->offset;
12301                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
12302
12303                 /* Check if we need to access the other memory page */
12304                 if (is_sfp) {
12305                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
12306                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
12307                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
12308                         }
12309                 } else {
12310                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
12311                                 /* Compute memory page number and offset. */
12312                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
12313                                 addr++;
12314                         }
12315                 }
12316                 status = i40e_aq_get_phy_register(hw,
12317                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
12318                                 addr, 1, offset, &value, NULL);
12319                 if (status)
12320                         return -EIO;
12321                 data[i] = (uint8_t)value;
12322         }
12323         return 0;
12324 }
12325
12326 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
12327                                      struct rte_ether_addr *mac_addr)
12328 {
12329         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
12330         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12331         struct i40e_vsi *vsi = pf->main_vsi;
12332         struct i40e_mac_filter_info mac_filter;
12333         struct i40e_mac_filter *f;
12334         int ret;
12335
12336         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
12337                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
12338                 return -EINVAL;
12339         }
12340
12341         TAILQ_FOREACH(f, &vsi->mac_list, next) {
12342                 if (rte_is_same_ether_addr(&pf->dev_addr,
12343                                                 &f->mac_info.mac_addr))
12344                         break;
12345         }
12346
12347         if (f == NULL) {
12348                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
12349                 return -EIO;
12350         }
12351
12352         mac_filter = f->mac_info;
12353         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
12354         if (ret != I40E_SUCCESS) {
12355                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
12356                 return -EIO;
12357         }
12358         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
12359         ret = i40e_vsi_add_mac(vsi, &mac_filter);
12360         if (ret != I40E_SUCCESS) {
12361                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
12362                 return -EIO;
12363         }
12364         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
12365
12366         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
12367                                         mac_addr->addr_bytes, NULL);
12368         if (ret != I40E_SUCCESS) {
12369                 PMD_DRV_LOG(ERR, "Failed to change mac");
12370                 return -EIO;
12371         }
12372
12373         return 0;
12374 }
12375
12376 static int
12377 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
12378 {
12379         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12380         struct rte_eth_dev_data *dev_data = pf->dev_data;
12381         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12382         int ret = 0;
12383
12384         /* check if mtu is within the allowed range */
12385         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12386                 return -EINVAL;
12387
12388         /* mtu setting is forbidden if port is start */
12389         if (dev_data->dev_started) {
12390                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12391                             dev_data->port_id);
12392                 return -EBUSY;
12393         }
12394
12395         if (frame_size > RTE_ETHER_MAX_LEN)
12396                 dev_data->dev_conf.rxmode.offloads |=
12397                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12398         else
12399                 dev_data->dev_conf.rxmode.offloads &=
12400                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12401
12402         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12403
12404         return ret;
12405 }
12406
12407 /* Restore ethertype filter */
12408 static void
12409 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12410 {
12411         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12412         struct i40e_ethertype_filter_list
12413                 *ethertype_list = &pf->ethertype.ethertype_list;
12414         struct i40e_ethertype_filter *f;
12415         struct i40e_control_filter_stats stats;
12416         uint16_t flags;
12417
12418         TAILQ_FOREACH(f, ethertype_list, rules) {
12419                 flags = 0;
12420                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12421                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12422                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12423                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12424                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12425
12426                 memset(&stats, 0, sizeof(stats));
12427                 i40e_aq_add_rem_control_packet_filter(hw,
12428                                             f->input.mac_addr.addr_bytes,
12429                                             f->input.ether_type,
12430                                             flags, pf->main_vsi->seid,
12431                                             f->queue, 1, &stats, NULL);
12432         }
12433         PMD_DRV_LOG(INFO, "Ethertype filter:"
12434                     " mac_etype_used = %u, etype_used = %u,"
12435                     " mac_etype_free = %u, etype_free = %u",
12436                     stats.mac_etype_used, stats.etype_used,
12437                     stats.mac_etype_free, stats.etype_free);
12438 }
12439
12440 /* Restore tunnel filter */
12441 static void
12442 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12443 {
12444         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12445         struct i40e_vsi *vsi;
12446         struct i40e_pf_vf *vf;
12447         struct i40e_tunnel_filter_list
12448                 *tunnel_list = &pf->tunnel.tunnel_list;
12449         struct i40e_tunnel_filter *f;
12450         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12451         bool big_buffer = 0;
12452
12453         TAILQ_FOREACH(f, tunnel_list, rules) {
12454                 if (!f->is_to_vf)
12455                         vsi = pf->main_vsi;
12456                 else {
12457                         vf = &pf->vfs[f->vf_id];
12458                         vsi = vf->vsi;
12459                 }
12460                 memset(&cld_filter, 0, sizeof(cld_filter));
12461                 rte_ether_addr_copy((struct rte_ether_addr *)
12462                                 &f->input.outer_mac,
12463                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12464                 rte_ether_addr_copy((struct rte_ether_addr *)
12465                                 &f->input.inner_mac,
12466                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12467                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12468                 cld_filter.element.flags = f->input.flags;
12469                 cld_filter.element.tenant_id = f->input.tenant_id;
12470                 cld_filter.element.queue_number = f->queue;
12471                 rte_memcpy(cld_filter.general_fields,
12472                            f->input.general_fields,
12473                            sizeof(f->input.general_fields));
12474
12475                 if (((f->input.flags &
12476                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12477                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12478                     ((f->input.flags &
12479                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12480                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12481                     ((f->input.flags &
12482                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12483                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12484                         big_buffer = 1;
12485
12486                 if (big_buffer)
12487                         i40e_aq_add_cloud_filters_bb(hw,
12488                                         vsi->seid, &cld_filter, 1);
12489                 else
12490                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12491                                                   &cld_filter.element, 1);
12492         }
12493 }
12494
12495 /* Restore RSS filter */
12496 static inline void
12497 i40e_rss_filter_restore(struct i40e_pf *pf)
12498 {
12499         struct i40e_rss_conf_list *list = &pf->rss_config_list;
12500         struct i40e_rss_filter *filter;
12501
12502         TAILQ_FOREACH(filter, list, next) {
12503                 i40e_config_rss_filter(pf, &filter->rss_filter_info, TRUE);
12504         }
12505 }
12506
12507 static void
12508 i40e_filter_restore(struct i40e_pf *pf)
12509 {
12510         i40e_ethertype_filter_restore(pf);
12511         i40e_tunnel_filter_restore(pf);
12512         i40e_fdir_filter_restore(pf);
12513         i40e_rss_filter_restore(pf);
12514 }
12515
12516 bool
12517 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12518 {
12519         if (strcmp(dev->device->driver->name, drv->driver.name))
12520                 return false;
12521
12522         return true;
12523 }
12524
12525 bool
12526 is_i40e_supported(struct rte_eth_dev *dev)
12527 {
12528         return is_device_supported(dev, &rte_i40e_pmd);
12529 }
12530
12531 struct i40e_customized_pctype*
12532 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12533 {
12534         int i;
12535
12536         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12537                 if (pf->customized_pctype[i].index == index)
12538                         return &pf->customized_pctype[i];
12539         }
12540         return NULL;
12541 }
12542
12543 static int
12544 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12545                               uint32_t pkg_size, uint32_t proto_num,
12546                               struct rte_pmd_i40e_proto_info *proto,
12547                               enum rte_pmd_i40e_package_op op)
12548 {
12549         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12550         uint32_t pctype_num;
12551         struct rte_pmd_i40e_ptype_info *pctype;
12552         uint32_t buff_size;
12553         struct i40e_customized_pctype *new_pctype = NULL;
12554         uint8_t proto_id;
12555         uint8_t pctype_value;
12556         char name[64];
12557         uint32_t i, j, n;
12558         int ret;
12559
12560         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12561             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12562                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12563                 return -1;
12564         }
12565
12566         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12567                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12568                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12569         if (ret) {
12570                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12571                 return -1;
12572         }
12573         if (!pctype_num) {
12574                 PMD_DRV_LOG(INFO, "No new pctype added");
12575                 return -1;
12576         }
12577
12578         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12579         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12580         if (!pctype) {
12581                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12582                 return -1;
12583         }
12584         /* get information about new pctype list */
12585         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12586                                         (uint8_t *)pctype, buff_size,
12587                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12588         if (ret) {
12589                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12590                 rte_free(pctype);
12591                 return -1;
12592         }
12593
12594         /* Update customized pctype. */
12595         for (i = 0; i < pctype_num; i++) {
12596                 pctype_value = pctype[i].ptype_id;
12597                 memset(name, 0, sizeof(name));
12598                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12599                         proto_id = pctype[i].protocols[j];
12600                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12601                                 continue;
12602                         for (n = 0; n < proto_num; n++) {
12603                                 if (proto[n].proto_id != proto_id)
12604                                         continue;
12605                                 strlcat(name, proto[n].name, sizeof(name));
12606                                 strlcat(name, "_", sizeof(name));
12607                                 break;
12608                         }
12609                 }
12610                 name[strlen(name) - 1] = '\0';
12611                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12612                 if (!strcmp(name, "GTPC"))
12613                         new_pctype =
12614                                 i40e_find_customized_pctype(pf,
12615                                                       I40E_CUSTOMIZED_GTPC);
12616                 else if (!strcmp(name, "GTPU_IPV4"))
12617                         new_pctype =
12618                                 i40e_find_customized_pctype(pf,
12619                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12620                 else if (!strcmp(name, "GTPU_IPV6"))
12621                         new_pctype =
12622                                 i40e_find_customized_pctype(pf,
12623                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12624                 else if (!strcmp(name, "GTPU"))
12625                         new_pctype =
12626                                 i40e_find_customized_pctype(pf,
12627                                                       I40E_CUSTOMIZED_GTPU);
12628                 else if (!strcmp(name, "IPV4_L2TPV3"))
12629                         new_pctype =
12630                                 i40e_find_customized_pctype(pf,
12631                                                 I40E_CUSTOMIZED_IPV4_L2TPV3);
12632                 else if (!strcmp(name, "IPV6_L2TPV3"))
12633                         new_pctype =
12634                                 i40e_find_customized_pctype(pf,
12635                                                 I40E_CUSTOMIZED_IPV6_L2TPV3);
12636                 else if (!strcmp(name, "IPV4_ESP"))
12637                         new_pctype =
12638                                 i40e_find_customized_pctype(pf,
12639                                                 I40E_CUSTOMIZED_ESP_IPV4);
12640                 else if (!strcmp(name, "IPV6_ESP"))
12641                         new_pctype =
12642                                 i40e_find_customized_pctype(pf,
12643                                                 I40E_CUSTOMIZED_ESP_IPV6);
12644                 else if (!strcmp(name, "IPV4_UDP_ESP"))
12645                         new_pctype =
12646                                 i40e_find_customized_pctype(pf,
12647                                                 I40E_CUSTOMIZED_ESP_IPV4_UDP);
12648                 else if (!strcmp(name, "IPV6_UDP_ESP"))
12649                         new_pctype =
12650                                 i40e_find_customized_pctype(pf,
12651                                                 I40E_CUSTOMIZED_ESP_IPV6_UDP);
12652                 else if (!strcmp(name, "IPV4_AH"))
12653                         new_pctype =
12654                                 i40e_find_customized_pctype(pf,
12655                                                 I40E_CUSTOMIZED_AH_IPV4);
12656                 else if (!strcmp(name, "IPV6_AH"))
12657                         new_pctype =
12658                                 i40e_find_customized_pctype(pf,
12659                                                 I40E_CUSTOMIZED_AH_IPV6);
12660                 if (new_pctype) {
12661                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12662                                 new_pctype->pctype = pctype_value;
12663                                 new_pctype->valid = true;
12664                         } else {
12665                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12666                                 new_pctype->valid = false;
12667                         }
12668                 }
12669         }
12670
12671         rte_free(pctype);
12672         return 0;
12673 }
12674
12675 static int
12676 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12677                              uint32_t pkg_size, uint32_t proto_num,
12678                              struct rte_pmd_i40e_proto_info *proto,
12679                              enum rte_pmd_i40e_package_op op)
12680 {
12681         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12682         uint16_t port_id = dev->data->port_id;
12683         uint32_t ptype_num;
12684         struct rte_pmd_i40e_ptype_info *ptype;
12685         uint32_t buff_size;
12686         uint8_t proto_id;
12687         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12688         uint32_t i, j, n;
12689         bool in_tunnel;
12690         int ret;
12691
12692         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12693             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12694                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12695                 return -1;
12696         }
12697
12698         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12699                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12700                 return 0;
12701         }
12702
12703         /* get information about new ptype num */
12704         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12705                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12706                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12707         if (ret) {
12708                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12709                 return ret;
12710         }
12711         if (!ptype_num) {
12712                 PMD_DRV_LOG(INFO, "No new ptype added");
12713                 return -1;
12714         }
12715
12716         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12717         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12718         if (!ptype) {
12719                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12720                 return -1;
12721         }
12722
12723         /* get information about new ptype list */
12724         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12725                                         (uint8_t *)ptype, buff_size,
12726                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12727         if (ret) {
12728                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12729                 rte_free(ptype);
12730                 return ret;
12731         }
12732
12733         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12734         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12735         if (!ptype_mapping) {
12736                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12737                 rte_free(ptype);
12738                 return -1;
12739         }
12740
12741         /* Update ptype mapping table. */
12742         for (i = 0; i < ptype_num; i++) {
12743                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12744                 ptype_mapping[i].sw_ptype = 0;
12745                 in_tunnel = false;
12746                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12747                         proto_id = ptype[i].protocols[j];
12748                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12749                                 continue;
12750                         for (n = 0; n < proto_num; n++) {
12751                                 if (proto[n].proto_id != proto_id)
12752                                         continue;
12753                                 memset(name, 0, sizeof(name));
12754                                 strcpy(name, proto[n].name);
12755                                 PMD_DRV_LOG(INFO, "name = %s\n", name);
12756                                 if (!strncasecmp(name, "PPPOE", 5))
12757                                         ptype_mapping[i].sw_ptype |=
12758                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12759                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12760                                          !in_tunnel) {
12761                                         ptype_mapping[i].sw_ptype |=
12762                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12763                                         ptype_mapping[i].sw_ptype |=
12764                                                 RTE_PTYPE_L4_FRAG;
12765                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12766                                            in_tunnel) {
12767                                         ptype_mapping[i].sw_ptype |=
12768                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12769                                         ptype_mapping[i].sw_ptype |=
12770                                                 RTE_PTYPE_INNER_L4_FRAG;
12771                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12772                                         ptype_mapping[i].sw_ptype |=
12773                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12774                                         in_tunnel = true;
12775                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12776                                            !in_tunnel)
12777                                         ptype_mapping[i].sw_ptype |=
12778                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12779                                 else if (!strncasecmp(name, "IPV4", 4) &&
12780                                          in_tunnel)
12781                                         ptype_mapping[i].sw_ptype |=
12782                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12783                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12784                                          !in_tunnel) {
12785                                         ptype_mapping[i].sw_ptype |=
12786                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12787                                         ptype_mapping[i].sw_ptype |=
12788                                                 RTE_PTYPE_L4_FRAG;
12789                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12790                                            in_tunnel) {
12791                                         ptype_mapping[i].sw_ptype |=
12792                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12793                                         ptype_mapping[i].sw_ptype |=
12794                                                 RTE_PTYPE_INNER_L4_FRAG;
12795                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12796                                         ptype_mapping[i].sw_ptype |=
12797                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12798                                         in_tunnel = true;
12799                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12800                                            !in_tunnel)
12801                                         ptype_mapping[i].sw_ptype |=
12802                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12803                                 else if (!strncasecmp(name, "IPV6", 4) &&
12804                                          in_tunnel)
12805                                         ptype_mapping[i].sw_ptype |=
12806                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12807                                 else if (!strncasecmp(name, "UDP", 3) &&
12808                                          !in_tunnel)
12809                                         ptype_mapping[i].sw_ptype |=
12810                                                 RTE_PTYPE_L4_UDP;
12811                                 else if (!strncasecmp(name, "UDP", 3) &&
12812                                          in_tunnel)
12813                                         ptype_mapping[i].sw_ptype |=
12814                                                 RTE_PTYPE_INNER_L4_UDP;
12815                                 else if (!strncasecmp(name, "TCP", 3) &&
12816                                          !in_tunnel)
12817                                         ptype_mapping[i].sw_ptype |=
12818                                                 RTE_PTYPE_L4_TCP;
12819                                 else if (!strncasecmp(name, "TCP", 3) &&
12820                                          in_tunnel)
12821                                         ptype_mapping[i].sw_ptype |=
12822                                                 RTE_PTYPE_INNER_L4_TCP;
12823                                 else if (!strncasecmp(name, "SCTP", 4) &&
12824                                          !in_tunnel)
12825                                         ptype_mapping[i].sw_ptype |=
12826                                                 RTE_PTYPE_L4_SCTP;
12827                                 else if (!strncasecmp(name, "SCTP", 4) &&
12828                                          in_tunnel)
12829                                         ptype_mapping[i].sw_ptype |=
12830                                                 RTE_PTYPE_INNER_L4_SCTP;
12831                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12832                                           !strncasecmp(name, "ICMPV6", 6)) &&
12833                                          !in_tunnel)
12834                                         ptype_mapping[i].sw_ptype |=
12835                                                 RTE_PTYPE_L4_ICMP;
12836                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12837                                           !strncasecmp(name, "ICMPV6", 6)) &&
12838                                          in_tunnel)
12839                                         ptype_mapping[i].sw_ptype |=
12840                                                 RTE_PTYPE_INNER_L4_ICMP;
12841                                 else if (!strncasecmp(name, "GTPC", 4)) {
12842                                         ptype_mapping[i].sw_ptype |=
12843                                                 RTE_PTYPE_TUNNEL_GTPC;
12844                                         in_tunnel = true;
12845                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12846                                         ptype_mapping[i].sw_ptype |=
12847                                                 RTE_PTYPE_TUNNEL_GTPU;
12848                                         in_tunnel = true;
12849                                 } else if (!strncasecmp(name, "ESP", 3)) {
12850                                         ptype_mapping[i].sw_ptype |=
12851                                                 RTE_PTYPE_TUNNEL_ESP;
12852                                         in_tunnel = true;
12853                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12854                                         ptype_mapping[i].sw_ptype |=
12855                                                 RTE_PTYPE_TUNNEL_GRENAT;
12856                                         in_tunnel = true;
12857                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12858                                            !strncasecmp(name, "L2TPV2", 6) ||
12859                                            !strncasecmp(name, "L2TPV3", 6)) {
12860                                         ptype_mapping[i].sw_ptype |=
12861                                                 RTE_PTYPE_TUNNEL_L2TP;
12862                                         in_tunnel = true;
12863                                 }
12864
12865                                 break;
12866                         }
12867                 }
12868         }
12869
12870         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12871                                                 ptype_num, 0);
12872         if (ret)
12873                 PMD_DRV_LOG(ERR, "Failed to update ptype mapping table.");
12874
12875         rte_free(ptype_mapping);
12876         rte_free(ptype);
12877         return ret;
12878 }
12879
12880 void
12881 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12882                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12883 {
12884         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12885         uint32_t proto_num;
12886         struct rte_pmd_i40e_proto_info *proto;
12887         uint32_t buff_size;
12888         uint32_t i;
12889         int ret;
12890
12891         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12892             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12893                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12894                 return;
12895         }
12896
12897         /* get information about protocol number */
12898         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12899                                        (uint8_t *)&proto_num, sizeof(proto_num),
12900                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12901         if (ret) {
12902                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12903                 return;
12904         }
12905         if (!proto_num) {
12906                 PMD_DRV_LOG(INFO, "No new protocol added");
12907                 return;
12908         }
12909
12910         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12911         proto = rte_zmalloc("new_proto", buff_size, 0);
12912         if (!proto) {
12913                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12914                 return;
12915         }
12916
12917         /* get information about protocol list */
12918         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12919                                         (uint8_t *)proto, buff_size,
12920                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12921         if (ret) {
12922                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12923                 rte_free(proto);
12924                 return;
12925         }
12926
12927         /* Check if GTP is supported. */
12928         for (i = 0; i < proto_num; i++) {
12929                 if (!strncmp(proto[i].name, "GTP", 3)) {
12930                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12931                                 pf->gtp_support = true;
12932                         else
12933                                 pf->gtp_support = false;
12934                         break;
12935                 }
12936         }
12937
12938         /* Check if ESP is supported. */
12939         for (i = 0; i < proto_num; i++) {
12940                 if (!strncmp(proto[i].name, "ESP", 3)) {
12941                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12942                                 pf->esp_support = true;
12943                         else
12944                                 pf->esp_support = false;
12945                         break;
12946                 }
12947         }
12948
12949         /* Update customized pctype info */
12950         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12951                                             proto_num, proto, op);
12952         if (ret)
12953                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12954
12955         /* Update customized ptype info */
12956         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12957                                            proto_num, proto, op);
12958         if (ret)
12959                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12960
12961         rte_free(proto);
12962 }
12963
12964 /* Create a QinQ cloud filter
12965  *
12966  * The Fortville NIC has limited resources for tunnel filters,
12967  * so we can only reuse existing filters.
12968  *
12969  * In step 1 we define which Field Vector fields can be used for
12970  * filter types.
12971  * As we do not have the inner tag defined as a field,
12972  * we have to define it first, by reusing one of L1 entries.
12973  *
12974  * In step 2 we are replacing one of existing filter types with
12975  * a new one for QinQ.
12976  * As we reusing L1 and replacing L2, some of the default filter
12977  * types will disappear,which depends on L1 and L2 entries we reuse.
12978  *
12979  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12980  *
12981  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12982  *              later when we define the cloud filter.
12983  *      a.      Valid_flags.replace_cloud = 0
12984  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12985  *      c.      New_filter = 0x10
12986  *      d.      TR bit = 0xff (optional, not used here)
12987  *      e.      Buffer – 2 entries:
12988  *              i.      Byte 0 = 8 (outer vlan FV index).
12989  *                      Byte 1 = 0 (rsv)
12990  *                      Byte 2-3 = 0x0fff
12991  *              ii.     Byte 0 = 37 (inner vlan FV index).
12992  *                      Byte 1 =0 (rsv)
12993  *                      Byte 2-3 = 0x0fff
12994  *
12995  * Step 2:
12996  * 2.   Create cloud filter using two L1 filters entries: stag and
12997  *              new filter(outer vlan+ inner vlan)
12998  *      a.      Valid_flags.replace_cloud = 1
12999  *      b.      Old_filter = 1 (instead of outer IP)
13000  *      c.      New_filter = 0x10
13001  *      d.      Buffer – 2 entries:
13002  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
13003  *                      Byte 1-3 = 0 (rsv)
13004  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
13005  *                      Byte 9-11 = 0 (rsv)
13006  */
13007 static int
13008 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
13009 {
13010         int ret = -ENOTSUP;
13011         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
13012         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
13013         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13014         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
13015
13016         if (pf->support_multi_driver) {
13017                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
13018                 return ret;
13019         }
13020
13021         /* Init */
13022         memset(&filter_replace, 0,
13023                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13024         memset(&filter_replace_buf, 0,
13025                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13026
13027         /* create L1 filter */
13028         filter_replace.old_filter_type =
13029                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
13030         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13031         filter_replace.tr_bit = 0;
13032
13033         /* Prepare the buffer, 2 entries */
13034         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
13035         filter_replace_buf.data[0] |=
13036                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13037         /* Field Vector 12b mask */
13038         filter_replace_buf.data[2] = 0xff;
13039         filter_replace_buf.data[3] = 0x0f;
13040         filter_replace_buf.data[4] =
13041                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
13042         filter_replace_buf.data[4] |=
13043                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13044         /* Field Vector 12b mask */
13045         filter_replace_buf.data[6] = 0xff;
13046         filter_replace_buf.data[7] = 0x0f;
13047         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13048                         &filter_replace_buf);
13049         if (ret != I40E_SUCCESS)
13050                 return ret;
13051
13052         if (filter_replace.old_filter_type !=
13053             filter_replace.new_filter_type)
13054                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
13055                             " original: 0x%x, new: 0x%x",
13056                             dev->device->name,
13057                             filter_replace.old_filter_type,
13058                             filter_replace.new_filter_type);
13059
13060         /* Apply the second L2 cloud filter */
13061         memset(&filter_replace, 0,
13062                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
13063         memset(&filter_replace_buf, 0,
13064                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
13065
13066         /* create L2 filter, input for L2 filter will be L1 filter  */
13067         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
13068         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
13069         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13070
13071         /* Prepare the buffer, 2 entries */
13072         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
13073         filter_replace_buf.data[0] |=
13074                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13075         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
13076         filter_replace_buf.data[4] |=
13077                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
13078         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
13079                         &filter_replace_buf);
13080         if (!ret && (filter_replace.old_filter_type !=
13081                      filter_replace.new_filter_type))
13082                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
13083                             " original: 0x%x, new: 0x%x",
13084                             dev->device->name,
13085                             filter_replace.old_filter_type,
13086                             filter_replace.new_filter_type);
13087
13088         return ret;
13089 }
13090
13091 int
13092 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
13093                    const struct rte_flow_action_rss *in)
13094 {
13095         if (in->key_len > RTE_DIM(out->key) ||
13096             in->queue_num > RTE_DIM(out->queue))
13097                 return -EINVAL;
13098         if (!in->key && in->key_len)
13099                 return -EINVAL;
13100         out->conf = (struct rte_flow_action_rss){
13101                 .func = in->func,
13102                 .level = in->level,
13103                 .types = in->types,
13104                 .key_len = in->key_len,
13105                 .queue_num = in->queue_num,
13106                 .queue = memcpy(out->queue, in->queue,
13107                                 sizeof(*in->queue) * in->queue_num),
13108         };
13109         if (in->key)
13110                 out->conf.key = memcpy(out->key, in->key, in->key_len);
13111         return 0;
13112 }
13113
13114 /* Write HENA register to enable hash */
13115 static int
13116 i40e_rss_hash_set(struct i40e_pf *pf, struct i40e_rte_flow_rss_conf *rss_conf)
13117 {
13118         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13119         uint8_t *key = (void *)(uintptr_t)rss_conf->conf.key;
13120         uint64_t hena;
13121         int ret;
13122
13123         ret = i40e_set_rss_key(pf->main_vsi, key,
13124                                rss_conf->conf.key_len);
13125         if (ret)
13126                 return ret;
13127
13128         hena = i40e_config_hena(pf->adapter, rss_conf->conf.types);
13129         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
13130         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
13131         I40E_WRITE_FLUSH(hw);
13132
13133         return 0;
13134 }
13135
13136 /* Configure hash input set */
13137 static int
13138 i40e_rss_conf_hash_inset(struct i40e_pf *pf, uint64_t types)
13139 {
13140         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13141         struct rte_eth_input_set_conf conf;
13142         uint64_t mask0;
13143         int ret = 0;
13144         uint32_t j;
13145         int i;
13146         static const struct {
13147                 uint64_t type;
13148                 enum rte_eth_input_set_field field;
13149         } inset_match_table[] = {
13150                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_SRC_ONLY,
13151                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13152                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L3_DST_ONLY,
13153                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13154                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_SRC_ONLY,
13155                         RTE_ETH_INPUT_SET_UNKNOWN},
13156                 {ETH_RSS_FRAG_IPV4 | ETH_RSS_L4_DST_ONLY,
13157                         RTE_ETH_INPUT_SET_UNKNOWN},
13158
13159                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_SRC_ONLY,
13160                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13161                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L3_DST_ONLY,
13162                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13163                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_SRC_ONLY,
13164                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13165                 {ETH_RSS_NONFRAG_IPV4_TCP | ETH_RSS_L4_DST_ONLY,
13166                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13167
13168                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_SRC_ONLY,
13169                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13170                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L3_DST_ONLY,
13171                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13172                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_SRC_ONLY,
13173                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13174                 {ETH_RSS_NONFRAG_IPV4_UDP | ETH_RSS_L4_DST_ONLY,
13175                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13176
13177                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_SRC_ONLY,
13178                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13179                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L3_DST_ONLY,
13180                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13181                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_SRC_ONLY,
13182                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13183                 {ETH_RSS_NONFRAG_IPV4_SCTP | ETH_RSS_L4_DST_ONLY,
13184                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13185
13186                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_SRC_ONLY,
13187                         RTE_ETH_INPUT_SET_L3_SRC_IP4},
13188                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L3_DST_ONLY,
13189                         RTE_ETH_INPUT_SET_L3_DST_IP4},
13190                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_SRC_ONLY,
13191                         RTE_ETH_INPUT_SET_UNKNOWN},
13192                 {ETH_RSS_NONFRAG_IPV4_OTHER | ETH_RSS_L4_DST_ONLY,
13193                         RTE_ETH_INPUT_SET_UNKNOWN},
13194
13195                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_SRC_ONLY,
13196                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13197                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L3_DST_ONLY,
13198                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13199                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_SRC_ONLY,
13200                         RTE_ETH_INPUT_SET_UNKNOWN},
13201                 {ETH_RSS_FRAG_IPV6 | ETH_RSS_L4_DST_ONLY,
13202                         RTE_ETH_INPUT_SET_UNKNOWN},
13203
13204                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_SRC_ONLY,
13205                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13206                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L3_DST_ONLY,
13207                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13208                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_SRC_ONLY,
13209                         RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT},
13210                 {ETH_RSS_NONFRAG_IPV6_TCP | ETH_RSS_L4_DST_ONLY,
13211                         RTE_ETH_INPUT_SET_L4_TCP_DST_PORT},
13212
13213                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_SRC_ONLY,
13214                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13215                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L3_DST_ONLY,
13216                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13217                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_SRC_ONLY,
13218                         RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT},
13219                 {ETH_RSS_NONFRAG_IPV6_UDP | ETH_RSS_L4_DST_ONLY,
13220                         RTE_ETH_INPUT_SET_L4_UDP_DST_PORT},
13221
13222                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_SRC_ONLY,
13223                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13224                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L3_DST_ONLY,
13225                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13226                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_SRC_ONLY,
13227                         RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT},
13228                 {ETH_RSS_NONFRAG_IPV6_SCTP | ETH_RSS_L4_DST_ONLY,
13229                         RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT},
13230
13231                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_SRC_ONLY,
13232                         RTE_ETH_INPUT_SET_L3_SRC_IP6},
13233                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L3_DST_ONLY,
13234                         RTE_ETH_INPUT_SET_L3_DST_IP6},
13235                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_SRC_ONLY,
13236                         RTE_ETH_INPUT_SET_UNKNOWN},
13237                 {ETH_RSS_NONFRAG_IPV6_OTHER | ETH_RSS_L4_DST_ONLY,
13238                         RTE_ETH_INPUT_SET_UNKNOWN},
13239         };
13240
13241         mask0 = types & pf->adapter->flow_types_mask;
13242         conf.op = RTE_ETH_INPUT_SET_SELECT;
13243         conf.inset_size = 0;
13244         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < RTE_ETH_FLOW_MAX; i++) {
13245                 if (mask0 & (1ULL << i)) {
13246                         conf.flow_type = i;
13247                         break;
13248                 }
13249         }
13250
13251         for (j = 0; j < RTE_DIM(inset_match_table); j++) {
13252                 if ((types & inset_match_table[j].type) ==
13253                     inset_match_table[j].type) {
13254                         if (inset_match_table[j].field ==
13255                             RTE_ETH_INPUT_SET_UNKNOWN)
13256                                 return -EINVAL;
13257
13258                         conf.field[conf.inset_size] =
13259                                 inset_match_table[j].field;
13260                         conf.inset_size++;
13261                 }
13262         }
13263
13264         if (conf.inset_size) {
13265                 ret = i40e_hash_filter_inset_select(hw, &conf);
13266                 if (ret)
13267                         return ret;
13268         }
13269
13270         return ret;
13271 }
13272
13273 /* Look up the conflicted rule then mark it as invalid */
13274 static void
13275 i40e_rss_mark_invalid_rule(struct i40e_pf *pf,
13276                 struct i40e_rte_flow_rss_conf *conf)
13277 {
13278         struct i40e_rss_filter *rss_item;
13279         uint64_t rss_inset;
13280
13281         /* Clear input set bits before comparing the pctype */
13282         rss_inset = ~(ETH_RSS_L3_SRC_ONLY | ETH_RSS_L3_DST_ONLY |
13283                 ETH_RSS_L4_SRC_ONLY | ETH_RSS_L4_DST_ONLY);
13284
13285         /* Look up the conflicted rule then mark it as invalid */
13286         TAILQ_FOREACH(rss_item, &pf->rss_config_list, next) {
13287                 if (!rss_item->rss_filter_info.valid)
13288                         continue;
13289
13290                 if (conf->conf.queue_num &&
13291                     rss_item->rss_filter_info.conf.queue_num)
13292                         rss_item->rss_filter_info.valid = false;
13293
13294                 if (conf->conf.types &&
13295                     (rss_item->rss_filter_info.conf.types &
13296                     rss_inset) ==
13297                     (conf->conf.types & rss_inset))
13298                         rss_item->rss_filter_info.valid = false;
13299
13300                 if (conf->conf.func ==
13301                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
13302                     rss_item->rss_filter_info.conf.func ==
13303                     RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13304                         rss_item->rss_filter_info.valid = false;
13305         }
13306 }
13307
13308 /* Configure RSS hash function */
13309 static int
13310 i40e_rss_config_hash_function(struct i40e_pf *pf,
13311                 struct i40e_rte_flow_rss_conf *conf)
13312 {
13313         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13314         uint32_t reg, i;
13315         uint64_t mask0;
13316         uint16_t j;
13317
13318         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13319                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13320                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
13321                         PMD_DRV_LOG(DEBUG, "Hash function already set to Simple XOR");
13322                         I40E_WRITE_FLUSH(hw);
13323                         i40e_rss_mark_invalid_rule(pf, conf);
13324
13325                         return 0;
13326                 }
13327                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
13328
13329                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13330                 I40E_WRITE_FLUSH(hw);
13331                 i40e_rss_mark_invalid_rule(pf, conf);
13332         } else if (conf->conf.func ==
13333                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13334                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13335
13336                 i40e_set_symmetric_hash_enable_per_port(hw, 1);
13337                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13338                         if (mask0 & (1UL << i))
13339                                 break;
13340                 }
13341
13342                 if (i == UINT64_BIT)
13343                         return -EINVAL;
13344
13345                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13346                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13347                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13348                                 i40e_write_global_rx_ctl(hw,
13349                                         I40E_GLQF_HSYM(j),
13350                                         I40E_GLQF_HSYM_SYMH_ENA_MASK);
13351                 }
13352         }
13353
13354         return 0;
13355 }
13356
13357 /* Enable RSS according to the configuration */
13358 static int
13359 i40e_rss_enable_hash(struct i40e_pf *pf,
13360                 struct i40e_rte_flow_rss_conf *conf)
13361 {
13362         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13363         struct i40e_rte_flow_rss_conf rss_conf;
13364
13365         if (!(conf->conf.types & pf->adapter->flow_types_mask))
13366                 return -ENOTSUP;
13367
13368         memset(&rss_conf, 0, sizeof(rss_conf));
13369         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13370
13371         /* Configure hash input set */
13372         if (i40e_rss_conf_hash_inset(pf, conf->conf.types))
13373                 return -EINVAL;
13374
13375         if (rss_conf.conf.key == NULL || rss_conf.conf.key_len <
13376             (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
13377                 /* Random default keys */
13378                 static uint32_t rss_key_default[] = {0x6b793944,
13379                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
13380                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
13381                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
13382
13383                 rss_conf.conf.key = (uint8_t *)rss_key_default;
13384                 rss_conf.conf.key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
13385                                 sizeof(uint32_t);
13386                 PMD_DRV_LOG(INFO,
13387                         "No valid RSS key config for i40e, using default\n");
13388         }
13389
13390         rss_conf.conf.types |= rss_info->conf.types;
13391         i40e_rss_hash_set(pf, &rss_conf);
13392
13393         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ)
13394                 i40e_rss_config_hash_function(pf, conf);
13395
13396         i40e_rss_mark_invalid_rule(pf, conf);
13397
13398         return 0;
13399 }
13400
13401 /* Configure RSS queue region */
13402 static int
13403 i40e_rss_config_queue_region(struct i40e_pf *pf,
13404                 struct i40e_rte_flow_rss_conf *conf)
13405 {
13406         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13407         uint32_t lut = 0;
13408         uint16_t j, num;
13409         uint32_t i;
13410
13411         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13412          * It's necessary to calculate the actual PF queues that are configured.
13413          */
13414         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13415                 num = i40e_pf_calc_configured_queues_num(pf);
13416         else
13417                 num = pf->dev_data->nb_rx_queues;
13418
13419         num = RTE_MIN(num, conf->conf.queue_num);
13420         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13421                         num);
13422
13423         if (num == 0) {
13424                 PMD_DRV_LOG(ERR,
13425                         "No PF queues are configured to enable RSS for port %u",
13426                         pf->dev_data->port_id);
13427                 return -ENOTSUP;
13428         }
13429
13430         /* Fill in redirection table */
13431         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13432                 if (j == num)
13433                         j = 0;
13434                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
13435                         hw->func_caps.rss_table_entry_width) - 1));
13436                 if ((i & 3) == 3)
13437                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13438         }
13439
13440         i40e_rss_mark_invalid_rule(pf, conf);
13441
13442         return 0;
13443 }
13444
13445 /* Configure RSS hash function to default */
13446 static int
13447 i40e_rss_clear_hash_function(struct i40e_pf *pf,
13448                 struct i40e_rte_flow_rss_conf *conf)
13449 {
13450         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13451         uint32_t i, reg;
13452         uint64_t mask0;
13453         uint16_t j;
13454
13455         if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13456                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
13457                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
13458                         PMD_DRV_LOG(DEBUG,
13459                                 "Hash function already set to Toeplitz");
13460                         I40E_WRITE_FLUSH(hw);
13461
13462                         return 0;
13463                 }
13464                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
13465
13466                 i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
13467                 I40E_WRITE_FLUSH(hw);
13468         } else if (conf->conf.func ==
13469                    RTE_ETH_HASH_FUNCTION_SYMMETRIC_TOEPLITZ) {
13470                 mask0 = conf->conf.types & pf->adapter->flow_types_mask;
13471
13472                 for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
13473                         if (mask0 & (1UL << i))
13474                                 break;
13475                 }
13476
13477                 if (i == UINT64_BIT)
13478                         return -EINVAL;
13479
13480                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
13481                      j < I40E_FILTER_PCTYPE_MAX; j++) {
13482                         if (pf->adapter->pctypes_tbl[i] & (1ULL << j))
13483                                 i40e_write_global_rx_ctl(hw,
13484                                         I40E_GLQF_HSYM(j),
13485                                         0);
13486                 }
13487         }
13488
13489         return 0;
13490 }
13491
13492 /* Disable RSS hash and configure default input set */
13493 static int
13494 i40e_rss_disable_hash(struct i40e_pf *pf,
13495                 struct i40e_rte_flow_rss_conf *conf)
13496 {
13497         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13498         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13499         struct i40e_rte_flow_rss_conf rss_conf;
13500         uint32_t i;
13501
13502         memset(&rss_conf, 0, sizeof(rss_conf));
13503         rte_memcpy(&rss_conf, conf, sizeof(rss_conf));
13504
13505         /* Disable RSS hash */
13506         rss_conf.conf.types = rss_info->conf.types & ~(conf->conf.types);
13507         i40e_rss_hash_set(pf, &rss_conf);
13508
13509         for (i = RTE_ETH_FLOW_IPV4; i <= RTE_ETH_FLOW_L2_PAYLOAD; i++) {
13510                 if (!(pf->adapter->flow_types_mask & (1ULL << i)) ||
13511                     !(conf->conf.types & (1ULL << i)))
13512                         continue;
13513
13514                 /* Configure default input set */
13515                 struct rte_eth_input_set_conf input_conf = {
13516                         .op = RTE_ETH_INPUT_SET_SELECT,
13517                         .flow_type = i,
13518                         .inset_size = 1,
13519                 };
13520                 input_conf.field[0] = RTE_ETH_INPUT_SET_DEFAULT;
13521                 i40e_hash_filter_inset_select(hw, &input_conf);
13522         }
13523
13524         rss_info->conf.types = rss_conf.conf.types;
13525
13526         i40e_rss_clear_hash_function(pf, conf);
13527
13528         return 0;
13529 }
13530
13531 /* Configure RSS queue region to default */
13532 static int
13533 i40e_rss_clear_queue_region(struct i40e_pf *pf)
13534 {
13535         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
13536         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13537         uint16_t queue[I40E_MAX_Q_PER_TC];
13538         uint32_t num_rxq, i;
13539         uint32_t lut = 0;
13540         uint16_t j, num;
13541
13542         num_rxq = RTE_MIN(pf->dev_data->nb_rx_queues, I40E_MAX_Q_PER_TC);
13543
13544         for (j = 0; j < num_rxq; j++)
13545                 queue[j] = j;
13546
13547         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
13548          * It's necessary to calculate the actual PF queues that are configured.
13549          */
13550         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
13551                 num = i40e_pf_calc_configured_queues_num(pf);
13552         else
13553                 num = pf->dev_data->nb_rx_queues;
13554
13555         num = RTE_MIN(num, num_rxq);
13556         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
13557                         num);
13558
13559         if (num == 0) {
13560                 PMD_DRV_LOG(ERR,
13561                         "No PF queues are configured to enable RSS for port %u",
13562                         pf->dev_data->port_id);
13563                 return -ENOTSUP;
13564         }
13565
13566         /* Fill in redirection table */
13567         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
13568                 if (j == num)
13569                         j = 0;
13570                 lut = (lut << 8) | (queue[j] & ((0x1 <<
13571                         hw->func_caps.rss_table_entry_width) - 1));
13572                 if ((i & 3) == 3)
13573                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
13574         }
13575
13576         rss_info->conf.queue_num = 0;
13577         memset(&rss_info->conf.queue, 0, sizeof(uint16_t));
13578
13579         return 0;
13580 }
13581
13582 int
13583 i40e_config_rss_filter(struct i40e_pf *pf,
13584                 struct i40e_rte_flow_rss_conf *conf, bool add)
13585 {
13586         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
13587         struct rte_flow_action_rss update_conf = rss_info->conf;
13588         int ret = 0;
13589
13590         if (add) {
13591                 if (conf->conf.queue_num) {
13592                         /* Configure RSS queue region */
13593                         ret = i40e_rss_config_queue_region(pf, conf);
13594                         if (ret)
13595                                 return ret;
13596
13597                         update_conf.queue_num = conf->conf.queue_num;
13598                         update_conf.queue = conf->conf.queue;
13599                 } else if (conf->conf.func ==
13600                            RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
13601                         /* Configure hash function */
13602                         ret = i40e_rss_config_hash_function(pf, conf);
13603                         if (ret)
13604                                 return ret;
13605
13606                         update_conf.func = conf->conf.func;
13607                 } else {
13608                         /* Configure hash enable and input set */
13609                         ret = i40e_rss_enable_hash(pf, conf);
13610                         if (ret)
13611                                 return ret;
13612
13613                         update_conf.types |= conf->conf.types;
13614                         update_conf.key = conf->conf.key;
13615                         update_conf.key_len = conf->conf.key_len;
13616                 }
13617
13618                 /* Update RSS info in pf */
13619                 if (i40e_rss_conf_init(rss_info, &update_conf))
13620                         return -EINVAL;
13621         } else {
13622                 if (!conf->valid)
13623                         return 0;
13624
13625                 if (conf->conf.queue_num)
13626                         i40e_rss_clear_queue_region(pf);
13627                 else if (conf->conf.func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR)
13628                         i40e_rss_clear_hash_function(pf, conf);
13629                 else
13630                         i40e_rss_disable_hash(pf, conf);
13631         }
13632
13633         return 0;
13634 }
13635
13636 RTE_LOG_REGISTER(i40e_logtype_init, pmd.net.i40e.init, NOTICE);
13637 RTE_LOG_REGISTER(i40e_logtype_driver, pmd.net.i40e.driver, NOTICE);
13638 #ifdef RTE_LIBRTE_I40E_DEBUG_RX
13639 RTE_LOG_REGISTER(i40e_logtype_rx, pmd.net.i40e.rx, DEBUG);
13640 #endif
13641 #ifdef RTE_LIBRTE_I40E_DEBUG_TX
13642 RTE_LOG_REGISTER(i40e_logtype_tx, pmd.net.i40e.tx, DEBUG);
13643 #endif
13644 #ifdef RTE_LIBRTE_I40E_DEBUG_TX_FREE
13645 RTE_LOG_REGISTER(i40e_logtype_tx_free, pmd.net.i40e.tx_free, DEBUG);
13646 #endif
13647
13648 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
13649                               ETH_I40E_FLOATING_VEB_ARG "=1"
13650                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
13651                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
13652                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
13653                               ETH_I40E_USE_LATEST_VEC "=0|1");