drivers/net/i40e/i40e_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <errno.h>
   7 #include <stdint.h>
   8 #include <string.h>
   9 #include <unistd.h>
  10 #include <stdarg.h>
  11 #include <inttypes.h>
  12 #include <assert.h>
  13
  14 #include <rte_common.h>
  15 #include <rte_eal.h>
  16 #include <rte_string_fns.h>
  17 #include <rte_pci.h>
  18 #include <rte_bus_pci.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_ethdev_pci.h>
  22 #include <rte_memzone.h>
  23 #include <rte_malloc.h>
  24 #include <rte_memcpy.h>
  25 #include <rte_alarm.h>
  26 #include <rte_dev.h>
  27 #include <rte_tailq.h>
  28 #include <rte_hash_crc.h>
  29
  30 #include "i40e_logs.h"
  31 #include "base/i40e_prototype.h"
  32 #include "base/i40e_adminq_cmd.h"
  33 #include "base/i40e_type.h"
  34 #include "base/i40e_register.h"
  35 #include "base/i40e_dcb.h"
  36 #include "i40e_ethdev.h"
  37 #include "i40e_rxtx.h"
  38 #include "i40e_pf.h"
  39 #include "i40e_regs.h"
  40 #include "rte_pmd_i40e.h"
  41
  42 #define ETH_I40E_FLOATING_VEB_ARG       "enable_floating_veb"
  43 #define ETH_I40E_FLOATING_VEB_LIST_ARG  "floating_veb_list"
  44 #define ETH_I40E_SUPPORT_MULTI_DRIVER   "support-multi-driver"
  45 #define ETH_I40E_QUEUE_NUM_PER_VF_ARG   "queue-num-per-vf"
  46 #define ETH_I40E_USE_LATEST_VEC "use-latest-supported-vec"
  47
  48 #define I40E_CLEAR_PXE_WAIT_MS     200
  49
  50 /* Maximun number of capability elements */
  51 #define I40E_MAX_CAP_ELE_NUM       128
  52
  53 /* Wait count and interval */
  54 #define I40E_CHK_Q_ENA_COUNT       1000
  55 #define I40E_CHK_Q_ENA_INTERVAL_US 1000
  56
  57 /* Maximun number of VSI */
  58 #define I40E_MAX_NUM_VSIS          (384UL)
  59
  60 #define I40E_PRE_TX_Q_CFG_WAIT_US       10 /* 10 us */
  61
  62 /* Flow control default timer */
  63 #define I40E_DEFAULT_PAUSE_TIME 0xFFFFU
  64
  65 /* Flow control enable fwd bit */
  66 #define I40E_PRTMAC_FWD_CTRL   0x00000001
  67
  68 /* Receive Packet Buffer size */
  69 #define I40E_RXPBSIZE (968 * 1024)
  70
  71 /* Kilobytes shift */
  72 #define I40E_KILOSHIFT 10
  73
  74 /* Flow control default high water */
  75 #define I40E_DEFAULT_HIGH_WATER (0xF2000 >> I40E_KILOSHIFT)
  76
  77 /* Flow control default low water */
  78 #define I40E_DEFAULT_LOW_WATER  (0xF2000 >> I40E_KILOSHIFT)
  79
  80 /* Receive Average Packet Size in Byte*/
  81 #define I40E_PACKET_AVERAGE_SIZE 128
  82
  83 /* Mask of PF interrupt causes */
  84 #define I40E_PFINT_ICR0_ENA_MASK ( \
  85                 I40E_PFINT_ICR0_ENA_ECC_ERR_MASK | \
  86                 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK | \
  87                 I40E_PFINT_ICR0_ENA_GRST_MASK | \
  88                 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK | \
  89                 I40E_PFINT_ICR0_ENA_STORM_DETECT_MASK | \
  90                 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK | \
  91                 I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK | \
  92                 I40E_PFINT_ICR0_ENA_VFLR_MASK | \
  93                 I40E_PFINT_ICR0_ENA_ADMINQ_MASK)
  94
  95 #define I40E_FLOW_TYPES ( \
  96         (1UL << RTE_ETH_FLOW_FRAG_IPV4) | \
  97         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  98         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  99         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 100         (1UL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 101         (1UL << RTE_ETH_FLOW_FRAG_IPV6) | \
 102         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 103         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 104         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 105         (1UL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 106         (1UL << RTE_ETH_FLOW_L2_PAYLOAD))
 107
 108 /* Additional timesync values. */
 109 #define I40E_PTP_40GB_INCVAL     0x0199999999ULL
 110 #define I40E_PTP_10GB_INCVAL     0x0333333333ULL
 111 #define I40E_PTP_1GB_INCVAL      0x2000000000ULL
 112 #define I40E_PRTTSYN_TSYNENA     0x80000000
 113 #define I40E_PRTTSYN_TSYNTYPE    0x0e000000
 114 #define I40E_CYCLECOUNTER_MASK   0xffffffffffffffffULL
 115
 116 /**
 117  * Below are values for writing un-exposed registers suggested
 118  * by silicon experts
 119  */
 120 /* Destination MAC address */
 121 #define I40E_REG_INSET_L2_DMAC                   0xE000000000000000ULL
 122 /* Source MAC address */
 123 #define I40E_REG_INSET_L2_SMAC                   0x1C00000000000000ULL
 124 /* Outer (S-Tag) VLAN tag in the outer L2 header */
 125 #define I40E_REG_INSET_L2_OUTER_VLAN             0x0000000004000000ULL
 126 /* Inner (C-Tag) or single VLAN tag in the outer L2 header */
 127 #define I40E_REG_INSET_L2_INNER_VLAN             0x0080000000000000ULL
 128 /* Single VLAN tag in the inner L2 header */
 129 #define I40E_REG_INSET_TUNNEL_VLAN               0x0100000000000000ULL
 130 /* Source IPv4 address */
 131 #define I40E_REG_INSET_L3_SRC_IP4                0x0001800000000000ULL
 132 /* Destination IPv4 address */
 133 #define I40E_REG_INSET_L3_DST_IP4                0x0000001800000000ULL
 134 /* Source IPv4 address for X722 */
 135 #define I40E_X722_REG_INSET_L3_SRC_IP4           0x0006000000000000ULL
 136 /* Destination IPv4 address for X722 */
 137 #define I40E_X722_REG_INSET_L3_DST_IP4           0x0000060000000000ULL
 138 /* IPv4 Protocol for X722 */
 139 #define I40E_X722_REG_INSET_L3_IP4_PROTO         0x0010000000000000ULL
 140 /* IPv4 Time to Live for X722 */
 141 #define I40E_X722_REG_INSET_L3_IP4_TTL           0x0010000000000000ULL
 142 /* IPv4 Type of Service (TOS) */
 143 #define I40E_REG_INSET_L3_IP4_TOS                0x0040000000000000ULL
 144 /* IPv4 Protocol */
 145 #define I40E_REG_INSET_L3_IP4_PROTO              0x0004000000000000ULL
 146 /* IPv4 Time to Live */
 147 #define I40E_REG_INSET_L3_IP4_TTL                0x0004000000000000ULL
 148 /* Source IPv6 address */
 149 #define I40E_REG_INSET_L3_SRC_IP6                0x0007F80000000000ULL
 150 /* Destination IPv6 address */
 151 #define I40E_REG_INSET_L3_DST_IP6                0x000007F800000000ULL
 152 /* IPv6 Traffic Class (TC) */
 153 #define I40E_REG_INSET_L3_IP6_TC                 0x0040000000000000ULL
 154 /* IPv6 Next Header */
 155 #define I40E_REG_INSET_L3_IP6_NEXT_HDR           0x0008000000000000ULL
 156 /* IPv6 Hop Limit */
 157 #define I40E_REG_INSET_L3_IP6_HOP_LIMIT          0x0008000000000000ULL
 158 /* Source L4 port */
 159 #define I40E_REG_INSET_L4_SRC_PORT               0x0000000400000000ULL
 160 /* Destination L4 port */
 161 #define I40E_REG_INSET_L4_DST_PORT               0x0000000200000000ULL
 162 /* SCTP verification tag */
 163 #define I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG  0x0000000180000000ULL
 164 /* Inner destination MAC address (MAC-in-UDP/MAC-in-GRE)*/
 165 #define I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC   0x0000000001C00000ULL
 166 /* Source port of tunneling UDP */
 167 #define I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT    0x0000000000200000ULL
 168 /* Destination port of tunneling UDP */
 169 #define I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT    0x0000000000100000ULL
 170 /* UDP Tunneling ID, NVGRE/GRE key */
 171 #define I40E_REG_INSET_TUNNEL_ID                 0x00000000000C0000ULL
 172 /* Last ether type */
 173 #define I40E_REG_INSET_LAST_ETHER_TYPE           0x0000000000004000ULL
 174 /* Tunneling outer destination IPv4 address */
 175 #define I40E_REG_INSET_TUNNEL_L3_DST_IP4         0x00000000000000C0ULL
 176 /* Tunneling outer destination IPv6 address */
 177 #define I40E_REG_INSET_TUNNEL_L3_DST_IP6         0x0000000000003FC0ULL
 178 /* 1st word of flex payload */
 179 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD1        0x0000000000002000ULL
 180 /* 2nd word of flex payload */
 181 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD2        0x0000000000001000ULL
 182 /* 3rd word of flex payload */
 183 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD3        0x0000000000000800ULL
 184 /* 4th word of flex payload */
 185 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD4        0x0000000000000400ULL
 186 /* 5th word of flex payload */
 187 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD5        0x0000000000000200ULL
 188 /* 6th word of flex payload */
 189 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD6        0x0000000000000100ULL
 190 /* 7th word of flex payload */
 191 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD7        0x0000000000000080ULL
 192 /* 8th word of flex payload */
 193 #define I40E_REG_INSET_FLEX_PAYLOAD_WORD8        0x0000000000000040ULL
 194 /* all 8 words flex payload */
 195 #define I40E_REG_INSET_FLEX_PAYLOAD_WORDS        0x0000000000003FC0ULL
 196 #define I40E_REG_INSET_MASK_DEFAULT              0x0000000000000000ULL
 197
 198 #define I40E_TRANSLATE_INSET 0
 199 #define I40E_TRANSLATE_REG   1
 200
 201 #define I40E_INSET_IPV4_TOS_MASK        0x0009FF00UL
 202 #define I40E_INSET_IPv4_TTL_MASK        0x000D00FFUL
 203 #define I40E_INSET_IPV4_PROTO_MASK      0x000DFF00UL
 204 #define I40E_INSET_IPV6_TC_MASK         0x0009F00FUL
 205 #define I40E_INSET_IPV6_HOP_LIMIT_MASK  0x000CFF00UL
 206 #define I40E_INSET_IPV6_NEXT_HDR_MASK   0x000C00FFUL
 207
 208 /* PCI offset for querying capability */
 209 #define PCI_DEV_CAP_REG            0xA4
 210 /* PCI offset for enabling/disabling Extended Tag */
 211 #define PCI_DEV_CTRL_REG           0xA8
 212 /* Bit mask of Extended Tag capability */
 213 #define PCI_DEV_CAP_EXT_TAG_MASK   0x20
 214 /* Bit shift of Extended Tag enable/disable */
 215 #define PCI_DEV_CTRL_EXT_TAG_SHIFT 8
 216 /* Bit mask of Extended Tag enable/disable */
 217 #define PCI_DEV_CTRL_EXT_TAG_MASK  (1 << PCI_DEV_CTRL_EXT_TAG_SHIFT)
 218
 219 static int eth_i40e_dev_init(struct rte_eth_dev *eth_dev, void *init_params);
 220 static int eth_i40e_dev_uninit(struct rte_eth_dev *eth_dev);
 221 static int i40e_dev_configure(struct rte_eth_dev *dev);
 222 static int i40e_dev_start(struct rte_eth_dev *dev);
 223 static void i40e_dev_stop(struct rte_eth_dev *dev);
 224 static void i40e_dev_close(struct rte_eth_dev *dev);
 225 static int  i40e_dev_reset(struct rte_eth_dev *dev);
 226 static void i40e_dev_promiscuous_enable(struct rte_eth_dev *dev);
 227 static void i40e_dev_promiscuous_disable(struct rte_eth_dev *dev);
 228 static void i40e_dev_allmulticast_enable(struct rte_eth_dev *dev);
 229 static void i40e_dev_allmulticast_disable(struct rte_eth_dev *dev);
 230 static int i40e_dev_set_link_up(struct rte_eth_dev *dev);
 231 static int i40e_dev_set_link_down(struct rte_eth_dev *dev);
 232 static int i40e_dev_stats_get(struct rte_eth_dev *dev,
 233                                struct rte_eth_stats *stats);
 234 static int i40e_dev_xstats_get(struct rte_eth_dev *dev,
 235                                struct rte_eth_xstat *xstats, unsigned n);
 236 static int i40e_dev_xstats_get_names(struct rte_eth_dev *dev,
 237                                      struct rte_eth_xstat_name *xstats_names,
 238                                      unsigned limit);
 239 static void i40e_dev_stats_reset(struct rte_eth_dev *dev);
 240 static int i40e_dev_queue_stats_mapping_set(struct rte_eth_dev *dev,
 241                                             uint16_t queue_id,
 242                                             uint8_t stat_idx,
 243                                             uint8_t is_rx);
 244 static int i40e_fw_version_get(struct rte_eth_dev *dev,
 245                                 char *fw_version, size_t fw_size);
 246 static void i40e_dev_info_get(struct rte_eth_dev *dev,
 247                               struct rte_eth_dev_info *dev_info);
 248 static int i40e_vlan_filter_set(struct rte_eth_dev *dev,
 249                                 uint16_t vlan_id,
 250                                 int on);
 251 static int i40e_vlan_tpid_set(struct rte_eth_dev *dev,
 252                               enum rte_vlan_type vlan_type,
 253                               uint16_t tpid);
 254 static int i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 255 static void i40e_vlan_strip_queue_set(struct rte_eth_dev *dev,
 256                                       uint16_t queue,
 257                                       int on);
 258 static int i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on);
 259 static int i40e_dev_led_on(struct rte_eth_dev *dev);
 260 static int i40e_dev_led_off(struct rte_eth_dev *dev);
 261 static int i40e_flow_ctrl_get(struct rte_eth_dev *dev,
 262                               struct rte_eth_fc_conf *fc_conf);
 263 static int i40e_flow_ctrl_set(struct rte_eth_dev *dev,
 264                               struct rte_eth_fc_conf *fc_conf);
 265 static int i40e_priority_flow_ctrl_set(struct rte_eth_dev *dev,
 266                                        struct rte_eth_pfc_conf *pfc_conf);
 267 static int i40e_macaddr_add(struct rte_eth_dev *dev,
 268                             struct rte_ether_addr *mac_addr,
 269                             uint32_t index,
 270                             uint32_t pool);
 271 static void i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 272 static int i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
 273                                     struct rte_eth_rss_reta_entry64 *reta_conf,
 274                                     uint16_t reta_size);
 275 static int i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
 276                                    struct rte_eth_rss_reta_entry64 *reta_conf,
 277                                    uint16_t reta_size);
 278
 279 static int i40e_get_cap(struct i40e_hw *hw);
 280 static int i40e_pf_parameter_init(struct rte_eth_dev *dev);
 281 static int i40e_pf_setup(struct i40e_pf *pf);
 282 static int i40e_dev_rxtx_init(struct i40e_pf *pf);
 283 static int i40e_vmdq_setup(struct rte_eth_dev *dev);
 284 static int i40e_dcb_setup(struct rte_eth_dev *dev);
 285 static void i40e_stat_update_32(struct i40e_hw *hw, uint32_t reg,
 286                 bool offset_loaded, uint64_t *offset, uint64_t *stat);
 287 static void i40e_stat_update_48(struct i40e_hw *hw,
 288                                uint32_t hireg,
 289                                uint32_t loreg,
 290                                bool offset_loaded,
 291                                uint64_t *offset,
 292                                uint64_t *stat);
 293 static void i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue);
 294 static void i40e_dev_interrupt_handler(void *param);
 295 static void i40e_dev_alarm_handler(void *param);
 296 static int i40e_res_pool_init(struct i40e_res_pool_info *pool,
 297                                 uint32_t base, uint32_t num);
 298 static void i40e_res_pool_destroy(struct i40e_res_pool_info *pool);
 299 static int i40e_res_pool_free(struct i40e_res_pool_info *pool,
 300                         uint32_t base);
 301 static int i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
 302                         uint16_t num);
 303 static int i40e_dev_init_vlan(struct rte_eth_dev *dev);
 304 static int i40e_veb_release(struct i40e_veb *veb);
 305 static struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf,
 306                                                 struct i40e_vsi *vsi);
 307 static int i40e_pf_config_mq_rx(struct i40e_pf *pf);
 308 static int i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on);
 309 static inline int i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
 310                                              struct i40e_macvlan_filter *mv_f,
 311                                              int num,
 312                                              uint16_t vlan);
 313 static int i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi);
 314 static int i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
 315                                     struct rte_eth_rss_conf *rss_conf);
 316 static int i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 317                                       struct rte_eth_rss_conf *rss_conf);
 318 static int i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 319                                         struct rte_eth_udp_tunnel *udp_tunnel);
 320 static int i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 321                                         struct rte_eth_udp_tunnel *udp_tunnel);
 322 static void i40e_filter_input_set_init(struct i40e_pf *pf);
 323 static int i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
 324                                 enum rte_filter_op filter_op,
 325                                 void *arg);
 326 static int i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
 327                                 enum rte_filter_type filter_type,
 328                                 enum rte_filter_op filter_op,
 329                                 void *arg);
 330 static int i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
 331                                   struct rte_eth_dcb_info *dcb_info);
 332 static int i40e_dev_sync_phy_type(struct i40e_hw *hw);
 333 static void i40e_configure_registers(struct i40e_hw *hw);
 334 static void i40e_hw_init(struct rte_eth_dev *dev);
 335 static int i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi);
 336 static enum i40e_status_code i40e_aq_del_mirror_rule(struct i40e_hw *hw,
 337                                                      uint16_t seid,
 338                                                      uint16_t rule_type,
 339                                                      uint16_t *entries,
 340                                                      uint16_t count,
 341                                                      uint16_t rule_id);
 342 static int i40e_mirror_rule_set(struct rte_eth_dev *dev,
 343                         struct rte_eth_mirror_conf *mirror_conf,
 344                         uint8_t sw_id, uint8_t on);
 345 static int i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id);
 346
 347 static int i40e_timesync_enable(struct rte_eth_dev *dev);
 348 static int i40e_timesync_disable(struct rte_eth_dev *dev);
 349 static int i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
 350                                            struct timespec *timestamp,
 351                                            uint32_t flags);
 352 static int i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
 353                                            struct timespec *timestamp);
 354 static void i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw);
 355
 356 static int i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta);
 357
 358 static int i40e_timesync_read_time(struct rte_eth_dev *dev,
 359                                    struct timespec *timestamp);
 360 static int i40e_timesync_write_time(struct rte_eth_dev *dev,
 361                                     const struct timespec *timestamp);
 362
 363 static int i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev,
 364                                          uint16_t queue_id);
 365 static int i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev,
 366                                           uint16_t queue_id);
 367
 368 static int i40e_get_regs(struct rte_eth_dev *dev,
 369                          struct rte_dev_reg_info *regs);
 370
 371 static int i40e_get_eeprom_length(struct rte_eth_dev *dev);
 372
 373 static int i40e_get_eeprom(struct rte_eth_dev *dev,
 374                            struct rte_dev_eeprom_info *eeprom);
 375
 376 static int i40e_get_module_info(struct rte_eth_dev *dev,
 377                                 struct rte_eth_dev_module_info *modinfo);
 378 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
 379                                   struct rte_dev_eeprom_info *info);
 380
 381 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
 382                                       struct rte_ether_addr *mac_addr);
 383
 384 static int i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 385
 386 static int i40e_ethertype_filter_convert(
 387         const struct rte_eth_ethertype_filter *input,
 388         struct i40e_ethertype_filter *filter);
 389 static int i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
 390                                    struct i40e_ethertype_filter *filter);
 391
 392 static int i40e_tunnel_filter_convert(
 393         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
 394         struct i40e_tunnel_filter *tunnel_filter);
 395 static int i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
 396                                 struct i40e_tunnel_filter *tunnel_filter);
 397 static int i40e_cloud_filter_qinq_create(struct i40e_pf *pf);
 398
 399 static void i40e_ethertype_filter_restore(struct i40e_pf *pf);
 400 static void i40e_tunnel_filter_restore(struct i40e_pf *pf);
 401 static void i40e_filter_restore(struct i40e_pf *pf);
 402 static void i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev);
 403
 404 int i40e_logtype_init;
 405 int i40e_logtype_driver;
 406
 407 static const char *const valid_keys[] = {
 408         ETH_I40E_FLOATING_VEB_ARG,
 409         ETH_I40E_FLOATING_VEB_LIST_ARG,
 410         ETH_I40E_SUPPORT_MULTI_DRIVER,
 411         ETH_I40E_QUEUE_NUM_PER_VF_ARG,
 412         ETH_I40E_USE_LATEST_VEC,
 413         NULL};
 414
 415 static const struct rte_pci_id pci_id_i40e_map[] = {
 416         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_XL710) },
 417         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QEMU) },
 418         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_B) },
 419         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_C) },
 420         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_A) },
 421         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_B) },
 422         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_C) },
 423         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T) },
 424         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2) },
 425         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_20G_KR2_A) },
 426         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T4) },
 427         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_B) },
 428         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_25G_SFP28) },
 429         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0) },
 430         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_KX_X722) },
 431         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_QSFP_X722) },
 432         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_X722) },
 433         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_1G_BASE_T_X722) },
 434         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_X722) },
 435         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_SFP_I_X722) },
 436         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X710_N3000) },
 437         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_XXV710_N3000) },
 438         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_10G_BASE_T_BC) },
 439         { .vendor_id = 0, /* sentinel */ },
 440 };
 441
 442 static const struct eth_dev_ops i40e_eth_dev_ops = {
 443         .dev_configure                = i40e_dev_configure,
 444         .dev_start                    = i40e_dev_start,
 445         .dev_stop                     = i40e_dev_stop,
 446         .dev_close                    = i40e_dev_close,
 447         .dev_reset                    = i40e_dev_reset,
 448         .promiscuous_enable           = i40e_dev_promiscuous_enable,
 449         .promiscuous_disable          = i40e_dev_promiscuous_disable,
 450         .allmulticast_enable          = i40e_dev_allmulticast_enable,
 451         .allmulticast_disable         = i40e_dev_allmulticast_disable,
 452         .dev_set_link_up              = i40e_dev_set_link_up,
 453         .dev_set_link_down            = i40e_dev_set_link_down,
 454         .link_update                  = i40e_dev_link_update,
 455         .stats_get                    = i40e_dev_stats_get,
 456         .xstats_get                   = i40e_dev_xstats_get,
 457         .xstats_get_names             = i40e_dev_xstats_get_names,
 458         .stats_reset                  = i40e_dev_stats_reset,
 459         .xstats_reset                 = i40e_dev_stats_reset,
 460         .queue_stats_mapping_set      = i40e_dev_queue_stats_mapping_set,
 461         .fw_version_get               = i40e_fw_version_get,
 462         .dev_infos_get                = i40e_dev_info_get,
 463         .dev_supported_ptypes_get     = i40e_dev_supported_ptypes_get,
 464         .vlan_filter_set              = i40e_vlan_filter_set,
 465         .vlan_tpid_set                = i40e_vlan_tpid_set,
 466         .vlan_offload_set             = i40e_vlan_offload_set,
 467         .vlan_strip_queue_set         = i40e_vlan_strip_queue_set,
 468         .vlan_pvid_set                = i40e_vlan_pvid_set,
 469         .rx_queue_start               = i40e_dev_rx_queue_start,
 470         .rx_queue_stop                = i40e_dev_rx_queue_stop,
 471         .tx_queue_start               = i40e_dev_tx_queue_start,
 472         .tx_queue_stop                = i40e_dev_tx_queue_stop,
 473         .rx_queue_setup               = i40e_dev_rx_queue_setup,
 474         .rx_queue_intr_enable         = i40e_dev_rx_queue_intr_enable,
 475         .rx_queue_intr_disable        = i40e_dev_rx_queue_intr_disable,
 476         .rx_queue_release             = i40e_dev_rx_queue_release,
 477         .rx_queue_count               = i40e_dev_rx_queue_count,
 478         .rx_descriptor_done           = i40e_dev_rx_descriptor_done,
 479         .rx_descriptor_status         = i40e_dev_rx_descriptor_status,
 480         .tx_descriptor_status         = i40e_dev_tx_descriptor_status,
 481         .tx_queue_setup               = i40e_dev_tx_queue_setup,
 482         .tx_queue_release             = i40e_dev_tx_queue_release,
 483         .dev_led_on                   = i40e_dev_led_on,
 484         .dev_led_off                  = i40e_dev_led_off,
 485         .flow_ctrl_get                = i40e_flow_ctrl_get,
 486         .flow_ctrl_set                = i40e_flow_ctrl_set,
 487         .priority_flow_ctrl_set       = i40e_priority_flow_ctrl_set,
 488         .mac_addr_add                 = i40e_macaddr_add,
 489         .mac_addr_remove              = i40e_macaddr_remove,
 490         .reta_update                  = i40e_dev_rss_reta_update,
 491         .reta_query                   = i40e_dev_rss_reta_query,
 492         .rss_hash_update              = i40e_dev_rss_hash_update,
 493         .rss_hash_conf_get            = i40e_dev_rss_hash_conf_get,
 494         .udp_tunnel_port_add          = i40e_dev_udp_tunnel_port_add,
 495         .udp_tunnel_port_del          = i40e_dev_udp_tunnel_port_del,
 496         .filter_ctrl                  = i40e_dev_filter_ctrl,
 497         .rxq_info_get                 = i40e_rxq_info_get,
 498         .txq_info_get                 = i40e_txq_info_get,
 499         .mirror_rule_set              = i40e_mirror_rule_set,
 500         .mirror_rule_reset            = i40e_mirror_rule_reset,
 501         .timesync_enable              = i40e_timesync_enable,
 502         .timesync_disable             = i40e_timesync_disable,
 503         .timesync_read_rx_timestamp   = i40e_timesync_read_rx_timestamp,
 504         .timesync_read_tx_timestamp   = i40e_timesync_read_tx_timestamp,
 505         .get_dcb_info                 = i40e_dev_get_dcb_info,
 506         .timesync_adjust_time         = i40e_timesync_adjust_time,
 507         .timesync_read_time           = i40e_timesync_read_time,
 508         .timesync_write_time          = i40e_timesync_write_time,
 509         .get_reg                      = i40e_get_regs,
 510         .get_eeprom_length            = i40e_get_eeprom_length,
 511         .get_eeprom                   = i40e_get_eeprom,
 512         .get_module_info              = i40e_get_module_info,
 513         .get_module_eeprom            = i40e_get_module_eeprom,
 514         .mac_addr_set                 = i40e_set_default_mac_addr,
 515         .mtu_set                      = i40e_dev_mtu_set,
 516         .tm_ops_get                   = i40e_tm_ops_get,
 517 };
 518
 519 /* store statistics names and its offset in stats structure */
 520 struct rte_i40e_xstats_name_off {
 521         char name[RTE_ETH_XSTATS_NAME_SIZE];
 522         unsigned offset;
 523 };
 524
 525 static const struct rte_i40e_xstats_name_off rte_i40e_stats_strings[] = {
 526         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 527         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 528         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 529         {"rx_dropped", offsetof(struct i40e_eth_stats, rx_discards)},
 530         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 531                 rx_unknown_protocol)},
 532         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 533         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 534         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 535         {"tx_dropped", offsetof(struct i40e_eth_stats, tx_discards)},
 536 };
 537
 538 #define I40E_NB_ETH_XSTATS (sizeof(rte_i40e_stats_strings) / \
 539                 sizeof(rte_i40e_stats_strings[0]))
 540
 541 static const struct rte_i40e_xstats_name_off rte_i40e_hw_port_strings[] = {
 542         {"tx_link_down_dropped", offsetof(struct i40e_hw_port_stats,
 543                 tx_dropped_link_down)},
 544         {"rx_crc_errors", offsetof(struct i40e_hw_port_stats, crc_errors)},
 545         {"rx_illegal_byte_errors", offsetof(struct i40e_hw_port_stats,
 546                 illegal_bytes)},
 547         {"rx_error_bytes", offsetof(struct i40e_hw_port_stats, error_bytes)},
 548         {"mac_local_errors", offsetof(struct i40e_hw_port_stats,
 549                 mac_local_faults)},
 550         {"mac_remote_errors", offsetof(struct i40e_hw_port_stats,
 551                 mac_remote_faults)},
 552         {"rx_length_errors", offsetof(struct i40e_hw_port_stats,
 553                 rx_length_errors)},
 554         {"tx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_tx)},
 555         {"rx_xon_packets", offsetof(struct i40e_hw_port_stats, link_xon_rx)},
 556         {"tx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_tx)},
 557         {"rx_xoff_packets", offsetof(struct i40e_hw_port_stats, link_xoff_rx)},
 558         {"rx_size_64_packets", offsetof(struct i40e_hw_port_stats, rx_size_64)},
 559         {"rx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 560                 rx_size_127)},
 561         {"rx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 562                 rx_size_255)},
 563         {"rx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 564                 rx_size_511)},
 565         {"rx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 566                 rx_size_1023)},
 567         {"rx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 568                 rx_size_1522)},
 569         {"rx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 570                 rx_size_big)},
 571         {"rx_undersized_errors", offsetof(struct i40e_hw_port_stats,
 572                 rx_undersize)},
 573         {"rx_oversize_errors", offsetof(struct i40e_hw_port_stats,
 574                 rx_oversize)},
 575         {"rx_mac_short_dropped", offsetof(struct i40e_hw_port_stats,
 576                 mac_short_packet_dropped)},
 577         {"rx_fragmented_errors", offsetof(struct i40e_hw_port_stats,
 578                 rx_fragments)},
 579         {"rx_jabber_errors", offsetof(struct i40e_hw_port_stats, rx_jabber)},
 580         {"tx_size_64_packets", offsetof(struct i40e_hw_port_stats, tx_size_64)},
 581         {"tx_size_65_to_127_packets", offsetof(struct i40e_hw_port_stats,
 582                 tx_size_127)},
 583         {"tx_size_128_to_255_packets", offsetof(struct i40e_hw_port_stats,
 584                 tx_size_255)},
 585         {"tx_size_256_to_511_packets", offsetof(struct i40e_hw_port_stats,
 586                 tx_size_511)},
 587         {"tx_size_512_to_1023_packets", offsetof(struct i40e_hw_port_stats,
 588                 tx_size_1023)},
 589         {"tx_size_1024_to_1522_packets", offsetof(struct i40e_hw_port_stats,
 590                 tx_size_1522)},
 591         {"tx_size_1523_to_max_packets", offsetof(struct i40e_hw_port_stats,
 592                 tx_size_big)},
 593         {"rx_flow_director_atr_match_packets",
 594                 offsetof(struct i40e_hw_port_stats, fd_atr_match)},
 595         {"rx_flow_director_sb_match_packets",
 596                 offsetof(struct i40e_hw_port_stats, fd_sb_match)},
 597         {"tx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 598                 tx_lpi_status)},
 599         {"rx_low_power_idle_status", offsetof(struct i40e_hw_port_stats,
 600                 rx_lpi_status)},
 601         {"tx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 602                 tx_lpi_count)},
 603         {"rx_low_power_idle_count", offsetof(struct i40e_hw_port_stats,
 604                 rx_lpi_count)},
 605 };
 606
 607 #define I40E_NB_HW_PORT_XSTATS (sizeof(rte_i40e_hw_port_strings) / \
 608                 sizeof(rte_i40e_hw_port_strings[0]))
 609
 610 static const struct rte_i40e_xstats_name_off rte_i40e_rxq_prio_strings[] = {
 611         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 612                 priority_xon_rx)},
 613         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 614                 priority_xoff_rx)},
 615 };
 616
 617 #define I40E_NB_RXQ_PRIO_XSTATS (sizeof(rte_i40e_rxq_prio_strings) / \
 618                 sizeof(rte_i40e_rxq_prio_strings[0]))
 619
 620 static const struct rte_i40e_xstats_name_off rte_i40e_txq_prio_strings[] = {
 621         {"xon_packets", offsetof(struct i40e_hw_port_stats,
 622                 priority_xon_tx)},
 623         {"xoff_packets", offsetof(struct i40e_hw_port_stats,
 624                 priority_xoff_tx)},
 625         {"xon_to_xoff_packets", offsetof(struct i40e_hw_port_stats,
 626                 priority_xon_2_xoff)},
 627 };
 628
 629 #define I40E_NB_TXQ_PRIO_XSTATS (sizeof(rte_i40e_txq_prio_strings) / \
 630                 sizeof(rte_i40e_txq_prio_strings[0]))
 631
 632 static int
 633 eth_i40e_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
 634         struct rte_pci_device *pci_dev)
 635 {
 636         char name[RTE_ETH_NAME_MAX_LEN];
 637         struct rte_eth_devargs eth_da = { .nb_representor_ports = 0 };
 638         int i, retval;
 639
 640         if (pci_dev->device.devargs) {
 641                 retval = rte_eth_devargs_parse(pci_dev->device.devargs->args,
 642                                 &eth_da);
 643                 if (retval)
 644                         return retval;
 645         }
 646
 647         retval = rte_eth_dev_create(&pci_dev->device, pci_dev->device.name,
 648                 sizeof(struct i40e_adapter),
 649                 eth_dev_pci_specific_init, pci_dev,
 650                 eth_i40e_dev_init, NULL);
 651
 652         if (retval || eth_da.nb_representor_ports < 1)
 653                 return retval;
 654
 655         /* probe VF representor ports */
 656         struct rte_eth_dev *pf_ethdev = rte_eth_dev_allocated(
 657                 pci_dev->device.name);
 658
 659         if (pf_ethdev == NULL)
 660                 return -ENODEV;
 661
 662         for (i = 0; i < eth_da.nb_representor_ports; i++) {
 663                 struct i40e_vf_representor representor = {
 664                         .vf_id = eth_da.representor_ports[i],
 665                         .switch_domain_id = I40E_DEV_PRIVATE_TO_PF(
 666                                 pf_ethdev->data->dev_private)->switch_domain_id,
 667                         .adapter = I40E_DEV_PRIVATE_TO_ADAPTER(
 668                                 pf_ethdev->data->dev_private)
 669                 };
 670
 671                 /* representor port net_bdf_port */
 672                 snprintf(name, sizeof(name), "net_%s_representor_%d",
 673                         pci_dev->device.name, eth_da.representor_ports[i]);
 674
 675                 retval = rte_eth_dev_create(&pci_dev->device, name,
 676                         sizeof(struct i40e_vf_representor), NULL, NULL,
 677                         i40e_vf_representor_init, &representor);
 678
 679                 if (retval)
 680                         PMD_DRV_LOG(ERR, "failed to create i40e vf "
 681                                 "representor %s.", name);
 682         }
 683
 684         return 0;
 685 }
 686
 687 static int eth_i40e_pci_remove(struct rte_pci_device *pci_dev)
 688 {
 689         struct rte_eth_dev *ethdev;
 690
 691         ethdev = rte_eth_dev_allocated(pci_dev->device.name);
 692         if (!ethdev)
 693                 return -ENODEV;
 694
 695
 696         if (ethdev->data->dev_flags & RTE_ETH_DEV_REPRESENTOR)
 697                 return rte_eth_dev_destroy(ethdev, i40e_vf_representor_uninit);
 698         else
 699                 return rte_eth_dev_destroy(ethdev, eth_i40e_dev_uninit);
 700 }
 701
 702 static struct rte_pci_driver rte_i40e_pmd = {
 703         .id_table = pci_id_i40e_map,
 704         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
 705                      RTE_PCI_DRV_IOVA_AS_VA,
 706         .probe = eth_i40e_pci_probe,
 707         .remove = eth_i40e_pci_remove,
 708 };
 709
 710 static inline void
 711 i40e_write_global_rx_ctl(struct i40e_hw *hw, uint32_t reg_addr,
 712                          uint32_t reg_val)
 713 {
 714         uint32_t ori_reg_val;
 715         struct rte_eth_dev *dev;
 716
 717         ori_reg_val = i40e_read_rx_ctl(hw, reg_addr);
 718         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
 719         i40e_write_rx_ctl(hw, reg_addr, reg_val);
 720         if (ori_reg_val != reg_val)
 721                 PMD_DRV_LOG(WARNING,
 722                             "i40e device %s changed global register [0x%08x]."
 723                             " original: 0x%08x, new: 0x%08x",
 724                             dev->device->name, reg_addr, ori_reg_val, reg_val);
 725 }
 726
 727 RTE_PMD_REGISTER_PCI(net_i40e, rte_i40e_pmd);
 728 RTE_PMD_REGISTER_PCI_TABLE(net_i40e, pci_id_i40e_map);
 729 RTE_PMD_REGISTER_KMOD_DEP(net_i40e, "* igb_uio | uio_pci_generic | vfio-pci");
 730
 731 #ifndef I40E_GLQF_ORT
 732 #define I40E_GLQF_ORT(_i)    (0x00268900 + ((_i) * 4))
 733 #endif
 734 #ifndef I40E_GLQF_PIT
 735 #define I40E_GLQF_PIT(_i)    (0x00268C80 + ((_i) * 4))
 736 #endif
 737 #ifndef I40E_GLQF_L3_MAP
 738 #define I40E_GLQF_L3_MAP(_i) (0x0026C700 + ((_i) * 4))
 739 #endif
 740
 741 static inline void i40e_GLQF_reg_init(struct i40e_hw *hw)
 742 {
 743         /*
 744          * Initialize registers for parsing packet type of QinQ
 745          * This should be removed from code once proper
 746          * configuration API is added to avoid configuration conflicts
 747          * between ports of the same device.
 748          */
 749         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(40), 0x00000029);
 750         I40E_WRITE_GLB_REG(hw, I40E_GLQF_PIT(9), 0x00009420);
 751 }
 752
 753 static inline void i40e_config_automask(struct i40e_pf *pf)
 754 {
 755         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 756         uint32_t val;
 757
 758         /* INTENA flag is not auto-cleared for interrupt */
 759         val = I40E_READ_REG(hw, I40E_GLINT_CTL);
 760         val |= I40E_GLINT_CTL_DIS_AUTOMASK_PF0_MASK |
 761                 I40E_GLINT_CTL_DIS_AUTOMASK_VF0_MASK;
 762
 763         /* If support multi-driver, PF will use INT0. */
 764         if (!pf->support_multi_driver)
 765                 val |= I40E_GLINT_CTL_DIS_AUTOMASK_N_MASK;
 766
 767         I40E_WRITE_REG(hw, I40E_GLINT_CTL, val);
 768 }
 769
 770 #define I40E_FLOW_CONTROL_ETHERTYPE  0x8808
 771
 772 /*
 773  * Add a ethertype filter to drop all flow control frames transmitted
 774  * from VSIs.
 775 */
 776 static void
 777 i40e_add_tx_flow_control_drop_filter(struct i40e_pf *pf)
 778 {
 779         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 780         uint16_t flags = I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC |
 781                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP |
 782                         I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX;
 783         int ret;
 784
 785         ret = i40e_aq_add_rem_control_packet_filter(hw, NULL,
 786                                 I40E_FLOW_CONTROL_ETHERTYPE, flags,
 787                                 pf->main_vsi_seid, 0,
 788                                 TRUE, NULL, NULL);
 789         if (ret)
 790                 PMD_INIT_LOG(ERR,
 791                         "Failed to add filter to drop flow control frames from VSIs.");
 792 }
 793
 794 static int
 795 floating_veb_list_handler(__rte_unused const char *key,
 796                           const char *floating_veb_value,
 797                           void *opaque)
 798 {
 799         int idx = 0;
 800         unsigned int count = 0;
 801         char *end = NULL;
 802         int min, max;
 803         bool *vf_floating_veb = opaque;
 804
 805         while (isblank(*floating_veb_value))
 806                 floating_veb_value++;
 807
 808         /* Reset floating VEB configuration for VFs */
 809         for (idx = 0; idx < I40E_MAX_VF; idx++)
 810                 vf_floating_veb[idx] = false;
 811
 812         min = I40E_MAX_VF;
 813         do {
 814                 while (isblank(*floating_veb_value))
 815                         floating_veb_value++;
 816                 if (*floating_veb_value == '\0')
 817                         return -1;
 818                 errno = 0;
 819                 idx = strtoul(floating_veb_value, &end, 10);
 820                 if (errno || end == NULL)
 821                         return -1;
 822                 while (isblank(*end))
 823                         end++;
 824                 if (*end == '-') {
 825                         min = idx;
 826                 } else if ((*end == ';') || (*end == '\0')) {
 827                         max = idx;
 828                         if (min == I40E_MAX_VF)
 829                                 min = idx;
 830                         if (max >= I40E_MAX_VF)
 831                                 max = I40E_MAX_VF - 1;
 832                         for (idx = min; idx <= max; idx++) {
 833                                 vf_floating_veb[idx] = true;
 834                                 count++;
 835                         }
 836                         min = I40E_MAX_VF;
 837                 } else {
 838                         return -1;
 839                 }
 840                 floating_veb_value = end + 1;
 841         } while (*end != '\0');
 842
 843         if (count == 0)
 844                 return -1;
 845
 846         return 0;
 847 }
 848
 849 static void
 850 config_vf_floating_veb(struct rte_devargs *devargs,
 851                        uint16_t floating_veb,
 852                        bool *vf_floating_veb)
 853 {
 854         struct rte_kvargs *kvlist;
 855         int i;
 856         const char *floating_veb_list = ETH_I40E_FLOATING_VEB_LIST_ARG;
 857
 858         if (!floating_veb)
 859                 return;
 860         /* All the VFs attach to the floating VEB by default
 861          * when the floating VEB is enabled.
 862          */
 863         for (i = 0; i < I40E_MAX_VF; i++)
 864                 vf_floating_veb[i] = true;
 865
 866         if (devargs == NULL)
 867                 return;
 868
 869         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 870         if (kvlist == NULL)
 871                 return;
 872
 873         if (!rte_kvargs_count(kvlist, floating_veb_list)) {
 874                 rte_kvargs_free(kvlist);
 875                 return;
 876         }
 877         /* When the floating_veb_list parameter exists, all the VFs
 878          * will attach to the legacy VEB firstly, then configure VFs
 879          * to the floating VEB according to the floating_veb_list.
 880          */
 881         if (rte_kvargs_process(kvlist, floating_veb_list,
 882                                floating_veb_list_handler,
 883                                vf_floating_veb) < 0) {
 884                 rte_kvargs_free(kvlist);
 885                 return;
 886         }
 887         rte_kvargs_free(kvlist);
 888 }
 889
 890 static int
 891 i40e_check_floating_handler(__rte_unused const char *key,
 892                             const char *value,
 893                             __rte_unused void *opaque)
 894 {
 895         if (strcmp(value, "1"))
 896                 return -1;
 897
 898         return 0;
 899 }
 900
 901 static int
 902 is_floating_veb_supported(struct rte_devargs *devargs)
 903 {
 904         struct rte_kvargs *kvlist;
 905         const char *floating_veb_key = ETH_I40E_FLOATING_VEB_ARG;
 906
 907         if (devargs == NULL)
 908                 return 0;
 909
 910         kvlist = rte_kvargs_parse(devargs->args, valid_keys);
 911         if (kvlist == NULL)
 912                 return 0;
 913
 914         if (!rte_kvargs_count(kvlist, floating_veb_key)) {
 915                 rte_kvargs_free(kvlist);
 916                 return 0;
 917         }
 918         /* Floating VEB is enabled when there's key-value:
 919          * enable_floating_veb=1
 920          */
 921         if (rte_kvargs_process(kvlist, floating_veb_key,
 922                                i40e_check_floating_handler, NULL) < 0) {
 923                 rte_kvargs_free(kvlist);
 924                 return 0;
 925         }
 926         rte_kvargs_free(kvlist);
 927
 928         return 1;
 929 }
 930
 931 static void
 932 config_floating_veb(struct rte_eth_dev *dev)
 933 {
 934         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 935         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 936         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 937
 938         memset(pf->floating_veb_list, 0, sizeof(pf->floating_veb_list));
 939
 940         if (hw->aq.fw_maj_ver >= FLOATING_VEB_SUPPORTED_FW_MAJ) {
 941                 pf->floating_veb =
 942                         is_floating_veb_supported(pci_dev->device.devargs);
 943                 config_vf_floating_veb(pci_dev->device.devargs,
 944                                        pf->floating_veb,
 945                                        pf->floating_veb_list);
 946         } else {
 947                 pf->floating_veb = false;
 948         }
 949 }
 950
 951 #define I40E_L2_TAGS_S_TAG_SHIFT 1
 952 #define I40E_L2_TAGS_S_TAG_MASK I40E_MASK(0x1, I40E_L2_TAGS_S_TAG_SHIFT)
 953
 954 static int
 955 i40e_init_ethtype_filter_list(struct rte_eth_dev *dev)
 956 {
 957         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 958         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
 959         char ethertype_hash_name[RTE_HASH_NAMESIZE];
 960         int ret;
 961
 962         struct rte_hash_parameters ethertype_hash_params = {
 963                 .name = ethertype_hash_name,
 964                 .entries = I40E_MAX_ETHERTYPE_FILTER_NUM,
 965                 .key_len = sizeof(struct i40e_ethertype_filter_input),
 966                 .hash_func = rte_hash_crc,
 967                 .hash_func_init_val = 0,
 968                 .socket_id = rte_socket_id(),
 969         };
 970
 971         /* Initialize ethertype filter rule list and hash */
 972         TAILQ_INIT(&ethertype_rule->ethertype_list);
 973         snprintf(ethertype_hash_name, RTE_HASH_NAMESIZE,
 974                  "ethertype_%s", dev->device->name);
 975         ethertype_rule->hash_table = rte_hash_create(&ethertype_hash_params);
 976         if (!ethertype_rule->hash_table) {
 977                 PMD_INIT_LOG(ERR, "Failed to create ethertype hash table!");
 978                 return -EINVAL;
 979         }
 980         ethertype_rule->hash_map = rte_zmalloc("i40e_ethertype_hash_map",
 981                                        sizeof(struct i40e_ethertype_filter *) *
 982                                        I40E_MAX_ETHERTYPE_FILTER_NUM,
 983                                        0);
 984         if (!ethertype_rule->hash_map) {
 985                 PMD_INIT_LOG(ERR,
 986                              "Failed to allocate memory for ethertype hash map!");
 987                 ret = -ENOMEM;
 988                 goto err_ethertype_hash_map_alloc;
 989         }
 990
 991         return 0;
 992
 993 err_ethertype_hash_map_alloc:
 994         rte_hash_free(ethertype_rule->hash_table);
 995
 996         return ret;
 997 }
 998
 999 static int
1000 i40e_init_tunnel_filter_list(struct rte_eth_dev *dev)
1001 {
1002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1003         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
1004         char tunnel_hash_name[RTE_HASH_NAMESIZE];
1005         int ret;
1006
1007         struct rte_hash_parameters tunnel_hash_params = {
1008                 .name = tunnel_hash_name,
1009                 .entries = I40E_MAX_TUNNEL_FILTER_NUM,
1010                 .key_len = sizeof(struct i40e_tunnel_filter_input),
1011                 .hash_func = rte_hash_crc,
1012                 .hash_func_init_val = 0,
1013                 .socket_id = rte_socket_id(),
1014         };
1015
1016         /* Initialize tunnel filter rule list and hash */
1017         TAILQ_INIT(&tunnel_rule->tunnel_list);
1018         snprintf(tunnel_hash_name, RTE_HASH_NAMESIZE,
1019                  "tunnel_%s", dev->device->name);
1020         tunnel_rule->hash_table = rte_hash_create(&tunnel_hash_params);
1021         if (!tunnel_rule->hash_table) {
1022                 PMD_INIT_LOG(ERR, "Failed to create tunnel hash table!");
1023                 return -EINVAL;
1024         }
1025         tunnel_rule->hash_map = rte_zmalloc("i40e_tunnel_hash_map",
1026                                     sizeof(struct i40e_tunnel_filter *) *
1027                                     I40E_MAX_TUNNEL_FILTER_NUM,
1028                                     0);
1029         if (!tunnel_rule->hash_map) {
1030                 PMD_INIT_LOG(ERR,
1031                              "Failed to allocate memory for tunnel hash map!");
1032                 ret = -ENOMEM;
1033                 goto err_tunnel_hash_map_alloc;
1034         }
1035
1036         return 0;
1037
1038 err_tunnel_hash_map_alloc:
1039         rte_hash_free(tunnel_rule->hash_table);
1040
1041         return ret;
1042 }
1043
1044 static int
1045 i40e_init_fdir_filter_list(struct rte_eth_dev *dev)
1046 {
1047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1048         struct i40e_fdir_info *fdir_info = &pf->fdir;
1049         char fdir_hash_name[RTE_HASH_NAMESIZE];
1050         int ret;
1051
1052         struct rte_hash_parameters fdir_hash_params = {
1053                 .name = fdir_hash_name,
1054                 .entries = I40E_MAX_FDIR_FILTER_NUM,
1055                 .key_len = sizeof(struct i40e_fdir_input),
1056                 .hash_func = rte_hash_crc,
1057                 .hash_func_init_val = 0,
1058                 .socket_id = rte_socket_id(),
1059         };
1060
1061         /* Initialize flow director filter rule list and hash */
1062         TAILQ_INIT(&fdir_info->fdir_list);
1063         snprintf(fdir_hash_name, RTE_HASH_NAMESIZE,
1064                  "fdir_%s", dev->device->name);
1065         fdir_info->hash_table = rte_hash_create(&fdir_hash_params);
1066         if (!fdir_info->hash_table) {
1067                 PMD_INIT_LOG(ERR, "Failed to create fdir hash table!");
1068                 return -EINVAL;
1069         }
1070         fdir_info->hash_map = rte_zmalloc("i40e_fdir_hash_map",
1071                                           sizeof(struct i40e_fdir_filter *) *
1072                                           I40E_MAX_FDIR_FILTER_NUM,
1073                                           0);
1074         if (!fdir_info->hash_map) {
1075                 PMD_INIT_LOG(ERR,
1076                              "Failed to allocate memory for fdir hash map!");
1077                 ret = -ENOMEM;
1078                 goto err_fdir_hash_map_alloc;
1079         }
1080         return 0;
1081
1082 err_fdir_hash_map_alloc:
1083         rte_hash_free(fdir_info->hash_table);
1084
1085         return ret;
1086 }
1087
1088 static void
1089 i40e_init_customized_info(struct i40e_pf *pf)
1090 {
1091         int i;
1092
1093         /* Initialize customized pctype */
1094         for (i = I40E_CUSTOMIZED_GTPC; i < I40E_CUSTOMIZED_MAX; i++) {
1095                 pf->customized_pctype[i].index = i;
1096                 pf->customized_pctype[i].pctype = I40E_FILTER_PCTYPE_INVALID;
1097                 pf->customized_pctype[i].valid = false;
1098         }
1099
1100         pf->gtp_support = false;
1101 }
1102
1103 void
1104 i40e_init_queue_region_conf(struct rte_eth_dev *dev)
1105 {
1106         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1107         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1108         struct i40e_queue_regions *info = &pf->queue_region;
1109         uint16_t i;
1110
1111         for (i = 0; i < I40E_PFQF_HREGION_MAX_INDEX; i++)
1112                 i40e_write_rx_ctl(hw, I40E_PFQF_HREGION(i), 0);
1113
1114         memset(info, 0, sizeof(struct i40e_queue_regions));
1115 }
1116
1117 static int
1118 i40e_parse_multi_drv_handler(__rte_unused const char *key,
1119                                const char *value,
1120                                void *opaque)
1121 {
1122         struct i40e_pf *pf;
1123         unsigned long support_multi_driver;
1124         char *end;
1125
1126         pf = (struct i40e_pf *)opaque;
1127
1128         errno = 0;
1129         support_multi_driver = strtoul(value, &end, 10);
1130         if (errno != 0 || end == value || *end != 0) {
1131                 PMD_DRV_LOG(WARNING, "Wrong global configuration");
1132                 return -(EINVAL);
1133         }
1134
1135         if (support_multi_driver == 1 || support_multi_driver == 0)
1136                 pf->support_multi_driver = (bool)support_multi_driver;
1137         else
1138                 PMD_DRV_LOG(WARNING, "%s must be 1 or 0,",
1139                             "enable global configuration by default."
1140                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1141         return 0;
1142 }
1143
1144 static int
1145 i40e_support_multi_driver(struct rte_eth_dev *dev)
1146 {
1147         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1148         struct rte_kvargs *kvlist;
1149         int kvargs_count;
1150
1151         /* Enable global configuration by default */
1152         pf->support_multi_driver = false;
1153
1154         if (!dev->device->devargs)
1155                 return 0;
1156
1157         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1158         if (!kvlist)
1159                 return -EINVAL;
1160
1161         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER);
1162         if (!kvargs_count) {
1163                 rte_kvargs_free(kvlist);
1164                 return 0;
1165         }
1166
1167         if (kvargs_count > 1)
1168                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1169                             "the first invalid or last valid one is used !",
1170                             ETH_I40E_SUPPORT_MULTI_DRIVER);
1171
1172         if (rte_kvargs_process(kvlist, ETH_I40E_SUPPORT_MULTI_DRIVER,
1173                                i40e_parse_multi_drv_handler, pf) < 0) {
1174                 rte_kvargs_free(kvlist);
1175                 return -EINVAL;
1176         }
1177
1178         rte_kvargs_free(kvlist);
1179         return 0;
1180 }
1181
1182 static int
1183 i40e_aq_debug_write_global_register(struct i40e_hw *hw,
1184                                     uint32_t reg_addr, uint64_t reg_val,
1185                                     struct i40e_asq_cmd_details *cmd_details)
1186 {
1187         uint64_t ori_reg_val;
1188         struct rte_eth_dev *dev;
1189         int ret;
1190
1191         ret = i40e_aq_debug_read_register(hw, reg_addr, &ori_reg_val, NULL);
1192         if (ret != I40E_SUCCESS) {
1193                 PMD_DRV_LOG(ERR,
1194                             "Fail to debug read from 0x%08x",
1195                             reg_addr);
1196                 return -EIO;
1197         }
1198         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
1199
1200         if (ori_reg_val != reg_val)
1201                 PMD_DRV_LOG(WARNING,
1202                             "i40e device %s changed global register [0x%08x]."
1203                             " original: 0x%"PRIx64", after: 0x%"PRIx64,
1204                             dev->device->name, reg_addr, ori_reg_val, reg_val);
1205
1206         return i40e_aq_debug_write_register(hw, reg_addr, reg_val, cmd_details);
1207 }
1208
1209 static int
1210 i40e_parse_latest_vec_handler(__rte_unused const char *key,
1211                                 const char *value,
1212                                 void *opaque)
1213 {
1214         struct i40e_adapter *ad = opaque;
1215         int use_latest_vec;
1216
1217         use_latest_vec = atoi(value);
1218
1219         if (use_latest_vec != 0 && use_latest_vec != 1)
1220                 PMD_DRV_LOG(WARNING, "Value should be 0 or 1, set it as 1!");
1221
1222         ad->use_latest_vec = (uint8_t)use_latest_vec;
1223
1224         return 0;
1225 }
1226
1227 static int
1228 i40e_use_latest_vec(struct rte_eth_dev *dev)
1229 {
1230         struct i40e_adapter *ad =
1231                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1232         struct rte_kvargs *kvlist;
1233         int kvargs_count;
1234
1235         ad->use_latest_vec = false;
1236
1237         if (!dev->device->devargs)
1238                 return 0;
1239
1240         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
1241         if (!kvlist)
1242                 return -EINVAL;
1243
1244         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_USE_LATEST_VEC);
1245         if (!kvargs_count) {
1246                 rte_kvargs_free(kvlist);
1247                 return 0;
1248         }
1249
1250         if (kvargs_count > 1)
1251                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
1252                             "the first invalid or last valid one is used !",
1253                             ETH_I40E_USE_LATEST_VEC);
1254
1255         if (rte_kvargs_process(kvlist, ETH_I40E_USE_LATEST_VEC,
1256                                 i40e_parse_latest_vec_handler, ad) < 0) {
1257                 rte_kvargs_free(kvlist);
1258                 return -EINVAL;
1259         }
1260
1261         rte_kvargs_free(kvlist);
1262         return 0;
1263 }
1264
1265 #define I40E_ALARM_INTERVAL 50000 /* us */
1266
1267 static int
1268 eth_i40e_dev_init(struct rte_eth_dev *dev, void *init_params __rte_unused)
1269 {
1270         struct rte_pci_device *pci_dev;
1271         struct rte_intr_handle *intr_handle;
1272         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1273         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1274         struct i40e_vsi *vsi;
1275         int ret;
1276         uint32_t len, val;
1277         uint8_t aq_fail = 0;
1278
1279         PMD_INIT_FUNC_TRACE();
1280
1281         dev->dev_ops = &i40e_eth_dev_ops;
1282         dev->rx_pkt_burst = i40e_recv_pkts;
1283         dev->tx_pkt_burst = i40e_xmit_pkts;
1284         dev->tx_pkt_prepare = i40e_prep_pkts;
1285
1286         /* for secondary processes, we don't initialise any further as primary
1287          * has already done this work. Only check we don't need a different
1288          * RX function */
1289         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1290                 i40e_set_rx_function(dev);
1291                 i40e_set_tx_function(dev);
1292                 return 0;
1293         }
1294         i40e_set_default_ptype_table(dev);
1295         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1296         intr_handle = &pci_dev->intr_handle;
1297
1298         rte_eth_copy_pci_info(dev, pci_dev);
1299
1300         pf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1301         pf->adapter->eth_dev = dev;
1302         pf->dev_data = dev->data;
1303
1304         hw->back = I40E_PF_TO_ADAPTER(pf);
1305         hw->hw_addr = (uint8_t *)(pci_dev->mem_resource[0].addr);
1306         if (!hw->hw_addr) {
1307                 PMD_INIT_LOG(ERR,
1308                         "Hardware is not available, as address is NULL");
1309                 return -ENODEV;
1310         }
1311
1312         hw->vendor_id = pci_dev->id.vendor_id;
1313         hw->device_id = pci_dev->id.device_id;
1314         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1315         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1316         hw->bus.device = pci_dev->addr.devid;
1317         hw->bus.func = pci_dev->addr.function;
1318         hw->adapter_stopped = 0;
1319         hw->adapter_closed = 0;
1320
1321         /*
1322          * Switch Tag value should not be identical to either the First Tag
1323          * or Second Tag values. So set something other than common Ethertype
1324          * for internal switching.
1325          */
1326         hw->switch_tag = 0xffff;
1327
1328         val = I40E_READ_REG(hw, I40E_GL_FWSTS);
1329         if (val & I40E_GL_FWSTS_FWS1B_MASK) {
1330                 PMD_INIT_LOG(ERR, "\nERROR: "
1331                         "Firmware recovery mode detected. Limiting functionality.\n"
1332                         "Refer to the Intel(R) Ethernet Adapters and Devices "
1333                         "User Guide for details on firmware recovery mode.");
1334                 return -EIO;
1335         }
1336
1337         /* Check if need to support multi-driver */
1338         i40e_support_multi_driver(dev);
1339         /* Check if users want the latest supported vec path */
1340         i40e_use_latest_vec(dev);
1341
1342         /* Make sure all is clean before doing PF reset */
1343         i40e_clear_hw(hw);
1344
1345         /* Reset here to make sure all is clean for each PF */
1346         ret = i40e_pf_reset(hw);
1347         if (ret) {
1348                 PMD_INIT_LOG(ERR, "Failed to reset pf: %d", ret);
1349                 return ret;
1350         }
1351
1352         /* Initialize the shared code (base driver) */
1353         ret = i40e_init_shared_code(hw);
1354         if (ret) {
1355                 PMD_INIT_LOG(ERR, "Failed to init shared code (base driver): %d", ret);
1356                 return ret;
1357         }
1358
1359         /* Initialize the parameters for adminq */
1360         i40e_init_adminq_parameter(hw);
1361         ret = i40e_init_adminq(hw);
1362         if (ret != I40E_SUCCESS) {
1363                 PMD_INIT_LOG(ERR, "Failed to init adminq: %d", ret);
1364                 return -EIO;
1365         }
1366         PMD_INIT_LOG(INFO, "FW %d.%d API %d.%d NVM %02d.%02d.%02d eetrack %04x",
1367                      hw->aq.fw_maj_ver, hw->aq.fw_min_ver,
1368                      hw->aq.api_maj_ver, hw->aq.api_min_ver,
1369                      ((hw->nvm.version >> 12) & 0xf),
1370                      ((hw->nvm.version >> 4) & 0xff),
1371                      (hw->nvm.version & 0xf), hw->nvm.eetrack);
1372
1373         /* Initialize the hardware */
1374         i40e_hw_init(dev);
1375
1376         i40e_config_automask(pf);
1377
1378         i40e_set_default_pctype_table(dev);
1379
1380         /*
1381          * To work around the NVM issue, initialize registers
1382          * for packet type of QinQ by software.
1383          * It should be removed once issues are fixed in NVM.
1384          */
1385         if (!pf->support_multi_driver)
1386                 i40e_GLQF_reg_init(hw);
1387
1388         /* Initialize the input set for filters (hash and fd) to default value */
1389         i40e_filter_input_set_init(pf);
1390
1391         /* initialise the L3_MAP register */
1392         if (!pf->support_multi_driver) {
1393                 ret = i40e_aq_debug_write_global_register(hw,
1394                                                    I40E_GLQF_L3_MAP(40),
1395                                                    0x00000028,  NULL);
1396                 if (ret)
1397                         PMD_INIT_LOG(ERR, "Failed to write L3 MAP register %d",
1398                                      ret);
1399                 PMD_INIT_LOG(DEBUG,
1400                              "Global register 0x%08x is changed with 0x28",
1401                              I40E_GLQF_L3_MAP(40));
1402         }
1403
1404         /* Need the special FW version to support floating VEB */
1405         config_floating_veb(dev);
1406         /* Clear PXE mode */
1407         i40e_clear_pxe_mode(hw);
1408         i40e_dev_sync_phy_type(hw);
1409
1410         /*
1411          * On X710, performance number is far from the expectation on recent
1412          * firmware versions. The fix for this issue may not be integrated in
1413          * the following firmware version. So the workaround in software driver
1414          * is needed. It needs to modify the initial values of 3 internal only
1415          * registers. Note that the workaround can be removed when it is fixed
1416          * in firmware in the future.
1417          */
1418         i40e_configure_registers(hw);
1419
1420         /* Get hw capabilities */
1421         ret = i40e_get_cap(hw);
1422         if (ret != I40E_SUCCESS) {
1423                 PMD_INIT_LOG(ERR, "Failed to get capabilities: %d", ret);
1424                 goto err_get_capabilities;
1425         }
1426
1427         /* Initialize parameters for PF */
1428         ret = i40e_pf_parameter_init(dev);
1429         if (ret != 0) {
1430                 PMD_INIT_LOG(ERR, "Failed to do parameter init: %d", ret);
1431                 goto err_parameter_init;
1432         }
1433
1434         /* Initialize the queue management */
1435         ret = i40e_res_pool_init(&pf->qp_pool, 0, hw->func_caps.num_tx_qp);
1436         if (ret < 0) {
1437                 PMD_INIT_LOG(ERR, "Failed to init queue pool");
1438                 goto err_qp_pool_init;
1439         }
1440         ret = i40e_res_pool_init(&pf->msix_pool, 1,
1441                                 hw->func_caps.num_msix_vectors - 1);
1442         if (ret < 0) {
1443                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1444                 goto err_msix_pool_init;
1445         }
1446
1447         /* Initialize lan hmc */
1448         ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
1449                                 hw->func_caps.num_rx_qp, 0, 0);
1450         if (ret != I40E_SUCCESS) {
1451                 PMD_INIT_LOG(ERR, "Failed to init lan hmc: %d", ret);
1452                 goto err_init_lan_hmc;
1453         }
1454
1455         /* Configure lan hmc */
1456         ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
1457         if (ret != I40E_SUCCESS) {
1458                 PMD_INIT_LOG(ERR, "Failed to configure lan hmc: %d", ret);
1459                 goto err_configure_lan_hmc;
1460         }
1461
1462         /* Get and check the mac address */
1463         i40e_get_mac_addr(hw, hw->mac.addr);
1464         if (i40e_validate_mac_addr(hw->mac.addr) != I40E_SUCCESS) {
1465                 PMD_INIT_LOG(ERR, "mac address is not valid");
1466                 ret = -EIO;
1467                 goto err_get_mac_addr;
1468         }
1469         /* Copy the permanent MAC address */
1470         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.addr,
1471                         (struct rte_ether_addr *)hw->mac.perm_addr);
1472
1473         /* Disable flow control */
1474         hw->fc.requested_mode = I40E_FC_NONE;
1475         i40e_set_fc(hw, &aq_fail, TRUE);
1476
1477         /* Set the global registers with default ether type value */
1478         if (!pf->support_multi_driver) {
1479                 ret = i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
1480                                          RTE_ETHER_TYPE_VLAN);
1481                 if (ret != I40E_SUCCESS) {
1482                         PMD_INIT_LOG(ERR,
1483                                      "Failed to set the default outer "
1484                                      "VLAN ether type");
1485                         goto err_setup_pf_switch;
1486                 }
1487         }
1488
1489         /* PF setup, which includes VSI setup */
1490         ret = i40e_pf_setup(pf);
1491         if (ret) {
1492                 PMD_INIT_LOG(ERR, "Failed to setup pf switch: %d", ret);
1493                 goto err_setup_pf_switch;
1494         }
1495
1496         vsi = pf->main_vsi;
1497
1498         /* Disable double vlan by default */
1499         i40e_vsi_config_double_vlan(vsi, FALSE);
1500
1501         /* Disable S-TAG identification when floating_veb is disabled */
1502         if (!pf->floating_veb) {
1503                 ret = I40E_READ_REG(hw, I40E_PRT_L2TAGSEN);
1504                 if (ret & I40E_L2_TAGS_S_TAG_MASK) {
1505                         ret &= ~I40E_L2_TAGS_S_TAG_MASK;
1506                         I40E_WRITE_REG(hw, I40E_PRT_L2TAGSEN, ret);
1507                 }
1508         }
1509
1510         if (!vsi->max_macaddrs)
1511                 len = RTE_ETHER_ADDR_LEN;
1512         else
1513                 len = RTE_ETHER_ADDR_LEN * vsi->max_macaddrs;
1514
1515         /* Should be after VSI initialized */
1516         dev->data->mac_addrs = rte_zmalloc("i40e", len, 0);
1517         if (!dev->data->mac_addrs) {
1518                 PMD_INIT_LOG(ERR,
1519                         "Failed to allocated memory for storing mac address");
1520                 goto err_mac_alloc;
1521         }
1522         rte_ether_addr_copy((struct rte_ether_addr *)hw->mac.perm_addr,
1523                                         &dev->data->mac_addrs[0]);
1524
1525         /* Init dcb to sw mode by default */
1526         ret = i40e_dcb_init_configure(dev, TRUE);
1527         if (ret != I40E_SUCCESS) {
1528                 PMD_INIT_LOG(INFO, "Failed to init dcb.");
1529                 pf->flags &= ~I40E_FLAG_DCB;
1530         }
1531         /* Update HW struct after DCB configuration */
1532         i40e_get_cap(hw);
1533
1534         /* initialize pf host driver to setup SRIOV resource if applicable */
1535         i40e_pf_host_init(dev);
1536
1537         /* register callback func to eal lib */
1538         rte_intr_callback_register(intr_handle,
1539                                    i40e_dev_interrupt_handler, dev);
1540
1541         /* configure and enable device interrupt */
1542         i40e_pf_config_irq0(hw, TRUE);
1543         i40e_pf_enable_irq0(hw);
1544
1545         /* enable uio intr after callback register */
1546         rte_intr_enable(intr_handle);
1547
1548         /* By default disable flexible payload in global configuration */
1549         if (!pf->support_multi_driver)
1550                 i40e_flex_payload_reg_set_default(hw);
1551
1552         /*
1553          * Add an ethertype filter to drop all flow control frames transmitted
1554          * from VSIs. By doing so, we stop VF from sending out PAUSE or PFC
1555          * frames to wire.
1556          */
1557         i40e_add_tx_flow_control_drop_filter(pf);
1558
1559         /* Set the max frame size to 0x2600 by default,
1560          * in case other drivers changed the default value.
1561          */
1562         i40e_aq_set_mac_config(hw, I40E_FRAME_SIZE_MAX, TRUE, 0, NULL);
1563
1564         /* initialize mirror rule list */
1565         TAILQ_INIT(&pf->mirror_list);
1566
1567         /* initialize Traffic Manager configuration */
1568         i40e_tm_conf_init(dev);
1569
1570         /* Initialize customized information */
1571         i40e_init_customized_info(pf);
1572
1573         ret = i40e_init_ethtype_filter_list(dev);
1574         if (ret < 0)
1575                 goto err_init_ethtype_filter_list;
1576         ret = i40e_init_tunnel_filter_list(dev);
1577         if (ret < 0)
1578                 goto err_init_tunnel_filter_list;
1579         ret = i40e_init_fdir_filter_list(dev);
1580         if (ret < 0)
1581                 goto err_init_fdir_filter_list;
1582
1583         /* initialize queue region configuration */
1584         i40e_init_queue_region_conf(dev);
1585
1586         /* initialize rss configuration from rte_flow */
1587         memset(&pf->rss_info, 0,
1588                 sizeof(struct i40e_rte_flow_rss_conf));
1589
1590         /* reset all stats of the device, including pf and main vsi */
1591         i40e_dev_stats_reset(dev);
1592
1593         return 0;
1594
1595 err_init_fdir_filter_list:
1596         rte_free(pf->tunnel.hash_table);
1597         rte_free(pf->tunnel.hash_map);
1598 err_init_tunnel_filter_list:
1599         rte_free(pf->ethertype.hash_table);
1600         rte_free(pf->ethertype.hash_map);
1601 err_init_ethtype_filter_list:
1602         rte_free(dev->data->mac_addrs);
1603 err_mac_alloc:
1604         i40e_vsi_release(pf->main_vsi);
1605 err_setup_pf_switch:
1606 err_get_mac_addr:
1607 err_configure_lan_hmc:
1608         (void)i40e_shutdown_lan_hmc(hw);
1609 err_init_lan_hmc:
1610         i40e_res_pool_destroy(&pf->msix_pool);
1611 err_msix_pool_init:
1612         i40e_res_pool_destroy(&pf->qp_pool);
1613 err_qp_pool_init:
1614 err_parameter_init:
1615 err_get_capabilities:
1616         (void)i40e_shutdown_adminq(hw);
1617
1618         return ret;
1619 }
1620
1621 static void
1622 i40e_rm_ethtype_filter_list(struct i40e_pf *pf)
1623 {
1624         struct i40e_ethertype_filter *p_ethertype;
1625         struct i40e_ethertype_rule *ethertype_rule;
1626
1627         ethertype_rule = &pf->ethertype;
1628         /* Remove all ethertype filter rules and hash */
1629         if (ethertype_rule->hash_map)
1630                 rte_free(ethertype_rule->hash_map);
1631         if (ethertype_rule->hash_table)
1632                 rte_hash_free(ethertype_rule->hash_table);
1633
1634         while ((p_ethertype = TAILQ_FIRST(&ethertype_rule->ethertype_list))) {
1635                 TAILQ_REMOVE(&ethertype_rule->ethertype_list,
1636                              p_ethertype, rules);
1637                 rte_free(p_ethertype);
1638         }
1639 }
1640
1641 static void
1642 i40e_rm_tunnel_filter_list(struct i40e_pf *pf)
1643 {
1644         struct i40e_tunnel_filter *p_tunnel;
1645         struct i40e_tunnel_rule *tunnel_rule;
1646
1647         tunnel_rule = &pf->tunnel;
1648         /* Remove all tunnel director rules and hash */
1649         if (tunnel_rule->hash_map)
1650                 rte_free(tunnel_rule->hash_map);
1651         if (tunnel_rule->hash_table)
1652                 rte_hash_free(tunnel_rule->hash_table);
1653
1654         while ((p_tunnel = TAILQ_FIRST(&tunnel_rule->tunnel_list))) {
1655                 TAILQ_REMOVE(&tunnel_rule->tunnel_list, p_tunnel, rules);
1656                 rte_free(p_tunnel);
1657         }
1658 }
1659
1660 static void
1661 i40e_rm_fdir_filter_list(struct i40e_pf *pf)
1662 {
1663         struct i40e_fdir_filter *p_fdir;
1664         struct i40e_fdir_info *fdir_info;
1665
1666         fdir_info = &pf->fdir;
1667         /* Remove all flow director rules and hash */
1668         if (fdir_info->hash_map)
1669                 rte_free(fdir_info->hash_map);
1670         if (fdir_info->hash_table)
1671                 rte_hash_free(fdir_info->hash_table);
1672
1673         while ((p_fdir = TAILQ_FIRST(&fdir_info->fdir_list))) {
1674                 TAILQ_REMOVE(&fdir_info->fdir_list, p_fdir, rules);
1675                 rte_free(p_fdir);
1676         }
1677 }
1678
1679 void i40e_flex_payload_reg_set_default(struct i40e_hw *hw)
1680 {
1681         /*
1682          * Disable by default flexible payload
1683          * for corresponding L2/L3/L4 layers.
1684          */
1685         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33), 0x00000000);
1686         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(34), 0x00000000);
1687         I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(35), 0x00000000);
1688 }
1689
1690 static int
1691 eth_i40e_dev_uninit(struct rte_eth_dev *dev)
1692 {
1693         struct i40e_pf *pf;
1694         struct rte_pci_device *pci_dev;
1695         struct rte_intr_handle *intr_handle;
1696         struct i40e_hw *hw;
1697         struct i40e_filter_control_settings settings;
1698         struct rte_flow *p_flow;
1699         int ret;
1700         uint8_t aq_fail = 0;
1701         int retries = 0;
1702
1703         PMD_INIT_FUNC_TRACE();
1704
1705         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1706                 return 0;
1707
1708         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1709         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1710         pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1711         intr_handle = &pci_dev->intr_handle;
1712
1713         ret = rte_eth_switch_domain_free(pf->switch_domain_id);
1714         if (ret)
1715                 PMD_INIT_LOG(WARNING, "failed to free switch domain: %d", ret);
1716
1717         if (hw->adapter_closed == 0)
1718                 i40e_dev_close(dev);
1719
1720         dev->dev_ops = NULL;
1721         dev->rx_pkt_burst = NULL;
1722         dev->tx_pkt_burst = NULL;
1723
1724         /* Clear PXE mode */
1725         i40e_clear_pxe_mode(hw);
1726
1727         /* Unconfigure filter control */
1728         memset(&settings, 0, sizeof(settings));
1729         ret = i40e_set_filter_control(hw, &settings);
1730         if (ret)
1731                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
1732                                         ret);
1733
1734         /* Disable flow control */
1735         hw->fc.requested_mode = I40E_FC_NONE;
1736         i40e_set_fc(hw, &aq_fail, TRUE);
1737
1738         /* uninitialize pf host driver */
1739         i40e_pf_host_uninit(dev);
1740
1741         /* disable uio intr before callback unregister */
1742         rte_intr_disable(intr_handle);
1743
1744         /* unregister callback func to eal lib */
1745         do {
1746                 ret = rte_intr_callback_unregister(intr_handle,
1747                                 i40e_dev_interrupt_handler, dev);
1748                 if (ret >= 0) {
1749                         break;
1750                 } else if (ret != -EAGAIN) {
1751                         PMD_INIT_LOG(ERR,
1752                                  "intr callback unregister failed: %d",
1753                                  ret);
1754                         return ret;
1755                 }
1756                 i40e_msec_delay(500);
1757         } while (retries++ < 5);
1758
1759         i40e_rm_ethtype_filter_list(pf);
1760         i40e_rm_tunnel_filter_list(pf);
1761         i40e_rm_fdir_filter_list(pf);
1762
1763         /* Remove all flows */
1764         while ((p_flow = TAILQ_FIRST(&pf->flow_list))) {
1765                 TAILQ_REMOVE(&pf->flow_list, p_flow, node);
1766                 rte_free(p_flow);
1767         }
1768
1769         /* Remove all Traffic Manager configuration */
1770         i40e_tm_conf_uninit(dev);
1771
1772         return 0;
1773 }
1774
1775 static int
1776 i40e_dev_configure(struct rte_eth_dev *dev)
1777 {
1778         struct i40e_adapter *ad =
1779                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1780         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782         enum rte_eth_rx_mq_mode mq_mode = dev->data->dev_conf.rxmode.mq_mode;
1783         int i, ret;
1784
1785         ret = i40e_dev_sync_phy_type(hw);
1786         if (ret)
1787                 return ret;
1788
1789         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1790          * bulk allocation or vector Rx preconditions we will reset it.
1791          */
1792         ad->rx_bulk_alloc_allowed = true;
1793         ad->rx_vec_allowed = true;
1794         ad->tx_simple_allowed = true;
1795         ad->tx_vec_allowed = true;
1796
1797         /* Only legacy filter API needs the following fdir config. So when the
1798          * legacy filter API is deprecated, the following codes should also be
1799          * removed.
1800          */
1801         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT) {
1802                 ret = i40e_fdir_setup(pf);
1803                 if (ret != I40E_SUCCESS) {
1804                         PMD_DRV_LOG(ERR, "Failed to setup flow director.");
1805                         return -ENOTSUP;
1806                 }
1807                 ret = i40e_fdir_configure(dev);
1808                 if (ret < 0) {
1809                         PMD_DRV_LOG(ERR, "failed to configure fdir.");
1810                         goto err;
1811                 }
1812         } else
1813                 i40e_fdir_teardown(pf);
1814
1815         ret = i40e_dev_init_vlan(dev);
1816         if (ret < 0)
1817                 goto err;
1818
1819         /* VMDQ setup.
1820          *  Needs to move VMDQ setting out of i40e_pf_config_mq_rx() as VMDQ and
1821          *  RSS setting have different requirements.
1822          *  General PMD driver call sequence are NIC init, configure,
1823          *  rx/tx_queue_setup and dev_start. In rx/tx_queue_setup() function, it
1824          *  will try to lookup the VSI that specific queue belongs to if VMDQ
1825          *  applicable. So, VMDQ setting has to be done before
1826          *  rx/tx_queue_setup(). This function is good  to place vmdq_setup.
1827          *  For RSS setting, it will try to calculate actual configured RX queue
1828          *  number, which will be available after rx_queue_setup(). dev_start()
1829          *  function is good to place RSS setup.
1830          */
1831         if (mq_mode & ETH_MQ_RX_VMDQ_FLAG) {
1832                 ret = i40e_vmdq_setup(dev);
1833                 if (ret)
1834                         goto err;
1835         }
1836
1837         if (mq_mode & ETH_MQ_RX_DCB_FLAG) {
1838                 ret = i40e_dcb_setup(dev);
1839                 if (ret) {
1840                         PMD_DRV_LOG(ERR, "failed to configure DCB.");
1841                         goto err_dcb;
1842                 }
1843         }
1844
1845         TAILQ_INIT(&pf->flow_list);
1846
1847         return 0;
1848
1849 err_dcb:
1850         /* need to release vmdq resource if exists */
1851         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
1852                 i40e_vsi_release(pf->vmdq[i].vsi);
1853                 pf->vmdq[i].vsi = NULL;
1854         }
1855         rte_free(pf->vmdq);
1856         pf->vmdq = NULL;
1857 err:
1858         /* Need to release fdir resource if exists.
1859          * Only legacy filter API needs the following fdir config. So when the
1860          * legacy filter API is deprecated, the following code should also be
1861          * removed.
1862          */
1863         i40e_fdir_teardown(pf);
1864         return ret;
1865 }
1866
1867 void
1868 i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi)
1869 {
1870         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1871         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1872         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1873         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1874         uint16_t msix_vect = vsi->msix_intr;
1875         uint16_t i;
1876
1877         for (i = 0; i < vsi->nb_qps; i++) {
1878                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1879                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1880                 rte_wmb();
1881         }
1882
1883         if (vsi->type != I40E_VSI_SRIOV) {
1884                 if (!rte_intr_allow_others(intr_handle)) {
1885                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1886                                        I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
1887                         I40E_WRITE_REG(hw,
1888                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1889                                        0);
1890                 } else {
1891                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1892                                        I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK);
1893                         I40E_WRITE_REG(hw,
1894                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1895                                                        msix_vect - 1), 0);
1896                 }
1897         } else {
1898                 uint32_t reg;
1899                 reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1900                         vsi->user_param + (msix_vect - 1);
1901
1902                 I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1903                                I40E_VPINT_LNKLSTN_FIRSTQ_INDX_MASK);
1904         }
1905         I40E_WRITE_FLUSH(hw);
1906 }
1907
1908 static void
1909 __vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t msix_vect,
1910                        int base_queue, int nb_queue,
1911                        uint16_t itr_idx)
1912 {
1913         int i;
1914         uint32_t val;
1915         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1916         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
1917
1918         /* Bind all RX queues to allocated MSIX interrupt */
1919         for (i = 0; i < nb_queue; i++) {
1920                 val = (msix_vect << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
1921                         itr_idx << I40E_QINT_RQCTL_ITR_INDX_SHIFT |
1922                         ((base_queue + i + 1) <<
1923                          I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
1924                         (0 << I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT) |
1925                         I40E_QINT_RQCTL_CAUSE_ENA_MASK;
1926
1927                 if (i == nb_queue - 1)
1928                         val |= I40E_QINT_RQCTL_NEXTQ_INDX_MASK;
1929                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(base_queue + i), val);
1930         }
1931
1932         /* Write first RX queue to Link list register as the head element */
1933         if (vsi->type != I40E_VSI_SRIOV) {
1934                 uint16_t interval =
1935                         i40e_calc_itr_interval(1, pf->support_multi_driver);
1936
1937                 if (msix_vect == I40E_MISC_VEC_ID) {
1938                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
1939                                        (base_queue <<
1940                                         I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1941                                        (0x0 <<
1942                                         I40E_PFINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1943                         I40E_WRITE_REG(hw,
1944                                        I40E_PFINT_ITR0(I40E_ITR_INDEX_DEFAULT),
1945                                        interval);
1946                 } else {
1947                         I40E_WRITE_REG(hw, I40E_PFINT_LNKLSTN(msix_vect - 1),
1948                                        (base_queue <<
1949                                         I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1950                                        (0x0 <<
1951                                         I40E_PFINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1952                         I40E_WRITE_REG(hw,
1953                                        I40E_PFINT_ITRN(I40E_ITR_INDEX_DEFAULT,
1954                                                        msix_vect - 1),
1955                                        interval);
1956                 }
1957         } else {
1958                 uint32_t reg;
1959
1960                 if (msix_vect == I40E_MISC_VEC_ID) {
1961                         I40E_WRITE_REG(hw,
1962                                        I40E_VPINT_LNKLST0(vsi->user_param),
1963                                        (base_queue <<
1964                                         I40E_VPINT_LNKLST0_FIRSTQ_INDX_SHIFT) |
1965                                        (0x0 <<
1966                                         I40E_VPINT_LNKLST0_FIRSTQ_TYPE_SHIFT));
1967                 } else {
1968                         /* num_msix_vectors_vf needs to minus irq0 */
1969                         reg = (hw->func_caps.num_msix_vectors_vf - 1) *
1970                                 vsi->user_param + (msix_vect - 1);
1971
1972                         I40E_WRITE_REG(hw, I40E_VPINT_LNKLSTN(reg),
1973                                        (base_queue <<
1974                                         I40E_VPINT_LNKLSTN_FIRSTQ_INDX_SHIFT) |
1975                                        (0x0 <<
1976                                         I40E_VPINT_LNKLSTN_FIRSTQ_TYPE_SHIFT));
1977                 }
1978         }
1979
1980         I40E_WRITE_FLUSH(hw);
1981 }
1982
1983 void
1984 i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx)
1985 {
1986         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1987         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
1990         uint16_t msix_vect = vsi->msix_intr;
1991         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1992         uint16_t queue_idx = 0;
1993         int record = 0;
1994         int i;
1995
1996         for (i = 0; i < vsi->nb_qps; i++) {
1997                 I40E_WRITE_REG(hw, I40E_QINT_TQCTL(vsi->base_queue + i), 0);
1998                 I40E_WRITE_REG(hw, I40E_QINT_RQCTL(vsi->base_queue + i), 0);
1999         }
2000
2001         /* VF bind interrupt */
2002         if (vsi->type == I40E_VSI_SRIOV) {
2003                 __vsi_queues_bind_intr(vsi, msix_vect,
2004                                        vsi->base_queue, vsi->nb_qps,
2005                                        itr_idx);
2006                 return;
2007         }
2008
2009         /* PF & VMDq bind interrupt */
2010         if (rte_intr_dp_is_en(intr_handle)) {
2011                 if (vsi->type == I40E_VSI_MAIN) {
2012                         queue_idx = 0;
2013                         record = 1;
2014                 } else if (vsi->type == I40E_VSI_VMDQ2) {
2015                         struct i40e_vsi *main_vsi =
2016                                 I40E_DEV_PRIVATE_TO_MAIN_VSI(vsi->adapter);
2017                         queue_idx = vsi->base_queue - main_vsi->nb_qps;
2018                         record = 1;
2019                 }
2020         }
2021
2022         for (i = 0; i < vsi->nb_used_qps; i++) {
2023                 if (nb_msix <= 1) {
2024                         if (!rte_intr_allow_others(intr_handle))
2025                                 /* allow to share MISC_VEC_ID */
2026                                 msix_vect = I40E_MISC_VEC_ID;
2027
2028                         /* no enough msix_vect, map all to one */
2029                         __vsi_queues_bind_intr(vsi, msix_vect,
2030                                                vsi->base_queue + i,
2031                                                vsi->nb_used_qps - i,
2032                                                itr_idx);
2033                         for (; !!record && i < vsi->nb_used_qps; i++)
2034                                 intr_handle->intr_vec[queue_idx + i] =
2035                                         msix_vect;
2036                         break;
2037                 }
2038                 /* 1:1 queue/msix_vect mapping */
2039                 __vsi_queues_bind_intr(vsi, msix_vect,
2040                                        vsi->base_queue + i, 1,
2041                                        itr_idx);
2042                 if (!!record)
2043                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
2044
2045                 msix_vect++;
2046                 nb_msix--;
2047         }
2048 }
2049
2050 static void
2051 i40e_vsi_enable_queues_intr(struct i40e_vsi *vsi)
2052 {
2053         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2054         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2057         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2058         uint16_t msix_intr, i;
2059
2060         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2061                 for (i = 0; i < vsi->nb_msix; i++) {
2062                         msix_intr = vsi->msix_intr + i;
2063                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2064                                 I40E_PFINT_DYN_CTLN_INTENA_MASK |
2065                                 I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
2066                                 I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2067                 }
2068         else
2069                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2070                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
2071                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
2072                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2073
2074         I40E_WRITE_FLUSH(hw);
2075 }
2076
2077 static void
2078 i40e_vsi_disable_queues_intr(struct i40e_vsi *vsi)
2079 {
2080         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
2081         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2082         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2083         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2084         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
2085         uint16_t msix_intr, i;
2086
2087         if (rte_intr_allow_others(intr_handle) && !pf->support_multi_driver)
2088                 for (i = 0; i < vsi->nb_msix; i++) {
2089                         msix_intr = vsi->msix_intr + i;
2090                         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTLN(msix_intr - 1),
2091                                        I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
2092                 }
2093         else
2094                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
2095                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
2096
2097         I40E_WRITE_FLUSH(hw);
2098 }
2099
2100 static inline uint8_t
2101 i40e_parse_link_speeds(uint16_t link_speeds)
2102 {
2103         uint8_t link_speed = I40E_LINK_SPEED_UNKNOWN;
2104
2105         if (link_speeds & ETH_LINK_SPEED_40G)
2106                 link_speed |= I40E_LINK_SPEED_40GB;
2107         if (link_speeds & ETH_LINK_SPEED_25G)
2108                 link_speed |= I40E_LINK_SPEED_25GB;
2109         if (link_speeds & ETH_LINK_SPEED_20G)
2110                 link_speed |= I40E_LINK_SPEED_20GB;
2111         if (link_speeds & ETH_LINK_SPEED_10G)
2112                 link_speed |= I40E_LINK_SPEED_10GB;
2113         if (link_speeds & ETH_LINK_SPEED_1G)
2114                 link_speed |= I40E_LINK_SPEED_1GB;
2115         if (link_speeds & ETH_LINK_SPEED_100M)
2116                 link_speed |= I40E_LINK_SPEED_100MB;
2117
2118         return link_speed;
2119 }
2120
2121 static int
2122 i40e_phy_conf_link(struct i40e_hw *hw,
2123                    uint8_t abilities,
2124                    uint8_t force_speed,
2125                    bool is_up)
2126 {
2127         enum i40e_status_code status;
2128         struct i40e_aq_get_phy_abilities_resp phy_ab;
2129         struct i40e_aq_set_phy_config phy_conf;
2130         enum i40e_aq_phy_type cnt;
2131         uint8_t avail_speed;
2132         uint32_t phy_type_mask = 0;
2133
2134         const uint8_t mask = I40E_AQ_PHY_FLAG_PAUSE_TX |
2135                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2136                         I40E_AQ_PHY_FLAG_PAUSE_RX |
2137                         I40E_AQ_PHY_FLAG_LOW_POWER;
2138         int ret = -ENOTSUP;
2139
2140         /* To get phy capabilities of available speeds. */
2141         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
2142                                               NULL);
2143         if (status) {
2144                 PMD_DRV_LOG(ERR, "Failed to get PHY capabilities: %d\n",
2145                                 status);
2146                 return ret;
2147         }
2148         avail_speed = phy_ab.link_speed;
2149
2150         /* To get the current phy config. */
2151         status = i40e_aq_get_phy_capabilities(hw, false, false, &phy_ab,
2152                                               NULL);
2153         if (status) {
2154                 PMD_DRV_LOG(ERR, "Failed to get the current PHY config: %d\n",
2155                                 status);
2156                 return ret;
2157         }
2158
2159         /* If link needs to go up and it is in autoneg mode the speed is OK,
2160          * no need to set up again.
2161          */
2162         if (is_up && phy_ab.phy_type != 0 &&
2163                      abilities & I40E_AQ_PHY_AN_ENABLED &&
2164                      phy_ab.link_speed != 0)
2165                 return I40E_SUCCESS;
2166
2167         memset(&phy_conf, 0, sizeof(phy_conf));
2168
2169         /* bits 0-2 use the values from get_phy_abilities_resp */
2170         abilities &= ~mask;
2171         abilities |= phy_ab.abilities & mask;
2172
2173         phy_conf.abilities = abilities;
2174
2175         /* If link needs to go up, but the force speed is not supported,
2176          * Warn users and config the default available speeds.
2177          */
2178         if (is_up && !(force_speed & avail_speed)) {
2179                 PMD_DRV_LOG(WARNING, "Invalid speed setting, set to default!\n");
2180                 phy_conf.link_speed = avail_speed;
2181         } else {
2182                 phy_conf.link_speed = is_up ? force_speed : avail_speed;
2183         }
2184
2185         /* PHY type mask needs to include each type except PHY type extension */
2186         for (cnt = I40E_PHY_TYPE_SGMII; cnt < I40E_PHY_TYPE_25GBASE_KR; cnt++)
2187                 phy_type_mask |= 1 << cnt;
2188
2189         /* use get_phy_abilities_resp value for the rest */
2190         phy_conf.phy_type = is_up ? cpu_to_le32(phy_type_mask) : 0;
2191         phy_conf.phy_type_ext = is_up ? (I40E_AQ_PHY_TYPE_EXT_25G_KR |
2192                 I40E_AQ_PHY_TYPE_EXT_25G_CR | I40E_AQ_PHY_TYPE_EXT_25G_SR |
2193                 I40E_AQ_PHY_TYPE_EXT_25G_LR) : 0;
2194         phy_conf.fec_config = phy_ab.fec_cfg_curr_mod_ext_info;
2195         phy_conf.eee_capability = phy_ab.eee_capability;
2196         phy_conf.eeer = phy_ab.eeer_val;
2197         phy_conf.low_power_ctrl = phy_ab.d3_lpan;
2198
2199         PMD_DRV_LOG(DEBUG, "\tCurrent: abilities %x, link_speed %x",
2200                     phy_ab.abilities, phy_ab.link_speed);
2201         PMD_DRV_LOG(DEBUG, "\tConfig:  abilities %x, link_speed %x",
2202                     phy_conf.abilities, phy_conf.link_speed);
2203
2204         status = i40e_aq_set_phy_config(hw, &phy_conf, NULL);
2205         if (status)
2206                 return ret;
2207
2208         return I40E_SUCCESS;
2209 }
2210
2211 static int
2212 i40e_apply_link_speed(struct rte_eth_dev *dev)
2213 {
2214         uint8_t speed;
2215         uint8_t abilities = 0;
2216         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2217         struct rte_eth_conf *conf = &dev->data->dev_conf;
2218
2219         if (conf->link_speeds == ETH_LINK_SPEED_AUTONEG) {
2220                 conf->link_speeds = ETH_LINK_SPEED_40G |
2221                                     ETH_LINK_SPEED_25G |
2222                                     ETH_LINK_SPEED_20G |
2223                                     ETH_LINK_SPEED_10G |
2224                                     ETH_LINK_SPEED_1G |
2225                                     ETH_LINK_SPEED_100M;
2226         }
2227         speed = i40e_parse_link_speeds(conf->link_speeds);
2228         abilities |= I40E_AQ_PHY_ENABLE_ATOMIC_LINK |
2229                      I40E_AQ_PHY_AN_ENABLED |
2230                      I40E_AQ_PHY_LINK_ENABLED;
2231
2232         return i40e_phy_conf_link(hw, abilities, speed, true);
2233 }
2234
2235 static int
2236 i40e_dev_start(struct rte_eth_dev *dev)
2237 {
2238         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2239         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2240         struct i40e_vsi *main_vsi = pf->main_vsi;
2241         int ret, i;
2242         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2244         uint32_t intr_vector = 0;
2245         struct i40e_vsi *vsi;
2246
2247         hw->adapter_stopped = 0;
2248
2249         if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED) {
2250                 PMD_INIT_LOG(ERR,
2251                 "Invalid link_speeds for port %u, autonegotiation disabled",
2252                               dev->data->port_id);
2253                 return -EINVAL;
2254         }
2255
2256         rte_intr_disable(intr_handle);
2257
2258         if ((rte_intr_cap_multiple(intr_handle) ||
2259              !RTE_ETH_DEV_SRIOV(dev).active) &&
2260             dev->data->dev_conf.intr_conf.rxq != 0) {
2261                 intr_vector = dev->data->nb_rx_queues;
2262                 ret = rte_intr_efd_enable(intr_handle, intr_vector);
2263                 if (ret)
2264                         return ret;
2265         }
2266
2267         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2268                 intr_handle->intr_vec =
2269                         rte_zmalloc("intr_vec",
2270                                     dev->data->nb_rx_queues * sizeof(int),
2271                                     0);
2272                 if (!intr_handle->intr_vec) {
2273                         PMD_INIT_LOG(ERR,
2274                                 "Failed to allocate %d rx_queues intr_vec",
2275                                 dev->data->nb_rx_queues);
2276                         return -ENOMEM;
2277                 }
2278         }
2279
2280         /* Initialize VSI */
2281         ret = i40e_dev_rxtx_init(pf);
2282         if (ret != I40E_SUCCESS) {
2283                 PMD_DRV_LOG(ERR, "Failed to init rx/tx queues");
2284                 goto err_up;
2285         }
2286
2287         /* Map queues with MSIX interrupt */
2288         main_vsi->nb_used_qps = dev->data->nb_rx_queues -
2289                 pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2290         i40e_vsi_queues_bind_intr(main_vsi, I40E_ITR_INDEX_DEFAULT);
2291         i40e_vsi_enable_queues_intr(main_vsi);
2292
2293         /* Map VMDQ VSI queues with MSIX interrupt */
2294         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2295                 pf->vmdq[i].vsi->nb_used_qps = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
2296                 i40e_vsi_queues_bind_intr(pf->vmdq[i].vsi,
2297                                           I40E_ITR_INDEX_DEFAULT);
2298                 i40e_vsi_enable_queues_intr(pf->vmdq[i].vsi);
2299         }
2300
2301         /* enable FDIR MSIX interrupt */
2302         if (pf->fdir.fdir_vsi) {
2303                 i40e_vsi_queues_bind_intr(pf->fdir.fdir_vsi,
2304                                           I40E_ITR_INDEX_NONE);
2305                 i40e_vsi_enable_queues_intr(pf->fdir.fdir_vsi);
2306         }
2307
2308         /* Enable all queues which have been configured */
2309         ret = i40e_dev_switch_queues(pf, TRUE);
2310         if (ret != I40E_SUCCESS) {
2311                 PMD_DRV_LOG(ERR, "Failed to enable VSI");
2312                 goto err_up;
2313         }
2314
2315         /* Enable receiving broadcast packets */
2316         ret = i40e_aq_set_vsi_broadcast(hw, main_vsi->seid, true, NULL);
2317         if (ret != I40E_SUCCESS)
2318                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2319
2320         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2321                 ret = i40e_aq_set_vsi_broadcast(hw, pf->vmdq[i].vsi->seid,
2322                                                 true, NULL);
2323                 if (ret != I40E_SUCCESS)
2324                         PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
2325         }
2326
2327         /* Enable the VLAN promiscuous mode. */
2328         if (pf->vfs) {
2329                 for (i = 0; i < pf->vf_num; i++) {
2330                         vsi = pf->vfs[i].vsi;
2331                         i40e_aq_set_vsi_vlan_promisc(hw, vsi->seid,
2332                                                      true, NULL);
2333                 }
2334         }
2335
2336         /* Enable mac loopback mode */
2337         if (dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_MODE_NONE ||
2338             dev->data->dev_conf.lpbk_mode == I40E_AQ_LB_PHY_LOCAL) {
2339                 ret = i40e_aq_set_lb_modes(hw, dev->data->dev_conf.lpbk_mode, NULL);
2340                 if (ret != I40E_SUCCESS) {
2341                         PMD_DRV_LOG(ERR, "fail to set loopback link");
2342                         goto err_up;
2343                 }
2344         }
2345
2346         /* Apply link configure */
2347         ret = i40e_apply_link_speed(dev);
2348         if (I40E_SUCCESS != ret) {
2349                 PMD_DRV_LOG(ERR, "Fail to apply link setting");
2350                 goto err_up;
2351         }
2352
2353         if (!rte_intr_allow_others(intr_handle)) {
2354                 rte_intr_callback_unregister(intr_handle,
2355                                              i40e_dev_interrupt_handler,
2356                                              (void *)dev);
2357                 /* configure and enable device interrupt */
2358                 i40e_pf_config_irq0(hw, FALSE);
2359                 i40e_pf_enable_irq0(hw);
2360
2361                 if (dev->data->dev_conf.intr_conf.lsc != 0)
2362                         PMD_INIT_LOG(INFO,
2363                                 "lsc won't enable because of no intr multiplex");
2364         } else {
2365                 ret = i40e_aq_set_phy_int_mask(hw,
2366                                                ~(I40E_AQ_EVENT_LINK_UPDOWN |
2367                                                I40E_AQ_EVENT_MODULE_QUAL_FAIL |
2368                                                I40E_AQ_EVENT_MEDIA_NA), NULL);
2369                 if (ret != I40E_SUCCESS)
2370                         PMD_DRV_LOG(WARNING, "Fail to set phy mask");
2371
2372                 /* Call get_link_info aq commond to enable/disable LSE */
2373                 i40e_dev_link_update(dev, 0);
2374         }
2375
2376         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2377                 rte_eal_alarm_set(I40E_ALARM_INTERVAL,
2378                                   i40e_dev_alarm_handler, dev);
2379         } else {
2380                 /* enable uio intr after callback register */
2381                 rte_intr_enable(intr_handle);
2382         }
2383
2384         i40e_filter_restore(pf);
2385
2386         if (pf->tm_conf.root && !pf->tm_conf.committed)
2387                 PMD_DRV_LOG(WARNING,
2388                             "please call hierarchy_commit() "
2389                             "before starting the port");
2390
2391         return I40E_SUCCESS;
2392
2393 err_up:
2394         i40e_dev_switch_queues(pf, FALSE);
2395         i40e_dev_clear_queues(dev);
2396
2397         return ret;
2398 }
2399
2400 static void
2401 i40e_dev_stop(struct rte_eth_dev *dev)
2402 {
2403         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2404         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2405         struct i40e_vsi *main_vsi = pf->main_vsi;
2406         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2407         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2408         int i;
2409
2410         if (hw->adapter_stopped == 1)
2411                 return;
2412
2413         if (dev->data->dev_conf.intr_conf.rxq == 0) {
2414                 rte_eal_alarm_cancel(i40e_dev_alarm_handler, dev);
2415                 rte_intr_enable(intr_handle);
2416         }
2417
2418         /* Disable all queues */
2419         i40e_dev_switch_queues(pf, FALSE);
2420
2421         /* un-map queues with interrupt registers */
2422         i40e_vsi_disable_queues_intr(main_vsi);
2423         i40e_vsi_queues_unbind_intr(main_vsi);
2424
2425         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2426                 i40e_vsi_disable_queues_intr(pf->vmdq[i].vsi);
2427                 i40e_vsi_queues_unbind_intr(pf->vmdq[i].vsi);
2428         }
2429
2430         if (pf->fdir.fdir_vsi) {
2431                 i40e_vsi_queues_unbind_intr(pf->fdir.fdir_vsi);
2432                 i40e_vsi_disable_queues_intr(pf->fdir.fdir_vsi);
2433         }
2434         /* Clear all queues and release memory */
2435         i40e_dev_clear_queues(dev);
2436
2437         /* Set link down */
2438         i40e_dev_set_link_down(dev);
2439
2440         if (!rte_intr_allow_others(intr_handle))
2441                 /* resume to the default handler */
2442                 rte_intr_callback_register(intr_handle,
2443                                            i40e_dev_interrupt_handler,
2444                                            (void *)dev);
2445
2446         /* Clean datapath event and queue/vec mapping */
2447         rte_intr_efd_disable(intr_handle);
2448         if (intr_handle->intr_vec) {
2449                 rte_free(intr_handle->intr_vec);
2450                 intr_handle->intr_vec = NULL;
2451         }
2452
2453         /* reset hierarchy commit */
2454         pf->tm_conf.committed = false;
2455
2456         hw->adapter_stopped = 1;
2457
2458         pf->adapter->rss_reta_updated = 0;
2459 }
2460
2461 static void
2462 i40e_dev_close(struct rte_eth_dev *dev)
2463 {
2464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2465         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2466         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2467         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2468         struct i40e_mirror_rule *p_mirror;
2469         uint32_t reg;
2470         int i;
2471         int ret;
2472
2473         PMD_INIT_FUNC_TRACE();
2474
2475         i40e_dev_stop(dev);
2476
2477         /* Remove all mirror rules */
2478         while ((p_mirror = TAILQ_FIRST(&pf->mirror_list))) {
2479                 ret = i40e_aq_del_mirror_rule(hw,
2480                                               pf->main_vsi->veb->seid,
2481                                               p_mirror->rule_type,
2482                                               p_mirror->entries,
2483                                               p_mirror->num_entries,
2484                                               p_mirror->id);
2485                 if (ret < 0)
2486                         PMD_DRV_LOG(ERR, "failed to remove mirror rule: "
2487                                     "status = %d, aq_err = %d.", ret,
2488                                     hw->aq.asq_last_status);
2489
2490                 /* remove mirror software resource anyway */
2491                 TAILQ_REMOVE(&pf->mirror_list, p_mirror, rules);
2492                 rte_free(p_mirror);
2493                 pf->nb_mirror_rule--;
2494         }
2495
2496         i40e_dev_free_queues(dev);
2497
2498         /* Disable interrupt */
2499         i40e_pf_disable_irq0(hw);
2500         rte_intr_disable(intr_handle);
2501
2502         /*
2503          * Only legacy filter API needs the following fdir config. So when the
2504          * legacy filter API is deprecated, the following code should also be
2505          * removed.
2506          */
2507         i40e_fdir_teardown(pf);
2508
2509         /* shutdown and destroy the HMC */
2510         i40e_shutdown_lan_hmc(hw);
2511
2512         for (i = 0; i < pf->nb_cfg_vmdq_vsi; i++) {
2513                 i40e_vsi_release(pf->vmdq[i].vsi);
2514                 pf->vmdq[i].vsi = NULL;
2515         }
2516         rte_free(pf->vmdq);
2517         pf->vmdq = NULL;
2518
2519         /* release all the existing VSIs and VEBs */
2520         i40e_vsi_release(pf->main_vsi);
2521
2522         /* shutdown the adminq */
2523         i40e_aq_queue_shutdown(hw, true);
2524         i40e_shutdown_adminq(hw);
2525
2526         i40e_res_pool_destroy(&pf->qp_pool);
2527         i40e_res_pool_destroy(&pf->msix_pool);
2528
2529         /* Disable flexible payload in global configuration */
2530         if (!pf->support_multi_driver)
2531                 i40e_flex_payload_reg_set_default(hw);
2532
2533         /* force a PF reset to clean anything leftover */
2534         reg = I40E_READ_REG(hw, I40E_PFGEN_CTRL);
2535         I40E_WRITE_REG(hw, I40E_PFGEN_CTRL,
2536                         (reg | I40E_PFGEN_CTRL_PFSWR_MASK));
2537         I40E_WRITE_FLUSH(hw);
2538
2539         hw->adapter_closed = 1;
2540 }
2541
2542 /*
2543  * Reset PF device only to re-initialize resources in PMD layer
2544  */
2545 static int
2546 i40e_dev_reset(struct rte_eth_dev *dev)
2547 {
2548         int ret;
2549
2550         /* When a DPDK PMD PF begin to reset PF port, it should notify all
2551          * its VF to make them align with it. The detailed notification
2552          * mechanism is PMD specific. As to i40e PF, it is rather complex.
2553          * To avoid unexpected behavior in VF, currently reset of PF with
2554          * SR-IOV activation is not supported. It might be supported later.
2555          */
2556         if (dev->data->sriov.active)
2557                 return -ENOTSUP;
2558
2559         ret = eth_i40e_dev_uninit(dev);
2560         if (ret)
2561                 return ret;
2562
2563         ret = eth_i40e_dev_init(dev, NULL);
2564
2565         return ret;
2566 }
2567
2568 static void
2569 i40e_dev_promiscuous_enable(struct rte_eth_dev *dev)
2570 {
2571         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2572         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2573         struct i40e_vsi *vsi = pf->main_vsi;
2574         int status;
2575
2576         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2577                                                      true, NULL, true);
2578         if (status != I40E_SUCCESS)
2579                 PMD_DRV_LOG(ERR, "Failed to enable unicast promiscuous");
2580
2581         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2582                                                         TRUE, NULL);
2583         if (status != I40E_SUCCESS)
2584                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2585
2586 }
2587
2588 static void
2589 i40e_dev_promiscuous_disable(struct rte_eth_dev *dev)
2590 {
2591         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2592         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2593         struct i40e_vsi *vsi = pf->main_vsi;
2594         int status;
2595
2596         status = i40e_aq_set_vsi_unicast_promiscuous(hw, vsi->seid,
2597                                                      false, NULL, true);
2598         if (status != I40E_SUCCESS)
2599                 PMD_DRV_LOG(ERR, "Failed to disable unicast promiscuous");
2600
2601         /* must remain in all_multicast mode */
2602         if (dev->data->all_multicast == 1)
2603                 return;
2604
2605         status = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid,
2606                                                         false, NULL);
2607         if (status != I40E_SUCCESS)
2608                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2609 }
2610
2611 static void
2612 i40e_dev_allmulticast_enable(struct rte_eth_dev *dev)
2613 {
2614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         struct i40e_vsi *vsi = pf->main_vsi;
2617         int ret;
2618
2619         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vsi->seid, TRUE, NULL);
2620         if (ret != I40E_SUCCESS)
2621                 PMD_DRV_LOG(ERR, "Failed to enable multicast promiscuous");
2622 }
2623
2624 static void
2625 i40e_dev_allmulticast_disable(struct rte_eth_dev *dev)
2626 {
2627         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2628         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2629         struct i40e_vsi *vsi = pf->main_vsi;
2630         int ret;
2631
2632         if (dev->data->promiscuous == 1)
2633                 return; /* must remain in all_multicast mode */
2634
2635         ret = i40e_aq_set_vsi_multicast_promiscuous(hw,
2636                                 vsi->seid, FALSE, NULL);
2637         if (ret != I40E_SUCCESS)
2638                 PMD_DRV_LOG(ERR, "Failed to disable multicast promiscuous");
2639 }
2640
2641 /*
2642  * Set device link up.
2643  */
2644 static int
2645 i40e_dev_set_link_up(struct rte_eth_dev *dev)
2646 {
2647         /* re-apply link speed setting */
2648         return i40e_apply_link_speed(dev);
2649 }
2650
2651 /*
2652  * Set device link down.
2653  */
2654 static int
2655 i40e_dev_set_link_down(struct rte_eth_dev *dev)
2656 {
2657         uint8_t speed = I40E_LINK_SPEED_UNKNOWN;
2658         uint8_t abilities = 0;
2659         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2660
2661         abilities = I40E_AQ_PHY_ENABLE_ATOMIC_LINK;
2662         return i40e_phy_conf_link(hw, abilities, speed, false);
2663 }
2664
2665 static __rte_always_inline void
2666 update_link_reg(struct i40e_hw *hw, struct rte_eth_link *link)
2667 {
2668 /* Link status registers and values*/
2669 #define I40E_PRTMAC_LINKSTA             0x001E2420
2670 #define I40E_REG_LINK_UP                0x40000080
2671 #define I40E_PRTMAC_MACC                0x001E24E0
2672 #define I40E_REG_MACC_25GB              0x00020000
2673 #define I40E_REG_SPEED_MASK             0x38000000
2674 #define I40E_REG_SPEED_0                0x00000000
2675 #define I40E_REG_SPEED_1                0x08000000
2676 #define I40E_REG_SPEED_2                0x10000000
2677 #define I40E_REG_SPEED_3                0x18000000
2678 #define I40E_REG_SPEED_4                0x20000000
2679         uint32_t link_speed;
2680         uint32_t reg_val;
2681
2682         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_LINKSTA);
2683         link_speed = reg_val & I40E_REG_SPEED_MASK;
2684         reg_val &= I40E_REG_LINK_UP;
2685         link->link_status = (reg_val == I40E_REG_LINK_UP) ? 1 : 0;
2686
2687         if (unlikely(link->link_status == 0))
2688                 return;
2689
2690         /* Parse the link status */
2691         switch (link_speed) {
2692         case I40E_REG_SPEED_0:
2693                 link->link_speed = ETH_SPEED_NUM_100M;
2694                 break;
2695         case I40E_REG_SPEED_1:
2696                 link->link_speed = ETH_SPEED_NUM_1G;
2697                 break;
2698         case I40E_REG_SPEED_2:
2699                 if (hw->mac.type == I40E_MAC_X722)
2700                         link->link_speed = ETH_SPEED_NUM_2_5G;
2701                 else
2702                         link->link_speed = ETH_SPEED_NUM_10G;
2703                 break;
2704         case I40E_REG_SPEED_3:
2705                 if (hw->mac.type == I40E_MAC_X722) {
2706                         link->link_speed = ETH_SPEED_NUM_5G;
2707                 } else {
2708                         reg_val = I40E_READ_REG(hw, I40E_PRTMAC_MACC);
2709
2710                         if (reg_val & I40E_REG_MACC_25GB)
2711                                 link->link_speed = ETH_SPEED_NUM_25G;
2712                         else
2713                                 link->link_speed = ETH_SPEED_NUM_40G;
2714                 }
2715                 break;
2716         case I40E_REG_SPEED_4:
2717                 if (hw->mac.type == I40E_MAC_X722)
2718                         link->link_speed = ETH_SPEED_NUM_10G;
2719                 else
2720                         link->link_speed = ETH_SPEED_NUM_20G;
2721                 break;
2722         default:
2723                 PMD_DRV_LOG(ERR, "Unknown link speed info %u", link_speed);
2724                 break;
2725         }
2726 }
2727
2728 static __rte_always_inline void
2729 update_link_aq(struct i40e_hw *hw, struct rte_eth_link *link,
2730         bool enable_lse, int wait_to_complete)
2731 {
2732 #define CHECK_INTERVAL             100  /* 100ms */
2733 #define MAX_REPEAT_TIME            10  /* 1s (10 * 100ms) in total */
2734         uint32_t rep_cnt = MAX_REPEAT_TIME;
2735         struct i40e_link_status link_status;
2736         int status;
2737
2738         memset(&link_status, 0, sizeof(link_status));
2739
2740         do {
2741                 memset(&link_status, 0, sizeof(link_status));
2742
2743                 /* Get link status information from hardware */
2744                 status = i40e_aq_get_link_info(hw, enable_lse,
2745                                                 &link_status, NULL);
2746                 if (unlikely(status != I40E_SUCCESS)) {
2747                         link->link_speed = ETH_SPEED_NUM_100M;
2748                         link->link_duplex = ETH_LINK_FULL_DUPLEX;
2749                         PMD_DRV_LOG(ERR, "Failed to get link info");
2750                         return;
2751                 }
2752
2753                 link->link_status = link_status.link_info & I40E_AQ_LINK_UP;
2754                 if (!wait_to_complete || link->link_status)
2755                         break;
2756
2757                 rte_delay_ms(CHECK_INTERVAL);
2758         } while (--rep_cnt);
2759
2760         /* Parse the link status */
2761         switch (link_status.link_speed) {
2762         case I40E_LINK_SPEED_100MB:
2763                 link->link_speed = ETH_SPEED_NUM_100M;
2764                 break;
2765         case I40E_LINK_SPEED_1GB:
2766                 link->link_speed = ETH_SPEED_NUM_1G;
2767                 break;
2768         case I40E_LINK_SPEED_10GB:
2769                 link->link_speed = ETH_SPEED_NUM_10G;
2770                 break;
2771         case I40E_LINK_SPEED_20GB:
2772                 link->link_speed = ETH_SPEED_NUM_20G;
2773                 break;
2774         case I40E_LINK_SPEED_25GB:
2775                 link->link_speed = ETH_SPEED_NUM_25G;
2776                 break;
2777         case I40E_LINK_SPEED_40GB:
2778                 link->link_speed = ETH_SPEED_NUM_40G;
2779                 break;
2780         default:
2781                 link->link_speed = ETH_SPEED_NUM_100M;
2782                 break;
2783         }
2784 }
2785
2786 int
2787 i40e_dev_link_update(struct rte_eth_dev *dev,
2788                      int wait_to_complete)
2789 {
2790         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2791         struct rte_eth_link link;
2792         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2793         int ret;
2794
2795         memset(&link, 0, sizeof(link));
2796
2797         /* i40e uses full duplex only */
2798         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2799         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2800                         ETH_LINK_SPEED_FIXED);
2801
2802         if (!wait_to_complete && !enable_lse)
2803                 update_link_reg(hw, &link);
2804         else
2805                 update_link_aq(hw, &link, enable_lse, wait_to_complete);
2806
2807         ret = rte_eth_linkstatus_set(dev, &link);
2808         i40e_notify_all_vfs_link_status(dev);
2809
2810         return ret;
2811 }
2812
2813 /* Get all the statistics of a VSI */
2814 void
2815 i40e_update_vsi_stats(struct i40e_vsi *vsi)
2816 {
2817         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
2818         struct i40e_eth_stats *nes = &vsi->eth_stats;
2819         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2820         int idx = rte_le_to_cpu_16(vsi->info.stat_counter_idx);
2821
2822         i40e_stat_update_48(hw, I40E_GLV_GORCH(idx), I40E_GLV_GORCL(idx),
2823                             vsi->offset_loaded, &oes->rx_bytes,
2824                             &nes->rx_bytes);
2825         i40e_stat_update_48(hw, I40E_GLV_UPRCH(idx), I40E_GLV_UPRCL(idx),
2826                             vsi->offset_loaded, &oes->rx_unicast,
2827                             &nes->rx_unicast);
2828         i40e_stat_update_48(hw, I40E_GLV_MPRCH(idx), I40E_GLV_MPRCL(idx),
2829                             vsi->offset_loaded, &oes->rx_multicast,
2830                             &nes->rx_multicast);
2831         i40e_stat_update_48(hw, I40E_GLV_BPRCH(idx), I40E_GLV_BPRCL(idx),
2832                             vsi->offset_loaded, &oes->rx_broadcast,
2833                             &nes->rx_broadcast);
2834         /* exclude CRC bytes */
2835         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
2836                 nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
2837
2838         i40e_stat_update_32(hw, I40E_GLV_RDPC(idx), vsi->offset_loaded,
2839                             &oes->rx_discards, &nes->rx_discards);
2840         /* GLV_REPC not supported */
2841         /* GLV_RMPC not supported */
2842         i40e_stat_update_32(hw, I40E_GLV_RUPP(idx), vsi->offset_loaded,
2843                             &oes->rx_unknown_protocol,
2844                             &nes->rx_unknown_protocol);
2845         i40e_stat_update_48(hw, I40E_GLV_GOTCH(idx), I40E_GLV_GOTCL(idx),
2846                             vsi->offset_loaded, &oes->tx_bytes,
2847                             &nes->tx_bytes);
2848         i40e_stat_update_48(hw, I40E_GLV_UPTCH(idx), I40E_GLV_UPTCL(idx),
2849                             vsi->offset_loaded, &oes->tx_unicast,
2850                             &nes->tx_unicast);
2851         i40e_stat_update_48(hw, I40E_GLV_MPTCH(idx), I40E_GLV_MPTCL(idx),
2852                             vsi->offset_loaded, &oes->tx_multicast,
2853                             &nes->tx_multicast);
2854         i40e_stat_update_48(hw, I40E_GLV_BPTCH(idx), I40E_GLV_BPTCL(idx),
2855                             vsi->offset_loaded,  &oes->tx_broadcast,
2856                             &nes->tx_broadcast);
2857         /* GLV_TDPC not supported */
2858         i40e_stat_update_32(hw, I40E_GLV_TEPC(idx), vsi->offset_loaded,
2859                             &oes->tx_errors, &nes->tx_errors);
2860         vsi->offset_loaded = true;
2861
2862         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats start *******************",
2863                     vsi->vsi_id);
2864         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
2865         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
2866         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
2867         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
2868         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
2869         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
2870                     nes->rx_unknown_protocol);
2871         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
2872         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
2873         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
2874         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
2875         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
2876         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
2877         PMD_DRV_LOG(DEBUG, "***************** VSI[%u] stats end *******************",
2878                     vsi->vsi_id);
2879 }
2880
2881 static void
2882 i40e_read_stats_registers(struct i40e_pf *pf, struct i40e_hw *hw)
2883 {
2884         unsigned int i;
2885         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
2886         struct i40e_hw_port_stats *os = &pf->stats_offset; /* old stats */
2887
2888         /* Get rx/tx bytes of internal transfer packets */
2889         i40e_stat_update_48(hw, I40E_GLV_GORCH(hw->port),
2890                         I40E_GLV_GORCL(hw->port),
2891                         pf->offset_loaded,
2892                         &pf->internal_stats_offset.rx_bytes,
2893                         &pf->internal_stats.rx_bytes);
2894
2895         i40e_stat_update_48(hw, I40E_GLV_GOTCH(hw->port),
2896                         I40E_GLV_GOTCL(hw->port),
2897                         pf->offset_loaded,
2898                         &pf->internal_stats_offset.tx_bytes,
2899                         &pf->internal_stats.tx_bytes);
2900         /* Get total internal rx packet count */
2901         i40e_stat_update_48(hw, I40E_GLV_UPRCH(hw->port),
2902                             I40E_GLV_UPRCL(hw->port),
2903                             pf->offset_loaded,
2904                             &pf->internal_stats_offset.rx_unicast,
2905                             &pf->internal_stats.rx_unicast);
2906         i40e_stat_update_48(hw, I40E_GLV_MPRCH(hw->port),
2907                             I40E_GLV_MPRCL(hw->port),
2908                             pf->offset_loaded,
2909                             &pf->internal_stats_offset.rx_multicast,
2910                             &pf->internal_stats.rx_multicast);
2911         i40e_stat_update_48(hw, I40E_GLV_BPRCH(hw->port),
2912                             I40E_GLV_BPRCL(hw->port),
2913                             pf->offset_loaded,
2914                             &pf->internal_stats_offset.rx_broadcast,
2915                             &pf->internal_stats.rx_broadcast);
2916         /* Get total internal tx packet count */
2917         i40e_stat_update_48(hw, I40E_GLV_UPTCH(hw->port),
2918                             I40E_GLV_UPTCL(hw->port),
2919                             pf->offset_loaded,
2920                             &pf->internal_stats_offset.tx_unicast,
2921                             &pf->internal_stats.tx_unicast);
2922         i40e_stat_update_48(hw, I40E_GLV_MPTCH(hw->port),
2923                             I40E_GLV_MPTCL(hw->port),
2924                             pf->offset_loaded,
2925                             &pf->internal_stats_offset.tx_multicast,
2926                             &pf->internal_stats.tx_multicast);
2927         i40e_stat_update_48(hw, I40E_GLV_BPTCH(hw->port),
2928                             I40E_GLV_BPTCL(hw->port),
2929                             pf->offset_loaded,
2930                             &pf->internal_stats_offset.tx_broadcast,
2931                             &pf->internal_stats.tx_broadcast);
2932
2933         /* exclude CRC size */
2934         pf->internal_stats.rx_bytes -= (pf->internal_stats.rx_unicast +
2935                 pf->internal_stats.rx_multicast +
2936                 pf->internal_stats.rx_broadcast) * RTE_ETHER_CRC_LEN;
2937
2938         /* Get statistics of struct i40e_eth_stats */
2939         i40e_stat_update_48(hw, I40E_GLPRT_GORCH(hw->port),
2940                             I40E_GLPRT_GORCL(hw->port),
2941                             pf->offset_loaded, &os->eth.rx_bytes,
2942                             &ns->eth.rx_bytes);
2943         i40e_stat_update_48(hw, I40E_GLPRT_UPRCH(hw->port),
2944                             I40E_GLPRT_UPRCL(hw->port),
2945                             pf->offset_loaded, &os->eth.rx_unicast,
2946                             &ns->eth.rx_unicast);
2947         i40e_stat_update_48(hw, I40E_GLPRT_MPRCH(hw->port),
2948                             I40E_GLPRT_MPRCL(hw->port),
2949                             pf->offset_loaded, &os->eth.rx_multicast,
2950                             &ns->eth.rx_multicast);
2951         i40e_stat_update_48(hw, I40E_GLPRT_BPRCH(hw->port),
2952                             I40E_GLPRT_BPRCL(hw->port),
2953                             pf->offset_loaded, &os->eth.rx_broadcast,
2954                             &ns->eth.rx_broadcast);
2955         /* Workaround: CRC size should not be included in byte statistics,
2956          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
2957          * packet.
2958          */
2959         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
2960                 ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
2961
2962         /* exclude internal rx bytes
2963          * Workaround: it is possible I40E_GLV_GORCH[H/L] is updated before
2964          * I40E_GLPRT_GORCH[H/L], so there is a small window that cause negative
2965          * value.
2966          * same to I40E_GLV_UPRC[H/L], I40E_GLV_MPRC[H/L], I40E_GLV_BPRC[H/L].
2967          */
2968         if (ns->eth.rx_bytes < pf->internal_stats.rx_bytes)
2969                 ns->eth.rx_bytes = 0;
2970         else
2971                 ns->eth.rx_bytes -= pf->internal_stats.rx_bytes;
2972
2973         if (ns->eth.rx_unicast < pf->internal_stats.rx_unicast)
2974                 ns->eth.rx_unicast = 0;
2975         else
2976                 ns->eth.rx_unicast -= pf->internal_stats.rx_unicast;
2977
2978         if (ns->eth.rx_multicast < pf->internal_stats.rx_multicast)
2979                 ns->eth.rx_multicast = 0;
2980         else
2981                 ns->eth.rx_multicast -= pf->internal_stats.rx_multicast;
2982
2983         if (ns->eth.rx_broadcast < pf->internal_stats.rx_broadcast)
2984                 ns->eth.rx_broadcast = 0;
2985         else
2986                 ns->eth.rx_broadcast -= pf->internal_stats.rx_broadcast;
2987
2988         i40e_stat_update_32(hw, I40E_GLPRT_RDPC(hw->port),
2989                             pf->offset_loaded, &os->eth.rx_discards,
2990                             &ns->eth.rx_discards);
2991         /* GLPRT_REPC not supported */
2992         /* GLPRT_RMPC not supported */
2993         i40e_stat_update_32(hw, I40E_GLPRT_RUPP(hw->port),
2994                             pf->offset_loaded,
2995                             &os->eth.rx_unknown_protocol,
2996                             &ns->eth.rx_unknown_protocol);
2997         i40e_stat_update_48(hw, I40E_GLPRT_GOTCH(hw->port),
2998                             I40E_GLPRT_GOTCL(hw->port),
2999                             pf->offset_loaded, &os->eth.tx_bytes,
3000                             &ns->eth.tx_bytes);
3001         i40e_stat_update_48(hw, I40E_GLPRT_UPTCH(hw->port),
3002                             I40E_GLPRT_UPTCL(hw->port),
3003                             pf->offset_loaded, &os->eth.tx_unicast,
3004                             &ns->eth.tx_unicast);
3005         i40e_stat_update_48(hw, I40E_GLPRT_MPTCH(hw->port),
3006                             I40E_GLPRT_MPTCL(hw->port),
3007                             pf->offset_loaded, &os->eth.tx_multicast,
3008                             &ns->eth.tx_multicast);
3009         i40e_stat_update_48(hw, I40E_GLPRT_BPTCH(hw->port),
3010                             I40E_GLPRT_BPTCL(hw->port),
3011                             pf->offset_loaded, &os->eth.tx_broadcast,
3012                             &ns->eth.tx_broadcast);
3013         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3014                 ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
3015
3016         /* exclude internal tx bytes
3017          * Workaround: it is possible I40E_GLV_GOTCH[H/L] is updated before
3018          * I40E_GLPRT_GOTCH[H/L], so there is a small window that cause negative
3019          * value.
3020          * same to I40E_GLV_UPTC[H/L], I40E_GLV_MPTC[H/L], I40E_GLV_BPTC[H/L].
3021          */
3022         if (ns->eth.tx_bytes < pf->internal_stats.tx_bytes)
3023                 ns->eth.tx_bytes = 0;
3024         else
3025                 ns->eth.tx_bytes -= pf->internal_stats.tx_bytes;
3026
3027         if (ns->eth.tx_unicast < pf->internal_stats.tx_unicast)
3028                 ns->eth.tx_unicast = 0;
3029         else
3030                 ns->eth.tx_unicast -= pf->internal_stats.tx_unicast;
3031
3032         if (ns->eth.tx_multicast < pf->internal_stats.tx_multicast)
3033                 ns->eth.tx_multicast = 0;
3034         else
3035                 ns->eth.tx_multicast -= pf->internal_stats.tx_multicast;
3036
3037         if (ns->eth.tx_broadcast < pf->internal_stats.tx_broadcast)
3038                 ns->eth.tx_broadcast = 0;
3039         else
3040                 ns->eth.tx_broadcast -= pf->internal_stats.tx_broadcast;
3041
3042         /* GLPRT_TEPC not supported */
3043
3044         /* additional port specific stats */
3045         i40e_stat_update_32(hw, I40E_GLPRT_TDOLD(hw->port),
3046                             pf->offset_loaded, &os->tx_dropped_link_down,
3047                             &ns->tx_dropped_link_down);
3048         i40e_stat_update_32(hw, I40E_GLPRT_CRCERRS(hw->port),
3049                             pf->offset_loaded, &os->crc_errors,
3050                             &ns->crc_errors);
3051         i40e_stat_update_32(hw, I40E_GLPRT_ILLERRC(hw->port),
3052                             pf->offset_loaded, &os->illegal_bytes,
3053                             &ns->illegal_bytes);
3054         /* GLPRT_ERRBC not supported */
3055         i40e_stat_update_32(hw, I40E_GLPRT_MLFC(hw->port),
3056                             pf->offset_loaded, &os->mac_local_faults,
3057                             &ns->mac_local_faults);
3058         i40e_stat_update_32(hw, I40E_GLPRT_MRFC(hw->port),
3059                             pf->offset_loaded, &os->mac_remote_faults,
3060                             &ns->mac_remote_faults);
3061         i40e_stat_update_32(hw, I40E_GLPRT_RLEC(hw->port),
3062                             pf->offset_loaded, &os->rx_length_errors,
3063                             &ns->rx_length_errors);
3064         i40e_stat_update_32(hw, I40E_GLPRT_LXONRXC(hw->port),
3065                             pf->offset_loaded, &os->link_xon_rx,
3066                             &ns->link_xon_rx);
3067         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
3068                             pf->offset_loaded, &os->link_xoff_rx,
3069                             &ns->link_xoff_rx);
3070         for (i = 0; i < 8; i++) {
3071                 i40e_stat_update_32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
3072                                     pf->offset_loaded,
3073                                     &os->priority_xon_rx[i],
3074                                     &ns->priority_xon_rx[i]);
3075                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
3076                                     pf->offset_loaded,
3077                                     &os->priority_xoff_rx[i],
3078                                     &ns->priority_xoff_rx[i]);
3079         }
3080         i40e_stat_update_32(hw, I40E_GLPRT_LXONTXC(hw->port),
3081                             pf->offset_loaded, &os->link_xon_tx,
3082                             &ns->link_xon_tx);
3083         i40e_stat_update_32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
3084                             pf->offset_loaded, &os->link_xoff_tx,
3085                             &ns->link_xoff_tx);
3086         for (i = 0; i < 8; i++) {
3087                 i40e_stat_update_32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
3088                                     pf->offset_loaded,
3089                                     &os->priority_xon_tx[i],
3090                                     &ns->priority_xon_tx[i]);
3091                 i40e_stat_update_32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
3092                                     pf->offset_loaded,
3093                                     &os->priority_xoff_tx[i],
3094                                     &ns->priority_xoff_tx[i]);
3095                 i40e_stat_update_32(hw, I40E_GLPRT_RXON2OFFCNT(hw->port, i),
3096                                     pf->offset_loaded,
3097                                     &os->priority_xon_2_xoff[i],
3098                                     &ns->priority_xon_2_xoff[i]);
3099         }
3100         i40e_stat_update_48(hw, I40E_GLPRT_PRC64H(hw->port),
3101                             I40E_GLPRT_PRC64L(hw->port),
3102                             pf->offset_loaded, &os->rx_size_64,
3103                             &ns->rx_size_64);
3104         i40e_stat_update_48(hw, I40E_GLPRT_PRC127H(hw->port),
3105                             I40E_GLPRT_PRC127L(hw->port),
3106                             pf->offset_loaded, &os->rx_size_127,
3107                             &ns->rx_size_127);
3108         i40e_stat_update_48(hw, I40E_GLPRT_PRC255H(hw->port),
3109                             I40E_GLPRT_PRC255L(hw->port),
3110                             pf->offset_loaded, &os->rx_size_255,
3111                             &ns->rx_size_255);
3112         i40e_stat_update_48(hw, I40E_GLPRT_PRC511H(hw->port),
3113                             I40E_GLPRT_PRC511L(hw->port),
3114                             pf->offset_loaded, &os->rx_size_511,
3115                             &ns->rx_size_511);
3116         i40e_stat_update_48(hw, I40E_GLPRT_PRC1023H(hw->port),
3117                             I40E_GLPRT_PRC1023L(hw->port),
3118                             pf->offset_loaded, &os->rx_size_1023,
3119                             &ns->rx_size_1023);
3120         i40e_stat_update_48(hw, I40E_GLPRT_PRC1522H(hw->port),
3121                             I40E_GLPRT_PRC1522L(hw->port),
3122                             pf->offset_loaded, &os->rx_size_1522,
3123                             &ns->rx_size_1522);
3124         i40e_stat_update_48(hw, I40E_GLPRT_PRC9522H(hw->port),
3125                             I40E_GLPRT_PRC9522L(hw->port),
3126                             pf->offset_loaded, &os->rx_size_big,
3127                             &ns->rx_size_big);
3128         i40e_stat_update_32(hw, I40E_GLPRT_RUC(hw->port),
3129                             pf->offset_loaded, &os->rx_undersize,
3130                             &ns->rx_undersize);
3131         i40e_stat_update_32(hw, I40E_GLPRT_RFC(hw->port),
3132                             pf->offset_loaded, &os->rx_fragments,
3133                             &ns->rx_fragments);
3134         i40e_stat_update_32(hw, I40E_GLPRT_ROC(hw->port),
3135                             pf->offset_loaded, &os->rx_oversize,
3136                             &ns->rx_oversize);
3137         i40e_stat_update_32(hw, I40E_GLPRT_RJC(hw->port),
3138                             pf->offset_loaded, &os->rx_jabber,
3139                             &ns->rx_jabber);
3140         i40e_stat_update_48(hw, I40E_GLPRT_PTC64H(hw->port),
3141                             I40E_GLPRT_PTC64L(hw->port),
3142                             pf->offset_loaded, &os->tx_size_64,
3143                             &ns->tx_size_64);
3144         i40e_stat_update_48(hw, I40E_GLPRT_PTC127H(hw->port),
3145                             I40E_GLPRT_PTC127L(hw->port),
3146                             pf->offset_loaded, &os->tx_size_127,
3147                             &ns->tx_size_127);
3148         i40e_stat_update_48(hw, I40E_GLPRT_PTC255H(hw->port),
3149                             I40E_GLPRT_PTC255L(hw->port),
3150                             pf->offset_loaded, &os->tx_size_255,
3151                             &ns->tx_size_255);
3152         i40e_stat_update_48(hw, I40E_GLPRT_PTC511H(hw->port),
3153                             I40E_GLPRT_PTC511L(hw->port),
3154                             pf->offset_loaded, &os->tx_size_511,
3155                             &ns->tx_size_511);
3156         i40e_stat_update_48(hw, I40E_GLPRT_PTC1023H(hw->port),
3157                             I40E_GLPRT_PTC1023L(hw->port),
3158                             pf->offset_loaded, &os->tx_size_1023,
3159                             &ns->tx_size_1023);
3160         i40e_stat_update_48(hw, I40E_GLPRT_PTC1522H(hw->port),
3161                             I40E_GLPRT_PTC1522L(hw->port),
3162                             pf->offset_loaded, &os->tx_size_1522,
3163                             &ns->tx_size_1522);
3164         i40e_stat_update_48(hw, I40E_GLPRT_PTC9522H(hw->port),
3165                             I40E_GLPRT_PTC9522L(hw->port),
3166                             pf->offset_loaded, &os->tx_size_big,
3167                             &ns->tx_size_big);
3168         i40e_stat_update_32(hw, I40E_GLQF_PCNT(pf->fdir.match_counter_index),
3169                            pf->offset_loaded,
3170                            &os->fd_sb_match, &ns->fd_sb_match);
3171         /* GLPRT_MSPDC not supported */
3172         /* GLPRT_XEC not supported */
3173
3174         pf->offset_loaded = true;
3175
3176         if (pf->main_vsi)
3177                 i40e_update_vsi_stats(pf->main_vsi);
3178 }
3179
3180 /* Get all statistics of a port */
3181 static int
3182 i40e_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3183 {
3184         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3185         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3186         struct i40e_hw_port_stats *ns = &pf->stats; /* new stats */
3187         struct i40e_vsi *vsi;
3188         unsigned i;
3189
3190         /* call read registers - updates values, now write them to struct */
3191         i40e_read_stats_registers(pf, hw);
3192
3193         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3194                         pf->main_vsi->eth_stats.rx_multicast +
3195                         pf->main_vsi->eth_stats.rx_broadcast -
3196                         pf->main_vsi->eth_stats.rx_discards;
3197         stats->opackets = ns->eth.tx_unicast +
3198                         ns->eth.tx_multicast +
3199                         ns->eth.tx_broadcast;
3200         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3201         stats->obytes   = ns->eth.tx_bytes;
3202         stats->oerrors  = ns->eth.tx_errors +
3203                         pf->main_vsi->eth_stats.tx_errors;
3204
3205         /* Rx Errors */
3206         stats->imissed  = ns->eth.rx_discards +
3207                         pf->main_vsi->eth_stats.rx_discards;
3208         stats->ierrors  = ns->crc_errors +
3209                         ns->rx_length_errors + ns->rx_undersize +
3210                         ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3211
3212         if (pf->vfs) {
3213                 for (i = 0; i < pf->vf_num; i++) {
3214                         vsi = pf->vfs[i].vsi;
3215                         i40e_update_vsi_stats(vsi);
3216
3217                         stats->ipackets += (vsi->eth_stats.rx_unicast +
3218                                         vsi->eth_stats.rx_multicast +
3219                                         vsi->eth_stats.rx_broadcast -
3220                                         vsi->eth_stats.rx_discards);
3221                         stats->ibytes   += vsi->eth_stats.rx_bytes;
3222                         stats->oerrors  += vsi->eth_stats.tx_errors;
3223                         stats->imissed  += vsi->eth_stats.rx_discards;
3224                 }
3225         }
3226
3227         PMD_DRV_LOG(DEBUG, "***************** PF stats start *******************");
3228         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", ns->eth.rx_bytes);
3229         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", ns->eth.rx_unicast);
3230         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", ns->eth.rx_multicast);
3231         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", ns->eth.rx_broadcast);
3232         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", ns->eth.rx_discards);
3233         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3234                     ns->eth.rx_unknown_protocol);
3235         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", ns->eth.tx_bytes);
3236         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", ns->eth.tx_unicast);
3237         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", ns->eth.tx_multicast);
3238         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", ns->eth.tx_broadcast);
3239         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", ns->eth.tx_discards);
3240         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", ns->eth.tx_errors);
3241
3242         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:     %"PRIu64"",
3243                     ns->tx_dropped_link_down);
3244         PMD_DRV_LOG(DEBUG, "crc_errors:               %"PRIu64"", ns->crc_errors);
3245         PMD_DRV_LOG(DEBUG, "illegal_bytes:            %"PRIu64"",
3246                     ns->illegal_bytes);
3247         PMD_DRV_LOG(DEBUG, "error_bytes:              %"PRIu64"", ns->error_bytes);
3248         PMD_DRV_LOG(DEBUG, "mac_local_faults:         %"PRIu64"",
3249                     ns->mac_local_faults);
3250         PMD_DRV_LOG(DEBUG, "mac_remote_faults:        %"PRIu64"",
3251                     ns->mac_remote_faults);
3252         PMD_DRV_LOG(DEBUG, "rx_length_errors:         %"PRIu64"",
3253                     ns->rx_length_errors);
3254         PMD_DRV_LOG(DEBUG, "link_xon_rx:              %"PRIu64"", ns->link_xon_rx);
3255         PMD_DRV_LOG(DEBUG, "link_xoff_rx:             %"PRIu64"", ns->link_xoff_rx);
3256         for (i = 0; i < 8; i++) {
3257                 PMD_DRV_LOG(DEBUG, "priority_xon_rx[%d]:      %"PRIu64"",
3258                                 i, ns->priority_xon_rx[i]);
3259                 PMD_DRV_LOG(DEBUG, "priority_xoff_rx[%d]:     %"PRIu64"",
3260                                 i, ns->priority_xoff_rx[i]);
3261         }
3262         PMD_DRV_LOG(DEBUG, "link_xon_tx:              %"PRIu64"", ns->link_xon_tx);
3263         PMD_DRV_LOG(DEBUG, "link_xoff_tx:             %"PRIu64"", ns->link_xoff_tx);
3264         for (i = 0; i < 8; i++) {
3265                 PMD_DRV_LOG(DEBUG, "priority_xon_tx[%d]:      %"PRIu64"",
3266                                 i, ns->priority_xon_tx[i]);
3267                 PMD_DRV_LOG(DEBUG, "priority_xoff_tx[%d]:     %"PRIu64"",
3268                                 i, ns->priority_xoff_tx[i]);
3269                 PMD_DRV_LOG(DEBUG, "priority_xon_2_xoff[%d]:  %"PRIu64"",
3270                                 i, ns->priority_xon_2_xoff[i]);
3271         }
3272         PMD_DRV_LOG(DEBUG, "rx_size_64:               %"PRIu64"", ns->rx_size_64);
3273         PMD_DRV_LOG(DEBUG, "rx_size_127:              %"PRIu64"", ns->rx_size_127);
3274         PMD_DRV_LOG(DEBUG, "rx_size_255:              %"PRIu64"", ns->rx_size_255);
3275         PMD_DRV_LOG(DEBUG, "rx_size_511:              %"PRIu64"", ns->rx_size_511);
3276         PMD_DRV_LOG(DEBUG, "rx_size_1023:             %"PRIu64"", ns->rx_size_1023);
3277         PMD_DRV_LOG(DEBUG, "rx_size_1522:             %"PRIu64"", ns->rx_size_1522);
3278         PMD_DRV_LOG(DEBUG, "rx_size_big:              %"PRIu64"", ns->rx_size_big);
3279         PMD_DRV_LOG(DEBUG, "rx_undersize:             %"PRIu64"", ns->rx_undersize);
3280         PMD_DRV_LOG(DEBUG, "rx_fragments:             %"PRIu64"", ns->rx_fragments);
3281         PMD_DRV_LOG(DEBUG, "rx_oversize:              %"PRIu64"", ns->rx_oversize);
3282         PMD_DRV_LOG(DEBUG, "rx_jabber:                %"PRIu64"", ns->rx_jabber);
3283         PMD_DRV_LOG(DEBUG, "tx_size_64:               %"PRIu64"", ns->tx_size_64);
3284         PMD_DRV_LOG(DEBUG, "tx_size_127:              %"PRIu64"", ns->tx_size_127);
3285         PMD_DRV_LOG(DEBUG, "tx_size_255:              %"PRIu64"", ns->tx_size_255);
3286         PMD_DRV_LOG(DEBUG, "tx_size_511:              %"PRIu64"", ns->tx_size_511);
3287         PMD_DRV_LOG(DEBUG, "tx_size_1023:             %"PRIu64"", ns->tx_size_1023);
3288         PMD_DRV_LOG(DEBUG, "tx_size_1522:             %"PRIu64"", ns->tx_size_1522);
3289         PMD_DRV_LOG(DEBUG, "tx_size_big:              %"PRIu64"", ns->tx_size_big);
3290         PMD_DRV_LOG(DEBUG, "mac_short_packet_dropped: %"PRIu64"",
3291                         ns->mac_short_packet_dropped);
3292         PMD_DRV_LOG(DEBUG, "checksum_error:           %"PRIu64"",
3293                     ns->checksum_error);
3294         PMD_DRV_LOG(DEBUG, "fdir_match:               %"PRIu64"", ns->fd_sb_match);
3295         PMD_DRV_LOG(DEBUG, "***************** PF stats end ********************");
3296         return 0;
3297 }
3298
3299 /* Reset the statistics */
3300 static void
3301 i40e_dev_stats_reset(struct rte_eth_dev *dev)
3302 {
3303         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3304         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3305
3306         /* Mark PF and VSI stats to update the offset, aka "reset" */
3307         pf->offset_loaded = false;
3308         if (pf->main_vsi)
3309                 pf->main_vsi->offset_loaded = false;
3310
3311         /* read the stats, reading current register values into offset */
3312         i40e_read_stats_registers(pf, hw);
3313 }
3314
3315 static uint32_t
3316 i40e_xstats_calc_num(void)
3317 {
3318         return I40E_NB_ETH_XSTATS + I40E_NB_HW_PORT_XSTATS +
3319                 (I40E_NB_RXQ_PRIO_XSTATS * 8) +
3320                 (I40E_NB_TXQ_PRIO_XSTATS * 8);
3321 }
3322
3323 static int i40e_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3324                                      struct rte_eth_xstat_name *xstats_names,
3325                                      __rte_unused unsigned limit)
3326 {
3327         unsigned count = 0;
3328         unsigned i, prio;
3329
3330         if (xstats_names == NULL)
3331                 return i40e_xstats_calc_num();
3332
3333         /* Note: limit checked in rte_eth_xstats_names() */
3334
3335         /* Get stats from i40e_eth_stats struct */
3336         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3337                 strlcpy(xstats_names[count].name,
3338                         rte_i40e_stats_strings[i].name,
3339                         sizeof(xstats_names[count].name));
3340                 count++;
3341         }
3342
3343         /* Get individiual stats from i40e_hw_port struct */
3344         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3345                 strlcpy(xstats_names[count].name,
3346                         rte_i40e_hw_port_strings[i].name,
3347                         sizeof(xstats_names[count].name));
3348                 count++;
3349         }
3350
3351         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3352                 for (prio = 0; prio < 8; prio++) {
3353                         snprintf(xstats_names[count].name,
3354                                  sizeof(xstats_names[count].name),
3355                                  "rx_priority%u_%s", prio,
3356                                  rte_i40e_rxq_prio_strings[i].name);
3357                         count++;
3358                 }
3359         }
3360
3361         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3362                 for (prio = 0; prio < 8; prio++) {
3363                         snprintf(xstats_names[count].name,
3364                                  sizeof(xstats_names[count].name),
3365                                  "tx_priority%u_%s", prio,
3366                                  rte_i40e_txq_prio_strings[i].name);
3367                         count++;
3368                 }
3369         }
3370         return count;
3371 }
3372
3373 static int
3374 i40e_dev_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3375                     unsigned n)
3376 {
3377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3379         unsigned i, count, prio;
3380         struct i40e_hw_port_stats *hw_stats = &pf->stats;
3381
3382         count = i40e_xstats_calc_num();
3383         if (n < count)
3384                 return count;
3385
3386         i40e_read_stats_registers(pf, hw);
3387
3388         if (xstats == NULL)
3389                 return 0;
3390
3391         count = 0;
3392
3393         /* Get stats from i40e_eth_stats struct */
3394         for (i = 0; i < I40E_NB_ETH_XSTATS; i++) {
3395                 xstats[count].value = *(uint64_t *)(((char *)&hw_stats->eth) +
3396                         rte_i40e_stats_strings[i].offset);
3397                 xstats[count].id = count;
3398                 count++;
3399         }
3400
3401         /* Get individiual stats from i40e_hw_port struct */
3402         for (i = 0; i < I40E_NB_HW_PORT_XSTATS; i++) {
3403                 xstats[count].value = *(uint64_t *)(((char *)hw_stats) +
3404                         rte_i40e_hw_port_strings[i].offset);
3405                 xstats[count].id = count;
3406                 count++;
3407         }
3408
3409         for (i = 0; i < I40E_NB_RXQ_PRIO_XSTATS; i++) {
3410                 for (prio = 0; prio < 8; prio++) {
3411                         xstats[count].value =
3412                                 *(uint64_t *)(((char *)hw_stats) +
3413                                 rte_i40e_rxq_prio_strings[i].offset +
3414                                 (sizeof(uint64_t) * prio));
3415                         xstats[count].id = count;
3416                         count++;
3417                 }
3418         }
3419
3420         for (i = 0; i < I40E_NB_TXQ_PRIO_XSTATS; i++) {
3421                 for (prio = 0; prio < 8; prio++) {
3422                         xstats[count].value =
3423                                 *(uint64_t *)(((char *)hw_stats) +
3424                                 rte_i40e_txq_prio_strings[i].offset +
3425                                 (sizeof(uint64_t) * prio));
3426                         xstats[count].id = count;
3427                         count++;
3428                 }
3429         }
3430
3431         return count;
3432 }
3433
3434 static int
3435 i40e_dev_queue_stats_mapping_set(__rte_unused struct rte_eth_dev *dev,
3436                                  __rte_unused uint16_t queue_id,
3437                                  __rte_unused uint8_t stat_idx,
3438                                  __rte_unused uint8_t is_rx)
3439 {
3440         PMD_INIT_FUNC_TRACE();
3441
3442         return -ENOSYS;
3443 }
3444
3445 static int
3446 i40e_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
3447 {
3448         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3449         u32 full_ver;
3450         u8 ver, patch;
3451         u16 build;
3452         int ret;
3453
3454         full_ver = hw->nvm.oem_ver;
3455         ver = (u8)(full_ver >> 24);
3456         build = (u16)((full_ver >> 8) & 0xffff);
3457         patch = (u8)(full_ver & 0xff);
3458
3459         ret = snprintf(fw_version, fw_size,
3460                  "%d.%d%d 0x%08x %d.%d.%d",
3461                  ((hw->nvm.version >> 12) & 0xf),
3462                  ((hw->nvm.version >> 4) & 0xff),
3463                  (hw->nvm.version & 0xf), hw->nvm.eetrack,
3464                  ver, build, patch);
3465
3466         ret += 1; /* add the size of '\0' */
3467         if (fw_size < (u32)ret)
3468                 return ret;
3469         else
3470                 return 0;
3471 }
3472
3473 /*
3474  * When using NVM 6.01(for X710 XL710 XXV710)/3.33(for X722) or later,
3475  * the Rx data path does not hang if the FW LLDP is stopped.
3476  * return true if lldp need to stop
3477  * return false if we cannot disable the LLDP to avoid Rx data path blocking.
3478  */
3479 static bool
3480 i40e_need_stop_lldp(struct rte_eth_dev *dev)
3481 {
3482         double nvm_ver;
3483         char ver_str[64] = {0};
3484         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3485
3486         i40e_fw_version_get(dev, ver_str, 64);
3487         nvm_ver = atof(ver_str);
3488         if ((hw->mac.type == I40E_MAC_X722 ||
3489              hw->mac.type == I40E_MAC_X722_VF) &&
3490              ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(3.33 * 1000)))
3491                 return true;
3492         else if ((uint32_t)(nvm_ver * 1000) >= (uint32_t)(6.01 * 1000))
3493                 return true;
3494
3495         return false;
3496 }
3497
3498 static void
3499 i40e_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3500 {
3501         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3502         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3503         struct i40e_vsi *vsi = pf->main_vsi;
3504         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
3505
3506         dev_info->max_rx_queues = vsi->nb_qps;
3507         dev_info->max_tx_queues = vsi->nb_qps;
3508         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
3509         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
3510         dev_info->max_mac_addrs = vsi->max_macaddrs;
3511         dev_info->max_vfs = pci_dev->max_vfs;
3512         dev_info->max_mtu = dev_info->max_rx_pktlen - I40E_ETH_OVERHEAD;
3513         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3514         dev_info->rx_queue_offload_capa = 0;
3515         dev_info->rx_offload_capa =
3516                 DEV_RX_OFFLOAD_VLAN_STRIP |
3517                 DEV_RX_OFFLOAD_QINQ_STRIP |
3518                 DEV_RX_OFFLOAD_IPV4_CKSUM |
3519                 DEV_RX_OFFLOAD_UDP_CKSUM |
3520                 DEV_RX_OFFLOAD_TCP_CKSUM |
3521                 DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3522                 DEV_RX_OFFLOAD_KEEP_CRC |
3523                 DEV_RX_OFFLOAD_SCATTER |
3524                 DEV_RX_OFFLOAD_VLAN_EXTEND |
3525                 DEV_RX_OFFLOAD_VLAN_FILTER |
3526                 DEV_RX_OFFLOAD_JUMBO_FRAME;
3527
3528         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3529         dev_info->tx_offload_capa =
3530                 DEV_TX_OFFLOAD_VLAN_INSERT |
3531                 DEV_TX_OFFLOAD_QINQ_INSERT |
3532                 DEV_TX_OFFLOAD_IPV4_CKSUM |
3533                 DEV_TX_OFFLOAD_UDP_CKSUM |
3534                 DEV_TX_OFFLOAD_TCP_CKSUM |
3535                 DEV_TX_OFFLOAD_SCTP_CKSUM |
3536                 DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3537                 DEV_TX_OFFLOAD_TCP_TSO |
3538                 DEV_TX_OFFLOAD_VXLAN_TNL_TSO |
3539                 DEV_TX_OFFLOAD_GRE_TNL_TSO |
3540                 DEV_TX_OFFLOAD_IPIP_TNL_TSO |
3541                 DEV_TX_OFFLOAD_GENEVE_TNL_TSO |
3542                 DEV_TX_OFFLOAD_MULTI_SEGS |
3543                 dev_info->tx_queue_offload_capa;
3544         dev_info->dev_capa =
3545                 RTE_ETH_DEV_CAPA_RUNTIME_RX_QUEUE_SETUP |
3546                 RTE_ETH_DEV_CAPA_RUNTIME_TX_QUEUE_SETUP;
3547
3548         dev_info->hash_key_size = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
3549                                                 sizeof(uint32_t);
3550         dev_info->reta_size = pf->hash_lut_size;
3551         dev_info->flow_type_rss_offloads = pf->adapter->flow_types_mask;
3552
3553         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3554                 .rx_thresh = {
3555                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
3556                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
3557                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
3558                 },
3559                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
3560                 .rx_drop_en = 0,
3561                 .offloads = 0,
3562         };
3563
3564         dev_info->default_txconf = (struct rte_eth_txconf) {
3565                 .tx_thresh = {
3566                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
3567                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
3568                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
3569                 },
3570                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
3571                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
3572                 .offloads = 0,
3573         };
3574
3575         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3576                 .nb_max = I40E_MAX_RING_DESC,
3577                 .nb_min = I40E_MIN_RING_DESC,
3578                 .nb_align = I40E_ALIGN_RING_DESC,
3579         };
3580
3581         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3582                 .nb_max = I40E_MAX_RING_DESC,
3583                 .nb_min = I40E_MIN_RING_DESC,
3584                 .nb_align = I40E_ALIGN_RING_DESC,
3585                 .nb_seg_max = I40E_TX_MAX_SEG,
3586                 .nb_mtu_seg_max = I40E_TX_MAX_MTU_SEG,
3587         };
3588
3589         if (pf->flags & I40E_FLAG_VMDQ) {
3590                 dev_info->max_vmdq_pools = pf->max_nb_vmdq_vsi;
3591                 dev_info->vmdq_queue_base = dev_info->max_rx_queues;
3592                 dev_info->vmdq_queue_num = pf->vmdq_nb_qps *
3593                                                 pf->max_nb_vmdq_vsi;
3594                 dev_info->vmdq_pool_base = I40E_VMDQ_POOL_BASE;
3595                 dev_info->max_rx_queues += dev_info->vmdq_queue_num;
3596                 dev_info->max_tx_queues += dev_info->vmdq_queue_num;
3597         }
3598
3599         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3600                 /* For XL710 */
3601                 dev_info->speed_capa = ETH_LINK_SPEED_40G;
3602                 dev_info->default_rxportconf.nb_queues = 2;
3603                 dev_info->default_txportconf.nb_queues = 2;
3604                 if (dev->data->nb_rx_queues == 1)
3605                         dev_info->default_rxportconf.ring_size = 2048;
3606                 else
3607                         dev_info->default_rxportconf.ring_size = 1024;
3608                 if (dev->data->nb_tx_queues == 1)
3609                         dev_info->default_txportconf.ring_size = 1024;
3610                 else
3611                         dev_info->default_txportconf.ring_size = 512;
3612
3613         } else if (I40E_PHY_TYPE_SUPPORT_25G(hw->phy.phy_types)) {
3614                 /* For XXV710 */
3615                 dev_info->speed_capa = ETH_LINK_SPEED_25G;
3616                 dev_info->default_rxportconf.nb_queues = 1;
3617                 dev_info->default_txportconf.nb_queues = 1;
3618                 dev_info->default_rxportconf.ring_size = 256;
3619                 dev_info->default_txportconf.ring_size = 256;
3620         } else {
3621                 /* For X710 */
3622                 dev_info->speed_capa = ETH_LINK_SPEED_1G | ETH_LINK_SPEED_10G;
3623                 dev_info->default_rxportconf.nb_queues = 1;
3624                 dev_info->default_txportconf.nb_queues = 1;
3625                 if (dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_10G) {
3626                         dev_info->default_rxportconf.ring_size = 512;
3627                         dev_info->default_txportconf.ring_size = 256;
3628                 } else {
3629                         dev_info->default_rxportconf.ring_size = 256;
3630                         dev_info->default_txportconf.ring_size = 256;
3631                 }
3632         }
3633         dev_info->default_rxportconf.burst_size = 32;
3634         dev_info->default_txportconf.burst_size = 32;
3635 }
3636
3637 static int
3638 i40e_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3639 {
3640         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3641         struct i40e_vsi *vsi = pf->main_vsi;
3642         PMD_INIT_FUNC_TRACE();
3643
3644         if (on)
3645                 return i40e_vsi_add_vlan(vsi, vlan_id);
3646         else
3647                 return i40e_vsi_delete_vlan(vsi, vlan_id);
3648 }
3649
3650 static int
3651 i40e_vlan_tpid_set_by_registers(struct rte_eth_dev *dev,
3652                                 enum rte_vlan_type vlan_type,
3653                                 uint16_t tpid, int qinq)
3654 {
3655         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3656         uint64_t reg_r = 0;
3657         uint64_t reg_w = 0;
3658         uint16_t reg_id = 3;
3659         int ret;
3660
3661         if (qinq) {
3662                 if (vlan_type == ETH_VLAN_TYPE_OUTER)
3663                         reg_id = 2;
3664         }
3665
3666         ret = i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
3667                                           &reg_r, NULL);
3668         if (ret != I40E_SUCCESS) {
3669                 PMD_DRV_LOG(ERR,
3670                            "Fail to debug read from I40E_GL_SWT_L2TAGCTRL[%d]",
3671                            reg_id);
3672                 return -EIO;
3673         }
3674         PMD_DRV_LOG(DEBUG,
3675                     "Debug read from I40E_GL_SWT_L2TAGCTRL[%d]: 0x%08"PRIx64,
3676                     reg_id, reg_r);
3677
3678         reg_w = reg_r & (~(I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK));
3679         reg_w |= ((uint64_t)tpid << I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT);
3680         if (reg_r == reg_w) {
3681                 PMD_DRV_LOG(DEBUG, "No need to write");
3682                 return 0;
3683         }
3684
3685         ret = i40e_aq_debug_write_global_register(hw,
3686                                            I40E_GL_SWT_L2TAGCTRL(reg_id),
3687                                            reg_w, NULL);
3688         if (ret != I40E_SUCCESS) {
3689                 PMD_DRV_LOG(ERR,
3690                             "Fail to debug write to I40E_GL_SWT_L2TAGCTRL[%d]",
3691                             reg_id);
3692                 return -EIO;
3693         }
3694         PMD_DRV_LOG(DEBUG,
3695                     "Global register 0x%08x is changed with value 0x%08x",
3696                     I40E_GL_SWT_L2TAGCTRL(reg_id), (uint32_t)reg_w);
3697
3698         return 0;
3699 }
3700
3701 static int
3702 i40e_vlan_tpid_set(struct rte_eth_dev *dev,
3703                    enum rte_vlan_type vlan_type,
3704                    uint16_t tpid)
3705 {
3706         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3707         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3708         int qinq = dev->data->dev_conf.rxmode.offloads &
3709                    DEV_RX_OFFLOAD_VLAN_EXTEND;
3710         int ret = 0;
3711
3712         if ((vlan_type != ETH_VLAN_TYPE_INNER &&
3713              vlan_type != ETH_VLAN_TYPE_OUTER) ||
3714             (!qinq && vlan_type == ETH_VLAN_TYPE_INNER)) {
3715                 PMD_DRV_LOG(ERR,
3716                             "Unsupported vlan type.");
3717                 return -EINVAL;
3718         }
3719
3720         if (pf->support_multi_driver) {
3721                 PMD_DRV_LOG(ERR, "Setting TPID is not supported.");
3722                 return -ENOTSUP;
3723         }
3724
3725         /* 802.1ad frames ability is added in NVM API 1.7*/
3726         if (hw->flags & I40E_HW_FLAG_802_1AD_CAPABLE) {
3727                 if (qinq) {
3728                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3729                                 hw->first_tag = rte_cpu_to_le_16(tpid);
3730                         else if (vlan_type == ETH_VLAN_TYPE_INNER)
3731                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3732                 } else {
3733                         if (vlan_type == ETH_VLAN_TYPE_OUTER)
3734                                 hw->second_tag = rte_cpu_to_le_16(tpid);
3735                 }
3736                 ret = i40e_aq_set_switch_config(hw, 0, 0, 0, NULL);
3737                 if (ret != I40E_SUCCESS) {
3738                         PMD_DRV_LOG(ERR,
3739                                     "Set switch config failed aq_err: %d",
3740                                     hw->aq.asq_last_status);
3741                         ret = -EIO;
3742                 }
3743         } else
3744                 /* If NVM API < 1.7, keep the register setting */
3745                 ret = i40e_vlan_tpid_set_by_registers(dev, vlan_type,
3746                                                       tpid, qinq);
3747
3748         return ret;
3749 }
3750
3751 static int
3752 i40e_vlan_offload_set(struct rte_eth_dev *dev, int mask)
3753 {
3754         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3755         struct i40e_vsi *vsi = pf->main_vsi;
3756         struct rte_eth_rxmode *rxmode;
3757
3758         rxmode = &dev->data->dev_conf.rxmode;
3759         if (mask & ETH_VLAN_FILTER_MASK) {
3760                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
3761                         i40e_vsi_config_vlan_filter(vsi, TRUE);
3762                 else
3763                         i40e_vsi_config_vlan_filter(vsi, FALSE);
3764         }
3765
3766         if (mask & ETH_VLAN_STRIP_MASK) {
3767                 /* Enable or disable VLAN stripping */
3768                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
3769                         i40e_vsi_config_vlan_stripping(vsi, TRUE);
3770                 else
3771                         i40e_vsi_config_vlan_stripping(vsi, FALSE);
3772         }
3773
3774         if (mask & ETH_VLAN_EXTEND_MASK) {
3775                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND) {
3776                         i40e_vsi_config_double_vlan(vsi, TRUE);
3777                         /* Set global registers with default ethertype. */
3778                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_OUTER,
3779                                            RTE_ETHER_TYPE_VLAN);
3780                         i40e_vlan_tpid_set(dev, ETH_VLAN_TYPE_INNER,
3781                                            RTE_ETHER_TYPE_VLAN);
3782                 }
3783                 else
3784                         i40e_vsi_config_double_vlan(vsi, FALSE);
3785         }
3786
3787         return 0;
3788 }
3789
3790 static void
3791 i40e_vlan_strip_queue_set(__rte_unused struct rte_eth_dev *dev,
3792                           __rte_unused uint16_t queue,
3793                           __rte_unused int on)
3794 {
3795         PMD_INIT_FUNC_TRACE();
3796 }
3797
3798 static int
3799 i40e_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3800 {
3801         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3802         struct i40e_vsi *vsi = pf->main_vsi;
3803         struct rte_eth_dev_data *data = I40E_VSI_TO_DEV_DATA(vsi);
3804         struct i40e_vsi_vlan_pvid_info info;
3805
3806         memset(&info, 0, sizeof(info));
3807         info.on = on;
3808         if (info.on)
3809                 info.config.pvid = pvid;
3810         else {
3811                 info.config.reject.tagged =
3812                                 data->dev_conf.txmode.hw_vlan_reject_tagged;
3813                 info.config.reject.untagged =
3814                                 data->dev_conf.txmode.hw_vlan_reject_untagged;
3815         }
3816
3817         return i40e_vsi_vlan_pvid_set(vsi, &info);
3818 }
3819
3820 static int
3821 i40e_dev_led_on(struct rte_eth_dev *dev)
3822 {
3823         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3824         uint32_t mode = i40e_led_get(hw);
3825
3826         if (mode == 0)
3827                 i40e_led_set(hw, 0xf, true); /* 0xf means led always true */
3828
3829         return 0;
3830 }
3831
3832 static int
3833 i40e_dev_led_off(struct rte_eth_dev *dev)
3834 {
3835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3836         uint32_t mode = i40e_led_get(hw);
3837
3838         if (mode != 0)
3839                 i40e_led_set(hw, 0, false);
3840
3841         return 0;
3842 }
3843
3844 static int
3845 i40e_flow_ctrl_get(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3846 {
3847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3848         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3849
3850         fc_conf->pause_time = pf->fc_conf.pause_time;
3851
3852         /* read out from register, in case they are modified by other port */
3853         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] =
3854                 I40E_READ_REG(hw, I40E_GLRPB_GHW) >> I40E_KILOSHIFT;
3855         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] =
3856                 I40E_READ_REG(hw, I40E_GLRPB_GLW) >> I40E_KILOSHIFT;
3857
3858         fc_conf->high_water =  pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS];
3859         fc_conf->low_water = pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS];
3860
3861          /* Return current mode according to actual setting*/
3862         switch (hw->fc.current_mode) {
3863         case I40E_FC_FULL:
3864                 fc_conf->mode = RTE_FC_FULL;
3865                 break;
3866         case I40E_FC_TX_PAUSE:
3867                 fc_conf->mode = RTE_FC_TX_PAUSE;
3868                 break;
3869         case I40E_FC_RX_PAUSE:
3870                 fc_conf->mode = RTE_FC_RX_PAUSE;
3871                 break;
3872         case I40E_FC_NONE:
3873         default:
3874                 fc_conf->mode = RTE_FC_NONE;
3875         };
3876
3877         return 0;
3878 }
3879
3880 static int
3881 i40e_flow_ctrl_set(struct rte_eth_dev *dev, struct rte_eth_fc_conf *fc_conf)
3882 {
3883         uint32_t mflcn_reg, fctrl_reg, reg;
3884         uint32_t max_high_water;
3885         uint8_t i, aq_failure;
3886         int err;
3887         struct i40e_hw *hw;
3888         struct i40e_pf *pf;
3889         enum i40e_fc_mode rte_fcmode_2_i40e_fcmode[] = {
3890                 [RTE_FC_NONE] = I40E_FC_NONE,
3891                 [RTE_FC_RX_PAUSE] = I40E_FC_RX_PAUSE,
3892                 [RTE_FC_TX_PAUSE] = I40E_FC_TX_PAUSE,
3893                 [RTE_FC_FULL] = I40E_FC_FULL
3894         };
3895
3896         /* high_water field in the rte_eth_fc_conf using the kilobytes unit */
3897
3898         max_high_water = I40E_RXPBSIZE >> I40E_KILOSHIFT;
3899         if ((fc_conf->high_water > max_high_water) ||
3900                         (fc_conf->high_water < fc_conf->low_water)) {
3901                 PMD_INIT_LOG(ERR,
3902                         "Invalid high/low water setup value in KB, High_water must be <= %d.",
3903                         max_high_water);
3904                 return -EINVAL;
3905         }
3906
3907         hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3908         pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3909         hw->fc.requested_mode = rte_fcmode_2_i40e_fcmode[fc_conf->mode];
3910
3911         pf->fc_conf.pause_time = fc_conf->pause_time;
3912         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->high_water;
3913         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = fc_conf->low_water;
3914
3915         PMD_INIT_FUNC_TRACE();
3916
3917         /* All the link flow control related enable/disable register
3918          * configuration is handle by the F/W
3919          */
3920         err = i40e_set_fc(hw, &aq_failure, true);
3921         if (err < 0)
3922                 return -ENOSYS;
3923
3924         if (I40E_PHY_TYPE_SUPPORT_40G(hw->phy.phy_types)) {
3925                 /* Configure flow control refresh threshold,
3926                  * the value for stat_tx_pause_refresh_timer[8]
3927                  * is used for global pause operation.
3928                  */
3929
3930                 I40E_WRITE_REG(hw,
3931                                I40E_PRTMAC_HSEC_CTL_TX_PAUSE_REFRESH_TIMER(8),
3932                                pf->fc_conf.pause_time);
3933
3934                 /* configure the timer value included in transmitted pause
3935                  * frame,
3936                  * the value for stat_tx_pause_quanta[8] is used for global
3937                  * pause operation
3938                  */
3939                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_TX_PAUSE_QUANTA(8),
3940                                pf->fc_conf.pause_time);
3941
3942                 fctrl_reg = I40E_READ_REG(hw,
3943                                           I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL);
3944
3945                 if (fc_conf->mac_ctrl_frame_fwd != 0)
3946                         fctrl_reg |= I40E_PRTMAC_FWD_CTRL;
3947                 else
3948                         fctrl_reg &= ~I40E_PRTMAC_FWD_CTRL;
3949
3950                 I40E_WRITE_REG(hw, I40E_PRTMAC_HSEC_CTL_RX_FORWARD_CONTROL,
3951                                fctrl_reg);
3952         } else {
3953                 /* Configure pause time (2 TCs per register) */
3954                 reg = (uint32_t)pf->fc_conf.pause_time * (uint32_t)0x00010001;
3955                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS / 2; i++)
3956                         I40E_WRITE_REG(hw, I40E_PRTDCB_FCTTVN(i), reg);
3957
3958                 /* Configure flow control refresh threshold value */
3959                 I40E_WRITE_REG(hw, I40E_PRTDCB_FCRTV,
3960                                pf->fc_conf.pause_time / 2);
3961
3962                 mflcn_reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
3963
3964                 /* set or clear MFLCN.PMCF & MFLCN.DPF bits
3965                  *depending on configuration
3966                  */
3967                 if (fc_conf->mac_ctrl_frame_fwd != 0) {
3968                         mflcn_reg |= I40E_PRTDCB_MFLCN_PMCF_MASK;
3969                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_DPF_MASK;
3970                 } else {
3971                         mflcn_reg &= ~I40E_PRTDCB_MFLCN_PMCF_MASK;
3972                         mflcn_reg |= I40E_PRTDCB_MFLCN_DPF_MASK;
3973                 }
3974
3975                 I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, mflcn_reg);
3976         }
3977
3978         if (!pf->support_multi_driver) {
3979                 /* config water marker both based on the packets and bytes */
3980                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PHW,
3981                                  (pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3982                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3983                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_PLW,
3984                                   (pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3985                                  << I40E_KILOSHIFT) / I40E_PACKET_AVERAGE_SIZE);
3986                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GHW,
3987                                   pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS]
3988                                   << I40E_KILOSHIFT);
3989                 I40E_WRITE_GLB_REG(hw, I40E_GLRPB_GLW,
3990                                    pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS]
3991                                    << I40E_KILOSHIFT);
3992         } else {
3993                 PMD_DRV_LOG(ERR,
3994                             "Water marker configuration is not supported.");
3995         }
3996
3997         I40E_WRITE_FLUSH(hw);
3998
3999         return 0;
4000 }
4001
4002 static int
4003 i40e_priority_flow_ctrl_set(__rte_unused struct rte_eth_dev *dev,
4004                             __rte_unused struct rte_eth_pfc_conf *pfc_conf)
4005 {
4006         PMD_INIT_FUNC_TRACE();
4007
4008         return -ENOSYS;
4009 }
4010
4011 /* Add a MAC address, and update filters */
4012 static int
4013 i40e_macaddr_add(struct rte_eth_dev *dev,
4014                  struct rte_ether_addr *mac_addr,
4015                  __rte_unused uint32_t index,
4016                  uint32_t pool)
4017 {
4018         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4019         struct i40e_mac_filter_info mac_filter;
4020         struct i40e_vsi *vsi;
4021         struct rte_eth_rxmode *rxmode = &dev->data->dev_conf.rxmode;
4022         int ret;
4023
4024         /* If VMDQ not enabled or configured, return */
4025         if (pool != 0 && (!(pf->flags & I40E_FLAG_VMDQ) ||
4026                           !pf->nb_cfg_vmdq_vsi)) {
4027                 PMD_DRV_LOG(ERR, "VMDQ not %s, can't set mac to pool %u",
4028                         pf->flags & I40E_FLAG_VMDQ ? "configured" : "enabled",
4029                         pool);
4030                 return -ENOTSUP;
4031         }
4032
4033         if (pool > pf->nb_cfg_vmdq_vsi) {
4034                 PMD_DRV_LOG(ERR, "Pool number %u invalid. Max pool is %u",
4035                                 pool, pf->nb_cfg_vmdq_vsi);
4036                 return -EINVAL;
4037         }
4038
4039         rte_memcpy(&mac_filter.mac_addr, mac_addr, RTE_ETHER_ADDR_LEN);
4040         if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4041                 mac_filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
4042         else
4043                 mac_filter.filter_type = RTE_MAC_PERFECT_MATCH;
4044
4045         if (pool == 0)
4046                 vsi = pf->main_vsi;
4047         else
4048                 vsi = pf->vmdq[pool - 1].vsi;
4049
4050         ret = i40e_vsi_add_mac(vsi, &mac_filter);
4051         if (ret != I40E_SUCCESS) {
4052                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
4053                 return -ENODEV;
4054         }
4055         return 0;
4056 }
4057
4058 /* Remove a MAC address, and update filters */
4059 static void
4060 i40e_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
4061 {
4062         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4063         struct i40e_vsi *vsi;
4064         struct rte_eth_dev_data *data = dev->data;
4065         struct rte_ether_addr *macaddr;
4066         int ret;
4067         uint32_t i;
4068         uint64_t pool_sel;
4069
4070         macaddr = &(data->mac_addrs[index]);
4071
4072         pool_sel = dev->data->mac_pool_sel[index];
4073
4074         for (i = 0; i < sizeof(pool_sel) * CHAR_BIT; i++) {
4075                 if (pool_sel & (1ULL << i)) {
4076                         if (i == 0)
4077                                 vsi = pf->main_vsi;
4078                         else {
4079                                 /* No VMDQ pool enabled or configured */
4080                                 if (!(pf->flags & I40E_FLAG_VMDQ) ||
4081                                         (i > pf->nb_cfg_vmdq_vsi)) {
4082                                         PMD_DRV_LOG(ERR,
4083                                                 "No VMDQ pool enabled/configured");
4084                                         return;
4085                                 }
4086                                 vsi = pf->vmdq[i - 1].vsi;
4087                         }
4088                         ret = i40e_vsi_delete_mac(vsi, macaddr);
4089
4090                         if (ret) {
4091                                 PMD_DRV_LOG(ERR, "Failed to remove MACVLAN filter");
4092                                 return;
4093                         }
4094                 }
4095         }
4096 }
4097
4098 /* Set perfect match or hash match of MAC and VLAN for a VF */
4099 static int
4100 i40e_vf_mac_filter_set(struct i40e_pf *pf,
4101                  struct rte_eth_mac_filter *filter,
4102                  bool add)
4103 {
4104         struct i40e_hw *hw;
4105         struct i40e_mac_filter_info mac_filter;
4106         struct rte_ether_addr old_mac;
4107         struct rte_ether_addr *new_mac;
4108         struct i40e_pf_vf *vf = NULL;
4109         uint16_t vf_id;
4110         int ret;
4111
4112         if (pf == NULL) {
4113                 PMD_DRV_LOG(ERR, "Invalid PF argument.");
4114                 return -EINVAL;
4115         }
4116         hw = I40E_PF_TO_HW(pf);
4117
4118         if (filter == NULL) {
4119                 PMD_DRV_LOG(ERR, "Invalid mac filter argument.");
4120                 return -EINVAL;
4121         }
4122
4123         new_mac = &filter->mac_addr;
4124
4125         if (rte_is_zero_ether_addr(new_mac)) {
4126                 PMD_DRV_LOG(ERR, "Invalid ethernet address.");
4127                 return -EINVAL;
4128         }
4129
4130         vf_id = filter->dst_id;
4131
4132         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
4133                 PMD_DRV_LOG(ERR, "Invalid argument.");
4134                 return -EINVAL;
4135         }
4136         vf = &pf->vfs[vf_id];
4137
4138         if (add && rte_is_same_ether_addr(new_mac, &pf->dev_addr)) {
4139                 PMD_DRV_LOG(INFO, "Ignore adding permanent MAC address.");
4140                 return -EINVAL;
4141         }
4142
4143         if (add) {
4144                 rte_memcpy(&old_mac, hw->mac.addr, RTE_ETHER_ADDR_LEN);
4145                 rte_memcpy(hw->mac.addr, new_mac->addr_bytes,
4146                                 RTE_ETHER_ADDR_LEN);
4147                 rte_memcpy(&mac_filter.mac_addr, &filter->mac_addr,
4148                                  RTE_ETHER_ADDR_LEN);
4149
4150                 mac_filter.filter_type = filter->filter_type;
4151                 ret = i40e_vsi_add_mac(vf->vsi, &mac_filter);
4152                 if (ret != I40E_SUCCESS) {
4153                         PMD_DRV_LOG(ERR, "Failed to add MAC filter.");
4154                         return -1;
4155                 }
4156                 rte_ether_addr_copy(new_mac, &pf->dev_addr);
4157         } else {
4158                 rte_memcpy(hw->mac.addr, hw->mac.perm_addr,
4159                                 RTE_ETHER_ADDR_LEN);
4160                 ret = i40e_vsi_delete_mac(vf->vsi, &filter->mac_addr);
4161                 if (ret != I40E_SUCCESS) {
4162                         PMD_DRV_LOG(ERR, "Failed to delete MAC filter.");
4163                         return -1;
4164                 }
4165
4166                 /* Clear device address as it has been removed */
4167                 if (rte_is_same_ether_addr(&pf->dev_addr, new_mac))
4168                         memset(&pf->dev_addr, 0, sizeof(struct rte_ether_addr));
4169         }
4170
4171         return 0;
4172 }
4173
4174 /* MAC filter handle */
4175 static int
4176 i40e_mac_filter_handle(struct rte_eth_dev *dev, enum rte_filter_op filter_op,
4177                 void *arg)
4178 {
4179         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4180         struct rte_eth_mac_filter *filter;
4181         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4182         int ret = I40E_NOT_SUPPORTED;
4183
4184         filter = (struct rte_eth_mac_filter *)(arg);
4185
4186         switch (filter_op) {
4187         case RTE_ETH_FILTER_NOP:
4188                 ret = I40E_SUCCESS;
4189                 break;
4190         case RTE_ETH_FILTER_ADD:
4191                 i40e_pf_disable_irq0(hw);
4192                 if (filter->is_vf)
4193                         ret = i40e_vf_mac_filter_set(pf, filter, 1);
4194                 i40e_pf_enable_irq0(hw);
4195                 break;
4196         case RTE_ETH_FILTER_DELETE:
4197                 i40e_pf_disable_irq0(hw);
4198                 if (filter->is_vf)
4199                         ret = i40e_vf_mac_filter_set(pf, filter, 0);
4200                 i40e_pf_enable_irq0(hw);
4201                 break;
4202         default:
4203                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
4204                 ret = I40E_ERR_PARAM;
4205                 break;
4206         }
4207
4208         return ret;
4209 }
4210
4211 static int
4212 i40e_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4213 {
4214         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
4215         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4216         uint32_t reg;
4217         int ret;
4218
4219         if (!lut)
4220                 return -EINVAL;
4221
4222         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4223                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id,
4224                                           vsi->type != I40E_VSI_SRIOV,
4225                                           lut, lut_size);
4226                 if (ret) {
4227                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4228                         return ret;
4229                 }
4230         } else {
4231                 uint32_t *lut_dw = (uint32_t *)lut;
4232                 uint16_t i, lut_size_dw = lut_size / 4;
4233
4234                 if (vsi->type == I40E_VSI_SRIOV) {
4235                         for (i = 0; i <= lut_size_dw; i++) {
4236                                 reg = I40E_VFQF_HLUT1(i, vsi->user_param);
4237                                 lut_dw[i] = i40e_read_rx_ctl(hw, reg);
4238                         }
4239                 } else {
4240                         for (i = 0; i < lut_size_dw; i++)
4241                                 lut_dw[i] = I40E_READ_REG(hw,
4242                                                           I40E_PFQF_HLUT(i));
4243                 }
4244         }
4245
4246         return 0;
4247 }
4248
4249 int
4250 i40e_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4251 {
4252         struct i40e_pf *pf;
4253         struct i40e_hw *hw;
4254         int ret;
4255
4256         if (!vsi || !lut)
4257                 return -EINVAL;
4258
4259         pf = I40E_VSI_TO_PF(vsi);
4260         hw = I40E_VSI_TO_HW(vsi);
4261
4262         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
4263                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id,
4264                                           vsi->type != I40E_VSI_SRIOV,
4265                                           lut, lut_size);
4266                 if (ret) {
4267                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4268                         return ret;
4269                 }
4270         } else {
4271                 uint32_t *lut_dw = (uint32_t *)lut;
4272                 uint16_t i, lut_size_dw = lut_size / 4;
4273
4274                 if (vsi->type == I40E_VSI_SRIOV) {
4275                         for (i = 0; i < lut_size_dw; i++)
4276                                 I40E_WRITE_REG(
4277                                         hw,
4278                                         I40E_VFQF_HLUT1(i, vsi->user_param),
4279                                         lut_dw[i]);
4280                 } else {
4281                         for (i = 0; i < lut_size_dw; i++)
4282                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i),
4283                                                lut_dw[i]);
4284                 }
4285                 I40E_WRITE_FLUSH(hw);
4286         }
4287
4288         return 0;
4289 }
4290
4291 static int
4292 i40e_dev_rss_reta_update(struct rte_eth_dev *dev,
4293                          struct rte_eth_rss_reta_entry64 *reta_conf,
4294                          uint16_t reta_size)
4295 {
4296         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4297         uint16_t i, lut_size = pf->hash_lut_size;
4298         uint16_t idx, shift;
4299         uint8_t *lut;
4300         int ret;
4301
4302         if (reta_size != lut_size ||
4303                 reta_size > ETH_RSS_RETA_SIZE_512) {
4304                 PMD_DRV_LOG(ERR,
4305                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4306                         reta_size, lut_size);
4307                 return -EINVAL;
4308         }
4309
4310         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4311         if (!lut) {
4312                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4313                 return -ENOMEM;
4314         }
4315         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4316         if (ret)
4317                 goto out;
4318         for (i = 0; i < reta_size; i++) {
4319                 idx = i / RTE_RETA_GROUP_SIZE;
4320                 shift = i % RTE_RETA_GROUP_SIZE;
4321                 if (reta_conf[idx].mask & (1ULL << shift))
4322                         lut[i] = reta_conf[idx].reta[shift];
4323         }
4324         ret = i40e_set_rss_lut(pf->main_vsi, lut, reta_size);
4325
4326         pf->adapter->rss_reta_updated = 1;
4327
4328 out:
4329         rte_free(lut);
4330
4331         return ret;
4332 }
4333
4334 static int
4335 i40e_dev_rss_reta_query(struct rte_eth_dev *dev,
4336                         struct rte_eth_rss_reta_entry64 *reta_conf,
4337                         uint16_t reta_size)
4338 {
4339         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4340         uint16_t i, lut_size = pf->hash_lut_size;
4341         uint16_t idx, shift;
4342         uint8_t *lut;
4343         int ret;
4344
4345         if (reta_size != lut_size ||
4346                 reta_size > ETH_RSS_RETA_SIZE_512) {
4347                 PMD_DRV_LOG(ERR,
4348                         "The size of hash lookup table configured (%d) doesn't match the number hardware can supported (%d)",
4349                         reta_size, lut_size);
4350                 return -EINVAL;
4351         }
4352
4353         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
4354         if (!lut) {
4355                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4356                 return -ENOMEM;
4357         }
4358
4359         ret = i40e_get_rss_lut(pf->main_vsi, lut, reta_size);
4360         if (ret)
4361                 goto out;
4362         for (i = 0; i < reta_size; i++) {
4363                 idx = i / RTE_RETA_GROUP_SIZE;
4364                 shift = i % RTE_RETA_GROUP_SIZE;
4365                 if (reta_conf[idx].mask & (1ULL << shift))
4366                         reta_conf[idx].reta[shift] = lut[i];
4367         }
4368
4369 out:
4370         rte_free(lut);
4371
4372         return ret;
4373 }
4374
4375 /**
4376  * i40e_allocate_dma_mem_d - specific memory alloc for shared code (base driver)
4377  * @hw:   pointer to the HW structure
4378  * @mem:  pointer to mem struct to fill out
4379  * @size: size of memory requested
4380  * @alignment: what to align the allocation to
4381  **/
4382 enum i40e_status_code
4383 i40e_allocate_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4384                         struct i40e_dma_mem *mem,
4385                         u64 size,
4386                         u32 alignment)
4387 {
4388         const struct rte_memzone *mz = NULL;
4389         char z_name[RTE_MEMZONE_NAMESIZE];
4390
4391         if (!mem)
4392                 return I40E_ERR_PARAM;
4393
4394         snprintf(z_name, sizeof(z_name), "i40e_dma_%"PRIu64, rte_rand());
4395         mz = rte_memzone_reserve_bounded(z_name, size, SOCKET_ID_ANY,
4396                         RTE_MEMZONE_IOVA_CONTIG, alignment, RTE_PGSIZE_2M);
4397         if (!mz)
4398                 return I40E_ERR_NO_MEMORY;
4399
4400         mem->size = size;
4401         mem->va = mz->addr;
4402         mem->pa = mz->iova;
4403         mem->zone = (const void *)mz;
4404         PMD_DRV_LOG(DEBUG,
4405                 "memzone %s allocated with physical address: %"PRIu64,
4406                 mz->name, mem->pa);
4407
4408         return I40E_SUCCESS;
4409 }
4410
4411 /**
4412  * i40e_free_dma_mem_d - specific memory free for shared code (base driver)
4413  * @hw:   pointer to the HW structure
4414  * @mem:  ptr to mem struct to free
4415  **/
4416 enum i40e_status_code
4417 i40e_free_dma_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4418                     struct i40e_dma_mem *mem)
4419 {
4420         if (!mem)
4421                 return I40E_ERR_PARAM;
4422
4423         PMD_DRV_LOG(DEBUG,
4424                 "memzone %s to be freed with physical address: %"PRIu64,
4425                 ((const struct rte_memzone *)mem->zone)->name, mem->pa);
4426         rte_memzone_free((const struct rte_memzone *)mem->zone);
4427         mem->zone = NULL;
4428         mem->va = NULL;
4429         mem->pa = (u64)0;
4430
4431         return I40E_SUCCESS;
4432 }
4433
4434 /**
4435  * i40e_allocate_virt_mem_d - specific memory alloc for shared code (base driver)
4436  * @hw:   pointer to the HW structure
4437  * @mem:  pointer to mem struct to fill out
4438  * @size: size of memory requested
4439  **/
4440 enum i40e_status_code
4441 i40e_allocate_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4442                          struct i40e_virt_mem *mem,
4443                          u32 size)
4444 {
4445         if (!mem)
4446                 return I40E_ERR_PARAM;
4447
4448         mem->size = size;
4449         mem->va = rte_zmalloc("i40e", size, 0);
4450
4451         if (mem->va)
4452                 return I40E_SUCCESS;
4453         else
4454                 return I40E_ERR_NO_MEMORY;
4455 }
4456
4457 /**
4458  * i40e_free_virt_mem_d - specific memory free for shared code (base driver)
4459  * @hw:   pointer to the HW structure
4460  * @mem:  pointer to mem struct to free
4461  **/
4462 enum i40e_status_code
4463 i40e_free_virt_mem_d(__attribute__((unused)) struct i40e_hw *hw,
4464                      struct i40e_virt_mem *mem)
4465 {
4466         if (!mem)
4467                 return I40E_ERR_PARAM;
4468
4469         rte_free(mem->va);
4470         mem->va = NULL;
4471
4472         return I40E_SUCCESS;
4473 }
4474
4475 void
4476 i40e_init_spinlock_d(struct i40e_spinlock *sp)
4477 {
4478         rte_spinlock_init(&sp->spinlock);
4479 }
4480
4481 void
4482 i40e_acquire_spinlock_d(struct i40e_spinlock *sp)
4483 {
4484         rte_spinlock_lock(&sp->spinlock);
4485 }
4486
4487 void
4488 i40e_release_spinlock_d(struct i40e_spinlock *sp)
4489 {
4490         rte_spinlock_unlock(&sp->spinlock);
4491 }
4492
4493 void
4494 i40e_destroy_spinlock_d(__attribute__((unused)) struct i40e_spinlock *sp)
4495 {
4496         return;
4497 }
4498
4499 /**
4500  * Get the hardware capabilities, which will be parsed
4501  * and saved into struct i40e_hw.
4502  */
4503 static int
4504 i40e_get_cap(struct i40e_hw *hw)
4505 {
4506         struct i40e_aqc_list_capabilities_element_resp *buf;
4507         uint16_t len, size = 0;
4508         int ret;
4509
4510         /* Calculate a huge enough buff for saving response data temporarily */
4511         len = sizeof(struct i40e_aqc_list_capabilities_element_resp) *
4512                                                 I40E_MAX_CAP_ELE_NUM;
4513         buf = rte_zmalloc("i40e", len, 0);
4514         if (!buf) {
4515                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
4516                 return I40E_ERR_NO_MEMORY;
4517         }
4518
4519         /* Get, parse the capabilities and save it to hw */
4520         ret = i40e_aq_discover_capabilities(hw, buf, len, &size,
4521                         i40e_aqc_opc_list_func_capabilities, NULL);
4522         if (ret != I40E_SUCCESS)
4523                 PMD_DRV_LOG(ERR, "Failed to discover capabilities");
4524
4525         /* Free the temporary buffer after being used */
4526         rte_free(buf);
4527
4528         return ret;
4529 }
4530
4531 #define RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF        4
4532
4533 static int i40e_pf_parse_vf_queue_number_handler(const char *key,
4534                 const char *value,
4535                 void *opaque)
4536 {
4537         struct i40e_pf *pf;
4538         unsigned long num;
4539         char *end;
4540
4541         pf = (struct i40e_pf *)opaque;
4542         RTE_SET_USED(key);
4543
4544         errno = 0;
4545         num = strtoul(value, &end, 0);
4546         if (errno != 0 || end == value || *end != 0) {
4547                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %s, Now it is "
4548                             "kept the value = %hu", value, pf->vf_nb_qp_max);
4549                 return -(EINVAL);
4550         }
4551
4552         if (num <= I40E_MAX_QP_NUM_PER_VF && rte_is_power_of_2(num))
4553                 pf->vf_nb_qp_max = (uint16_t)num;
4554         else
4555                 /* here return 0 to make next valid same argument work */
4556                 PMD_DRV_LOG(WARNING, "Wrong VF queue number = %lu, it must be "
4557                             "power of 2 and equal or less than 16 !, Now it is "
4558                             "kept the value = %hu", num, pf->vf_nb_qp_max);
4559
4560         return 0;
4561 }
4562
4563 static int i40e_pf_config_vf_rxq_number(struct rte_eth_dev *dev)
4564 {
4565         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4566         struct rte_kvargs *kvlist;
4567         int kvargs_count;
4568
4569         /* set default queue number per VF as 4 */
4570         pf->vf_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VF;
4571
4572         if (dev->device->devargs == NULL)
4573                 return 0;
4574
4575         kvlist = rte_kvargs_parse(dev->device->devargs->args, valid_keys);
4576         if (kvlist == NULL)
4577                 return -(EINVAL);
4578
4579         kvargs_count = rte_kvargs_count(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4580         if (!kvargs_count) {
4581                 rte_kvargs_free(kvlist);
4582                 return 0;
4583         }
4584
4585         if (kvargs_count > 1)
4586                 PMD_DRV_LOG(WARNING, "More than one argument \"%s\" and only "
4587                             "the first invalid or last valid one is used !",
4588                             ETH_I40E_QUEUE_NUM_PER_VF_ARG);
4589
4590         rte_kvargs_process(kvlist, ETH_I40E_QUEUE_NUM_PER_VF_ARG,
4591                            i40e_pf_parse_vf_queue_number_handler, pf);
4592
4593         rte_kvargs_free(kvlist);
4594
4595         return 0;
4596 }
4597
4598 static int
4599 i40e_pf_parameter_init(struct rte_eth_dev *dev)
4600 {
4601         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4602         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4603         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
4604         uint16_t qp_count = 0, vsi_count = 0;
4605
4606         if (pci_dev->max_vfs && !hw->func_caps.sr_iov_1_1) {
4607                 PMD_INIT_LOG(ERR, "HW configuration doesn't support SRIOV");
4608                 return -EINVAL;
4609         }
4610
4611         i40e_pf_config_vf_rxq_number(dev);
4612
4613         /* Add the parameter init for LFC */
4614         pf->fc_conf.pause_time = I40E_DEFAULT_PAUSE_TIME;
4615         pf->fc_conf.high_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_HIGH_WATER;
4616         pf->fc_conf.low_water[I40E_MAX_TRAFFIC_CLASS] = I40E_DEFAULT_LOW_WATER;
4617
4618         pf->flags = I40E_FLAG_HEADER_SPLIT_DISABLED;
4619         pf->max_num_vsi = hw->func_caps.num_vsis;
4620         pf->lan_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_PF;
4621         pf->vmdq_nb_qp_max = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
4622
4623         /* FDir queue/VSI allocation */
4624         pf->fdir_qp_offset = 0;
4625         if (hw->func_caps.fd) {
4626                 pf->flags |= I40E_FLAG_FDIR;
4627                 pf->fdir_nb_qps = I40E_DEFAULT_QP_NUM_FDIR;
4628         } else {
4629                 pf->fdir_nb_qps = 0;
4630         }
4631         qp_count += pf->fdir_nb_qps;
4632         vsi_count += 1;
4633
4634         /* LAN queue/VSI allocation */
4635         pf->lan_qp_offset = pf->fdir_qp_offset + pf->fdir_nb_qps;
4636         if (!hw->func_caps.rss) {
4637                 pf->lan_nb_qps = 1;
4638         } else {
4639                 pf->flags |= I40E_FLAG_RSS;
4640                 if (hw->mac.type == I40E_MAC_X722)
4641                         pf->flags |= I40E_FLAG_RSS_AQ_CAPABLE;
4642                 pf->lan_nb_qps = pf->lan_nb_qp_max;
4643         }
4644         qp_count += pf->lan_nb_qps;
4645         vsi_count += 1;
4646
4647         /* VF queue/VSI allocation */
4648         pf->vf_qp_offset = pf->lan_qp_offset + pf->lan_nb_qps;
4649         if (hw->func_caps.sr_iov_1_1 && pci_dev->max_vfs) {
4650                 pf->flags |= I40E_FLAG_SRIOV;
4651                 pf->vf_nb_qps = pf->vf_nb_qp_max;
4652                 pf->vf_num = pci_dev->max_vfs;
4653                 PMD_DRV_LOG(DEBUG,
4654                         "%u VF VSIs, %u queues per VF VSI, in total %u queues",
4655                         pf->vf_num, pf->vf_nb_qps, pf->vf_nb_qps * pf->vf_num);
4656         } else {
4657                 pf->vf_nb_qps = 0;
4658                 pf->vf_num = 0;
4659         }
4660         qp_count += pf->vf_nb_qps * pf->vf_num;
4661         vsi_count += pf->vf_num;
4662
4663         /* VMDq queue/VSI allocation */
4664         pf->vmdq_qp_offset = pf->vf_qp_offset + pf->vf_nb_qps * pf->vf_num;
4665         pf->vmdq_nb_qps = 0;
4666         pf->max_nb_vmdq_vsi = 0;
4667         if (hw->func_caps.vmdq) {
4668                 if (qp_count < hw->func_caps.num_tx_qp &&
4669                         vsi_count < hw->func_caps.num_vsis) {
4670                         pf->max_nb_vmdq_vsi = (hw->func_caps.num_tx_qp -
4671                                 qp_count) / pf->vmdq_nb_qp_max;
4672
4673                         /* Limit the maximum number of VMDq vsi to the maximum
4674                          * ethdev can support
4675                          */
4676                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4677                                 hw->func_caps.num_vsis - vsi_count);
4678                         pf->max_nb_vmdq_vsi = RTE_MIN(pf->max_nb_vmdq_vsi,
4679                                 ETH_64_POOLS);
4680                         if (pf->max_nb_vmdq_vsi) {
4681                                 pf->flags |= I40E_FLAG_VMDQ;
4682                                 pf->vmdq_nb_qps = pf->vmdq_nb_qp_max;
4683                                 PMD_DRV_LOG(DEBUG,
4684                                         "%u VMDQ VSIs, %u queues per VMDQ VSI, in total %u queues",
4685                                         pf->max_nb_vmdq_vsi, pf->vmdq_nb_qps,
4686                                         pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi);
4687                         } else {
4688                                 PMD_DRV_LOG(INFO,
4689                                         "No enough queues left for VMDq");
4690                         }
4691                 } else {
4692                         PMD_DRV_LOG(INFO, "No queue or VSI left for VMDq");
4693                 }
4694         }
4695         qp_count += pf->vmdq_nb_qps * pf->max_nb_vmdq_vsi;
4696         vsi_count += pf->max_nb_vmdq_vsi;
4697
4698         if (hw->func_caps.dcb)
4699                 pf->flags |= I40E_FLAG_DCB;
4700
4701         if (qp_count > hw->func_caps.num_tx_qp) {
4702                 PMD_DRV_LOG(ERR,
4703                         "Failed to allocate %u queues, which exceeds the hardware maximum %u",
4704                         qp_count, hw->func_caps.num_tx_qp);
4705                 return -EINVAL;
4706         }
4707         if (vsi_count > hw->func_caps.num_vsis) {
4708                 PMD_DRV_LOG(ERR,
4709                         "Failed to allocate %u VSIs, which exceeds the hardware maximum %u",
4710                         vsi_count, hw->func_caps.num_vsis);
4711                 return -EINVAL;
4712         }
4713
4714         return 0;
4715 }
4716
4717 static int
4718 i40e_pf_get_switch_config(struct i40e_pf *pf)
4719 {
4720         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4721         struct i40e_aqc_get_switch_config_resp *switch_config;
4722         struct i40e_aqc_switch_config_element_resp *element;
4723         uint16_t start_seid = 0, num_reported;
4724         int ret;
4725
4726         switch_config = (struct i40e_aqc_get_switch_config_resp *)\
4727                         rte_zmalloc("i40e", I40E_AQ_LARGE_BUF, 0);
4728         if (!switch_config) {
4729                 PMD_DRV_LOG(ERR, "Failed to allocated memory");
4730                 return -ENOMEM;
4731         }
4732
4733         /* Get the switch configurations */
4734         ret = i40e_aq_get_switch_config(hw, switch_config,
4735                 I40E_AQ_LARGE_BUF, &start_seid, NULL);
4736         if (ret != I40E_SUCCESS) {
4737                 PMD_DRV_LOG(ERR, "Failed to get switch configurations");
4738                 goto fail;
4739         }
4740         num_reported = rte_le_to_cpu_16(switch_config->header.num_reported);
4741         if (num_reported != 1) { /* The number should be 1 */
4742                 PMD_DRV_LOG(ERR, "Wrong number of switch config reported");
4743                 goto fail;
4744         }
4745
4746         /* Parse the switch configuration elements */
4747         element = &(switch_config->element[0]);
4748         if (element->element_type == I40E_SWITCH_ELEMENT_TYPE_VSI) {
4749                 pf->mac_seid = rte_le_to_cpu_16(element->uplink_seid);
4750                 pf->main_vsi_seid = rte_le_to_cpu_16(element->seid);
4751         } else
4752                 PMD_DRV_LOG(INFO, "Unknown element type");
4753
4754 fail:
4755         rte_free(switch_config);
4756
4757         return ret;
4758 }
4759
4760 static int
4761 i40e_res_pool_init (struct i40e_res_pool_info *pool, uint32_t base,
4762                         uint32_t num)
4763 {
4764         struct pool_entry *entry;
4765
4766         if (pool == NULL || num == 0)
4767                 return -EINVAL;
4768
4769         entry = rte_zmalloc("i40e", sizeof(*entry), 0);
4770         if (entry == NULL) {
4771                 PMD_DRV_LOG(ERR, "Failed to allocate memory for resource pool");
4772                 return -ENOMEM;
4773         }
4774
4775         /* queue heap initialize */
4776         pool->num_free = num;
4777         pool->num_alloc = 0;
4778         pool->base = base;
4779         LIST_INIT(&pool->alloc_list);
4780         LIST_INIT(&pool->free_list);
4781
4782         /* Initialize element  */
4783         entry->base = 0;
4784         entry->len = num;
4785
4786         LIST_INSERT_HEAD(&pool->free_list, entry, next);
4787         return 0;
4788 }
4789
4790 static void
4791 i40e_res_pool_destroy(struct i40e_res_pool_info *pool)
4792 {
4793         struct pool_entry *entry, *next_entry;
4794
4795         if (pool == NULL)
4796                 return;
4797
4798         for (entry = LIST_FIRST(&pool->alloc_list);
4799                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4800                         entry = next_entry) {
4801                 LIST_REMOVE(entry, next);
4802                 rte_free(entry);
4803         }
4804
4805         for (entry = LIST_FIRST(&pool->free_list);
4806                         entry && (next_entry = LIST_NEXT(entry, next), 1);
4807                         entry = next_entry) {
4808                 LIST_REMOVE(entry, next);
4809                 rte_free(entry);
4810         }
4811
4812         pool->num_free = 0;
4813         pool->num_alloc = 0;
4814         pool->base = 0;
4815         LIST_INIT(&pool->alloc_list);
4816         LIST_INIT(&pool->free_list);
4817 }
4818
4819 static int
4820 i40e_res_pool_free(struct i40e_res_pool_info *pool,
4821                        uint32_t base)
4822 {
4823         struct pool_entry *entry, *next, *prev, *valid_entry = NULL;
4824         uint32_t pool_offset;
4825         int insert;
4826
4827         if (pool == NULL) {
4828                 PMD_DRV_LOG(ERR, "Invalid parameter");
4829                 return -EINVAL;
4830         }
4831
4832         pool_offset = base - pool->base;
4833         /* Lookup in alloc list */
4834         LIST_FOREACH(entry, &pool->alloc_list, next) {
4835                 if (entry->base == pool_offset) {
4836                         valid_entry = entry;
4837                         LIST_REMOVE(entry, next);
4838                         break;
4839                 }
4840         }
4841
4842         /* Not find, return */
4843         if (valid_entry == NULL) {
4844                 PMD_DRV_LOG(ERR, "Failed to find entry");
4845                 return -EINVAL;
4846         }
4847
4848         /**
4849          * Found it, move it to free list  and try to merge.
4850          * In order to make merge easier, always sort it by qbase.
4851          * Find adjacent prev and last entries.
4852          */
4853         prev = next = NULL;
4854         LIST_FOREACH(entry, &pool->free_list, next) {
4855                 if (entry->base > valid_entry->base) {
4856                         next = entry;
4857                         break;
4858                 }
4859                 prev = entry;
4860         }
4861
4862         insert = 0;
4863         /* Try to merge with next one*/
4864         if (next != NULL) {
4865                 /* Merge with next one */
4866                 if (valid_entry->base + valid_entry->len == next->base) {
4867                         next->base = valid_entry->base;
4868                         next->len += valid_entry->len;
4869                         rte_free(valid_entry);
4870                         valid_entry = next;
4871                         insert = 1;
4872                 }
4873         }
4874
4875         if (prev != NULL) {
4876                 /* Merge with previous one */
4877                 if (prev->base + prev->len == valid_entry->base) {
4878                         prev->len += valid_entry->len;
4879                         /* If it merge with next one, remove next node */
4880                         if (insert == 1) {
4881                                 LIST_REMOVE(valid_entry, next);
4882                                 rte_free(valid_entry);
4883                         } else {
4884                                 rte_free(valid_entry);
4885                                 insert = 1;
4886                         }
4887                 }
4888         }
4889
4890         /* Not find any entry to merge, insert */
4891         if (insert == 0) {
4892                 if (prev != NULL)
4893                         LIST_INSERT_AFTER(prev, valid_entry, next);
4894                 else if (next != NULL)
4895                         LIST_INSERT_BEFORE(next, valid_entry, next);
4896                 else /* It's empty list, insert to head */
4897                         LIST_INSERT_HEAD(&pool->free_list, valid_entry, next);
4898         }
4899
4900         pool->num_free += valid_entry->len;
4901         pool->num_alloc -= valid_entry->len;
4902
4903         return 0;
4904 }
4905
4906 static int
4907 i40e_res_pool_alloc(struct i40e_res_pool_info *pool,
4908                        uint16_t num)
4909 {
4910         struct pool_entry *entry, *valid_entry;
4911
4912         if (pool == NULL || num == 0) {
4913                 PMD_DRV_LOG(ERR, "Invalid parameter");
4914                 return -EINVAL;
4915         }
4916
4917         if (pool->num_free < num) {
4918                 PMD_DRV_LOG(ERR, "No resource. ask:%u, available:%u",
4919                             num, pool->num_free);
4920                 return -ENOMEM;
4921         }
4922
4923         valid_entry = NULL;
4924         /* Lookup  in free list and find most fit one */
4925         LIST_FOREACH(entry, &pool->free_list, next) {
4926                 if (entry->len >= num) {
4927                         /* Find best one */
4928                         if (entry->len == num) {
4929                                 valid_entry = entry;
4930                                 break;
4931                         }
4932                         if (valid_entry == NULL || valid_entry->len > entry->len)
4933                                 valid_entry = entry;
4934                 }
4935         }
4936
4937         /* Not find one to satisfy the request, return */
4938         if (valid_entry == NULL) {
4939                 PMD_DRV_LOG(ERR, "No valid entry found");
4940                 return -ENOMEM;
4941         }
4942         /**
4943          * The entry have equal queue number as requested,
4944          * remove it from alloc_list.
4945          */
4946         if (valid_entry->len == num) {
4947                 LIST_REMOVE(valid_entry, next);
4948         } else {
4949                 /**
4950                  * The entry have more numbers than requested,
4951                  * create a new entry for alloc_list and minus its
4952                  * queue base and number in free_list.
4953                  */
4954                 entry = rte_zmalloc("res_pool", sizeof(*entry), 0);
4955                 if (entry == NULL) {
4956                         PMD_DRV_LOG(ERR,
4957                                 "Failed to allocate memory for resource pool");
4958                         return -ENOMEM;
4959                 }
4960                 entry->base = valid_entry->base;
4961                 entry->len = num;
4962                 valid_entry->base += num;
4963                 valid_entry->len -= num;
4964                 valid_entry = entry;
4965         }
4966
4967         /* Insert it into alloc list, not sorted */
4968         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
4969
4970         pool->num_free -= valid_entry->len;
4971         pool->num_alloc += valid_entry->len;
4972
4973         return valid_entry->base + pool->base;
4974 }
4975
4976 /**
4977  * bitmap_is_subset - Check whether src2 is subset of src1
4978  **/
4979 static inline int
4980 bitmap_is_subset(uint8_t src1, uint8_t src2)
4981 {
4982         return !((src1 ^ src2) & src2);
4983 }
4984
4985 static enum i40e_status_code
4986 validate_tcmap_parameter(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
4987 {
4988         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
4989
4990         /* If DCB is not supported, only default TC is supported */
4991         if (!hw->func_caps.dcb && enabled_tcmap != I40E_DEFAULT_TCMAP) {
4992                 PMD_DRV_LOG(ERR, "DCB is not enabled, only TC0 is supported");
4993                 return I40E_NOT_SUPPORTED;
4994         }
4995
4996         if (!bitmap_is_subset(hw->func_caps.enabled_tcmap, enabled_tcmap)) {
4997                 PMD_DRV_LOG(ERR,
4998                         "Enabled TC map 0x%x not applicable to HW support 0x%x",
4999                         hw->func_caps.enabled_tcmap, enabled_tcmap);
5000                 return I40E_NOT_SUPPORTED;
5001         }
5002         return I40E_SUCCESS;
5003 }
5004
5005 int
5006 i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
5007                                 struct i40e_vsi_vlan_pvid_info *info)
5008 {
5009         struct i40e_hw *hw;
5010         struct i40e_vsi_context ctxt;
5011         uint8_t vlan_flags = 0;
5012         int ret;
5013
5014         if (vsi == NULL || info == NULL) {
5015                 PMD_DRV_LOG(ERR, "invalid parameters");
5016                 return I40E_ERR_PARAM;
5017         }
5018
5019         if (info->on) {
5020                 vsi->info.pvid = info->config.pvid;
5021                 /**
5022                  * If insert pvid is enabled, only tagged pkts are
5023                  * allowed to be sent out.
5024                  */
5025                 vlan_flags |= I40E_AQ_VSI_PVLAN_INSERT_PVID |
5026                                 I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5027         } else {
5028                 vsi->info.pvid = 0;
5029                 if (info->config.reject.tagged == 0)
5030                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_TAGGED;
5031
5032                 if (info->config.reject.untagged == 0)
5033                         vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_UNTAGGED;
5034         }
5035         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_INSERT_PVID |
5036                                         I40E_AQ_VSI_PVLAN_MODE_MASK);
5037         vsi->info.port_vlan_flags |= vlan_flags;
5038         vsi->info.valid_sections =
5039                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5040         memset(&ctxt, 0, sizeof(ctxt));
5041         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5042         ctxt.seid = vsi->seid;
5043
5044         hw = I40E_VSI_TO_HW(vsi);
5045         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5046         if (ret != I40E_SUCCESS)
5047                 PMD_DRV_LOG(ERR, "Failed to update VSI params");
5048
5049         return ret;
5050 }
5051
5052 static int
5053 i40e_vsi_update_tc_bandwidth(struct i40e_vsi *vsi, uint8_t enabled_tcmap)
5054 {
5055         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5056         int i, ret;
5057         struct i40e_aqc_configure_vsi_tc_bw_data tc_bw_data;
5058
5059         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5060         if (ret != I40E_SUCCESS)
5061                 return ret;
5062
5063         if (!vsi->seid) {
5064                 PMD_DRV_LOG(ERR, "seid not valid");
5065                 return -EINVAL;
5066         }
5067
5068         memset(&tc_bw_data, 0, sizeof(tc_bw_data));
5069         tc_bw_data.tc_valid_bits = enabled_tcmap;
5070         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5071                 tc_bw_data.tc_bw_credits[i] =
5072                         (enabled_tcmap & (1 << i)) ? 1 : 0;
5073
5074         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &tc_bw_data, NULL);
5075         if (ret != I40E_SUCCESS) {
5076                 PMD_DRV_LOG(ERR, "Failed to configure TC BW");
5077                 return ret;
5078         }
5079
5080         rte_memcpy(vsi->info.qs_handle, tc_bw_data.qs_handles,
5081                                         sizeof(vsi->info.qs_handle));
5082         return I40E_SUCCESS;
5083 }
5084
5085 static enum i40e_status_code
5086 i40e_vsi_config_tc_queue_mapping(struct i40e_vsi *vsi,
5087                                  struct i40e_aqc_vsi_properties_data *info,
5088                                  uint8_t enabled_tcmap)
5089 {
5090         enum i40e_status_code ret;
5091         int i, total_tc = 0;
5092         uint16_t qpnum_per_tc, bsf, qp_idx;
5093
5094         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
5095         if (ret != I40E_SUCCESS)
5096                 return ret;
5097
5098         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5099                 if (enabled_tcmap & (1 << i))
5100                         total_tc++;
5101         if (total_tc == 0)
5102                 total_tc = 1;
5103         vsi->enabled_tc = enabled_tcmap;
5104
5105         /* Number of queues per enabled TC */
5106         qpnum_per_tc = i40e_align_floor(vsi->nb_qps / total_tc);
5107         qpnum_per_tc = RTE_MIN(qpnum_per_tc, I40E_MAX_Q_PER_TC);
5108         bsf = rte_bsf32(qpnum_per_tc);
5109
5110         /* Adjust the queue number to actual queues that can be applied */
5111         if (!(vsi->type == I40E_VSI_MAIN && total_tc == 1))
5112                 vsi->nb_qps = qpnum_per_tc * total_tc;
5113
5114         /**
5115          * Configure TC and queue mapping parameters, for enabled TC,
5116          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
5117          * default queue will serve it.
5118          */
5119         qp_idx = 0;
5120         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5121                 if (vsi->enabled_tc & (1 << i)) {
5122                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
5123                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5124                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
5125                         qp_idx += qpnum_per_tc;
5126                 } else
5127                         info->tc_mapping[i] = 0;
5128         }
5129
5130         /* Associate queue number with VSI */
5131         if (vsi->type == I40E_VSI_SRIOV) {
5132                 info->mapping_flags |=
5133                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
5134                 for (i = 0; i < vsi->nb_qps; i++)
5135                         info->queue_mapping[i] =
5136                                 rte_cpu_to_le_16(vsi->base_queue + i);
5137         } else {
5138                 info->mapping_flags |=
5139                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5140                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
5141         }
5142         info->valid_sections |=
5143                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
5144
5145         return I40E_SUCCESS;
5146 }
5147
5148 static int
5149 i40e_veb_release(struct i40e_veb *veb)
5150 {
5151         struct i40e_vsi *vsi;
5152         struct i40e_hw *hw;
5153
5154         if (veb == NULL)
5155                 return -EINVAL;
5156
5157         if (!TAILQ_EMPTY(&veb->head)) {
5158                 PMD_DRV_LOG(ERR, "VEB still has VSI attached, can't remove");
5159                 return -EACCES;
5160         }
5161         /* associate_vsi field is NULL for floating VEB */
5162         if (veb->associate_vsi != NULL) {
5163                 vsi = veb->associate_vsi;
5164                 hw = I40E_VSI_TO_HW(vsi);
5165
5166                 vsi->uplink_seid = veb->uplink_seid;
5167                 vsi->veb = NULL;
5168         } else {
5169                 veb->associate_pf->main_vsi->floating_veb = NULL;
5170                 hw = I40E_VSI_TO_HW(veb->associate_pf->main_vsi);
5171         }
5172
5173         i40e_aq_delete_element(hw, veb->seid, NULL);
5174         rte_free(veb);
5175         return I40E_SUCCESS;
5176 }
5177
5178 /* Setup a veb */
5179 static struct i40e_veb *
5180 i40e_veb_setup(struct i40e_pf *pf, struct i40e_vsi *vsi)
5181 {
5182         struct i40e_veb *veb;
5183         int ret;
5184         struct i40e_hw *hw;
5185
5186         if (pf == NULL) {
5187                 PMD_DRV_LOG(ERR,
5188                             "veb setup failed, associated PF shouldn't null");
5189                 return NULL;
5190         }
5191         hw = I40E_PF_TO_HW(pf);
5192
5193         veb = rte_zmalloc("i40e_veb", sizeof(struct i40e_veb), 0);
5194         if (!veb) {
5195                 PMD_DRV_LOG(ERR, "Failed to allocate memory for veb");
5196                 goto fail;
5197         }
5198
5199         veb->associate_vsi = vsi;
5200         veb->associate_pf = pf;
5201         TAILQ_INIT(&veb->head);
5202         veb->uplink_seid = vsi ? vsi->uplink_seid : 0;
5203
5204         /* create floating veb if vsi is NULL */
5205         if (vsi != NULL) {
5206                 ret = i40e_aq_add_veb(hw, veb->uplink_seid, vsi->seid,
5207                                       I40E_DEFAULT_TCMAP, false,
5208                                       &veb->seid, false, NULL);
5209         } else {
5210                 ret = i40e_aq_add_veb(hw, 0, 0, I40E_DEFAULT_TCMAP,
5211                                       true, &veb->seid, false, NULL);
5212         }
5213
5214         if (ret != I40E_SUCCESS) {
5215                 PMD_DRV_LOG(ERR, "Add veb failed, aq_err: %d",
5216                             hw->aq.asq_last_status);
5217                 goto fail;
5218         }
5219         veb->enabled_tc = I40E_DEFAULT_TCMAP;
5220
5221         /* get statistics index */
5222         ret = i40e_aq_get_veb_parameters(hw, veb->seid, NULL, NULL,
5223                                 &veb->stats_idx, NULL, NULL, NULL);
5224         if (ret != I40E_SUCCESS) {
5225                 PMD_DRV_LOG(ERR, "Get veb statistics index failed, aq_err: %d",
5226                             hw->aq.asq_last_status);
5227                 goto fail;
5228         }
5229         /* Get VEB bandwidth, to be implemented */
5230         /* Now associated vsi binding to the VEB, set uplink to this VEB */
5231         if (vsi)
5232                 vsi->uplink_seid = veb->seid;
5233
5234         return veb;
5235 fail:
5236         rte_free(veb);
5237         return NULL;
5238 }
5239
5240 int
5241 i40e_vsi_release(struct i40e_vsi *vsi)
5242 {
5243         struct i40e_pf *pf;
5244         struct i40e_hw *hw;
5245         struct i40e_vsi_list *vsi_list;
5246         void *temp;
5247         int ret;
5248         struct i40e_mac_filter *f;
5249         uint16_t user_param;
5250
5251         if (!vsi)
5252                 return I40E_SUCCESS;
5253
5254         if (!vsi->adapter)
5255                 return -EFAULT;
5256
5257         user_param = vsi->user_param;
5258
5259         pf = I40E_VSI_TO_PF(vsi);
5260         hw = I40E_VSI_TO_HW(vsi);
5261
5262         /* VSI has child to attach, release child first */
5263         if (vsi->veb) {
5264                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->veb->head, list, temp) {
5265                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5266                                 return -1;
5267                 }
5268                 i40e_veb_release(vsi->veb);
5269         }
5270
5271         if (vsi->floating_veb) {
5272                 TAILQ_FOREACH_SAFE(vsi_list, &vsi->floating_veb->head, list, temp) {
5273                         if (i40e_vsi_release(vsi_list->vsi) != I40E_SUCCESS)
5274                                 return -1;
5275                 }
5276         }
5277
5278         /* Remove all macvlan filters of the VSI */
5279         i40e_vsi_remove_all_macvlan_filter(vsi);
5280         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp)
5281                 rte_free(f);
5282
5283         if (vsi->type != I40E_VSI_MAIN &&
5284             ((vsi->type != I40E_VSI_SRIOV) ||
5285             !pf->floating_veb_list[user_param])) {
5286                 /* Remove vsi from parent's sibling list */
5287                 if (vsi->parent_vsi == NULL || vsi->parent_vsi->veb == NULL) {
5288                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5289                         return I40E_ERR_PARAM;
5290                 }
5291                 TAILQ_REMOVE(&vsi->parent_vsi->veb->head,
5292                                 &vsi->sib_vsi_list, list);
5293
5294                 /* Remove all switch element of the VSI */
5295                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5296                 if (ret != I40E_SUCCESS)
5297                         PMD_DRV_LOG(ERR, "Failed to delete element");
5298         }
5299
5300         if ((vsi->type == I40E_VSI_SRIOV) &&
5301             pf->floating_veb_list[user_param]) {
5302                 /* Remove vsi from parent's sibling list */
5303                 if (vsi->parent_vsi == NULL ||
5304                     vsi->parent_vsi->floating_veb == NULL) {
5305                         PMD_DRV_LOG(ERR, "VSI's parent VSI is NULL");
5306                         return I40E_ERR_PARAM;
5307                 }
5308                 TAILQ_REMOVE(&vsi->parent_vsi->floating_veb->head,
5309                              &vsi->sib_vsi_list, list);
5310
5311                 /* Remove all switch element of the VSI */
5312                 ret = i40e_aq_delete_element(hw, vsi->seid, NULL);
5313                 if (ret != I40E_SUCCESS)
5314                         PMD_DRV_LOG(ERR, "Failed to delete element");
5315         }
5316
5317         i40e_res_pool_free(&pf->qp_pool, vsi->base_queue);
5318
5319         if (vsi->type != I40E_VSI_SRIOV)
5320                 i40e_res_pool_free(&pf->msix_pool, vsi->msix_intr);
5321         rte_free(vsi);
5322
5323         return I40E_SUCCESS;
5324 }
5325
5326 static int
5327 i40e_update_default_filter_setting(struct i40e_vsi *vsi)
5328 {
5329         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5330         struct i40e_aqc_remove_macvlan_element_data def_filter;
5331         struct i40e_mac_filter_info filter;
5332         int ret;
5333
5334         if (vsi->type != I40E_VSI_MAIN)
5335                 return I40E_ERR_CONFIG;
5336         memset(&def_filter, 0, sizeof(def_filter));
5337         rte_memcpy(def_filter.mac_addr, hw->mac.perm_addr,
5338                                         ETH_ADDR_LEN);
5339         def_filter.vlan_tag = 0;
5340         def_filter.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
5341                                 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
5342         ret = i40e_aq_remove_macvlan(hw, vsi->seid, &def_filter, 1, NULL);
5343         if (ret != I40E_SUCCESS) {
5344                 struct i40e_mac_filter *f;
5345                 struct rte_ether_addr *mac;
5346
5347                 PMD_DRV_LOG(DEBUG,
5348                             "Cannot remove the default macvlan filter");
5349                 /* It needs to add the permanent mac into mac list */
5350                 f = rte_zmalloc("macv_filter", sizeof(*f), 0);
5351                 if (f == NULL) {
5352                         PMD_DRV_LOG(ERR, "failed to allocate memory");
5353                         return I40E_ERR_NO_MEMORY;
5354                 }
5355                 mac = &f->mac_info.mac_addr;
5356                 rte_memcpy(&mac->addr_bytes, hw->mac.perm_addr,
5357                                 ETH_ADDR_LEN);
5358                 f->mac_info.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5359                 TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
5360                 vsi->mac_num++;
5361
5362                 return ret;
5363         }
5364         rte_memcpy(&filter.mac_addr,
5365                 (struct rte_ether_addr *)(hw->mac.perm_addr), ETH_ADDR_LEN);
5366         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5367         return i40e_vsi_add_mac(vsi, &filter);
5368 }
5369
5370 /*
5371  * i40e_vsi_get_bw_config - Query VSI BW Information
5372  * @vsi: the VSI to be queried
5373  *
5374  * Returns 0 on success, negative value on failure
5375  */
5376 static enum i40e_status_code
5377 i40e_vsi_get_bw_config(struct i40e_vsi *vsi)
5378 {
5379         struct i40e_aqc_query_vsi_bw_config_resp bw_config;
5380         struct i40e_aqc_query_vsi_ets_sla_config_resp ets_sla_config;
5381         struct i40e_hw *hw = &vsi->adapter->hw;
5382         i40e_status ret;
5383         int i;
5384         uint32_t bw_max;
5385
5386         memset(&bw_config, 0, sizeof(bw_config));
5387         ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5388         if (ret != I40E_SUCCESS) {
5389                 PMD_DRV_LOG(ERR, "VSI failed to get bandwidth configuration %u",
5390                             hw->aq.asq_last_status);
5391                 return ret;
5392         }
5393
5394         memset(&ets_sla_config, 0, sizeof(ets_sla_config));
5395         ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid,
5396                                         &ets_sla_config, NULL);
5397         if (ret != I40E_SUCCESS) {
5398                 PMD_DRV_LOG(ERR,
5399                         "VSI failed to get TC bandwdith configuration %u",
5400                         hw->aq.asq_last_status);
5401                 return ret;
5402         }
5403
5404         /* store and print out BW info */
5405         vsi->bw_info.bw_limit = rte_le_to_cpu_16(bw_config.port_bw_limit);
5406         vsi->bw_info.bw_max = bw_config.max_bw;
5407         PMD_DRV_LOG(DEBUG, "VSI bw limit:%u", vsi->bw_info.bw_limit);
5408         PMD_DRV_LOG(DEBUG, "VSI max_bw:%u", vsi->bw_info.bw_max);
5409         bw_max = rte_le_to_cpu_16(ets_sla_config.tc_bw_max[0]) |
5410                     (rte_le_to_cpu_16(ets_sla_config.tc_bw_max[1]) <<
5411                      I40E_16_BIT_WIDTH);
5412         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5413                 vsi->bw_info.bw_ets_share_credits[i] =
5414                                 ets_sla_config.share_credits[i];
5415                 vsi->bw_info.bw_ets_credits[i] =
5416                                 rte_le_to_cpu_16(ets_sla_config.credits[i]);
5417                 /* 4 bits per TC, 4th bit is reserved */
5418                 vsi->bw_info.bw_ets_max[i] =
5419                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
5420                                   RTE_LEN2MASK(3, uint8_t));
5421                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:share credits %u", i,
5422                             vsi->bw_info.bw_ets_share_credits[i]);
5423                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u:credits %u", i,
5424                             vsi->bw_info.bw_ets_credits[i]);
5425                 PMD_DRV_LOG(DEBUG, "\tVSI TC%u: max credits: %u", i,
5426                             vsi->bw_info.bw_ets_max[i]);
5427         }
5428
5429         return I40E_SUCCESS;
5430 }
5431
5432 /* i40e_enable_pf_lb
5433  * @pf: pointer to the pf structure
5434  *
5435  * allow loopback on pf
5436  */
5437 static inline void
5438 i40e_enable_pf_lb(struct i40e_pf *pf)
5439 {
5440         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5441         struct i40e_vsi_context ctxt;
5442         int ret;
5443
5444         /* Use the FW API if FW >= v5.0 */
5445         if (hw->aq.fw_maj_ver < 5 && hw->mac.type != I40E_MAC_X722) {
5446                 PMD_INIT_LOG(ERR, "FW < v5.0, cannot enable loopback");
5447                 return;
5448         }
5449
5450         memset(&ctxt, 0, sizeof(ctxt));
5451         ctxt.seid = pf->main_vsi_seid;
5452         ctxt.pf_num = hw->pf_id;
5453         ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5454         if (ret) {
5455                 PMD_DRV_LOG(ERR, "cannot get pf vsi config, err %d, aq_err %d",
5456                             ret, hw->aq.asq_last_status);
5457                 return;
5458         }
5459         ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5460         ctxt.info.valid_sections =
5461                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5462         ctxt.info.switch_id |=
5463                 rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5464
5465         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5466         if (ret)
5467                 PMD_DRV_LOG(ERR, "update vsi switch failed, aq_err=%d",
5468                             hw->aq.asq_last_status);
5469 }
5470
5471 /* Setup a VSI */
5472 struct i40e_vsi *
5473 i40e_vsi_setup(struct i40e_pf *pf,
5474                enum i40e_vsi_type type,
5475                struct i40e_vsi *uplink_vsi,
5476                uint16_t user_param)
5477 {
5478         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
5479         struct i40e_vsi *vsi;
5480         struct i40e_mac_filter_info filter;
5481         int ret;
5482         struct i40e_vsi_context ctxt;
5483         struct rte_ether_addr broadcast =
5484                 {.addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff}};
5485
5486         if (type != I40E_VSI_MAIN && type != I40E_VSI_SRIOV &&
5487             uplink_vsi == NULL) {
5488                 PMD_DRV_LOG(ERR,
5489                         "VSI setup failed, VSI link shouldn't be NULL");
5490                 return NULL;
5491         }
5492
5493         if (type == I40E_VSI_MAIN && uplink_vsi != NULL) {
5494                 PMD_DRV_LOG(ERR,
5495                         "VSI setup failed, MAIN VSI uplink VSI should be NULL");
5496                 return NULL;
5497         }
5498
5499         /* two situations
5500          * 1.type is not MAIN and uplink vsi is not NULL
5501          * If uplink vsi didn't setup VEB, create one first under veb field
5502          * 2.type is SRIOV and the uplink is NULL
5503          * If floating VEB is NULL, create one veb under floating veb field
5504          */
5505
5506         if (type != I40E_VSI_MAIN && uplink_vsi != NULL &&
5507             uplink_vsi->veb == NULL) {
5508                 uplink_vsi->veb = i40e_veb_setup(pf, uplink_vsi);
5509
5510                 if (uplink_vsi->veb == NULL) {
5511                         PMD_DRV_LOG(ERR, "VEB setup failed");
5512                         return NULL;
5513                 }
5514                 /* set ALLOWLOOPBACk on pf, when veb is created */
5515                 i40e_enable_pf_lb(pf);
5516         }
5517
5518         if (type == I40E_VSI_SRIOV && uplink_vsi == NULL &&
5519             pf->main_vsi->floating_veb == NULL) {
5520                 pf->main_vsi->floating_veb = i40e_veb_setup(pf, uplink_vsi);
5521
5522                 if (pf->main_vsi->floating_veb == NULL) {
5523                         PMD_DRV_LOG(ERR, "VEB setup failed");
5524                         return NULL;
5525                 }
5526         }
5527
5528         vsi = rte_zmalloc("i40e_vsi", sizeof(struct i40e_vsi), 0);
5529         if (!vsi) {
5530                 PMD_DRV_LOG(ERR, "Failed to allocate memory for vsi");
5531                 return NULL;
5532         }
5533         TAILQ_INIT(&vsi->mac_list);
5534         vsi->type = type;
5535         vsi->adapter = I40E_PF_TO_ADAPTER(pf);
5536         vsi->max_macaddrs = I40E_NUM_MACADDR_MAX;
5537         vsi->parent_vsi = uplink_vsi ? uplink_vsi : pf->main_vsi;
5538         vsi->user_param = user_param;
5539         vsi->vlan_anti_spoof_on = 0;
5540         vsi->vlan_filter_on = 0;
5541         /* Allocate queues */
5542         switch (vsi->type) {
5543         case I40E_VSI_MAIN  :
5544                 vsi->nb_qps = pf->lan_nb_qps;
5545                 break;
5546         case I40E_VSI_SRIOV :
5547                 vsi->nb_qps = pf->vf_nb_qps;
5548                 break;
5549         case I40E_VSI_VMDQ2:
5550                 vsi->nb_qps = pf->vmdq_nb_qps;
5551                 break;
5552         case I40E_VSI_FDIR:
5553                 vsi->nb_qps = pf->fdir_nb_qps;
5554                 break;
5555         default:
5556                 goto fail_mem;
5557         }
5558         /*
5559          * The filter status descriptor is reported in rx queue 0,
5560          * while the tx queue for fdir filter programming has no
5561          * such constraints, can be non-zero queues.
5562          * To simplify it, choose FDIR vsi use queue 0 pair.
5563          * To make sure it will use queue 0 pair, queue allocation
5564          * need be done before this function is called
5565          */
5566         if (type != I40E_VSI_FDIR) {
5567                 ret = i40e_res_pool_alloc(&pf->qp_pool, vsi->nb_qps);
5568                         if (ret < 0) {
5569                                 PMD_DRV_LOG(ERR, "VSI %d allocate queue failed %d",
5570                                                 vsi->seid, ret);
5571                                 goto fail_mem;
5572                         }
5573                         vsi->base_queue = ret;
5574         } else
5575                 vsi->base_queue = I40E_FDIR_QUEUE_ID;
5576
5577         /* VF has MSIX interrupt in VF range, don't allocate here */
5578         if (type == I40E_VSI_MAIN) {
5579                 if (pf->support_multi_driver) {
5580                         /* If support multi-driver, need to use INT0 instead of
5581                          * allocating from msix pool. The Msix pool is init from
5582                          * INT1, so it's OK just set msix_intr to 0 and nb_msix
5583                          * to 1 without calling i40e_res_pool_alloc.
5584                          */
5585                         vsi->msix_intr = 0;
5586                         vsi->nb_msix = 1;
5587                 } else {
5588                         ret = i40e_res_pool_alloc(&pf->msix_pool,
5589                                                   RTE_MIN(vsi->nb_qps,
5590                                                      RTE_MAX_RXTX_INTR_VEC_ID));
5591                         if (ret < 0) {
5592                                 PMD_DRV_LOG(ERR,
5593                                             "VSI MAIN %d get heap failed %d",
5594                                             vsi->seid, ret);
5595                                 goto fail_queue_alloc;
5596                         }
5597                         vsi->msix_intr = ret;
5598                         vsi->nb_msix = RTE_MIN(vsi->nb_qps,
5599                                                RTE_MAX_RXTX_INTR_VEC_ID);
5600                 }
5601         } else if (type != I40E_VSI_SRIOV) {
5602                 ret = i40e_res_pool_alloc(&pf->msix_pool, 1);
5603                 if (ret < 0) {
5604                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d", vsi->seid, ret);
5605                         goto fail_queue_alloc;
5606                 }
5607                 vsi->msix_intr = ret;
5608                 vsi->nb_msix = 1;
5609         } else {
5610                 vsi->msix_intr = 0;
5611                 vsi->nb_msix = 0;
5612         }
5613
5614         /* Add VSI */
5615         if (type == I40E_VSI_MAIN) {
5616                 /* For main VSI, no need to add since it's default one */
5617                 vsi->uplink_seid = pf->mac_seid;
5618                 vsi->seid = pf->main_vsi_seid;
5619                 /* Bind queues with specific MSIX interrupt */
5620                 /**
5621                  * Needs 2 interrupt at least, one for misc cause which will
5622                  * enabled from OS side, Another for queues binding the
5623                  * interrupt from device side only.
5624                  */
5625
5626                 /* Get default VSI parameters from hardware */
5627                 memset(&ctxt, 0, sizeof(ctxt));
5628                 ctxt.seid = vsi->seid;
5629                 ctxt.pf_num = hw->pf_id;
5630                 ctxt.uplink_seid = vsi->uplink_seid;
5631                 ctxt.vf_num = 0;
5632                 ret = i40e_aq_get_vsi_params(hw, &ctxt, NULL);
5633                 if (ret != I40E_SUCCESS) {
5634                         PMD_DRV_LOG(ERR, "Failed to get VSI params");
5635                         goto fail_msix_alloc;
5636                 }
5637                 rte_memcpy(&vsi->info, &ctxt.info,
5638                         sizeof(struct i40e_aqc_vsi_properties_data));
5639                 vsi->vsi_id = ctxt.vsi_number;
5640                 vsi->info.valid_sections = 0;
5641
5642                 /* Configure tc, enabled TC0 only */
5643                 if (i40e_vsi_update_tc_bandwidth(vsi, I40E_DEFAULT_TCMAP) !=
5644                         I40E_SUCCESS) {
5645                         PMD_DRV_LOG(ERR, "Failed to update TC bandwidth");
5646                         goto fail_msix_alloc;
5647                 }
5648
5649                 /* TC, queue mapping */
5650                 memset(&ctxt, 0, sizeof(ctxt));
5651                 vsi->info.valid_sections |=
5652                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5653                 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
5654                                         I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5655                 rte_memcpy(&ctxt.info, &vsi->info,
5656                         sizeof(struct i40e_aqc_vsi_properties_data));
5657                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5658                                                 I40E_DEFAULT_TCMAP);
5659                 if (ret != I40E_SUCCESS) {
5660                         PMD_DRV_LOG(ERR,
5661                                 "Failed to configure TC queue mapping");
5662                         goto fail_msix_alloc;
5663                 }
5664                 ctxt.seid = vsi->seid;
5665                 ctxt.pf_num = hw->pf_id;
5666                 ctxt.uplink_seid = vsi->uplink_seid;
5667                 ctxt.vf_num = 0;
5668
5669                 /* Update VSI parameters */
5670                 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5671                 if (ret != I40E_SUCCESS) {
5672                         PMD_DRV_LOG(ERR, "Failed to update VSI params");
5673                         goto fail_msix_alloc;
5674                 }
5675
5676                 rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
5677                                                 sizeof(vsi->info.tc_mapping));
5678                 rte_memcpy(&vsi->info.queue_mapping,
5679                                 &ctxt.info.queue_mapping,
5680                         sizeof(vsi->info.queue_mapping));
5681                 vsi->info.mapping_flags = ctxt.info.mapping_flags;
5682                 vsi->info.valid_sections = 0;
5683
5684                 rte_memcpy(pf->dev_addr.addr_bytes, hw->mac.perm_addr,
5685                                 ETH_ADDR_LEN);
5686
5687                 /**
5688                  * Updating default filter settings are necessary to prevent
5689                  * reception of tagged packets.
5690                  * Some old firmware configurations load a default macvlan
5691                  * filter which accepts both tagged and untagged packets.
5692                  * The updating is to use a normal filter instead if needed.
5693                  * For NVM 4.2.2 or after, the updating is not needed anymore.
5694                  * The firmware with correct configurations load the default
5695                  * macvlan filter which is expected and cannot be removed.
5696                  */
5697                 i40e_update_default_filter_setting(vsi);
5698                 i40e_config_qinq(hw, vsi);
5699         } else if (type == I40E_VSI_SRIOV) {
5700                 memset(&ctxt, 0, sizeof(ctxt));
5701                 /**
5702                  * For other VSI, the uplink_seid equals to uplink VSI's
5703                  * uplink_seid since they share same VEB
5704                  */
5705                 if (uplink_vsi == NULL)
5706                         vsi->uplink_seid = pf->main_vsi->floating_veb->seid;
5707                 else
5708                         vsi->uplink_seid = uplink_vsi->uplink_seid;
5709                 ctxt.pf_num = hw->pf_id;
5710                 ctxt.vf_num = hw->func_caps.vf_base_id + user_param;
5711                 ctxt.uplink_seid = vsi->uplink_seid;
5712                 ctxt.connection_type = 0x1;
5713                 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
5714
5715                 /* Use the VEB configuration if FW >= v5.0 */
5716                 if (hw->aq.fw_maj_ver >= 5 || hw->mac.type == I40E_MAC_X722) {
5717                         /* Configure switch ID */
5718                         ctxt.info.valid_sections |=
5719                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5720                         ctxt.info.switch_id =
5721                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5722                 }
5723
5724                 /* Configure port/vlan */
5725                 ctxt.info.valid_sections |=
5726                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5727                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5728                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5729                                                 hw->func_caps.enabled_tcmap);
5730                 if (ret != I40E_SUCCESS) {
5731                         PMD_DRV_LOG(ERR,
5732                                 "Failed to configure TC queue mapping");
5733                         goto fail_msix_alloc;
5734                 }
5735
5736                 ctxt.info.up_enable_bits = hw->func_caps.enabled_tcmap;
5737                 ctxt.info.valid_sections |=
5738                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5739                 /**
5740                  * Since VSI is not created yet, only configure parameter,
5741                  * will add vsi below.
5742                  */
5743
5744                 i40e_config_qinq(hw, vsi);
5745         } else if (type == I40E_VSI_VMDQ2) {
5746                 memset(&ctxt, 0, sizeof(ctxt));
5747                 /*
5748                  * For other VSI, the uplink_seid equals to uplink VSI's
5749                  * uplink_seid since they share same VEB
5750                  */
5751                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5752                 ctxt.pf_num = hw->pf_id;
5753                 ctxt.vf_num = 0;
5754                 ctxt.uplink_seid = vsi->uplink_seid;
5755                 ctxt.connection_type = 0x1;
5756                 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5757
5758                 ctxt.info.valid_sections |=
5759                                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5760                 /* user_param carries flag to enable loop back */
5761                 if (user_param) {
5762                         ctxt.info.switch_id =
5763                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
5764                         ctxt.info.switch_id |=
5765                         rte_cpu_to_le_16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5766                 }
5767
5768                 /* Configure port/vlan */
5769                 ctxt.info.valid_sections |=
5770                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5771                 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
5772                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5773                                                 I40E_DEFAULT_TCMAP);
5774                 if (ret != I40E_SUCCESS) {
5775                         PMD_DRV_LOG(ERR,
5776                                 "Failed to configure TC queue mapping");
5777                         goto fail_msix_alloc;
5778                 }
5779                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5780                 ctxt.info.valid_sections |=
5781                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5782         } else if (type == I40E_VSI_FDIR) {
5783                 memset(&ctxt, 0, sizeof(ctxt));
5784                 vsi->uplink_seid = uplink_vsi->uplink_seid;
5785                 ctxt.pf_num = hw->pf_id;
5786                 ctxt.vf_num = 0;
5787                 ctxt.uplink_seid = vsi->uplink_seid;
5788                 ctxt.connection_type = 0x1;     /* regular data port */
5789                 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
5790                 ret = i40e_vsi_config_tc_queue_mapping(vsi, &ctxt.info,
5791                                                 I40E_DEFAULT_TCMAP);
5792                 if (ret != I40E_SUCCESS) {
5793                         PMD_DRV_LOG(ERR,
5794                                 "Failed to configure TC queue mapping.");
5795                         goto fail_msix_alloc;
5796                 }
5797                 ctxt.info.up_enable_bits = I40E_DEFAULT_TCMAP;
5798                 ctxt.info.valid_sections |=
5799                         rte_cpu_to_le_16(I40E_AQ_VSI_PROP_SCHED_VALID);
5800         } else {
5801                 PMD_DRV_LOG(ERR, "VSI: Not support other type VSI yet");
5802                 goto fail_msix_alloc;
5803         }
5804
5805         if (vsi->type != I40E_VSI_MAIN) {
5806                 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5807                 if (ret != I40E_SUCCESS) {
5808                         PMD_DRV_LOG(ERR, "add vsi failed, aq_err=%d",
5809                                     hw->aq.asq_last_status);
5810                         goto fail_msix_alloc;
5811                 }
5812                 memcpy(&vsi->info, &ctxt.info, sizeof(ctxt.info));
5813                 vsi->info.valid_sections = 0;
5814                 vsi->seid = ctxt.seid;
5815                 vsi->vsi_id = ctxt.vsi_number;
5816                 vsi->sib_vsi_list.vsi = vsi;
5817                 if (vsi->type == I40E_VSI_SRIOV && uplink_vsi == NULL) {
5818                         TAILQ_INSERT_TAIL(&pf->main_vsi->floating_veb->head,
5819                                           &vsi->sib_vsi_list, list);
5820                 } else {
5821                         TAILQ_INSERT_TAIL(&uplink_vsi->veb->head,
5822                                           &vsi->sib_vsi_list, list);
5823                 }
5824         }
5825
5826         /* MAC/VLAN configuration */
5827         rte_memcpy(&filter.mac_addr, &broadcast, RTE_ETHER_ADDR_LEN);
5828         filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
5829
5830         ret = i40e_vsi_add_mac(vsi, &filter);
5831         if (ret != I40E_SUCCESS) {
5832                 PMD_DRV_LOG(ERR, "Failed to add MACVLAN filter");
5833                 goto fail_msix_alloc;
5834         }
5835
5836         /* Get VSI BW information */
5837         i40e_vsi_get_bw_config(vsi);
5838         return vsi;
5839 fail_msix_alloc:
5840         i40e_res_pool_free(&pf->msix_pool,vsi->msix_intr);
5841 fail_queue_alloc:
5842         i40e_res_pool_free(&pf->qp_pool,vsi->base_queue);
5843 fail_mem:
5844         rte_free(vsi);
5845         return NULL;
5846 }
5847
5848 /* Configure vlan filter on or off */
5849 int
5850 i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on)
5851 {
5852         int i, num;
5853         struct i40e_mac_filter *f;
5854         void *temp;
5855         struct i40e_mac_filter_info *mac_filter;
5856         enum rte_mac_filter_type desired_filter;
5857         int ret = I40E_SUCCESS;
5858
5859         if (on) {
5860                 /* Filter to match MAC and VLAN */
5861                 desired_filter = RTE_MACVLAN_PERFECT_MATCH;
5862         } else {
5863                 /* Filter to match only MAC */
5864                 desired_filter = RTE_MAC_PERFECT_MATCH;
5865         }
5866
5867         num = vsi->mac_num;
5868
5869         mac_filter = rte_zmalloc("mac_filter_info_data",
5870                                  num * sizeof(*mac_filter), 0);
5871         if (mac_filter == NULL) {
5872                 PMD_DRV_LOG(ERR, "failed to allocate memory");
5873                 return I40E_ERR_NO_MEMORY;
5874         }
5875
5876         i = 0;
5877
5878         /* Remove all existing mac */
5879         TAILQ_FOREACH_SAFE(f, &vsi->mac_list, next, temp) {
5880                 mac_filter[i] = f->mac_info;
5881                 ret = i40e_vsi_delete_mac(vsi, &f->mac_info.mac_addr);
5882                 if (ret) {
5883                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5884                                     on ? "enable" : "disable");
5885                         goto DONE;
5886                 }
5887                 i++;
5888         }
5889
5890         /* Override with new filter */
5891         for (i = 0; i < num; i++) {
5892                 mac_filter[i].filter_type = desired_filter;
5893                 ret = i40e_vsi_add_mac(vsi, &mac_filter[i]);
5894                 if (ret) {
5895                         PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan filter",
5896                                     on ? "enable" : "disable");
5897                         goto DONE;
5898                 }
5899         }
5900
5901 DONE:
5902         rte_free(mac_filter);
5903         return ret;
5904 }
5905
5906 /* Configure vlan stripping on or off */
5907 int
5908 i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on)
5909 {
5910         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5911         struct i40e_vsi_context ctxt;
5912         uint8_t vlan_flags;
5913         int ret = I40E_SUCCESS;
5914
5915         /* Check if it has been already on or off */
5916         if (vsi->info.valid_sections &
5917                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID)) {
5918                 if (on) {
5919                         if ((vsi->info.port_vlan_flags &
5920                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) == 0)
5921                                 return 0; /* already on */
5922                 } else {
5923                         if ((vsi->info.port_vlan_flags &
5924                                 I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
5925                                 I40E_AQ_VSI_PVLAN_EMOD_MASK)
5926                                 return 0; /* already off */
5927                 }
5928         }
5929
5930         if (on)
5931                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
5932         else
5933                 vlan_flags = I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
5934         vsi->info.valid_sections =
5935                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_VLAN_VALID);
5936         vsi->info.port_vlan_flags &= ~(I40E_AQ_VSI_PVLAN_EMOD_MASK);
5937         vsi->info.port_vlan_flags |= vlan_flags;
5938         ctxt.seid = vsi->seid;
5939         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
5940         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5941         if (ret)
5942                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
5943                             on ? "enable" : "disable");
5944
5945         return ret;
5946 }
5947
5948 static int
5949 i40e_dev_init_vlan(struct rte_eth_dev *dev)
5950 {
5951         struct rte_eth_dev_data *data = dev->data;
5952         int ret;
5953         int mask = 0;
5954
5955         /* Apply vlan offload setting */
5956         mask = ETH_VLAN_STRIP_MASK |
5957                ETH_VLAN_FILTER_MASK |
5958                ETH_VLAN_EXTEND_MASK;
5959         ret = i40e_vlan_offload_set(dev, mask);
5960         if (ret) {
5961                 PMD_DRV_LOG(INFO, "Failed to update vlan offload");
5962                 return ret;
5963         }
5964
5965         /* Apply pvid setting */
5966         ret = i40e_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
5967                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
5968         if (ret)
5969                 PMD_DRV_LOG(INFO, "Failed to update VSI params");
5970
5971         return ret;
5972 }
5973
5974 static int
5975 i40e_vsi_config_double_vlan(struct i40e_vsi *vsi, int on)
5976 {
5977         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
5978
5979         return i40e_aq_set_port_parameters(hw, vsi->seid, 0, 1, on, NULL);
5980 }
5981
5982 static int
5983 i40e_update_flow_control(struct i40e_hw *hw)
5984 {
5985 #define I40E_LINK_PAUSE_RXTX (I40E_AQ_LINK_PAUSE_RX | I40E_AQ_LINK_PAUSE_TX)
5986         struct i40e_link_status link_status;
5987         uint32_t rxfc = 0, txfc = 0, reg;
5988         uint8_t an_info;
5989         int ret;
5990
5991         memset(&link_status, 0, sizeof(link_status));
5992         ret = i40e_aq_get_link_info(hw, FALSE, &link_status, NULL);
5993         if (ret != I40E_SUCCESS) {
5994                 PMD_DRV_LOG(ERR, "Failed to get link status information");
5995                 goto write_reg; /* Disable flow control */
5996         }
5997
5998         an_info = hw->phy.link_info.an_info;
5999         if (!(an_info & I40E_AQ_AN_COMPLETED)) {
6000                 PMD_DRV_LOG(INFO, "Link auto negotiation not completed");
6001                 ret = I40E_ERR_NOT_READY;
6002                 goto write_reg; /* Disable flow control */
6003         }
6004         /**
6005          * If link auto negotiation is enabled, flow control needs to
6006          * be configured according to it
6007          */
6008         switch (an_info & I40E_LINK_PAUSE_RXTX) {
6009         case I40E_LINK_PAUSE_RXTX:
6010                 rxfc = 1;
6011                 txfc = 1;
6012                 hw->fc.current_mode = I40E_FC_FULL;
6013                 break;
6014         case I40E_AQ_LINK_PAUSE_RX:
6015                 rxfc = 1;
6016                 hw->fc.current_mode = I40E_FC_RX_PAUSE;
6017                 break;
6018         case I40E_AQ_LINK_PAUSE_TX:
6019                 txfc = 1;
6020                 hw->fc.current_mode = I40E_FC_TX_PAUSE;
6021                 break;
6022         default:
6023                 hw->fc.current_mode = I40E_FC_NONE;
6024                 break;
6025         }
6026
6027 write_reg:
6028         I40E_WRITE_REG(hw, I40E_PRTDCB_FCCFG,
6029                 txfc << I40E_PRTDCB_FCCFG_TFCE_SHIFT);
6030         reg = I40E_READ_REG(hw, I40E_PRTDCB_MFLCN);
6031         reg &= ~I40E_PRTDCB_MFLCN_RFCE_MASK;
6032         reg |= rxfc << I40E_PRTDCB_MFLCN_RFCE_SHIFT;
6033         I40E_WRITE_REG(hw, I40E_PRTDCB_MFLCN, reg);
6034
6035         return ret;
6036 }
6037
6038 /* PF setup */
6039 static int
6040 i40e_pf_setup(struct i40e_pf *pf)
6041 {
6042         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6043         struct i40e_filter_control_settings settings;
6044         struct i40e_vsi *vsi;
6045         int ret;
6046
6047         /* Clear all stats counters */
6048         pf->offset_loaded = FALSE;
6049         memset(&pf->stats, 0, sizeof(struct i40e_hw_port_stats));
6050         memset(&pf->stats_offset, 0, sizeof(struct i40e_hw_port_stats));
6051         memset(&pf->internal_stats, 0, sizeof(struct i40e_eth_stats));
6052         memset(&pf->internal_stats_offset, 0, sizeof(struct i40e_eth_stats));
6053
6054         ret = i40e_pf_get_switch_config(pf);
6055         if (ret != I40E_SUCCESS) {
6056                 PMD_DRV_LOG(ERR, "Could not get switch config, err %d", ret);
6057                 return ret;
6058         }
6059
6060         ret = rte_eth_switch_domain_alloc(&pf->switch_domain_id);
6061         if (ret)
6062                 PMD_INIT_LOG(WARNING,
6063                         "failed to allocate switch domain for device %d", ret);
6064
6065         if (pf->flags & I40E_FLAG_FDIR) {
6066                 /* make queue allocated first, let FDIR use queue pair 0*/
6067                 ret = i40e_res_pool_alloc(&pf->qp_pool, I40E_DEFAULT_QP_NUM_FDIR);
6068                 if (ret != I40E_FDIR_QUEUE_ID) {
6069                         PMD_DRV_LOG(ERR,
6070                                 "queue allocation fails for FDIR: ret =%d",
6071                                 ret);
6072                         pf->flags &= ~I40E_FLAG_FDIR;
6073                 }
6074         }
6075         /*  main VSI setup */
6076         vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, NULL, 0);
6077         if (!vsi) {
6078                 PMD_DRV_LOG(ERR, "Setup of main vsi failed");
6079                 return I40E_ERR_NOT_READY;
6080         }
6081         pf->main_vsi = vsi;
6082
6083         /* Configure filter control */
6084         memset(&settings, 0, sizeof(settings));
6085         if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_128)
6086                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_128;
6087         else if (hw->func_caps.rss_table_size == ETH_RSS_RETA_SIZE_512)
6088                 settings.hash_lut_size = I40E_HASH_LUT_SIZE_512;
6089         else {
6090                 PMD_DRV_LOG(ERR, "Hash lookup table size (%u) not supported",
6091                         hw->func_caps.rss_table_size);
6092                 return I40E_ERR_PARAM;
6093         }
6094         PMD_DRV_LOG(INFO, "Hardware capability of hash lookup table size: %u",
6095                 hw->func_caps.rss_table_size);
6096         pf->hash_lut_size = hw->func_caps.rss_table_size;
6097
6098         /* Enable ethtype and macvlan filters */
6099         settings.enable_ethtype = TRUE;
6100         settings.enable_macvlan = TRUE;
6101         ret = i40e_set_filter_control(hw, &settings);
6102         if (ret)
6103                 PMD_INIT_LOG(WARNING, "setup_pf_filter_control failed: %d",
6104                                                                 ret);
6105
6106         /* Update flow control according to the auto negotiation */
6107         i40e_update_flow_control(hw);
6108
6109         return I40E_SUCCESS;
6110 }
6111
6112 int
6113 i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6114 {
6115         uint32_t reg;
6116         uint16_t j;
6117
6118         /**
6119          * Set or clear TX Queue Disable flags,
6120          * which is required by hardware.
6121          */
6122         i40e_pre_tx_queue_cfg(hw, q_idx, on);
6123         rte_delay_us(I40E_PRE_TX_Q_CFG_WAIT_US);
6124
6125         /* Wait until the request is finished */
6126         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6127                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6128                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6129                 if (!(((reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6130                         ((reg >> I40E_QTX_ENA_QENA_STAT_SHIFT)
6131                                                         & 0x1))) {
6132                         break;
6133                 }
6134         }
6135         if (on) {
6136                 if (reg & I40E_QTX_ENA_QENA_STAT_MASK)
6137                         return I40E_SUCCESS; /* already on, skip next steps */
6138
6139                 I40E_WRITE_REG(hw, I40E_QTX_HEAD(q_idx), 0);
6140                 reg |= I40E_QTX_ENA_QENA_REQ_MASK;
6141         } else {
6142                 if (!(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6143                         return I40E_SUCCESS; /* already off, skip next steps */
6144                 reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
6145         }
6146         /* Write the register */
6147         I40E_WRITE_REG(hw, I40E_QTX_ENA(q_idx), reg);
6148         /* Check the result */
6149         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6150                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6151                 reg = I40E_READ_REG(hw, I40E_QTX_ENA(q_idx));
6152                 if (on) {
6153                         if ((reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6154                                 (reg & I40E_QTX_ENA_QENA_STAT_MASK))
6155                                 break;
6156                 } else {
6157                         if (!(reg & I40E_QTX_ENA_QENA_REQ_MASK) &&
6158                                 !(reg & I40E_QTX_ENA_QENA_STAT_MASK))
6159                                 break;
6160                 }
6161         }
6162         /* Check if it is timeout */
6163         if (j >= I40E_CHK_Q_ENA_COUNT) {
6164                 PMD_DRV_LOG(ERR, "Failed to %s tx queue[%u]",
6165                             (on ? "enable" : "disable"), q_idx);
6166                 return I40E_ERR_TIMEOUT;
6167         }
6168
6169         return I40E_SUCCESS;
6170 }
6171
6172 /* Swith on or off the tx queues */
6173 static int
6174 i40e_dev_switch_tx_queues(struct i40e_pf *pf, bool on)
6175 {
6176         struct rte_eth_dev_data *dev_data = pf->dev_data;
6177         struct i40e_tx_queue *txq;
6178         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6179         uint16_t i;
6180         int ret;
6181
6182         for (i = 0; i < dev_data->nb_tx_queues; i++) {
6183                 txq = dev_data->tx_queues[i];
6184                 /* Don't operate the queue if not configured or
6185                  * if starting only per queue */
6186                 if (!txq || !txq->q_set || (on && txq->tx_deferred_start))
6187                         continue;
6188                 if (on)
6189                         ret = i40e_dev_tx_queue_start(dev, i);
6190                 else
6191                         ret = i40e_dev_tx_queue_stop(dev, i);
6192                 if ( ret != I40E_SUCCESS)
6193                         return ret;
6194         }
6195
6196         return I40E_SUCCESS;
6197 }
6198
6199 int
6200 i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on)
6201 {
6202         uint32_t reg;
6203         uint16_t j;
6204
6205         /* Wait until the request is finished */
6206         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6207                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6208                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6209                 if (!((reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 0x1) ^
6210                         ((reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 0x1))
6211                         break;
6212         }
6213
6214         if (on) {
6215                 if (reg & I40E_QRX_ENA_QENA_STAT_MASK)
6216                         return I40E_SUCCESS; /* Already on, skip next steps */
6217                 reg |= I40E_QRX_ENA_QENA_REQ_MASK;
6218         } else {
6219                 if (!(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6220                         return I40E_SUCCESS; /* Already off, skip next steps */
6221                 reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
6222         }
6223
6224         /* Write the register */
6225         I40E_WRITE_REG(hw, I40E_QRX_ENA(q_idx), reg);
6226         /* Check the result */
6227         for (j = 0; j < I40E_CHK_Q_ENA_COUNT; j++) {
6228                 rte_delay_us(I40E_CHK_Q_ENA_INTERVAL_US);
6229                 reg = I40E_READ_REG(hw, I40E_QRX_ENA(q_idx));
6230                 if (on) {
6231                         if ((reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6232                                 (reg & I40E_QRX_ENA_QENA_STAT_MASK))
6233                                 break;
6234                 } else {
6235                         if (!(reg & I40E_QRX_ENA_QENA_REQ_MASK) &&
6236                                 !(reg & I40E_QRX_ENA_QENA_STAT_MASK))
6237                                 break;
6238                 }
6239         }
6240
6241         /* Check if it is timeout */
6242         if (j >= I40E_CHK_Q_ENA_COUNT) {
6243                 PMD_DRV_LOG(ERR, "Failed to %s rx queue[%u]",
6244                             (on ? "enable" : "disable"), q_idx);
6245                 return I40E_ERR_TIMEOUT;
6246         }
6247
6248         return I40E_SUCCESS;
6249 }
6250 /* Switch on or off the rx queues */
6251 static int
6252 i40e_dev_switch_rx_queues(struct i40e_pf *pf, bool on)
6253 {
6254         struct rte_eth_dev_data *dev_data = pf->dev_data;
6255         struct i40e_rx_queue *rxq;
6256         struct rte_eth_dev *dev = pf->adapter->eth_dev;
6257         uint16_t i;
6258         int ret;
6259
6260         for (i = 0; i < dev_data->nb_rx_queues; i++) {
6261                 rxq = dev_data->rx_queues[i];
6262                 /* Don't operate the queue if not configured or
6263                  * if starting only per queue */
6264                 if (!rxq || !rxq->q_set || (on && rxq->rx_deferred_start))
6265                         continue;
6266                 if (on)
6267                         ret = i40e_dev_rx_queue_start(dev, i);
6268                 else
6269                         ret = i40e_dev_rx_queue_stop(dev, i);
6270                 if (ret != I40E_SUCCESS)
6271                         return ret;
6272         }
6273
6274         return I40E_SUCCESS;
6275 }
6276
6277 /* Switch on or off all the rx/tx queues */
6278 int
6279 i40e_dev_switch_queues(struct i40e_pf *pf, bool on)
6280 {
6281         int ret;
6282
6283         if (on) {
6284                 /* enable rx queues before enabling tx queues */
6285                 ret = i40e_dev_switch_rx_queues(pf, on);
6286                 if (ret) {
6287                         PMD_DRV_LOG(ERR, "Failed to switch rx queues");
6288                         return ret;
6289                 }
6290                 ret = i40e_dev_switch_tx_queues(pf, on);
6291         } else {
6292                 /* Stop tx queues before stopping rx queues */
6293                 ret = i40e_dev_switch_tx_queues(pf, on);
6294                 if (ret) {
6295                         PMD_DRV_LOG(ERR, "Failed to switch tx queues");
6296                         return ret;
6297                 }
6298                 ret = i40e_dev_switch_rx_queues(pf, on);
6299         }
6300
6301         return ret;
6302 }
6303
6304 /* Initialize VSI for TX */
6305 static int
6306 i40e_dev_tx_init(struct i40e_pf *pf)
6307 {
6308         struct rte_eth_dev_data *data = pf->dev_data;
6309         uint16_t i;
6310         uint32_t ret = I40E_SUCCESS;
6311         struct i40e_tx_queue *txq;
6312
6313         for (i = 0; i < data->nb_tx_queues; i++) {
6314                 txq = data->tx_queues[i];
6315                 if (!txq || !txq->q_set)
6316                         continue;
6317                 ret = i40e_tx_queue_init(txq);
6318                 if (ret != I40E_SUCCESS)
6319                         break;
6320         }
6321         if (ret == I40E_SUCCESS)
6322                 i40e_set_tx_function(container_of(pf, struct i40e_adapter, pf)
6323                                      ->eth_dev);
6324
6325         return ret;
6326 }
6327
6328 /* Initialize VSI for RX */
6329 static int
6330 i40e_dev_rx_init(struct i40e_pf *pf)
6331 {
6332         struct rte_eth_dev_data *data = pf->dev_data;
6333         int ret = I40E_SUCCESS;
6334         uint16_t i;
6335         struct i40e_rx_queue *rxq;
6336
6337         i40e_pf_config_mq_rx(pf);
6338         for (i = 0; i < data->nb_rx_queues; i++) {
6339                 rxq = data->rx_queues[i];
6340                 if (!rxq || !rxq->q_set)
6341                         continue;
6342
6343                 ret = i40e_rx_queue_init(rxq);
6344                 if (ret != I40E_SUCCESS) {
6345                         PMD_DRV_LOG(ERR,
6346                                 "Failed to do RX queue initialization");
6347                         break;
6348                 }
6349         }
6350         if (ret == I40E_SUCCESS)
6351                 i40e_set_rx_function(container_of(pf, struct i40e_adapter, pf)
6352                                      ->eth_dev);
6353
6354         return ret;
6355 }
6356
6357 static int
6358 i40e_dev_rxtx_init(struct i40e_pf *pf)
6359 {
6360         int err;
6361
6362         err = i40e_dev_tx_init(pf);
6363         if (err) {
6364                 PMD_DRV_LOG(ERR, "Failed to do TX initialization");
6365                 return err;
6366         }
6367         err = i40e_dev_rx_init(pf);
6368         if (err) {
6369                 PMD_DRV_LOG(ERR, "Failed to do RX initialization");
6370                 return err;
6371         }
6372
6373         return err;
6374 }
6375
6376 static int
6377 i40e_vmdq_setup(struct rte_eth_dev *dev)
6378 {
6379         struct rte_eth_conf *conf = &dev->data->dev_conf;
6380         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6381         int i, err, conf_vsis, j, loop;
6382         struct i40e_vsi *vsi;
6383         struct i40e_vmdq_info *vmdq_info;
6384         struct rte_eth_vmdq_rx_conf *vmdq_conf;
6385         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
6386
6387         /*
6388          * Disable interrupt to avoid message from VF. Furthermore, it will
6389          * avoid race condition in VSI creation/destroy.
6390          */
6391         i40e_pf_disable_irq0(hw);
6392
6393         if ((pf->flags & I40E_FLAG_VMDQ) == 0) {
6394                 PMD_INIT_LOG(ERR, "FW doesn't support VMDQ");
6395                 return -ENOTSUP;
6396         }
6397
6398         conf_vsis = conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools;
6399         if (conf_vsis > pf->max_nb_vmdq_vsi) {
6400                 PMD_INIT_LOG(ERR, "VMDQ config: %u, max support:%u",
6401                         conf->rx_adv_conf.vmdq_rx_conf.nb_queue_pools,
6402                         pf->max_nb_vmdq_vsi);
6403                 return -ENOTSUP;
6404         }
6405
6406         if (pf->vmdq != NULL) {
6407                 PMD_INIT_LOG(INFO, "VMDQ already configured");
6408                 return 0;
6409         }
6410
6411         pf->vmdq = rte_zmalloc("vmdq_info_struct",
6412                                 sizeof(*vmdq_info) * conf_vsis, 0);
6413
6414         if (pf->vmdq == NULL) {
6415                 PMD_INIT_LOG(ERR, "Failed to allocate memory");
6416                 return -ENOMEM;
6417         }
6418
6419         vmdq_conf = &conf->rx_adv_conf.vmdq_rx_conf;
6420
6421         /* Create VMDQ VSI */
6422         for (i = 0; i < conf_vsis; i++) {
6423                 vsi = i40e_vsi_setup(pf, I40E_VSI_VMDQ2, pf->main_vsi,
6424                                 vmdq_conf->enable_loop_back);
6425                 if (vsi == NULL) {
6426                         PMD_INIT_LOG(ERR, "Failed to create VMDQ VSI");
6427                         err = -1;
6428                         goto err_vsi_setup;
6429                 }
6430                 vmdq_info = &pf->vmdq[i];
6431                 vmdq_info->pf = pf;
6432                 vmdq_info->vsi = vsi;
6433         }
6434         pf->nb_cfg_vmdq_vsi = conf_vsis;
6435
6436         /* Configure Vlan */
6437         loop = sizeof(vmdq_conf->pool_map[0].pools) * CHAR_BIT;
6438         for (i = 0; i < vmdq_conf->nb_pool_maps; i++) {
6439                 for (j = 0; j < loop && j < pf->nb_cfg_vmdq_vsi; j++) {
6440                         if (vmdq_conf->pool_map[i].pools & (1UL << j)) {
6441                                 PMD_INIT_LOG(INFO, "Add vlan %u to vmdq pool %u",
6442                                         vmdq_conf->pool_map[i].vlan_id, j);
6443
6444                                 err = i40e_vsi_add_vlan(pf->vmdq[j].vsi,
6445                                                 vmdq_conf->pool_map[i].vlan_id);
6446                                 if (err) {
6447                                         PMD_INIT_LOG(ERR, "Failed to add vlan");
6448                                         err = -1;
6449                                         goto err_vsi_setup;
6450                                 }
6451                         }
6452                 }
6453         }
6454
6455         i40e_pf_enable_irq0(hw);
6456
6457         return 0;
6458
6459 err_vsi_setup:
6460         for (i = 0; i < conf_vsis; i++)
6461                 if (pf->vmdq[i].vsi == NULL)
6462                         break;
6463                 else
6464                         i40e_vsi_release(pf->vmdq[i].vsi);
6465
6466         rte_free(pf->vmdq);
6467         pf->vmdq = NULL;
6468         i40e_pf_enable_irq0(hw);
6469         return err;
6470 }
6471
6472 static void
6473 i40e_stat_update_32(struct i40e_hw *hw,
6474                    uint32_t reg,
6475                    bool offset_loaded,
6476                    uint64_t *offset,
6477                    uint64_t *stat)
6478 {
6479         uint64_t new_data;
6480
6481         new_data = (uint64_t)I40E_READ_REG(hw, reg);
6482         if (!offset_loaded)
6483                 *offset = new_data;
6484
6485         if (new_data >= *offset)
6486                 *stat = (uint64_t)(new_data - *offset);
6487         else
6488                 *stat = (uint64_t)((new_data +
6489                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
6490 }
6491
6492 static void
6493 i40e_stat_update_48(struct i40e_hw *hw,
6494                    uint32_t hireg,
6495                    uint32_t loreg,
6496                    bool offset_loaded,
6497                    uint64_t *offset,
6498                    uint64_t *stat)
6499 {
6500         uint64_t new_data;
6501
6502         new_data = (uint64_t)I40E_READ_REG(hw, loreg);
6503         new_data |= ((uint64_t)(I40E_READ_REG(hw, hireg) &
6504                         I40E_16_BIT_MASK)) << I40E_32_BIT_WIDTH;
6505
6506         if (!offset_loaded)
6507                 *offset = new_data;
6508
6509         if (new_data >= *offset)
6510                 *stat = new_data - *offset;
6511         else
6512                 *stat = (uint64_t)((new_data +
6513                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
6514
6515         *stat &= I40E_48_BIT_MASK;
6516 }
6517
6518 /* Disable IRQ0 */
6519 void
6520 i40e_pf_disable_irq0(struct i40e_hw *hw)
6521 {
6522         /* Disable all interrupt types */
6523         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6524                        I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6525         I40E_WRITE_FLUSH(hw);
6526 }
6527
6528 /* Enable IRQ0 */
6529 void
6530 i40e_pf_enable_irq0(struct i40e_hw *hw)
6531 {
6532         I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
6533                 I40E_PFINT_DYN_CTL0_INTENA_MASK |
6534                 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
6535                 I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
6536         I40E_WRITE_FLUSH(hw);
6537 }
6538
6539 static void
6540 i40e_pf_config_irq0(struct i40e_hw *hw, bool no_queue)
6541 {
6542         /* read pending request and disable first */
6543         i40e_pf_disable_irq0(hw);
6544         I40E_WRITE_REG(hw, I40E_PFINT_ICR0_ENA, I40E_PFINT_ICR0_ENA_MASK);
6545         I40E_WRITE_REG(hw, I40E_PFINT_STAT_CTL0,
6546                 I40E_PFINT_STAT_CTL0_OTHER_ITR_INDX_MASK);
6547
6548         if (no_queue)
6549                 /* Link no queues with irq0 */
6550                 I40E_WRITE_REG(hw, I40E_PFINT_LNKLST0,
6551                                I40E_PFINT_LNKLST0_FIRSTQ_INDX_MASK);
6552 }
6553
6554 static void
6555 i40e_dev_handle_vfr_event(struct rte_eth_dev *dev)
6556 {
6557         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6558         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6559         int i;
6560         uint16_t abs_vf_id;
6561         uint32_t index, offset, val;
6562
6563         if (!pf->vfs)
6564                 return;
6565         /**
6566          * Try to find which VF trigger a reset, use absolute VF id to access
6567          * since the reg is global register.
6568          */
6569         for (i = 0; i < pf->vf_num; i++) {
6570                 abs_vf_id = hw->func_caps.vf_base_id + i;
6571                 index = abs_vf_id / I40E_UINT32_BIT_SIZE;
6572                 offset = abs_vf_id % I40E_UINT32_BIT_SIZE;
6573                 val = I40E_READ_REG(hw, I40E_GLGEN_VFLRSTAT(index));
6574                 /* VFR event occurred */
6575                 if (val & (0x1 << offset)) {
6576                         int ret;
6577
6578                         /* Clear the event first */
6579                         I40E_WRITE_REG(hw, I40E_GLGEN_VFLRSTAT(index),
6580                                                         (0x1 << offset));
6581                         PMD_DRV_LOG(INFO, "VF %u reset occurred", abs_vf_id);
6582                         /**
6583                          * Only notify a VF reset event occurred,
6584                          * don't trigger another SW reset
6585                          */
6586                         ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
6587                         if (ret != I40E_SUCCESS)
6588                                 PMD_DRV_LOG(ERR, "Failed to do VF reset");
6589                 }
6590         }
6591 }
6592
6593 static void
6594 i40e_notify_all_vfs_link_status(struct rte_eth_dev *dev)
6595 {
6596         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
6597         int i;
6598
6599         for (i = 0; i < pf->vf_num; i++)
6600                 i40e_notify_vf_link_status(dev, &pf->vfs[i]);
6601 }
6602
6603 static void
6604 i40e_dev_handle_aq_msg(struct rte_eth_dev *dev)
6605 {
6606         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6607         struct i40e_arq_event_info info;
6608         uint16_t pending, opcode;
6609         int ret;
6610
6611         info.buf_len = I40E_AQ_BUF_SZ;
6612         info.msg_buf = rte_zmalloc("msg_buffer", info.buf_len, 0);
6613         if (!info.msg_buf) {
6614                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
6615                 return;
6616         }
6617
6618         pending = 1;
6619         while (pending) {
6620                 ret = i40e_clean_arq_element(hw, &info, &pending);
6621
6622                 if (ret != I40E_SUCCESS) {
6623                         PMD_DRV_LOG(INFO,
6624                                 "Failed to read msg from AdminQ, aq_err: %u",
6625                                 hw->aq.asq_last_status);
6626                         break;
6627                 }
6628                 opcode = rte_le_to_cpu_16(info.desc.opcode);
6629
6630                 switch (opcode) {
6631                 case i40e_aqc_opc_send_msg_to_pf:
6632                         /* Refer to i40e_aq_send_msg_to_pf() for argument layout*/
6633                         i40e_pf_host_handle_vf_msg(dev,
6634                                         rte_le_to_cpu_16(info.desc.retval),
6635                                         rte_le_to_cpu_32(info.desc.cookie_high),
6636                                         rte_le_to_cpu_32(info.desc.cookie_low),
6637                                         info.msg_buf,
6638                                         info.msg_len);
6639                         break;
6640                 case i40e_aqc_opc_get_link_status:
6641                         ret = i40e_dev_link_update(dev, 0);
6642                         if (!ret)
6643                                 _rte_eth_dev_callback_process(dev,
6644                                         RTE_ETH_EVENT_INTR_LSC, NULL);
6645                         break;
6646                 default:
6647                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
6648                                     opcode);
6649                         break;
6650                 }
6651         }
6652         rte_free(info.msg_buf);
6653 }
6654
6655 /**
6656  * Interrupt handler triggered by NIC  for handling
6657  * specific interrupt.
6658  *
6659  * @param handle
6660  *  Pointer to interrupt handle.
6661  * @param param
6662  *  The address of parameter (struct rte_eth_dev *) regsitered before.
6663  *
6664  * @return
6665  *  void
6666  */
6667 static void
6668 i40e_dev_interrupt_handler(void *param)
6669 {
6670         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6671         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6672         uint32_t icr0;
6673
6674         /* Disable interrupt */
6675         i40e_pf_disable_irq0(hw);
6676
6677         /* read out interrupt causes */
6678         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6679
6680         /* No interrupt event indicated */
6681         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK)) {
6682                 PMD_DRV_LOG(INFO, "No interrupt event");
6683                 goto done;
6684         }
6685         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6686                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6687         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6688                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6689         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6690                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6691         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6692                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6693         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6694                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6695         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6696                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6697         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6698                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6699
6700         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6701                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6702                 i40e_dev_handle_vfr_event(dev);
6703         }
6704         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6705                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6706                 i40e_dev_handle_aq_msg(dev);
6707         }
6708
6709 done:
6710         /* Enable interrupt */
6711         i40e_pf_enable_irq0(hw);
6712 }
6713
6714 static void
6715 i40e_dev_alarm_handler(void *param)
6716 {
6717         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
6718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
6719         uint32_t icr0;
6720
6721         /* Disable interrupt */
6722         i40e_pf_disable_irq0(hw);
6723
6724         /* read out interrupt causes */
6725         icr0 = I40E_READ_REG(hw, I40E_PFINT_ICR0);
6726
6727         /* No interrupt event indicated */
6728         if (!(icr0 & I40E_PFINT_ICR0_INTEVENT_MASK))
6729                 goto done;
6730         if (icr0 & I40E_PFINT_ICR0_ECC_ERR_MASK)
6731                 PMD_DRV_LOG(ERR, "ICR0: unrecoverable ECC error");
6732         if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK)
6733                 PMD_DRV_LOG(ERR, "ICR0: malicious programming detected");
6734         if (icr0 & I40E_PFINT_ICR0_GRST_MASK)
6735                 PMD_DRV_LOG(INFO, "ICR0: global reset requested");
6736         if (icr0 & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK)
6737                 PMD_DRV_LOG(INFO, "ICR0: PCI exception activated");
6738         if (icr0 & I40E_PFINT_ICR0_STORM_DETECT_MASK)
6739                 PMD_DRV_LOG(INFO, "ICR0: a change in the storm control state");
6740         if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK)
6741                 PMD_DRV_LOG(ERR, "ICR0: HMC error");
6742         if (icr0 & I40E_PFINT_ICR0_PE_CRITERR_MASK)
6743                 PMD_DRV_LOG(ERR, "ICR0: protocol engine critical error");
6744
6745         if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
6746                 PMD_DRV_LOG(INFO, "ICR0: VF reset detected");
6747                 i40e_dev_handle_vfr_event(dev);
6748         }
6749         if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
6750                 PMD_DRV_LOG(INFO, "ICR0: adminq event");
6751                 i40e_dev_handle_aq_msg(dev);
6752         }
6753
6754 done:
6755         /* Enable interrupt */
6756         i40e_pf_enable_irq0(hw);
6757         rte_eal_alarm_set(I40E_ALARM_INTERVAL,
6758                           i40e_dev_alarm_handler, dev);
6759 }
6760
6761 int
6762 i40e_add_macvlan_filters(struct i40e_vsi *vsi,
6763                          struct i40e_macvlan_filter *filter,
6764                          int total)
6765 {
6766         int ele_num, ele_buff_size;
6767         int num, actual_num, i;
6768         uint16_t flags;
6769         int ret = I40E_SUCCESS;
6770         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6771         struct i40e_aqc_add_macvlan_element_data *req_list;
6772
6773         if (filter == NULL  || total == 0)
6774                 return I40E_ERR_PARAM;
6775         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6776         ele_buff_size = hw->aq.asq_buf_size;
6777
6778         req_list = rte_zmalloc("macvlan_add", ele_buff_size, 0);
6779         if (req_list == NULL) {
6780                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6781                 return I40E_ERR_NO_MEMORY;
6782         }
6783
6784         num = 0;
6785         do {
6786                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6787                 memset(req_list, 0, ele_buff_size);
6788
6789                 for (i = 0; i < actual_num; i++) {
6790                         rte_memcpy(req_list[i].mac_addr,
6791                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6792                         req_list[i].vlan_tag =
6793                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6794
6795                         switch (filter[num + i].filter_type) {
6796                         case RTE_MAC_PERFECT_MATCH:
6797                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH |
6798                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6799                                 break;
6800                         case RTE_MACVLAN_PERFECT_MATCH:
6801                                 flags = I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
6802                                 break;
6803                         case RTE_MAC_HASH_MATCH:
6804                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH |
6805                                         I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
6806                                 break;
6807                         case RTE_MACVLAN_HASH_MATCH:
6808                                 flags = I40E_AQC_MACVLAN_ADD_HASH_MATCH;
6809                                 break;
6810                         default:
6811                                 PMD_DRV_LOG(ERR, "Invalid MAC match type");
6812                                 ret = I40E_ERR_PARAM;
6813                                 goto DONE;
6814                         }
6815
6816                         req_list[i].queue_number = 0;
6817
6818                         req_list[i].flags = rte_cpu_to_le_16(flags);
6819                 }
6820
6821                 ret = i40e_aq_add_macvlan(hw, vsi->seid, req_list,
6822                                                 actual_num, NULL);
6823                 if (ret != I40E_SUCCESS) {
6824                         PMD_DRV_LOG(ERR, "Failed to add macvlan filter");
6825                         goto DONE;
6826                 }
6827                 num += actual_num;
6828         } while (num < total);
6829
6830 DONE:
6831         rte_free(req_list);
6832         return ret;
6833 }
6834
6835 int
6836 i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
6837                             struct i40e_macvlan_filter *filter,
6838                             int total)
6839 {
6840         int ele_num, ele_buff_size;
6841         int num, actual_num, i;
6842         uint16_t flags;
6843         int ret = I40E_SUCCESS;
6844         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6845         struct i40e_aqc_remove_macvlan_element_data *req_list;
6846
6847         if (filter == NULL  || total == 0)
6848                 return I40E_ERR_PARAM;
6849
6850         ele_num = hw->aq.asq_buf_size / sizeof(*req_list);
6851         ele_buff_size = hw->aq.asq_buf_size;
6852
6853         req_list = rte_zmalloc("macvlan_remove", ele_buff_size, 0);
6854         if (req_list == NULL) {
6855                 PMD_DRV_LOG(ERR, "Fail to allocate memory");
6856                 return I40E_ERR_NO_MEMORY;
6857         }
6858
6859         num = 0;
6860         do {
6861                 actual_num = (num + ele_num > total) ? (total - num) : ele_num;
6862                 memset(req_list, 0, ele_buff_size);
6863
6864                 for (i = 0; i < actual_num; i++) {
6865                         rte_memcpy(req_list[i].mac_addr,
6866                                 &filter[num + i].macaddr, ETH_ADDR_LEN);
6867                         req_list[i].vlan_tag =
6868                                 rte_cpu_to_le_16(filter[num + i].vlan_id);
6869
6870                         switch (filter[num + i].filter_type) {
6871                         case RTE_MAC_PERFECT_MATCH:
6872                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
6873                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6874                                 break;
6875                         case RTE_MACVLAN_PERFECT_MATCH:
6876                                 flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
6877                                 break;
6878                         case RTE_MAC_HASH_MATCH:
6879                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH |
6880                                         I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
6881                                 break;
6882                         case RTE_MACVLAN_HASH_MATCH:
6883                                 flags = I40E_AQC_MACVLAN_DEL_HASH_MATCH;
6884                                 break;
6885                         default:
6886                                 PMD_DRV_LOG(ERR, "Invalid MAC filter type");
6887                                 ret = I40E_ERR_PARAM;
6888                                 goto DONE;
6889                         }
6890                         req_list[i].flags = rte_cpu_to_le_16(flags);
6891                 }
6892
6893                 ret = i40e_aq_remove_macvlan(hw, vsi->seid, req_list,
6894                                                 actual_num, NULL);
6895                 if (ret != I40E_SUCCESS) {
6896                         PMD_DRV_LOG(ERR, "Failed to remove macvlan filter");
6897                         goto DONE;
6898                 }
6899                 num += actual_num;
6900         } while (num < total);
6901
6902 DONE:
6903         rte_free(req_list);
6904         return ret;
6905 }
6906
6907 /* Find out specific MAC filter */
6908 static struct i40e_mac_filter *
6909 i40e_find_mac_filter(struct i40e_vsi *vsi,
6910                          struct rte_ether_addr *macaddr)
6911 {
6912         struct i40e_mac_filter *f;
6913
6914         TAILQ_FOREACH(f, &vsi->mac_list, next) {
6915                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
6916                         return f;
6917         }
6918
6919         return NULL;
6920 }
6921
6922 static bool
6923 i40e_find_vlan_filter(struct i40e_vsi *vsi,
6924                          uint16_t vlan_id)
6925 {
6926         uint32_t vid_idx, vid_bit;
6927
6928         if (vlan_id > ETH_VLAN_ID_MAX)
6929                 return 0;
6930
6931         vid_idx = I40E_VFTA_IDX(vlan_id);
6932         vid_bit = I40E_VFTA_BIT(vlan_id);
6933
6934         if (vsi->vfta[vid_idx] & vid_bit)
6935                 return 1;
6936         else
6937                 return 0;
6938 }
6939
6940 static void
6941 i40e_store_vlan_filter(struct i40e_vsi *vsi,
6942                        uint16_t vlan_id, bool on)
6943 {
6944         uint32_t vid_idx, vid_bit;
6945
6946         vid_idx = I40E_VFTA_IDX(vlan_id);
6947         vid_bit = I40E_VFTA_BIT(vlan_id);
6948
6949         if (on)
6950                 vsi->vfta[vid_idx] |= vid_bit;
6951         else
6952                 vsi->vfta[vid_idx] &= ~vid_bit;
6953 }
6954
6955 void
6956 i40e_set_vlan_filter(struct i40e_vsi *vsi,
6957                      uint16_t vlan_id, bool on)
6958 {
6959         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
6960         struct i40e_aqc_add_remove_vlan_element_data vlan_data = {0};
6961         int ret;
6962
6963         if (vlan_id > ETH_VLAN_ID_MAX)
6964                 return;
6965
6966         i40e_store_vlan_filter(vsi, vlan_id, on);
6967
6968         if ((!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on) || !vlan_id)
6969                 return;
6970
6971         vlan_data.vlan_tag = rte_cpu_to_le_16(vlan_id);
6972
6973         if (on) {
6974                 ret = i40e_aq_add_vlan(hw, vsi->seid,
6975                                        &vlan_data, 1, NULL);
6976                 if (ret != I40E_SUCCESS)
6977                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
6978         } else {
6979                 ret = i40e_aq_remove_vlan(hw, vsi->seid,
6980                                           &vlan_data, 1, NULL);
6981                 if (ret != I40E_SUCCESS)
6982                         PMD_DRV_LOG(ERR,
6983                                     "Failed to remove vlan filter");
6984         }
6985 }
6986
6987 /**
6988  * Find all vlan options for specific mac addr,
6989  * return with actual vlan found.
6990  */
6991 int
6992 i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
6993                            struct i40e_macvlan_filter *mv_f,
6994                            int num, struct rte_ether_addr *addr)
6995 {
6996         int i;
6997         uint32_t j, k;
6998
6999         /**
7000          * Not to use i40e_find_vlan_filter to decrease the loop time,
7001          * although the code looks complex.
7002           */
7003         if (num < vsi->vlan_num)
7004                 return I40E_ERR_PARAM;
7005
7006         i = 0;
7007         for (j = 0; j < I40E_VFTA_SIZE; j++) {
7008                 if (vsi->vfta[j]) {
7009                         for (k = 0; k < I40E_UINT32_BIT_SIZE; k++) {
7010                                 if (vsi->vfta[j] & (1 << k)) {
7011                                         if (i > num - 1) {
7012                                                 PMD_DRV_LOG(ERR,
7013                                                         "vlan number doesn't match");
7014                                                 return I40E_ERR_PARAM;
7015                                         }
7016                                         rte_memcpy(&mv_f[i].macaddr,
7017                                                         addr, ETH_ADDR_LEN);
7018                                         mv_f[i].vlan_id =
7019                                                 j * I40E_UINT32_BIT_SIZE + k;
7020                                         i++;
7021                                 }
7022                         }
7023                 }
7024         }
7025         return I40E_SUCCESS;
7026 }
7027
7028 static inline int
7029 i40e_find_all_mac_for_vlan(struct i40e_vsi *vsi,
7030                            struct i40e_macvlan_filter *mv_f,
7031                            int num,
7032                            uint16_t vlan)
7033 {
7034         int i = 0;
7035         struct i40e_mac_filter *f;
7036
7037         if (num < vsi->mac_num)
7038                 return I40E_ERR_PARAM;
7039
7040         TAILQ_FOREACH(f, &vsi->mac_list, next) {
7041                 if (i > num - 1) {
7042                         PMD_DRV_LOG(ERR, "buffer number not match");
7043                         return I40E_ERR_PARAM;
7044                 }
7045                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7046                                 ETH_ADDR_LEN);
7047                 mv_f[i].vlan_id = vlan;
7048                 mv_f[i].filter_type = f->mac_info.filter_type;
7049                 i++;
7050         }
7051
7052         return I40E_SUCCESS;
7053 }
7054
7055 static int
7056 i40e_vsi_remove_all_macvlan_filter(struct i40e_vsi *vsi)
7057 {
7058         int i, j, num;
7059         struct i40e_mac_filter *f;
7060         struct i40e_macvlan_filter *mv_f;
7061         int ret = I40E_SUCCESS;
7062
7063         if (vsi == NULL || vsi->mac_num == 0)
7064                 return I40E_ERR_PARAM;
7065
7066         /* Case that no vlan is set */
7067         if (vsi->vlan_num == 0)
7068                 num = vsi->mac_num;
7069         else
7070                 num = vsi->mac_num * vsi->vlan_num;
7071
7072         mv_f = rte_zmalloc("macvlan_data", num * sizeof(*mv_f), 0);
7073         if (mv_f == NULL) {
7074                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7075                 return I40E_ERR_NO_MEMORY;
7076         }
7077
7078         i = 0;
7079         if (vsi->vlan_num == 0) {
7080                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7081                         rte_memcpy(&mv_f[i].macaddr,
7082                                 &f->mac_info.mac_addr, ETH_ADDR_LEN);
7083                         mv_f[i].filter_type = f->mac_info.filter_type;
7084                         mv_f[i].vlan_id = 0;
7085                         i++;
7086                 }
7087         } else {
7088                 TAILQ_FOREACH(f, &vsi->mac_list, next) {
7089                         ret = i40e_find_all_vlan_for_mac(vsi,&mv_f[i],
7090                                         vsi->vlan_num, &f->mac_info.mac_addr);
7091                         if (ret != I40E_SUCCESS)
7092                                 goto DONE;
7093                         for (j = i; j < i + vsi->vlan_num; j++)
7094                                 mv_f[j].filter_type = f->mac_info.filter_type;
7095                         i += vsi->vlan_num;
7096                 }
7097         }
7098
7099         ret = i40e_remove_macvlan_filters(vsi, mv_f, num);
7100 DONE:
7101         rte_free(mv_f);
7102
7103         return ret;
7104 }
7105
7106 int
7107 i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7108 {
7109         struct i40e_macvlan_filter *mv_f;
7110         int mac_num;
7111         int ret = I40E_SUCCESS;
7112
7113         if (!vsi || vlan > RTE_ETHER_MAX_VLAN_ID)
7114                 return I40E_ERR_PARAM;
7115
7116         /* If it's already set, just return */
7117         if (i40e_find_vlan_filter(vsi,vlan))
7118                 return I40E_SUCCESS;
7119
7120         mac_num = vsi->mac_num;
7121
7122         if (mac_num == 0) {
7123                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7124                 return I40E_ERR_PARAM;
7125         }
7126
7127         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7128
7129         if (mv_f == NULL) {
7130                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7131                 return I40E_ERR_NO_MEMORY;
7132         }
7133
7134         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7135
7136         if (ret != I40E_SUCCESS)
7137                 goto DONE;
7138
7139         ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7140
7141         if (ret != I40E_SUCCESS)
7142                 goto DONE;
7143
7144         i40e_set_vlan_filter(vsi, vlan, 1);
7145
7146         vsi->vlan_num++;
7147         ret = I40E_SUCCESS;
7148 DONE:
7149         rte_free(mv_f);
7150         return ret;
7151 }
7152
7153 int
7154 i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan)
7155 {
7156         struct i40e_macvlan_filter *mv_f;
7157         int mac_num;
7158         int ret = I40E_SUCCESS;
7159
7160         /**
7161          * Vlan 0 is the generic filter for untagged packets
7162          * and can't be removed.
7163          */
7164         if (!vsi || vlan == 0 || vlan > RTE_ETHER_MAX_VLAN_ID)
7165                 return I40E_ERR_PARAM;
7166
7167         /* If can't find it, just return */
7168         if (!i40e_find_vlan_filter(vsi, vlan))
7169                 return I40E_ERR_PARAM;
7170
7171         mac_num = vsi->mac_num;
7172
7173         if (mac_num == 0) {
7174                 PMD_DRV_LOG(ERR, "Error! VSI doesn't have a mac addr");
7175                 return I40E_ERR_PARAM;
7176         }
7177
7178         mv_f = rte_zmalloc("macvlan_data", mac_num * sizeof(*mv_f), 0);
7179
7180         if (mv_f == NULL) {
7181                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7182                 return I40E_ERR_NO_MEMORY;
7183         }
7184
7185         ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, vlan);
7186
7187         if (ret != I40E_SUCCESS)
7188                 goto DONE;
7189
7190         ret = i40e_remove_macvlan_filters(vsi, mv_f, mac_num);
7191
7192         if (ret != I40E_SUCCESS)
7193                 goto DONE;
7194
7195         /* This is last vlan to remove, replace all mac filter with vlan 0 */
7196         if (vsi->vlan_num == 1) {
7197                 ret = i40e_find_all_mac_for_vlan(vsi, mv_f, mac_num, 0);
7198                 if (ret != I40E_SUCCESS)
7199                         goto DONE;
7200
7201                 ret = i40e_add_macvlan_filters(vsi, mv_f, mac_num);
7202                 if (ret != I40E_SUCCESS)
7203                         goto DONE;
7204         }
7205
7206         i40e_set_vlan_filter(vsi, vlan, 0);
7207
7208         vsi->vlan_num--;
7209         ret = I40E_SUCCESS;
7210 DONE:
7211         rte_free(mv_f);
7212         return ret;
7213 }
7214
7215 int
7216 i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *mac_filter)
7217 {
7218         struct i40e_mac_filter *f;
7219         struct i40e_macvlan_filter *mv_f;
7220         int i, vlan_num = 0;
7221         int ret = I40E_SUCCESS;
7222
7223         /* If it's add and we've config it, return */
7224         f = i40e_find_mac_filter(vsi, &mac_filter->mac_addr);
7225         if (f != NULL)
7226                 return I40E_SUCCESS;
7227         if ((mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH) ||
7228                 (mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH)) {
7229
7230                 /**
7231                  * If vlan_num is 0, that's the first time to add mac,
7232                  * set mask for vlan_id 0.
7233                  */
7234                 if (vsi->vlan_num == 0) {
7235                         i40e_set_vlan_filter(vsi, 0, 1);
7236                         vsi->vlan_num = 1;
7237                 }
7238                 vlan_num = vsi->vlan_num;
7239         } else if ((mac_filter->filter_type == RTE_MAC_PERFECT_MATCH) ||
7240                         (mac_filter->filter_type == RTE_MAC_HASH_MATCH))
7241                 vlan_num = 1;
7242
7243         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7244         if (mv_f == NULL) {
7245                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7246                 return I40E_ERR_NO_MEMORY;
7247         }
7248
7249         for (i = 0; i < vlan_num; i++) {
7250                 mv_f[i].filter_type = mac_filter->filter_type;
7251                 rte_memcpy(&mv_f[i].macaddr, &mac_filter->mac_addr,
7252                                 ETH_ADDR_LEN);
7253         }
7254
7255         if (mac_filter->filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7256                 mac_filter->filter_type == RTE_MACVLAN_HASH_MATCH) {
7257                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num,
7258                                         &mac_filter->mac_addr);
7259                 if (ret != I40E_SUCCESS)
7260                         goto DONE;
7261         }
7262
7263         ret = i40e_add_macvlan_filters(vsi, mv_f, vlan_num);
7264         if (ret != I40E_SUCCESS)
7265                 goto DONE;
7266
7267         /* Add the mac addr into mac list */
7268         f = rte_zmalloc("macv_filter", sizeof(*f), 0);
7269         if (f == NULL) {
7270                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7271                 ret = I40E_ERR_NO_MEMORY;
7272                 goto DONE;
7273         }
7274         rte_memcpy(&f->mac_info.mac_addr, &mac_filter->mac_addr,
7275                         ETH_ADDR_LEN);
7276         f->mac_info.filter_type = mac_filter->filter_type;
7277         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
7278         vsi->mac_num++;
7279
7280         ret = I40E_SUCCESS;
7281 DONE:
7282         rte_free(mv_f);
7283
7284         return ret;
7285 }
7286
7287 int
7288 i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct rte_ether_addr *addr)
7289 {
7290         struct i40e_mac_filter *f;
7291         struct i40e_macvlan_filter *mv_f;
7292         int i, vlan_num;
7293         enum rte_mac_filter_type filter_type;
7294         int ret = I40E_SUCCESS;
7295
7296         /* Can't find it, return an error */
7297         f = i40e_find_mac_filter(vsi, addr);
7298         if (f == NULL)
7299                 return I40E_ERR_PARAM;
7300
7301         vlan_num = vsi->vlan_num;
7302         filter_type = f->mac_info.filter_type;
7303         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7304                 filter_type == RTE_MACVLAN_HASH_MATCH) {
7305                 if (vlan_num == 0) {
7306                         PMD_DRV_LOG(ERR, "VLAN number shouldn't be 0");
7307                         return I40E_ERR_PARAM;
7308                 }
7309         } else if (filter_type == RTE_MAC_PERFECT_MATCH ||
7310                         filter_type == RTE_MAC_HASH_MATCH)
7311                 vlan_num = 1;
7312
7313         mv_f = rte_zmalloc("macvlan_data", vlan_num * sizeof(*mv_f), 0);
7314         if (mv_f == NULL) {
7315                 PMD_DRV_LOG(ERR, "failed to allocate memory");
7316                 return I40E_ERR_NO_MEMORY;
7317         }
7318
7319         for (i = 0; i < vlan_num; i++) {
7320                 mv_f[i].filter_type = filter_type;
7321                 rte_memcpy(&mv_f[i].macaddr, &f->mac_info.mac_addr,
7322                                 ETH_ADDR_LEN);
7323         }
7324         if (filter_type == RTE_MACVLAN_PERFECT_MATCH ||
7325                         filter_type == RTE_MACVLAN_HASH_MATCH) {
7326                 ret = i40e_find_all_vlan_for_mac(vsi, mv_f, vlan_num, addr);
7327                 if (ret != I40E_SUCCESS)
7328                         goto DONE;
7329         }
7330
7331         ret = i40e_remove_macvlan_filters(vsi, mv_f, vlan_num);
7332         if (ret != I40E_SUCCESS)
7333                 goto DONE;
7334
7335         /* Remove the mac addr into mac list */
7336         TAILQ_REMOVE(&vsi->mac_list, f, next);
7337         rte_free(f);
7338         vsi->mac_num--;
7339
7340         ret = I40E_SUCCESS;
7341 DONE:
7342         rte_free(mv_f);
7343         return ret;
7344 }
7345
7346 /* Configure hash enable flags for RSS */
7347 uint64_t
7348 i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags)
7349 {
7350         uint64_t hena = 0;
7351         int i;
7352
7353         if (!flags)
7354                 return hena;
7355
7356         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7357                 if (flags & (1ULL << i))
7358                         hena |= adapter->pctypes_tbl[i];
7359         }
7360
7361         return hena;
7362 }
7363
7364 /* Parse the hash enable flags */
7365 uint64_t
7366 i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags)
7367 {
7368         uint64_t rss_hf = 0;
7369
7370         if (!flags)
7371                 return rss_hf;
7372         int i;
7373
7374         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < I40E_FLOW_TYPE_MAX; i++) {
7375                 if (flags & adapter->pctypes_tbl[i])
7376                         rss_hf |= (1ULL << i);
7377         }
7378         return rss_hf;
7379 }
7380
7381 /* Disable RSS */
7382 static void
7383 i40e_pf_disable_rss(struct i40e_pf *pf)
7384 {
7385         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7386
7387         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
7388         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
7389         I40E_WRITE_FLUSH(hw);
7390 }
7391
7392 int
7393 i40e_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
7394 {
7395         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7396         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7397         uint16_t key_idx = (vsi->type == I40E_VSI_SRIOV) ?
7398                            I40E_VFQF_HKEY_MAX_INDEX :
7399                            I40E_PFQF_HKEY_MAX_INDEX;
7400         int ret = 0;
7401
7402         if (!key || key_len == 0) {
7403                 PMD_DRV_LOG(DEBUG, "No key to be configured");
7404                 return 0;
7405         } else if (key_len != (key_idx + 1) *
7406                 sizeof(uint32_t)) {
7407                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
7408                 return -EINVAL;
7409         }
7410
7411         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7412                 struct i40e_aqc_get_set_rss_key_data *key_dw =
7413                         (struct i40e_aqc_get_set_rss_key_data *)key;
7414
7415                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
7416                 if (ret)
7417                         PMD_INIT_LOG(ERR, "Failed to configure RSS key via AQ");
7418         } else {
7419                 uint32_t *hash_key = (uint32_t *)key;
7420                 uint16_t i;
7421
7422                 if (vsi->type == I40E_VSI_SRIOV) {
7423                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
7424                                 I40E_WRITE_REG(
7425                                         hw,
7426                                         I40E_VFQF_HKEY1(i, vsi->user_param),
7427                                         hash_key[i]);
7428
7429                 } else {
7430                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
7431                                 I40E_WRITE_REG(hw, I40E_PFQF_HKEY(i),
7432                                                hash_key[i]);
7433                 }
7434                 I40E_WRITE_FLUSH(hw);
7435         }
7436
7437         return ret;
7438 }
7439
7440 static int
7441 i40e_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
7442 {
7443         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
7444         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
7445         uint32_t reg;
7446         int ret;
7447
7448         if (!key || !key_len)
7449                 return 0;
7450
7451         if (pf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
7452                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
7453                         (struct i40e_aqc_get_set_rss_key_data *)key);
7454                 if (ret) {
7455                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
7456                         return ret;
7457                 }
7458         } else {
7459                 uint32_t *key_dw = (uint32_t *)key;
7460                 uint16_t i;
7461
7462                 if (vsi->type == I40E_VSI_SRIOV) {
7463                         for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++) {
7464                                 reg = I40E_VFQF_HKEY1(i, vsi->user_param);
7465                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7466                         }
7467                         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
7468                                    sizeof(uint32_t);
7469                 } else {
7470                         for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++) {
7471                                 reg = I40E_PFQF_HKEY(i);
7472                                 key_dw[i] = i40e_read_rx_ctl(hw, reg);
7473                         }
7474                         *key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
7475                                    sizeof(uint32_t);
7476                 }
7477         }
7478         return 0;
7479 }
7480
7481 static int
7482 i40e_hw_rss_hash_set(struct i40e_pf *pf, struct rte_eth_rss_conf *rss_conf)
7483 {
7484         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7485         uint64_t hena;
7486         int ret;
7487
7488         ret = i40e_set_rss_key(pf->main_vsi, rss_conf->rss_key,
7489                                rss_conf->rss_key_len);
7490         if (ret)
7491                 return ret;
7492
7493         hena = i40e_config_hena(pf->adapter, rss_conf->rss_hf);
7494         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (uint32_t)hena);
7495         i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (uint32_t)(hena >> 32));
7496         I40E_WRITE_FLUSH(hw);
7497
7498         return 0;
7499 }
7500
7501 static int
7502 i40e_dev_rss_hash_update(struct rte_eth_dev *dev,
7503                          struct rte_eth_rss_conf *rss_conf)
7504 {
7505         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7506         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7507         uint64_t rss_hf = rss_conf->rss_hf & pf->adapter->flow_types_mask;
7508         uint64_t hena;
7509
7510         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7511         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7512
7513         if (!(hena & pf->adapter->pctypes_mask)) { /* RSS disabled */
7514                 if (rss_hf != 0) /* Enable RSS */
7515                         return -EINVAL;
7516                 return 0; /* Nothing to do */
7517         }
7518         /* RSS enabled */
7519         if (rss_hf == 0) /* Disable RSS */
7520                 return -EINVAL;
7521
7522         return i40e_hw_rss_hash_set(pf, rss_conf);
7523 }
7524
7525 static int
7526 i40e_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
7527                            struct rte_eth_rss_conf *rss_conf)
7528 {
7529         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
7530         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
7531         uint64_t hena;
7532         int ret;
7533
7534         if (!rss_conf)
7535                 return -EINVAL;
7536
7537         ret = i40e_get_rss_key(pf->main_vsi, rss_conf->rss_key,
7538                          &rss_conf->rss_key_len);
7539         if (ret)
7540                 return ret;
7541
7542         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0));
7543         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1))) << 32;
7544         rss_conf->rss_hf = i40e_parse_hena(pf->adapter, hena);
7545
7546         return 0;
7547 }
7548
7549 static int
7550 i40e_dev_get_filter_type(uint16_t filter_type, uint16_t *flag)
7551 {
7552         switch (filter_type) {
7553         case RTE_TUNNEL_FILTER_IMAC_IVLAN:
7554                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
7555                 break;
7556         case RTE_TUNNEL_FILTER_IMAC_IVLAN_TENID:
7557                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
7558                 break;
7559         case RTE_TUNNEL_FILTER_IMAC_TENID:
7560                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID;
7561                 break;
7562         case RTE_TUNNEL_FILTER_OMAC_TENID_IMAC:
7563                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC;
7564                 break;
7565         case ETH_TUNNEL_FILTER_IMAC:
7566                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7567                 break;
7568         case ETH_TUNNEL_FILTER_OIP:
7569                 *flag = I40E_AQC_ADD_CLOUD_FILTER_OIP;
7570                 break;
7571         case ETH_TUNNEL_FILTER_IIP:
7572                 *flag = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7573                 break;
7574         default:
7575                 PMD_DRV_LOG(ERR, "invalid tunnel filter type");
7576                 return -EINVAL;
7577         }
7578
7579         return 0;
7580 }
7581
7582 /* Convert tunnel filter structure */
7583 static int
7584 i40e_tunnel_filter_convert(
7585         struct i40e_aqc_cloud_filters_element_bb *cld_filter,
7586         struct i40e_tunnel_filter *tunnel_filter)
7587 {
7588         rte_ether_addr_copy((struct rte_ether_addr *)
7589                         &cld_filter->element.outer_mac,
7590                 (struct rte_ether_addr *)&tunnel_filter->input.outer_mac);
7591         rte_ether_addr_copy((struct rte_ether_addr *)
7592                         &cld_filter->element.inner_mac,
7593                 (struct rte_ether_addr *)&tunnel_filter->input.inner_mac);
7594         tunnel_filter->input.inner_vlan = cld_filter->element.inner_vlan;
7595         if ((rte_le_to_cpu_16(cld_filter->element.flags) &
7596              I40E_AQC_ADD_CLOUD_FLAGS_IPV6) ==
7597             I40E_AQC_ADD_CLOUD_FLAGS_IPV6)
7598                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV6;
7599         else
7600                 tunnel_filter->input.ip_type = I40E_TUNNEL_IPTYPE_IPV4;
7601         tunnel_filter->input.flags = cld_filter->element.flags;
7602         tunnel_filter->input.tenant_id = cld_filter->element.tenant_id;
7603         tunnel_filter->queue = cld_filter->element.queue_number;
7604         rte_memcpy(tunnel_filter->input.general_fields,
7605                    cld_filter->general_fields,
7606                    sizeof(cld_filter->general_fields));
7607
7608         return 0;
7609 }
7610
7611 /* Check if there exists the tunnel filter */
7612 struct i40e_tunnel_filter *
7613 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
7614                              const struct i40e_tunnel_filter_input *input)
7615 {
7616         int ret;
7617
7618         ret = rte_hash_lookup(tunnel_rule->hash_table, (const void *)input);
7619         if (ret < 0)
7620                 return NULL;
7621
7622         return tunnel_rule->hash_map[ret];
7623 }
7624
7625 /* Add a tunnel filter into the SW list */
7626 static int
7627 i40e_sw_tunnel_filter_insert(struct i40e_pf *pf,
7628                              struct i40e_tunnel_filter *tunnel_filter)
7629 {
7630         struct i40e_tunnel_rule *rule = &pf->tunnel;
7631         int ret;
7632
7633         ret = rte_hash_add_key(rule->hash_table, &tunnel_filter->input);
7634         if (ret < 0) {
7635                 PMD_DRV_LOG(ERR,
7636                             "Failed to insert tunnel filter to hash table %d!",
7637                             ret);
7638                 return ret;
7639         }
7640         rule->hash_map[ret] = tunnel_filter;
7641
7642         TAILQ_INSERT_TAIL(&rule->tunnel_list, tunnel_filter, rules);
7643
7644         return 0;
7645 }
7646
7647 /* Delete a tunnel filter from the SW list */
7648 int
7649 i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
7650                           struct i40e_tunnel_filter_input *input)
7651 {
7652         struct i40e_tunnel_rule *rule = &pf->tunnel;
7653         struct i40e_tunnel_filter *tunnel_filter;
7654         int ret;
7655
7656         ret = rte_hash_del_key(rule->hash_table, input);
7657         if (ret < 0) {
7658                 PMD_DRV_LOG(ERR,
7659                             "Failed to delete tunnel filter to hash table %d!",
7660                             ret);
7661                 return ret;
7662         }
7663         tunnel_filter = rule->hash_map[ret];
7664         rule->hash_map[ret] = NULL;
7665
7666         TAILQ_REMOVE(&rule->tunnel_list, tunnel_filter, rules);
7667         rte_free(tunnel_filter);
7668
7669         return 0;
7670 }
7671
7672 int
7673 i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
7674                         struct rte_eth_tunnel_filter_conf *tunnel_filter,
7675                         uint8_t add)
7676 {
7677         uint16_t ip_type;
7678         uint32_t ipv4_addr, ipv4_addr_le;
7679         uint8_t i, tun_type = 0;
7680         /* internal varialbe to convert ipv6 byte order */
7681         uint32_t convert_ipv6[4];
7682         int val, ret = 0;
7683         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7684         struct i40e_vsi *vsi = pf->main_vsi;
7685         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
7686         struct i40e_aqc_cloud_filters_element_bb *pfilter;
7687         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
7688         struct i40e_tunnel_filter *tunnel, *node;
7689         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
7690
7691         cld_filter = rte_zmalloc("tunnel_filter",
7692                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
7693         0);
7694
7695         if (NULL == cld_filter) {
7696                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7697                 return -ENOMEM;
7698         }
7699         pfilter = cld_filter;
7700
7701         rte_ether_addr_copy(&tunnel_filter->outer_mac,
7702                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
7703         rte_ether_addr_copy(&tunnel_filter->inner_mac,
7704                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
7705
7706         pfilter->element.inner_vlan =
7707                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
7708         if (tunnel_filter->ip_type == RTE_TUNNEL_IPTYPE_IPV4) {
7709                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
7710                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
7711                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
7712                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
7713                                 &ipv4_addr_le,
7714                                 sizeof(pfilter->element.ipaddr.v4.data));
7715         } else {
7716                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
7717                 for (i = 0; i < 4; i++) {
7718                         convert_ipv6[i] =
7719                         rte_cpu_to_le_32(rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv6_addr[i]));
7720                 }
7721                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
7722                            &convert_ipv6,
7723                            sizeof(pfilter->element.ipaddr.v6.data));
7724         }
7725
7726         /* check tunneled type */
7727         switch (tunnel_filter->tunnel_type) {
7728         case RTE_TUNNEL_TYPE_VXLAN:
7729                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
7730                 break;
7731         case RTE_TUNNEL_TYPE_NVGRE:
7732                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
7733                 break;
7734         case RTE_TUNNEL_TYPE_IP_IN_GRE:
7735                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
7736                 break;
7737         case RTE_TUNNEL_TYPE_VXLAN_GPE:
7738                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE;
7739                 break;
7740         default:
7741                 /* Other tunnel types is not supported. */
7742                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
7743                 rte_free(cld_filter);
7744                 return -EINVAL;
7745         }
7746
7747         val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
7748                                        &pfilter->element.flags);
7749         if (val < 0) {
7750                 rte_free(cld_filter);
7751                 return -EINVAL;
7752         }
7753
7754         pfilter->element.flags |= rte_cpu_to_le_16(
7755                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
7756                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
7757         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
7758         pfilter->element.queue_number =
7759                 rte_cpu_to_le_16(tunnel_filter->queue_id);
7760
7761         /* Check if there is the filter in SW list */
7762         memset(&check_filter, 0, sizeof(check_filter));
7763         i40e_tunnel_filter_convert(cld_filter, &check_filter);
7764         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
7765         if (add && node) {
7766                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
7767                 rte_free(cld_filter);
7768                 return -EINVAL;
7769         }
7770
7771         if (!add && !node) {
7772                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
7773                 rte_free(cld_filter);
7774                 return -EINVAL;
7775         }
7776
7777         if (add) {
7778                 ret = i40e_aq_add_cloud_filters(hw,
7779                                         vsi->seid, &cld_filter->element, 1);
7780                 if (ret < 0) {
7781                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
7782                         rte_free(cld_filter);
7783                         return -ENOTSUP;
7784                 }
7785                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
7786                 if (tunnel == NULL) {
7787                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
7788                         rte_free(cld_filter);
7789                         return -ENOMEM;
7790                 }
7791
7792                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
7793                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
7794                 if (ret < 0)
7795                         rte_free(tunnel);
7796         } else {
7797                 ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
7798                                                    &cld_filter->element, 1);
7799                 if (ret < 0) {
7800                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
7801                         rte_free(cld_filter);
7802                         return -ENOTSUP;
7803                 }
7804                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
7805         }
7806
7807         rte_free(cld_filter);
7808         return ret;
7809 }
7810
7811 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0 0x48
7812 #define I40E_TR_VXLAN_GRE_KEY_MASK              0x4
7813 #define I40E_TR_GENEVE_KEY_MASK                 0x8
7814 #define I40E_TR_GENERIC_UDP_TUNNEL_MASK         0x40
7815 #define I40E_TR_GRE_KEY_MASK                    0x400
7816 #define I40E_TR_GRE_KEY_WITH_XSUM_MASK          0x800
7817 #define I40E_TR_GRE_NO_KEY_MASK                 0x8000
7818
7819 static enum
7820 i40e_status_code i40e_replace_mpls_l1_filter(struct i40e_pf *pf)
7821 {
7822         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7823         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7824         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7825         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7826         enum i40e_status_code status = I40E_SUCCESS;
7827
7828         if (pf->support_multi_driver) {
7829                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7830                 return I40E_NOT_SUPPORTED;
7831         }
7832
7833         memset(&filter_replace, 0,
7834                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7835         memset(&filter_replace_buf, 0,
7836                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7837
7838         /* create L1 filter */
7839         filter_replace.old_filter_type =
7840                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7841         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X11;
7842         filter_replace.tr_bit = 0;
7843
7844         /* Prepare the buffer, 3 entries */
7845         filter_replace_buf.data[0] =
7846                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7847         filter_replace_buf.data[0] |=
7848                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7849         filter_replace_buf.data[2] = 0xFF;
7850         filter_replace_buf.data[3] = 0xFF;
7851         filter_replace_buf.data[4] =
7852                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7853         filter_replace_buf.data[4] |=
7854                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7855         filter_replace_buf.data[7] = 0xF0;
7856         filter_replace_buf.data[8]
7857                 = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_TR_WORD0;
7858         filter_replace_buf.data[8] |=
7859                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7860         filter_replace_buf.data[10] = I40E_TR_VXLAN_GRE_KEY_MASK |
7861                 I40E_TR_GENEVE_KEY_MASK |
7862                 I40E_TR_GENERIC_UDP_TUNNEL_MASK;
7863         filter_replace_buf.data[11] = (I40E_TR_GRE_KEY_MASK |
7864                 I40E_TR_GRE_KEY_WITH_XSUM_MASK |
7865                 I40E_TR_GRE_NO_KEY_MASK) >> 8;
7866
7867         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7868                                                &filter_replace_buf);
7869         if (!status && (filter_replace.old_filter_type !=
7870                         filter_replace.new_filter_type))
7871                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
7872                             " original: 0x%x, new: 0x%x",
7873                             dev->device->name,
7874                             filter_replace.old_filter_type,
7875                             filter_replace.new_filter_type);
7876
7877         return status;
7878 }
7879
7880 static enum
7881 i40e_status_code i40e_replace_mpls_cloud_filter(struct i40e_pf *pf)
7882 {
7883         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7884         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7885         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7886         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7887         enum i40e_status_code status = I40E_SUCCESS;
7888
7889         if (pf->support_multi_driver) {
7890                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
7891                 return I40E_NOT_SUPPORTED;
7892         }
7893
7894         /* For MPLSoUDP */
7895         memset(&filter_replace, 0,
7896                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7897         memset(&filter_replace_buf, 0,
7898                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7899         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7900                 I40E_AQC_MIRROR_CLOUD_FILTER;
7901         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IIP;
7902         filter_replace.new_filter_type =
7903                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
7904         /* Prepare the buffer, 2 entries */
7905         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7906         filter_replace_buf.data[0] |=
7907                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7908         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7909         filter_replace_buf.data[4] |=
7910                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7911         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7912                                                &filter_replace_buf);
7913         if (status < 0)
7914                 return status;
7915         if (filter_replace.old_filter_type !=
7916             filter_replace.new_filter_type)
7917                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7918                             " original: 0x%x, new: 0x%x",
7919                             dev->device->name,
7920                             filter_replace.old_filter_type,
7921                             filter_replace.new_filter_type);
7922
7923         /* For MPLSoGRE */
7924         memset(&filter_replace, 0,
7925                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7926         memset(&filter_replace_buf, 0,
7927                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7928
7929         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER |
7930                 I40E_AQC_MIRROR_CLOUD_FILTER;
7931         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC;
7932         filter_replace.new_filter_type =
7933                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
7934         /* Prepare the buffer, 2 entries */
7935         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
7936         filter_replace_buf.data[0] |=
7937                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7938         filter_replace_buf.data[4] = I40E_AQC_ADD_L1_FILTER_0X11;
7939         filter_replace_buf.data[4] |=
7940                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7941
7942         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7943                                                &filter_replace_buf);
7944         if (!status && (filter_replace.old_filter_type !=
7945                         filter_replace.new_filter_type))
7946                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
7947                             " original: 0x%x, new: 0x%x",
7948                             dev->device->name,
7949                             filter_replace.old_filter_type,
7950                             filter_replace.new_filter_type);
7951
7952         return status;
7953 }
7954
7955 static enum i40e_status_code
7956 i40e_replace_gtp_l1_filter(struct i40e_pf *pf)
7957 {
7958         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
7959         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
7960         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
7961         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
7962         enum i40e_status_code status = I40E_SUCCESS;
7963
7964         if (pf->support_multi_driver) {
7965                 PMD_DRV_LOG(ERR, "Replace l1 filter is not supported.");
7966                 return I40E_NOT_SUPPORTED;
7967         }
7968
7969         /* For GTP-C */
7970         memset(&filter_replace, 0,
7971                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
7972         memset(&filter_replace_buf, 0,
7973                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
7974         /* create L1 filter */
7975         filter_replace.old_filter_type =
7976                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC;
7977         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X12;
7978         filter_replace.tr_bit = I40E_AQC_NEW_TR_22 |
7979                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7980         /* Prepare the buffer, 2 entries */
7981         filter_replace_buf.data[0] =
7982                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
7983         filter_replace_buf.data[0] |=
7984                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7985         filter_replace_buf.data[2] = 0xFF;
7986         filter_replace_buf.data[3] = 0xFF;
7987         filter_replace_buf.data[4] =
7988                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
7989         filter_replace_buf.data[4] |=
7990                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
7991         filter_replace_buf.data[6] = 0xFF;
7992         filter_replace_buf.data[7] = 0xFF;
7993         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
7994                                                &filter_replace_buf);
7995         if (status < 0)
7996                 return status;
7997         if (filter_replace.old_filter_type !=
7998             filter_replace.new_filter_type)
7999                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8000                             " original: 0x%x, new: 0x%x",
8001                             dev->device->name,
8002                             filter_replace.old_filter_type,
8003                             filter_replace.new_filter_type);
8004
8005         /* for GTP-U */
8006         memset(&filter_replace, 0,
8007                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8008         memset(&filter_replace_buf, 0,
8009                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8010         /* create L1 filter */
8011         filter_replace.old_filter_type =
8012                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY;
8013         filter_replace.new_filter_type = I40E_AQC_ADD_L1_FILTER_0X13;
8014         filter_replace.tr_bit = I40E_AQC_NEW_TR_21 |
8015                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8016         /* Prepare the buffer, 2 entries */
8017         filter_replace_buf.data[0] =
8018                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0;
8019         filter_replace_buf.data[0] |=
8020                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8021         filter_replace_buf.data[2] = 0xFF;
8022         filter_replace_buf.data[3] = 0xFF;
8023         filter_replace_buf.data[4] =
8024                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1;
8025         filter_replace_buf.data[4] |=
8026                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8027         filter_replace_buf.data[6] = 0xFF;
8028         filter_replace_buf.data[7] = 0xFF;
8029
8030         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8031                                                &filter_replace_buf);
8032         if (!status && (filter_replace.old_filter_type !=
8033                         filter_replace.new_filter_type))
8034                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
8035                             " original: 0x%x, new: 0x%x",
8036                             dev->device->name,
8037                             filter_replace.old_filter_type,
8038                             filter_replace.new_filter_type);
8039
8040         return status;
8041 }
8042
8043 static enum
8044 i40e_status_code i40e_replace_gtp_cloud_filter(struct i40e_pf *pf)
8045 {
8046         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
8047         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
8048         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8049         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
8050         enum i40e_status_code status = I40E_SUCCESS;
8051
8052         if (pf->support_multi_driver) {
8053                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
8054                 return I40E_NOT_SUPPORTED;
8055         }
8056
8057         /* for GTP-C */
8058         memset(&filter_replace, 0,
8059                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8060         memset(&filter_replace_buf, 0,
8061                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8062         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8063         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN;
8064         filter_replace.new_filter_type =
8065                 I40E_AQC_ADD_CLOUD_FILTER_0X11;
8066         /* Prepare the buffer, 2 entries */
8067         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X12;
8068         filter_replace_buf.data[0] |=
8069                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8070         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8071         filter_replace_buf.data[4] |=
8072                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8073         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8074                                                &filter_replace_buf);
8075         if (status < 0)
8076                 return status;
8077         if (filter_replace.old_filter_type !=
8078             filter_replace.new_filter_type)
8079                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8080                             " original: 0x%x, new: 0x%x",
8081                             dev->device->name,
8082                             filter_replace.old_filter_type,
8083                             filter_replace.new_filter_type);
8084
8085         /* for GTP-U */
8086         memset(&filter_replace, 0,
8087                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
8088         memset(&filter_replace_buf, 0,
8089                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
8090         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
8091         filter_replace.old_filter_type =
8092                 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID;
8093         filter_replace.new_filter_type =
8094                 I40E_AQC_ADD_CLOUD_FILTER_0X12;
8095         /* Prepare the buffer, 2 entries */
8096         filter_replace_buf.data[0] = I40E_AQC_ADD_L1_FILTER_0X13;
8097         filter_replace_buf.data[0] |=
8098                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8099         filter_replace_buf.data[4] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
8100         filter_replace_buf.data[4] |=
8101                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
8102
8103         status = i40e_aq_replace_cloud_filters(hw, &filter_replace,
8104                                                &filter_replace_buf);
8105         if (!status && (filter_replace.old_filter_type !=
8106                         filter_replace.new_filter_type))
8107                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
8108                             " original: 0x%x, new: 0x%x",
8109                             dev->device->name,
8110                             filter_replace.old_filter_type,
8111                             filter_replace.new_filter_type);
8112
8113         return status;
8114 }
8115
8116 int
8117 i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
8118                       struct i40e_tunnel_filter_conf *tunnel_filter,
8119                       uint8_t add)
8120 {
8121         uint16_t ip_type;
8122         uint32_t ipv4_addr, ipv4_addr_le;
8123         uint8_t i, tun_type = 0;
8124         /* internal variable to convert ipv6 byte order */
8125         uint32_t convert_ipv6[4];
8126         int val, ret = 0;
8127         struct i40e_pf_vf *vf = NULL;
8128         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8129         struct i40e_vsi *vsi;
8130         struct i40e_aqc_cloud_filters_element_bb *cld_filter;
8131         struct i40e_aqc_cloud_filters_element_bb *pfilter;
8132         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
8133         struct i40e_tunnel_filter *tunnel, *node;
8134         struct i40e_tunnel_filter check_filter; /* Check if filter exists */
8135         uint32_t teid_le;
8136         bool big_buffer = 0;
8137
8138         cld_filter = rte_zmalloc("tunnel_filter",
8139                          sizeof(struct i40e_aqc_add_rm_cloud_filt_elem_ext),
8140                          0);
8141
8142         if (cld_filter == NULL) {
8143                 PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8144                 return -ENOMEM;
8145         }
8146         pfilter = cld_filter;
8147
8148         rte_ether_addr_copy(&tunnel_filter->outer_mac,
8149                         (struct rte_ether_addr *)&pfilter->element.outer_mac);
8150         rte_ether_addr_copy(&tunnel_filter->inner_mac,
8151                         (struct rte_ether_addr *)&pfilter->element.inner_mac);
8152
8153         pfilter->element.inner_vlan =
8154                 rte_cpu_to_le_16(tunnel_filter->inner_vlan);
8155         if (tunnel_filter->ip_type == I40E_TUNNEL_IPTYPE_IPV4) {
8156                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV4;
8157                 ipv4_addr = rte_be_to_cpu_32(tunnel_filter->ip_addr.ipv4_addr);
8158                 ipv4_addr_le = rte_cpu_to_le_32(ipv4_addr);
8159                 rte_memcpy(&pfilter->element.ipaddr.v4.data,
8160                                 &ipv4_addr_le,
8161                                 sizeof(pfilter->element.ipaddr.v4.data));
8162         } else {
8163                 ip_type = I40E_AQC_ADD_CLOUD_FLAGS_IPV6;
8164                 for (i = 0; i < 4; i++) {
8165                         convert_ipv6[i] =
8166                         rte_cpu_to_le_32(rte_be_to_cpu_32(
8167                                          tunnel_filter->ip_addr.ipv6_addr[i]));
8168                 }
8169                 rte_memcpy(&pfilter->element.ipaddr.v6.data,
8170                            &convert_ipv6,
8171                            sizeof(pfilter->element.ipaddr.v6.data));
8172         }
8173
8174         /* check tunneled type */
8175         switch (tunnel_filter->tunnel_type) {
8176         case I40E_TUNNEL_TYPE_VXLAN:
8177                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_VXLAN;
8178                 break;
8179         case I40E_TUNNEL_TYPE_NVGRE:
8180                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC;
8181                 break;
8182         case I40E_TUNNEL_TYPE_IP_IN_GRE:
8183                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_IP;
8184                 break;
8185         case I40E_TUNNEL_TYPE_MPLSoUDP:
8186                 if (!pf->mpls_replace_flag) {
8187                         i40e_replace_mpls_l1_filter(pf);
8188                         i40e_replace_mpls_cloud_filter(pf);
8189                         pf->mpls_replace_flag = 1;
8190                 }
8191                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8192                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8193                         teid_le >> 4;
8194                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8195                         (teid_le & 0xF) << 12;
8196                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8197                         0x40;
8198                 big_buffer = 1;
8199                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP;
8200                 break;
8201         case I40E_TUNNEL_TYPE_MPLSoGRE:
8202                 if (!pf->mpls_replace_flag) {
8203                         i40e_replace_mpls_l1_filter(pf);
8204                         i40e_replace_mpls_cloud_filter(pf);
8205                         pf->mpls_replace_flag = 1;
8206                 }
8207                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8208                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0] =
8209                         teid_le >> 4;
8210                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1] =
8211                         (teid_le & 0xF) << 12;
8212                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2] =
8213                         0x0;
8214                 big_buffer = 1;
8215                 tun_type = I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE;
8216                 break;
8217         case I40E_TUNNEL_TYPE_GTPC:
8218                 if (!pf->gtp_replace_flag) {
8219                         i40e_replace_gtp_l1_filter(pf);
8220                         i40e_replace_gtp_cloud_filter(pf);
8221                         pf->gtp_replace_flag = 1;
8222                 }
8223                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8224                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0] =
8225                         (teid_le >> 16) & 0xFFFF;
8226                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1] =
8227                         teid_le & 0xFFFF;
8228                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2] =
8229                         0x0;
8230                 big_buffer = 1;
8231                 break;
8232         case I40E_TUNNEL_TYPE_GTPU:
8233                 if (!pf->gtp_replace_flag) {
8234                         i40e_replace_gtp_l1_filter(pf);
8235                         i40e_replace_gtp_cloud_filter(pf);
8236                         pf->gtp_replace_flag = 1;
8237                 }
8238                 teid_le = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8239                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0] =
8240                         (teid_le >> 16) & 0xFFFF;
8241                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1] =
8242                         teid_le & 0xFFFF;
8243                 pfilter->general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2] =
8244                         0x0;
8245                 big_buffer = 1;
8246                 break;
8247         case I40E_TUNNEL_TYPE_QINQ:
8248                 if (!pf->qinq_replace_flag) {
8249                         ret = i40e_cloud_filter_qinq_create(pf);
8250                         if (ret < 0)
8251                                 PMD_DRV_LOG(DEBUG,
8252                                             "QinQ tunnel filter already created.");
8253                         pf->qinq_replace_flag = 1;
8254                 }
8255                 /*      Add in the General fields the values of
8256                  *      the Outer and Inner VLAN
8257                  *      Big Buffer should be set, see changes in
8258                  *      i40e_aq_add_cloud_filters
8259                  */
8260                 pfilter->general_fields[0] = tunnel_filter->inner_vlan;
8261                 pfilter->general_fields[1] = tunnel_filter->outer_vlan;
8262                 big_buffer = 1;
8263                 break;
8264         default:
8265                 /* Other tunnel types is not supported. */
8266                 PMD_DRV_LOG(ERR, "tunnel type is not supported.");
8267                 rte_free(cld_filter);
8268                 return -EINVAL;
8269         }
8270
8271         if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoUDP)
8272                 pfilter->element.flags =
8273                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8274         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_MPLSoGRE)
8275                 pfilter->element.flags =
8276                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8277         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPC)
8278                 pfilter->element.flags =
8279                         I40E_AQC_ADD_CLOUD_FILTER_0X11;
8280         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_GTPU)
8281                 pfilter->element.flags =
8282                         I40E_AQC_ADD_CLOUD_FILTER_0X12;
8283         else if (tunnel_filter->tunnel_type == I40E_TUNNEL_TYPE_QINQ)
8284                 pfilter->element.flags |=
8285                         I40E_AQC_ADD_CLOUD_FILTER_0X10;
8286         else {
8287                 val = i40e_dev_get_filter_type(tunnel_filter->filter_type,
8288                                                 &pfilter->element.flags);
8289                 if (val < 0) {
8290                         rte_free(cld_filter);
8291                         return -EINVAL;
8292                 }
8293         }
8294
8295         pfilter->element.flags |= rte_cpu_to_le_16(
8296                 I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE |
8297                 ip_type | (tun_type << I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT));
8298         pfilter->element.tenant_id = rte_cpu_to_le_32(tunnel_filter->tenant_id);
8299         pfilter->element.queue_number =
8300                 rte_cpu_to_le_16(tunnel_filter->queue_id);
8301
8302         if (!tunnel_filter->is_to_vf)
8303                 vsi = pf->main_vsi;
8304         else {
8305                 if (tunnel_filter->vf_id >= pf->vf_num) {
8306                         PMD_DRV_LOG(ERR, "Invalid argument.");
8307                         rte_free(cld_filter);
8308                         return -EINVAL;
8309                 }
8310                 vf = &pf->vfs[tunnel_filter->vf_id];
8311                 vsi = vf->vsi;
8312         }
8313
8314         /* Check if there is the filter in SW list */
8315         memset(&check_filter, 0, sizeof(check_filter));
8316         i40e_tunnel_filter_convert(cld_filter, &check_filter);
8317         check_filter.is_to_vf = tunnel_filter->is_to_vf;
8318         check_filter.vf_id = tunnel_filter->vf_id;
8319         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &check_filter.input);
8320         if (add && node) {
8321                 PMD_DRV_LOG(ERR, "Conflict with existing tunnel rules!");
8322                 rte_free(cld_filter);
8323                 return -EINVAL;
8324         }
8325
8326         if (!add && !node) {
8327                 PMD_DRV_LOG(ERR, "There's no corresponding tunnel filter!");
8328                 rte_free(cld_filter);
8329                 return -EINVAL;
8330         }
8331
8332         if (add) {
8333                 if (big_buffer)
8334                         ret = i40e_aq_add_cloud_filters_bb(hw,
8335                                                    vsi->seid, cld_filter, 1);
8336                 else
8337                         ret = i40e_aq_add_cloud_filters(hw,
8338                                         vsi->seid, &cld_filter->element, 1);
8339                 if (ret < 0) {
8340                         PMD_DRV_LOG(ERR, "Failed to add a tunnel filter.");
8341                         rte_free(cld_filter);
8342                         return -ENOTSUP;
8343                 }
8344                 tunnel = rte_zmalloc("tunnel_filter", sizeof(*tunnel), 0);
8345                 if (tunnel == NULL) {
8346                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
8347                         rte_free(cld_filter);
8348                         return -ENOMEM;
8349                 }
8350
8351                 rte_memcpy(tunnel, &check_filter, sizeof(check_filter));
8352                 ret = i40e_sw_tunnel_filter_insert(pf, tunnel);
8353                 if (ret < 0)
8354                         rte_free(tunnel);
8355         } else {
8356                 if (big_buffer)
8357                         ret = i40e_aq_rem_cloud_filters_bb(
8358                                 hw, vsi->seid, cld_filter, 1);
8359                 else
8360                         ret = i40e_aq_rem_cloud_filters(hw, vsi->seid,
8361                                                 &cld_filter->element, 1);
8362                 if (ret < 0) {
8363                         PMD_DRV_LOG(ERR, "Failed to delete a tunnel filter.");
8364                         rte_free(cld_filter);
8365                         return -ENOTSUP;
8366                 }
8367                 ret = i40e_sw_tunnel_filter_del(pf, &node->input);
8368         }
8369
8370         rte_free(cld_filter);
8371         return ret;
8372 }
8373
8374 static int
8375 i40e_get_vxlan_port_idx(struct i40e_pf *pf, uint16_t port)
8376 {
8377         uint8_t i;
8378
8379         for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
8380                 if (pf->vxlan_ports[i] == port)
8381                         return i;
8382         }
8383
8384         return -1;
8385 }
8386
8387 static int
8388 i40e_add_vxlan_port(struct i40e_pf *pf, uint16_t port, int udp_type)
8389 {
8390         int  idx, ret;
8391         uint8_t filter_idx;
8392         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8393
8394         idx = i40e_get_vxlan_port_idx(pf, port);
8395
8396         /* Check if port already exists */
8397         if (idx >= 0) {
8398                 PMD_DRV_LOG(ERR, "Port %d already offloaded", port);
8399                 return -EINVAL;
8400         }
8401
8402         /* Now check if there is space to add the new port */
8403         idx = i40e_get_vxlan_port_idx(pf, 0);
8404         if (idx < 0) {
8405                 PMD_DRV_LOG(ERR,
8406                         "Maximum number of UDP ports reached, not adding port %d",
8407                         port);
8408                 return -ENOSPC;
8409         }
8410
8411         ret =  i40e_aq_add_udp_tunnel(hw, port, udp_type,
8412                                         &filter_idx, NULL);
8413         if (ret < 0) {
8414                 PMD_DRV_LOG(ERR, "Failed to add VXLAN UDP port %d", port);
8415                 return -1;
8416         }
8417
8418         PMD_DRV_LOG(INFO, "Added port %d with AQ command with index %d",
8419                          port,  filter_idx);
8420
8421         /* New port: add it and mark its index in the bitmap */
8422         pf->vxlan_ports[idx] = port;
8423         pf->vxlan_bitmap |= (1 << idx);
8424
8425         if (!(pf->flags & I40E_FLAG_VXLAN))
8426                 pf->flags |= I40E_FLAG_VXLAN;
8427
8428         return 0;
8429 }
8430
8431 static int
8432 i40e_del_vxlan_port(struct i40e_pf *pf, uint16_t port)
8433 {
8434         int idx;
8435         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8436
8437         if (!(pf->flags & I40E_FLAG_VXLAN)) {
8438                 PMD_DRV_LOG(ERR, "VXLAN UDP port was not configured.");
8439                 return -EINVAL;
8440         }
8441
8442         idx = i40e_get_vxlan_port_idx(pf, port);
8443
8444         if (idx < 0) {
8445                 PMD_DRV_LOG(ERR, "Port %d doesn't exist", port);
8446                 return -EINVAL;
8447         }
8448
8449         if (i40e_aq_del_udp_tunnel(hw, idx, NULL) < 0) {
8450                 PMD_DRV_LOG(ERR, "Failed to delete VXLAN UDP port %d", port);
8451                 return -1;
8452         }
8453
8454         PMD_DRV_LOG(INFO, "Deleted port %d with AQ command with index %d",
8455                         port, idx);
8456
8457         pf->vxlan_ports[idx] = 0;
8458         pf->vxlan_bitmap &= ~(1 << idx);
8459
8460         if (!pf->vxlan_bitmap)
8461                 pf->flags &= ~I40E_FLAG_VXLAN;
8462
8463         return 0;
8464 }
8465
8466 /* Add UDP tunneling port */
8467 static int
8468 i40e_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
8469                              struct rte_eth_udp_tunnel *udp_tunnel)
8470 {
8471         int ret = 0;
8472         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8473
8474         if (udp_tunnel == NULL)
8475                 return -EINVAL;
8476
8477         switch (udp_tunnel->prot_type) {
8478         case RTE_TUNNEL_TYPE_VXLAN:
8479                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8480                                           I40E_AQC_TUNNEL_TYPE_VXLAN);
8481                 break;
8482         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8483                 ret = i40e_add_vxlan_port(pf, udp_tunnel->udp_port,
8484                                           I40E_AQC_TUNNEL_TYPE_VXLAN_GPE);
8485                 break;
8486         case RTE_TUNNEL_TYPE_GENEVE:
8487         case RTE_TUNNEL_TYPE_TEREDO:
8488                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8489                 ret = -1;
8490                 break;
8491
8492         default:
8493                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8494                 ret = -1;
8495                 break;
8496         }
8497
8498         return ret;
8499 }
8500
8501 /* Remove UDP tunneling port */
8502 static int
8503 i40e_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
8504                              struct rte_eth_udp_tunnel *udp_tunnel)
8505 {
8506         int ret = 0;
8507         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8508
8509         if (udp_tunnel == NULL)
8510                 return -EINVAL;
8511
8512         switch (udp_tunnel->prot_type) {
8513         case RTE_TUNNEL_TYPE_VXLAN:
8514         case RTE_TUNNEL_TYPE_VXLAN_GPE:
8515                 ret = i40e_del_vxlan_port(pf, udp_tunnel->udp_port);
8516                 break;
8517         case RTE_TUNNEL_TYPE_GENEVE:
8518         case RTE_TUNNEL_TYPE_TEREDO:
8519                 PMD_DRV_LOG(ERR, "Tunnel type is not supported now.");
8520                 ret = -1;
8521                 break;
8522         default:
8523                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
8524                 ret = -1;
8525                 break;
8526         }
8527
8528         return ret;
8529 }
8530
8531 /* Calculate the maximum number of contiguous PF queues that are configured */
8532 static int
8533 i40e_pf_calc_configured_queues_num(struct i40e_pf *pf)
8534 {
8535         struct rte_eth_dev_data *data = pf->dev_data;
8536         int i, num;
8537         struct i40e_rx_queue *rxq;
8538
8539         num = 0;
8540         for (i = 0; i < pf->lan_nb_qps; i++) {
8541                 rxq = data->rx_queues[i];
8542                 if (rxq && rxq->q_set)
8543                         num++;
8544                 else
8545                         break;
8546         }
8547
8548         return num;
8549 }
8550
8551 /* Configure RSS */
8552 static int
8553 i40e_pf_config_rss(struct i40e_pf *pf)
8554 {
8555         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
8556         struct rte_eth_rss_conf rss_conf;
8557         uint32_t i, lut = 0;
8558         uint16_t j, num;
8559
8560         /*
8561          * If both VMDQ and RSS enabled, not all of PF queues are configured.
8562          * It's necessary to calculate the actual PF queues that are configured.
8563          */
8564         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
8565                 num = i40e_pf_calc_configured_queues_num(pf);
8566         else
8567                 num = pf->dev_data->nb_rx_queues;
8568
8569         num = RTE_MIN(num, I40E_MAX_Q_PER_TC);
8570         PMD_INIT_LOG(INFO, "Max of contiguous %u PF queues are configured",
8571                         num);
8572
8573         if (num == 0) {
8574                 PMD_INIT_LOG(ERR, "No PF queues are configured to enable RSS");
8575                 return -ENOTSUP;
8576         }
8577
8578         if (pf->adapter->rss_reta_updated == 0) {
8579                 for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
8580                         if (j == num)
8581                                 j = 0;
8582                         lut = (lut << 8) | (j & ((0x1 <<
8583                                 hw->func_caps.rss_table_entry_width) - 1));
8584                         if ((i & 3) == 3)
8585                                 I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2),
8586                                                rte_bswap32(lut));
8587                 }
8588         }
8589
8590         rss_conf = pf->dev_data->dev_conf.rx_adv_conf.rss_conf;
8591         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
8592                 i40e_pf_disable_rss(pf);
8593                 return 0;
8594         }
8595         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
8596                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
8597                 /* Random default keys */
8598                 static uint32_t rss_key_default[] = {0x6b793944,
8599                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
8600                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
8601                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
8602
8603                 rss_conf.rss_key = (uint8_t *)rss_key_default;
8604                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
8605                                                         sizeof(uint32_t);
8606         }
8607
8608         return i40e_hw_rss_hash_set(pf, &rss_conf);
8609 }
8610
8611 static int
8612 i40e_tunnel_filter_param_check(struct i40e_pf *pf,
8613                                struct rte_eth_tunnel_filter_conf *filter)
8614 {
8615         if (pf == NULL || filter == NULL) {
8616                 PMD_DRV_LOG(ERR, "Invalid parameter");
8617                 return -EINVAL;
8618         }
8619
8620         if (filter->queue_id >= pf->dev_data->nb_rx_queues) {
8621                 PMD_DRV_LOG(ERR, "Invalid queue ID");
8622                 return -EINVAL;
8623         }
8624
8625         if (filter->inner_vlan > RTE_ETHER_MAX_VLAN_ID) {
8626                 PMD_DRV_LOG(ERR, "Invalid inner VLAN ID");
8627                 return -EINVAL;
8628         }
8629
8630         if ((filter->filter_type & ETH_TUNNEL_FILTER_OMAC) &&
8631                 (rte_is_zero_ether_addr(&filter->outer_mac))) {
8632                 PMD_DRV_LOG(ERR, "Cannot add NULL outer MAC address");
8633                 return -EINVAL;
8634         }
8635
8636         if ((filter->filter_type & ETH_TUNNEL_FILTER_IMAC) &&
8637                 (rte_is_zero_ether_addr(&filter->inner_mac))) {
8638                 PMD_DRV_LOG(ERR, "Cannot add NULL inner MAC address");
8639                 return -EINVAL;
8640         }
8641
8642         return 0;
8643 }
8644
8645 #define I40E_GL_PRS_FVBM_MSK_ENA 0x80000000
8646 #define I40E_GL_PRS_FVBM(_i)     (0x00269760 + ((_i) * 4))
8647 static int
8648 i40e_dev_set_gre_key_len(struct i40e_hw *hw, uint8_t len)
8649 {
8650         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8651         uint32_t val, reg;
8652         int ret = -EINVAL;
8653
8654         if (pf->support_multi_driver) {
8655                 PMD_DRV_LOG(ERR, "GRE key length configuration is unsupported");
8656                 return -ENOTSUP;
8657         }
8658
8659         val = I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2));
8660         PMD_DRV_LOG(DEBUG, "Read original GL_PRS_FVBM with 0x%08x", val);
8661
8662         if (len == 3) {
8663                 reg = val | I40E_GL_PRS_FVBM_MSK_ENA;
8664         } else if (len == 4) {
8665                 reg = val & ~I40E_GL_PRS_FVBM_MSK_ENA;
8666         } else {
8667                 PMD_DRV_LOG(ERR, "Unsupported GRE key length of %u", len);
8668                 return ret;
8669         }
8670
8671         if (reg != val) {
8672                 ret = i40e_aq_debug_write_global_register(hw,
8673                                                    I40E_GL_PRS_FVBM(2),
8674                                                    reg, NULL);
8675                 if (ret != 0)
8676                         return ret;
8677                 PMD_DRV_LOG(DEBUG, "Global register 0x%08x is changed "
8678                             "with value 0x%08x",
8679                             I40E_GL_PRS_FVBM(2), reg);
8680         } else {
8681                 ret = 0;
8682         }
8683         PMD_DRV_LOG(DEBUG, "Read modified GL_PRS_FVBM with 0x%08x",
8684                     I40E_READ_REG(hw, I40E_GL_PRS_FVBM(2)));
8685
8686         return ret;
8687 }
8688
8689 static int
8690 i40e_dev_global_config_set(struct i40e_hw *hw, struct rte_eth_global_cfg *cfg)
8691 {
8692         int ret = -EINVAL;
8693
8694         if (!hw || !cfg)
8695                 return -EINVAL;
8696
8697         switch (cfg->cfg_type) {
8698         case RTE_ETH_GLOBAL_CFG_TYPE_GRE_KEY_LEN:
8699                 ret = i40e_dev_set_gre_key_len(hw, cfg->cfg.gre_key_len);
8700                 break;
8701         default:
8702                 PMD_DRV_LOG(ERR, "Unknown config type %u", cfg->cfg_type);
8703                 break;
8704         }
8705
8706         return ret;
8707 }
8708
8709 static int
8710 i40e_filter_ctrl_global_config(struct rte_eth_dev *dev,
8711                                enum rte_filter_op filter_op,
8712                                void *arg)
8713 {
8714         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
8715         int ret = I40E_ERR_PARAM;
8716
8717         switch (filter_op) {
8718         case RTE_ETH_FILTER_SET:
8719                 ret = i40e_dev_global_config_set(hw,
8720                         (struct rte_eth_global_cfg *)arg);
8721                 break;
8722         default:
8723                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8724                 break;
8725         }
8726
8727         return ret;
8728 }
8729
8730 static int
8731 i40e_tunnel_filter_handle(struct rte_eth_dev *dev,
8732                           enum rte_filter_op filter_op,
8733                           void *arg)
8734 {
8735         struct rte_eth_tunnel_filter_conf *filter;
8736         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
8737         int ret = I40E_SUCCESS;
8738
8739         filter = (struct rte_eth_tunnel_filter_conf *)(arg);
8740
8741         if (i40e_tunnel_filter_param_check(pf, filter) < 0)
8742                 return I40E_ERR_PARAM;
8743
8744         switch (filter_op) {
8745         case RTE_ETH_FILTER_NOP:
8746                 if (!(pf->flags & I40E_FLAG_VXLAN))
8747                         ret = I40E_NOT_SUPPORTED;
8748                 break;
8749         case RTE_ETH_FILTER_ADD:
8750                 ret = i40e_dev_tunnel_filter_set(pf, filter, 1);
8751                 break;
8752         case RTE_ETH_FILTER_DELETE:
8753                 ret = i40e_dev_tunnel_filter_set(pf, filter, 0);
8754                 break;
8755         default:
8756                 PMD_DRV_LOG(ERR, "unknown operation %u", filter_op);
8757                 ret = I40E_ERR_PARAM;
8758                 break;
8759         }
8760
8761         return ret;
8762 }
8763
8764 static int
8765 i40e_pf_config_mq_rx(struct i40e_pf *pf)
8766 {
8767         int ret = 0;
8768         enum rte_eth_rx_mq_mode mq_mode = pf->dev_data->dev_conf.rxmode.mq_mode;
8769
8770         /* RSS setup */
8771         if (mq_mode & ETH_MQ_RX_RSS_FLAG)
8772                 ret = i40e_pf_config_rss(pf);
8773         else
8774                 i40e_pf_disable_rss(pf);
8775
8776         return ret;
8777 }
8778
8779 /* Get the symmetric hash enable configurations per port */
8780 static void
8781 i40e_get_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t *enable)
8782 {
8783         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8784
8785         *enable = reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK ? 1 : 0;
8786 }
8787
8788 /* Set the symmetric hash enable configurations per port */
8789 static void
8790 i40e_set_symmetric_hash_enable_per_port(struct i40e_hw *hw, uint8_t enable)
8791 {
8792         uint32_t reg = i40e_read_rx_ctl(hw, I40E_PRTQF_CTL_0);
8793
8794         if (enable > 0) {
8795                 if (reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK) {
8796                         PMD_DRV_LOG(INFO,
8797                                 "Symmetric hash has already been enabled");
8798                         return;
8799                 }
8800                 reg |= I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8801         } else {
8802                 if (!(reg & I40E_PRTQF_CTL_0_HSYM_ENA_MASK)) {
8803                         PMD_DRV_LOG(INFO,
8804                                 "Symmetric hash has already been disabled");
8805                         return;
8806                 }
8807                 reg &= ~I40E_PRTQF_CTL_0_HSYM_ENA_MASK;
8808         }
8809         i40e_write_rx_ctl(hw, I40E_PRTQF_CTL_0, reg);
8810         I40E_WRITE_FLUSH(hw);
8811 }
8812
8813 /*
8814  * Get global configurations of hash function type and symmetric hash enable
8815  * per flow type (pctype). Note that global configuration means it affects all
8816  * the ports on the same NIC.
8817  */
8818 static int
8819 i40e_get_hash_filter_global_config(struct i40e_hw *hw,
8820                                    struct rte_eth_hash_global_conf *g_cfg)
8821 {
8822         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8823         uint32_t reg;
8824         uint16_t i, j;
8825
8826         memset(g_cfg, 0, sizeof(*g_cfg));
8827         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8828         if (reg & I40E_GLQF_CTL_HTOEP_MASK)
8829                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_TOEPLITZ;
8830         else
8831                 g_cfg->hash_func = RTE_ETH_HASH_FUNCTION_SIMPLE_XOR;
8832         PMD_DRV_LOG(DEBUG, "Hash function is %s",
8833                 (reg & I40E_GLQF_CTL_HTOEP_MASK) ? "Toeplitz" : "Simple XOR");
8834
8835         /*
8836          * As i40e supports less than 64 flow types, only first 64 bits need to
8837          * be checked.
8838          */
8839         for (i = 1; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8840                 g_cfg->valid_bit_mask[i] = 0ULL;
8841                 g_cfg->sym_hash_enable_mask[i] = 0ULL;
8842         }
8843
8844         g_cfg->valid_bit_mask[0] = adapter->flow_types_mask;
8845
8846         for (i = RTE_ETH_FLOW_UNKNOWN + 1; i < UINT64_BIT; i++) {
8847                 if (!adapter->pctypes_tbl[i])
8848                         continue;
8849                 for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8850                      j < I40E_FILTER_PCTYPE_MAX; j++) {
8851                         if (adapter->pctypes_tbl[i] & (1ULL << j)) {
8852                                 reg = i40e_read_rx_ctl(hw, I40E_GLQF_HSYM(j));
8853                                 if (reg & I40E_GLQF_HSYM_SYMH_ENA_MASK) {
8854                                         g_cfg->sym_hash_enable_mask[0] |=
8855                                                                 (1ULL << i);
8856                                 }
8857                         }
8858                 }
8859         }
8860
8861         return 0;
8862 }
8863
8864 static int
8865 i40e_hash_global_config_check(const struct i40e_adapter *adapter,
8866                               const struct rte_eth_hash_global_conf *g_cfg)
8867 {
8868         uint32_t i;
8869         uint64_t mask0, i40e_mask = adapter->flow_types_mask;
8870
8871         if (g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_TOEPLITZ &&
8872                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_SIMPLE_XOR &&
8873                 g_cfg->hash_func != RTE_ETH_HASH_FUNCTION_DEFAULT) {
8874                 PMD_DRV_LOG(ERR, "Unsupported hash function type %d",
8875                                                 g_cfg->hash_func);
8876                 return -EINVAL;
8877         }
8878
8879         /*
8880          * As i40e supports less than 64 flow types, only first 64 bits need to
8881          * be checked.
8882          */
8883         mask0 = g_cfg->valid_bit_mask[0];
8884         for (i = 0; i < RTE_SYM_HASH_MASK_ARRAY_SIZE; i++) {
8885                 if (i == 0) {
8886                         /* Check if any unsupported flow type configured */
8887                         if ((mask0 | i40e_mask) ^ i40e_mask)
8888                                 goto mask_err;
8889                 } else {
8890                         if (g_cfg->valid_bit_mask[i])
8891                                 goto mask_err;
8892                 }
8893         }
8894
8895         return 0;
8896
8897 mask_err:
8898         PMD_DRV_LOG(ERR, "i40e unsupported flow type bit(s) configured");
8899
8900         return -EINVAL;
8901 }
8902
8903 /*
8904  * Set global configurations of hash function type and symmetric hash enable
8905  * per flow type (pctype). Note any modifying global configuration will affect
8906  * all the ports on the same NIC.
8907  */
8908 static int
8909 i40e_set_hash_filter_global_config(struct i40e_hw *hw,
8910                                    struct rte_eth_hash_global_conf *g_cfg)
8911 {
8912         struct i40e_adapter *adapter = (struct i40e_adapter *)hw->back;
8913         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
8914         int ret;
8915         uint16_t i, j;
8916         uint32_t reg;
8917         uint64_t mask0 = g_cfg->valid_bit_mask[0] & adapter->flow_types_mask;
8918
8919         if (pf->support_multi_driver) {
8920                 PMD_DRV_LOG(ERR, "Hash global configuration is not supported.");
8921                 return -ENOTSUP;
8922         }
8923
8924         /* Check the input parameters */
8925         ret = i40e_hash_global_config_check(adapter, g_cfg);
8926         if (ret < 0)
8927                 return ret;
8928
8929         /*
8930          * As i40e supports less than 64 flow types, only first 64 bits need to
8931          * be configured.
8932          */
8933         for (i = RTE_ETH_FLOW_UNKNOWN + 1; mask0 && i < UINT64_BIT; i++) {
8934                 if (mask0 & (1UL << i)) {
8935                         reg = (g_cfg->sym_hash_enable_mask[0] & (1ULL << i)) ?
8936                                         I40E_GLQF_HSYM_SYMH_ENA_MASK : 0;
8937
8938                         for (j = I40E_FILTER_PCTYPE_INVALID + 1;
8939                              j < I40E_FILTER_PCTYPE_MAX; j++) {
8940                                 if (adapter->pctypes_tbl[i] & (1ULL << j))
8941                                         i40e_write_global_rx_ctl(hw,
8942                                                           I40E_GLQF_HSYM(j),
8943                                                           reg);
8944                         }
8945                 }
8946         }
8947
8948         reg = i40e_read_rx_ctl(hw, I40E_GLQF_CTL);
8949         if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_TOEPLITZ) {
8950                 /* Toeplitz */
8951                 if (reg & I40E_GLQF_CTL_HTOEP_MASK) {
8952                         PMD_DRV_LOG(DEBUG,
8953                                 "Hash function already set to Toeplitz");
8954                         goto out;
8955                 }
8956                 reg |= I40E_GLQF_CTL_HTOEP_MASK;
8957         } else if (g_cfg->hash_func == RTE_ETH_HASH_FUNCTION_SIMPLE_XOR) {
8958                 /* Simple XOR */
8959                 if (!(reg & I40E_GLQF_CTL_HTOEP_MASK)) {
8960                         PMD_DRV_LOG(DEBUG,
8961                                 "Hash function already set to Simple XOR");
8962                         goto out;
8963                 }
8964                 reg &= ~I40E_GLQF_CTL_HTOEP_MASK;
8965         } else
8966                 /* Use the default, and keep it as it is */
8967                 goto out;
8968
8969         i40e_write_global_rx_ctl(hw, I40E_GLQF_CTL, reg);
8970
8971 out:
8972         I40E_WRITE_FLUSH(hw);
8973
8974         return 0;
8975 }
8976
8977 /**
8978  * Valid input sets for hash and flow director filters per PCTYPE
8979  */
8980 static uint64_t
8981 i40e_get_valid_input_set(enum i40e_filter_pctype pctype,
8982                 enum rte_filter_type filter)
8983 {
8984         uint64_t valid;
8985
8986         static const uint64_t valid_hash_inset_table[] = {
8987                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
8988                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8989                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8990                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_SRC |
8991                         I40E_INSET_IPV4_DST | I40E_INSET_IPV4_TOS |
8992                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
8993                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
8994                         I40E_INSET_FLEX_PAYLOAD,
8995                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
8996                         I40E_INSET_DMAC | I40E_INSET_SMAC |
8997                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
8998                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
8999                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9000                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9001                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9002                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9003                         I40E_INSET_FLEX_PAYLOAD,
9004                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9005                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9006                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9007                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9008                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9009                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9010                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9011                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9012                         I40E_INSET_FLEX_PAYLOAD,
9013                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9014                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9015                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9016                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9017                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9018                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9019                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9020                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9021                         I40E_INSET_FLEX_PAYLOAD,
9022                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9023                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9024                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9025                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9026                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9027                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9028                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9029                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9030                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9031                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9032                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9033                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9034                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9035                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9036                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9037                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9038                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9039                         I40E_INSET_TCP_FLAGS | I40E_INSET_FLEX_PAYLOAD,
9040                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9041                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9042                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9043                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9044                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9045                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9046                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9047                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9048                         I40E_INSET_SCTP_VT | I40E_INSET_FLEX_PAYLOAD,
9049                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9050                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9051                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9052                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV4_TOS |
9053                         I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL |
9054                         I40E_INSET_TUNNEL_DMAC | I40E_INSET_TUNNEL_ID |
9055                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9056                         I40E_INSET_FLEX_PAYLOAD,
9057                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9058                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9059                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9060                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9061                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9062                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_TUNNEL_DMAC |
9063                         I40E_INSET_TUNNEL_ID | I40E_INSET_IPV6_SRC |
9064                         I40E_INSET_IPV6_DST | I40E_INSET_FLEX_PAYLOAD,
9065                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9066                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9067                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9068                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9069                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9070                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9071                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9072                         I40E_INSET_DST_PORT | I40E_INSET_FLEX_PAYLOAD,
9073                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9074                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9075                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9076                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9077                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9078                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9079                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9080                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9081                         I40E_INSET_FLEX_PAYLOAD,
9082                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9083                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9084                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9085                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9086                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9087                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9088                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9089                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9090                         I40E_INSET_FLEX_PAYLOAD,
9091                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9092                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9093                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9094                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9095                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9096                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9097                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9098                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9099                         I40E_INSET_FLEX_PAYLOAD,
9100                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9101                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9102                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9103                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9104                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9105                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9106                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9107                         I40E_INSET_DST_PORT | I40E_INSET_TCP_FLAGS |
9108                         I40E_INSET_FLEX_PAYLOAD,
9109                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9110                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9111                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9112                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9113                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9114                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9115                         I40E_INSET_IPV6_DST | I40E_INSET_SRC_PORT |
9116                         I40E_INSET_DST_PORT | I40E_INSET_SCTP_VT |
9117                         I40E_INSET_FLEX_PAYLOAD,
9118                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9119                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9120                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9121                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_IPV6_TC |
9122                         I40E_INSET_IPV6_FLOW | I40E_INSET_IPV6_NEXT_HDR |
9123                         I40E_INSET_IPV6_HOP_LIMIT | I40E_INSET_IPV6_SRC |
9124                         I40E_INSET_IPV6_DST | I40E_INSET_TUNNEL_ID |
9125                         I40E_INSET_FLEX_PAYLOAD,
9126                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9127                         I40E_INSET_DMAC | I40E_INSET_SMAC |
9128                         I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9129                         I40E_INSET_VLAN_TUNNEL | I40E_INSET_LAST_ETHER_TYPE |
9130                         I40E_INSET_FLEX_PAYLOAD,
9131         };
9132
9133         /**
9134          * Flow director supports only fields defined in
9135          * union rte_eth_fdir_flow.
9136          */
9137         static const uint64_t valid_fdir_inset_table[] = {
9138                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9139                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9140                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9141                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9142                 I40E_INSET_IPV4_TTL,
9143                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9144                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9145                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9146                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9147                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9148                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9149                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9150                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9151                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9152                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9153                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9154                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9155                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9156                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9157                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9158                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9159                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9160                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9161                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9162                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9163                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9164                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9165                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9166                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9167                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9168                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9169                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9170                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9171                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_TTL |
9172                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9173                 I40E_INSET_SCTP_VT,
9174                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9175                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9176                 I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9177                 I40E_INSET_IPV4_TOS | I40E_INSET_IPV4_PROTO |
9178                 I40E_INSET_IPV4_TTL,
9179                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9180                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9181                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9182                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9183                 I40E_INSET_IPV6_HOP_LIMIT,
9184                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9185                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9186                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9187                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9188                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9189                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9190                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9191                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9192                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9193                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9194                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9195                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9196                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9197                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9198                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9199                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9200                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9201                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9202                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9203                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9204                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9205                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9206                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9207                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9208                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9209                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9210                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9211                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9212                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_HOP_LIMIT |
9213                 I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9214                 I40E_INSET_SCTP_VT,
9215                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9216                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9217                 I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9218                 I40E_INSET_IPV6_TC | I40E_INSET_IPV6_NEXT_HDR |
9219                 I40E_INSET_IPV6_HOP_LIMIT,
9220                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9221                 I40E_INSET_VLAN_OUTER | I40E_INSET_VLAN_INNER |
9222                 I40E_INSET_LAST_ETHER_TYPE,
9223         };
9224
9225         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9226                 return 0;
9227         if (filter == RTE_ETH_FILTER_HASH)
9228                 valid = valid_hash_inset_table[pctype];
9229         else
9230                 valid = valid_fdir_inset_table[pctype];
9231
9232         return valid;
9233 }
9234
9235 /**
9236  * Validate if the input set is allowed for a specific PCTYPE
9237  */
9238 int
9239 i40e_validate_input_set(enum i40e_filter_pctype pctype,
9240                 enum rte_filter_type filter, uint64_t inset)
9241 {
9242         uint64_t valid;
9243
9244         valid = i40e_get_valid_input_set(pctype, filter);
9245         if (inset & (~valid))
9246                 return -EINVAL;
9247
9248         return 0;
9249 }
9250
9251 /* default input set fields combination per pctype */
9252 uint64_t
9253 i40e_get_default_input_set(uint16_t pctype)
9254 {
9255         static const uint64_t default_inset_table[] = {
9256                 [I40E_FILTER_PCTYPE_FRAG_IPV4] =
9257                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9258                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] =
9259                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9260                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9261                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP] =
9262                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9263                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9264                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP] =
9265                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9266                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9267                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] =
9268                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9269                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9270                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK] =
9271                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9272                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9273                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] =
9274                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST |
9275                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9276                         I40E_INSET_SCTP_VT,
9277                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] =
9278                         I40E_INSET_IPV4_SRC | I40E_INSET_IPV4_DST,
9279                 [I40E_FILTER_PCTYPE_FRAG_IPV6] =
9280                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9281                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] =
9282                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9283                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9284                 [I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP] =
9285                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9286                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9287                 [I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP] =
9288                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9289                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9290                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] =
9291                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9292                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9293                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK] =
9294                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9295                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT,
9296                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] =
9297                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST |
9298                         I40E_INSET_SRC_PORT | I40E_INSET_DST_PORT |
9299                         I40E_INSET_SCTP_VT,
9300                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] =
9301                         I40E_INSET_IPV6_SRC | I40E_INSET_IPV6_DST,
9302                 [I40E_FILTER_PCTYPE_L2_PAYLOAD] =
9303                         I40E_INSET_LAST_ETHER_TYPE,
9304         };
9305
9306         if (pctype > I40E_FILTER_PCTYPE_L2_PAYLOAD)
9307                 return 0;
9308
9309         return default_inset_table[pctype];
9310 }
9311
9312 /**
9313  * Parse the input set from index to logical bit masks
9314  */
9315 static int
9316 i40e_parse_input_set(uint64_t *inset,
9317                      enum i40e_filter_pctype pctype,
9318                      enum rte_eth_input_set_field *field,
9319                      uint16_t size)
9320 {
9321         uint16_t i, j;
9322         int ret = -EINVAL;
9323
9324         static const struct {
9325                 enum rte_eth_input_set_field field;
9326                 uint64_t inset;
9327         } inset_convert_table[] = {
9328                 {RTE_ETH_INPUT_SET_NONE, I40E_INSET_NONE},
9329                 {RTE_ETH_INPUT_SET_L2_SRC_MAC, I40E_INSET_SMAC},
9330                 {RTE_ETH_INPUT_SET_L2_DST_MAC, I40E_INSET_DMAC},
9331                 {RTE_ETH_INPUT_SET_L2_OUTER_VLAN, I40E_INSET_VLAN_OUTER},
9332                 {RTE_ETH_INPUT_SET_L2_INNER_VLAN, I40E_INSET_VLAN_INNER},
9333                 {RTE_ETH_INPUT_SET_L2_ETHERTYPE, I40E_INSET_LAST_ETHER_TYPE},
9334                 {RTE_ETH_INPUT_SET_L3_SRC_IP4, I40E_INSET_IPV4_SRC},
9335                 {RTE_ETH_INPUT_SET_L3_DST_IP4, I40E_INSET_IPV4_DST},
9336                 {RTE_ETH_INPUT_SET_L3_IP4_TOS, I40E_INSET_IPV4_TOS},
9337                 {RTE_ETH_INPUT_SET_L3_IP4_PROTO, I40E_INSET_IPV4_PROTO},
9338                 {RTE_ETH_INPUT_SET_L3_IP4_TTL, I40E_INSET_IPV4_TTL},
9339                 {RTE_ETH_INPUT_SET_L3_SRC_IP6, I40E_INSET_IPV6_SRC},
9340                 {RTE_ETH_INPUT_SET_L3_DST_IP6, I40E_INSET_IPV6_DST},
9341                 {RTE_ETH_INPUT_SET_L3_IP6_TC, I40E_INSET_IPV6_TC},
9342                 {RTE_ETH_INPUT_SET_L3_IP6_NEXT_HEADER,
9343                         I40E_INSET_IPV6_NEXT_HDR},
9344                 {RTE_ETH_INPUT_SET_L3_IP6_HOP_LIMITS,
9345                         I40E_INSET_IPV6_HOP_LIMIT},
9346                 {RTE_ETH_INPUT_SET_L4_UDP_SRC_PORT, I40E_INSET_SRC_PORT},
9347                 {RTE_ETH_INPUT_SET_L4_TCP_SRC_PORT, I40E_INSET_SRC_PORT},
9348                 {RTE_ETH_INPUT_SET_L4_SCTP_SRC_PORT, I40E_INSET_SRC_PORT},
9349                 {RTE_ETH_INPUT_SET_L4_UDP_DST_PORT, I40E_INSET_DST_PORT},
9350                 {RTE_ETH_INPUT_SET_L4_TCP_DST_PORT, I40E_INSET_DST_PORT},
9351                 {RTE_ETH_INPUT_SET_L4_SCTP_DST_PORT, I40E_INSET_DST_PORT},
9352                 {RTE_ETH_INPUT_SET_L4_SCTP_VERIFICATION_TAG,
9353                         I40E_INSET_SCTP_VT},
9354                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_DST_MAC,
9355                         I40E_INSET_TUNNEL_DMAC},
9356                 {RTE_ETH_INPUT_SET_TUNNEL_L2_INNER_VLAN,
9357                         I40E_INSET_VLAN_TUNNEL},
9358                 {RTE_ETH_INPUT_SET_TUNNEL_L4_UDP_KEY,
9359                         I40E_INSET_TUNNEL_ID},
9360                 {RTE_ETH_INPUT_SET_TUNNEL_GRE_KEY, I40E_INSET_TUNNEL_ID},
9361                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_1ST_WORD,
9362                         I40E_INSET_FLEX_PAYLOAD_W1},
9363                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_2ND_WORD,
9364                         I40E_INSET_FLEX_PAYLOAD_W2},
9365                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_3RD_WORD,
9366                         I40E_INSET_FLEX_PAYLOAD_W3},
9367                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_4TH_WORD,
9368                         I40E_INSET_FLEX_PAYLOAD_W4},
9369                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_5TH_WORD,
9370                         I40E_INSET_FLEX_PAYLOAD_W5},
9371                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_6TH_WORD,
9372                         I40E_INSET_FLEX_PAYLOAD_W6},
9373                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_7TH_WORD,
9374                         I40E_INSET_FLEX_PAYLOAD_W7},
9375                 {RTE_ETH_INPUT_SET_FLEX_PAYLOAD_8TH_WORD,
9376                         I40E_INSET_FLEX_PAYLOAD_W8},
9377         };
9378
9379         if (!inset || !field || size > RTE_ETH_INSET_SIZE_MAX)
9380                 return ret;
9381
9382         /* Only one item allowed for default or all */
9383         if (size == 1) {
9384                 if (field[0] == RTE_ETH_INPUT_SET_DEFAULT) {
9385                         *inset = i40e_get_default_input_set(pctype);
9386                         return 0;
9387                 } else if (field[0] == RTE_ETH_INPUT_SET_NONE) {
9388                         *inset = I40E_INSET_NONE;
9389                         return 0;
9390                 }
9391         }
9392
9393         for (i = 0, *inset = 0; i < size; i++) {
9394                 for (j = 0; j < RTE_DIM(inset_convert_table); j++) {
9395                         if (field[i] == inset_convert_table[j].field) {
9396                                 *inset |= inset_convert_table[j].inset;
9397                                 break;
9398                         }
9399                 }
9400
9401                 /* It contains unsupported input set, return immediately */
9402                 if (j == RTE_DIM(inset_convert_table))
9403                         return ret;
9404         }
9405
9406         return 0;
9407 }
9408
9409 /**
9410  * Translate the input set from bit masks to register aware bit masks
9411  * and vice versa
9412  */
9413 uint64_t
9414 i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input)
9415 {
9416         uint64_t val = 0;
9417         uint16_t i;
9418
9419         struct inset_map {
9420                 uint64_t inset;
9421                 uint64_t inset_reg;
9422         };
9423
9424         static const struct inset_map inset_map_common[] = {
9425                 {I40E_INSET_DMAC, I40E_REG_INSET_L2_DMAC},
9426                 {I40E_INSET_SMAC, I40E_REG_INSET_L2_SMAC},
9427                 {I40E_INSET_VLAN_OUTER, I40E_REG_INSET_L2_OUTER_VLAN},
9428                 {I40E_INSET_VLAN_INNER, I40E_REG_INSET_L2_INNER_VLAN},
9429                 {I40E_INSET_LAST_ETHER_TYPE, I40E_REG_INSET_LAST_ETHER_TYPE},
9430                 {I40E_INSET_IPV4_TOS, I40E_REG_INSET_L3_IP4_TOS},
9431                 {I40E_INSET_IPV6_SRC, I40E_REG_INSET_L3_SRC_IP6},
9432                 {I40E_INSET_IPV6_DST, I40E_REG_INSET_L3_DST_IP6},
9433                 {I40E_INSET_IPV6_TC, I40E_REG_INSET_L3_IP6_TC},
9434                 {I40E_INSET_IPV6_NEXT_HDR, I40E_REG_INSET_L3_IP6_NEXT_HDR},
9435                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_REG_INSET_L3_IP6_HOP_LIMIT},
9436                 {I40E_INSET_SRC_PORT, I40E_REG_INSET_L4_SRC_PORT},
9437                 {I40E_INSET_DST_PORT, I40E_REG_INSET_L4_DST_PORT},
9438                 {I40E_INSET_SCTP_VT, I40E_REG_INSET_L4_SCTP_VERIFICATION_TAG},
9439                 {I40E_INSET_TUNNEL_ID, I40E_REG_INSET_TUNNEL_ID},
9440                 {I40E_INSET_TUNNEL_DMAC,
9441                         I40E_REG_INSET_TUNNEL_L2_INNER_DST_MAC},
9442                 {I40E_INSET_TUNNEL_IPV4_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP4},
9443                 {I40E_INSET_TUNNEL_IPV6_DST, I40E_REG_INSET_TUNNEL_L3_DST_IP6},
9444                 {I40E_INSET_TUNNEL_SRC_PORT,
9445                         I40E_REG_INSET_TUNNEL_L4_UDP_SRC_PORT},
9446                 {I40E_INSET_TUNNEL_DST_PORT,
9447                         I40E_REG_INSET_TUNNEL_L4_UDP_DST_PORT},
9448                 {I40E_INSET_VLAN_TUNNEL, I40E_REG_INSET_TUNNEL_VLAN},
9449                 {I40E_INSET_FLEX_PAYLOAD_W1, I40E_REG_INSET_FLEX_PAYLOAD_WORD1},
9450                 {I40E_INSET_FLEX_PAYLOAD_W2, I40E_REG_INSET_FLEX_PAYLOAD_WORD2},
9451                 {I40E_INSET_FLEX_PAYLOAD_W3, I40E_REG_INSET_FLEX_PAYLOAD_WORD3},
9452                 {I40E_INSET_FLEX_PAYLOAD_W4, I40E_REG_INSET_FLEX_PAYLOAD_WORD4},
9453                 {I40E_INSET_FLEX_PAYLOAD_W5, I40E_REG_INSET_FLEX_PAYLOAD_WORD5},
9454                 {I40E_INSET_FLEX_PAYLOAD_W6, I40E_REG_INSET_FLEX_PAYLOAD_WORD6},
9455                 {I40E_INSET_FLEX_PAYLOAD_W7, I40E_REG_INSET_FLEX_PAYLOAD_WORD7},
9456                 {I40E_INSET_FLEX_PAYLOAD_W8, I40E_REG_INSET_FLEX_PAYLOAD_WORD8},
9457         };
9458
9459     /* some different registers map in x722*/
9460         static const struct inset_map inset_map_diff_x722[] = {
9461                 {I40E_INSET_IPV4_SRC, I40E_X722_REG_INSET_L3_SRC_IP4},
9462                 {I40E_INSET_IPV4_DST, I40E_X722_REG_INSET_L3_DST_IP4},
9463                 {I40E_INSET_IPV4_PROTO, I40E_X722_REG_INSET_L3_IP4_PROTO},
9464                 {I40E_INSET_IPV4_TTL, I40E_X722_REG_INSET_L3_IP4_TTL},
9465         };
9466
9467         static const struct inset_map inset_map_diff_not_x722[] = {
9468                 {I40E_INSET_IPV4_SRC, I40E_REG_INSET_L3_SRC_IP4},
9469                 {I40E_INSET_IPV4_DST, I40E_REG_INSET_L3_DST_IP4},
9470                 {I40E_INSET_IPV4_PROTO, I40E_REG_INSET_L3_IP4_PROTO},
9471                 {I40E_INSET_IPV4_TTL, I40E_REG_INSET_L3_IP4_TTL},
9472         };
9473
9474         if (input == 0)
9475                 return val;
9476
9477         /* Translate input set to register aware inset */
9478         if (type == I40E_MAC_X722) {
9479                 for (i = 0; i < RTE_DIM(inset_map_diff_x722); i++) {
9480                         if (input & inset_map_diff_x722[i].inset)
9481                                 val |= inset_map_diff_x722[i].inset_reg;
9482                 }
9483         } else {
9484                 for (i = 0; i < RTE_DIM(inset_map_diff_not_x722); i++) {
9485                         if (input & inset_map_diff_not_x722[i].inset)
9486                                 val |= inset_map_diff_not_x722[i].inset_reg;
9487                 }
9488         }
9489
9490         for (i = 0; i < RTE_DIM(inset_map_common); i++) {
9491                 if (input & inset_map_common[i].inset)
9492                         val |= inset_map_common[i].inset_reg;
9493         }
9494
9495         return val;
9496 }
9497
9498 int
9499 i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask, uint8_t nb_elem)
9500 {
9501         uint8_t i, idx = 0;
9502         uint64_t inset_need_mask = inset;
9503
9504         static const struct {
9505                 uint64_t inset;
9506                 uint32_t mask;
9507         } inset_mask_map[] = {
9508                 {I40E_INSET_IPV4_TOS, I40E_INSET_IPV4_TOS_MASK},
9509                 {I40E_INSET_IPV4_PROTO | I40E_INSET_IPV4_TTL, 0},
9510                 {I40E_INSET_IPV4_PROTO, I40E_INSET_IPV4_PROTO_MASK},
9511                 {I40E_INSET_IPV4_TTL, I40E_INSET_IPv4_TTL_MASK},
9512                 {I40E_INSET_IPV6_TC, I40E_INSET_IPV6_TC_MASK},
9513                 {I40E_INSET_IPV6_NEXT_HDR | I40E_INSET_IPV6_HOP_LIMIT, 0},
9514                 {I40E_INSET_IPV6_NEXT_HDR, I40E_INSET_IPV6_NEXT_HDR_MASK},
9515                 {I40E_INSET_IPV6_HOP_LIMIT, I40E_INSET_IPV6_HOP_LIMIT_MASK},
9516         };
9517
9518         if (!inset || !mask || !nb_elem)
9519                 return 0;
9520
9521         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9522                 /* Clear the inset bit, if no MASK is required,
9523                  * for example proto + ttl
9524                  */
9525                 if ((inset & inset_mask_map[i].inset) ==
9526                      inset_mask_map[i].inset && inset_mask_map[i].mask == 0)
9527                         inset_need_mask &= ~inset_mask_map[i].inset;
9528                 if (!inset_need_mask)
9529                         return 0;
9530         }
9531         for (i = 0, idx = 0; i < RTE_DIM(inset_mask_map); i++) {
9532                 if ((inset_need_mask & inset_mask_map[i].inset) ==
9533                     inset_mask_map[i].inset) {
9534                         if (idx >= nb_elem) {
9535                                 PMD_DRV_LOG(ERR, "exceed maximal number of bitmasks");
9536                                 return -EINVAL;
9537                         }
9538                         mask[idx] = inset_mask_map[i].mask;
9539                         idx++;
9540                 }
9541         }
9542
9543         return idx;
9544 }
9545
9546 void
9547 i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9548 {
9549         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9550
9551         PMD_DRV_LOG(DEBUG, "[0x%08x] original: 0x%08x", addr, reg);
9552         if (reg != val)
9553                 i40e_write_rx_ctl(hw, addr, val);
9554         PMD_DRV_LOG(DEBUG, "[0x%08x] after: 0x%08x", addr,
9555                     (uint32_t)i40e_read_rx_ctl(hw, addr));
9556 }
9557
9558 void
9559 i40e_check_write_global_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val)
9560 {
9561         uint32_t reg = i40e_read_rx_ctl(hw, addr);
9562         struct rte_eth_dev *dev;
9563
9564         dev = ((struct i40e_adapter *)hw->back)->eth_dev;
9565         if (reg != val) {
9566                 i40e_write_rx_ctl(hw, addr, val);
9567                 PMD_DRV_LOG(WARNING,
9568                             "i40e device %s changed global register [0x%08x]."
9569                             " original: 0x%08x, new: 0x%08x",
9570                             dev->device->name, addr, reg,
9571                             (uint32_t)i40e_read_rx_ctl(hw, addr));
9572         }
9573 }
9574
9575 static void
9576 i40e_filter_input_set_init(struct i40e_pf *pf)
9577 {
9578         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9579         enum i40e_filter_pctype pctype;
9580         uint64_t input_set, inset_reg;
9581         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9582         int num, i;
9583         uint16_t flow_type;
9584
9585         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
9586              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
9587                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
9588
9589                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
9590                         continue;
9591
9592                 input_set = i40e_get_default_input_set(pctype);
9593
9594                 num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9595                                                    I40E_INSET_MASK_NUM_REG);
9596                 if (num < 0)
9597                         return;
9598                 if (pf->support_multi_driver && num > 0) {
9599                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9600                         return;
9601                 }
9602                 inset_reg = i40e_translate_input_set_reg(hw->mac.type,
9603                                         input_set);
9604
9605                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9606                                       (uint32_t)(inset_reg & UINT32_MAX));
9607                 i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9608                                      (uint32_t)((inset_reg >>
9609                                      I40E_32_BIT_WIDTH) & UINT32_MAX));
9610                 if (!pf->support_multi_driver) {
9611                         i40e_check_write_global_reg(hw,
9612                                             I40E_GLQF_HASH_INSET(0, pctype),
9613                                             (uint32_t)(inset_reg & UINT32_MAX));
9614                         i40e_check_write_global_reg(hw,
9615                                              I40E_GLQF_HASH_INSET(1, pctype),
9616                                              (uint32_t)((inset_reg >>
9617                                               I40E_32_BIT_WIDTH) & UINT32_MAX));
9618
9619                         for (i = 0; i < num; i++) {
9620                                 i40e_check_write_global_reg(hw,
9621                                                     I40E_GLQF_FD_MSK(i, pctype),
9622                                                     mask_reg[i]);
9623                                 i40e_check_write_global_reg(hw,
9624                                                   I40E_GLQF_HASH_MSK(i, pctype),
9625                                                   mask_reg[i]);
9626                         }
9627                         /*clear unused mask registers of the pctype */
9628                         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++) {
9629                                 i40e_check_write_global_reg(hw,
9630                                                     I40E_GLQF_FD_MSK(i, pctype),
9631                                                     0);
9632                                 i40e_check_write_global_reg(hw,
9633                                                   I40E_GLQF_HASH_MSK(i, pctype),
9634                                                   0);
9635                         }
9636                 } else {
9637                         PMD_DRV_LOG(ERR, "Input set setting is not supported.");
9638                 }
9639                 I40E_WRITE_FLUSH(hw);
9640
9641                 /* store the default input set */
9642                 if (!pf->support_multi_driver)
9643                         pf->hash_input_set[pctype] = input_set;
9644                 pf->fdir.input_set[pctype] = input_set;
9645         }
9646 }
9647
9648 int
9649 i40e_hash_filter_inset_select(struct i40e_hw *hw,
9650                          struct rte_eth_input_set_conf *conf)
9651 {
9652         struct i40e_pf *pf = &((struct i40e_adapter *)hw->back)->pf;
9653         enum i40e_filter_pctype pctype;
9654         uint64_t input_set, inset_reg = 0;
9655         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9656         int ret, i, num;
9657
9658         if (!conf) {
9659                 PMD_DRV_LOG(ERR, "Invalid pointer");
9660                 return -EFAULT;
9661         }
9662         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9663             conf->op != RTE_ETH_INPUT_SET_ADD) {
9664                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9665                 return -EINVAL;
9666         }
9667
9668         if (pf->support_multi_driver) {
9669                 PMD_DRV_LOG(ERR, "Hash input set setting is not supported.");
9670                 return -ENOTSUP;
9671         }
9672
9673         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9674         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9675                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9676                 return -EINVAL;
9677         }
9678
9679         if (hw->mac.type == I40E_MAC_X722) {
9680                 /* get translated pctype value in fd pctype register */
9681                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(hw,
9682                         I40E_GLQF_FD_PCTYPES((int)pctype));
9683         }
9684
9685         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9686                                    conf->inset_size);
9687         if (ret) {
9688                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9689                 return -EINVAL;
9690         }
9691
9692         if (conf->op == RTE_ETH_INPUT_SET_ADD) {
9693                 /* get inset value in register */
9694                 inset_reg = i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(1, pctype));
9695                 inset_reg <<= I40E_32_BIT_WIDTH;
9696                 inset_reg |= i40e_read_rx_ctl(hw, I40E_GLQF_HASH_INSET(0, pctype));
9697                 input_set |= pf->hash_input_set[pctype];
9698         }
9699         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9700                                            I40E_INSET_MASK_NUM_REG);
9701         if (num < 0)
9702                 return -EINVAL;
9703
9704         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9705
9706         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(0, pctype),
9707                                     (uint32_t)(inset_reg & UINT32_MAX));
9708         i40e_check_write_global_reg(hw, I40E_GLQF_HASH_INSET(1, pctype),
9709                                     (uint32_t)((inset_reg >>
9710                                     I40E_32_BIT_WIDTH) & UINT32_MAX));
9711
9712         for (i = 0; i < num; i++)
9713                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9714                                             mask_reg[i]);
9715         /*clear unused mask registers of the pctype */
9716         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9717                 i40e_check_write_global_reg(hw, I40E_GLQF_HASH_MSK(i, pctype),
9718                                             0);
9719         I40E_WRITE_FLUSH(hw);
9720
9721         pf->hash_input_set[pctype] = input_set;
9722         return 0;
9723 }
9724
9725 int
9726 i40e_fdir_filter_inset_select(struct i40e_pf *pf,
9727                          struct rte_eth_input_set_conf *conf)
9728 {
9729         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9730         enum i40e_filter_pctype pctype;
9731         uint64_t input_set, inset_reg = 0;
9732         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
9733         int ret, i, num;
9734
9735         if (!hw || !conf) {
9736                 PMD_DRV_LOG(ERR, "Invalid pointer");
9737                 return -EFAULT;
9738         }
9739         if (conf->op != RTE_ETH_INPUT_SET_SELECT &&
9740             conf->op != RTE_ETH_INPUT_SET_ADD) {
9741                 PMD_DRV_LOG(ERR, "Unsupported input set operation");
9742                 return -EINVAL;
9743         }
9744
9745         pctype = i40e_flowtype_to_pctype(pf->adapter, conf->flow_type);
9746
9747         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
9748                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
9749                 return -EINVAL;
9750         }
9751
9752         ret = i40e_parse_input_set(&input_set, pctype, conf->field,
9753                                    conf->inset_size);
9754         if (ret) {
9755                 PMD_DRV_LOG(ERR, "Failed to parse input set");
9756                 return -EINVAL;
9757         }
9758
9759         /* get inset value in register */
9760         inset_reg = i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 1));
9761         inset_reg <<= I40E_32_BIT_WIDTH;
9762         inset_reg |= i40e_read_rx_ctl(hw, I40E_PRTQF_FD_INSET(pctype, 0));
9763
9764         /* Can not change the inset reg for flex payload for fdir,
9765          * it is done by writing I40E_PRTQF_FD_FLXINSET
9766          * in i40e_set_flex_mask_on_pctype.
9767          */
9768         if (conf->op == RTE_ETH_INPUT_SET_SELECT)
9769                 inset_reg &= I40E_REG_INSET_FLEX_PAYLOAD_WORDS;
9770         else
9771                 input_set |= pf->fdir.input_set[pctype];
9772         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
9773                                            I40E_INSET_MASK_NUM_REG);
9774         if (num < 0)
9775                 return -EINVAL;
9776         if (pf->support_multi_driver && num > 0) {
9777                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9778                 return -ENOTSUP;
9779         }
9780
9781         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
9782
9783         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
9784                               (uint32_t)(inset_reg & UINT32_MAX));
9785         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
9786                              (uint32_t)((inset_reg >>
9787                              I40E_32_BIT_WIDTH) & UINT32_MAX));
9788
9789         if (!pf->support_multi_driver) {
9790                 for (i = 0; i < num; i++)
9791                         i40e_check_write_global_reg(hw,
9792                                                     I40E_GLQF_FD_MSK(i, pctype),
9793                                                     mask_reg[i]);
9794                 /*clear unused mask registers of the pctype */
9795                 for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
9796                         i40e_check_write_global_reg(hw,
9797                                                     I40E_GLQF_FD_MSK(i, pctype),
9798                                                     0);
9799         } else {
9800                 PMD_DRV_LOG(ERR, "FDIR bit mask is not supported.");
9801         }
9802         I40E_WRITE_FLUSH(hw);
9803
9804         pf->fdir.input_set[pctype] = input_set;
9805         return 0;
9806 }
9807
9808 static int
9809 i40e_hash_filter_get(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9810 {
9811         int ret = 0;
9812
9813         if (!hw || !info) {
9814                 PMD_DRV_LOG(ERR, "Invalid pointer");
9815                 return -EFAULT;
9816         }
9817
9818         switch (info->info_type) {
9819         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9820                 i40e_get_symmetric_hash_enable_per_port(hw,
9821                                         &(info->info.enable));
9822                 break;
9823         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9824                 ret = i40e_get_hash_filter_global_config(hw,
9825                                 &(info->info.global_conf));
9826                 break;
9827         default:
9828                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9829                                                         info->info_type);
9830                 ret = -EINVAL;
9831                 break;
9832         }
9833
9834         return ret;
9835 }
9836
9837 static int
9838 i40e_hash_filter_set(struct i40e_hw *hw, struct rte_eth_hash_filter_info *info)
9839 {
9840         int ret = 0;
9841
9842         if (!hw || !info) {
9843                 PMD_DRV_LOG(ERR, "Invalid pointer");
9844                 return -EFAULT;
9845         }
9846
9847         switch (info->info_type) {
9848         case RTE_ETH_HASH_FILTER_SYM_HASH_ENA_PER_PORT:
9849                 i40e_set_symmetric_hash_enable_per_port(hw, info->info.enable);
9850                 break;
9851         case RTE_ETH_HASH_FILTER_GLOBAL_CONFIG:
9852                 ret = i40e_set_hash_filter_global_config(hw,
9853                                 &(info->info.global_conf));
9854                 break;
9855         case RTE_ETH_HASH_FILTER_INPUT_SET_SELECT:
9856                 ret = i40e_hash_filter_inset_select(hw,
9857                                                &(info->info.input_set_conf));
9858                 break;
9859
9860         default:
9861                 PMD_DRV_LOG(ERR, "Hash filter info type (%d) not supported",
9862                                                         info->info_type);
9863                 ret = -EINVAL;
9864                 break;
9865         }
9866
9867         return ret;
9868 }
9869
9870 /* Operations for hash function */
9871 static int
9872 i40e_hash_filter_ctrl(struct rte_eth_dev *dev,
9873                       enum rte_filter_op filter_op,
9874                       void *arg)
9875 {
9876         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
9877         int ret = 0;
9878
9879         switch (filter_op) {
9880         case RTE_ETH_FILTER_NOP:
9881                 break;
9882         case RTE_ETH_FILTER_GET:
9883                 ret = i40e_hash_filter_get(hw,
9884                         (struct rte_eth_hash_filter_info *)arg);
9885                 break;
9886         case RTE_ETH_FILTER_SET:
9887                 ret = i40e_hash_filter_set(hw,
9888                         (struct rte_eth_hash_filter_info *)arg);
9889                 break;
9890         default:
9891                 PMD_DRV_LOG(WARNING, "Filter operation (%d) not supported",
9892                                                                 filter_op);
9893                 ret = -ENOTSUP;
9894                 break;
9895         }
9896
9897         return ret;
9898 }
9899
9900 /* Convert ethertype filter structure */
9901 static int
9902 i40e_ethertype_filter_convert(const struct rte_eth_ethertype_filter *input,
9903                               struct i40e_ethertype_filter *filter)
9904 {
9905         rte_memcpy(&filter->input.mac_addr, &input->mac_addr,
9906                 RTE_ETHER_ADDR_LEN);
9907         filter->input.ether_type = input->ether_type;
9908         filter->flags = input->flags;
9909         filter->queue = input->queue;
9910
9911         return 0;
9912 }
9913
9914 /* Check if there exists the ehtertype filter */
9915 struct i40e_ethertype_filter *
9916 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
9917                                 const struct i40e_ethertype_filter_input *input)
9918 {
9919         int ret;
9920
9921         ret = rte_hash_lookup(ethertype_rule->hash_table, (const void *)input);
9922         if (ret < 0)
9923                 return NULL;
9924
9925         return ethertype_rule->hash_map[ret];
9926 }
9927
9928 /* Add ethertype filter in SW list */
9929 static int
9930 i40e_sw_ethertype_filter_insert(struct i40e_pf *pf,
9931                                 struct i40e_ethertype_filter *filter)
9932 {
9933         struct i40e_ethertype_rule *rule = &pf->ethertype;
9934         int ret;
9935
9936         ret = rte_hash_add_key(rule->hash_table, &filter->input);
9937         if (ret < 0) {
9938                 PMD_DRV_LOG(ERR,
9939                             "Failed to insert ethertype filter"
9940                             " to hash table %d!",
9941                             ret);
9942                 return ret;
9943         }
9944         rule->hash_map[ret] = filter;
9945
9946         TAILQ_INSERT_TAIL(&rule->ethertype_list, filter, rules);
9947
9948         return 0;
9949 }
9950
9951 /* Delete ethertype filter in SW list */
9952 int
9953 i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
9954                              struct i40e_ethertype_filter_input *input)
9955 {
9956         struct i40e_ethertype_rule *rule = &pf->ethertype;
9957         struct i40e_ethertype_filter *filter;
9958         int ret;
9959
9960         ret = rte_hash_del_key(rule->hash_table, input);
9961         if (ret < 0) {
9962                 PMD_DRV_LOG(ERR,
9963                             "Failed to delete ethertype filter"
9964                             " to hash table %d!",
9965                             ret);
9966                 return ret;
9967         }
9968         filter = rule->hash_map[ret];
9969         rule->hash_map[ret] = NULL;
9970
9971         TAILQ_REMOVE(&rule->ethertype_list, filter, rules);
9972         rte_free(filter);
9973
9974         return 0;
9975 }
9976
9977 /*
9978  * Configure ethertype filter, which can director packet by filtering
9979  * with mac address and ether_type or only ether_type
9980  */
9981 int
9982 i40e_ethertype_filter_set(struct i40e_pf *pf,
9983                         struct rte_eth_ethertype_filter *filter,
9984                         bool add)
9985 {
9986         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
9987         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
9988         struct i40e_ethertype_filter *ethertype_filter, *node;
9989         struct i40e_ethertype_filter check_filter;
9990         struct i40e_control_filter_stats stats;
9991         uint16_t flags = 0;
9992         int ret;
9993
9994         if (filter->queue >= pf->dev_data->nb_rx_queues) {
9995                 PMD_DRV_LOG(ERR, "Invalid queue ID");
9996                 return -EINVAL;
9997         }
9998         if (filter->ether_type == RTE_ETHER_TYPE_IPV4 ||
9999                 filter->ether_type == RTE_ETHER_TYPE_IPV6) {
10000                 PMD_DRV_LOG(ERR,
10001                         "unsupported ether_type(0x%04x) in control packet filter.",
10002                         filter->ether_type);
10003                 return -EINVAL;
10004         }
10005         if (filter->ether_type == RTE_ETHER_TYPE_VLAN)
10006                 PMD_DRV_LOG(WARNING,
10007                         "filter vlan ether_type in first tag is not supported.");
10008
10009         /* Check if there is the filter in SW list */
10010         memset(&check_filter, 0, sizeof(check_filter));
10011         i40e_ethertype_filter_convert(filter, &check_filter);
10012         node = i40e_sw_ethertype_filter_lookup(ethertype_rule,
10013                                                &check_filter.input);
10014         if (add && node) {
10015                 PMD_DRV_LOG(ERR, "Conflict with existing ethertype rules!");
10016                 return -EINVAL;
10017         }
10018
10019         if (!add && !node) {
10020                 PMD_DRV_LOG(ERR, "There's no corresponding ethertype filter!");
10021                 return -EINVAL;
10022         }
10023
10024         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
10025                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
10026         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
10027                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
10028         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
10029
10030         memset(&stats, 0, sizeof(stats));
10031         ret = i40e_aq_add_rem_control_packet_filter(hw,
10032                         filter->mac_addr.addr_bytes,
10033                         filter->ether_type, flags,
10034                         pf->main_vsi->seid,
10035                         filter->queue, add, &stats, NULL);
10036
10037         PMD_DRV_LOG(INFO,
10038                 "add/rem control packet filter, return %d, mac_etype_used = %u, etype_used = %u, mac_etype_free = %u, etype_free = %u",
10039                 ret, stats.mac_etype_used, stats.etype_used,
10040                 stats.mac_etype_free, stats.etype_free);
10041         if (ret < 0)
10042                 return -ENOSYS;
10043
10044         /* Add or delete a filter in SW list */
10045         if (add) {
10046                 ethertype_filter = rte_zmalloc("ethertype_filter",
10047                                        sizeof(*ethertype_filter), 0);
10048                 if (ethertype_filter == NULL) {
10049                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
10050                         return -ENOMEM;
10051                 }
10052
10053                 rte_memcpy(ethertype_filter, &check_filter,
10054                            sizeof(check_filter));
10055                 ret = i40e_sw_ethertype_filter_insert(pf, ethertype_filter);
10056                 if (ret < 0)
10057                         rte_free(ethertype_filter);
10058         } else {
10059                 ret = i40e_sw_ethertype_filter_del(pf, &node->input);
10060         }
10061
10062         return ret;
10063 }
10064
10065 /*
10066  * Handle operations for ethertype filter.
10067  */
10068 static int
10069 i40e_ethertype_filter_handle(struct rte_eth_dev *dev,
10070                                 enum rte_filter_op filter_op,
10071                                 void *arg)
10072 {
10073         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10074         int ret = 0;
10075
10076         if (filter_op == RTE_ETH_FILTER_NOP)
10077                 return ret;
10078
10079         if (arg == NULL) {
10080                 PMD_DRV_LOG(ERR, "arg shouldn't be NULL for operation %u",
10081                             filter_op);
10082                 return -EINVAL;
10083         }
10084
10085         switch (filter_op) {
10086         case RTE_ETH_FILTER_ADD:
10087                 ret = i40e_ethertype_filter_set(pf,
10088                         (struct rte_eth_ethertype_filter *)arg,
10089                         TRUE);
10090                 break;
10091         case RTE_ETH_FILTER_DELETE:
10092                 ret = i40e_ethertype_filter_set(pf,
10093                         (struct rte_eth_ethertype_filter *)arg,
10094                         FALSE);
10095                 break;
10096         default:
10097                 PMD_DRV_LOG(ERR, "unsupported operation %u", filter_op);
10098                 ret = -ENOSYS;
10099                 break;
10100         }
10101         return ret;
10102 }
10103
10104 static int
10105 i40e_dev_filter_ctrl(struct rte_eth_dev *dev,
10106                      enum rte_filter_type filter_type,
10107                      enum rte_filter_op filter_op,
10108                      void *arg)
10109 {
10110         int ret = 0;
10111
10112         if (dev == NULL)
10113                 return -EINVAL;
10114
10115         switch (filter_type) {
10116         case RTE_ETH_FILTER_NONE:
10117                 /* For global configuration */
10118                 ret = i40e_filter_ctrl_global_config(dev, filter_op, arg);
10119                 break;
10120         case RTE_ETH_FILTER_HASH:
10121                 ret = i40e_hash_filter_ctrl(dev, filter_op, arg);
10122                 break;
10123         case RTE_ETH_FILTER_MACVLAN:
10124                 ret = i40e_mac_filter_handle(dev, filter_op, arg);
10125                 break;
10126         case RTE_ETH_FILTER_ETHERTYPE:
10127                 ret = i40e_ethertype_filter_handle(dev, filter_op, arg);
10128                 break;
10129         case RTE_ETH_FILTER_TUNNEL:
10130                 ret = i40e_tunnel_filter_handle(dev, filter_op, arg);
10131                 break;
10132         case RTE_ETH_FILTER_FDIR:
10133                 ret = i40e_fdir_ctrl_func(dev, filter_op, arg);
10134                 break;
10135         case RTE_ETH_FILTER_GENERIC:
10136                 if (filter_op != RTE_ETH_FILTER_GET)
10137                         return -EINVAL;
10138                 *(const void **)arg = &i40e_flow_ops;
10139                 break;
10140         default:
10141                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
10142                                                         filter_type);
10143                 ret = -EINVAL;
10144                 break;
10145         }
10146
10147         return ret;
10148 }
10149
10150 /*
10151  * Check and enable Extended Tag.
10152  * Enabling Extended Tag is important for 40G performance.
10153  */
10154 static void
10155 i40e_enable_extended_tag(struct rte_eth_dev *dev)
10156 {
10157         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
10158         uint32_t buf = 0;
10159         int ret;
10160
10161         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10162                                       PCI_DEV_CAP_REG);
10163         if (ret < 0) {
10164                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10165                             PCI_DEV_CAP_REG);
10166                 return;
10167         }
10168         if (!(buf & PCI_DEV_CAP_EXT_TAG_MASK)) {
10169                 PMD_DRV_LOG(ERR, "Does not support Extended Tag");
10170                 return;
10171         }
10172
10173         buf = 0;
10174         ret = rte_pci_read_config(pci_dev, &buf, sizeof(buf),
10175                                       PCI_DEV_CTRL_REG);
10176         if (ret < 0) {
10177                 PMD_DRV_LOG(ERR, "Failed to read PCI offset 0x%x",
10178                             PCI_DEV_CTRL_REG);
10179                 return;
10180         }
10181         if (buf & PCI_DEV_CTRL_EXT_TAG_MASK) {
10182                 PMD_DRV_LOG(DEBUG, "Extended Tag has already been enabled");
10183                 return;
10184         }
10185         buf |= PCI_DEV_CTRL_EXT_TAG_MASK;
10186         ret = rte_pci_write_config(pci_dev, &buf, sizeof(buf),
10187                                        PCI_DEV_CTRL_REG);
10188         if (ret < 0) {
10189                 PMD_DRV_LOG(ERR, "Failed to write PCI offset 0x%x",
10190                             PCI_DEV_CTRL_REG);
10191                 return;
10192         }
10193 }
10194
10195 /*
10196  * As some registers wouldn't be reset unless a global hardware reset,
10197  * hardware initialization is needed to put those registers into an
10198  * expected initial state.
10199  */
10200 static void
10201 i40e_hw_init(struct rte_eth_dev *dev)
10202 {
10203         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10204
10205         i40e_enable_extended_tag(dev);
10206
10207         /* clear the PF Queue Filter control register */
10208         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, 0);
10209
10210         /* Disable symmetric hash per port */
10211         i40e_set_symmetric_hash_enable_per_port(hw, 0);
10212 }
10213
10214 /*
10215  * For X722 it is possible to have multiple pctypes mapped to the same flowtype
10216  * however this function will return only one highest pctype index,
10217  * which is not quite correct. This is known problem of i40e driver
10218  * and needs to be fixed later.
10219  */
10220 enum i40e_filter_pctype
10221 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter, uint16_t flow_type)
10222 {
10223         int i;
10224         uint64_t pctype_mask;
10225
10226         if (flow_type < I40E_FLOW_TYPE_MAX) {
10227                 pctype_mask = adapter->pctypes_tbl[flow_type];
10228                 for (i = I40E_FILTER_PCTYPE_MAX - 1; i > 0; i--) {
10229                         if (pctype_mask & (1ULL << i))
10230                                 return (enum i40e_filter_pctype)i;
10231                 }
10232         }
10233         return I40E_FILTER_PCTYPE_INVALID;
10234 }
10235
10236 uint16_t
10237 i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
10238                         enum i40e_filter_pctype pctype)
10239 {
10240         uint16_t flowtype;
10241         uint64_t pctype_mask = 1ULL << pctype;
10242
10243         for (flowtype = RTE_ETH_FLOW_UNKNOWN + 1; flowtype < I40E_FLOW_TYPE_MAX;
10244              flowtype++) {
10245                 if (adapter->pctypes_tbl[flowtype] & pctype_mask)
10246                         return flowtype;
10247         }
10248
10249         return RTE_ETH_FLOW_UNKNOWN;
10250 }
10251
10252 /*
10253  * On X710, performance number is far from the expectation on recent firmware
10254  * versions; on XL710, performance number is also far from the expectation on
10255  * recent firmware versions, if promiscuous mode is disabled, or promiscuous
10256  * mode is enabled and port MAC address is equal to the packet destination MAC
10257  * address. The fix for this issue may not be integrated in the following
10258  * firmware version. So the workaround in software driver is needed. It needs
10259  * to modify the initial values of 3 internal only registers for both X710 and
10260  * XL710. Note that the values for X710 or XL710 could be different, and the
10261  * workaround can be removed when it is fixed in firmware in the future.
10262  */
10263
10264 /* For both X710 and XL710 */
10265 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1      0x10000200
10266 #define I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2      0x203F0200
10267 #define I40E_GL_SWR_PRI_JOIN_MAP_0              0x26CE00
10268
10269 #define I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x011f0200
10270 #define I40E_GL_SWR_PRI_JOIN_MAP_2       0x26CE08
10271
10272 /* For X722 */
10273 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE 0x20000200
10274 #define I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE 0x013F0200
10275
10276 /* For X710 */
10277 #define I40E_GL_SWR_PM_UP_THR_EF_VALUE   0x03030303
10278 /* For XL710 */
10279 #define I40E_GL_SWR_PM_UP_THR_SF_VALUE   0x06060606
10280 #define I40E_GL_SWR_PM_UP_THR            0x269FBC
10281
10282 /*
10283  * GL_SWR_PM_UP_THR:
10284  * The value is not impacted from the link speed, its value is set according
10285  * to the total number of ports for a better pipe-monitor configuration.
10286  */
10287 static bool
10288 i40e_get_swr_pm_cfg(struct i40e_hw *hw, uint32_t *value)
10289 {
10290 #define I40E_GL_SWR_PM_EF_DEVICE(dev) \
10291                 .device_id = (dev),   \
10292                 .val = I40E_GL_SWR_PM_UP_THR_EF_VALUE
10293
10294 #define I40E_GL_SWR_PM_SF_DEVICE(dev) \
10295                 .device_id = (dev),   \
10296                 .val = I40E_GL_SWR_PM_UP_THR_SF_VALUE
10297
10298         static const struct {
10299                 uint16_t device_id;
10300                 uint32_t val;
10301         } swr_pm_table[] = {
10302                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_SFP_XL710) },
10303                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_KX_C) },
10304                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T) },
10305                 { I40E_GL_SWR_PM_EF_DEVICE(I40E_DEV_ID_10G_BASE_T4) },
10306
10307                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_KX_B) },
10308                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_A) },
10309                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_QSFP_B) },
10310                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2) },
10311                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_20G_KR2_A) },
10312                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_B) },
10313                 { I40E_GL_SWR_PM_SF_DEVICE(I40E_DEV_ID_25G_SFP28) },
10314         };
10315         uint32_t i;
10316
10317         if (value == NULL) {
10318                 PMD_DRV_LOG(ERR, "value is NULL");
10319                 return false;
10320         }
10321
10322         for (i = 0; i < RTE_DIM(swr_pm_table); i++) {
10323                 if (hw->device_id == swr_pm_table[i].device_id) {
10324                         *value = swr_pm_table[i].val;
10325
10326                         PMD_DRV_LOG(DEBUG, "Device 0x%x with GL_SWR_PM_UP_THR "
10327                                     "value - 0x%08x",
10328                                     hw->device_id, *value);
10329                         return true;
10330                 }
10331         }
10332
10333         return false;
10334 }
10335
10336 static int
10337 i40e_dev_sync_phy_type(struct i40e_hw *hw)
10338 {
10339         enum i40e_status_code status;
10340         struct i40e_aq_get_phy_abilities_resp phy_ab;
10341         int ret = -ENOTSUP;
10342         int retries = 0;
10343
10344         status = i40e_aq_get_phy_capabilities(hw, false, true, &phy_ab,
10345                                               NULL);
10346
10347         while (status) {
10348                 PMD_INIT_LOG(WARNING, "Failed to sync phy type: status=%d",
10349                         status);
10350                 retries++;
10351                 rte_delay_us(100000);
10352                 if  (retries < 5)
10353                         status = i40e_aq_get_phy_capabilities(hw, false,
10354                                         true, &phy_ab, NULL);
10355                 else
10356                         return ret;
10357         }
10358         return 0;
10359 }
10360
10361 static void
10362 i40e_configure_registers(struct i40e_hw *hw)
10363 {
10364         static struct {
10365                 uint32_t addr;
10366                 uint64_t val;
10367         } reg_table[] = {
10368                 {I40E_GL_SWR_PRI_JOIN_MAP_0, 0},
10369                 {I40E_GL_SWR_PRI_JOIN_MAP_2, 0},
10370                 {I40E_GL_SWR_PM_UP_THR, 0}, /* Compute value dynamically */
10371         };
10372         uint64_t reg;
10373         uint32_t i;
10374         int ret;
10375
10376         for (i = 0; i < RTE_DIM(reg_table); i++) {
10377                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_0) {
10378                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10379                                 reg_table[i].val =
10380                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_0_VALUE;
10381                         else /* For X710/XL710/XXV710 */
10382                                 if (hw->aq.fw_maj_ver < 6)
10383                                         reg_table[i].val =
10384                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_1;
10385                                 else
10386                                         reg_table[i].val =
10387                                              I40E_GL_SWR_PRI_JOIN_MAP_0_VALUE_2;
10388                 }
10389
10390                 if (reg_table[i].addr == I40E_GL_SWR_PRI_JOIN_MAP_2) {
10391                         if (hw->mac.type == I40E_MAC_X722) /* For X722 */
10392                                 reg_table[i].val =
10393                                         I40E_X722_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10394                         else /* For X710/XL710/XXV710 */
10395                                 reg_table[i].val =
10396                                         I40E_GL_SWR_PRI_JOIN_MAP_2_VALUE;
10397                 }
10398
10399                 if (reg_table[i].addr == I40E_GL_SWR_PM_UP_THR) {
10400                         uint32_t cfg_val;
10401
10402                         if (!i40e_get_swr_pm_cfg(hw, &cfg_val)) {
10403                                 PMD_DRV_LOG(DEBUG, "Device 0x%x skips "
10404                                             "GL_SWR_PM_UP_THR value fixup",
10405                                             hw->device_id);
10406                                 continue;
10407                         }
10408
10409                         reg_table[i].val = cfg_val;
10410                 }
10411
10412                 ret = i40e_aq_debug_read_register(hw, reg_table[i].addr,
10413                                                         &reg, NULL);
10414                 if (ret < 0) {
10415                         PMD_DRV_LOG(ERR, "Failed to read from 0x%"PRIx32,
10416                                                         reg_table[i].addr);
10417                         break;
10418                 }
10419                 PMD_DRV_LOG(DEBUG, "Read from 0x%"PRIx32": 0x%"PRIx64,
10420                                                 reg_table[i].addr, reg);
10421                 if (reg == reg_table[i].val)
10422                         continue;
10423
10424                 ret = i40e_aq_debug_write_register(hw, reg_table[i].addr,
10425                                                 reg_table[i].val, NULL);
10426                 if (ret < 0) {
10427                         PMD_DRV_LOG(ERR,
10428                                 "Failed to write 0x%"PRIx64" to the address of 0x%"PRIx32,
10429                                 reg_table[i].val, reg_table[i].addr);
10430                         break;
10431                 }
10432                 PMD_DRV_LOG(DEBUG, "Write 0x%"PRIx64" to the address of "
10433                         "0x%"PRIx32, reg_table[i].val, reg_table[i].addr);
10434         }
10435 }
10436
10437 #define I40E_VSI_TSR(_i)            (0x00050800 + ((_i) * 4))
10438 #define I40E_VSI_TSR_QINQ_CONFIG    0xc030
10439 #define I40E_VSI_L2TAGSTXVALID(_i)  (0x00042800 + ((_i) * 4))
10440 #define I40E_VSI_L2TAGSTXVALID_QINQ 0xab
10441 static int
10442 i40e_config_qinq(struct i40e_hw *hw, struct i40e_vsi *vsi)
10443 {
10444         uint32_t reg;
10445         int ret;
10446
10447         if (vsi->vsi_id >= I40E_MAX_NUM_VSIS) {
10448                 PMD_DRV_LOG(ERR, "VSI ID exceeds the maximum");
10449                 return -EINVAL;
10450         }
10451
10452         /* Configure for double VLAN RX stripping */
10453         reg = I40E_READ_REG(hw, I40E_VSI_TSR(vsi->vsi_id));
10454         if ((reg & I40E_VSI_TSR_QINQ_CONFIG) != I40E_VSI_TSR_QINQ_CONFIG) {
10455                 reg |= I40E_VSI_TSR_QINQ_CONFIG;
10456                 ret = i40e_aq_debug_write_register(hw,
10457                                                    I40E_VSI_TSR(vsi->vsi_id),
10458                                                    reg, NULL);
10459                 if (ret < 0) {
10460                         PMD_DRV_LOG(ERR, "Failed to update VSI_TSR[%d]",
10461                                     vsi->vsi_id);
10462                         return I40E_ERR_CONFIG;
10463                 }
10464         }
10465
10466         /* Configure for double VLAN TX insertion */
10467         reg = I40E_READ_REG(hw, I40E_VSI_L2TAGSTXVALID(vsi->vsi_id));
10468         if ((reg & 0xff) != I40E_VSI_L2TAGSTXVALID_QINQ) {
10469                 reg = I40E_VSI_L2TAGSTXVALID_QINQ;
10470                 ret = i40e_aq_debug_write_register(hw,
10471                                                    I40E_VSI_L2TAGSTXVALID(
10472                                                    vsi->vsi_id), reg, NULL);
10473                 if (ret < 0) {
10474                         PMD_DRV_LOG(ERR,
10475                                 "Failed to update VSI_L2TAGSTXVALID[%d]",
10476                                 vsi->vsi_id);
10477                         return I40E_ERR_CONFIG;
10478                 }
10479         }
10480
10481         return 0;
10482 }
10483
10484 /**
10485  * i40e_aq_add_mirror_rule
10486  * @hw: pointer to the hardware structure
10487  * @seid: VEB seid to add mirror rule to
10488  * @dst_id: destination vsi seid
10489  * @entries: Buffer which contains the entities to be mirrored
10490  * @count: number of entities contained in the buffer
10491  * @rule_id:the rule_id of the rule to be added
10492  *
10493  * Add a mirror rule for a given veb.
10494  *
10495  **/
10496 static enum i40e_status_code
10497 i40e_aq_add_mirror_rule(struct i40e_hw *hw,
10498                         uint16_t seid, uint16_t dst_id,
10499                         uint16_t rule_type, uint16_t *entries,
10500                         uint16_t count, uint16_t *rule_id)
10501 {
10502         struct i40e_aq_desc desc;
10503         struct i40e_aqc_add_delete_mirror_rule cmd;
10504         struct i40e_aqc_add_delete_mirror_rule_completion *resp =
10505                 (struct i40e_aqc_add_delete_mirror_rule_completion *)
10506                 &desc.params.raw;
10507         uint16_t buff_len;
10508         enum i40e_status_code status;
10509
10510         i40e_fill_default_direct_cmd_desc(&desc,
10511                                           i40e_aqc_opc_add_mirror_rule);
10512         memset(&cmd, 0, sizeof(cmd));
10513
10514         buff_len = sizeof(uint16_t) * count;
10515         desc.datalen = rte_cpu_to_le_16(buff_len);
10516         if (buff_len > 0)
10517                 desc.flags |= rte_cpu_to_le_16(
10518                         (uint16_t)(I40E_AQ_FLAG_BUF | I40E_AQ_FLAG_RD));
10519         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10520                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10521         cmd.num_entries = rte_cpu_to_le_16(count);
10522         cmd.seid = rte_cpu_to_le_16(seid);
10523         cmd.destination = rte_cpu_to_le_16(dst_id);
10524
10525         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10526         status = i40e_asq_send_command(hw, &desc, entries, buff_len, NULL);
10527         PMD_DRV_LOG(INFO,
10528                 "i40e_aq_add_mirror_rule, aq_status %d, rule_id = %u mirror_rules_used = %u, mirror_rules_free = %u,",
10529                 hw->aq.asq_last_status, resp->rule_id,
10530                 resp->mirror_rules_used, resp->mirror_rules_free);
10531         *rule_id = rte_le_to_cpu_16(resp->rule_id);
10532
10533         return status;
10534 }
10535
10536 /**
10537  * i40e_aq_del_mirror_rule
10538  * @hw: pointer to the hardware structure
10539  * @seid: VEB seid to add mirror rule to
10540  * @entries: Buffer which contains the entities to be mirrored
10541  * @count: number of entities contained in the buffer
10542  * @rule_id:the rule_id of the rule to be delete
10543  *
10544  * Delete a mirror rule for a given veb.
10545  *
10546  **/
10547 static enum i40e_status_code
10548 i40e_aq_del_mirror_rule(struct i40e_hw *hw,
10549                 uint16_t seid, uint16_t rule_type, uint16_t *entries,
10550                 uint16_t count, uint16_t rule_id)
10551 {
10552         struct i40e_aq_desc desc;
10553         struct i40e_aqc_add_delete_mirror_rule cmd;
10554         uint16_t buff_len = 0;
10555         enum i40e_status_code status;
10556         void *buff = NULL;
10557
10558         i40e_fill_default_direct_cmd_desc(&desc,
10559                                           i40e_aqc_opc_delete_mirror_rule);
10560         memset(&cmd, 0, sizeof(cmd));
10561         if (rule_type == I40E_AQC_MIRROR_RULE_TYPE_VLAN) {
10562                 desc.flags |= rte_cpu_to_le_16((uint16_t)(I40E_AQ_FLAG_BUF |
10563                                                           I40E_AQ_FLAG_RD));
10564                 cmd.num_entries = count;
10565                 buff_len = sizeof(uint16_t) * count;
10566                 desc.datalen = rte_cpu_to_le_16(buff_len);
10567                 buff = (void *)entries;
10568         } else
10569                 /* rule id is filled in destination field for deleting mirror rule */
10570                 cmd.destination = rte_cpu_to_le_16(rule_id);
10571
10572         cmd.rule_type = rte_cpu_to_le_16(rule_type <<
10573                                 I40E_AQC_MIRROR_RULE_TYPE_SHIFT);
10574         cmd.seid = rte_cpu_to_le_16(seid);
10575
10576         rte_memcpy(&desc.params.raw, &cmd, sizeof(cmd));
10577         status = i40e_asq_send_command(hw, &desc, buff, buff_len, NULL);
10578
10579         return status;
10580 }
10581
10582 /**
10583  * i40e_mirror_rule_set
10584  * @dev: pointer to the hardware structure
10585  * @mirror_conf: mirror rule info
10586  * @sw_id: mirror rule's sw_id
10587  * @on: enable/disable
10588  *
10589  * set a mirror rule.
10590  *
10591  **/
10592 static int
10593 i40e_mirror_rule_set(struct rte_eth_dev *dev,
10594                         struct rte_eth_mirror_conf *mirror_conf,
10595                         uint8_t sw_id, uint8_t on)
10596 {
10597         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10599         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10600         struct i40e_mirror_rule *parent = NULL;
10601         uint16_t seid, dst_seid, rule_id;
10602         uint16_t i, j = 0;
10603         int ret;
10604
10605         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_set: sw_id = %d.", sw_id);
10606
10607         if (pf->main_vsi->veb == NULL || pf->vfs == NULL) {
10608                 PMD_DRV_LOG(ERR,
10609                         "mirror rule can not be configured without veb or vfs.");
10610                 return -ENOSYS;
10611         }
10612         if (pf->nb_mirror_rule > I40E_MAX_MIRROR_RULES) {
10613                 PMD_DRV_LOG(ERR, "mirror table is full.");
10614                 return -ENOSPC;
10615         }
10616         if (mirror_conf->dst_pool > pf->vf_num) {
10617                 PMD_DRV_LOG(ERR, "invalid destination pool %u.",
10618                                  mirror_conf->dst_pool);
10619                 return -EINVAL;
10620         }
10621
10622         seid = pf->main_vsi->veb->seid;
10623
10624         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10625                 if (sw_id <= it->index) {
10626                         mirr_rule = it;
10627                         break;
10628                 }
10629                 parent = it;
10630         }
10631         if (mirr_rule && sw_id == mirr_rule->index) {
10632                 if (on) {
10633                         PMD_DRV_LOG(ERR, "mirror rule exists.");
10634                         return -EEXIST;
10635                 } else {
10636                         ret = i40e_aq_del_mirror_rule(hw, seid,
10637                                         mirr_rule->rule_type,
10638                                         mirr_rule->entries,
10639                                         mirr_rule->num_entries, mirr_rule->id);
10640                         if (ret < 0) {
10641                                 PMD_DRV_LOG(ERR,
10642                                         "failed to remove mirror rule: ret = %d, aq_err = %d.",
10643                                         ret, hw->aq.asq_last_status);
10644                                 return -ENOSYS;
10645                         }
10646                         TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10647                         rte_free(mirr_rule);
10648                         pf->nb_mirror_rule--;
10649                         return 0;
10650                 }
10651         } else if (!on) {
10652                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10653                 return -ENOENT;
10654         }
10655
10656         mirr_rule = rte_zmalloc("i40e_mirror_rule",
10657                                 sizeof(struct i40e_mirror_rule) , 0);
10658         if (!mirr_rule) {
10659                 PMD_DRV_LOG(ERR, "failed to allocate memory");
10660                 return I40E_ERR_NO_MEMORY;
10661         }
10662         switch (mirror_conf->rule_type) {
10663         case ETH_MIRROR_VLAN:
10664                 for (i = 0, j = 0; i < ETH_MIRROR_MAX_VLANS; i++) {
10665                         if (mirror_conf->vlan.vlan_mask & (1ULL << i)) {
10666                                 mirr_rule->entries[j] =
10667                                         mirror_conf->vlan.vlan_id[i];
10668                                 j++;
10669                         }
10670                 }
10671                 if (j == 0) {
10672                         PMD_DRV_LOG(ERR, "vlan is not specified.");
10673                         rte_free(mirr_rule);
10674                         return -EINVAL;
10675                 }
10676                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_VLAN;
10677                 break;
10678         case ETH_MIRROR_VIRTUAL_POOL_UP:
10679         case ETH_MIRROR_VIRTUAL_POOL_DOWN:
10680                 /* check if the specified pool bit is out of range */
10681                 if (mirror_conf->pool_mask > (uint64_t)(1ULL << (pf->vf_num + 1))) {
10682                         PMD_DRV_LOG(ERR, "pool mask is out of range.");
10683                         rte_free(mirr_rule);
10684                         return -EINVAL;
10685                 }
10686                 for (i = 0, j = 0; i < pf->vf_num; i++) {
10687                         if (mirror_conf->pool_mask & (1ULL << i)) {
10688                                 mirr_rule->entries[j] = pf->vfs[i].vsi->seid;
10689                                 j++;
10690                         }
10691                 }
10692                 if (mirror_conf->pool_mask & (1ULL << pf->vf_num)) {
10693                         /* add pf vsi to entries */
10694                         mirr_rule->entries[j] = pf->main_vsi_seid;
10695                         j++;
10696                 }
10697                 if (j == 0) {
10698                         PMD_DRV_LOG(ERR, "pool is not specified.");
10699                         rte_free(mirr_rule);
10700                         return -EINVAL;
10701                 }
10702                 /* egress and ingress in aq commands means from switch but not port */
10703                 mirr_rule->rule_type =
10704                         (mirror_conf->rule_type == ETH_MIRROR_VIRTUAL_POOL_UP) ?
10705                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS :
10706                         I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS;
10707                 break;
10708         case ETH_MIRROR_UPLINK_PORT:
10709                 /* egress and ingress in aq commands means from switch but not port*/
10710                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS;
10711                 break;
10712         case ETH_MIRROR_DOWNLINK_PORT:
10713                 mirr_rule->rule_type = I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS;
10714                 break;
10715         default:
10716                 PMD_DRV_LOG(ERR, "unsupported mirror type %d.",
10717                         mirror_conf->rule_type);
10718                 rte_free(mirr_rule);
10719                 return -EINVAL;
10720         }
10721
10722         /* If the dst_pool is equal to vf_num, consider it as PF */
10723         if (mirror_conf->dst_pool == pf->vf_num)
10724                 dst_seid = pf->main_vsi_seid;
10725         else
10726                 dst_seid = pf->vfs[mirror_conf->dst_pool].vsi->seid;
10727
10728         ret = i40e_aq_add_mirror_rule(hw, seid, dst_seid,
10729                                       mirr_rule->rule_type, mirr_rule->entries,
10730                                       j, &rule_id);
10731         if (ret < 0) {
10732                 PMD_DRV_LOG(ERR,
10733                         "failed to add mirror rule: ret = %d, aq_err = %d.",
10734                         ret, hw->aq.asq_last_status);
10735                 rte_free(mirr_rule);
10736                 return -ENOSYS;
10737         }
10738
10739         mirr_rule->index = sw_id;
10740         mirr_rule->num_entries = j;
10741         mirr_rule->id = rule_id;
10742         mirr_rule->dst_vsi_seid = dst_seid;
10743
10744         if (parent)
10745                 TAILQ_INSERT_AFTER(&pf->mirror_list, parent, mirr_rule, rules);
10746         else
10747                 TAILQ_INSERT_HEAD(&pf->mirror_list, mirr_rule, rules);
10748
10749         pf->nb_mirror_rule++;
10750         return 0;
10751 }
10752
10753 /**
10754  * i40e_mirror_rule_reset
10755  * @dev: pointer to the device
10756  * @sw_id: mirror rule's sw_id
10757  *
10758  * reset a mirror rule.
10759  *
10760  **/
10761 static int
10762 i40e_mirror_rule_reset(struct rte_eth_dev *dev, uint8_t sw_id)
10763 {
10764         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
10765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10766         struct i40e_mirror_rule *it, *mirr_rule = NULL;
10767         uint16_t seid;
10768         int ret;
10769
10770         PMD_DRV_LOG(DEBUG, "i40e_mirror_rule_reset: sw_id = %d.", sw_id);
10771
10772         seid = pf->main_vsi->veb->seid;
10773
10774         TAILQ_FOREACH(it, &pf->mirror_list, rules) {
10775                 if (sw_id == it->index) {
10776                         mirr_rule = it;
10777                         break;
10778                 }
10779         }
10780         if (mirr_rule) {
10781                 ret = i40e_aq_del_mirror_rule(hw, seid,
10782                                 mirr_rule->rule_type,
10783                                 mirr_rule->entries,
10784                                 mirr_rule->num_entries, mirr_rule->id);
10785                 if (ret < 0) {
10786                         PMD_DRV_LOG(ERR,
10787                                 "failed to remove mirror rule: status = %d, aq_err = %d.",
10788                                 ret, hw->aq.asq_last_status);
10789                         return -ENOSYS;
10790                 }
10791                 TAILQ_REMOVE(&pf->mirror_list, mirr_rule, rules);
10792                 rte_free(mirr_rule);
10793                 pf->nb_mirror_rule--;
10794         } else {
10795                 PMD_DRV_LOG(ERR, "mirror rule doesn't exist.");
10796                 return -ENOENT;
10797         }
10798         return 0;
10799 }
10800
10801 static uint64_t
10802 i40e_read_systime_cyclecounter(struct rte_eth_dev *dev)
10803 {
10804         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10805         uint64_t systim_cycles;
10806
10807         systim_cycles = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_L);
10808         systim_cycles |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TIME_H)
10809                         << 32;
10810
10811         return systim_cycles;
10812 }
10813
10814 static uint64_t
10815 i40e_read_rx_tstamp_cyclecounter(struct rte_eth_dev *dev, uint8_t index)
10816 {
10817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10818         uint64_t rx_tstamp;
10819
10820         rx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_L(index));
10821         rx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(index))
10822                         << 32;
10823
10824         return rx_tstamp;
10825 }
10826
10827 static uint64_t
10828 i40e_read_tx_tstamp_cyclecounter(struct rte_eth_dev *dev)
10829 {
10830         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10831         uint64_t tx_tstamp;
10832
10833         tx_tstamp = (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_L);
10834         tx_tstamp |= (uint64_t)I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H)
10835                         << 32;
10836
10837         return tx_tstamp;
10838 }
10839
10840 static void
10841 i40e_start_timecounters(struct rte_eth_dev *dev)
10842 {
10843         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10844         struct i40e_adapter *adapter = dev->data->dev_private;
10845         struct rte_eth_link link;
10846         uint32_t tsync_inc_l;
10847         uint32_t tsync_inc_h;
10848
10849         /* Get current link speed. */
10850         i40e_dev_link_update(dev, 1);
10851         rte_eth_linkstatus_get(dev, &link);
10852
10853         switch (link.link_speed) {
10854         case ETH_SPEED_NUM_40G:
10855         case ETH_SPEED_NUM_25G:
10856                 tsync_inc_l = I40E_PTP_40GB_INCVAL & 0xFFFFFFFF;
10857                 tsync_inc_h = I40E_PTP_40GB_INCVAL >> 32;
10858                 break;
10859         case ETH_SPEED_NUM_10G:
10860                 tsync_inc_l = I40E_PTP_10GB_INCVAL & 0xFFFFFFFF;
10861                 tsync_inc_h = I40E_PTP_10GB_INCVAL >> 32;
10862                 break;
10863         case ETH_SPEED_NUM_1G:
10864                 tsync_inc_l = I40E_PTP_1GB_INCVAL & 0xFFFFFFFF;
10865                 tsync_inc_h = I40E_PTP_1GB_INCVAL >> 32;
10866                 break;
10867         default:
10868                 tsync_inc_l = 0x0;
10869                 tsync_inc_h = 0x0;
10870         }
10871
10872         /* Set the timesync increment value. */
10873         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, tsync_inc_l);
10874         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, tsync_inc_h);
10875
10876         memset(&adapter->systime_tc, 0, sizeof(struct rte_timecounter));
10877         memset(&adapter->rx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10878         memset(&adapter->tx_tstamp_tc, 0, sizeof(struct rte_timecounter));
10879
10880         adapter->systime_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10881         adapter->systime_tc.cc_shift = 0;
10882         adapter->systime_tc.nsec_mask = 0;
10883
10884         adapter->rx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10885         adapter->rx_tstamp_tc.cc_shift = 0;
10886         adapter->rx_tstamp_tc.nsec_mask = 0;
10887
10888         adapter->tx_tstamp_tc.cc_mask = I40E_CYCLECOUNTER_MASK;
10889         adapter->tx_tstamp_tc.cc_shift = 0;
10890         adapter->tx_tstamp_tc.nsec_mask = 0;
10891 }
10892
10893 static int
10894 i40e_timesync_adjust_time(struct rte_eth_dev *dev, int64_t delta)
10895 {
10896         struct i40e_adapter *adapter = dev->data->dev_private;
10897
10898         adapter->systime_tc.nsec += delta;
10899         adapter->rx_tstamp_tc.nsec += delta;
10900         adapter->tx_tstamp_tc.nsec += delta;
10901
10902         return 0;
10903 }
10904
10905 static int
10906 i40e_timesync_write_time(struct rte_eth_dev *dev, const struct timespec *ts)
10907 {
10908         uint64_t ns;
10909         struct i40e_adapter *adapter = dev->data->dev_private;
10910
10911         ns = rte_timespec_to_ns(ts);
10912
10913         /* Set the timecounters to a new value. */
10914         adapter->systime_tc.nsec = ns;
10915         adapter->rx_tstamp_tc.nsec = ns;
10916         adapter->tx_tstamp_tc.nsec = ns;
10917
10918         return 0;
10919 }
10920
10921 static int
10922 i40e_timesync_read_time(struct rte_eth_dev *dev, struct timespec *ts)
10923 {
10924         uint64_t ns, systime_cycles;
10925         struct i40e_adapter *adapter = dev->data->dev_private;
10926
10927         systime_cycles = i40e_read_systime_cyclecounter(dev);
10928         ns = rte_timecounter_update(&adapter->systime_tc, systime_cycles);
10929         *ts = rte_ns_to_timespec(ns);
10930
10931         return 0;
10932 }
10933
10934 static int
10935 i40e_timesync_enable(struct rte_eth_dev *dev)
10936 {
10937         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10938         uint32_t tsync_ctl_l;
10939         uint32_t tsync_ctl_h;
10940
10941         /* Stop the timesync system time. */
10942         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10943         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10944         /* Reset the timesync system time value. */
10945         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_L, 0x0);
10946         I40E_WRITE_REG(hw, I40E_PRTTSYN_TIME_H, 0x0);
10947
10948         i40e_start_timecounters(dev);
10949
10950         /* Clear timesync registers. */
10951         I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
10952         I40E_READ_REG(hw, I40E_PRTTSYN_TXTIME_H);
10953         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(0));
10954         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(1));
10955         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(2));
10956         I40E_READ_REG(hw, I40E_PRTTSYN_RXTIME_H(3));
10957
10958         /* Enable timestamping of PTP packets. */
10959         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10960         tsync_ctl_l |= I40E_PRTTSYN_TSYNENA;
10961
10962         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10963         tsync_ctl_h |= I40E_PRTTSYN_TSYNENA;
10964         tsync_ctl_h |= I40E_PRTTSYN_TSYNTYPE;
10965
10966         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10967         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10968
10969         return 0;
10970 }
10971
10972 static int
10973 i40e_timesync_disable(struct rte_eth_dev *dev)
10974 {
10975         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
10976         uint32_t tsync_ctl_l;
10977         uint32_t tsync_ctl_h;
10978
10979         /* Disable timestamping of transmitted PTP packets. */
10980         tsync_ctl_l = I40E_READ_REG(hw, I40E_PRTTSYN_CTL0);
10981         tsync_ctl_l &= ~I40E_PRTTSYN_TSYNENA;
10982
10983         tsync_ctl_h = I40E_READ_REG(hw, I40E_PRTTSYN_CTL1);
10984         tsync_ctl_h &= ~I40E_PRTTSYN_TSYNENA;
10985
10986         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL0, tsync_ctl_l);
10987         I40E_WRITE_REG(hw, I40E_PRTTSYN_CTL1, tsync_ctl_h);
10988
10989         /* Reset the timesync increment value. */
10990         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_L, 0x0);
10991         I40E_WRITE_REG(hw, I40E_PRTTSYN_INC_H, 0x0);
10992
10993         return 0;
10994 }
10995
10996 static int
10997 i40e_timesync_read_rx_timestamp(struct rte_eth_dev *dev,
10998                                 struct timespec *timestamp, uint32_t flags)
10999 {
11000         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11001         struct i40e_adapter *adapter = dev->data->dev_private;
11002         uint32_t sync_status;
11003         uint32_t index = flags & 0x03;
11004         uint64_t rx_tstamp_cycles;
11005         uint64_t ns;
11006
11007         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_1);
11008         if ((sync_status & (1 << index)) == 0)
11009                 return -EINVAL;
11010
11011         rx_tstamp_cycles = i40e_read_rx_tstamp_cyclecounter(dev, index);
11012         ns = rte_timecounter_update(&adapter->rx_tstamp_tc, rx_tstamp_cycles);
11013         *timestamp = rte_ns_to_timespec(ns);
11014
11015         return 0;
11016 }
11017
11018 static int
11019 i40e_timesync_read_tx_timestamp(struct rte_eth_dev *dev,
11020                                 struct timespec *timestamp)
11021 {
11022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11023         struct i40e_adapter *adapter = dev->data->dev_private;
11024         uint32_t sync_status;
11025         uint64_t tx_tstamp_cycles;
11026         uint64_t ns;
11027
11028         sync_status = I40E_READ_REG(hw, I40E_PRTTSYN_STAT_0);
11029         if ((sync_status & I40E_PRTTSYN_STAT_0_TXTIME_MASK) == 0)
11030                 return -EINVAL;
11031
11032         tx_tstamp_cycles = i40e_read_tx_tstamp_cyclecounter(dev);
11033         ns = rte_timecounter_update(&adapter->tx_tstamp_tc, tx_tstamp_cycles);
11034         *timestamp = rte_ns_to_timespec(ns);
11035
11036         return 0;
11037 }
11038
11039 /*
11040  * i40e_parse_dcb_configure - parse dcb configure from user
11041  * @dev: the device being configured
11042  * @dcb_cfg: pointer of the result of parse
11043  * @*tc_map: bit map of enabled traffic classes
11044  *
11045  * Returns 0 on success, negative value on failure
11046  */
11047 static int
11048 i40e_parse_dcb_configure(struct rte_eth_dev *dev,
11049                          struct i40e_dcbx_config *dcb_cfg,
11050                          uint8_t *tc_map)
11051 {
11052         struct rte_eth_dcb_rx_conf *dcb_rx_conf;
11053         uint8_t i, tc_bw, bw_lf;
11054
11055         memset(dcb_cfg, 0, sizeof(struct i40e_dcbx_config));
11056
11057         dcb_rx_conf = &dev->data->dev_conf.rx_adv_conf.dcb_rx_conf;
11058         if (dcb_rx_conf->nb_tcs > I40E_MAX_TRAFFIC_CLASS) {
11059                 PMD_INIT_LOG(ERR, "number of tc exceeds max.");
11060                 return -EINVAL;
11061         }
11062
11063         /* assume each tc has the same bw */
11064         tc_bw = I40E_MAX_PERCENT / dcb_rx_conf->nb_tcs;
11065         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11066                 dcb_cfg->etscfg.tcbwtable[i] = tc_bw;
11067         /* to ensure the sum of tcbw is equal to 100 */
11068         bw_lf = I40E_MAX_PERCENT % dcb_rx_conf->nb_tcs;
11069         for (i = 0; i < bw_lf; i++)
11070                 dcb_cfg->etscfg.tcbwtable[i]++;
11071
11072         /* assume each tc has the same Transmission Selection Algorithm */
11073         for (i = 0; i < dcb_rx_conf->nb_tcs; i++)
11074                 dcb_cfg->etscfg.tsatable[i] = I40E_IEEE_TSA_ETS;
11075
11076         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11077                 dcb_cfg->etscfg.prioritytable[i] =
11078                                 dcb_rx_conf->dcb_tc[i];
11079
11080         /* FW needs one App to configure HW */
11081         dcb_cfg->numapps = I40E_DEFAULT_DCB_APP_NUM;
11082         dcb_cfg->app[0].selector = I40E_APP_SEL_ETHTYPE;
11083         dcb_cfg->app[0].priority = I40E_DEFAULT_DCB_APP_PRIO;
11084         dcb_cfg->app[0].protocolid = I40E_APP_PROTOID_FCOE;
11085
11086         if (dcb_rx_conf->nb_tcs == 0)
11087                 *tc_map = 1; /* tc0 only */
11088         else
11089                 *tc_map = RTE_LEN2MASK(dcb_rx_conf->nb_tcs, uint8_t);
11090
11091         if (dev->data->dev_conf.dcb_capability_en & ETH_DCB_PFC_SUPPORT) {
11092                 dcb_cfg->pfc.willing = 0;
11093                 dcb_cfg->pfc.pfccap = I40E_MAX_TRAFFIC_CLASS;
11094                 dcb_cfg->pfc.pfcenable = *tc_map;
11095         }
11096         return 0;
11097 }
11098
11099
11100 static enum i40e_status_code
11101 i40e_vsi_update_queue_mapping(struct i40e_vsi *vsi,
11102                               struct i40e_aqc_vsi_properties_data *info,
11103                               uint8_t enabled_tcmap)
11104 {
11105         enum i40e_status_code ret;
11106         int i, total_tc = 0;
11107         uint16_t qpnum_per_tc, bsf, qp_idx;
11108         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(vsi);
11109         struct i40e_pf *pf = I40E_VSI_TO_PF(vsi);
11110         uint16_t used_queues;
11111
11112         ret = validate_tcmap_parameter(vsi, enabled_tcmap);
11113         if (ret != I40E_SUCCESS)
11114                 return ret;
11115
11116         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11117                 if (enabled_tcmap & (1 << i))
11118                         total_tc++;
11119         }
11120         if (total_tc == 0)
11121                 total_tc = 1;
11122         vsi->enabled_tc = enabled_tcmap;
11123
11124         /* different VSI has different queues assigned */
11125         if (vsi->type == I40E_VSI_MAIN)
11126                 used_queues = dev_data->nb_rx_queues -
11127                         pf->nb_cfg_vmdq_vsi * RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11128         else if (vsi->type == I40E_VSI_VMDQ2)
11129                 used_queues = RTE_LIBRTE_I40E_QUEUE_NUM_PER_VM;
11130         else {
11131                 PMD_INIT_LOG(ERR, "unsupported VSI type.");
11132                 return I40E_ERR_NO_AVAILABLE_VSI;
11133         }
11134
11135         qpnum_per_tc = used_queues / total_tc;
11136         /* Number of queues per enabled TC */
11137         if (qpnum_per_tc == 0) {
11138                 PMD_INIT_LOG(ERR, " number of queues is less that tcs.");
11139                 return I40E_ERR_INVALID_QP_ID;
11140         }
11141         qpnum_per_tc = RTE_MIN(i40e_align_floor(qpnum_per_tc),
11142                                 I40E_MAX_Q_PER_TC);
11143         bsf = rte_bsf32(qpnum_per_tc);
11144
11145         /**
11146          * Configure TC and queue mapping parameters, for enabled TC,
11147          * allocate qpnum_per_tc queues to this traffic. For disabled TC,
11148          * default queue will serve it.
11149          */
11150         qp_idx = 0;
11151         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11152                 if (vsi->enabled_tc & (1 << i)) {
11153                         info->tc_mapping[i] = rte_cpu_to_le_16((qp_idx <<
11154                                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
11155                                 (bsf << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT));
11156                         qp_idx += qpnum_per_tc;
11157                 } else
11158                         info->tc_mapping[i] = 0;
11159         }
11160
11161         /* Associate queue number with VSI, Keep vsi->nb_qps unchanged */
11162         if (vsi->type == I40E_VSI_SRIOV) {
11163                 info->mapping_flags |=
11164                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
11165                 for (i = 0; i < vsi->nb_qps; i++)
11166                         info->queue_mapping[i] =
11167                                 rte_cpu_to_le_16(vsi->base_queue + i);
11168         } else {
11169                 info->mapping_flags |=
11170                         rte_cpu_to_le_16(I40E_AQ_VSI_QUE_MAP_CONTIG);
11171                 info->queue_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
11172         }
11173         info->valid_sections |=
11174                 rte_cpu_to_le_16(I40E_AQ_VSI_PROP_QUEUE_MAP_VALID);
11175
11176         return I40E_SUCCESS;
11177 }
11178
11179 /*
11180  * i40e_config_switch_comp_tc - Configure VEB tc setting for given TC map
11181  * @veb: VEB to be configured
11182  * @tc_map: enabled TC bitmap
11183  *
11184  * Returns 0 on success, negative value on failure
11185  */
11186 static enum i40e_status_code
11187 i40e_config_switch_comp_tc(struct i40e_veb *veb, uint8_t tc_map)
11188 {
11189         struct i40e_aqc_configure_switching_comp_bw_config_data veb_bw;
11190         struct i40e_aqc_query_switching_comp_bw_config_resp bw_query;
11191         struct i40e_aqc_query_switching_comp_ets_config_resp ets_query;
11192         struct i40e_hw *hw = I40E_VSI_TO_HW(veb->associate_vsi);
11193         enum i40e_status_code ret = I40E_SUCCESS;
11194         int i;
11195         uint32_t bw_max;
11196
11197         /* Check if enabled_tc is same as existing or new TCs */
11198         if (veb->enabled_tc == tc_map)
11199                 return ret;
11200
11201         /* configure tc bandwidth */
11202         memset(&veb_bw, 0, sizeof(veb_bw));
11203         veb_bw.tc_valid_bits = tc_map;
11204         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11205         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11206                 if (tc_map & BIT_ULL(i))
11207                         veb_bw.tc_bw_share_credits[i] = 1;
11208         }
11209         ret = i40e_aq_config_switch_comp_bw_config(hw, veb->seid,
11210                                                    &veb_bw, NULL);
11211         if (ret) {
11212                 PMD_INIT_LOG(ERR,
11213                         "AQ command Config switch_comp BW allocation per TC failed = %d",
11214                         hw->aq.asq_last_status);
11215                 return ret;
11216         }
11217
11218         memset(&ets_query, 0, sizeof(ets_query));
11219         ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
11220                                                    &ets_query, NULL);
11221         if (ret != I40E_SUCCESS) {
11222                 PMD_DRV_LOG(ERR,
11223                         "Failed to get switch_comp ETS configuration %u",
11224                         hw->aq.asq_last_status);
11225                 return ret;
11226         }
11227         memset(&bw_query, 0, sizeof(bw_query));
11228         ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
11229                                                   &bw_query, NULL);
11230         if (ret != I40E_SUCCESS) {
11231                 PMD_DRV_LOG(ERR,
11232                         "Failed to get switch_comp bandwidth configuration %u",
11233                         hw->aq.asq_last_status);
11234                 return ret;
11235         }
11236
11237         /* store and print out BW info */
11238         veb->bw_info.bw_limit = rte_le_to_cpu_16(ets_query.port_bw_limit);
11239         veb->bw_info.bw_max = ets_query.tc_bw_max;
11240         PMD_DRV_LOG(DEBUG, "switch_comp bw limit:%u", veb->bw_info.bw_limit);
11241         PMD_DRV_LOG(DEBUG, "switch_comp max_bw:%u", veb->bw_info.bw_max);
11242         bw_max = rte_le_to_cpu_16(bw_query.tc_bw_max[0]) |
11243                     (rte_le_to_cpu_16(bw_query.tc_bw_max[1]) <<
11244                      I40E_16_BIT_WIDTH);
11245         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11246                 veb->bw_info.bw_ets_share_credits[i] =
11247                                 bw_query.tc_bw_share_credits[i];
11248                 veb->bw_info.bw_ets_credits[i] =
11249                                 rte_le_to_cpu_16(bw_query.tc_bw_limits[i]);
11250                 /* 4 bits per TC, 4th bit is reserved */
11251                 veb->bw_info.bw_ets_max[i] =
11252                         (uint8_t)((bw_max >> (i * I40E_4_BIT_WIDTH)) &
11253                                   RTE_LEN2MASK(3, uint8_t));
11254                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:share credits %u", i,
11255                             veb->bw_info.bw_ets_share_credits[i]);
11256                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u:credits %u", i,
11257                             veb->bw_info.bw_ets_credits[i]);
11258                 PMD_DRV_LOG(DEBUG, "\tVEB TC%u: max credits: %u", i,
11259                             veb->bw_info.bw_ets_max[i]);
11260         }
11261
11262         veb->enabled_tc = tc_map;
11263
11264         return ret;
11265 }
11266
11267
11268 /*
11269  * i40e_vsi_config_tc - Configure VSI tc setting for given TC map
11270  * @vsi: VSI to be configured
11271  * @tc_map: enabled TC bitmap
11272  *
11273  * Returns 0 on success, negative value on failure
11274  */
11275 static enum i40e_status_code
11276 i40e_vsi_config_tc(struct i40e_vsi *vsi, uint8_t tc_map)
11277 {
11278         struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
11279         struct i40e_vsi_context ctxt;
11280         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
11281         enum i40e_status_code ret = I40E_SUCCESS;
11282         int i;
11283
11284         /* Check if enabled_tc is same as existing or new TCs */
11285         if (vsi->enabled_tc == tc_map)
11286                 return ret;
11287
11288         /* configure tc bandwidth */
11289         memset(&bw_data, 0, sizeof(bw_data));
11290         bw_data.tc_valid_bits = tc_map;
11291         /* Enable ETS TCs with equal BW Share for now across all VSIs */
11292         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11293                 if (tc_map & BIT_ULL(i))
11294                         bw_data.tc_bw_credits[i] = 1;
11295         }
11296         ret = i40e_aq_config_vsi_tc_bw(hw, vsi->seid, &bw_data, NULL);
11297         if (ret) {
11298                 PMD_INIT_LOG(ERR,
11299                         "AQ command Config VSI BW allocation per TC failed = %d",
11300                         hw->aq.asq_last_status);
11301                 goto out;
11302         }
11303         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
11304                 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
11305
11306         /* Update Queue Pairs Mapping for currently enabled UPs */
11307         ctxt.seid = vsi->seid;
11308         ctxt.pf_num = hw->pf_id;
11309         ctxt.vf_num = 0;
11310         ctxt.uplink_seid = vsi->uplink_seid;
11311         ctxt.info = vsi->info;
11312         i40e_get_cap(hw);
11313         ret = i40e_vsi_update_queue_mapping(vsi, &ctxt.info, tc_map);
11314         if (ret)
11315                 goto out;
11316
11317         /* Update the VSI after updating the VSI queue-mapping information */
11318         ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
11319         if (ret) {
11320                 PMD_INIT_LOG(ERR, "Failed to configure TC queue mapping = %d",
11321                         hw->aq.asq_last_status);
11322                 goto out;
11323         }
11324         /* update the local VSI info with updated queue map */
11325         rte_memcpy(&vsi->info.tc_mapping, &ctxt.info.tc_mapping,
11326                                         sizeof(vsi->info.tc_mapping));
11327         rte_memcpy(&vsi->info.queue_mapping,
11328                         &ctxt.info.queue_mapping,
11329                 sizeof(vsi->info.queue_mapping));
11330         vsi->info.mapping_flags = ctxt.info.mapping_flags;
11331         vsi->info.valid_sections = 0;
11332
11333         /* query and update current VSI BW information */
11334         ret = i40e_vsi_get_bw_config(vsi);
11335         if (ret) {
11336                 PMD_INIT_LOG(ERR,
11337                          "Failed updating vsi bw info, err %s aq_err %s",
11338                          i40e_stat_str(hw, ret),
11339                          i40e_aq_str(hw, hw->aq.asq_last_status));
11340                 goto out;
11341         }
11342
11343         vsi->enabled_tc = tc_map;
11344
11345 out:
11346         return ret;
11347 }
11348
11349 /*
11350  * i40e_dcb_hw_configure - program the dcb setting to hw
11351  * @pf: pf the configuration is taken on
11352  * @new_cfg: new configuration
11353  * @tc_map: enabled TC bitmap
11354  *
11355  * Returns 0 on success, negative value on failure
11356  */
11357 static enum i40e_status_code
11358 i40e_dcb_hw_configure(struct i40e_pf *pf,
11359                       struct i40e_dcbx_config *new_cfg,
11360                       uint8_t tc_map)
11361 {
11362         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
11363         struct i40e_dcbx_config *old_cfg = &hw->local_dcbx_config;
11364         struct i40e_vsi *main_vsi = pf->main_vsi;
11365         struct i40e_vsi_list *vsi_list;
11366         enum i40e_status_code ret;
11367         int i;
11368         uint32_t val;
11369
11370         /* Use the FW API if FW > v4.4*/
11371         if (!(((hw->aq.fw_maj_ver == 4) && (hw->aq.fw_min_ver >= 4)) ||
11372               (hw->aq.fw_maj_ver >= 5))) {
11373                 PMD_INIT_LOG(ERR,
11374                         "FW < v4.4, can not use FW LLDP API to configure DCB");
11375                 return I40E_ERR_FIRMWARE_API_VERSION;
11376         }
11377
11378         /* Check if need reconfiguration */
11379         if (!memcmp(new_cfg, old_cfg, sizeof(struct i40e_dcbx_config))) {
11380                 PMD_INIT_LOG(ERR, "No Change in DCB Config required.");
11381                 return I40E_SUCCESS;
11382         }
11383
11384         /* Copy the new config to the current config */
11385         *old_cfg = *new_cfg;
11386         old_cfg->etsrec = old_cfg->etscfg;
11387         ret = i40e_set_dcb_config(hw);
11388         if (ret) {
11389                 PMD_INIT_LOG(ERR, "Set DCB Config failed, err %s aq_err %s",
11390                          i40e_stat_str(hw, ret),
11391                          i40e_aq_str(hw, hw->aq.asq_last_status));
11392                 return ret;
11393         }
11394         /* set receive Arbiter to RR mode and ETS scheme by default */
11395         for (i = 0; i <= I40E_PRTDCB_RETSTCC_MAX_INDEX; i++) {
11396                 val = I40E_READ_REG(hw, I40E_PRTDCB_RETSTCC(i));
11397                 val &= ~(I40E_PRTDCB_RETSTCC_BWSHARE_MASK     |
11398                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK |
11399                          I40E_PRTDCB_RETSTCC_ETSTC_SHIFT);
11400                 val |= ((uint32_t)old_cfg->etscfg.tcbwtable[i] <<
11401                         I40E_PRTDCB_RETSTCC_BWSHARE_SHIFT) &
11402                          I40E_PRTDCB_RETSTCC_BWSHARE_MASK;
11403                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_UPINTC_MODE_SHIFT) &
11404                          I40E_PRTDCB_RETSTCC_UPINTC_MODE_MASK;
11405                 val |= ((uint32_t)1 << I40E_PRTDCB_RETSTCC_ETSTC_SHIFT) &
11406                          I40E_PRTDCB_RETSTCC_ETSTC_MASK;
11407                 I40E_WRITE_REG(hw, I40E_PRTDCB_RETSTCC(i), val);
11408         }
11409         /* get local mib to check whether it is configured correctly */
11410         /* IEEE mode */
11411         hw->local_dcbx_config.dcbx_mode = I40E_DCBX_MODE_IEEE;
11412         /* Get Local DCB Config */
11413         i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_LOCAL, 0,
11414                                      &hw->local_dcbx_config);
11415
11416         /* if Veb is created, need to update TC of it at first */
11417         if (main_vsi->veb) {
11418                 ret = i40e_config_switch_comp_tc(main_vsi->veb, tc_map);
11419                 if (ret)
11420                         PMD_INIT_LOG(WARNING,
11421                                  "Failed configuring TC for VEB seid=%d",
11422                                  main_vsi->veb->seid);
11423         }
11424         /* Update each VSI */
11425         i40e_vsi_config_tc(main_vsi, tc_map);
11426         if (main_vsi->veb) {
11427                 TAILQ_FOREACH(vsi_list, &main_vsi->veb->head, list) {
11428                         /* Beside main VSI and VMDQ VSIs, only enable default
11429                          * TC for other VSIs
11430                          */
11431                         if (vsi_list->vsi->type == I40E_VSI_VMDQ2)
11432                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11433                                                          tc_map);
11434                         else
11435                                 ret = i40e_vsi_config_tc(vsi_list->vsi,
11436                                                          I40E_DEFAULT_TCMAP);
11437                         if (ret)
11438                                 PMD_INIT_LOG(WARNING,
11439                                         "Failed configuring TC for VSI seid=%d",
11440                                         vsi_list->vsi->seid);
11441                         /* continue */
11442                 }
11443         }
11444         return I40E_SUCCESS;
11445 }
11446
11447 /*
11448  * i40e_dcb_init_configure - initial dcb config
11449  * @dev: device being configured
11450  * @sw_dcb: indicate whether dcb is sw configured or hw offload
11451  *
11452  * Returns 0 on success, negative value on failure
11453  */
11454 int
11455 i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb)
11456 {
11457         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11458         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11459         int i, ret = 0;
11460
11461         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11462                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11463                 return -ENOTSUP;
11464         }
11465
11466         /* DCB initialization:
11467          * Update DCB configuration from the Firmware and configure
11468          * LLDP MIB change event.
11469          */
11470         if (sw_dcb == TRUE) {
11471                 if (i40e_need_stop_lldp(dev)) {
11472                         ret = i40e_aq_stop_lldp(hw, TRUE, NULL);
11473                         if (ret != I40E_SUCCESS)
11474                                 PMD_INIT_LOG(DEBUG, "Failed to stop lldp");
11475                 }
11476
11477                 ret = i40e_init_dcb(hw);
11478                 /* If lldp agent is stopped, the return value from
11479                  * i40e_init_dcb we expect is failure with I40E_AQ_RC_EPERM
11480                  * adminq status. Otherwise, it should return success.
11481                  */
11482                 if ((ret == I40E_SUCCESS) || (ret != I40E_SUCCESS &&
11483                     hw->aq.asq_last_status == I40E_AQ_RC_EPERM)) {
11484                         memset(&hw->local_dcbx_config, 0,
11485                                 sizeof(struct i40e_dcbx_config));
11486                         /* set dcb default configuration */
11487                         hw->local_dcbx_config.etscfg.willing = 0;
11488                         hw->local_dcbx_config.etscfg.maxtcs = 0;
11489                         hw->local_dcbx_config.etscfg.tcbwtable[0] = 100;
11490                         hw->local_dcbx_config.etscfg.tsatable[0] =
11491                                                 I40E_IEEE_TSA_ETS;
11492                         /* all UPs mapping to TC0 */
11493                         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11494                                 hw->local_dcbx_config.etscfg.prioritytable[i] = 0;
11495                         hw->local_dcbx_config.etsrec =
11496                                 hw->local_dcbx_config.etscfg;
11497                         hw->local_dcbx_config.pfc.willing = 0;
11498                         hw->local_dcbx_config.pfc.pfccap =
11499                                                 I40E_MAX_TRAFFIC_CLASS;
11500                         /* FW needs one App to configure HW */
11501                         hw->local_dcbx_config.numapps = 1;
11502                         hw->local_dcbx_config.app[0].selector =
11503                                                 I40E_APP_SEL_ETHTYPE;
11504                         hw->local_dcbx_config.app[0].priority = 3;
11505                         hw->local_dcbx_config.app[0].protocolid =
11506                                                 I40E_APP_PROTOID_FCOE;
11507                         ret = i40e_set_dcb_config(hw);
11508                         if (ret) {
11509                                 PMD_INIT_LOG(ERR,
11510                                         "default dcb config fails. err = %d, aq_err = %d.",
11511                                         ret, hw->aq.asq_last_status);
11512                                 return -ENOSYS;
11513                         }
11514                 } else {
11515                         PMD_INIT_LOG(ERR,
11516                                 "DCB initialization in FW fails, err = %d, aq_err = %d.",
11517                                 ret, hw->aq.asq_last_status);
11518                         return -ENOTSUP;
11519                 }
11520         } else {
11521                 ret = i40e_aq_start_lldp(hw, NULL);
11522                 if (ret != I40E_SUCCESS)
11523                         PMD_INIT_LOG(DEBUG, "Failed to start lldp");
11524
11525                 ret = i40e_init_dcb(hw);
11526                 if (!ret) {
11527                         if (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED) {
11528                                 PMD_INIT_LOG(ERR,
11529                                         "HW doesn't support DCBX offload.");
11530                                 return -ENOTSUP;
11531                         }
11532                 } else {
11533                         PMD_INIT_LOG(ERR,
11534                                 "DCBX configuration failed, err = %d, aq_err = %d.",
11535                                 ret, hw->aq.asq_last_status);
11536                         return -ENOTSUP;
11537                 }
11538         }
11539         return 0;
11540 }
11541
11542 /*
11543  * i40e_dcb_setup - setup dcb related config
11544  * @dev: device being configured
11545  *
11546  * Returns 0 on success, negative value on failure
11547  */
11548 static int
11549 i40e_dcb_setup(struct rte_eth_dev *dev)
11550 {
11551         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11552         struct i40e_dcbx_config dcb_cfg;
11553         uint8_t tc_map = 0;
11554         int ret = 0;
11555
11556         if ((pf->flags & I40E_FLAG_DCB) == 0) {
11557                 PMD_INIT_LOG(ERR, "HW doesn't support DCB");
11558                 return -ENOTSUP;
11559         }
11560
11561         if (pf->vf_num != 0)
11562                 PMD_INIT_LOG(DEBUG, " DCB only works on pf and vmdq vsis.");
11563
11564         ret = i40e_parse_dcb_configure(dev, &dcb_cfg, &tc_map);
11565         if (ret) {
11566                 PMD_INIT_LOG(ERR, "invalid dcb config");
11567                 return -EINVAL;
11568         }
11569         ret = i40e_dcb_hw_configure(pf, &dcb_cfg, tc_map);
11570         if (ret) {
11571                 PMD_INIT_LOG(ERR, "dcb sw configure fails");
11572                 return -ENOSYS;
11573         }
11574
11575         return 0;
11576 }
11577
11578 static int
11579 i40e_dev_get_dcb_info(struct rte_eth_dev *dev,
11580                       struct rte_eth_dcb_info *dcb_info)
11581 {
11582         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11583         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11584         struct i40e_vsi *vsi = pf->main_vsi;
11585         struct i40e_dcbx_config *dcb_cfg = &hw->local_dcbx_config;
11586         uint16_t bsf, tc_mapping;
11587         int i, j = 0;
11588
11589         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_DCB_FLAG)
11590                 dcb_info->nb_tcs = rte_bsf32(vsi->enabled_tc + 1);
11591         else
11592                 dcb_info->nb_tcs = 1;
11593         for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
11594                 dcb_info->prio_tc[i] = dcb_cfg->etscfg.prioritytable[i];
11595         for (i = 0; i < dcb_info->nb_tcs; i++)
11596                 dcb_info->tc_bws[i] = dcb_cfg->etscfg.tcbwtable[i];
11597
11598         /* get queue mapping if vmdq is disabled */
11599         if (!pf->nb_cfg_vmdq_vsi) {
11600                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11601                         if (!(vsi->enabled_tc & (1 << i)))
11602                                 continue;
11603                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11604                         dcb_info->tc_queue.tc_rxq[j][i].base =
11605                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11606                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11607                         dcb_info->tc_queue.tc_txq[j][i].base =
11608                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11609                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11610                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11611                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11612                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11613                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11614                 }
11615                 return 0;
11616         }
11617
11618         /* get queue mapping if vmdq is enabled */
11619         do {
11620                 vsi = pf->vmdq[j].vsi;
11621                 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
11622                         if (!(vsi->enabled_tc & (1 << i)))
11623                                 continue;
11624                         tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
11625                         dcb_info->tc_queue.tc_rxq[j][i].base =
11626                                 (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
11627                                 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
11628                         dcb_info->tc_queue.tc_txq[j][i].base =
11629                                 dcb_info->tc_queue.tc_rxq[j][i].base;
11630                         bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
11631                                 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
11632                         dcb_info->tc_queue.tc_rxq[j][i].nb_queue = 1 << bsf;
11633                         dcb_info->tc_queue.tc_txq[j][i].nb_queue =
11634                                 dcb_info->tc_queue.tc_rxq[j][i].nb_queue;
11635                 }
11636                 j++;
11637         } while (j < RTE_MIN(pf->nb_cfg_vmdq_vsi, ETH_MAX_VMDQ_POOL));
11638         return 0;
11639 }
11640
11641 static int
11642 i40e_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
11643 {
11644         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11645         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11647         uint16_t msix_intr;
11648
11649         msix_intr = intr_handle->intr_vec[queue_id];
11650         if (msix_intr == I40E_MISC_VEC_ID)
11651                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11652                                I40E_PFINT_DYN_CTL0_INTENA_MASK |
11653                                I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
11654                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11655         else
11656                 I40E_WRITE_REG(hw,
11657                                I40E_PFINT_DYN_CTLN(msix_intr -
11658                                                    I40E_RX_VEC_START),
11659                                I40E_PFINT_DYN_CTLN_INTENA_MASK |
11660                                I40E_PFINT_DYN_CTLN_CLEARPBA_MASK |
11661                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11662
11663         I40E_WRITE_FLUSH(hw);
11664         rte_intr_enable(&pci_dev->intr_handle);
11665
11666         return 0;
11667 }
11668
11669 static int
11670 i40e_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
11671 {
11672         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
11673         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
11674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11675         uint16_t msix_intr;
11676
11677         msix_intr = intr_handle->intr_vec[queue_id];
11678         if (msix_intr == I40E_MISC_VEC_ID)
11679                 I40E_WRITE_REG(hw, I40E_PFINT_DYN_CTL0,
11680                                I40E_PFINT_DYN_CTL0_ITR_INDX_MASK);
11681         else
11682                 I40E_WRITE_REG(hw,
11683                                I40E_PFINT_DYN_CTLN(msix_intr -
11684                                                    I40E_RX_VEC_START),
11685                                I40E_PFINT_DYN_CTLN_ITR_INDX_MASK);
11686         I40E_WRITE_FLUSH(hw);
11687
11688         return 0;
11689 }
11690
11691 /**
11692  * This function is used to check if the register is valid.
11693  * Below is the valid registers list for X722 only:
11694  * 0x2b800--0x2bb00
11695  * 0x38700--0x38a00
11696  * 0x3d800--0x3db00
11697  * 0x208e00--0x209000
11698  * 0x20be00--0x20c000
11699  * 0x263c00--0x264000
11700  * 0x265c00--0x266000
11701  */
11702 static inline int i40e_valid_regs(enum i40e_mac_type type, uint32_t reg_offset)
11703 {
11704         if ((type != I40E_MAC_X722) &&
11705             ((reg_offset >= 0x2b800 && reg_offset <= 0x2bb00) ||
11706              (reg_offset >= 0x38700 && reg_offset <= 0x38a00) ||
11707              (reg_offset >= 0x3d800 && reg_offset <= 0x3db00) ||
11708              (reg_offset >= 0x208e00 && reg_offset <= 0x209000) ||
11709              (reg_offset >= 0x20be00 && reg_offset <= 0x20c000) ||
11710              (reg_offset >= 0x263c00 && reg_offset <= 0x264000) ||
11711              (reg_offset >= 0x265c00 && reg_offset <= 0x266000)))
11712                 return 0;
11713         else
11714                 return 1;
11715 }
11716
11717 static int i40e_get_regs(struct rte_eth_dev *dev,
11718                          struct rte_dev_reg_info *regs)
11719 {
11720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11721         uint32_t *ptr_data = regs->data;
11722         uint32_t reg_idx, arr_idx, arr_idx2, reg_offset;
11723         const struct i40e_reg_info *reg_info;
11724
11725         if (ptr_data == NULL) {
11726                 regs->length = I40E_GLGEN_STAT_CLEAR + 4;
11727                 regs->width = sizeof(uint32_t);
11728                 return 0;
11729         }
11730
11731         /* The first few registers have to be read using AQ operations */
11732         reg_idx = 0;
11733         while (i40e_regs_adminq[reg_idx].name) {
11734                 reg_info = &i40e_regs_adminq[reg_idx++];
11735                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11736                         for (arr_idx2 = 0;
11737                                         arr_idx2 <= reg_info->count2;
11738                                         arr_idx2++) {
11739                                 reg_offset = arr_idx * reg_info->stride1 +
11740                                         arr_idx2 * reg_info->stride2;
11741                                 reg_offset += reg_info->base_addr;
11742                                 ptr_data[reg_offset >> 2] =
11743                                         i40e_read_rx_ctl(hw, reg_offset);
11744                         }
11745         }
11746
11747         /* The remaining registers can be read using primitives */
11748         reg_idx = 0;
11749         while (i40e_regs_others[reg_idx].name) {
11750                 reg_info = &i40e_regs_others[reg_idx++];
11751                 for (arr_idx = 0; arr_idx <= reg_info->count1; arr_idx++)
11752                         for (arr_idx2 = 0;
11753                                         arr_idx2 <= reg_info->count2;
11754                                         arr_idx2++) {
11755                                 reg_offset = arr_idx * reg_info->stride1 +
11756                                         arr_idx2 * reg_info->stride2;
11757                                 reg_offset += reg_info->base_addr;
11758                                 if (!i40e_valid_regs(hw->mac.type, reg_offset))
11759                                         ptr_data[reg_offset >> 2] = 0;
11760                                 else
11761                                         ptr_data[reg_offset >> 2] =
11762                                                 I40E_READ_REG(hw, reg_offset);
11763                         }
11764         }
11765
11766         return 0;
11767 }
11768
11769 static int i40e_get_eeprom_length(struct rte_eth_dev *dev)
11770 {
11771         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11772
11773         /* Convert word count to byte count */
11774         return hw->nvm.sr_size << 1;
11775 }
11776
11777 static int i40e_get_eeprom(struct rte_eth_dev *dev,
11778                            struct rte_dev_eeprom_info *eeprom)
11779 {
11780         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11781         uint16_t *data = eeprom->data;
11782         uint16_t offset, length, cnt_words;
11783         int ret_code;
11784
11785         offset = eeprom->offset >> 1;
11786         length = eeprom->length >> 1;
11787         cnt_words = length;
11788
11789         if (offset > hw->nvm.sr_size ||
11790                 offset + length > hw->nvm.sr_size) {
11791                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
11792                 return -EINVAL;
11793         }
11794
11795         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
11796
11797         ret_code = i40e_read_nvm_buffer(hw, offset, &cnt_words, data);
11798         if (ret_code != I40E_SUCCESS || cnt_words != length) {
11799                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
11800                 return -EIO;
11801         }
11802
11803         return 0;
11804 }
11805
11806 static int i40e_get_module_info(struct rte_eth_dev *dev,
11807                                 struct rte_eth_dev_module_info *modinfo)
11808 {
11809         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11810         uint32_t sff8472_comp = 0;
11811         uint32_t sff8472_swap = 0;
11812         uint32_t sff8636_rev = 0;
11813         i40e_status status;
11814         uint32_t type = 0;
11815
11816         /* Check if firmware supports reading module EEPROM. */
11817         if (!(hw->flags & I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE)) {
11818                 PMD_DRV_LOG(ERR,
11819                             "Module EEPROM memory read not supported. "
11820                             "Please update the NVM image.\n");
11821                 return -EINVAL;
11822         }
11823
11824         status = i40e_update_link_info(hw);
11825         if (status)
11826                 return -EIO;
11827
11828         if (hw->phy.link_info.phy_type == I40E_PHY_TYPE_EMPTY) {
11829                 PMD_DRV_LOG(ERR,
11830                             "Cannot read module EEPROM memory. "
11831                             "No module connected.\n");
11832                 return -EINVAL;
11833         }
11834
11835         type = hw->phy.link_info.module_type[0];
11836
11837         switch (type) {
11838         case I40E_MODULE_TYPE_SFP:
11839                 status = i40e_aq_get_phy_register(hw,
11840                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11841                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11842                                 I40E_MODULE_SFF_8472_COMP,
11843                                 &sff8472_comp, NULL);
11844                 if (status)
11845                         return -EIO;
11846
11847                 status = i40e_aq_get_phy_register(hw,
11848                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11849                                 I40E_I2C_EEPROM_DEV_ADDR, 1,
11850                                 I40E_MODULE_SFF_8472_SWAP,
11851                                 &sff8472_swap, NULL);
11852                 if (status)
11853                         return -EIO;
11854
11855                 /* Check if the module requires address swap to access
11856                  * the other EEPROM memory page.
11857                  */
11858                 if (sff8472_swap & I40E_MODULE_SFF_ADDR_MODE) {
11859                         PMD_DRV_LOG(WARNING,
11860                                     "Module address swap to access "
11861                                     "page 0xA2 is not supported.\n");
11862                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11863                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11864                 } else if (sff8472_comp == 0x00) {
11865                         /* Module is not SFF-8472 compliant */
11866                         modinfo->type = RTE_ETH_MODULE_SFF_8079;
11867                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8079_LEN;
11868                 } else {
11869                         modinfo->type = RTE_ETH_MODULE_SFF_8472;
11870                         modinfo->eeprom_len = RTE_ETH_MODULE_SFF_8472_LEN;
11871                 }
11872                 break;
11873         case I40E_MODULE_TYPE_QSFP_PLUS:
11874                 /* Read from memory page 0. */
11875                 status = i40e_aq_get_phy_register(hw,
11876                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11877                                 0, 1,
11878                                 I40E_MODULE_REVISION_ADDR,
11879                                 &sff8636_rev, NULL);
11880                 if (status)
11881                         return -EIO;
11882                 /* Determine revision compliance byte */
11883                 if (sff8636_rev > 0x02) {
11884                         /* Module is SFF-8636 compliant */
11885                         modinfo->type = RTE_ETH_MODULE_SFF_8636;
11886                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11887                 } else {
11888                         modinfo->type = RTE_ETH_MODULE_SFF_8436;
11889                         modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11890                 }
11891                 break;
11892         case I40E_MODULE_TYPE_QSFP28:
11893                 modinfo->type = RTE_ETH_MODULE_SFF_8636;
11894                 modinfo->eeprom_len = I40E_MODULE_QSFP_MAX_LEN;
11895                 break;
11896         default:
11897                 PMD_DRV_LOG(ERR, "Module type unrecognized\n");
11898                 return -EINVAL;
11899         }
11900         return 0;
11901 }
11902
11903 static int i40e_get_module_eeprom(struct rte_eth_dev *dev,
11904                                   struct rte_dev_eeprom_info *info)
11905 {
11906         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11907         bool is_sfp = false;
11908         i40e_status status;
11909         uint8_t *data;
11910         uint32_t value = 0;
11911         uint32_t i;
11912
11913         if (!info || !info->length || !info->data)
11914                 return -EINVAL;
11915
11916         if (hw->phy.link_info.module_type[0] == I40E_MODULE_TYPE_SFP)
11917                 is_sfp = true;
11918
11919         data = info->data;
11920         for (i = 0; i < info->length; i++) {
11921                 u32 offset = i + info->offset;
11922                 u32 addr = is_sfp ? I40E_I2C_EEPROM_DEV_ADDR : 0;
11923
11924                 /* Check if we need to access the other memory page */
11925                 if (is_sfp) {
11926                         if (offset >= RTE_ETH_MODULE_SFF_8079_LEN) {
11927                                 offset -= RTE_ETH_MODULE_SFF_8079_LEN;
11928                                 addr = I40E_I2C_EEPROM_DEV_ADDR2;
11929                         }
11930                 } else {
11931                         while (offset >= RTE_ETH_MODULE_SFF_8436_LEN) {
11932                                 /* Compute memory page number and offset. */
11933                                 offset -= RTE_ETH_MODULE_SFF_8436_LEN / 2;
11934                                 addr++;
11935                         }
11936                 }
11937                 status = i40e_aq_get_phy_register(hw,
11938                                 I40E_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE,
11939                                 addr, offset, 1, &value, NULL);
11940                 if (status)
11941                         return -EIO;
11942                 data[i] = (uint8_t)value;
11943         }
11944         return 0;
11945 }
11946
11947 static int i40e_set_default_mac_addr(struct rte_eth_dev *dev,
11948                                      struct rte_ether_addr *mac_addr)
11949 {
11950         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
11951         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
11952         struct i40e_vsi *vsi = pf->main_vsi;
11953         struct i40e_mac_filter_info mac_filter;
11954         struct i40e_mac_filter *f;
11955         int ret;
11956
11957         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
11958                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
11959                 return -EINVAL;
11960         }
11961
11962         TAILQ_FOREACH(f, &vsi->mac_list, next) {
11963                 if (rte_is_same_ether_addr(&pf->dev_addr,
11964                                                 &f->mac_info.mac_addr))
11965                         break;
11966         }
11967
11968         if (f == NULL) {
11969                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
11970                 return -EIO;
11971         }
11972
11973         mac_filter = f->mac_info;
11974         ret = i40e_vsi_delete_mac(vsi, &mac_filter.mac_addr);
11975         if (ret != I40E_SUCCESS) {
11976                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
11977                 return -EIO;
11978         }
11979         memcpy(&mac_filter.mac_addr, mac_addr, ETH_ADDR_LEN);
11980         ret = i40e_vsi_add_mac(vsi, &mac_filter);
11981         if (ret != I40E_SUCCESS) {
11982                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
11983                 return -EIO;
11984         }
11985         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
11986
11987         ret = i40e_aq_mac_address_write(hw, I40E_AQC_WRITE_TYPE_LAA_WOL,
11988                                         mac_addr->addr_bytes, NULL);
11989         if (ret != I40E_SUCCESS) {
11990                 PMD_DRV_LOG(ERR, "Failed to change mac");
11991                 return -EIO;
11992         }
11993
11994         return 0;
11995 }
11996
11997 static int
11998 i40e_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
11999 {
12000         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12001         struct rte_eth_dev_data *dev_data = pf->dev_data;
12002         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
12003         int ret = 0;
12004
12005         /* check if mtu is within the allowed range */
12006         if (mtu < RTE_ETHER_MIN_MTU || frame_size > I40E_FRAME_SIZE_MAX)
12007                 return -EINVAL;
12008
12009         /* mtu setting is forbidden if port is start */
12010         if (dev_data->dev_started) {
12011                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
12012                             dev_data->port_id);
12013                 return -EBUSY;
12014         }
12015
12016         if (frame_size > RTE_ETHER_MAX_LEN)
12017                 dev_data->dev_conf.rxmode.offloads |=
12018                         DEV_RX_OFFLOAD_JUMBO_FRAME;
12019         else
12020                 dev_data->dev_conf.rxmode.offloads &=
12021                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
12022
12023         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
12024
12025         return ret;
12026 }
12027
12028 /* Restore ethertype filter */
12029 static void
12030 i40e_ethertype_filter_restore(struct i40e_pf *pf)
12031 {
12032         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12033         struct i40e_ethertype_filter_list
12034                 *ethertype_list = &pf->ethertype.ethertype_list;
12035         struct i40e_ethertype_filter *f;
12036         struct i40e_control_filter_stats stats;
12037         uint16_t flags;
12038
12039         TAILQ_FOREACH(f, ethertype_list, rules) {
12040                 flags = 0;
12041                 if (!(f->flags & RTE_ETHTYPE_FLAGS_MAC))
12042                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
12043                 if (f->flags & RTE_ETHTYPE_FLAGS_DROP)
12044                         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
12045                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
12046
12047                 memset(&stats, 0, sizeof(stats));
12048                 i40e_aq_add_rem_control_packet_filter(hw,
12049                                             f->input.mac_addr.addr_bytes,
12050                                             f->input.ether_type,
12051                                             flags, pf->main_vsi->seid,
12052                                             f->queue, 1, &stats, NULL);
12053         }
12054         PMD_DRV_LOG(INFO, "Ethertype filter:"
12055                     " mac_etype_used = %u, etype_used = %u,"
12056                     " mac_etype_free = %u, etype_free = %u",
12057                     stats.mac_etype_used, stats.etype_used,
12058                     stats.mac_etype_free, stats.etype_free);
12059 }
12060
12061 /* Restore tunnel filter */
12062 static void
12063 i40e_tunnel_filter_restore(struct i40e_pf *pf)
12064 {
12065         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12066         struct i40e_vsi *vsi;
12067         struct i40e_pf_vf *vf;
12068         struct i40e_tunnel_filter_list
12069                 *tunnel_list = &pf->tunnel.tunnel_list;
12070         struct i40e_tunnel_filter *f;
12071         struct i40e_aqc_cloud_filters_element_bb cld_filter;
12072         bool big_buffer = 0;
12073
12074         TAILQ_FOREACH(f, tunnel_list, rules) {
12075                 if (!f->is_to_vf)
12076                         vsi = pf->main_vsi;
12077                 else {
12078                         vf = &pf->vfs[f->vf_id];
12079                         vsi = vf->vsi;
12080                 }
12081                 memset(&cld_filter, 0, sizeof(cld_filter));
12082                 rte_ether_addr_copy((struct rte_ether_addr *)
12083                                 &f->input.outer_mac,
12084                         (struct rte_ether_addr *)&cld_filter.element.outer_mac);
12085                 rte_ether_addr_copy((struct rte_ether_addr *)
12086                                 &f->input.inner_mac,
12087                         (struct rte_ether_addr *)&cld_filter.element.inner_mac);
12088                 cld_filter.element.inner_vlan = f->input.inner_vlan;
12089                 cld_filter.element.flags = f->input.flags;
12090                 cld_filter.element.tenant_id = f->input.tenant_id;
12091                 cld_filter.element.queue_number = f->queue;
12092                 rte_memcpy(cld_filter.general_fields,
12093                            f->input.general_fields,
12094                            sizeof(f->input.general_fields));
12095
12096                 if (((f->input.flags &
12097                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
12098                      I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
12099                     ((f->input.flags &
12100                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
12101                      I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
12102                     ((f->input.flags &
12103                      I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
12104                      I40E_AQC_ADD_CLOUD_FILTER_0X10))
12105                         big_buffer = 1;
12106
12107                 if (big_buffer)
12108                         i40e_aq_add_cloud_filters_bb(hw,
12109                                         vsi->seid, &cld_filter, 1);
12110                 else
12111                         i40e_aq_add_cloud_filters(hw, vsi->seid,
12112                                                   &cld_filter.element, 1);
12113         }
12114 }
12115
12116 /* Restore rss filter */
12117 static inline void
12118 i40e_rss_filter_restore(struct i40e_pf *pf)
12119 {
12120         struct i40e_rte_flow_rss_conf *conf =
12121                                         &pf->rss_info;
12122         if (conf->conf.queue_num)
12123                 i40e_config_rss_filter(pf, conf, TRUE);
12124 }
12125
12126 static void
12127 i40e_filter_restore(struct i40e_pf *pf)
12128 {
12129         i40e_ethertype_filter_restore(pf);
12130         i40e_tunnel_filter_restore(pf);
12131         i40e_fdir_filter_restore(pf);
12132         i40e_rss_filter_restore(pf);
12133 }
12134
12135 static bool
12136 is_device_supported(struct rte_eth_dev *dev, struct rte_pci_driver *drv)
12137 {
12138         if (strcmp(dev->device->driver->name, drv->driver.name))
12139                 return false;
12140
12141         return true;
12142 }
12143
12144 bool
12145 is_i40e_supported(struct rte_eth_dev *dev)
12146 {
12147         return is_device_supported(dev, &rte_i40e_pmd);
12148 }
12149
12150 struct i40e_customized_pctype*
12151 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index)
12152 {
12153         int i;
12154
12155         for (i = 0; i < I40E_CUSTOMIZED_MAX; i++) {
12156                 if (pf->customized_pctype[i].index == index)
12157                         return &pf->customized_pctype[i];
12158         }
12159         return NULL;
12160 }
12161
12162 static int
12163 i40e_update_customized_pctype(struct rte_eth_dev *dev, uint8_t *pkg,
12164                               uint32_t pkg_size, uint32_t proto_num,
12165                               struct rte_pmd_i40e_proto_info *proto,
12166                               enum rte_pmd_i40e_package_op op)
12167 {
12168         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12169         uint32_t pctype_num;
12170         struct rte_pmd_i40e_ptype_info *pctype;
12171         uint32_t buff_size;
12172         struct i40e_customized_pctype *new_pctype = NULL;
12173         uint8_t proto_id;
12174         uint8_t pctype_value;
12175         char name[64];
12176         uint32_t i, j, n;
12177         int ret;
12178
12179         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12180             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12181                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12182                 return -1;
12183         }
12184
12185         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12186                                 (uint8_t *)&pctype_num, sizeof(pctype_num),
12187                                 RTE_PMD_I40E_PKG_INFO_PCTYPE_NUM);
12188         if (ret) {
12189                 PMD_DRV_LOG(ERR, "Failed to get pctype number");
12190                 return -1;
12191         }
12192         if (!pctype_num) {
12193                 PMD_DRV_LOG(INFO, "No new pctype added");
12194                 return -1;
12195         }
12196
12197         buff_size = pctype_num * sizeof(struct rte_pmd_i40e_proto_info);
12198         pctype = rte_zmalloc("new_pctype", buff_size, 0);
12199         if (!pctype) {
12200                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12201                 return -1;
12202         }
12203         /* get information about new pctype list */
12204         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12205                                         (uint8_t *)pctype, buff_size,
12206                                         RTE_PMD_I40E_PKG_INFO_PCTYPE_LIST);
12207         if (ret) {
12208                 PMD_DRV_LOG(ERR, "Failed to get pctype list");
12209                 rte_free(pctype);
12210                 return -1;
12211         }
12212
12213         /* Update customized pctype. */
12214         for (i = 0; i < pctype_num; i++) {
12215                 pctype_value = pctype[i].ptype_id;
12216                 memset(name, 0, sizeof(name));
12217                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12218                         proto_id = pctype[i].protocols[j];
12219                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12220                                 continue;
12221                         for (n = 0; n < proto_num; n++) {
12222                                 if (proto[n].proto_id != proto_id)
12223                                         continue;
12224                                 strlcat(name, proto[n].name, sizeof(name));
12225                                 strlcat(name, "_", sizeof(name));
12226                                 break;
12227                         }
12228                 }
12229                 name[strlen(name) - 1] = '\0';
12230                 if (!strcmp(name, "GTPC"))
12231                         new_pctype =
12232                                 i40e_find_customized_pctype(pf,
12233                                                       I40E_CUSTOMIZED_GTPC);
12234                 else if (!strcmp(name, "GTPU_IPV4"))
12235                         new_pctype =
12236                                 i40e_find_customized_pctype(pf,
12237                                                    I40E_CUSTOMIZED_GTPU_IPV4);
12238                 else if (!strcmp(name, "GTPU_IPV6"))
12239                         new_pctype =
12240                                 i40e_find_customized_pctype(pf,
12241                                                    I40E_CUSTOMIZED_GTPU_IPV6);
12242                 else if (!strcmp(name, "GTPU"))
12243                         new_pctype =
12244                                 i40e_find_customized_pctype(pf,
12245                                                       I40E_CUSTOMIZED_GTPU);
12246                 if (new_pctype) {
12247                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD) {
12248                                 new_pctype->pctype = pctype_value;
12249                                 new_pctype->valid = true;
12250                         } else {
12251                                 new_pctype->pctype = I40E_FILTER_PCTYPE_INVALID;
12252                                 new_pctype->valid = false;
12253                         }
12254                 }
12255         }
12256
12257         rte_free(pctype);
12258         return 0;
12259 }
12260
12261 static int
12262 i40e_update_customized_ptype(struct rte_eth_dev *dev, uint8_t *pkg,
12263                              uint32_t pkg_size, uint32_t proto_num,
12264                              struct rte_pmd_i40e_proto_info *proto,
12265                              enum rte_pmd_i40e_package_op op)
12266 {
12267         struct rte_pmd_i40e_ptype_mapping *ptype_mapping;
12268         uint16_t port_id = dev->data->port_id;
12269         uint32_t ptype_num;
12270         struct rte_pmd_i40e_ptype_info *ptype;
12271         uint32_t buff_size;
12272         uint8_t proto_id;
12273         char name[RTE_PMD_I40E_DDP_NAME_SIZE];
12274         uint32_t i, j, n;
12275         bool in_tunnel;
12276         int ret;
12277
12278         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12279             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12280                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12281                 return -1;
12282         }
12283
12284         if (op == RTE_PMD_I40E_PKG_OP_WR_DEL) {
12285                 rte_pmd_i40e_ptype_mapping_reset(port_id);
12286                 return 0;
12287         }
12288
12289         /* get information about new ptype num */
12290         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12291                                 (uint8_t *)&ptype_num, sizeof(ptype_num),
12292                                 RTE_PMD_I40E_PKG_INFO_PTYPE_NUM);
12293         if (ret) {
12294                 PMD_DRV_LOG(ERR, "Failed to get ptype number");
12295                 return ret;
12296         }
12297         if (!ptype_num) {
12298                 PMD_DRV_LOG(INFO, "No new ptype added");
12299                 return -1;
12300         }
12301
12302         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_info);
12303         ptype = rte_zmalloc("new_ptype", buff_size, 0);
12304         if (!ptype) {
12305                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12306                 return -1;
12307         }
12308
12309         /* get information about new ptype list */
12310         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12311                                         (uint8_t *)ptype, buff_size,
12312                                         RTE_PMD_I40E_PKG_INFO_PTYPE_LIST);
12313         if (ret) {
12314                 PMD_DRV_LOG(ERR, "Failed to get ptype list");
12315                 rte_free(ptype);
12316                 return ret;
12317         }
12318
12319         buff_size = ptype_num * sizeof(struct rte_pmd_i40e_ptype_mapping);
12320         ptype_mapping = rte_zmalloc("ptype_mapping", buff_size, 0);
12321         if (!ptype_mapping) {
12322                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12323                 rte_free(ptype);
12324                 return -1;
12325         }
12326
12327         /* Update ptype mapping table. */
12328         for (i = 0; i < ptype_num; i++) {
12329                 ptype_mapping[i].hw_ptype = ptype[i].ptype_id;
12330                 ptype_mapping[i].sw_ptype = 0;
12331                 in_tunnel = false;
12332                 for (j = 0; j < RTE_PMD_I40E_PROTO_NUM; j++) {
12333                         proto_id = ptype[i].protocols[j];
12334                         if (proto_id == RTE_PMD_I40E_PROTO_UNUSED)
12335                                 continue;
12336                         for (n = 0; n < proto_num; n++) {
12337                                 if (proto[n].proto_id != proto_id)
12338                                         continue;
12339                                 memset(name, 0, sizeof(name));
12340                                 strcpy(name, proto[n].name);
12341                                 if (!strncasecmp(name, "PPPOE", 5))
12342                                         ptype_mapping[i].sw_ptype |=
12343                                                 RTE_PTYPE_L2_ETHER_PPPOE;
12344                                 else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12345                                          !in_tunnel) {
12346                                         ptype_mapping[i].sw_ptype |=
12347                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12348                                         ptype_mapping[i].sw_ptype |=
12349                                                 RTE_PTYPE_L4_FRAG;
12350                                 } else if (!strncasecmp(name, "IPV4FRAG", 8) &&
12351                                            in_tunnel) {
12352                                         ptype_mapping[i].sw_ptype |=
12353                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12354                                         ptype_mapping[i].sw_ptype |=
12355                                                 RTE_PTYPE_INNER_L4_FRAG;
12356                                 } else if (!strncasecmp(name, "OIPV4", 5)) {
12357                                         ptype_mapping[i].sw_ptype |=
12358                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12359                                         in_tunnel = true;
12360                                 } else if (!strncasecmp(name, "IPV4", 4) &&
12361                                            !in_tunnel)
12362                                         ptype_mapping[i].sw_ptype |=
12363                                                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN;
12364                                 else if (!strncasecmp(name, "IPV4", 4) &&
12365                                          in_tunnel)
12366                                         ptype_mapping[i].sw_ptype |=
12367                                             RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN;
12368                                 else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12369                                          !in_tunnel) {
12370                                         ptype_mapping[i].sw_ptype |=
12371                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12372                                         ptype_mapping[i].sw_ptype |=
12373                                                 RTE_PTYPE_L4_FRAG;
12374                                 } else if (!strncasecmp(name, "IPV6FRAG", 8) &&
12375                                            in_tunnel) {
12376                                         ptype_mapping[i].sw_ptype |=
12377                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12378                                         ptype_mapping[i].sw_ptype |=
12379                                                 RTE_PTYPE_INNER_L4_FRAG;
12380                                 } else if (!strncasecmp(name, "OIPV6", 5)) {
12381                                         ptype_mapping[i].sw_ptype |=
12382                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12383                                         in_tunnel = true;
12384                                 } else if (!strncasecmp(name, "IPV6", 4) &&
12385                                            !in_tunnel)
12386                                         ptype_mapping[i].sw_ptype |=
12387                                                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN;
12388                                 else if (!strncasecmp(name, "IPV6", 4) &&
12389                                          in_tunnel)
12390                                         ptype_mapping[i].sw_ptype |=
12391                                             RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN;
12392                                 else if (!strncasecmp(name, "UDP", 3) &&
12393                                          !in_tunnel)
12394                                         ptype_mapping[i].sw_ptype |=
12395                                                 RTE_PTYPE_L4_UDP;
12396                                 else if (!strncasecmp(name, "UDP", 3) &&
12397                                          in_tunnel)
12398                                         ptype_mapping[i].sw_ptype |=
12399                                                 RTE_PTYPE_INNER_L4_UDP;
12400                                 else if (!strncasecmp(name, "TCP", 3) &&
12401                                          !in_tunnel)
12402                                         ptype_mapping[i].sw_ptype |=
12403                                                 RTE_PTYPE_L4_TCP;
12404                                 else if (!strncasecmp(name, "TCP", 3) &&
12405                                          in_tunnel)
12406                                         ptype_mapping[i].sw_ptype |=
12407                                                 RTE_PTYPE_INNER_L4_TCP;
12408                                 else if (!strncasecmp(name, "SCTP", 4) &&
12409                                          !in_tunnel)
12410                                         ptype_mapping[i].sw_ptype |=
12411                                                 RTE_PTYPE_L4_SCTP;
12412                                 else if (!strncasecmp(name, "SCTP", 4) &&
12413                                          in_tunnel)
12414                                         ptype_mapping[i].sw_ptype |=
12415                                                 RTE_PTYPE_INNER_L4_SCTP;
12416                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12417                                           !strncasecmp(name, "ICMPV6", 6)) &&
12418                                          !in_tunnel)
12419                                         ptype_mapping[i].sw_ptype |=
12420                                                 RTE_PTYPE_L4_ICMP;
12421                                 else if ((!strncasecmp(name, "ICMP", 4) ||
12422                                           !strncasecmp(name, "ICMPV6", 6)) &&
12423                                          in_tunnel)
12424                                         ptype_mapping[i].sw_ptype |=
12425                                                 RTE_PTYPE_INNER_L4_ICMP;
12426                                 else if (!strncasecmp(name, "GTPC", 4)) {
12427                                         ptype_mapping[i].sw_ptype |=
12428                                                 RTE_PTYPE_TUNNEL_GTPC;
12429                                         in_tunnel = true;
12430                                 } else if (!strncasecmp(name, "GTPU", 4)) {
12431                                         ptype_mapping[i].sw_ptype |=
12432                                                 RTE_PTYPE_TUNNEL_GTPU;
12433                                         in_tunnel = true;
12434                                 } else if (!strncasecmp(name, "GRENAT", 6)) {
12435                                         ptype_mapping[i].sw_ptype |=
12436                                                 RTE_PTYPE_TUNNEL_GRENAT;
12437                                         in_tunnel = true;
12438                                 } else if (!strncasecmp(name, "L2TPV2CTL", 9) ||
12439                                            !strncasecmp(name, "L2TPV2", 6)) {
12440                                         ptype_mapping[i].sw_ptype |=
12441                                                 RTE_PTYPE_TUNNEL_L2TP;
12442                                         in_tunnel = true;
12443                                 }
12444
12445                                 break;
12446                         }
12447                 }
12448         }
12449
12450         ret = rte_pmd_i40e_ptype_mapping_update(port_id, ptype_mapping,
12451                                                 ptype_num, 0);
12452         if (ret)
12453                 PMD_DRV_LOG(ERR, "Failed to update mapping table.");
12454
12455         rte_free(ptype_mapping);
12456         rte_free(ptype);
12457         return ret;
12458 }
12459
12460 void
12461 i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
12462                             uint32_t pkg_size, enum rte_pmd_i40e_package_op op)
12463 {
12464         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
12465         uint32_t proto_num;
12466         struct rte_pmd_i40e_proto_info *proto;
12467         uint32_t buff_size;
12468         uint32_t i;
12469         int ret;
12470
12471         if (op != RTE_PMD_I40E_PKG_OP_WR_ADD &&
12472             op != RTE_PMD_I40E_PKG_OP_WR_DEL) {
12473                 PMD_DRV_LOG(ERR, "Unsupported operation.");
12474                 return;
12475         }
12476
12477         /* get information about protocol number */
12478         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12479                                        (uint8_t *)&proto_num, sizeof(proto_num),
12480                                        RTE_PMD_I40E_PKG_INFO_PROTOCOL_NUM);
12481         if (ret) {
12482                 PMD_DRV_LOG(ERR, "Failed to get protocol number");
12483                 return;
12484         }
12485         if (!proto_num) {
12486                 PMD_DRV_LOG(INFO, "No new protocol added");
12487                 return;
12488         }
12489
12490         buff_size = proto_num * sizeof(struct rte_pmd_i40e_proto_info);
12491         proto = rte_zmalloc("new_proto", buff_size, 0);
12492         if (!proto) {
12493                 PMD_DRV_LOG(ERR, "Failed to allocate memory");
12494                 return;
12495         }
12496
12497         /* get information about protocol list */
12498         ret = rte_pmd_i40e_get_ddp_info(pkg, pkg_size,
12499                                         (uint8_t *)proto, buff_size,
12500                                         RTE_PMD_I40E_PKG_INFO_PROTOCOL_LIST);
12501         if (ret) {
12502                 PMD_DRV_LOG(ERR, "Failed to get protocol list");
12503                 rte_free(proto);
12504                 return;
12505         }
12506
12507         /* Check if GTP is supported. */
12508         for (i = 0; i < proto_num; i++) {
12509                 if (!strncmp(proto[i].name, "GTP", 3)) {
12510                         if (op == RTE_PMD_I40E_PKG_OP_WR_ADD)
12511                                 pf->gtp_support = true;
12512                         else
12513                                 pf->gtp_support = false;
12514                         break;
12515                 }
12516         }
12517
12518         /* Update customized pctype info */
12519         ret = i40e_update_customized_pctype(dev, pkg, pkg_size,
12520                                             proto_num, proto, op);
12521         if (ret)
12522                 PMD_DRV_LOG(INFO, "No pctype is updated.");
12523
12524         /* Update customized ptype info */
12525         ret = i40e_update_customized_ptype(dev, pkg, pkg_size,
12526                                            proto_num, proto, op);
12527         if (ret)
12528                 PMD_DRV_LOG(INFO, "No ptype is updated.");
12529
12530         rte_free(proto);
12531 }
12532
12533 /* Create a QinQ cloud filter
12534  *
12535  * The Fortville NIC has limited resources for tunnel filters,
12536  * so we can only reuse existing filters.
12537  *
12538  * In step 1 we define which Field Vector fields can be used for
12539  * filter types.
12540  * As we do not have the inner tag defined as a field,
12541  * we have to define it first, by reusing one of L1 entries.
12542  *
12543  * In step 2 we are replacing one of existing filter types with
12544  * a new one for QinQ.
12545  * As we reusing L1 and replacing L2, some of the default filter
12546  * types will disappear,which depends on L1 and L2 entries we reuse.
12547  *
12548  * Step 1: Create L1 filter of outer vlan (12b) + inner vlan (12b)
12549  *
12550  * 1.   Create L1 filter of outer vlan (12b) which will be in use
12551  *              later when we define the cloud filter.
12552  *      a.      Valid_flags.replace_cloud = 0
12553  *      b.      Old_filter = 10 (Stag_Inner_Vlan)
12554  *      c.      New_filter = 0x10
12555  *      d.      TR bit = 0xff (optional, not used here)
12556  *      e.      Buffer – 2 entries:
12557  *              i.      Byte 0 = 8 (outer vlan FV index).
12558  *                      Byte 1 = 0 (rsv)
12559  *                      Byte 2-3 = 0x0fff
12560  *              ii.     Byte 0 = 37 (inner vlan FV index).
12561  *                      Byte 1 =0 (rsv)
12562  *                      Byte 2-3 = 0x0fff
12563  *
12564  * Step 2:
12565  * 2.   Create cloud filter using two L1 filters entries: stag and
12566  *              new filter(outer vlan+ inner vlan)
12567  *      a.      Valid_flags.replace_cloud = 1
12568  *      b.      Old_filter = 1 (instead of outer IP)
12569  *      c.      New_filter = 0x10
12570  *      d.      Buffer – 2 entries:
12571  *              i.      Byte 0 = 0x80 | 7 (valid | Stag).
12572  *                      Byte 1-3 = 0 (rsv)
12573  *              ii.     Byte 8 = 0x80 | 0x10 (valid | new l1 filter step1)
12574  *                      Byte 9-11 = 0 (rsv)
12575  */
12576 static int
12577 i40e_cloud_filter_qinq_create(struct i40e_pf *pf)
12578 {
12579         int ret = -ENOTSUP;
12580         struct i40e_aqc_replace_cloud_filters_cmd  filter_replace;
12581         struct i40e_aqc_replace_cloud_filters_cmd_buf  filter_replace_buf;
12582         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12583         struct rte_eth_dev *dev = ((struct i40e_adapter *)hw->back)->eth_dev;
12584
12585         if (pf->support_multi_driver) {
12586                 PMD_DRV_LOG(ERR, "Replace cloud filter is not supported.");
12587                 return ret;
12588         }
12589
12590         /* Init */
12591         memset(&filter_replace, 0,
12592                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12593         memset(&filter_replace_buf, 0,
12594                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12595
12596         /* create L1 filter */
12597         filter_replace.old_filter_type =
12598                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN;
12599         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12600         filter_replace.tr_bit = 0;
12601
12602         /* Prepare the buffer, 2 entries */
12603         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN;
12604         filter_replace_buf.data[0] |=
12605                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12606         /* Field Vector 12b mask */
12607         filter_replace_buf.data[2] = 0xff;
12608         filter_replace_buf.data[3] = 0x0f;
12609         filter_replace_buf.data[4] =
12610                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN;
12611         filter_replace_buf.data[4] |=
12612                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12613         /* Field Vector 12b mask */
12614         filter_replace_buf.data[6] = 0xff;
12615         filter_replace_buf.data[7] = 0x0f;
12616         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12617                         &filter_replace_buf);
12618         if (ret != I40E_SUCCESS)
12619                 return ret;
12620
12621         if (filter_replace.old_filter_type !=
12622             filter_replace.new_filter_type)
12623                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud l1 type."
12624                             " original: 0x%x, new: 0x%x",
12625                             dev->device->name,
12626                             filter_replace.old_filter_type,
12627                             filter_replace.new_filter_type);
12628
12629         /* Apply the second L2 cloud filter */
12630         memset(&filter_replace, 0,
12631                sizeof(struct i40e_aqc_replace_cloud_filters_cmd));
12632         memset(&filter_replace_buf, 0,
12633                sizeof(struct i40e_aqc_replace_cloud_filters_cmd_buf));
12634
12635         /* create L2 filter, input for L2 filter will be L1 filter  */
12636         filter_replace.valid_flags = I40E_AQC_REPLACE_CLOUD_FILTER;
12637         filter_replace.old_filter_type = I40E_AQC_ADD_CLOUD_FILTER_OIP;
12638         filter_replace.new_filter_type = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12639
12640         /* Prepare the buffer, 2 entries */
12641         filter_replace_buf.data[0] = I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG;
12642         filter_replace_buf.data[0] |=
12643                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12644         filter_replace_buf.data[4] = I40E_AQC_ADD_CLOUD_FILTER_0X10;
12645         filter_replace_buf.data[4] |=
12646                 I40E_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED;
12647         ret = i40e_aq_replace_cloud_filters(hw, &filter_replace,
12648                         &filter_replace_buf);
12649         if (!ret && (filter_replace.old_filter_type !=
12650                      filter_replace.new_filter_type))
12651                 PMD_DRV_LOG(WARNING, "i40e device %s changed cloud filter type."
12652                             " original: 0x%x, new: 0x%x",
12653                             dev->device->name,
12654                             filter_replace.old_filter_type,
12655                             filter_replace.new_filter_type);
12656
12657         return ret;
12658 }
12659
12660 int
12661 i40e_rss_conf_init(struct i40e_rte_flow_rss_conf *out,
12662                    const struct rte_flow_action_rss *in)
12663 {
12664         if (in->key_len > RTE_DIM(out->key) ||
12665             in->queue_num > RTE_DIM(out->queue))
12666                 return -EINVAL;
12667         if (!in->key && in->key_len)
12668                 return -EINVAL;
12669         out->conf = (struct rte_flow_action_rss){
12670                 .func = in->func,
12671                 .level = in->level,
12672                 .types = in->types,
12673                 .key_len = in->key_len,
12674                 .queue_num = in->queue_num,
12675                 .queue = memcpy(out->queue, in->queue,
12676                                 sizeof(*in->queue) * in->queue_num),
12677         };
12678         if (in->key)
12679                 out->conf.key = memcpy(out->key, in->key, in->key_len);
12680         return 0;
12681 }
12682
12683 int
12684 i40e_action_rss_same(const struct rte_flow_action_rss *comp,
12685                      const struct rte_flow_action_rss *with)
12686 {
12687         return (comp->func == with->func &&
12688                 comp->level == with->level &&
12689                 comp->types == with->types &&
12690                 comp->key_len == with->key_len &&
12691                 comp->queue_num == with->queue_num &&
12692                 !memcmp(comp->key, with->key, with->key_len) &&
12693                 !memcmp(comp->queue, with->queue,
12694                         sizeof(*with->queue) * with->queue_num));
12695 }
12696
12697 int
12698 i40e_config_rss_filter(struct i40e_pf *pf,
12699                 struct i40e_rte_flow_rss_conf *conf, bool add)
12700 {
12701         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
12702         uint32_t i, lut = 0;
12703         uint16_t j, num;
12704         struct rte_eth_rss_conf rss_conf = {
12705                 .rss_key = conf->conf.key_len ?
12706                         (void *)(uintptr_t)conf->conf.key : NULL,
12707                 .rss_key_len = conf->conf.key_len,
12708                 .rss_hf = conf->conf.types,
12709         };
12710         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
12711
12712         if (!add) {
12713                 if (i40e_action_rss_same(&rss_info->conf, &conf->conf)) {
12714                         i40e_pf_disable_rss(pf);
12715                         memset(rss_info, 0,
12716                                 sizeof(struct i40e_rte_flow_rss_conf));
12717                         return 0;
12718                 }
12719                 return -EINVAL;
12720         }
12721
12722         /* If both VMDQ and RSS enabled, not all of PF queues are configured.
12723          * It's necessary to calculate the actual PF queues that are configured.
12724          */
12725         if (pf->dev_data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_VMDQ_FLAG)
12726                 num = i40e_pf_calc_configured_queues_num(pf);
12727         else
12728                 num = pf->dev_data->nb_rx_queues;
12729
12730         num = RTE_MIN(num, conf->conf.queue_num);
12731         PMD_DRV_LOG(INFO, "Max of contiguous %u PF queues are configured",
12732                         num);
12733
12734         if (num == 0) {
12735                 PMD_DRV_LOG(ERR, "No PF queues are configured to enable RSS");
12736                 return -ENOTSUP;
12737         }
12738
12739         /* Fill in redirection table */
12740         for (i = 0, j = 0; i < hw->func_caps.rss_table_size; i++, j++) {
12741                 if (j == num)
12742                         j = 0;
12743                 lut = (lut << 8) | (conf->conf.queue[j] & ((0x1 <<
12744                         hw->func_caps.rss_table_entry_width) - 1));
12745                 if ((i & 3) == 3)
12746                         I40E_WRITE_REG(hw, I40E_PFQF_HLUT(i >> 2), lut);
12747         }
12748
12749         if ((rss_conf.rss_hf & pf->adapter->flow_types_mask) == 0) {
12750                 i40e_pf_disable_rss(pf);
12751                 return 0;
12752         }
12753         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
12754                 (I40E_PFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
12755                 /* Random default keys */
12756                 static uint32_t rss_key_default[] = {0x6b793944,
12757                         0x23504cb5, 0x5bea75b6, 0x309f4f12, 0x3dc0a2b8,
12758                         0x024ddcdf, 0x339b8ca0, 0x4c4af64a, 0x34fac605,
12759                         0x55d85839, 0x3a58997d, 0x2ec938e1, 0x66031581};
12760
12761                 rss_conf.rss_key = (uint8_t *)rss_key_default;
12762                 rss_conf.rss_key_len = (I40E_PFQF_HKEY_MAX_INDEX + 1) *
12763                                                         sizeof(uint32_t);
12764                 PMD_DRV_LOG(INFO,
12765                         "No valid RSS key config for i40e, using default\n");
12766         }
12767
12768         i40e_hw_rss_hash_set(pf, &rss_conf);
12769
12770         if (i40e_rss_conf_init(rss_info, &conf->conf))
12771                 return -EINVAL;
12772
12773         return 0;
12774 }
12775
12776 RTE_INIT(i40e_init_log)
12777 {
12778         i40e_logtype_init = rte_log_register("pmd.net.i40e.init");
12779         if (i40e_logtype_init >= 0)
12780                 rte_log_set_level(i40e_logtype_init, RTE_LOG_NOTICE);
12781         i40e_logtype_driver = rte_log_register("pmd.net.i40e.driver");
12782         if (i40e_logtype_driver >= 0)
12783                 rte_log_set_level(i40e_logtype_driver, RTE_LOG_NOTICE);
12784 }
12785
12786 RTE_PMD_REGISTER_PARAM_STRING(net_i40e,
12787                               ETH_I40E_FLOATING_VEB_ARG "=1"
12788                               ETH_I40E_FLOATING_VEB_LIST_ARG "=<string>"
12789                               ETH_I40E_QUEUE_NUM_PER_VF_ARG "=1|2|4|8|16"
12790                               ETH_I40E_SUPPORT_MULTI_DRIVER "=1"
12791                               ETH_I40E_USE_LATEST_VEC "=0|1");