1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
8 #include <rte_eth_ctrl.h>
10 #include <rte_kvargs.h>
12 #include <rte_flow_driver.h>
13 #include <rte_tm_driver.h>
15 #define I40E_VLAN_TAG_SIZE 4
17 #define I40E_AQ_LEN 32
18 #define I40E_AQ_BUF_SZ 4096
19 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
20 #define I40E_MAX_Q_PER_TC 64
21 #define I40E_NUM_DESC_DEFAULT 512
22 #define I40E_NUM_DESC_ALIGN 32
23 #define I40E_BUF_SIZE_MIN 1024
24 #define I40E_FRAME_SIZE_MAX 9728
25 #define I40E_QUEUE_BASE_ADDR_UNIT 128
26 /* number of VSIs and queue default setting */
27 #define I40E_MAX_QP_NUM_PER_VF 16
28 #define I40E_DEFAULT_QP_NUM_FDIR 1
29 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
30 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
31 /* Maximun number of MAC addresses */
32 #define I40E_NUM_MACADDR_MAX 64
33 /* Maximum number of VFs */
34 #define I40E_MAX_VF 128
35 /*flag of no loopback*/
36 #define I40E_AQ_LB_MODE_NONE 0x0
38 * vlan_id is a 12 bit number.
39 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
40 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
41 * The higher 7 bit val specifies VFTA array index.
43 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
44 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
46 /* Default TC traffic in case DCB is not enabled */
47 #define I40E_DEFAULT_TCMAP 0x1
48 #define I40E_FDIR_QUEUE_ID 0
50 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
51 #define I40E_VMDQ_POOL_BASE 1
53 #define I40E_DEFAULT_RX_FREE_THRESH 32
54 #define I40E_DEFAULT_RX_PTHRESH 8
55 #define I40E_DEFAULT_RX_HTHRESH 8
56 #define I40E_DEFAULT_RX_WTHRESH 0
58 #define I40E_DEFAULT_TX_FREE_THRESH 32
59 #define I40E_DEFAULT_TX_PTHRESH 32
60 #define I40E_DEFAULT_TX_HTHRESH 0
61 #define I40E_DEFAULT_TX_WTHRESH 0
62 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
64 /* Bit shift and mask */
65 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
66 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
67 #define I40E_8_BIT_WIDTH CHAR_BIT
68 #define I40E_8_BIT_MASK UINT8_MAX
69 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
70 #define I40E_16_BIT_MASK UINT16_MAX
71 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
72 #define I40E_32_BIT_MASK UINT32_MAX
73 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
74 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
76 /* Linux PF host with virtchnl version 1.1 */
77 #define PF_IS_V11(vf) \
78 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
79 ((vf)->version_minor == 1))
81 /* index flex payload per layer */
82 enum i40e_flxpld_layer_idx {
83 I40E_FLXPLD_L2_IDX = 0,
84 I40E_FLXPLD_L3_IDX = 1,
85 I40E_FLXPLD_L4_IDX = 2,
86 I40E_MAX_FLXPLD_LAYER = 3,
88 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
89 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
90 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
91 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
92 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
95 #define I40E_FLAG_RSS (1ULL << 0)
96 #define I40E_FLAG_DCB (1ULL << 1)
97 #define I40E_FLAG_VMDQ (1ULL << 2)
98 #define I40E_FLAG_SRIOV (1ULL << 3)
99 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
100 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
101 #define I40E_FLAG_FDIR (1ULL << 6)
102 #define I40E_FLAG_VXLAN (1ULL << 7)
103 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
104 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
105 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
109 I40E_FLAG_HEADER_SPLIT_DISABLED | \
110 I40E_FLAG_HEADER_SPLIT_ENABLED | \
113 I40E_FLAG_RSS_AQ_CAPABLE | \
114 I40E_FLAG_VF_MAC_BY_PF)
116 #define I40E_RSS_OFFLOAD_ALL ( \
117 ETH_RSS_FRAG_IPV4 | \
118 ETH_RSS_NONFRAG_IPV4_TCP | \
119 ETH_RSS_NONFRAG_IPV4_UDP | \
120 ETH_RSS_NONFRAG_IPV4_SCTP | \
121 ETH_RSS_NONFRAG_IPV4_OTHER | \
122 ETH_RSS_FRAG_IPV6 | \
123 ETH_RSS_NONFRAG_IPV6_TCP | \
124 ETH_RSS_NONFRAG_IPV6_UDP | \
125 ETH_RSS_NONFRAG_IPV6_SCTP | \
126 ETH_RSS_NONFRAG_IPV6_OTHER | \
129 /* All bits of RSS hash enable for X722*/
130 #define I40E_RSS_HENA_ALL_X722 ( \
131 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
132 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
133 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
134 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
135 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
136 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
139 /* All bits of RSS hash enable */
140 #define I40E_RSS_HENA_ALL ( \
141 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
142 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
143 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
144 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
145 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
146 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
148 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
150 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
151 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
152 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
153 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
154 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
156 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
157 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
159 /* Default queue interrupt throttling time in microseconds */
160 #define I40E_ITR_INDEX_DEFAULT 0
161 #define I40E_ITR_INDEX_NONE 3
162 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
163 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
164 /* Special FW support this floating VEB feature */
165 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
166 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
168 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
169 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
170 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
171 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
173 #define I40E_INSET_NONE 0x00000000000000000ULL
176 #define I40E_INSET_DMAC 0x0000000000000001ULL
177 #define I40E_INSET_SMAC 0x0000000000000002ULL
178 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
179 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
180 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
183 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
184 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
185 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
186 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
187 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
188 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
189 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
191 /* bit 16 ~ bit 31 */
192 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
193 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
194 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
195 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
196 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
197 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
198 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
199 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
201 /* bit 32 ~ bit 47, tunnel fields */
202 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
203 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
204 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
205 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
206 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
207 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
209 /* bit 48 ~ bit 55 */
210 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
212 /* bit 56 ~ bit 63, Flex Payload */
213 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
214 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
215 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
216 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
217 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
218 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
219 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
220 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
221 #define I40E_INSET_FLEX_PAYLOAD \
222 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
223 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
224 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
225 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
227 /* The max bandwidth of i40e is 40Gbps. */
228 #define I40E_QOS_BW_MAX 40000
229 /* The bandwidth should be the multiple of 50Mbps. */
230 #define I40E_QOS_BW_GRANULARITY 50
231 /* The min bandwidth weight is 1. */
232 #define I40E_QOS_BW_WEIGHT_MIN 1
233 /* The max bandwidth weight is 127. */
234 #define I40E_QOS_BW_WEIGHT_MAX 127
235 /* The max queue region index is 7. */
236 #define I40E_REGION_MAX_INDEX 7
238 #define I40E_MAX_PERCENT 100
239 #define I40E_DEFAULT_DCB_APP_NUM 1
240 #define I40E_DEFAULT_DCB_APP_PRIO 3
243 * The overhead from MTU to max frame size.
244 * Considering QinQ packet, the VLAN tag needs to be counted twice.
246 #define I40E_ETH_OVERHEAD \
247 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
252 * MAC filter structure
254 struct i40e_mac_filter_info {
255 enum rte_mac_filter_type filter_type;
256 struct ether_addr mac_addr;
259 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
261 /* MAC filter list structure */
262 struct i40e_mac_filter {
263 TAILQ_ENTRY(i40e_mac_filter) next;
264 struct i40e_mac_filter_info mac_info;
267 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
271 /* VSI list structure */
272 struct i40e_vsi_list {
273 TAILQ_ENTRY(i40e_vsi_list) list;
274 struct i40e_vsi *vsi;
277 struct i40e_rx_queue;
278 struct i40e_tx_queue;
280 /* Bandwidth limit information */
281 struct i40e_bw_info {
282 uint16_t bw_limit; /* BW Limit (0 = disabled) */
283 uint8_t bw_max; /* Max BW limit if enabled */
285 /* Relative credits within same TC with respect to other VSIs or Comps */
286 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
287 /* Bandwidth limit per TC */
288 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
289 /* Max bandwidth limit per TC */
290 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
293 /* Structure that defines a VEB */
295 struct i40e_vsi_list_head head;
296 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
297 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
298 uint16_t seid; /* The seid of VEB itself */
299 uint16_t uplink_seid; /* The uplink seid of this VEB */
301 struct i40e_eth_stats stats;
302 uint8_t enabled_tc; /* The traffic class enabled */
303 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
304 struct i40e_bw_info bw_info; /* VEB bandwidth information */
307 /* i40e MACVLAN filter structure */
308 struct i40e_macvlan_filter {
309 struct ether_addr macaddr;
310 enum rte_mac_filter_type filter_type;
315 * Structure that defines a VSI, associated with a adapter.
318 struct i40e_adapter *adapter; /* Backreference to associated adapter */
319 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
321 struct i40e_eth_stats eth_stats_offset;
322 struct i40e_eth_stats eth_stats;
324 * When drivers loaded, only a default main VSI exists. In case new VSI
325 * needs to add, HW needs to know the layout that VSIs are organized.
326 * Besides that, VSI isan element and can't switch packets, which needs
327 * to add new component VEB to perform switching. So, a new VSI needs
328 * to specify the uplink VSI (Parent VSI) before created. The
329 * uplink VSI will check whether it had a VEB to switch packets. If no,
330 * it will try to create one. Then, uplink VSI will move the new VSI
331 * into its' sib_vsi_list to manage all the downlink VSI.
332 * sib_vsi_list: the VSI list that shared the same uplink VSI.
333 * parent_vsi : the uplink VSI. It's NULL for main VSI.
334 * veb : the VEB associates with the VSI.
336 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
337 struct i40e_vsi *parent_vsi;
338 struct i40e_veb *veb; /* Associated veb, could be null */
339 struct i40e_veb *floating_veb; /* Associated floating veb */
341 enum i40e_vsi_type type; /* VSI types */
342 uint16_t vlan_num; /* Total VLAN number */
343 uint16_t mac_num; /* Total mac number */
344 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
345 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
346 /* specific VSI-defined parameters, SRIOV stored the vf_id */
348 uint16_t seid; /* The seid of VSI itself */
349 uint16_t uplink_seid; /* The uplink seid of this VSI */
350 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
351 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
352 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
353 uint16_t base_queue; /* The first queue index of this VSI */
355 * The offset to visit VSI related register, assigned by HW when
359 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
360 uint16_t nb_msix; /* The max number of msix vector */
361 uint8_t enabled_tc; /* The traffic class enabled */
362 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
363 uint8_t vlan_filter_on; /* The VLAN filter enabled */
364 struct i40e_bw_info bw_info; /* VSI bandwidth information */
368 LIST_ENTRY(pool_entry) next;
373 LIST_HEAD(res_list, pool_entry);
375 struct i40e_res_pool_info {
376 uint32_t base; /* Resource start index */
377 uint32_t num_alloc; /* Allocated resource number */
378 uint32_t num_free; /* Total available resource number */
379 struct res_list alloc_list; /* Allocated resource list */
380 struct res_list free_list; /* Available resource list */
384 I40E_VF_INACTIVE = 0,
391 * Structure to store private data for PF host.
395 struct i40e_vsi *vsi;
396 enum I40E_VF_STATE state; /* The number of queue pairs available */
397 uint16_t vf_idx; /* VF index in pf->vfs */
398 uint16_t lan_nb_qps; /* Actual queues allocated */
399 uint16_t reset_cnt; /* Total vf reset times */
400 struct ether_addr mac_addr; /* Default MAC address */
404 * Structure to store private data for flow control.
406 struct i40e_fc_conf {
407 uint16_t pause_time; /* Flow control pause timer */
408 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
409 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
410 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
411 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
415 * Structure to store private data for VMDQ instance
417 struct i40e_vmdq_info {
419 struct i40e_vsi *vsi;
422 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
423 #define I40E_MAX_FLX_SOURCE_OFF 480
424 #define NONUSE_FLX_PIT_DEST_OFF 63
425 #define NONUSE_FLX_PIT_FSIZE 1
426 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
427 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
428 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
429 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
430 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
431 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
432 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
433 NONUSE_FLX_PIT_DEST_OFF : \
434 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
435 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
436 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
437 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
438 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
439 #define I40E_FDIR_IPv6_TC_OFFSET 20
441 /* A structure used to define the input for GTP flow */
442 struct i40e_gtp_flow {
443 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
444 uint8_t msg_type; /* Message type. */
445 uint32_t teid; /* TEID in big endian. */
448 /* A structure used to define the input for GTP IPV4 flow */
449 struct i40e_gtp_ipv4_flow {
450 struct i40e_gtp_flow gtp;
451 struct rte_eth_ipv4_flow ip4;
454 /* A structure used to define the input for GTP IPV6 flow */
455 struct i40e_gtp_ipv6_flow {
456 struct i40e_gtp_flow gtp;
457 struct rte_eth_ipv6_flow ip6;
460 /* A structure used to define the input for raw type flow */
461 struct i40e_raw_flow {
468 * A union contains the inputs for all types of flow
469 * items in flows need to be in big endian
471 union i40e_fdir_flow {
472 struct rte_eth_l2_flow l2_flow;
473 struct rte_eth_udpv4_flow udp4_flow;
474 struct rte_eth_tcpv4_flow tcp4_flow;
475 struct rte_eth_sctpv4_flow sctp4_flow;
476 struct rte_eth_ipv4_flow ip4_flow;
477 struct rte_eth_udpv6_flow udp6_flow;
478 struct rte_eth_tcpv6_flow tcp6_flow;
479 struct rte_eth_sctpv6_flow sctp6_flow;
480 struct rte_eth_ipv6_flow ipv6_flow;
481 struct i40e_gtp_flow gtp_flow;
482 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
483 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
484 struct i40e_raw_flow raw_flow;
487 enum i40e_fdir_ip_type {
488 I40E_FDIR_IPTYPE_IPV4,
489 I40E_FDIR_IPTYPE_IPV6,
492 /* A structure used to contain extend input of flow */
493 struct i40e_fdir_flow_ext {
495 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
496 /* It is filled by the flexible payload to match. */
497 uint8_t is_vf; /* 1 for VF, 0 for port dev */
498 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
499 bool inner_ip; /* If there is inner ip */
500 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
501 bool customized_pctype; /* If customized pctype is used */
502 bool pkt_template; /* If raw packet template is used */
505 /* A structure used to define the input for a flow director filter entry */
506 struct i40e_fdir_input {
507 enum i40e_filter_pctype pctype;
508 union i40e_fdir_flow flow;
509 /* Flow fields to match, dependent on flow_type */
510 struct i40e_fdir_flow_ext flow_ext;
511 /* Additional fields to match */
514 /* Behavior will be taken if FDIR match */
515 enum i40e_fdir_behavior {
516 I40E_FDIR_ACCEPT = 0,
521 /* Flow director report status
522 * It defines what will be reported if FDIR entry is matched.
524 enum i40e_fdir_status {
525 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
526 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
527 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
528 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
531 /* A structure used to define an action when match FDIR packet filter. */
532 struct i40e_fdir_action {
533 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
534 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
535 enum i40e_fdir_status report_status; /* Status report option */
536 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
537 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
538 * flex bytes start from in flexible payload.
543 /* A structure used to define the flow director filter entry by filter_ctrl API
544 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
545 * RTE_ETH_FILTER_DELETE operations.
547 struct i40e_fdir_filter_conf {
549 /* ID, an unique value is required when deal with FDIR entry */
550 struct i40e_fdir_input input; /* Input set */
551 struct i40e_fdir_action action; /* Action taken when match */
555 * Structure to store flex pit for flow diretor.
557 struct i40e_fdir_flex_pit {
558 uint8_t src_offset; /* offset in words from the beginning of payload */
559 uint8_t size; /* size in words */
560 uint8_t dst_offset; /* offset in words of flexible payload */
563 struct i40e_fdir_flex_mask {
564 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
569 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
572 #define I40E_FILTER_PCTYPE_INVALID 0
573 #define I40E_FILTER_PCTYPE_MAX 64
574 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
576 struct i40e_fdir_filter {
577 TAILQ_ENTRY(i40e_fdir_filter) rules;
578 struct i40e_fdir_filter_conf fdir;
581 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
583 * A structure used to define fields of a FDIR related info.
585 struct i40e_fdir_info {
586 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
587 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
588 struct i40e_tx_queue *txq;
589 struct i40e_rx_queue *rxq;
590 void *prg_pkt; /* memory for fdir program packet */
591 uint64_t dma_addr; /* physic address of packet memory*/
592 /* input set bits for each pctype */
593 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
595 * the rule how bytes stream is extracted as flexible payload
596 * for each payload layer, the setting can up to three elements
598 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
599 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
601 struct i40e_fdir_filter_list fdir_list;
602 struct i40e_fdir_filter **hash_map;
603 struct rte_hash *hash_table;
605 /* Mark if flex pit and mask is set */
606 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
607 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
609 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
612 /* Ethertype filter number HW supports */
613 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
615 /* Ethertype filter struct */
616 struct i40e_ethertype_filter_input {
617 struct ether_addr mac_addr; /* Mac address to match */
618 uint16_t ether_type; /* Ether type to match */
621 struct i40e_ethertype_filter {
622 TAILQ_ENTRY(i40e_ethertype_filter) rules;
623 struct i40e_ethertype_filter_input input;
624 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
625 uint16_t queue; /* Queue assigned to when match */
628 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
630 struct i40e_ethertype_rule {
631 struct i40e_ethertype_filter_list ethertype_list;
632 struct i40e_ethertype_filter **hash_map;
633 struct rte_hash *hash_table;
636 /* queue region info */
637 struct i40e_queue_region_info {
638 /* the region id for this configuration */
640 /* the start queue index for this region */
641 uint8_t queue_start_index;
642 /* the total queue number of this queue region */
644 /* the total number of user priority for this region */
645 uint8_t user_priority_num;
646 /* the packet's user priority for this region */
647 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
648 /* the total number of flowtype for this region */
649 uint8_t flowtype_num;
651 * the pctype or hardware flowtype of packet,
652 * the specific index for each type has been defined
653 * in file i40e_type.h as enum i40e_filter_pctype.
655 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
658 struct i40e_queue_regions {
659 /* the total number of queue region for this port */
660 uint16_t queue_region_number;
661 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
664 /* Tunnel filter number HW supports */
665 #define I40E_MAX_TUNNEL_FILTER_NUM 400
667 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
668 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
669 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
670 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
671 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
672 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
673 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
674 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
675 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
676 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
677 #define I40E_AQC_NEW_TR_21 21
678 #define I40E_AQC_NEW_TR_22 22
680 enum i40e_tunnel_iptype {
681 I40E_TUNNEL_IPTYPE_IPV4,
682 I40E_TUNNEL_IPTYPE_IPV6,
685 /* Tunnel filter struct */
686 struct i40e_tunnel_filter_input {
687 uint8_t outer_mac[6]; /* Outer mac address to match */
688 uint8_t inner_mac[6]; /* Inner mac address to match */
689 uint16_t inner_vlan; /* Inner vlan address to match */
690 enum i40e_tunnel_iptype ip_type;
691 uint16_t flags; /* Filter type flag */
692 uint32_t tenant_id; /* Tenant id to match */
693 uint16_t general_fields[32]; /* Big buffer */
696 struct i40e_tunnel_filter {
697 TAILQ_ENTRY(i40e_tunnel_filter) rules;
698 struct i40e_tunnel_filter_input input;
699 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
700 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
701 uint16_t queue; /* Queue assigned to when match */
704 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
706 struct i40e_tunnel_rule {
707 struct i40e_tunnel_filter_list tunnel_list;
708 struct i40e_tunnel_filter **hash_map;
709 struct rte_hash *hash_table;
715 enum i40e_tunnel_type {
716 I40E_TUNNEL_TYPE_NONE = 0,
717 I40E_TUNNEL_TYPE_VXLAN,
718 I40E_TUNNEL_TYPE_GENEVE,
719 I40E_TUNNEL_TYPE_TEREDO,
720 I40E_TUNNEL_TYPE_NVGRE,
721 I40E_TUNNEL_TYPE_IP_IN_GRE,
722 I40E_L2_TUNNEL_TYPE_E_TAG,
723 I40E_TUNNEL_TYPE_MPLSoUDP,
724 I40E_TUNNEL_TYPE_MPLSoGRE,
725 I40E_TUNNEL_TYPE_QINQ,
726 I40E_TUNNEL_TYPE_GTPC,
727 I40E_TUNNEL_TYPE_GTPU,
728 I40E_TUNNEL_TYPE_MAX,
732 * Tunneling Packet filter configuration.
734 struct i40e_tunnel_filter_conf {
735 struct ether_addr outer_mac; /**< Outer MAC address to match. */
736 struct ether_addr inner_mac; /**< Inner MAC address to match. */
737 uint16_t inner_vlan; /**< Inner VLAN to match. */
738 uint32_t outer_vlan; /**< Outer VLAN to match */
739 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
741 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
742 * is set in filter_type, or inner destination IP address to match
743 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
746 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
747 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
749 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
750 uint16_t filter_type;
751 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
752 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
753 uint16_t queue_id; /**< Queue assigned to if match. */
754 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
755 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
758 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
759 #define I40E_MAX_MIRROR_RULES 64
761 * Mirror rule structure
763 struct i40e_mirror_rule {
764 TAILQ_ENTRY(i40e_mirror_rule) rules;
766 uint16_t index; /* the sw index of mirror rule */
767 uint16_t id; /* the rule id assigned by firmware */
768 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
769 uint16_t num_entries;
770 /* the info stores depend on the rule type.
771 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
772 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
774 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
777 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
780 * Struct to store flow created.
783 TAILQ_ENTRY(rte_flow) node;
784 enum rte_filter_type filter_type;
788 TAILQ_HEAD(i40e_flow_list, rte_flow);
790 /* Struct to store Traffic Manager shaper profile. */
791 struct i40e_tm_shaper_profile {
792 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
793 uint32_t shaper_profile_id;
794 uint32_t reference_count;
795 struct rte_tm_shaper_params profile;
798 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
800 /* node type of Traffic Manager */
801 enum i40e_tm_node_type {
802 I40E_TM_NODE_TYPE_PORT,
803 I40E_TM_NODE_TYPE_TC,
804 I40E_TM_NODE_TYPE_QUEUE,
805 I40E_TM_NODE_TYPE_MAX,
808 /* Struct to store Traffic Manager node configuration. */
809 struct i40e_tm_node {
810 TAILQ_ENTRY(i40e_tm_node) node;
814 uint32_t reference_count;
815 struct i40e_tm_node *parent;
816 struct i40e_tm_shaper_profile *shaper_profile;
817 struct rte_tm_node_params params;
820 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
822 /* Struct to store all the Traffic Manager configuration. */
823 struct i40e_tm_conf {
824 struct i40e_shaper_profile_list shaper_profile_list;
825 struct i40e_tm_node *root; /* root node - port */
826 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
827 struct i40e_tm_node_list queue_list; /* node list for all the queues */
829 * The number of added TC nodes.
830 * It should be no more than the TC number of this port.
834 * The number of added queue nodes.
835 * It should be no more than the queue number of this port.
837 uint32_t nb_queue_node;
839 * This flag is used to check if APP can change the TM node
841 * When it's true, means the configuration is applied to HW,
842 * APP should not change the configuration.
843 * As we don't support on-the-fly configuration, when starting
844 * the port, APP should call the hierarchy_commit API to set this
845 * flag to true. When stopping the port, this flag should be set
851 enum i40e_new_pctype {
852 I40E_CUSTOMIZED_GTPC = 0,
853 I40E_CUSTOMIZED_GTPU_IPV4,
854 I40E_CUSTOMIZED_GTPU_IPV6,
855 I40E_CUSTOMIZED_GTPU,
859 #define I40E_FILTER_PCTYPE_INVALID 0
860 struct i40e_customized_pctype {
861 enum i40e_new_pctype index; /* Indicate which customized pctype */
862 uint8_t pctype; /* New pctype value */
863 bool valid; /* Check if it's valid */
867 * Structure to store private data specific for PF instance.
870 struct i40e_adapter *adapter; /* The adapter this PF associate to */
871 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
872 uint16_t mac_seid; /* The seid of the MAC of this PF */
873 uint16_t main_vsi_seid; /* The seid of the main VSI */
874 uint16_t max_num_vsi;
875 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
876 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
878 struct i40e_hw_port_stats stats_offset;
879 struct i40e_hw_port_stats stats;
880 /* internal packet statistics, it should be excluded from the total */
881 struct i40e_eth_stats internal_stats_offset;
882 struct i40e_eth_stats internal_stats;
885 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
886 struct ether_addr dev_addr; /* PF device mac address */
887 uint64_t flags; /* PF feature flags */
888 /* All kinds of queue pair setting for different VSIs */
889 struct i40e_pf_vf *vfs;
891 /* Each of below queue pairs should be power of 2 since it's the
892 precondition after TC configuration applied */
893 uint16_t lan_nb_qp_max;
894 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
895 uint16_t lan_qp_offset;
896 uint16_t vmdq_nb_qp_max;
897 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
898 uint16_t vmdq_qp_offset;
899 uint16_t vf_nb_qp_max;
900 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
901 uint16_t vf_qp_offset;
902 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
903 uint16_t fdir_qp_offset;
905 uint16_t hash_lut_size; /* The size of hash lookup table */
906 /* input set bits for each pctype */
907 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
908 /* store VXLAN UDP ports */
909 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
910 uint16_t vxlan_bitmap; /* Vxlan bit mask */
912 /* VMDQ related info */
913 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
914 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
915 struct i40e_vmdq_info *vmdq;
917 struct i40e_fdir_info fdir; /* flow director info */
918 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
919 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
920 struct i40e_queue_regions queue_region; /* queue region info */
921 struct i40e_fc_conf fc_conf; /* Flow control conf */
922 struct i40e_mirror_rule_list mirror_list;
923 uint16_t nb_mirror_rule; /* The number of mirror rules */
924 bool floating_veb; /* The flag to use the floating VEB */
925 /* The floating enable flag for the specific VF */
926 bool floating_veb_list[I40E_MAX_VF];
927 struct i40e_flow_list flow_list;
928 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
929 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
930 bool qinq_replace_flag; /* QINQ filter replace is done */
931 struct i40e_tm_conf tm_conf;
933 /* Dynamic Device Personalization */
934 bool gtp_support; /* 1 - support GTP-C and GTP-U */
935 /* customer customized pctype */
936 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
940 PFMSG_LINK_CHANGE = 0x1,
941 PFMSG_RESET_IMPENDING = 0x2,
942 PFMSG_DRIVER_CLOSE = 0x4,
945 struct i40e_vsi_vlan_pvid_info {
946 uint16_t on; /* Enable or disable pvid */
948 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
950 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
951 * while 'untagged' will reject untagged packets.
959 struct i40e_vf_rx_queues {
960 uint64_t rx_dma_addr;
961 uint32_t rx_ring_len;
965 struct i40e_vf_tx_queues {
966 uint64_t tx_dma_addr;
967 uint32_t tx_ring_len;
971 * Structure to store private data specific for VF instance.
974 struct i40e_adapter *adapter; /* The adapter this VF associate to */
975 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
976 uint16_t num_queue_pairs;
977 uint16_t max_pkt_len; /* Maximum packet length */
978 bool promisc_unicast_enabled;
979 bool promisc_multicast_enabled;
981 uint32_t version_major; /* Major version number */
982 uint32_t version_minor; /* Minor version number */
983 uint16_t promisc_flags; /* Promiscuous setting */
984 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
989 enum virtchnl_link_speed link_speed;
991 volatile uint32_t pend_cmd; /* pending command not finished yet */
992 int32_t cmd_retval; /* return value of the cmd response from PF */
993 u16 pend_msg; /* flags indicates events from pf not handled yet */
994 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
997 struct virtchnl_vf_resource *vf_res; /* All VSIs */
998 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1003 #define I40E_MAX_PKT_TYPE 256
1004 #define I40E_FLOW_TYPE_MAX 64
1007 * Structure to store private data for each PF/VF instance.
1009 struct i40e_adapter {
1010 /* Common for both PF and VF */
1012 struct rte_eth_dev *eth_dev;
1014 /* Specific for PF or VF */
1020 /* For vector PMD */
1021 bool rx_bulk_alloc_allowed;
1022 bool rx_vec_allowed;
1023 bool tx_simple_allowed;
1024 bool tx_vec_allowed;
1027 struct rte_timecounter systime_tc;
1028 struct rte_timecounter rx_tstamp_tc;
1029 struct rte_timecounter tx_tstamp_tc;
1031 /* ptype mapping table */
1032 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1033 /* flow type to pctype mapping table */
1034 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1035 uint64_t flow_types_mask;
1036 uint64_t pctypes_mask;
1039 extern const struct rte_flow_ops i40e_flow_ops;
1041 union i40e_filter_t {
1042 struct rte_eth_ethertype_filter ethertype_filter;
1043 struct i40e_fdir_filter_conf fdir_filter;
1044 struct rte_eth_tunnel_filter_conf tunnel_filter;
1045 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1048 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1049 const struct rte_flow_attr *attr,
1050 const struct rte_flow_item pattern[],
1051 const struct rte_flow_action actions[],
1052 struct rte_flow_error *error,
1053 union i40e_filter_t *filter);
1054 struct i40e_valid_pattern {
1055 enum rte_flow_item_type *items;
1056 parse_filter_t parse_filter;
1059 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1060 int i40e_vsi_release(struct i40e_vsi *vsi);
1061 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1062 enum i40e_vsi_type type,
1063 struct i40e_vsi *uplink_vsi,
1064 uint16_t user_param);
1065 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1066 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1067 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1068 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1069 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1070 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1071 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1072 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1073 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1074 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1075 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1076 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1077 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1078 struct i40e_vsi_vlan_pvid_info *info);
1079 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1080 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1081 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1082 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1083 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1084 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1085 int i40e_fdir_setup(struct i40e_pf *pf);
1086 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1089 int i40e_fdir_configure(struct rte_eth_dev *dev);
1090 void i40e_fdir_teardown(struct i40e_pf *pf);
1091 enum i40e_filter_pctype
1092 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1093 uint16_t flow_type);
1094 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1095 enum i40e_filter_pctype pctype);
1096 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1097 enum rte_filter_op filter_op,
1099 int i40e_select_filter_input_set(struct i40e_hw *hw,
1100 struct rte_eth_input_set_conf *conf,
1101 enum rte_filter_type filter);
1102 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1103 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1104 struct rte_eth_input_set_conf *conf);
1105 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1106 struct rte_eth_input_set_conf *conf);
1107 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1108 uint32_t retval, uint8_t *msg,
1110 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1111 struct rte_eth_rxq_info *qinfo);
1112 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1113 struct rte_eth_txq_info *qinfo);
1114 struct i40e_ethertype_filter *
1115 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1116 const struct i40e_ethertype_filter_input *input);
1117 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1118 struct i40e_ethertype_filter_input *input);
1119 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1120 struct i40e_fdir_input *input);
1121 struct i40e_tunnel_filter *
1122 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1123 const struct i40e_tunnel_filter_input *input);
1124 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1125 struct i40e_tunnel_filter_input *input);
1126 uint64_t i40e_get_default_input_set(uint16_t pctype);
1127 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1128 struct rte_eth_ethertype_filter *filter,
1130 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1131 const struct rte_eth_fdir_filter *filter,
1133 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1134 const struct i40e_fdir_filter_conf *filter,
1136 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1137 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1139 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1140 struct i40e_tunnel_filter_conf *tunnel_filter,
1142 int i40e_fdir_flush(struct rte_eth_dev *dev);
1143 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1144 struct i40e_macvlan_filter *mv_f,
1145 int num, struct ether_addr *addr);
1146 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1147 struct i40e_macvlan_filter *filter,
1149 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1150 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1151 struct i40e_macvlan_filter *filter,
1153 bool is_i40e_supported(struct rte_eth_dev *dev);
1155 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1156 enum rte_filter_type filter, uint64_t inset);
1157 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1159 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1160 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1162 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1163 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1164 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1165 struct i40e_customized_pctype*
1166 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1167 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1169 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1170 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1171 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1172 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1174 #define I40E_DEV_TO_PCI(eth_dev) \
1175 RTE_DEV_TO_PCI((eth_dev)->device)
1177 /* I40E_DEV_PRIVATE_TO */
1178 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1179 (&((struct i40e_adapter *)adapter)->pf)
1180 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1181 (&((struct i40e_adapter *)adapter)->hw)
1182 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1183 ((struct i40e_adapter *)adapter)
1185 /* I40EVF_DEV_PRIVATE_TO */
1186 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1187 (&((struct i40e_adapter *)adapter)->vf)
1189 static inline struct i40e_vsi *
1190 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1197 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1198 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1199 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1202 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1203 return pf->main_vsi;
1206 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1207 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1210 #define I40E_VSI_TO_HW(vsi) \
1211 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1212 #define I40E_VSI_TO_PF(vsi) \
1213 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1214 #define I40E_VSI_TO_VF(vsi) \
1215 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1216 #define I40E_VSI_TO_DEV_DATA(vsi) \
1217 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1218 #define I40E_VSI_TO_ETH_DEV(vsi) \
1219 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1222 #define I40E_PF_TO_HW(pf) \
1223 (&(((struct i40e_pf *)pf)->adapter->hw))
1224 #define I40E_PF_TO_ADAPTER(pf) \
1225 ((struct i40e_adapter *)pf->adapter)
1228 #define I40E_VF_TO_HW(vf) \
1229 (&(((struct i40e_vf *)vf)->adapter->hw))
1232 i40e_init_adminq_parameter(struct i40e_hw *hw)
1234 hw->aq.num_arq_entries = I40E_AQ_LEN;
1235 hw->aq.num_asq_entries = I40E_AQ_LEN;
1236 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1237 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1241 i40e_align_floor(int n)
1245 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1248 static inline uint16_t
1249 i40e_calc_itr_interval(int16_t interval)
1251 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1252 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1254 /* Convert to hardware count, as writing each 1 represents 2 us */
1255 return interval / 2;
1258 #define I40E_VALID_FLOW(flow_type) \
1259 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1260 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1261 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1262 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1263 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1264 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1265 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1266 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1267 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1268 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1269 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1271 #define I40E_VALID_PCTYPE_X722(pctype) \
1272 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1273 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1274 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1275 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1276 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1277 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1278 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1279 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1280 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1281 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1282 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1283 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1284 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1285 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1286 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1287 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1288 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1290 #define I40E_VALID_PCTYPE(pctype) \
1291 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1292 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1293 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1294 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1295 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1296 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1297 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1298 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1299 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1300 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1301 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1303 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1304 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1305 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1306 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1307 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1308 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1309 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1311 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1312 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1313 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1314 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1315 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1317 #endif /* _I40E_ETHDEV_H_ */