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34 #ifndef _I40E_ETHDEV_H_
35 #define _I40E_ETHDEV_H_
37 #include <rte_eth_ctrl.h>
39 #define I40E_VLAN_TAG_SIZE 4
41 #define I40E_AQ_LEN 32
42 #define I40E_AQ_BUF_SZ 4096
43 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
44 #define I40E_MAX_Q_PER_TC 64
45 #define I40E_NUM_DESC_DEFAULT 512
46 #define I40E_NUM_DESC_ALIGN 32
47 #define I40E_BUF_SIZE_MIN 1024
48 #define I40E_FRAME_SIZE_MAX 9728
49 #define I40E_QUEUE_BASE_ADDR_UNIT 128
50 /* number of VSIs and queue default setting */
51 #define I40E_MAX_QP_NUM_PER_VF 16
52 #define I40E_DEFAULT_QP_NUM_FDIR 1
53 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
54 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
56 * vlan_id is a 12 bit number.
57 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
58 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
59 * The higher 7 bit val specifies VFTA array index.
61 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
62 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
64 /* Default TC traffic in case DCB is not enabled */
65 #define I40E_DEFAULT_TCMAP 0x1
66 #define I40E_FDIR_QUEUE_ID 0
68 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
69 #define I40E_VMDQ_POOL_BASE 1
71 #define I40E_DEFAULT_RX_FREE_THRESH 32
72 #define I40E_DEFAULT_RX_PTHRESH 8
73 #define I40E_DEFAULT_RX_HTHRESH 8
74 #define I40E_DEFAULT_RX_WTHRESH 0
76 #define I40E_DEFAULT_TX_FREE_THRESH 32
77 #define I40E_DEFAULT_TX_PTHRESH 32
78 #define I40E_DEFAULT_TX_HTHRESH 0
79 #define I40E_DEFAULT_TX_WTHRESH 0
80 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
82 /* Bit shift and mask */
83 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
84 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
85 #define I40E_8_BIT_WIDTH CHAR_BIT
86 #define I40E_8_BIT_MASK UINT8_MAX
87 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
88 #define I40E_16_BIT_MASK UINT16_MAX
89 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
90 #define I40E_32_BIT_MASK UINT32_MAX
91 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
92 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
94 /* Linux PF host with virtchnl version 1.1 */
95 #define PF_IS_V11(vf) \
96 (((vf)->version_major == I40E_VIRTCHNL_VERSION_MAJOR) && \
97 ((vf)->version_minor == 1))
99 /* index flex payload per layer */
100 enum i40e_flxpld_layer_idx {
101 I40E_FLXPLD_L2_IDX = 0,
102 I40E_FLXPLD_L3_IDX = 1,
103 I40E_FLXPLD_L4_IDX = 2,
104 I40E_MAX_FLXPLD_LAYER = 3,
106 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
107 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
108 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
109 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
110 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
113 #define I40E_FLAG_RSS (1ULL << 0)
114 #define I40E_FLAG_DCB (1ULL << 1)
115 #define I40E_FLAG_VMDQ (1ULL << 2)
116 #define I40E_FLAG_SRIOV (1ULL << 3)
117 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
118 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
119 #define I40E_FLAG_FDIR (1ULL << 6)
120 #define I40E_FLAG_VXLAN (1ULL << 7)
121 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
122 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
126 I40E_FLAG_HEADER_SPLIT_DISABLED | \
127 I40E_FLAG_HEADER_SPLIT_ENABLED | \
130 I40E_FLAG_RSS_AQ_CAPABLE)
132 #define I40E_RSS_OFFLOAD_ALL ( \
133 ETH_RSS_FRAG_IPV4 | \
134 ETH_RSS_NONFRAG_IPV4_TCP | \
135 ETH_RSS_NONFRAG_IPV4_UDP | \
136 ETH_RSS_NONFRAG_IPV4_SCTP | \
137 ETH_RSS_NONFRAG_IPV4_OTHER | \
138 ETH_RSS_FRAG_IPV6 | \
139 ETH_RSS_NONFRAG_IPV6_TCP | \
140 ETH_RSS_NONFRAG_IPV6_UDP | \
141 ETH_RSS_NONFRAG_IPV6_SCTP | \
142 ETH_RSS_NONFRAG_IPV6_OTHER | \
145 /* All bits of RSS hash enable */
146 #define I40E_RSS_HENA_ALL ( \
147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
148 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
149 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
150 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
151 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
152 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
153 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
154 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
155 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
156 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
157 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
158 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
159 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
160 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
162 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
163 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
165 /* Default queue interrupt throttling time in microseconds */
166 #define I40E_ITR_INDEX_DEFAULT 0
167 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
168 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
173 * MAC filter structure
175 struct i40e_mac_filter_info {
176 enum rte_mac_filter_type filter_type;
177 struct ether_addr mac_addr;
180 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
182 /* MAC filter list structure */
183 struct i40e_mac_filter {
184 TAILQ_ENTRY(i40e_mac_filter) next;
185 struct i40e_mac_filter_info mac_info;
188 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
192 /* VSI list structure */
193 struct i40e_vsi_list {
194 TAILQ_ENTRY(i40e_vsi_list) list;
195 struct i40e_vsi *vsi;
198 struct i40e_rx_queue;
199 struct i40e_tx_queue;
201 /* Structure that defines a VEB */
203 struct i40e_vsi_list_head head;
204 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
205 uint16_t seid; /* The seid of VEB itself */
206 uint16_t uplink_seid; /* The uplink seid of this VEB */
208 struct i40e_eth_stats stats;
211 /* i40e MACVLAN filter structure */
212 struct i40e_macvlan_filter {
213 struct ether_addr macaddr;
214 enum rte_mac_filter_type filter_type;
218 /* Bandwidth limit information */
219 struct i40e_bw_info {
220 uint16_t bw_limit; /* BW Limit (0 = disabled) */
221 uint8_t bw_max_quanta; /* Max Quanta when BW limit is enabled */
223 /* Relative TC credits across VSIs */
224 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
225 /* TC BW limit credits within VSI */
226 uint8_t bw_ets_limit_credits[I40E_MAX_TRAFFIC_CLASS];
227 /* TC BW limit max quanta within VSI */
228 uint8_t bw_ets_max_quanta[I40E_MAX_TRAFFIC_CLASS];
232 * Structure that defines a VSI, associated with a adapter.
235 struct i40e_adapter *adapter; /* Backreference to associated adapter */
236 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
238 struct i40e_eth_stats eth_stats_offset;
239 struct i40e_eth_stats eth_stats;
241 * When drivers loaded, only a default main VSI exists. In case new VSI
242 * needs to add, HW needs to know the layout that VSIs are organized.
243 * Besides that, VSI isan element and can't switch packets, which needs
244 * to add new component VEB to perform switching. So, a new VSI needs
245 * to specify the the uplink VSI (Parent VSI) before created. The
246 * uplink VSI will check whether it had a VEB to switch packets. If no,
247 * it will try to create one. Then, uplink VSI will move the new VSI
248 * into its' sib_vsi_list to manage all the downlink VSI.
249 * sib_vsi_list: the VSI list that shared the same uplink VSI.
250 * parent_vsi : the uplink VSI. It's NULL for main VSI.
251 * veb : the VEB associates with the VSI.
253 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
254 struct i40e_vsi *parent_vsi;
255 struct i40e_veb *veb; /* Associated veb, could be null */
257 enum i40e_vsi_type type; /* VSI types */
258 uint16_t vlan_num; /* Total VLAN number */
259 uint16_t mac_num; /* Total mac number */
260 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
261 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
262 /* specific VSI-defined parameters, SRIOV stored the vf_id */
264 uint16_t seid; /* The seid of VSI itself */
265 uint16_t uplink_seid; /* The uplink seid of this VSI */
266 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
267 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
268 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
269 uint16_t base_queue; /* The first queue index of this VSI */
271 * The offset to visit VSI related register, assigned by HW when
275 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
276 uint16_t nb_msix; /* The max number of msix vector */
277 uint8_t enabled_tc; /* The traffic class enabled */
278 struct i40e_bw_info bw_info; /* VSI bandwidth information */
282 LIST_ENTRY(pool_entry) next;
287 LIST_HEAD(res_list, pool_entry);
289 struct i40e_res_pool_info {
290 uint32_t base; /* Resource start index */
291 uint32_t num_alloc; /* Allocated resource number */
292 uint32_t num_free; /* Total available resource number */
293 struct res_list alloc_list; /* Allocated resource list */
294 struct res_list free_list; /* Available resource list */
298 I40E_VF_INACTIVE = 0,
305 * Structure to store private data for PF host.
309 struct i40e_vsi *vsi;
310 enum I40E_VF_STATE state; /* The number of queue pairs availiable */
311 uint16_t vf_idx; /* VF index in pf->vfs */
312 uint16_t lan_nb_qps; /* Actual queues allocated */
313 uint16_t reset_cnt; /* Total vf reset times */
317 * Structure to store private data for flow control.
319 struct i40e_fc_conf {
320 uint16_t pause_time; /* Flow control pause timer */
321 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
322 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
323 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
324 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
328 * Structure to store private data for VMDQ instance
330 struct i40e_vmdq_info {
332 struct i40e_vsi *vsi;
336 * Structure to store flex pit for flow diretor.
338 struct i40e_fdir_flex_pit {
339 uint8_t src_offset; /* offset in words from the beginning of payload */
340 uint8_t size; /* size in words */
341 uint8_t dst_offset; /* offset in words of flexible payload */
344 struct i40e_fdir_flex_mask {
345 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
349 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
352 #define I40E_FILTER_PCTYPE_MAX 64
354 * A structure used to define fields of a FDIR related info.
356 struct i40e_fdir_info {
357 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
358 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
359 struct i40e_tx_queue *txq;
360 struct i40e_rx_queue *rxq;
361 void *prg_pkt; /* memory for fdir program packet */
362 uint64_t dma_addr; /* physic address of packet memory*/
364 * the rule how bytes stream is extracted as flexible payload
365 * for each payload layer, the setting can up to three elements
367 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
368 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
371 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
372 #define I40E_MAX_MIRROR_RULES 64
374 * Mirror rule structure
376 struct i40e_mirror_rule {
377 TAILQ_ENTRY(i40e_mirror_rule) rules;
379 uint16_t index; /* the sw index of mirror rule */
380 uint16_t id; /* the rule id assigned by firmware */
381 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
382 uint16_t num_entries;
383 /* the info stores depend on the rule type.
384 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
385 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
387 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
390 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
393 * Structure to store private data specific for PF instance.
396 struct i40e_adapter *adapter; /* The adapter this PF associate to */
397 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
398 uint16_t mac_seid; /* The seid of the MAC of this PF */
399 uint16_t main_vsi_seid; /* The seid of the main VSI */
400 uint16_t max_num_vsi;
401 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
402 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
404 struct i40e_hw_port_stats stats_offset;
405 struct i40e_hw_port_stats stats;
408 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
409 struct ether_addr dev_addr; /* PF device mac address */
410 uint64_t flags; /* PF featuer flags */
411 /* All kinds of queue pair setting for different VSIs */
412 struct i40e_pf_vf *vfs;
414 /* Each of below queue pairs should be power of 2 since it's the
415 precondition after TC configuration applied */
416 uint16_t lan_nb_qp_max;
417 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
418 uint16_t lan_qp_offset;
419 uint16_t vmdq_nb_qp_max;
420 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
421 uint16_t vmdq_qp_offset;
422 uint16_t vf_nb_qp_max;
423 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
424 uint16_t vf_qp_offset;
425 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
426 uint16_t fdir_qp_offset;
428 uint16_t hash_lut_size; /* The size of hash lookup table */
429 /* store VXLAN UDP ports */
430 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
431 uint16_t vxlan_bitmap; /* Vxlan bit mask */
433 /* VMDQ related info */
434 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
435 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
436 struct i40e_vmdq_info *vmdq;
438 struct i40e_fdir_info fdir; /* flow director info */
439 struct i40e_fc_conf fc_conf; /* Flow control conf */
440 struct i40e_mirror_rule_list mirror_list;
441 uint16_t nb_mirror_rule; /* The number of mirror rules */
445 PFMSG_LINK_CHANGE = 0x1,
446 PFMSG_RESET_IMPENDING = 0x2,
447 PFMSG_DRIVER_CLOSE = 0x4,
450 struct i40e_vsi_vlan_pvid_info {
451 uint16_t on; /* Enable or disable pvid */
453 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
455 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
456 * while 'untagged' will reject untagged packets.
464 struct i40e_vf_rx_queues {
465 uint64_t rx_dma_addr;
466 uint32_t rx_ring_len;
470 struct i40e_vf_tx_queues {
471 uint64_t tx_dma_addr;
472 uint32_t tx_ring_len;
476 * Structure to store private data specific for VF instance.
479 struct i40e_adapter *adapter; /* The adapter this VF associate to */
480 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
481 uint16_t num_queue_pairs;
482 uint16_t max_pkt_len; /* Maximum packet length */
483 bool promisc_unicast_enabled;
484 bool promisc_multicast_enabled;
486 uint32_t version_major; /* Major version number */
487 uint32_t version_minor; /* Minor version number */
488 uint16_t promisc_flags; /* Promiscuous setting */
489 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
495 volatile uint32_t pend_cmd; /* pending command not finished yet */
496 u16 pend_msg; /* flags indicates events from pf not handled yet */
499 struct i40e_virtchnl_vf_resource *vf_res; /* All VSIs */
500 struct i40e_virtchnl_vsi_resource *vsi_res; /* LAN VSI */
506 * Structure to store private data for each PF/VF instance.
508 struct i40e_adapter {
509 /* Common for both PF and VF */
511 struct rte_eth_dev *eth_dev;
513 /* Specific for PF or VF */
520 bool rx_bulk_alloc_allowed;
522 bool tx_simple_allowed;
526 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
527 int i40e_vsi_release(struct i40e_vsi *vsi);
528 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
529 enum i40e_vsi_type type,
530 struct i40e_vsi *uplink_vsi,
531 uint16_t user_param);
532 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
533 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
534 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
535 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
536 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
537 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
538 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
539 void i40e_pf_disable_irq0(struct i40e_hw *hw);
540 void i40e_pf_enable_irq0(struct i40e_hw *hw);
541 int i40e_dev_link_update(struct rte_eth_dev *dev,
542 __rte_unused int wait_to_complete);
543 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi);
544 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
545 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
546 struct i40e_vsi_vlan_pvid_info *info);
547 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
548 uint64_t i40e_config_hena(uint64_t flags);
549 uint64_t i40e_parse_hena(uint64_t flags);
550 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
551 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
552 int i40e_fdir_setup(struct i40e_pf *pf);
553 const struct rte_memzone *i40e_memzone_reserve(const char *name,
556 int i40e_fdir_configure(struct rte_eth_dev *dev);
557 void i40e_fdir_teardown(struct i40e_pf *pf);
558 enum i40e_filter_pctype i40e_flowtype_to_pctype(uint16_t flow_type);
559 uint16_t i40e_pctype_to_flowtype(enum i40e_filter_pctype pctype);
560 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
561 enum rte_filter_op filter_op,
563 int i40e_select_filter_input_set(struct i40e_hw *hw,
564 struct rte_eth_input_set_conf *conf,
565 enum rte_filter_type filter);
566 int i40e_filter_inset_select(struct i40e_hw *hw,
567 struct rte_eth_input_set_conf *conf,
568 enum rte_filter_type filter);
570 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
571 struct rte_eth_rxq_info *qinfo);
572 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
573 struct rte_eth_txq_info *qinfo);
575 /* I40E_DEV_PRIVATE_TO */
576 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
577 (&((struct i40e_adapter *)adapter)->pf)
578 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
579 (&((struct i40e_adapter *)adapter)->hw)
580 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
581 ((struct i40e_adapter *)adapter)
583 /* I40EVF_DEV_PRIVATE_TO */
584 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
585 (&((struct i40e_adapter *)adapter)->vf)
587 static inline struct i40e_vsi *
588 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
595 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
596 if (hw->mac.type == I40E_MAC_VF) {
597 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
600 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
604 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
605 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
608 #define I40E_VSI_TO_HW(vsi) \
609 (&(((struct i40e_vsi *)vsi)->adapter->hw))
610 #define I40E_VSI_TO_PF(vsi) \
611 (&(((struct i40e_vsi *)vsi)->adapter->pf))
612 #define I40E_VSI_TO_VF(vsi) \
613 (&(((struct i40e_vsi *)vsi)->adapter->vf))
614 #define I40E_VSI_TO_DEV_DATA(vsi) \
615 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
616 #define I40E_VSI_TO_ETH_DEV(vsi) \
617 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
620 #define I40E_PF_TO_HW(pf) \
621 (&(((struct i40e_pf *)pf)->adapter->hw))
622 #define I40E_PF_TO_ADAPTER(pf) \
623 ((struct i40e_adapter *)pf->adapter)
626 #define I40E_VF_TO_HW(vf) \
627 (&(((struct i40e_vf *)vf)->adapter->hw))
630 i40e_init_adminq_parameter(struct i40e_hw *hw)
632 hw->aq.num_arq_entries = I40E_AQ_LEN;
633 hw->aq.num_asq_entries = I40E_AQ_LEN;
634 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
635 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
639 i40e_align_floor(int n)
643 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
646 static inline uint16_t
647 i40e_calc_itr_interval(int16_t interval)
649 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
650 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
652 /* Convert to hardware count, as writing each 1 represents 2 us */
653 return (interval / 2);
656 #define I40E_VALID_FLOW(flow_type) \
657 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
658 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
659 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
660 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
661 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
662 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
663 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
664 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
665 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
666 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
667 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
669 #define I40E_VALID_PCTYPE(pctype) \
670 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
671 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
672 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
673 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
674 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
675 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
676 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
677 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
678 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
679 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
680 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
682 #endif /* _I40E_ETHDEV_H_ */