1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2017 Intel Corporation
5 #ifndef _I40E_ETHDEV_H_
6 #define _I40E_ETHDEV_H_
8 #include <rte_eth_ctrl.h>
10 #include <rte_kvargs.h>
12 #include <rte_flow_driver.h>
13 #include <rte_tm_driver.h>
15 #define I40E_VLAN_TAG_SIZE 4
17 #define I40E_AQ_LEN 32
18 #define I40E_AQ_BUF_SZ 4096
19 /* Number of queues per TC should be one of 1, 2, 4, 8, 16, 32, 64 */
20 #define I40E_MAX_Q_PER_TC 64
21 #define I40E_NUM_DESC_DEFAULT 512
22 #define I40E_NUM_DESC_ALIGN 32
23 #define I40E_BUF_SIZE_MIN 1024
24 #define I40E_FRAME_SIZE_MAX 9728
25 #define I40E_QUEUE_BASE_ADDR_UNIT 128
26 /* number of VSIs and queue default setting */
27 #define I40E_MAX_QP_NUM_PER_VF 16
28 #define I40E_DEFAULT_QP_NUM_FDIR 1
29 #define I40E_UINT32_BIT_SIZE (CHAR_BIT * sizeof(uint32_t))
30 #define I40E_VFTA_SIZE (4096 / I40E_UINT32_BIT_SIZE)
31 /* Maximun number of MAC addresses */
32 #define I40E_NUM_MACADDR_MAX 64
33 /* Maximum number of VFs */
34 #define I40E_MAX_VF 128
37 * vlan_id is a 12 bit number.
38 * The VFTA array is actually a 4096 bit array, 128 of 32bit elements.
39 * 2^5 = 32. The val of lower 5 bits specifies the bit in the 32bit element.
40 * The higher 7 bit val specifies VFTA array index.
42 #define I40E_VFTA_BIT(vlan_id) (1 << ((vlan_id) & 0x1F))
43 #define I40E_VFTA_IDX(vlan_id) ((vlan_id) >> 5)
45 /* Default TC traffic in case DCB is not enabled */
46 #define I40E_DEFAULT_TCMAP 0x1
47 #define I40E_FDIR_QUEUE_ID 0
49 /* Always assign pool 0 to main VSI, VMDQ will start from 1 */
50 #define I40E_VMDQ_POOL_BASE 1
52 #define I40E_DEFAULT_RX_FREE_THRESH 32
53 #define I40E_DEFAULT_RX_PTHRESH 8
54 #define I40E_DEFAULT_RX_HTHRESH 8
55 #define I40E_DEFAULT_RX_WTHRESH 0
57 #define I40E_DEFAULT_TX_FREE_THRESH 32
58 #define I40E_DEFAULT_TX_PTHRESH 32
59 #define I40E_DEFAULT_TX_HTHRESH 0
60 #define I40E_DEFAULT_TX_WTHRESH 0
61 #define I40E_DEFAULT_TX_RSBIT_THRESH 32
63 /* Bit shift and mask */
64 #define I40E_4_BIT_WIDTH (CHAR_BIT / 2)
65 #define I40E_4_BIT_MASK RTE_LEN2MASK(I40E_4_BIT_WIDTH, uint8_t)
66 #define I40E_8_BIT_WIDTH CHAR_BIT
67 #define I40E_8_BIT_MASK UINT8_MAX
68 #define I40E_16_BIT_WIDTH (CHAR_BIT * 2)
69 #define I40E_16_BIT_MASK UINT16_MAX
70 #define I40E_32_BIT_WIDTH (CHAR_BIT * 4)
71 #define I40E_32_BIT_MASK UINT32_MAX
72 #define I40E_48_BIT_WIDTH (CHAR_BIT * 6)
73 #define I40E_48_BIT_MASK RTE_LEN2MASK(I40E_48_BIT_WIDTH, uint64_t)
75 /* Linux PF host with virtchnl version 1.1 */
76 #define PF_IS_V11(vf) \
77 (((vf)->version_major == VIRTCHNL_VERSION_MAJOR) && \
78 ((vf)->version_minor == 1))
80 /* index flex payload per layer */
81 enum i40e_flxpld_layer_idx {
82 I40E_FLXPLD_L2_IDX = 0,
83 I40E_FLXPLD_L3_IDX = 1,
84 I40E_FLXPLD_L4_IDX = 2,
85 I40E_MAX_FLXPLD_LAYER = 3,
87 #define I40E_MAX_FLXPLD_FIED 3 /* max number of flex payload fields */
88 #define I40E_FDIR_BITMASK_NUM_WORD 2 /* max number of bitmask words */
89 #define I40E_FDIR_MAX_FLEXWORD_NUM 8 /* max number of flexpayload words */
90 #define I40E_FDIR_MAX_FLEX_LEN 16 /* len in bytes of flex payload */
91 #define I40E_INSET_MASK_NUM_REG 2 /* number of input set mask registers */
94 #define I40E_FLAG_RSS (1ULL << 0)
95 #define I40E_FLAG_DCB (1ULL << 1)
96 #define I40E_FLAG_VMDQ (1ULL << 2)
97 #define I40E_FLAG_SRIOV (1ULL << 3)
98 #define I40E_FLAG_HEADER_SPLIT_DISABLED (1ULL << 4)
99 #define I40E_FLAG_HEADER_SPLIT_ENABLED (1ULL << 5)
100 #define I40E_FLAG_FDIR (1ULL << 6)
101 #define I40E_FLAG_VXLAN (1ULL << 7)
102 #define I40E_FLAG_RSS_AQ_CAPABLE (1ULL << 8)
103 #define I40E_FLAG_VF_MAC_BY_PF (1ULL << 9)
104 #define I40E_FLAG_ALL (I40E_FLAG_RSS | \
108 I40E_FLAG_HEADER_SPLIT_DISABLED | \
109 I40E_FLAG_HEADER_SPLIT_ENABLED | \
112 I40E_FLAG_RSS_AQ_CAPABLE | \
113 I40E_FLAG_VF_MAC_BY_PF)
115 #define I40E_RSS_OFFLOAD_ALL ( \
116 ETH_RSS_FRAG_IPV4 | \
117 ETH_RSS_NONFRAG_IPV4_TCP | \
118 ETH_RSS_NONFRAG_IPV4_UDP | \
119 ETH_RSS_NONFRAG_IPV4_SCTP | \
120 ETH_RSS_NONFRAG_IPV4_OTHER | \
121 ETH_RSS_FRAG_IPV6 | \
122 ETH_RSS_NONFRAG_IPV6_TCP | \
123 ETH_RSS_NONFRAG_IPV6_UDP | \
124 ETH_RSS_NONFRAG_IPV6_SCTP | \
125 ETH_RSS_NONFRAG_IPV6_OTHER | \
128 /* All bits of RSS hash enable for X722*/
129 #define I40E_RSS_HENA_ALL_X722 ( \
130 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
131 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
132 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
133 (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
134 (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
135 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK) | \
138 /* All bits of RSS hash enable */
139 #define I40E_RSS_HENA_ALL ( \
140 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
141 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
142 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
143 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
144 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4) | \
145 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
146 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
147 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
148 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
149 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6) | \
150 (1ULL << I40E_FILTER_PCTYPE_FCOE_OX) | \
151 (1ULL << I40E_FILTER_PCTYPE_FCOE_RX) | \
152 (1ULL << I40E_FILTER_PCTYPE_FCOE_OTHER) | \
153 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD))
155 #define I40E_MISC_VEC_ID RTE_INTR_VEC_ZERO_OFFSET
156 #define I40E_RX_VEC_START RTE_INTR_VEC_RXTX_OFFSET
158 /* Default queue interrupt throttling time in microseconds */
159 #define I40E_ITR_INDEX_DEFAULT 0
160 #define I40E_ITR_INDEX_NONE 3
161 #define I40E_QUEUE_ITR_INTERVAL_DEFAULT 32 /* 32 us */
162 #define I40E_QUEUE_ITR_INTERVAL_MAX 8160 /* 8160 us */
163 /* Special FW support this floating VEB feature */
164 #define FLOATING_VEB_SUPPORTED_FW_MAJ 5
165 #define FLOATING_VEB_SUPPORTED_FW_MIN 0
167 #define I40E_GL_SWT_L2TAGCTRL(_i) (0x001C0A70 + ((_i) * 4))
168 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT 16
169 #define I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_MASK \
170 I40E_MASK(0xFFFF, I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT)
172 #define I40E_INSET_NONE 0x00000000000000000ULL
175 #define I40E_INSET_DMAC 0x0000000000000001ULL
176 #define I40E_INSET_SMAC 0x0000000000000002ULL
177 #define I40E_INSET_VLAN_OUTER 0x0000000000000004ULL
178 #define I40E_INSET_VLAN_INNER 0x0000000000000008ULL
179 #define I40E_INSET_VLAN_TUNNEL 0x0000000000000010ULL
182 #define I40E_INSET_IPV4_SRC 0x0000000000000100ULL
183 #define I40E_INSET_IPV4_DST 0x0000000000000200ULL
184 #define I40E_INSET_IPV6_SRC 0x0000000000000400ULL
185 #define I40E_INSET_IPV6_DST 0x0000000000000800ULL
186 #define I40E_INSET_SRC_PORT 0x0000000000001000ULL
187 #define I40E_INSET_DST_PORT 0x0000000000002000ULL
188 #define I40E_INSET_SCTP_VT 0x0000000000004000ULL
190 /* bit 16 ~ bit 31 */
191 #define I40E_INSET_IPV4_TOS 0x0000000000010000ULL
192 #define I40E_INSET_IPV4_PROTO 0x0000000000020000ULL
193 #define I40E_INSET_IPV4_TTL 0x0000000000040000ULL
194 #define I40E_INSET_IPV6_TC 0x0000000000080000ULL
195 #define I40E_INSET_IPV6_FLOW 0x0000000000100000ULL
196 #define I40E_INSET_IPV6_NEXT_HDR 0x0000000000200000ULL
197 #define I40E_INSET_IPV6_HOP_LIMIT 0x0000000000400000ULL
198 #define I40E_INSET_TCP_FLAGS 0x0000000000800000ULL
200 /* bit 32 ~ bit 47, tunnel fields */
201 #define I40E_INSET_TUNNEL_IPV4_DST 0x0000000100000000ULL
202 #define I40E_INSET_TUNNEL_IPV6_DST 0x0000000200000000ULL
203 #define I40E_INSET_TUNNEL_DMAC 0x0000000400000000ULL
204 #define I40E_INSET_TUNNEL_SRC_PORT 0x0000000800000000ULL
205 #define I40E_INSET_TUNNEL_DST_PORT 0x0000001000000000ULL
206 #define I40E_INSET_TUNNEL_ID 0x0000002000000000ULL
208 /* bit 48 ~ bit 55 */
209 #define I40E_INSET_LAST_ETHER_TYPE 0x0001000000000000ULL
211 /* bit 56 ~ bit 63, Flex Payload */
212 #define I40E_INSET_FLEX_PAYLOAD_W1 0x0100000000000000ULL
213 #define I40E_INSET_FLEX_PAYLOAD_W2 0x0200000000000000ULL
214 #define I40E_INSET_FLEX_PAYLOAD_W3 0x0400000000000000ULL
215 #define I40E_INSET_FLEX_PAYLOAD_W4 0x0800000000000000ULL
216 #define I40E_INSET_FLEX_PAYLOAD_W5 0x1000000000000000ULL
217 #define I40E_INSET_FLEX_PAYLOAD_W6 0x2000000000000000ULL
218 #define I40E_INSET_FLEX_PAYLOAD_W7 0x4000000000000000ULL
219 #define I40E_INSET_FLEX_PAYLOAD_W8 0x8000000000000000ULL
220 #define I40E_INSET_FLEX_PAYLOAD \
221 (I40E_INSET_FLEX_PAYLOAD_W1 | I40E_INSET_FLEX_PAYLOAD_W2 | \
222 I40E_INSET_FLEX_PAYLOAD_W3 | I40E_INSET_FLEX_PAYLOAD_W4 | \
223 I40E_INSET_FLEX_PAYLOAD_W5 | I40E_INSET_FLEX_PAYLOAD_W6 | \
224 I40E_INSET_FLEX_PAYLOAD_W7 | I40E_INSET_FLEX_PAYLOAD_W8)
226 /* The max bandwidth of i40e is 40Gbps. */
227 #define I40E_QOS_BW_MAX 40000
228 /* The bandwidth should be the multiple of 50Mbps. */
229 #define I40E_QOS_BW_GRANULARITY 50
230 /* The min bandwidth weight is 1. */
231 #define I40E_QOS_BW_WEIGHT_MIN 1
232 /* The max bandwidth weight is 127. */
233 #define I40E_QOS_BW_WEIGHT_MAX 127
234 /* The max queue region index is 7. */
235 #define I40E_REGION_MAX_INDEX 7
237 #define I40E_MAX_PERCENT 100
238 #define I40E_DEFAULT_DCB_APP_NUM 1
239 #define I40E_DEFAULT_DCB_APP_PRIO 3
242 * The overhead from MTU to max frame size.
243 * Considering QinQ packet, the VLAN tag needs to be counted twice.
245 #define I40E_ETH_OVERHEAD \
246 (ETHER_HDR_LEN + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE * 2)
251 * MAC filter structure
253 struct i40e_mac_filter_info {
254 enum rte_mac_filter_type filter_type;
255 struct ether_addr mac_addr;
258 TAILQ_HEAD(i40e_mac_filter_list, i40e_mac_filter);
260 /* MAC filter list structure */
261 struct i40e_mac_filter {
262 TAILQ_ENTRY(i40e_mac_filter) next;
263 struct i40e_mac_filter_info mac_info;
266 TAILQ_HEAD(i40e_vsi_list_head, i40e_vsi_list);
270 /* VSI list structure */
271 struct i40e_vsi_list {
272 TAILQ_ENTRY(i40e_vsi_list) list;
273 struct i40e_vsi *vsi;
276 struct i40e_rx_queue;
277 struct i40e_tx_queue;
279 /* Bandwidth limit information */
280 struct i40e_bw_info {
281 uint16_t bw_limit; /* BW Limit (0 = disabled) */
282 uint8_t bw_max; /* Max BW limit if enabled */
284 /* Relative credits within same TC with respect to other VSIs or Comps */
285 uint8_t bw_ets_share_credits[I40E_MAX_TRAFFIC_CLASS];
286 /* Bandwidth limit per TC */
287 uint16_t bw_ets_credits[I40E_MAX_TRAFFIC_CLASS];
288 /* Max bandwidth limit per TC */
289 uint8_t bw_ets_max[I40E_MAX_TRAFFIC_CLASS];
292 /* Structure that defines a VEB */
294 struct i40e_vsi_list_head head;
295 struct i40e_vsi *associate_vsi; /* Associate VSI who owns the VEB */
296 struct i40e_pf *associate_pf; /* Associate PF who owns the VEB */
297 uint16_t seid; /* The seid of VEB itself */
298 uint16_t uplink_seid; /* The uplink seid of this VEB */
300 struct i40e_eth_stats stats;
301 uint8_t enabled_tc; /* The traffic class enabled */
302 uint8_t strict_prio_tc; /* bit map of TCs set to strict priority mode */
303 struct i40e_bw_info bw_info; /* VEB bandwidth information */
306 /* i40e MACVLAN filter structure */
307 struct i40e_macvlan_filter {
308 struct ether_addr macaddr;
309 enum rte_mac_filter_type filter_type;
314 * Structure that defines a VSI, associated with a adapter.
317 struct i40e_adapter *adapter; /* Backreference to associated adapter */
318 struct i40e_aqc_vsi_properties_data info; /* VSI properties */
320 struct i40e_eth_stats eth_stats_offset;
321 struct i40e_eth_stats eth_stats;
323 * When drivers loaded, only a default main VSI exists. In case new VSI
324 * needs to add, HW needs to know the layout that VSIs are organized.
325 * Besides that, VSI isan element and can't switch packets, which needs
326 * to add new component VEB to perform switching. So, a new VSI needs
327 * to specify the the uplink VSI (Parent VSI) before created. The
328 * uplink VSI will check whether it had a VEB to switch packets. If no,
329 * it will try to create one. Then, uplink VSI will move the new VSI
330 * into its' sib_vsi_list to manage all the downlink VSI.
331 * sib_vsi_list: the VSI list that shared the same uplink VSI.
332 * parent_vsi : the uplink VSI. It's NULL for main VSI.
333 * veb : the VEB associates with the VSI.
335 struct i40e_vsi_list sib_vsi_list; /* sibling vsi list */
336 struct i40e_vsi *parent_vsi;
337 struct i40e_veb *veb; /* Associated veb, could be null */
338 struct i40e_veb *floating_veb; /* Associated floating veb */
340 enum i40e_vsi_type type; /* VSI types */
341 uint16_t vlan_num; /* Total VLAN number */
342 uint16_t mac_num; /* Total mac number */
343 uint32_t vfta[I40E_VFTA_SIZE]; /* VLAN bitmap */
344 struct i40e_mac_filter_list mac_list; /* macvlan filter list */
345 /* specific VSI-defined parameters, SRIOV stored the vf_id */
347 uint16_t seid; /* The seid of VSI itself */
348 uint16_t uplink_seid; /* The uplink seid of this VSI */
349 uint16_t nb_qps; /* Number of queue pairs VSI can occupy */
350 uint16_t nb_used_qps; /* Number of queue pairs VSI uses */
351 uint16_t max_macaddrs; /* Maximum number of MAC addresses */
352 uint16_t base_queue; /* The first queue index of this VSI */
354 * The offset to visit VSI related register, assigned by HW when
358 uint16_t msix_intr; /* The MSIX interrupt binds to VSI */
359 uint16_t nb_msix; /* The max number of msix vector */
360 uint8_t enabled_tc; /* The traffic class enabled */
361 uint8_t vlan_anti_spoof_on; /* The VLAN anti-spoofing enabled */
362 uint8_t vlan_filter_on; /* The VLAN filter enabled */
363 struct i40e_bw_info bw_info; /* VSI bandwidth information */
367 LIST_ENTRY(pool_entry) next;
372 LIST_HEAD(res_list, pool_entry);
374 struct i40e_res_pool_info {
375 uint32_t base; /* Resource start index */
376 uint32_t num_alloc; /* Allocated resource number */
377 uint32_t num_free; /* Total available resource number */
378 struct res_list alloc_list; /* Allocated resource list */
379 struct res_list free_list; /* Available resource list */
383 I40E_VF_INACTIVE = 0,
390 * Structure to store private data for PF host.
394 struct i40e_vsi *vsi;
395 enum I40E_VF_STATE state; /* The number of queue pairs available */
396 uint16_t vf_idx; /* VF index in pf->vfs */
397 uint16_t lan_nb_qps; /* Actual queues allocated */
398 uint16_t reset_cnt; /* Total vf reset times */
399 struct ether_addr mac_addr; /* Default MAC address */
403 * Structure to store private data for flow control.
405 struct i40e_fc_conf {
406 uint16_t pause_time; /* Flow control pause timer */
407 /* FC high water 0-7 for pfc and 8 for lfc unit:kilobytes */
408 uint32_t high_water[I40E_MAX_TRAFFIC_CLASS + 1];
409 /* FC low water 0-7 for pfc and 8 for lfc unit:kilobytes */
410 uint32_t low_water[I40E_MAX_TRAFFIC_CLASS + 1];
414 * Structure to store private data for VMDQ instance
416 struct i40e_vmdq_info {
418 struct i40e_vsi *vsi;
421 #define I40E_FDIR_MAX_FLEXLEN 16 /**< Max length of flexbytes. */
422 #define I40E_MAX_FLX_SOURCE_OFF 480
423 #define NONUSE_FLX_PIT_DEST_OFF 63
424 #define NONUSE_FLX_PIT_FSIZE 1
425 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR 50
426 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
427 (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
428 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
429 (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
430 I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
431 ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
432 NONUSE_FLX_PIT_DEST_OFF : \
433 ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
434 I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
435 I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
436 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
437 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
438 #define I40E_FDIR_IPv6_TC_OFFSET 20
440 /* A structure used to define the input for GTP flow */
441 struct i40e_gtp_flow {
442 struct rte_eth_udpv4_flow udp; /* IPv4 UDP fields to match. */
443 uint8_t msg_type; /* Message type. */
444 uint32_t teid; /* TEID in big endian. */
447 /* A structure used to define the input for GTP IPV4 flow */
448 struct i40e_gtp_ipv4_flow {
449 struct i40e_gtp_flow gtp;
450 struct rte_eth_ipv4_flow ip4;
453 /* A structure used to define the input for GTP IPV6 flow */
454 struct i40e_gtp_ipv6_flow {
455 struct i40e_gtp_flow gtp;
456 struct rte_eth_ipv6_flow ip6;
459 /* A structure used to define the input for raw type flow */
460 struct i40e_raw_flow {
467 * A union contains the inputs for all types of flow
468 * items in flows need to be in big endian
470 union i40e_fdir_flow {
471 struct rte_eth_l2_flow l2_flow;
472 struct rte_eth_udpv4_flow udp4_flow;
473 struct rte_eth_tcpv4_flow tcp4_flow;
474 struct rte_eth_sctpv4_flow sctp4_flow;
475 struct rte_eth_ipv4_flow ip4_flow;
476 struct rte_eth_udpv6_flow udp6_flow;
477 struct rte_eth_tcpv6_flow tcp6_flow;
478 struct rte_eth_sctpv6_flow sctp6_flow;
479 struct rte_eth_ipv6_flow ipv6_flow;
480 struct i40e_gtp_flow gtp_flow;
481 struct i40e_gtp_ipv4_flow gtp_ipv4_flow;
482 struct i40e_gtp_ipv6_flow gtp_ipv6_flow;
483 struct i40e_raw_flow raw_flow;
486 enum i40e_fdir_ip_type {
487 I40E_FDIR_IPTYPE_IPV4,
488 I40E_FDIR_IPTYPE_IPV6,
491 /* A structure used to contain extend input of flow */
492 struct i40e_fdir_flow_ext {
494 uint8_t flexbytes[RTE_ETH_FDIR_MAX_FLEXLEN];
495 /* It is filled by the flexible payload to match. */
496 uint8_t is_vf; /* 1 for VF, 0 for port dev */
497 uint16_t dst_id; /* VF ID, available when is_vf is 1*/
498 bool inner_ip; /* If there is inner ip */
499 enum i40e_fdir_ip_type iip_type; /* ip type for inner ip */
500 bool customized_pctype; /* If customized pctype is used */
501 bool pkt_template; /* If raw packet template is used */
504 /* A structure used to define the input for a flow director filter entry */
505 struct i40e_fdir_input {
506 enum i40e_filter_pctype pctype;
507 union i40e_fdir_flow flow;
508 /* Flow fields to match, dependent on flow_type */
509 struct i40e_fdir_flow_ext flow_ext;
510 /* Additional fields to match */
513 /* Behavior will be taken if FDIR match */
514 enum i40e_fdir_behavior {
515 I40E_FDIR_ACCEPT = 0,
520 /* Flow director report status
521 * It defines what will be reported if FDIR entry is matched.
523 enum i40e_fdir_status {
524 I40E_FDIR_NO_REPORT_STATUS = 0, /* Report nothing. */
525 I40E_FDIR_REPORT_ID, /* Only report FD ID. */
526 I40E_FDIR_REPORT_ID_FLEX_4, /* Report FD ID and 4 flex bytes. */
527 I40E_FDIR_REPORT_FLEX_8, /* Report 8 flex bytes. */
530 /* A structure used to define an action when match FDIR packet filter. */
531 struct i40e_fdir_action {
532 uint16_t rx_queue; /* Queue assigned to if FDIR match. */
533 enum i40e_fdir_behavior behavior; /* Behavior will be taken */
534 enum i40e_fdir_status report_status; /* Status report option */
535 /* If report_status is I40E_FDIR_REPORT_ID_FLEX_4 or
536 * I40E_FDIR_REPORT_FLEX_8, flex_off specifies where the reported
537 * flex bytes start from in flexible payload.
542 /* A structure used to define the flow director filter entry by filter_ctrl API
543 * It supports RTE_ETH_FILTER_FDIR with RTE_ETH_FILTER_ADD and
544 * RTE_ETH_FILTER_DELETE operations.
546 struct i40e_fdir_filter_conf {
548 /* ID, an unique value is required when deal with FDIR entry */
549 struct i40e_fdir_input input; /* Input set */
550 struct i40e_fdir_action action; /* Action taken when match */
554 * Structure to store flex pit for flow diretor.
556 struct i40e_fdir_flex_pit {
557 uint8_t src_offset; /* offset in words from the beginning of payload */
558 uint8_t size; /* size in words */
559 uint8_t dst_offset; /* offset in words of flexible payload */
562 struct i40e_fdir_flex_mask {
563 uint8_t word_mask; /**< Bit i enables word i of flexible payload */
568 } bitmask[I40E_FDIR_BITMASK_NUM_WORD];
571 #define I40E_FILTER_PCTYPE_INVALID 0
572 #define I40E_FILTER_PCTYPE_MAX 64
573 #define I40E_MAX_FDIR_FILTER_NUM (1024 * 8)
575 struct i40e_fdir_filter {
576 TAILQ_ENTRY(i40e_fdir_filter) rules;
577 struct i40e_fdir_filter_conf fdir;
580 TAILQ_HEAD(i40e_fdir_filter_list, i40e_fdir_filter);
582 * A structure used to define fields of a FDIR related info.
584 struct i40e_fdir_info {
585 struct i40e_vsi *fdir_vsi; /* pointer to fdir VSI structure */
586 uint16_t match_counter_index; /* Statistic counter index used for fdir*/
587 struct i40e_tx_queue *txq;
588 struct i40e_rx_queue *rxq;
589 void *prg_pkt; /* memory for fdir program packet */
590 uint64_t dma_addr; /* physic address of packet memory*/
591 /* input set bits for each pctype */
592 uint64_t input_set[I40E_FILTER_PCTYPE_MAX];
594 * the rule how bytes stream is extracted as flexible payload
595 * for each payload layer, the setting can up to three elements
597 struct i40e_fdir_flex_pit flex_set[I40E_MAX_FLXPLD_LAYER * I40E_MAX_FLXPLD_FIED];
598 struct i40e_fdir_flex_mask flex_mask[I40E_FILTER_PCTYPE_MAX];
600 struct i40e_fdir_filter_list fdir_list;
601 struct i40e_fdir_filter **hash_map;
602 struct rte_hash *hash_table;
604 /* Mark if flex pit and mask is set */
605 bool flex_pit_flag[I40E_MAX_FLXPLD_LAYER];
606 bool flex_mask_flag[I40E_FILTER_PCTYPE_MAX];
608 bool inset_flag[I40E_FILTER_PCTYPE_MAX]; /* Mark if input set is set */
611 /* Ethertype filter number HW supports */
612 #define I40E_MAX_ETHERTYPE_FILTER_NUM 768
614 /* Ethertype filter struct */
615 struct i40e_ethertype_filter_input {
616 struct ether_addr mac_addr; /* Mac address to match */
617 uint16_t ether_type; /* Ether type to match */
620 struct i40e_ethertype_filter {
621 TAILQ_ENTRY(i40e_ethertype_filter) rules;
622 struct i40e_ethertype_filter_input input;
623 uint16_t flags; /* Flags from RTE_ETHTYPE_FLAGS_* */
624 uint16_t queue; /* Queue assigned to when match */
627 TAILQ_HEAD(i40e_ethertype_filter_list, i40e_ethertype_filter);
629 struct i40e_ethertype_rule {
630 struct i40e_ethertype_filter_list ethertype_list;
631 struct i40e_ethertype_filter **hash_map;
632 struct rte_hash *hash_table;
635 /* queue region info */
636 struct i40e_queue_region_info {
637 /* the region id for this configuration */
639 /* the start queue index for this region */
640 uint8_t queue_start_index;
641 /* the total queue number of this queue region */
643 /* the total number of user priority for this region */
644 uint8_t user_priority_num;
645 /* the packet's user priority for this region */
646 uint8_t user_priority[I40E_MAX_USER_PRIORITY];
647 /* the total number of flowtype for this region */
648 uint8_t flowtype_num;
650 * the pctype or hardware flowtype of packet,
651 * the specific index for each type has been defined
652 * in file i40e_type.h as enum i40e_filter_pctype.
654 uint8_t hw_flowtype[I40E_FILTER_PCTYPE_MAX];
657 struct i40e_queue_regions {
658 /* the total number of queue region for this port */
659 uint16_t queue_region_number;
660 struct i40e_queue_region_info region[I40E_REGION_MAX_INDEX + 1];
663 /* Tunnel filter number HW supports */
664 #define I40E_MAX_TUNNEL_FILTER_NUM 400
666 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD0 44
667 #define I40E_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TEID_WORD1 45
668 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOUDP 8
669 #define I40E_AQC_ADD_CLOUD_TNL_TYPE_MPLSOGRE 9
670 #define I40E_AQC_ADD_CLOUD_FILTER_0X10 0x10
671 #define I40E_AQC_ADD_CLOUD_FILTER_0X11 0x11
672 #define I40E_AQC_ADD_CLOUD_FILTER_0X12 0x12
673 #define I40E_AQC_ADD_L1_FILTER_0X11 0x11
674 #define I40E_AQC_ADD_L1_FILTER_0X12 0x12
675 #define I40E_AQC_ADD_L1_FILTER_0X13 0x13
676 #define I40E_AQC_NEW_TR_21 21
677 #define I40E_AQC_NEW_TR_22 22
679 enum i40e_tunnel_iptype {
680 I40E_TUNNEL_IPTYPE_IPV4,
681 I40E_TUNNEL_IPTYPE_IPV6,
684 /* Tunnel filter struct */
685 struct i40e_tunnel_filter_input {
686 uint8_t outer_mac[6]; /* Outer mac address to match */
687 uint8_t inner_mac[6]; /* Inner mac address to match */
688 uint16_t inner_vlan; /* Inner vlan address to match */
689 enum i40e_tunnel_iptype ip_type;
690 uint16_t flags; /* Filter type flag */
691 uint32_t tenant_id; /* Tenant id to match */
692 uint16_t general_fields[32]; /* Big buffer */
695 struct i40e_tunnel_filter {
696 TAILQ_ENTRY(i40e_tunnel_filter) rules;
697 struct i40e_tunnel_filter_input input;
698 uint8_t is_to_vf; /* 0 - to PF, 1 - to VF */
699 uint16_t vf_id; /* VF id, avaiblable when is_to_vf is 1. */
700 uint16_t queue; /* Queue assigned to when match */
703 TAILQ_HEAD(i40e_tunnel_filter_list, i40e_tunnel_filter);
705 struct i40e_tunnel_rule {
706 struct i40e_tunnel_filter_list tunnel_list;
707 struct i40e_tunnel_filter **hash_map;
708 struct rte_hash *hash_table;
714 enum i40e_tunnel_type {
715 I40E_TUNNEL_TYPE_NONE = 0,
716 I40E_TUNNEL_TYPE_VXLAN,
717 I40E_TUNNEL_TYPE_GENEVE,
718 I40E_TUNNEL_TYPE_TEREDO,
719 I40E_TUNNEL_TYPE_NVGRE,
720 I40E_TUNNEL_TYPE_IP_IN_GRE,
721 I40E_L2_TUNNEL_TYPE_E_TAG,
722 I40E_TUNNEL_TYPE_MPLSoUDP,
723 I40E_TUNNEL_TYPE_MPLSoGRE,
724 I40E_TUNNEL_TYPE_QINQ,
725 I40E_TUNNEL_TYPE_GTPC,
726 I40E_TUNNEL_TYPE_GTPU,
727 I40E_TUNNEL_TYPE_MAX,
731 * Tunneling Packet filter configuration.
733 struct i40e_tunnel_filter_conf {
734 struct ether_addr outer_mac; /**< Outer MAC address to match. */
735 struct ether_addr inner_mac; /**< Inner MAC address to match. */
736 uint16_t inner_vlan; /**< Inner VLAN to match. */
737 uint32_t outer_vlan; /**< Outer VLAN to match */
738 enum i40e_tunnel_iptype ip_type; /**< IP address type. */
740 * Outer destination IP address to match if ETH_TUNNEL_FILTER_OIP
741 * is set in filter_type, or inner destination IP address to match
742 * if ETH_TUNNEL_FILTER_IIP is set in filter_type.
745 uint32_t ipv4_addr; /**< IPv4 address in big endian. */
746 uint32_t ipv6_addr[4]; /**< IPv6 address in big endian. */
748 /** Flags from ETH_TUNNEL_FILTER_XX - see above. */
749 uint16_t filter_type;
750 enum i40e_tunnel_type tunnel_type; /**< Tunnel Type. */
751 uint32_t tenant_id; /**< Tenant ID to match. VNI, GRE key... */
752 uint16_t queue_id; /**< Queue assigned to if match. */
753 uint8_t is_to_vf; /**< 0 - to PF, 1 - to VF */
754 uint16_t vf_id; /**< VF id, avaiblable when is_to_vf is 1. */
757 #define I40E_MIRROR_MAX_ENTRIES_PER_RULE 64
758 #define I40E_MAX_MIRROR_RULES 64
760 * Mirror rule structure
762 struct i40e_mirror_rule {
763 TAILQ_ENTRY(i40e_mirror_rule) rules;
765 uint16_t index; /* the sw index of mirror rule */
766 uint16_t id; /* the rule id assigned by firmware */
767 uint16_t dst_vsi_seid; /* destination vsi for this mirror rule. */
768 uint16_t num_entries;
769 /* the info stores depend on the rule type.
770 If type is I40E_MIRROR_TYPE_VLAN, vlan ids are stored here.
771 If type is I40E_MIRROR_TYPE_VPORT_*, vsi's seid are stored.
773 uint16_t entries[I40E_MIRROR_MAX_ENTRIES_PER_RULE];
776 TAILQ_HEAD(i40e_mirror_rule_list, i40e_mirror_rule);
779 * Struct to store flow created.
782 TAILQ_ENTRY(rte_flow) node;
783 enum rte_filter_type filter_type;
787 TAILQ_HEAD(i40e_flow_list, rte_flow);
789 /* Struct to store Traffic Manager shaper profile. */
790 struct i40e_tm_shaper_profile {
791 TAILQ_ENTRY(i40e_tm_shaper_profile) node;
792 uint32_t shaper_profile_id;
793 uint32_t reference_count;
794 struct rte_tm_shaper_params profile;
797 TAILQ_HEAD(i40e_shaper_profile_list, i40e_tm_shaper_profile);
799 /* node type of Traffic Manager */
800 enum i40e_tm_node_type {
801 I40E_TM_NODE_TYPE_PORT,
802 I40E_TM_NODE_TYPE_TC,
803 I40E_TM_NODE_TYPE_QUEUE,
804 I40E_TM_NODE_TYPE_MAX,
807 /* Struct to store Traffic Manager node configuration. */
808 struct i40e_tm_node {
809 TAILQ_ENTRY(i40e_tm_node) node;
813 uint32_t reference_count;
814 struct i40e_tm_node *parent;
815 struct i40e_tm_shaper_profile *shaper_profile;
816 struct rte_tm_node_params params;
819 TAILQ_HEAD(i40e_tm_node_list, i40e_tm_node);
821 /* Struct to store all the Traffic Manager configuration. */
822 struct i40e_tm_conf {
823 struct i40e_shaper_profile_list shaper_profile_list;
824 struct i40e_tm_node *root; /* root node - port */
825 struct i40e_tm_node_list tc_list; /* node list for all the TCs */
826 struct i40e_tm_node_list queue_list; /* node list for all the queues */
828 * The number of added TC nodes.
829 * It should be no more than the TC number of this port.
833 * The number of added queue nodes.
834 * It should be no more than the queue number of this port.
836 uint32_t nb_queue_node;
838 * This flag is used to check if APP can change the TM node
840 * When it's true, means the configuration is applied to HW,
841 * APP should not change the configuration.
842 * As we don't support on-the-fly configuration, when starting
843 * the port, APP should call the hierarchy_commit API to set this
844 * flag to true. When stopping the port, this flag should be set
850 enum i40e_new_pctype {
851 I40E_CUSTOMIZED_GTPC = 0,
852 I40E_CUSTOMIZED_GTPU_IPV4,
853 I40E_CUSTOMIZED_GTPU_IPV6,
854 I40E_CUSTOMIZED_GTPU,
858 #define I40E_FILTER_PCTYPE_INVALID 0
859 struct i40e_customized_pctype {
860 enum i40e_new_pctype index; /* Indicate which customized pctype */
861 uint8_t pctype; /* New pctype value */
862 bool valid; /* Check if it's valid */
866 * Structure to store private data specific for PF instance.
869 struct i40e_adapter *adapter; /* The adapter this PF associate to */
870 struct i40e_vsi *main_vsi; /* pointer to main VSI structure */
871 uint16_t mac_seid; /* The seid of the MAC of this PF */
872 uint16_t main_vsi_seid; /* The seid of the main VSI */
873 uint16_t max_num_vsi;
874 struct i40e_res_pool_info qp_pool; /*Queue pair pool */
875 struct i40e_res_pool_info msix_pool; /* MSIX interrupt pool */
877 struct i40e_hw_port_stats stats_offset;
878 struct i40e_hw_port_stats stats;
879 /* internal packet statistics, it should be excluded from the total */
880 struct i40e_eth_stats internal_stats_offset;
881 struct i40e_eth_stats internal_stats;
884 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
885 struct ether_addr dev_addr; /* PF device mac address */
886 uint64_t flags; /* PF feature flags */
887 /* All kinds of queue pair setting for different VSIs */
888 struct i40e_pf_vf *vfs;
890 /* Each of below queue pairs should be power of 2 since it's the
891 precondition after TC configuration applied */
892 uint16_t lan_nb_qp_max;
893 uint16_t lan_nb_qps; /* The number of queue pairs of LAN */
894 uint16_t lan_qp_offset;
895 uint16_t vmdq_nb_qp_max;
896 uint16_t vmdq_nb_qps; /* The number of queue pairs of VMDq */
897 uint16_t vmdq_qp_offset;
898 uint16_t vf_nb_qp_max;
899 uint16_t vf_nb_qps; /* The number of queue pairs of VF */
900 uint16_t vf_qp_offset;
901 uint16_t fdir_nb_qps; /* The number of queue pairs of Flow Director */
902 uint16_t fdir_qp_offset;
904 uint16_t hash_lut_size; /* The size of hash lookup table */
905 /* input set bits for each pctype */
906 uint64_t hash_input_set[I40E_FILTER_PCTYPE_MAX];
907 /* store VXLAN UDP ports */
908 uint16_t vxlan_ports[I40E_MAX_PF_UDP_OFFLOAD_PORTS];
909 uint16_t vxlan_bitmap; /* Vxlan bit mask */
911 /* VMDQ related info */
912 uint16_t max_nb_vmdq_vsi; /* Max number of VMDQ VSIs supported */
913 uint16_t nb_cfg_vmdq_vsi; /* number of VMDQ VSIs configured */
914 struct i40e_vmdq_info *vmdq;
916 struct i40e_fdir_info fdir; /* flow director info */
917 struct i40e_ethertype_rule ethertype; /* Ethertype filter rule */
918 struct i40e_tunnel_rule tunnel; /* Tunnel filter rule */
919 struct i40e_queue_regions queue_region; /* queue region info */
920 struct i40e_fc_conf fc_conf; /* Flow control conf */
921 struct i40e_mirror_rule_list mirror_list;
922 uint16_t nb_mirror_rule; /* The number of mirror rules */
923 bool floating_veb; /* The flag to use the floating VEB */
924 /* The floating enable flag for the specific VF */
925 bool floating_veb_list[I40E_MAX_VF];
926 struct i40e_flow_list flow_list;
927 bool mpls_replace_flag; /* 1 - MPLS filter replace is done */
928 bool gtp_replace_flag; /* 1 - GTP-C/U filter replace is done */
929 bool qinq_replace_flag; /* QINQ filter replace is done */
930 struct i40e_tm_conf tm_conf;
932 /* Dynamic Device Personalization */
933 bool gtp_support; /* 1 - support GTP-C and GTP-U */
934 /* customer customized pctype */
935 struct i40e_customized_pctype customized_pctype[I40E_CUSTOMIZED_MAX];
939 PFMSG_LINK_CHANGE = 0x1,
940 PFMSG_RESET_IMPENDING = 0x2,
941 PFMSG_DRIVER_CLOSE = 0x4,
944 struct i40e_vsi_vlan_pvid_info {
945 uint16_t on; /* Enable or disable pvid */
947 uint16_t pvid; /* Valid in case 'on' is set to set pvid */
949 /* Valid in case 'on' is cleared. 'tagged' will reject tagged packets,
950 * while 'untagged' will reject untagged packets.
958 struct i40e_vf_rx_queues {
959 uint64_t rx_dma_addr;
960 uint32_t rx_ring_len;
964 struct i40e_vf_tx_queues {
965 uint64_t tx_dma_addr;
966 uint32_t tx_ring_len;
970 * Structure to store private data specific for VF instance.
973 struct i40e_adapter *adapter; /* The adapter this VF associate to */
974 struct rte_eth_dev_data *dev_data; /* Pointer to the device data */
975 uint16_t num_queue_pairs;
976 uint16_t max_pkt_len; /* Maximum packet length */
977 bool promisc_unicast_enabled;
978 bool promisc_multicast_enabled;
980 uint32_t version_major; /* Major version number */
981 uint32_t version_minor; /* Minor version number */
982 uint16_t promisc_flags; /* Promiscuous setting */
983 uint32_t vlan[I40E_VFTA_SIZE]; /* VLAN bit map */
988 enum virtchnl_link_speed link_speed;
990 volatile uint32_t pend_cmd; /* pending command not finished yet */
991 int32_t cmd_retval; /* return value of the cmd response from PF */
992 u16 pend_msg; /* flags indicates events from pf not handled yet */
993 uint8_t *aq_resp; /* buffer to store the adminq response from PF */
996 struct virtchnl_vf_resource *vf_res; /* All VSIs */
997 struct virtchnl_vsi_resource *vsi_res; /* LAN VSI */
1002 #define I40E_MAX_PKT_TYPE 256
1003 #define I40E_FLOW_TYPE_MAX 64
1006 * Structure to store private data for each PF/VF instance.
1008 struct i40e_adapter {
1009 /* Common for both PF and VF */
1011 struct rte_eth_dev *eth_dev;
1013 /* Specific for PF or VF */
1019 /* For vector PMD */
1020 bool rx_bulk_alloc_allowed;
1021 bool rx_vec_allowed;
1022 bool tx_simple_allowed;
1023 bool tx_vec_allowed;
1026 struct rte_timecounter systime_tc;
1027 struct rte_timecounter rx_tstamp_tc;
1028 struct rte_timecounter tx_tstamp_tc;
1030 /* ptype mapping table */
1031 uint32_t ptype_tbl[I40E_MAX_PKT_TYPE] __rte_cache_min_aligned;
1032 /* flow type to pctype mapping table */
1033 uint64_t pctypes_tbl[I40E_FLOW_TYPE_MAX] __rte_cache_min_aligned;
1034 uint64_t flow_types_mask;
1035 uint64_t pctypes_mask;
1038 extern const struct rte_flow_ops i40e_flow_ops;
1040 union i40e_filter_t {
1041 struct rte_eth_ethertype_filter ethertype_filter;
1042 struct i40e_fdir_filter_conf fdir_filter;
1043 struct rte_eth_tunnel_filter_conf tunnel_filter;
1044 struct i40e_tunnel_filter_conf consistent_tunnel_filter;
1047 typedef int (*parse_filter_t)(struct rte_eth_dev *dev,
1048 const struct rte_flow_attr *attr,
1049 const struct rte_flow_item pattern[],
1050 const struct rte_flow_action actions[],
1051 struct rte_flow_error *error,
1052 union i40e_filter_t *filter);
1053 struct i40e_valid_pattern {
1054 enum rte_flow_item_type *items;
1055 parse_filter_t parse_filter;
1058 int i40e_dev_switch_queues(struct i40e_pf *pf, bool on);
1059 int i40e_vsi_release(struct i40e_vsi *vsi);
1060 struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf,
1061 enum i40e_vsi_type type,
1062 struct i40e_vsi *uplink_vsi,
1063 uint16_t user_param);
1064 int i40e_switch_rx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1065 int i40e_switch_tx_queue(struct i40e_hw *hw, uint16_t q_idx, bool on);
1066 int i40e_vsi_add_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1067 int i40e_vsi_delete_vlan(struct i40e_vsi *vsi, uint16_t vlan);
1068 int i40e_vsi_add_mac(struct i40e_vsi *vsi, struct i40e_mac_filter_info *filter);
1069 int i40e_vsi_delete_mac(struct i40e_vsi *vsi, struct ether_addr *addr);
1070 void i40e_update_vsi_stats(struct i40e_vsi *vsi);
1071 void i40e_pf_disable_irq0(struct i40e_hw *hw);
1072 void i40e_pf_enable_irq0(struct i40e_hw *hw);
1073 int i40e_dev_link_update(struct rte_eth_dev *dev, int wait_to_complete);
1074 void i40e_vsi_queues_bind_intr(struct i40e_vsi *vsi, uint16_t itr_idx);
1075 void i40e_vsi_queues_unbind_intr(struct i40e_vsi *vsi);
1076 int i40e_vsi_vlan_pvid_set(struct i40e_vsi *vsi,
1077 struct i40e_vsi_vlan_pvid_info *info);
1078 int i40e_vsi_config_vlan_stripping(struct i40e_vsi *vsi, bool on);
1079 int i40e_vsi_config_vlan_filter(struct i40e_vsi *vsi, bool on);
1080 uint64_t i40e_config_hena(const struct i40e_adapter *adapter, uint64_t flags);
1081 uint64_t i40e_parse_hena(const struct i40e_adapter *adapter, uint64_t flags);
1082 enum i40e_status_code i40e_fdir_setup_tx_resources(struct i40e_pf *pf);
1083 enum i40e_status_code i40e_fdir_setup_rx_resources(struct i40e_pf *pf);
1084 int i40e_fdir_setup(struct i40e_pf *pf);
1085 const struct rte_memzone *i40e_memzone_reserve(const char *name,
1088 int i40e_fdir_configure(struct rte_eth_dev *dev);
1089 void i40e_fdir_teardown(struct i40e_pf *pf);
1090 enum i40e_filter_pctype
1091 i40e_flowtype_to_pctype(const struct i40e_adapter *adapter,
1092 uint16_t flow_type);
1093 uint16_t i40e_pctype_to_flowtype(const struct i40e_adapter *adapter,
1094 enum i40e_filter_pctype pctype);
1095 int i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1096 enum rte_filter_op filter_op,
1098 int i40e_select_filter_input_set(struct i40e_hw *hw,
1099 struct rte_eth_input_set_conf *conf,
1100 enum rte_filter_type filter);
1101 void i40e_fdir_filter_restore(struct i40e_pf *pf);
1102 int i40e_hash_filter_inset_select(struct i40e_hw *hw,
1103 struct rte_eth_input_set_conf *conf);
1104 int i40e_fdir_filter_inset_select(struct i40e_pf *pf,
1105 struct rte_eth_input_set_conf *conf);
1106 int i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf, uint32_t opcode,
1107 uint32_t retval, uint8_t *msg,
1109 void i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1110 struct rte_eth_rxq_info *qinfo);
1111 void i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
1112 struct rte_eth_txq_info *qinfo);
1113 struct i40e_ethertype_filter *
1114 i40e_sw_ethertype_filter_lookup(struct i40e_ethertype_rule *ethertype_rule,
1115 const struct i40e_ethertype_filter_input *input);
1116 int i40e_sw_ethertype_filter_del(struct i40e_pf *pf,
1117 struct i40e_ethertype_filter_input *input);
1118 int i40e_sw_fdir_filter_del(struct i40e_pf *pf,
1119 struct i40e_fdir_input *input);
1120 struct i40e_tunnel_filter *
1121 i40e_sw_tunnel_filter_lookup(struct i40e_tunnel_rule *tunnel_rule,
1122 const struct i40e_tunnel_filter_input *input);
1123 int i40e_sw_tunnel_filter_del(struct i40e_pf *pf,
1124 struct i40e_tunnel_filter_input *input);
1125 uint64_t i40e_get_default_input_set(uint16_t pctype);
1126 int i40e_ethertype_filter_set(struct i40e_pf *pf,
1127 struct rte_eth_ethertype_filter *filter,
1129 int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1130 const struct rte_eth_fdir_filter *filter,
1132 int i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1133 const struct i40e_fdir_filter_conf *filter,
1135 int i40e_dev_tunnel_filter_set(struct i40e_pf *pf,
1136 struct rte_eth_tunnel_filter_conf *tunnel_filter,
1138 int i40e_dev_consistent_tunnel_filter_set(struct i40e_pf *pf,
1139 struct i40e_tunnel_filter_conf *tunnel_filter,
1141 int i40e_fdir_flush(struct rte_eth_dev *dev);
1142 int i40e_find_all_vlan_for_mac(struct i40e_vsi *vsi,
1143 struct i40e_macvlan_filter *mv_f,
1144 int num, struct ether_addr *addr);
1145 int i40e_remove_macvlan_filters(struct i40e_vsi *vsi,
1146 struct i40e_macvlan_filter *filter,
1148 void i40e_set_vlan_filter(struct i40e_vsi *vsi, uint16_t vlan_id, bool on);
1149 int i40e_add_macvlan_filters(struct i40e_vsi *vsi,
1150 struct i40e_macvlan_filter *filter,
1152 bool is_i40e_supported(struct rte_eth_dev *dev);
1154 int i40e_validate_input_set(enum i40e_filter_pctype pctype,
1155 enum rte_filter_type filter, uint64_t inset);
1156 int i40e_generate_inset_mask_reg(uint64_t inset, uint32_t *mask,
1158 uint64_t i40e_translate_input_set_reg(enum i40e_mac_type type, uint64_t input);
1159 void i40e_check_write_reg(struct i40e_hw *hw, uint32_t addr, uint32_t val);
1161 int i40e_tm_ops_get(struct rte_eth_dev *dev, void *ops);
1162 void i40e_tm_conf_init(struct rte_eth_dev *dev);
1163 void i40e_tm_conf_uninit(struct rte_eth_dev *dev);
1164 struct i40e_customized_pctype*
1165 i40e_find_customized_pctype(struct i40e_pf *pf, uint8_t index);
1166 void i40e_update_customized_info(struct rte_eth_dev *dev, uint8_t *pkg,
1168 int i40e_dcb_init_configure(struct rte_eth_dev *dev, bool sw_dcb);
1169 int i40e_flush_queue_region_all_conf(struct rte_eth_dev *dev,
1170 struct i40e_hw *hw, struct i40e_pf *pf, uint16_t on);
1171 void i40e_init_queue_region_conf(struct rte_eth_dev *dev);
1173 #define I40E_DEV_TO_PCI(eth_dev) \
1174 RTE_DEV_TO_PCI((eth_dev)->device)
1176 /* I40E_DEV_PRIVATE_TO */
1177 #define I40E_DEV_PRIVATE_TO_PF(adapter) \
1178 (&((struct i40e_adapter *)adapter)->pf)
1179 #define I40E_DEV_PRIVATE_TO_HW(adapter) \
1180 (&((struct i40e_adapter *)adapter)->hw)
1181 #define I40E_DEV_PRIVATE_TO_ADAPTER(adapter) \
1182 ((struct i40e_adapter *)adapter)
1184 /* I40EVF_DEV_PRIVATE_TO */
1185 #define I40EVF_DEV_PRIVATE_TO_VF(adapter) \
1186 (&((struct i40e_adapter *)adapter)->vf)
1188 static inline struct i40e_vsi *
1189 i40e_get_vsi_from_adapter(struct i40e_adapter *adapter)
1196 hw = I40E_DEV_PRIVATE_TO_HW(adapter);
1197 if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1198 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(adapter);
1201 struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(adapter);
1202 return pf->main_vsi;
1205 #define I40E_DEV_PRIVATE_TO_MAIN_VSI(adapter) \
1206 i40e_get_vsi_from_adapter((struct i40e_adapter *)adapter)
1209 #define I40E_VSI_TO_HW(vsi) \
1210 (&(((struct i40e_vsi *)vsi)->adapter->hw))
1211 #define I40E_VSI_TO_PF(vsi) \
1212 (&(((struct i40e_vsi *)vsi)->adapter->pf))
1213 #define I40E_VSI_TO_VF(vsi) \
1214 (&(((struct i40e_vsi *)vsi)->adapter->vf))
1215 #define I40E_VSI_TO_DEV_DATA(vsi) \
1216 (((struct i40e_vsi *)vsi)->adapter->pf.dev_data)
1217 #define I40E_VSI_TO_ETH_DEV(vsi) \
1218 (((struct i40e_vsi *)vsi)->adapter->eth_dev)
1221 #define I40E_PF_TO_HW(pf) \
1222 (&(((struct i40e_pf *)pf)->adapter->hw))
1223 #define I40E_PF_TO_ADAPTER(pf) \
1224 ((struct i40e_adapter *)pf->adapter)
1227 #define I40E_VF_TO_HW(vf) \
1228 (&(((struct i40e_vf *)vf)->adapter->hw))
1231 i40e_init_adminq_parameter(struct i40e_hw *hw)
1233 hw->aq.num_arq_entries = I40E_AQ_LEN;
1234 hw->aq.num_asq_entries = I40E_AQ_LEN;
1235 hw->aq.arq_buf_size = I40E_AQ_BUF_SZ;
1236 hw->aq.asq_buf_size = I40E_AQ_BUF_SZ;
1240 i40e_align_floor(int n)
1244 return 1 << (sizeof(n) * CHAR_BIT - 1 - __builtin_clz(n));
1247 static inline uint16_t
1248 i40e_calc_itr_interval(int16_t interval)
1250 if (interval < 0 || interval > I40E_QUEUE_ITR_INTERVAL_MAX)
1251 interval = I40E_QUEUE_ITR_INTERVAL_DEFAULT;
1253 /* Convert to hardware count, as writing each 1 represents 2 us */
1254 return interval / 2;
1257 #define I40E_VALID_FLOW(flow_type) \
1258 ((flow_type) == RTE_ETH_FLOW_FRAG_IPV4 || \
1259 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_TCP || \
1260 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_UDP || \
1261 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_SCTP || \
1262 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV4_OTHER || \
1263 (flow_type) == RTE_ETH_FLOW_FRAG_IPV6 || \
1264 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_TCP || \
1265 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_UDP || \
1266 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_SCTP || \
1267 (flow_type) == RTE_ETH_FLOW_NONFRAG_IPV6_OTHER || \
1268 (flow_type) == RTE_ETH_FLOW_L2_PAYLOAD)
1270 #define I40E_VALID_PCTYPE_X722(pctype) \
1271 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1272 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1273 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK || \
1274 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1275 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP || \
1276 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP || \
1277 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1278 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1279 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1280 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1281 (pctype) == I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP || \
1282 (pctype) == I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP || \
1283 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1284 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK || \
1285 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1286 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1287 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1289 #define I40E_VALID_PCTYPE(pctype) \
1290 ((pctype) == I40E_FILTER_PCTYPE_FRAG_IPV4 || \
1291 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_TCP || \
1292 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_UDP || \
1293 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP || \
1294 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER || \
1295 (pctype) == I40E_FILTER_PCTYPE_FRAG_IPV6 || \
1296 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_UDP || \
1297 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_TCP || \
1298 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP || \
1299 (pctype) == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER || \
1300 (pctype) == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1302 #define I40E_PHY_TYPE_SUPPORT_40G(phy_type) \
1303 (((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_KR4) || \
1304 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4_CU) || \
1305 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_AOC) || \
1306 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_CR4) || \
1307 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_SR4) || \
1308 ((phy_type) & I40E_CAP_PHY_TYPE_40GBASE_LR4))
1310 #define I40E_PHY_TYPE_SUPPORT_25G(phy_type) \
1311 (((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_KR) || \
1312 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_CR) || \
1313 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_SR) || \
1314 ((phy_type) & I40E_CAP_PHY_TYPE_25GBASE_LR))
1316 #endif /* _I40E_ETHDEV_H_ */