drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static void i40evf_dev_close(struct rte_eth_dev *dev);
 123 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 130                                      uint16_t rx_queue_id);
 131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 132                                     uint16_t rx_queue_id);
 133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 134                                      uint16_t tx_queue_id);
 135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 136                                     uint16_t tx_queue_id);
 137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 138                                struct ether_addr *addr,
 139                                uint32_t index,
 140                                uint32_t pool);
 141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 143                         struct rte_eth_rss_reta_entry64 *reta_conf,
 144                         uint16_t reta_size);
 145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                         struct rte_eth_rss_reta_entry64 *reta_conf,
 147                         uint16_t reta_size);
 148 static int i40evf_config_rss(struct i40e_vf *vf);
 149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 150                                       struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 152                                         struct rte_eth_rss_conf *rss_conf);
 153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 155                                         struct ether_addr *mac_addr);
 156 static int
 157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static int
 159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 161                                    uint8_t *msg,
 162                                    uint16_t msglen);
 163
 164 /* Default hash key buffer for RSS */
 165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 166
 167 struct rte_i40evf_xstats_name_off {
 168         char name[RTE_ETH_XSTATS_NAME_SIZE];
 169         unsigned offset;
 170 };
 171
 172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 173         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 174         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 175         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 176         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 177         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 178         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 179                 rx_unknown_protocol)},
 180         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 182         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 183         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 184         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 185         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 186 };
 187
 188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 189                 sizeof(rte_i40evf_stats_strings[0]))
 190
 191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 192         .dev_configure        = i40evf_dev_configure,
 193         .dev_start            = i40evf_dev_start,
 194         .dev_stop             = i40evf_dev_stop,
 195         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 196         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 197         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 198         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 199         .link_update          = i40evf_dev_link_update,
 200         .stats_get            = i40evf_dev_stats_get,
 201         .stats_reset          = i40evf_dev_xstats_reset,
 202         .xstats_get           = i40evf_dev_xstats_get,
 203         .xstats_get_names     = i40evf_dev_xstats_get_names,
 204         .xstats_reset         = i40evf_dev_xstats_reset,
 205         .dev_close            = i40evf_dev_close,
 206         .dev_reset            = i40evf_dev_reset,
 207         .dev_infos_get        = i40evf_dev_info_get,
 208         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 209         .vlan_filter_set      = i40evf_vlan_filter_set,
 210         .vlan_offload_set     = i40evf_vlan_offload_set,
 211         .rx_queue_start       = i40evf_dev_rx_queue_start,
 212         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 213         .tx_queue_start       = i40evf_dev_tx_queue_start,
 214         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 215         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 216         .rx_queue_release     = i40e_dev_rx_queue_release,
 217         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 218         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 219         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 220         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 221         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 222         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 223         .tx_queue_release     = i40e_dev_tx_queue_release,
 224         .rx_queue_count       = i40e_dev_rx_queue_count,
 225         .rxq_info_get         = i40e_rxq_info_get,
 226         .txq_info_get         = i40e_txq_info_get,
 227         .mac_addr_add         = i40evf_add_mac_addr,
 228         .mac_addr_remove      = i40evf_del_mac_addr,
 229         .reta_update          = i40evf_dev_rss_reta_update,
 230         .reta_query           = i40evf_dev_rss_reta_query,
 231         .rss_hash_update      = i40evf_dev_rss_hash_update,
 232         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 233         .mtu_set              = i40evf_dev_mtu_set,
 234         .mac_addr_set         = i40evf_set_default_mac_addr,
 235 };
 236
 237 /*
 238  * Read data in admin queue to get msg from pf driver
 239  */
 240 static enum i40evf_aq_result
 241 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 242 {
 243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 245         struct i40e_arq_event_info event;
 246         enum virtchnl_ops opcode;
 247         enum i40e_status_code retval;
 248         int ret;
 249         enum i40evf_aq_result result = I40EVF_MSG_NON;
 250
 251         event.buf_len = data->buf_len;
 252         event.msg_buf = data->msg;
 253         ret = i40e_clean_arq_element(hw, &event, NULL);
 254         /* Can't read any msg from adminQ */
 255         if (ret) {
 256                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 257                         result = I40EVF_MSG_ERR;
 258                 return result;
 259         }
 260
 261         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 262         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 263         /* pf sys event */
 264         if (opcode == VIRTCHNL_OP_EVENT) {
 265                 struct virtchnl_pf_event *vpe =
 266                         (struct virtchnl_pf_event *)event.msg_buf;
 267
 268                 result = I40EVF_MSG_SYS;
 269                 switch (vpe->event) {
 270                 case VIRTCHNL_EVENT_LINK_CHANGE:
 271                         vf->link_up =
 272                                 vpe->event_data.link_event.link_status;
 273                         vf->link_speed =
 274                                 vpe->event_data.link_event.link_speed;
 275                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 276                         PMD_DRV_LOG(INFO, "Link status update:%s",
 277                                     vf->link_up ? "up" : "down");
 278                         break;
 279                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 280                         vf->vf_reset = true;
 281                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 282                         PMD_DRV_LOG(INFO, "vf is reseting");
 283                         break;
 284                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 285                         vf->dev_closed = true;
 286                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 287                         PMD_DRV_LOG(INFO, "PF driver closed");
 288                         break;
 289                 default:
 290                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 291                                     __func__, vpe->event);
 292                 }
 293         } else {
 294                 /* async reply msg on command issued by vf previously */
 295                 result = I40EVF_MSG_CMD;
 296                 /* Actual data length read from PF */
 297                 data->msg_len = event.msg_len;
 298         }
 299
 300         data->result = retval;
 301         data->ops = opcode;
 302
 303         return result;
 304 }
 305
 306 /**
 307  * clear current command. Only call in case execute
 308  * _atomic_set_cmd successfully.
 309  */
 310 static inline void
 311 _clear_cmd(struct i40e_vf *vf)
 312 {
 313         rte_wmb();
 314         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 315 }
 316
 317 /*
 318  * Check there is pending cmd in execution. If none, set new command.
 319  */
 320 static inline int
 321 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 322 {
 323         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 324                         VIRTCHNL_OP_UNKNOWN, ops);
 325
 326         if (!ret)
 327                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 328
 329         return !ret;
 330 }
 331
 332 #define MAX_TRY_TIMES 200
 333 #define ASQ_DELAY_MS  10
 334
 335 static int
 336 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 337 {
 338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 340         struct i40evf_arq_msg_info info;
 341         enum i40evf_aq_result ret;
 342         int err, i = 0;
 343
 344         if (_atomic_set_cmd(vf, args->ops))
 345                 return -1;
 346
 347         info.msg = args->out_buffer;
 348         info.buf_len = args->out_size;
 349         info.ops = VIRTCHNL_OP_UNKNOWN;
 350         info.result = I40E_SUCCESS;
 351
 352         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 353                      args->in_args, args->in_args_size, NULL);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 356                 _clear_cmd(vf);
 357                 return err;
 358         }
 359
 360         switch (args->ops) {
 361         case VIRTCHNL_OP_RESET_VF:
 362                 /*no need to process in this function */
 363                 err = 0;
 364                 break;
 365         case VIRTCHNL_OP_VERSION:
 366         case VIRTCHNL_OP_GET_VF_RESOURCES:
 367                 /* for init adminq commands, need to poll the response */
 368                 err = -1;
 369                 do {
 370                         ret = i40evf_read_pfmsg(dev, &info);
 371                         vf->cmd_retval = info.result;
 372                         if (ret == I40EVF_MSG_CMD) {
 373                                 err = 0;
 374                                 break;
 375                         } else if (ret == I40EVF_MSG_ERR)
 376                                 break;
 377                         rte_delay_ms(ASQ_DELAY_MS);
 378                         /* If don't read msg or read sys event, continue */
 379                 } while (i++ < MAX_TRY_TIMES);
 380                 _clear_cmd(vf);
 381                 break;
 382
 383         default:
 384                 /* for other adminq in running time, waiting the cmd done flag */
 385                 err = -1;
 386                 do {
 387                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 388                                 err = 0;
 389                                 break;
 390                         }
 391                         rte_delay_ms(ASQ_DELAY_MS);
 392                         /* If don't read msg or read sys event, continue */
 393                 } while (i++ < MAX_TRY_TIMES);
 394                 /* If there's no response is received, clear command */
 395                 if (i >= MAX_TRY_TIMES) {
 396                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 397                         _clear_cmd(vf);
 398                 }
 399                 break;
 400         }
 401
 402         return err | vf->cmd_retval;
 403 }
 404
 405 /*
 406  * Check API version with sync wait until version read or fail from admin queue
 407  */
 408 static int
 409 i40evf_check_api_version(struct rte_eth_dev *dev)
 410 {
 411         struct virtchnl_version_info version, *pver;
 412         int err;
 413         struct vf_cmd_info args;
 414         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 415
 416         version.major = VIRTCHNL_VERSION_MAJOR;
 417         version.minor = VIRTCHNL_VERSION_MINOR;
 418
 419         args.ops = VIRTCHNL_OP_VERSION;
 420         args.in_args = (uint8_t *)&version;
 421         args.in_args_size = sizeof(version);
 422         args.out_buffer = vf->aq_resp;
 423         args.out_size = I40E_AQ_BUF_SZ;
 424
 425         err = i40evf_execute_vf_cmd(dev, &args);
 426         if (err) {
 427                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 428                 return err;
 429         }
 430
 431         pver = (struct virtchnl_version_info *)args.out_buffer;
 432         vf->version_major = pver->major;
 433         vf->version_minor = pver->minor;
 434         if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 435                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 436                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 437         else {
 438                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 439                                         vf->version_major, vf->version_minor,
 440                                                 VIRTCHNL_VERSION_MAJOR,
 441                                                 VIRTCHNL_VERSION_MINOR);
 442                 return -1;
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int
 449 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 450 {
 451         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 452         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 453         int err;
 454         struct vf_cmd_info args;
 455         uint32_t caps, len;
 456
 457         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 458         args.out_buffer = vf->aq_resp;
 459         args.out_size = I40E_AQ_BUF_SZ;
 460         if (PF_IS_V11(vf)) {
 461                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 462                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 463                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 464                        VIRTCHNL_VF_OFFLOAD_VLAN |
 465                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 466                 args.in_args = (uint8_t *)&caps;
 467                 args.in_args_size = sizeof(caps);
 468         } else {
 469                 args.in_args = NULL;
 470                 args.in_args_size = 0;
 471         }
 472         err = i40evf_execute_vf_cmd(dev, &args);
 473
 474         if (err) {
 475                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 476                 return err;
 477         }
 478
 479         len =  sizeof(struct virtchnl_vf_resource) +
 480                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 481
 482         rte_memcpy(vf->vf_res, args.out_buffer,
 483                         RTE_MIN(args.out_size, len));
 484         i40e_vf_parse_hw_config(hw, vf->vf_res);
 485
 486         return 0;
 487 }
 488
 489 static int
 490 i40evf_config_promisc(struct rte_eth_dev *dev,
 491                       bool enable_unicast,
 492                       bool enable_multicast)
 493 {
 494         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 495         int err;
 496         struct vf_cmd_info args;
 497         struct virtchnl_promisc_info promisc;
 498
 499         promisc.flags = 0;
 500         promisc.vsi_id = vf->vsi_res->vsi_id;
 501
 502         if (enable_unicast)
 503                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 504
 505         if (enable_multicast)
 506                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 507
 508         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 509         args.in_args = (uint8_t *)&promisc;
 510         args.in_args_size = sizeof(promisc);
 511         args.out_buffer = vf->aq_resp;
 512         args.out_size = I40E_AQ_BUF_SZ;
 513
 514         err = i40evf_execute_vf_cmd(dev, &args);
 515
 516         if (err)
 517                 PMD_DRV_LOG(ERR, "fail to execute command "
 518                             "CONFIG_PROMISCUOUS_MODE");
 519         return err;
 520 }
 521
 522 static int
 523 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 524 {
 525         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 526         struct vf_cmd_info args;
 527         int ret;
 528
 529         memset(&args, 0, sizeof(args));
 530         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 531         args.in_args = NULL;
 532         args.in_args_size = 0;
 533         args.out_buffer = vf->aq_resp;
 534         args.out_size = I40E_AQ_BUF_SZ;
 535         ret = i40evf_execute_vf_cmd(dev, &args);
 536         if (ret)
 537                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 538                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 539
 540         return ret;
 541 }
 542
 543 static int
 544 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 545 {
 546         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 547         struct vf_cmd_info args;
 548         int ret;
 549
 550         memset(&args, 0, sizeof(args));
 551         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 552         args.in_args = NULL;
 553         args.in_args_size = 0;
 554         args.out_buffer = vf->aq_resp;
 555         args.out_size = I40E_AQ_BUF_SZ;
 556         ret = i40evf_execute_vf_cmd(dev, &args);
 557         if (ret)
 558                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 559                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 560
 561         return ret;
 562 }
 563
 564 static void
 565 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 566                                   uint16_t vsi_id,
 567                                   uint16_t queue_id,
 568                                   uint16_t nb_txq,
 569                                   struct i40e_tx_queue *txq)
 570 {
 571         txq_info->vsi_id = vsi_id;
 572         txq_info->queue_id = queue_id;
 573         if (queue_id < nb_txq) {
 574                 txq_info->ring_len = txq->nb_tx_desc;
 575                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 576         }
 577 }
 578
 579 static void
 580 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 581                                   uint16_t vsi_id,
 582                                   uint16_t queue_id,
 583                                   uint16_t nb_rxq,
 584                                   uint32_t max_pkt_size,
 585                                   struct i40e_rx_queue *rxq)
 586 {
 587         rxq_info->vsi_id = vsi_id;
 588         rxq_info->queue_id = queue_id;
 589         rxq_info->max_pkt_size = max_pkt_size;
 590         if (queue_id < nb_rxq) {
 591                 rxq_info->ring_len = rxq->nb_rx_desc;
 592                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 593                 rxq_info->databuffer_size =
 594                         (rte_pktmbuf_data_room_size(rxq->mp) -
 595                                 RTE_PKTMBUF_HEADROOM);
 596         }
 597 }
 598
 599 static int
 600 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 601 {
 602         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 603         struct i40e_rx_queue **rxq =
 604                 (struct i40e_rx_queue **)dev->data->rx_queues;
 605         struct i40e_tx_queue **txq =
 606                 (struct i40e_tx_queue **)dev->data->tx_queues;
 607         struct virtchnl_vsi_queue_config_info *vc_vqci;
 608         struct virtchnl_queue_pair_info *vc_qpi;
 609         struct vf_cmd_info args;
 610         uint16_t i, nb_qp = vf->num_queue_pairs;
 611         const uint32_t size =
 612                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 613         uint8_t buff[size];
 614         int ret;
 615
 616         memset(buff, 0, sizeof(buff));
 617         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 618         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 619         vc_vqci->num_queue_pairs = nb_qp;
 620
 621         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 622                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 623                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 624                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 625                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 626                                         vf->max_pkt_len, rxq[i]);
 627         }
 628         memset(&args, 0, sizeof(args));
 629         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 630         args.in_args = (uint8_t *)vc_vqci;
 631         args.in_args_size = size;
 632         args.out_buffer = vf->aq_resp;
 633         args.out_size = I40E_AQ_BUF_SZ;
 634         ret = i40evf_execute_vf_cmd(dev, &args);
 635         if (ret)
 636                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 637                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 638
 639         return ret;
 640 }
 641
 642 static int
 643 i40evf_config_irq_map(struct rte_eth_dev *dev)
 644 {
 645         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 646         struct vf_cmd_info args;
 647         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 648                 sizeof(struct virtchnl_vector_map)];
 649         struct virtchnl_irq_map_info *map_info;
 650         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 651         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 652         uint32_t vector_id;
 653         int i, err;
 654
 655         if (rte_intr_allow_others(intr_handle))
 656                 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 657         else
 658                 vector_id = I40E_MISC_VEC_ID;
 659
 660         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 661         map_info->num_vectors = 1;
 662         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 663         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 664         /* Alway use default dynamic MSIX interrupt */
 665         map_info->vecmap[0].vector_id = vector_id;
 666         /* Don't map any tx queue */
 667         map_info->vecmap[0].txq_map = 0;
 668         map_info->vecmap[0].rxq_map = 0;
 669         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 670                 map_info->vecmap[0].rxq_map |= 1 << i;
 671                 if (rte_intr_dp_is_en(intr_handle))
 672                         intr_handle->intr_vec[i] = vector_id;
 673         }
 674
 675         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 676         args.in_args = (u8 *)cmd_buffer;
 677         args.in_args_size = sizeof(cmd_buffer);
 678         args.out_buffer = vf->aq_resp;
 679         args.out_size = I40E_AQ_BUF_SZ;
 680         err = i40evf_execute_vf_cmd(dev, &args);
 681         if (err)
 682                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 683
 684         return err;
 685 }
 686
 687 static int
 688 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 689                                 bool on)
 690 {
 691         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 692         struct virtchnl_queue_select queue_select;
 693         int err;
 694         struct vf_cmd_info args;
 695         memset(&queue_select, 0, sizeof(queue_select));
 696         queue_select.vsi_id = vf->vsi_res->vsi_id;
 697
 698         if (isrx)
 699                 queue_select.rx_queues |= 1 << qid;
 700         else
 701                 queue_select.tx_queues |= 1 << qid;
 702
 703         if (on)
 704                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 705         else
 706                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 707         args.in_args = (u8 *)&queue_select;
 708         args.in_args_size = sizeof(queue_select);
 709         args.out_buffer = vf->aq_resp;
 710         args.out_size = I40E_AQ_BUF_SZ;
 711         err = i40evf_execute_vf_cmd(dev, &args);
 712         if (err)
 713                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 714                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 715
 716         return err;
 717 }
 718
 719 static int
 720 i40evf_start_queues(struct rte_eth_dev *dev)
 721 {
 722         struct rte_eth_dev_data *dev_data = dev->data;
 723         int i;
 724         struct i40e_rx_queue *rxq;
 725         struct i40e_tx_queue *txq;
 726
 727         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 728                 rxq = dev_data->rx_queues[i];
 729                 if (rxq->rx_deferred_start)
 730                         continue;
 731                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 732                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 733                         return -1;
 734                 }
 735         }
 736
 737         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 738                 txq = dev_data->tx_queues[i];
 739                 if (txq->tx_deferred_start)
 740                         continue;
 741                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 742                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 743                         return -1;
 744                 }
 745         }
 746
 747         return 0;
 748 }
 749
 750 static int
 751 i40evf_stop_queues(struct rte_eth_dev *dev)
 752 {
 753         int i;
 754
 755         /* Stop TX queues first */
 756         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 757                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 758                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 759                         return -1;
 760                 }
 761         }
 762
 763         /* Then stop RX queues */
 764         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 765                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 766                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 767                         return -1;
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 static int
 775 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 776                     struct ether_addr *addr,
 777                     __rte_unused uint32_t index,
 778                     __rte_unused uint32_t pool)
 779 {
 780         struct virtchnl_ether_addr_list *list;
 781         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 782         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 783                         sizeof(struct virtchnl_ether_addr)];
 784         int err;
 785         struct vf_cmd_info args;
 786
 787         if (is_zero_ether_addr(addr)) {
 788                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 789                             addr->addr_bytes[0], addr->addr_bytes[1],
 790                             addr->addr_bytes[2], addr->addr_bytes[3],
 791                             addr->addr_bytes[4], addr->addr_bytes[5]);
 792                 return I40E_ERR_INVALID_MAC_ADDR;
 793         }
 794
 795         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 796         list->vsi_id = vf->vsi_res->vsi_id;
 797         list->num_elements = 1;
 798         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 799                                         sizeof(addr->addr_bytes));
 800
 801         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 802         args.in_args = cmd_buffer;
 803         args.in_args_size = sizeof(cmd_buffer);
 804         args.out_buffer = vf->aq_resp;
 805         args.out_size = I40E_AQ_BUF_SZ;
 806         err = i40evf_execute_vf_cmd(dev, &args);
 807         if (err)
 808                 PMD_DRV_LOG(ERR, "fail to execute command "
 809                             "OP_ADD_ETHER_ADDRESS");
 810         else
 811                 vf->vsi.mac_num++;
 812
 813         return err;
 814 }
 815
 816 static void
 817 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 818                             struct ether_addr *addr)
 819 {
 820         struct virtchnl_ether_addr_list *list;
 821         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 822         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 823                         sizeof(struct virtchnl_ether_addr)];
 824         int err;
 825         struct vf_cmd_info args;
 826
 827         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 828                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 829                             addr->addr_bytes[0], addr->addr_bytes[1],
 830                             addr->addr_bytes[2], addr->addr_bytes[3],
 831                             addr->addr_bytes[4], addr->addr_bytes[5]);
 832                 return;
 833         }
 834
 835         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 836         list->vsi_id = vf->vsi_res->vsi_id;
 837         list->num_elements = 1;
 838         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 839                         sizeof(addr->addr_bytes));
 840
 841         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 842         args.in_args = cmd_buffer;
 843         args.in_args_size = sizeof(cmd_buffer);
 844         args.out_buffer = vf->aq_resp;
 845         args.out_size = I40E_AQ_BUF_SZ;
 846         err = i40evf_execute_vf_cmd(dev, &args);
 847         if (err)
 848                 PMD_DRV_LOG(ERR, "fail to execute command "
 849                             "OP_DEL_ETHER_ADDRESS");
 850         else
 851                 vf->vsi.mac_num--;
 852         return;
 853 }
 854
 855 static void
 856 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 857 {
 858         struct rte_eth_dev_data *data = dev->data;
 859         struct ether_addr *addr;
 860
 861         addr = &data->mac_addrs[index];
 862
 863         i40evf_del_mac_addr_by_addr(dev, addr);
 864 }
 865
 866 static int
 867 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 868 {
 869         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 870         struct virtchnl_queue_select q_stats;
 871         int err;
 872         struct vf_cmd_info args;
 873
 874         memset(&q_stats, 0, sizeof(q_stats));
 875         q_stats.vsi_id = vf->vsi_res->vsi_id;
 876         args.ops = VIRTCHNL_OP_GET_STATS;
 877         args.in_args = (u8 *)&q_stats;
 878         args.in_args_size = sizeof(q_stats);
 879         args.out_buffer = vf->aq_resp;
 880         args.out_size = I40E_AQ_BUF_SZ;
 881
 882         err = i40evf_execute_vf_cmd(dev, &args);
 883         if (err) {
 884                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 885                 *pstats = NULL;
 886                 return err;
 887         }
 888         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 889         return 0;
 890 }
 891
 892 static void
 893 i40evf_stat_update_48(uint64_t *offset,
 894                    uint64_t *stat)
 895 {
 896         if (*stat >= *offset)
 897                 *stat = *stat - *offset;
 898         else
 899                 *stat = (uint64_t)((*stat +
 900                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
 901
 902         *stat &= I40E_48_BIT_MASK;
 903 }
 904
 905 static void
 906 i40evf_stat_update_32(uint64_t *offset,
 907                    uint64_t *stat)
 908 {
 909         if (*stat >= *offset)
 910                 *stat = (uint64_t)(*stat - *offset);
 911         else
 912                 *stat = (uint64_t)((*stat +
 913                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
 914 }
 915
 916 static void
 917 i40evf_update_vsi_stats(struct i40e_vsi *vsi,
 918                                         struct i40e_eth_stats *nes)
 919 {
 920         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 921
 922         i40evf_stat_update_48(&oes->rx_bytes,
 923                             &nes->rx_bytes);
 924         i40evf_stat_update_48(&oes->rx_unicast,
 925                             &nes->rx_unicast);
 926         i40evf_stat_update_48(&oes->rx_multicast,
 927                             &nes->rx_multicast);
 928         i40evf_stat_update_48(&oes->rx_broadcast,
 929                             &nes->rx_broadcast);
 930         i40evf_stat_update_32(&oes->rx_discards,
 931                                 &nes->rx_discards);
 932         i40evf_stat_update_32(&oes->rx_unknown_protocol,
 933                             &nes->rx_unknown_protocol);
 934         i40evf_stat_update_48(&oes->tx_bytes,
 935                             &nes->tx_bytes);
 936         i40evf_stat_update_48(&oes->tx_unicast,
 937                             &nes->tx_unicast);
 938         i40evf_stat_update_48(&oes->tx_multicast,
 939                             &nes->tx_multicast);
 940         i40evf_stat_update_48(&oes->tx_broadcast,
 941                             &nes->tx_broadcast);
 942         i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
 943         i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
 944 }
 945
 946 static int
 947 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 948 {
 949         int ret;
 950         struct i40e_eth_stats *pstats = NULL;
 951         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 952         struct i40e_vsi *vsi = &vf->vsi;
 953
 954         ret = i40evf_update_stats(dev, &pstats);
 955         if (ret != 0)
 956                 return 0;
 957
 958         i40evf_update_vsi_stats(vsi, pstats);
 959
 960         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 961                                                 pstats->rx_broadcast;
 962         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 963                                                 pstats->tx_unicast;
 964         stats->imissed = pstats->rx_discards;
 965         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 966         stats->ibytes = pstats->rx_bytes;
 967         stats->obytes = pstats->tx_bytes;
 968
 969         return 0;
 970 }
 971
 972 static void
 973 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 974 {
 975         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 976         struct i40e_eth_stats *pstats = NULL;
 977
 978         /* read stat values to clear hardware registers */
 979         i40evf_update_stats(dev, &pstats);
 980
 981         /* set stats offset base on current values */
 982         vf->vsi.eth_stats_offset = *pstats;
 983 }
 984
 985 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 986                                       struct rte_eth_xstat_name *xstats_names,
 987                                       __rte_unused unsigned limit)
 988 {
 989         unsigned i;
 990
 991         if (xstats_names != NULL)
 992                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 993                         snprintf(xstats_names[i].name,
 994                                 sizeof(xstats_names[i].name),
 995                                 "%s", rte_i40evf_stats_strings[i].name);
 996                 }
 997         return I40EVF_NB_XSTATS;
 998 }
 999
1000 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1001                                  struct rte_eth_xstat *xstats, unsigned n)
1002 {
1003         int ret;
1004         unsigned i;
1005         struct i40e_eth_stats *pstats = NULL;
1006         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1007         struct i40e_vsi *vsi = &vf->vsi;
1008
1009         if (n < I40EVF_NB_XSTATS)
1010                 return I40EVF_NB_XSTATS;
1011
1012         ret = i40evf_update_stats(dev, &pstats);
1013         if (ret != 0)
1014                 return 0;
1015
1016         if (!xstats)
1017                 return 0;
1018
1019         i40evf_update_vsi_stats(vsi, pstats);
1020
1021         /* loop over xstats array and values from pstats */
1022         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1023                 xstats[i].id = i;
1024                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1025                         rte_i40evf_stats_strings[i].offset);
1026         }
1027
1028         return I40EVF_NB_XSTATS;
1029 }
1030
1031 static int
1032 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1033 {
1034         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1035         struct virtchnl_vlan_filter_list *vlan_list;
1036         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1037                                                         sizeof(uint16_t)];
1038         int err;
1039         struct vf_cmd_info args;
1040
1041         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1042         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1043         vlan_list->num_elements = 1;
1044         vlan_list->vlan_id[0] = vlanid;
1045
1046         args.ops = VIRTCHNL_OP_ADD_VLAN;
1047         args.in_args = (u8 *)&cmd_buffer;
1048         args.in_args_size = sizeof(cmd_buffer);
1049         args.out_buffer = vf->aq_resp;
1050         args.out_size = I40E_AQ_BUF_SZ;
1051         err = i40evf_execute_vf_cmd(dev, &args);
1052         if (err)
1053                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1054
1055         return err;
1056 }
1057
1058 static int
1059 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1060 {
1061         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1062         struct virtchnl_vlan_filter_list *vlan_list;
1063         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1064                                                         sizeof(uint16_t)];
1065         int err;
1066         struct vf_cmd_info args;
1067
1068         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1069         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1070         vlan_list->num_elements = 1;
1071         vlan_list->vlan_id[0] = vlanid;
1072
1073         args.ops = VIRTCHNL_OP_DEL_VLAN;
1074         args.in_args = (u8 *)&cmd_buffer;
1075         args.in_args_size = sizeof(cmd_buffer);
1076         args.out_buffer = vf->aq_resp;
1077         args.out_size = I40E_AQ_BUF_SZ;
1078         err = i40evf_execute_vf_cmd(dev, &args);
1079         if (err)
1080                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1081
1082         return err;
1083 }
1084
1085 static const struct rte_pci_id pci_id_i40evf_map[] = {
1086         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1087         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1088         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1089         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1090         { .vendor_id = 0, /* sentinel */ },
1091 };
1092
1093 static inline int
1094 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1095                                     struct rte_eth_link *link)
1096 {
1097         struct rte_eth_link *dst = &(dev->data->dev_link);
1098         struct rte_eth_link *src = link;
1099
1100         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1101                                         *(uint64_t *)src) == 0)
1102                 return -1;
1103
1104         return 0;
1105 }
1106
1107 /* Disable IRQ0 */
1108 static inline void
1109 i40evf_disable_irq0(struct i40e_hw *hw)
1110 {
1111         /* Disable all interrupt types */
1112         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1113         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1114                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1115         I40EVF_WRITE_FLUSH(hw);
1116 }
1117
1118 /* Enable IRQ0 */
1119 static inline void
1120 i40evf_enable_irq0(struct i40e_hw *hw)
1121 {
1122         /* Enable admin queue interrupt trigger */
1123         uint32_t val;
1124
1125         i40evf_disable_irq0(hw);
1126         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1127         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1128                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1129         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1130
1131         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1132                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1133                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1134                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1135
1136         I40EVF_WRITE_FLUSH(hw);
1137 }
1138
1139 static int
1140 i40evf_reset_vf(struct i40e_hw *hw)
1141 {
1142         int i, reset;
1143
1144         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1145                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1146                 return -1;
1147         }
1148         /**
1149           * After issuing vf reset command to pf, pf won't necessarily
1150           * reset vf, it depends on what state it exactly is. If it's not
1151           * initialized yet, it won't have vf reset since it's in a certain
1152           * state. If not, it will try to reset. Even vf is reset, pf will
1153           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1154           * it to ACTIVE. In this duration, vf may not catch the moment that
1155           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1156           */
1157         rte_delay_ms(200);
1158
1159         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1160                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1161                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1162                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1163                 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1164                         break;
1165                 else
1166                         rte_delay_ms(50);
1167         }
1168
1169         if (i >= MAX_RESET_WAIT_CNT) {
1170                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1171                 return -1;
1172         }
1173
1174         return 0;
1175 }
1176
1177 static int
1178 i40evf_init_vf(struct rte_eth_dev *dev)
1179 {
1180         int i, err, bufsz;
1181         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1182         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1183         uint16_t interval =
1184                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1185
1186         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1187         vf->dev_data = dev->data;
1188         err = i40e_set_mac_type(hw);
1189         if (err) {
1190                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1191                 goto err;
1192         }
1193
1194         i40e_init_adminq_parameter(hw);
1195         err = i40e_init_adminq(hw);
1196         if (err) {
1197                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1198                 goto err;
1199         }
1200
1201         /* Reset VF and wait until it's complete */
1202         if (i40evf_reset_vf(hw)) {
1203                 PMD_INIT_LOG(ERR, "reset NIC failed");
1204                 goto err_aq;
1205         }
1206
1207         /* VF reset, shutdown admin queue and initialize again */
1208         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1209                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1210                 goto err;
1211         }
1212
1213         i40e_init_adminq_parameter(hw);
1214         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1215                 PMD_INIT_LOG(ERR, "init_adminq failed");
1216                 goto err;
1217         }
1218         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1219         if (!vf->aq_resp) {
1220                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1221                 goto err_aq;
1222         }
1223         if (i40evf_check_api_version(dev) != 0) {
1224                 PMD_INIT_LOG(ERR, "check_api version failed");
1225                 goto err_api;
1226         }
1227         bufsz = sizeof(struct virtchnl_vf_resource) +
1228                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1229         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1230         if (!vf->vf_res) {
1231                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1232                 goto err_api;
1233         }
1234
1235         if (i40evf_get_vf_resource(dev) != 0) {
1236                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1237                 goto err_alloc;
1238         }
1239
1240         /* got VF config message back from PF, now we can parse it */
1241         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1242                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1243                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1244         }
1245
1246         if (!vf->vsi_res) {
1247                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1248                 goto err_alloc;
1249         }
1250
1251         if (hw->mac.type == I40E_MAC_X722_VF)
1252                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1253         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1254         vf->vsi.type = (enum i40e_vsi_type)vf->vsi_res->vsi_type;
1255         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1256         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1257
1258         /* Store the MAC address configured by host, or generate random one */
1259         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1260                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1261         else
1262                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1263
1264         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1265                        (I40E_ITR_INDEX_DEFAULT <<
1266                         I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1267                        (interval <<
1268                         I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1269         I40EVF_WRITE_FLUSH(hw);
1270
1271         return 0;
1272
1273 err_alloc:
1274         rte_free(vf->vf_res);
1275         vf->vsi_res = NULL;
1276 err_api:
1277         rte_free(vf->aq_resp);
1278 err_aq:
1279         i40e_shutdown_adminq(hw); /* ignore error */
1280 err:
1281         return -1;
1282 }
1283
1284 static int
1285 i40evf_uninit_vf(struct rte_eth_dev *dev)
1286 {
1287         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1288         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1289
1290         PMD_INIT_FUNC_TRACE();
1291
1292         if (hw->adapter_stopped == 0)
1293                 i40evf_dev_close(dev);
1294         rte_free(vf->vf_res);
1295         vf->vf_res = NULL;
1296         rte_free(vf->aq_resp);
1297         vf->aq_resp = NULL;
1298
1299         return 0;
1300 }
1301
1302 static void
1303 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1304                 __rte_unused uint16_t msglen)
1305 {
1306         struct virtchnl_pf_event *pf_msg =
1307                         (struct virtchnl_pf_event *)msg;
1308         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1309
1310         switch (pf_msg->event) {
1311         case VIRTCHNL_EVENT_RESET_IMPENDING:
1312                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1313                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1314                                               NULL, NULL);
1315                 break;
1316         case VIRTCHNL_EVENT_LINK_CHANGE:
1317                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1318                 vf->link_up = pf_msg->event_data.link_event.link_status;
1319                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1320                 break;
1321         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1322                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1323                 break;
1324         default:
1325                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1326                 break;
1327         }
1328 }
1329
1330 static void
1331 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1332 {
1333         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1334         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1335         struct i40e_arq_event_info info;
1336         uint16_t pending, aq_opc;
1337         enum virtchnl_ops msg_opc;
1338         enum i40e_status_code msg_ret;
1339         int ret;
1340
1341         info.buf_len = I40E_AQ_BUF_SZ;
1342         if (!vf->aq_resp) {
1343                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1344                 return;
1345         }
1346         info.msg_buf = vf->aq_resp;
1347
1348         pending = 1;
1349         while (pending) {
1350                 ret = i40e_clean_arq_element(hw, &info, &pending);
1351
1352                 if (ret != I40E_SUCCESS) {
1353                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1354                                     "ret: %d", ret);
1355                         break;
1356                 }
1357                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1358                 /* For the message sent from pf to vf, opcode is stored in
1359                  * cookie_high of struct i40e_aq_desc, while return error code
1360                  * are stored in cookie_low, Which is done by
1361                  * i40e_aq_send_msg_to_vf in PF driver.*/
1362                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1363                                                   info.desc.cookie_high);
1364                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1365                                                   info.desc.cookie_low);
1366                 switch (aq_opc) {
1367                 case i40e_aqc_opc_send_msg_to_vf:
1368                         if (msg_opc == VIRTCHNL_OP_EVENT)
1369                                 /* process event*/
1370                                 i40evf_handle_pf_event(dev, info.msg_buf,
1371                                                        info.msg_len);
1372                         else {
1373                                 /* read message and it's expected one */
1374                                 if (msg_opc == vf->pend_cmd) {
1375                                         vf->cmd_retval = msg_ret;
1376                                         /* prevent compiler reordering */
1377                                         rte_compiler_barrier();
1378                                         _clear_cmd(vf);
1379                                 } else
1380                                         PMD_DRV_LOG(ERR, "command mismatch,"
1381                                                 "expect %u, get %u",
1382                                                 vf->pend_cmd, msg_opc);
1383                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1384                                              " opcode = %d", msg_opc);
1385                         }
1386                         break;
1387                 default:
1388                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1389                                     aq_opc);
1390                         break;
1391                 }
1392         }
1393 }
1394
1395 /**
1396  * Interrupt handler triggered by NIC  for handling
1397  * specific interrupt. Only adminq interrupt is processed in VF.
1398  *
1399  * @param handle
1400  *  Pointer to interrupt handle.
1401  * @param param
1402  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1403  *
1404  * @return
1405  *  void
1406  */
1407 static void
1408 i40evf_dev_interrupt_handler(void *param)
1409 {
1410         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412         uint32_t icr0;
1413
1414         i40evf_disable_irq0(hw);
1415
1416         /* read out interrupt causes */
1417         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1418
1419         /* No interrupt event indicated */
1420         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1421                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1422                 goto done;
1423         }
1424
1425         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1426                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1427                 i40evf_handle_aq_msg(dev);
1428         }
1429
1430         /* Link Status Change interrupt */
1431         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1432                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1433                                    " do nothing");
1434
1435 done:
1436         i40evf_enable_irq0(hw);
1437         rte_intr_enable(dev->intr_handle);
1438 }
1439
1440 static int
1441 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1442 {
1443         struct i40e_hw *hw
1444                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1445         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1446
1447         PMD_INIT_FUNC_TRACE();
1448
1449         /* assign ops func pointer */
1450         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1451         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1452         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1453
1454         /*
1455          * For secondary processes, we don't initialise any further as primary
1456          * has already done this work.
1457          */
1458         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1459                 i40e_set_rx_function(eth_dev);
1460                 i40e_set_tx_function(eth_dev);
1461                 return 0;
1462         }
1463         i40e_set_default_ptype_table(eth_dev);
1464         rte_eth_copy_pci_info(eth_dev, pci_dev);
1465         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1466
1467         hw->vendor_id = pci_dev->id.vendor_id;
1468         hw->device_id = pci_dev->id.device_id;
1469         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1470         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1471         hw->bus.device = pci_dev->addr.devid;
1472         hw->bus.func = pci_dev->addr.function;
1473         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1474         hw->adapter_stopped = 0;
1475
1476         if(i40evf_init_vf(eth_dev) != 0) {
1477                 PMD_INIT_LOG(ERR, "Init vf failed");
1478                 return -1;
1479         }
1480
1481         /* register callback func to eal lib */
1482         rte_intr_callback_register(&pci_dev->intr_handle,
1483                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1484
1485         /* enable uio intr after callback register */
1486         rte_intr_enable(&pci_dev->intr_handle);
1487
1488         /* configure and enable device interrupt */
1489         i40evf_enable_irq0(hw);
1490
1491         /* copy mac addr */
1492         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1493                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1494                                         0);
1495         if (eth_dev->data->mac_addrs == NULL) {
1496                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1497                                 " store MAC addresses",
1498                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1499                 return -ENOMEM;
1500         }
1501         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1502                         &eth_dev->data->mac_addrs[0]);
1503
1504         return 0;
1505 }
1506
1507 static int
1508 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1509 {
1510         PMD_INIT_FUNC_TRACE();
1511
1512         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1513                 return -EPERM;
1514
1515         eth_dev->dev_ops = NULL;
1516         eth_dev->rx_pkt_burst = NULL;
1517         eth_dev->tx_pkt_burst = NULL;
1518
1519         if (i40evf_uninit_vf(eth_dev) != 0) {
1520                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1521                 return -1;
1522         }
1523
1524         rte_free(eth_dev->data->mac_addrs);
1525         eth_dev->data->mac_addrs = NULL;
1526
1527         return 0;
1528 }
1529
1530 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1531         struct rte_pci_device *pci_dev)
1532 {
1533         return rte_eth_dev_pci_generic_probe(pci_dev,
1534                 sizeof(struct i40e_adapter), i40evf_dev_init);
1535 }
1536
1537 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1538 {
1539         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1540 }
1541
1542 /*
1543  * virtual function driver struct
1544  */
1545 static struct rte_pci_driver rte_i40evf_pmd = {
1546         .id_table = pci_id_i40evf_map,
1547         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1548         .probe = eth_i40evf_pci_probe,
1549         .remove = eth_i40evf_pci_remove,
1550 };
1551
1552 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1553 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1554 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1555
1556 static int
1557 i40evf_dev_configure(struct rte_eth_dev *dev)
1558 {
1559         struct i40e_adapter *ad =
1560                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1561         struct rte_eth_conf *conf = &dev->data->dev_conf;
1562         struct i40e_vf *vf;
1563
1564         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1565          * allocation or vector Rx preconditions we will reset it.
1566          */
1567         ad->rx_bulk_alloc_allowed = true;
1568         ad->rx_vec_allowed = true;
1569         ad->tx_simple_allowed = true;
1570         ad->tx_vec_allowed = true;
1571
1572         /* For non-DPDK PF drivers, VF has no ability to disable HW
1573          * CRC strip, and is implicitly enabled by the PF.
1574          */
1575         if (!conf->rxmode.hw_strip_crc) {
1576                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1577                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1578                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1579                         /* Peer is running non-DPDK PF driver. */
1580                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1581                         return -EINVAL;
1582                 }
1583         }
1584
1585         return i40evf_init_vlan(dev);
1586 }
1587
1588 static int
1589 i40evf_init_vlan(struct rte_eth_dev *dev)
1590 {
1591         /* Apply vlan offload setting */
1592         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1593
1594         return I40E_SUCCESS;
1595 }
1596
1597 static void
1598 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1599 {
1600         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1601
1602         /* Vlan stripping setting */
1603         if (mask & ETH_VLAN_STRIP_MASK) {
1604                 /* Enable or disable VLAN stripping */
1605                 if (dev_conf->rxmode.hw_vlan_strip)
1606                         i40evf_enable_vlan_strip(dev);
1607                 else
1608                         i40evf_disable_vlan_strip(dev);
1609         }
1610 }
1611
1612 static int
1613 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1614 {
1615         struct i40e_rx_queue *rxq;
1616         int err = 0;
1617         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618
1619         PMD_INIT_FUNC_TRACE();
1620
1621         if (rx_queue_id < dev->data->nb_rx_queues) {
1622                 rxq = dev->data->rx_queues[rx_queue_id];
1623
1624                 err = i40e_alloc_rx_queue_mbufs(rxq);
1625                 if (err) {
1626                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1627                         return err;
1628                 }
1629
1630                 rte_wmb();
1631
1632                 /* Init the RX tail register. */
1633                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1634                 I40EVF_WRITE_FLUSH(hw);
1635
1636                 /* Ready to switch the queue on */
1637                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1638
1639                 if (err)
1640                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1641                                     rx_queue_id);
1642                 else
1643                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1644         }
1645
1646         return err;
1647 }
1648
1649 static int
1650 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1651 {
1652         struct i40e_rx_queue *rxq;
1653         int err;
1654
1655         if (rx_queue_id < dev->data->nb_rx_queues) {
1656                 rxq = dev->data->rx_queues[rx_queue_id];
1657
1658                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1659
1660                 if (err) {
1661                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1662                                     rx_queue_id);
1663                         return err;
1664                 }
1665
1666                 i40e_rx_queue_release_mbufs(rxq);
1667                 i40e_reset_rx_queue(rxq);
1668                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1669         }
1670
1671         return 0;
1672 }
1673
1674 static int
1675 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1676 {
1677         int err = 0;
1678
1679         PMD_INIT_FUNC_TRACE();
1680
1681         if (tx_queue_id < dev->data->nb_tx_queues) {
1682
1683                 /* Ready to switch the queue on */
1684                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1685
1686                 if (err)
1687                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1688                                     tx_queue_id);
1689                 else
1690                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1691         }
1692
1693         return err;
1694 }
1695
1696 static int
1697 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1698 {
1699         struct i40e_tx_queue *txq;
1700         int err;
1701
1702         if (tx_queue_id < dev->data->nb_tx_queues) {
1703                 txq = dev->data->tx_queues[tx_queue_id];
1704
1705                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1706
1707                 if (err) {
1708                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1709                                     tx_queue_id);
1710                         return err;
1711                 }
1712
1713                 i40e_tx_queue_release_mbufs(txq);
1714                 i40e_reset_tx_queue(txq);
1715                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1716         }
1717
1718         return 0;
1719 }
1720
1721 static int
1722 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1723 {
1724         int ret;
1725
1726         if (on)
1727                 ret = i40evf_add_vlan(dev, vlan_id);
1728         else
1729                 ret = i40evf_del_vlan(dev,vlan_id);
1730
1731         return ret;
1732 }
1733
1734 static int
1735 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1736 {
1737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738         struct rte_eth_dev_data *dev_data = dev->data;
1739         struct rte_pktmbuf_pool_private *mbp_priv;
1740         uint16_t buf_size, len;
1741
1742         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1743         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1744         I40EVF_WRITE_FLUSH(hw);
1745
1746         /* Calculate the maximum packet length allowed */
1747         mbp_priv = rte_mempool_get_priv(rxq->mp);
1748         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1749                                         RTE_PKTMBUF_HEADROOM);
1750         rxq->hs_mode = i40e_header_split_none;
1751         rxq->rx_hdr_len = 0;
1752         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1753         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1754         rxq->max_pkt_len = RTE_MIN(len,
1755                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1756
1757         /**
1758          * Check if the jumbo frame and maximum packet length are set correctly
1759          */
1760         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1761                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1762                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1763                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1764                                 "larger than %u and smaller than %u, as jumbo "
1765                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1766                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1767                         return I40E_ERR_CONFIG;
1768                 }
1769         } else {
1770                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1771                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1772                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1773                                 "larger than %u and smaller than %u, as jumbo "
1774                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1775                                                 (uint32_t)ETHER_MAX_LEN);
1776                         return I40E_ERR_CONFIG;
1777                 }
1778         }
1779
1780         if (dev_data->dev_conf.rxmode.enable_scatter ||
1781             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1782                 dev_data->scattered_rx = 1;
1783         }
1784
1785         return 0;
1786 }
1787
1788 static int
1789 i40evf_rx_init(struct rte_eth_dev *dev)
1790 {
1791         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1792         uint16_t i;
1793         int ret = I40E_SUCCESS;
1794         struct i40e_rx_queue **rxq =
1795                 (struct i40e_rx_queue **)dev->data->rx_queues;
1796
1797         i40evf_config_rss(vf);
1798         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1799                 if (!rxq[i] || !rxq[i]->q_set)
1800                         continue;
1801                 ret = i40evf_rxq_init(dev, rxq[i]);
1802                 if (ret != I40E_SUCCESS)
1803                         break;
1804         }
1805         if (ret == I40E_SUCCESS)
1806                 i40e_set_rx_function(dev);
1807
1808         return ret;
1809 }
1810
1811 static void
1812 i40evf_tx_init(struct rte_eth_dev *dev)
1813 {
1814         uint16_t i;
1815         struct i40e_tx_queue **txq =
1816                 (struct i40e_tx_queue **)dev->data->tx_queues;
1817         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818
1819         for (i = 0; i < dev->data->nb_tx_queues; i++)
1820                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1821
1822         i40e_set_tx_function(dev);
1823 }
1824
1825 static inline void
1826 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1827 {
1828         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1829         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1830         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1831
1832         if (!rte_intr_allow_others(intr_handle)) {
1833                 I40E_WRITE_REG(hw,
1834                                I40E_VFINT_DYN_CTL01,
1835                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1836                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1837                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1838                 I40EVF_WRITE_FLUSH(hw);
1839                 return;
1840         }
1841
1842         I40EVF_WRITE_FLUSH(hw);
1843 }
1844
1845 static inline void
1846 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1847 {
1848         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1849         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1850         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1851
1852         if (!rte_intr_allow_others(intr_handle)) {
1853                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1854                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1855                 I40EVF_WRITE_FLUSH(hw);
1856                 return;
1857         }
1858
1859         I40EVF_WRITE_FLUSH(hw);
1860 }
1861
1862 static int
1863 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1864 {
1865         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1866         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1867         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868         uint16_t interval =
1869                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1870         uint16_t msix_intr;
1871
1872         msix_intr = intr_handle->intr_vec[queue_id];
1873         if (msix_intr == I40E_MISC_VEC_ID)
1874                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1875                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1876                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1877                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1878                                (interval <<
1879                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1880         else
1881                 I40E_WRITE_REG(hw,
1882                                I40E_VFINT_DYN_CTLN1(msix_intr -
1883                                                     I40E_RX_VEC_START),
1884                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1885                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1886                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1887                                (interval <<
1888                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1889
1890         I40EVF_WRITE_FLUSH(hw);
1891
1892         rte_intr_enable(&pci_dev->intr_handle);
1893
1894         return 0;
1895 }
1896
1897 static int
1898 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1899 {
1900         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1901         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1902         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1903         uint16_t msix_intr;
1904
1905         msix_intr = intr_handle->intr_vec[queue_id];
1906         if (msix_intr == I40E_MISC_VEC_ID)
1907                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1908         else
1909                 I40E_WRITE_REG(hw,
1910                                I40E_VFINT_DYN_CTLN1(msix_intr -
1911                                                     I40E_RX_VEC_START),
1912                                0);
1913
1914         I40EVF_WRITE_FLUSH(hw);
1915
1916         return 0;
1917 }
1918
1919 static void
1920 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1921 {
1922         struct virtchnl_ether_addr_list *list;
1923         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1924         int err, i, j;
1925         int next_begin = 0;
1926         int begin = 0;
1927         uint32_t len;
1928         struct ether_addr *addr;
1929         struct vf_cmd_info args;
1930
1931         do {
1932                 j = 0;
1933                 len = sizeof(struct virtchnl_ether_addr_list);
1934                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1935                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1936                                 continue;
1937                         len += sizeof(struct virtchnl_ether_addr);
1938                         if (len >= I40E_AQ_BUF_SZ) {
1939                                 next_begin = i + 1;
1940                                 break;
1941                         }
1942                 }
1943
1944                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1945                 if (!list) {
1946                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1947                         return;
1948                 }
1949
1950                 for (i = begin; i < next_begin; i++) {
1951                         addr = &dev->data->mac_addrs[i];
1952                         if (is_zero_ether_addr(addr))
1953                                 continue;
1954                         rte_memcpy(list->list[j].addr, addr->addr_bytes,
1955                                          sizeof(addr->addr_bytes));
1956                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1957                                     addr->addr_bytes[0], addr->addr_bytes[1],
1958                                     addr->addr_bytes[2], addr->addr_bytes[3],
1959                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1960                         j++;
1961                 }
1962                 list->vsi_id = vf->vsi_res->vsi_id;
1963                 list->num_elements = j;
1964                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1965                            VIRTCHNL_OP_DEL_ETH_ADDR;
1966                 args.in_args = (uint8_t *)list;
1967                 args.in_args_size = len;
1968                 args.out_buffer = vf->aq_resp;
1969                 args.out_size = I40E_AQ_BUF_SZ;
1970                 err = i40evf_execute_vf_cmd(dev, &args);
1971                 if (err) {
1972                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1973                                     add ? "OP_ADD_ETHER_ADDRESS" :
1974                                     "OP_DEL_ETHER_ADDRESS");
1975                 } else {
1976                         if (add)
1977                                 vf->vsi.mac_num++;
1978                         else
1979                                 vf->vsi.mac_num--;
1980                 }
1981                 rte_free(list);
1982                 begin = next_begin;
1983         } while (begin < I40E_NUM_MACADDR_MAX);
1984 }
1985
1986 static int
1987 i40evf_dev_start(struct rte_eth_dev *dev)
1988 {
1989         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1990         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1991         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1992         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1993         uint32_t intr_vector = 0;
1994
1995         PMD_INIT_FUNC_TRACE();
1996
1997         hw->adapter_stopped = 0;
1998
1999         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2000         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2001                                         dev->data->nb_tx_queues);
2002
2003         /* check and configure queue intr-vector mapping */
2004         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2005                 intr_vector = dev->data->nb_rx_queues;
2006                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2007                         return -1;
2008         }
2009
2010         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2011                 intr_handle->intr_vec =
2012                         rte_zmalloc("intr_vec",
2013                                     dev->data->nb_rx_queues * sizeof(int), 0);
2014                 if (!intr_handle->intr_vec) {
2015                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2016                                      " intr_vec", dev->data->nb_rx_queues);
2017                         return -ENOMEM;
2018                 }
2019         }
2020
2021         if (i40evf_rx_init(dev) != 0){
2022                 PMD_DRV_LOG(ERR, "failed to do RX init");
2023                 return -1;
2024         }
2025
2026         i40evf_tx_init(dev);
2027
2028         if (i40evf_configure_vsi_queues(dev) != 0) {
2029                 PMD_DRV_LOG(ERR, "configure queues failed");
2030                 goto err_queue;
2031         }
2032         if (i40evf_config_irq_map(dev)) {
2033                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2034                 goto err_queue;
2035         }
2036
2037         /* Set all mac addrs */
2038         i40evf_add_del_all_mac_addr(dev, TRUE);
2039
2040         if (i40evf_start_queues(dev) != 0) {
2041                 PMD_DRV_LOG(ERR, "enable queues failed");
2042                 goto err_mac;
2043         }
2044
2045         i40evf_enable_queues_intr(dev);
2046         return 0;
2047
2048 err_mac:
2049         i40evf_add_del_all_mac_addr(dev, FALSE);
2050 err_queue:
2051         return -1;
2052 }
2053
2054 static void
2055 i40evf_dev_stop(struct rte_eth_dev *dev)
2056 {
2057         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2058         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2059         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060
2061         PMD_INIT_FUNC_TRACE();
2062
2063         if (hw->adapter_stopped == 1)
2064                 return;
2065         i40evf_stop_queues(dev);
2066         i40evf_disable_queues_intr(dev);
2067         i40e_dev_clear_queues(dev);
2068
2069         /* Clean datapath event and queue/vec mapping */
2070         rte_intr_efd_disable(intr_handle);
2071         if (intr_handle->intr_vec) {
2072                 rte_free(intr_handle->intr_vec);
2073                 intr_handle->intr_vec = NULL;
2074         }
2075         /* remove all mac addrs */
2076         i40evf_add_del_all_mac_addr(dev, FALSE);
2077         hw->adapter_stopped = 1;
2078
2079 }
2080
2081 static int
2082 i40evf_dev_link_update(struct rte_eth_dev *dev,
2083                        __rte_unused int wait_to_complete)
2084 {
2085         struct rte_eth_link new_link;
2086         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2087         /*
2088          * DPDK pf host provide interfacet to acquire link status
2089          * while Linux driver does not
2090          */
2091
2092         /* Linux driver PF host */
2093         switch (vf->link_speed) {
2094         case I40E_LINK_SPEED_100MB:
2095                 new_link.link_speed = ETH_SPEED_NUM_100M;
2096                 break;
2097         case I40E_LINK_SPEED_1GB:
2098                 new_link.link_speed = ETH_SPEED_NUM_1G;
2099                 break;
2100         case I40E_LINK_SPEED_10GB:
2101                 new_link.link_speed = ETH_SPEED_NUM_10G;
2102                 break;
2103         case I40E_LINK_SPEED_20GB:
2104                 new_link.link_speed = ETH_SPEED_NUM_20G;
2105                 break;
2106         case I40E_LINK_SPEED_25GB:
2107                 new_link.link_speed = ETH_SPEED_NUM_25G;
2108                 break;
2109         case I40E_LINK_SPEED_40GB:
2110                 new_link.link_speed = ETH_SPEED_NUM_40G;
2111                 break;
2112         default:
2113                 new_link.link_speed = ETH_SPEED_NUM_100M;
2114                 break;
2115         }
2116         /* full duplex only */
2117         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2118         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2119                                              ETH_LINK_DOWN;
2120
2121         i40evf_dev_atomic_write_link_status(dev, &new_link);
2122
2123         return 0;
2124 }
2125
2126 static void
2127 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2128 {
2129         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2130         int ret;
2131
2132         /* If enabled, just return */
2133         if (vf->promisc_unicast_enabled)
2134                 return;
2135
2136         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2137         if (ret == 0)
2138                 vf->promisc_unicast_enabled = TRUE;
2139 }
2140
2141 static void
2142 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2143 {
2144         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2145         int ret;
2146
2147         /* If disabled, just return */
2148         if (!vf->promisc_unicast_enabled)
2149                 return;
2150
2151         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2152         if (ret == 0)
2153                 vf->promisc_unicast_enabled = FALSE;
2154 }
2155
2156 static void
2157 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2158 {
2159         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2160         int ret;
2161
2162         /* If enabled, just return */
2163         if (vf->promisc_multicast_enabled)
2164                 return;
2165
2166         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2167         if (ret == 0)
2168                 vf->promisc_multicast_enabled = TRUE;
2169 }
2170
2171 static void
2172 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2173 {
2174         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2175         int ret;
2176
2177         /* If enabled, just return */
2178         if (!vf->promisc_multicast_enabled)
2179                 return;
2180
2181         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2182         if (ret == 0)
2183                 vf->promisc_multicast_enabled = FALSE;
2184 }
2185
2186 static void
2187 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2188 {
2189         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2190
2191         memset(dev_info, 0, sizeof(*dev_info));
2192         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2193         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2194         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2195         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2196         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2197         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2198         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2199         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2200         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2201         dev_info->rx_offload_capa =
2202                 DEV_RX_OFFLOAD_VLAN_STRIP |
2203                 DEV_RX_OFFLOAD_QINQ_STRIP |
2204                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2205                 DEV_RX_OFFLOAD_UDP_CKSUM |
2206                 DEV_RX_OFFLOAD_TCP_CKSUM;
2207         dev_info->tx_offload_capa =
2208                 DEV_TX_OFFLOAD_VLAN_INSERT |
2209                 DEV_TX_OFFLOAD_QINQ_INSERT |
2210                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2211                 DEV_TX_OFFLOAD_UDP_CKSUM |
2212                 DEV_TX_OFFLOAD_TCP_CKSUM |
2213                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2214
2215         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2216                 .rx_thresh = {
2217                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2218                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2219                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2220                 },
2221                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2222                 .rx_drop_en = 0,
2223         };
2224
2225         dev_info->default_txconf = (struct rte_eth_txconf) {
2226                 .tx_thresh = {
2227                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2228                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2229                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2230                 },
2231                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2232                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2233                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2234                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2235         };
2236
2237         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2238                 .nb_max = I40E_MAX_RING_DESC,
2239                 .nb_min = I40E_MIN_RING_DESC,
2240                 .nb_align = I40E_ALIGN_RING_DESC,
2241         };
2242
2243         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2244                 .nb_max = I40E_MAX_RING_DESC,
2245                 .nb_min = I40E_MIN_RING_DESC,
2246                 .nb_align = I40E_ALIGN_RING_DESC,
2247         };
2248 }
2249
2250 static void
2251 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2252 {
2253         if (i40evf_get_statistics(dev, stats))
2254                 PMD_DRV_LOG(ERR, "Get statistics failed");
2255 }
2256
2257 static void
2258 i40evf_dev_close(struct rte_eth_dev *dev)
2259 {
2260         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2261         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2262         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2263
2264         i40evf_dev_stop(dev);
2265         i40e_dev_free_queues(dev);
2266         i40evf_reset_vf(hw);
2267         i40e_shutdown_adminq(hw);
2268         /* disable uio intr before callback unregister */
2269         rte_intr_disable(intr_handle);
2270
2271         /* unregister callback func from eal lib */
2272         rte_intr_callback_unregister(intr_handle,
2273                                      i40evf_dev_interrupt_handler, dev);
2274         i40evf_disable_irq0(hw);
2275 }
2276
2277 /*
2278  * Reset VF device only to re-initialize resources in PMD layer
2279  */
2280 static int
2281 i40evf_dev_reset(struct rte_eth_dev *dev)
2282 {
2283         int ret;
2284
2285         ret = i40evf_dev_uninit(dev);
2286         if (ret)
2287                 return ret;
2288
2289         ret = i40evf_dev_init(dev);
2290
2291         return ret;
2292 }
2293
2294 static int
2295 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2296 {
2297         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2298         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2299         int ret;
2300
2301         if (!lut)
2302                 return -EINVAL;
2303
2304         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2305                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2306                                           lut, lut_size);
2307                 if (ret) {
2308                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2309                         return ret;
2310                 }
2311         } else {
2312                 uint32_t *lut_dw = (uint32_t *)lut;
2313                 uint16_t i, lut_size_dw = lut_size / 4;
2314
2315                 for (i = 0; i < lut_size_dw; i++)
2316                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2317         }
2318
2319         return 0;
2320 }
2321
2322 static int
2323 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2324 {
2325         struct i40e_vf *vf;
2326         struct i40e_hw *hw;
2327         int ret;
2328
2329         if (!vsi || !lut)
2330                 return -EINVAL;
2331
2332         vf = I40E_VSI_TO_VF(vsi);
2333         hw = I40E_VSI_TO_HW(vsi);
2334
2335         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2336                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2337                                           lut, lut_size);
2338                 if (ret) {
2339                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2340                         return ret;
2341                 }
2342         } else {
2343                 uint32_t *lut_dw = (uint32_t *)lut;
2344                 uint16_t i, lut_size_dw = lut_size / 4;
2345
2346                 for (i = 0; i < lut_size_dw; i++)
2347                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2348                 I40EVF_WRITE_FLUSH(hw);
2349         }
2350
2351         return 0;
2352 }
2353
2354 static int
2355 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2356                            struct rte_eth_rss_reta_entry64 *reta_conf,
2357                            uint16_t reta_size)
2358 {
2359         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2360         uint8_t *lut;
2361         uint16_t i, idx, shift;
2362         int ret;
2363
2364         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2365                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2366                         "(%d) doesn't match the number of hardware can "
2367                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2368                 return -EINVAL;
2369         }
2370
2371         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2372         if (!lut) {
2373                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2374                 return -ENOMEM;
2375         }
2376         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2377         if (ret)
2378                 goto out;
2379         for (i = 0; i < reta_size; i++) {
2380                 idx = i / RTE_RETA_GROUP_SIZE;
2381                 shift = i % RTE_RETA_GROUP_SIZE;
2382                 if (reta_conf[idx].mask & (1ULL << shift))
2383                         lut[i] = reta_conf[idx].reta[shift];
2384         }
2385         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2386
2387 out:
2388         rte_free(lut);
2389
2390         return ret;
2391 }
2392
2393 static int
2394 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2395                           struct rte_eth_rss_reta_entry64 *reta_conf,
2396                           uint16_t reta_size)
2397 {
2398         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2399         uint16_t i, idx, shift;
2400         uint8_t *lut;
2401         int ret;
2402
2403         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2404                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2405                         "(%d) doesn't match the number of hardware can "
2406                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2407                 return -EINVAL;
2408         }
2409
2410         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2411         if (!lut) {
2412                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2413                 return -ENOMEM;
2414         }
2415
2416         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2417         if (ret)
2418                 goto out;
2419         for (i = 0; i < reta_size; i++) {
2420                 idx = i / RTE_RETA_GROUP_SIZE;
2421                 shift = i % RTE_RETA_GROUP_SIZE;
2422                 if (reta_conf[idx].mask & (1ULL << shift))
2423                         reta_conf[idx].reta[shift] = lut[i];
2424         }
2425
2426 out:
2427         rte_free(lut);
2428
2429         return ret;
2430 }
2431
2432 static int
2433 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2434 {
2435         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2436         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2437         int ret = 0;
2438
2439         if (!key || key_len == 0) {
2440                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2441                 return 0;
2442         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2443                 sizeof(uint32_t)) {
2444                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2445                 return -EINVAL;
2446         }
2447
2448         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2449                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2450                         (struct i40e_aqc_get_set_rss_key_data *)key;
2451
2452                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2453                 if (ret)
2454                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2455                                      "via AQ");
2456         } else {
2457                 uint32_t *hash_key = (uint32_t *)key;
2458                 uint16_t i;
2459
2460                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2461                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2462                 I40EVF_WRITE_FLUSH(hw);
2463         }
2464
2465         return ret;
2466 }
2467
2468 static int
2469 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2470 {
2471         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2472         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2473         int ret;
2474
2475         if (!key || !key_len)
2476                 return -EINVAL;
2477
2478         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2479                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2480                         (struct i40e_aqc_get_set_rss_key_data *)key);
2481                 if (ret) {
2482                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2483                         return ret;
2484                 }
2485         } else {
2486                 uint32_t *key_dw = (uint32_t *)key;
2487                 uint16_t i;
2488
2489                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2490                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2491         }
2492         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2493
2494         return 0;
2495 }
2496
2497 static int
2498 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2499 {
2500         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2501         uint64_t rss_hf, hena;
2502         int ret;
2503
2504         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2505                                  rss_conf->rss_key_len);
2506         if (ret)
2507                 return ret;
2508
2509         rss_hf = rss_conf->rss_hf;
2510         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2511         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2512         if (hw->mac.type == I40E_MAC_X722)
2513                 hena &= ~I40E_RSS_HENA_ALL_X722;
2514         else
2515                 hena &= ~I40E_RSS_HENA_ALL;
2516         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2517         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2518         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2519         I40EVF_WRITE_FLUSH(hw);
2520
2521         return 0;
2522 }
2523
2524 static void
2525 i40evf_disable_rss(struct i40e_vf *vf)
2526 {
2527         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2528         uint64_t hena;
2529
2530         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2531         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2532         if (hw->mac.type == I40E_MAC_X722)
2533                 hena &= ~I40E_RSS_HENA_ALL_X722;
2534         else
2535                 hena &= ~I40E_RSS_HENA_ALL;
2536         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2537         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2538         I40EVF_WRITE_FLUSH(hw);
2539 }
2540
2541 static int
2542 i40evf_config_rss(struct i40e_vf *vf)
2543 {
2544         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2545         struct rte_eth_rss_conf rss_conf;
2546         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2547         uint16_t num;
2548
2549         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2550                 i40evf_disable_rss(vf);
2551                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2552                 return 0;
2553         }
2554
2555         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2556         /* Fill out the look up table */
2557         for (i = 0, j = 0; i < nb_q; i++, j++) {
2558                 if (j >= num)
2559                         j = 0;
2560                 lut = (lut << 8) | j;
2561                 if ((i & 3) == 3)
2562                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2563         }
2564
2565         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2566         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2567                 i40evf_disable_rss(vf);
2568                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2569                 return 0;
2570         }
2571
2572         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2573                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2574                 /* Calculate the default hash key */
2575                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2576                         rss_key_default[i] = (uint32_t)rte_rand();
2577                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2578                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2579                         sizeof(uint32_t);
2580         }
2581
2582         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2583 }
2584
2585 static int
2586 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2587                            struct rte_eth_rss_conf *rss_conf)
2588 {
2589         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2590         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2591         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2592         uint64_t hena;
2593
2594         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2595         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2596         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2597                  ? I40E_RSS_HENA_ALL_X722
2598                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2599                 if (rss_hf != 0) /* Enable RSS */
2600                         return -EINVAL;
2601                 return 0;
2602         }
2603
2604         /* RSS enabled */
2605         if (rss_hf == 0) /* Disable RSS */
2606                 return -EINVAL;
2607
2608         return i40evf_hw_rss_hash_set(vf, rss_conf);
2609 }
2610
2611 static int
2612 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2613                              struct rte_eth_rss_conf *rss_conf)
2614 {
2615         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2616         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2617         uint64_t hena;
2618
2619         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2620                            &rss_conf->rss_key_len);
2621
2622         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2623         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2624         rss_conf->rss_hf = i40e_parse_hena(hena);
2625
2626         return 0;
2627 }
2628
2629 static int
2630 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2631 {
2632         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2633         struct rte_eth_dev_data *dev_data = vf->dev_data;
2634         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2635         int ret = 0;
2636
2637         /* check if mtu is within the allowed range */
2638         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2639                 return -EINVAL;
2640
2641         /* mtu setting is forbidden if port is start */
2642         if (dev_data->dev_started) {
2643                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2644                             dev_data->port_id);
2645                 return -EBUSY;
2646         }
2647
2648         if (frame_size > ETHER_MAX_LEN)
2649                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2650         else
2651                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2652
2653         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2654
2655         return ret;
2656 }
2657
2658 static void
2659 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2660                             struct ether_addr *mac_addr)
2661 {
2662         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2663
2664         if (!is_valid_assigned_ether_addr(mac_addr)) {
2665                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2666                 return;
2667         }
2668
2669         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2670                 return;
2671
2672         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2673                 return;
2674
2675         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2676
2677         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2678 }