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34 #include <sys/queue.h>
42 #include <rte_byteorder.h>
43 #include <rte_common.h>
44 #include <rte_cycles.h>
46 #include <rte_interrupts.h>
48 #include <rte_debug.h>
50 #include <rte_bus_pci.h>
51 #include <rte_atomic.h>
52 #include <rte_branch_prediction.h>
53 #include <rte_memory.h>
54 #include <rte_memzone.h>
56 #include <rte_alarm.h>
57 #include <rte_ether.h>
58 #include <rte_ethdev.h>
59 #include <rte_ethdev_pci.h>
60 #include <rte_malloc.h>
63 #include "i40e_logs.h"
64 #include "base/i40e_prototype.h"
65 #include "base/i40e_adminq_cmd.h"
66 #include "base/i40e_type.h"
68 #include "i40e_rxtx.h"
69 #include "i40e_ethdev.h"
71 #define I40EVF_VSI_DEFAULT_MSIX_INTR 1
72 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
74 /* busy wait delay in msec */
75 #define I40EVF_BUSY_WAIT_DELAY 10
76 #define I40EVF_BUSY_WAIT_COUNT 50
77 #define MAX_RESET_WAIT_CNT 20
79 struct i40evf_arq_msg_info {
80 enum virtchnl_ops ops;
81 enum i40e_status_code result;
88 enum virtchnl_ops ops;
90 uint32_t in_args_size;
92 /* Input & output type. pass in buffer size and pass out
93 * actual return result
98 enum i40evf_aq_result {
99 I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
100 I40EVF_MSG_NON, /* Read nothing from admin queue */
101 I40EVF_MSG_SYS, /* Read system msg from admin queue */
102 I40EVF_MSG_CMD, /* Read async command result */
105 static int i40evf_dev_configure(struct rte_eth_dev *dev);
106 static int i40evf_dev_start(struct rte_eth_dev *dev);
107 static void i40evf_dev_stop(struct rte_eth_dev *dev);
108 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
109 struct rte_eth_dev_info *dev_info);
110 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
111 int wait_to_complete);
112 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
113 struct rte_eth_stats *stats);
114 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
115 struct rte_eth_xstat *xstats, unsigned n);
116 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
117 struct rte_eth_xstat_name *xstats_names,
119 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
120 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
121 uint16_t vlan_id, int on);
122 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
123 static void i40evf_dev_close(struct rte_eth_dev *dev);
124 static int i40evf_dev_reset(struct rte_eth_dev *dev);
125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
131 uint16_t rx_queue_id);
132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
133 uint16_t rx_queue_id);
134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
135 uint16_t tx_queue_id);
136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
137 uint16_t tx_queue_id);
138 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
139 struct ether_addr *addr,
142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
144 struct rte_eth_rss_reta_entry64 *reta_conf,
146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
147 struct rte_eth_rss_reta_entry64 *reta_conf,
149 static int i40evf_config_rss(struct i40e_vf *vf);
150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
151 struct rte_eth_rss_conf *rss_conf);
152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
153 struct rte_eth_rss_conf *rss_conf);
154 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
155 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
156 struct ether_addr *mac_addr);
158 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
160 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
161 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
165 /* Default hash key buffer for RSS */
166 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
168 struct rte_i40evf_xstats_name_off {
169 char name[RTE_ETH_XSTATS_NAME_SIZE];
173 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
174 {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
175 {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
176 {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
177 {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
178 {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
179 {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
180 rx_unknown_protocol)},
181 {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
182 {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
183 {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
184 {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
185 {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
186 {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
189 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
190 sizeof(rte_i40evf_stats_strings[0]))
192 static const struct eth_dev_ops i40evf_eth_dev_ops = {
193 .dev_configure = i40evf_dev_configure,
194 .dev_start = i40evf_dev_start,
195 .dev_stop = i40evf_dev_stop,
196 .promiscuous_enable = i40evf_dev_promiscuous_enable,
197 .promiscuous_disable = i40evf_dev_promiscuous_disable,
198 .allmulticast_enable = i40evf_dev_allmulticast_enable,
199 .allmulticast_disable = i40evf_dev_allmulticast_disable,
200 .link_update = i40evf_dev_link_update,
201 .stats_get = i40evf_dev_stats_get,
202 .stats_reset = i40evf_dev_xstats_reset,
203 .xstats_get = i40evf_dev_xstats_get,
204 .xstats_get_names = i40evf_dev_xstats_get_names,
205 .xstats_reset = i40evf_dev_xstats_reset,
206 .dev_close = i40evf_dev_close,
207 .dev_reset = i40evf_dev_reset,
208 .dev_infos_get = i40evf_dev_info_get,
209 .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
210 .vlan_filter_set = i40evf_vlan_filter_set,
211 .vlan_offload_set = i40evf_vlan_offload_set,
212 .rx_queue_start = i40evf_dev_rx_queue_start,
213 .rx_queue_stop = i40evf_dev_rx_queue_stop,
214 .tx_queue_start = i40evf_dev_tx_queue_start,
215 .tx_queue_stop = i40evf_dev_tx_queue_stop,
216 .rx_queue_setup = i40e_dev_rx_queue_setup,
217 .rx_queue_release = i40e_dev_rx_queue_release,
218 .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
219 .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
220 .rx_descriptor_done = i40e_dev_rx_descriptor_done,
221 .rx_descriptor_status = i40e_dev_rx_descriptor_status,
222 .tx_descriptor_status = i40e_dev_tx_descriptor_status,
223 .tx_queue_setup = i40e_dev_tx_queue_setup,
224 .tx_queue_release = i40e_dev_tx_queue_release,
225 .rx_queue_count = i40e_dev_rx_queue_count,
226 .rxq_info_get = i40e_rxq_info_get,
227 .txq_info_get = i40e_txq_info_get,
228 .mac_addr_add = i40evf_add_mac_addr,
229 .mac_addr_remove = i40evf_del_mac_addr,
230 .reta_update = i40evf_dev_rss_reta_update,
231 .reta_query = i40evf_dev_rss_reta_query,
232 .rss_hash_update = i40evf_dev_rss_hash_update,
233 .rss_hash_conf_get = i40evf_dev_rss_hash_conf_get,
234 .mtu_set = i40evf_dev_mtu_set,
235 .mac_addr_set = i40evf_set_default_mac_addr,
239 * Read data in admin queue to get msg from pf driver
241 static enum i40evf_aq_result
242 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
244 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
245 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
246 struct i40e_arq_event_info event;
247 enum virtchnl_ops opcode;
248 enum i40e_status_code retval;
250 enum i40evf_aq_result result = I40EVF_MSG_NON;
252 event.buf_len = data->buf_len;
253 event.msg_buf = data->msg;
254 ret = i40e_clean_arq_element(hw, &event, NULL);
255 /* Can't read any msg from adminQ */
257 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
258 result = I40EVF_MSG_ERR;
262 opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
263 retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
265 if (opcode == VIRTCHNL_OP_EVENT) {
266 struct virtchnl_pf_event *vpe =
267 (struct virtchnl_pf_event *)event.msg_buf;
269 result = I40EVF_MSG_SYS;
270 switch (vpe->event) {
271 case VIRTCHNL_EVENT_LINK_CHANGE:
273 vpe->event_data.link_event.link_status;
275 vpe->event_data.link_event.link_speed;
276 vf->pend_msg |= PFMSG_LINK_CHANGE;
277 PMD_DRV_LOG(INFO, "Link status update:%s",
278 vf->link_up ? "up" : "down");
280 case VIRTCHNL_EVENT_RESET_IMPENDING:
282 vf->pend_msg |= PFMSG_RESET_IMPENDING;
283 PMD_DRV_LOG(INFO, "vf is reseting");
285 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
286 vf->dev_closed = true;
287 vf->pend_msg |= PFMSG_DRIVER_CLOSE;
288 PMD_DRV_LOG(INFO, "PF driver closed");
291 PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
292 __func__, vpe->event);
295 /* async reply msg on command issued by vf previously */
296 result = I40EVF_MSG_CMD;
297 /* Actual data length read from PF */
298 data->msg_len = event.msg_len;
301 data->result = retval;
308 * clear current command. Only call in case execute
309 * _atomic_set_cmd successfully.
312 _clear_cmd(struct i40e_vf *vf)
315 vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
319 * Check there is pending cmd in execution. If none, set new command.
322 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
324 int ret = rte_atomic32_cmpset(&vf->pend_cmd,
325 VIRTCHNL_OP_UNKNOWN, ops);
328 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
333 #define MAX_TRY_TIMES 200
334 #define ASQ_DELAY_MS 10
337 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
339 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
340 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
341 struct i40evf_arq_msg_info info;
342 enum i40evf_aq_result ret;
345 if (_atomic_set_cmd(vf, args->ops))
348 info.msg = args->out_buffer;
349 info.buf_len = args->out_size;
350 info.ops = VIRTCHNL_OP_UNKNOWN;
351 info.result = I40E_SUCCESS;
353 err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
354 args->in_args, args->in_args_size, NULL);
356 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
362 case VIRTCHNL_OP_RESET_VF:
363 /*no need to process in this function */
366 case VIRTCHNL_OP_VERSION:
367 case VIRTCHNL_OP_GET_VF_RESOURCES:
368 /* for init adminq commands, need to poll the response */
371 ret = i40evf_read_pfmsg(dev, &info);
372 vf->cmd_retval = info.result;
373 if (ret == I40EVF_MSG_CMD) {
376 } else if (ret == I40EVF_MSG_ERR)
378 rte_delay_ms(ASQ_DELAY_MS);
379 /* If don't read msg or read sys event, continue */
380 } while (i++ < MAX_TRY_TIMES);
385 /* for other adminq in running time, waiting the cmd done flag */
388 if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
392 rte_delay_ms(ASQ_DELAY_MS);
393 /* If don't read msg or read sys event, continue */
394 } while (i++ < MAX_TRY_TIMES);
395 /* If there's no response is received, clear command */
396 if (i >= MAX_TRY_TIMES) {
397 PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
403 return err | vf->cmd_retval;
407 * Check API version with sync wait until version read or fail from admin queue
410 i40evf_check_api_version(struct rte_eth_dev *dev)
412 struct virtchnl_version_info version, *pver;
414 struct vf_cmd_info args;
415 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
417 version.major = VIRTCHNL_VERSION_MAJOR;
418 version.minor = VIRTCHNL_VERSION_MINOR;
420 args.ops = VIRTCHNL_OP_VERSION;
421 args.in_args = (uint8_t *)&version;
422 args.in_args_size = sizeof(version);
423 args.out_buffer = vf->aq_resp;
424 args.out_size = I40E_AQ_BUF_SZ;
426 err = i40evf_execute_vf_cmd(dev, &args);
428 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
432 pver = (struct virtchnl_version_info *)args.out_buffer;
433 vf->version_major = pver->major;
434 vf->version_minor = pver->minor;
435 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
436 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
437 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
439 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
440 vf->version_major, vf->version_minor,
441 VIRTCHNL_VERSION_MAJOR,
442 VIRTCHNL_VERSION_MINOR);
450 i40evf_get_vf_resource(struct rte_eth_dev *dev)
452 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
453 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
455 struct vf_cmd_info args;
458 args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
459 args.out_buffer = vf->aq_resp;
460 args.out_size = I40E_AQ_BUF_SZ;
462 caps = VIRTCHNL_VF_OFFLOAD_L2 |
463 VIRTCHNL_VF_OFFLOAD_RSS_AQ |
464 VIRTCHNL_VF_OFFLOAD_RSS_REG |
465 VIRTCHNL_VF_OFFLOAD_VLAN |
466 VIRTCHNL_VF_OFFLOAD_RX_POLLING;
467 args.in_args = (uint8_t *)∩︀
468 args.in_args_size = sizeof(caps);
471 args.in_args_size = 0;
473 err = i40evf_execute_vf_cmd(dev, &args);
476 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
480 len = sizeof(struct virtchnl_vf_resource) +
481 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
483 rte_memcpy(vf->vf_res, args.out_buffer,
484 RTE_MIN(args.out_size, len));
485 i40e_vf_parse_hw_config(hw, vf->vf_res);
491 i40evf_config_promisc(struct rte_eth_dev *dev,
493 bool enable_multicast)
495 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
497 struct vf_cmd_info args;
498 struct virtchnl_promisc_info promisc;
501 promisc.vsi_id = vf->vsi_res->vsi_id;
504 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
506 if (enable_multicast)
507 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
509 args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
510 args.in_args = (uint8_t *)&promisc;
511 args.in_args_size = sizeof(promisc);
512 args.out_buffer = vf->aq_resp;
513 args.out_size = I40E_AQ_BUF_SZ;
515 err = i40evf_execute_vf_cmd(dev, &args);
518 PMD_DRV_LOG(ERR, "fail to execute command "
519 "CONFIG_PROMISCUOUS_MODE");
524 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
526 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
527 struct vf_cmd_info args;
530 memset(&args, 0, sizeof(args));
531 args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
533 args.in_args_size = 0;
534 args.out_buffer = vf->aq_resp;
535 args.out_size = I40E_AQ_BUF_SZ;
536 ret = i40evf_execute_vf_cmd(dev, &args);
538 PMD_DRV_LOG(ERR, "Failed to execute command of "
539 "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
545 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
547 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
548 struct vf_cmd_info args;
551 memset(&args, 0, sizeof(args));
552 args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
554 args.in_args_size = 0;
555 args.out_buffer = vf->aq_resp;
556 args.out_size = I40E_AQ_BUF_SZ;
557 ret = i40evf_execute_vf_cmd(dev, &args);
559 PMD_DRV_LOG(ERR, "Failed to execute command of "
560 "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
566 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
570 struct i40e_tx_queue *txq)
572 txq_info->vsi_id = vsi_id;
573 txq_info->queue_id = queue_id;
574 if (queue_id < nb_txq) {
575 txq_info->ring_len = txq->nb_tx_desc;
576 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
581 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
585 uint32_t max_pkt_size,
586 struct i40e_rx_queue *rxq)
588 rxq_info->vsi_id = vsi_id;
589 rxq_info->queue_id = queue_id;
590 rxq_info->max_pkt_size = max_pkt_size;
591 if (queue_id < nb_rxq) {
592 rxq_info->ring_len = rxq->nb_rx_desc;
593 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
594 rxq_info->databuffer_size =
595 (rte_pktmbuf_data_room_size(rxq->mp) -
596 RTE_PKTMBUF_HEADROOM);
601 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
603 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
604 struct i40e_rx_queue **rxq =
605 (struct i40e_rx_queue **)dev->data->rx_queues;
606 struct i40e_tx_queue **txq =
607 (struct i40e_tx_queue **)dev->data->tx_queues;
608 struct virtchnl_vsi_queue_config_info *vc_vqci;
609 struct virtchnl_queue_pair_info *vc_qpi;
610 struct vf_cmd_info args;
611 uint16_t i, nb_qp = vf->num_queue_pairs;
612 const uint32_t size =
613 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
617 memset(buff, 0, sizeof(buff));
618 vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
619 vc_vqci->vsi_id = vf->vsi_res->vsi_id;
620 vc_vqci->num_queue_pairs = nb_qp;
622 for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
623 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
624 vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
625 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
626 vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
627 vf->max_pkt_len, rxq[i]);
629 memset(&args, 0, sizeof(args));
630 args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
631 args.in_args = (uint8_t *)vc_vqci;
632 args.in_args_size = size;
633 args.out_buffer = vf->aq_resp;
634 args.out_size = I40E_AQ_BUF_SZ;
635 ret = i40evf_execute_vf_cmd(dev, &args);
637 PMD_DRV_LOG(ERR, "Failed to execute command of "
638 "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
644 i40evf_config_irq_map(struct rte_eth_dev *dev)
646 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
647 struct vf_cmd_info args;
648 uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
649 sizeof(struct virtchnl_vector_map)];
650 struct virtchnl_irq_map_info *map_info;
651 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
652 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
656 if (rte_intr_allow_others(intr_handle))
657 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
659 vector_id = I40E_MISC_VEC_ID;
661 map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
662 map_info->num_vectors = 1;
663 map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
664 map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
665 /* Alway use default dynamic MSIX interrupt */
666 map_info->vecmap[0].vector_id = vector_id;
667 /* Don't map any tx queue */
668 map_info->vecmap[0].txq_map = 0;
669 map_info->vecmap[0].rxq_map = 0;
670 for (i = 0; i < dev->data->nb_rx_queues; i++) {
671 map_info->vecmap[0].rxq_map |= 1 << i;
672 if (rte_intr_dp_is_en(intr_handle))
673 intr_handle->intr_vec[i] = vector_id;
676 args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
677 args.in_args = (u8 *)cmd_buffer;
678 args.in_args_size = sizeof(cmd_buffer);
679 args.out_buffer = vf->aq_resp;
680 args.out_size = I40E_AQ_BUF_SZ;
681 err = i40evf_execute_vf_cmd(dev, &args);
683 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
689 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
692 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
693 struct virtchnl_queue_select queue_select;
695 struct vf_cmd_info args;
696 memset(&queue_select, 0, sizeof(queue_select));
697 queue_select.vsi_id = vf->vsi_res->vsi_id;
700 queue_select.rx_queues |= 1 << qid;
702 queue_select.tx_queues |= 1 << qid;
705 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
707 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
708 args.in_args = (u8 *)&queue_select;
709 args.in_args_size = sizeof(queue_select);
710 args.out_buffer = vf->aq_resp;
711 args.out_size = I40E_AQ_BUF_SZ;
712 err = i40evf_execute_vf_cmd(dev, &args);
714 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
715 isrx ? "RX" : "TX", qid, on ? "on" : "off");
721 i40evf_start_queues(struct rte_eth_dev *dev)
723 struct rte_eth_dev_data *dev_data = dev->data;
725 struct i40e_rx_queue *rxq;
726 struct i40e_tx_queue *txq;
728 for (i = 0; i < dev->data->nb_rx_queues; i++) {
729 rxq = dev_data->rx_queues[i];
730 if (rxq->rx_deferred_start)
732 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
733 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
738 for (i = 0; i < dev->data->nb_tx_queues; i++) {
739 txq = dev_data->tx_queues[i];
740 if (txq->tx_deferred_start)
742 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
743 PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
752 i40evf_stop_queues(struct rte_eth_dev *dev)
756 /* Stop TX queues first */
757 for (i = 0; i < dev->data->nb_tx_queues; i++) {
758 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
759 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
764 /* Then stop RX queues */
765 for (i = 0; i < dev->data->nb_rx_queues; i++) {
766 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
767 PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
776 i40evf_add_mac_addr(struct rte_eth_dev *dev,
777 struct ether_addr *addr,
778 __rte_unused uint32_t index,
779 __rte_unused uint32_t pool)
781 struct virtchnl_ether_addr_list *list;
782 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
783 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
784 sizeof(struct virtchnl_ether_addr)];
786 struct vf_cmd_info args;
788 if (is_zero_ether_addr(addr)) {
789 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
790 addr->addr_bytes[0], addr->addr_bytes[1],
791 addr->addr_bytes[2], addr->addr_bytes[3],
792 addr->addr_bytes[4], addr->addr_bytes[5]);
793 return I40E_ERR_INVALID_MAC_ADDR;
796 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
797 list->vsi_id = vf->vsi_res->vsi_id;
798 list->num_elements = 1;
799 rte_memcpy(list->list[0].addr, addr->addr_bytes,
800 sizeof(addr->addr_bytes));
802 args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
803 args.in_args = cmd_buffer;
804 args.in_args_size = sizeof(cmd_buffer);
805 args.out_buffer = vf->aq_resp;
806 args.out_size = I40E_AQ_BUF_SZ;
807 err = i40evf_execute_vf_cmd(dev, &args);
809 PMD_DRV_LOG(ERR, "fail to execute command "
810 "OP_ADD_ETHER_ADDRESS");
818 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
819 struct ether_addr *addr)
821 struct virtchnl_ether_addr_list *list;
822 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
823 uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
824 sizeof(struct virtchnl_ether_addr)];
826 struct vf_cmd_info args;
828 if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
829 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
830 addr->addr_bytes[0], addr->addr_bytes[1],
831 addr->addr_bytes[2], addr->addr_bytes[3],
832 addr->addr_bytes[4], addr->addr_bytes[5]);
836 list = (struct virtchnl_ether_addr_list *)cmd_buffer;
837 list->vsi_id = vf->vsi_res->vsi_id;
838 list->num_elements = 1;
839 rte_memcpy(list->list[0].addr, addr->addr_bytes,
840 sizeof(addr->addr_bytes));
842 args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
843 args.in_args = cmd_buffer;
844 args.in_args_size = sizeof(cmd_buffer);
845 args.out_buffer = vf->aq_resp;
846 args.out_size = I40E_AQ_BUF_SZ;
847 err = i40evf_execute_vf_cmd(dev, &args);
849 PMD_DRV_LOG(ERR, "fail to execute command "
850 "OP_DEL_ETHER_ADDRESS");
857 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
859 struct rte_eth_dev_data *data = dev->data;
860 struct ether_addr *addr;
862 addr = &data->mac_addrs[index];
864 i40evf_del_mac_addr_by_addr(dev, addr);
868 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
870 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
871 struct virtchnl_queue_select q_stats;
873 struct vf_cmd_info args;
875 memset(&q_stats, 0, sizeof(q_stats));
876 q_stats.vsi_id = vf->vsi_res->vsi_id;
877 args.ops = VIRTCHNL_OP_GET_STATS;
878 args.in_args = (u8 *)&q_stats;
879 args.in_args_size = sizeof(q_stats);
880 args.out_buffer = vf->aq_resp;
881 args.out_size = I40E_AQ_BUF_SZ;
883 err = i40evf_execute_vf_cmd(dev, &args);
885 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
889 *pstats = (struct i40e_eth_stats *)args.out_buffer;
894 i40evf_stat_update_48(uint64_t *offset,
897 if (*stat >= *offset)
898 *stat = *stat - *offset;
900 *stat = (uint64_t)((*stat +
901 ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
903 *stat &= I40E_48_BIT_MASK;
907 i40evf_stat_update_32(uint64_t *offset,
910 if (*stat >= *offset)
911 *stat = (uint64_t)(*stat - *offset);
913 *stat = (uint64_t)((*stat +
914 ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
918 i40evf_update_stats(struct i40e_vsi *vsi,
919 struct i40e_eth_stats *nes)
921 struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
923 i40evf_stat_update_48(&oes->rx_bytes,
925 i40evf_stat_update_48(&oes->rx_unicast,
927 i40evf_stat_update_48(&oes->rx_multicast,
929 i40evf_stat_update_48(&oes->rx_broadcast,
931 i40evf_stat_update_32(&oes->rx_discards,
933 i40evf_stat_update_32(&oes->rx_unknown_protocol,
934 &nes->rx_unknown_protocol);
935 i40evf_stat_update_48(&oes->tx_bytes,
937 i40evf_stat_update_48(&oes->tx_unicast,
939 i40evf_stat_update_48(&oes->tx_multicast,
941 i40evf_stat_update_48(&oes->tx_broadcast,
943 i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
944 i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
948 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
950 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
951 struct i40e_eth_stats *pstats = NULL;
953 /* read stat values to clear hardware registers */
954 i40evf_query_stats(dev, &pstats);
956 /* set stats offset base on current values */
957 vf->vsi.eth_stats_offset = *pstats;
960 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
961 struct rte_eth_xstat_name *xstats_names,
962 __rte_unused unsigned limit)
966 if (xstats_names != NULL)
967 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
968 snprintf(xstats_names[i].name,
969 sizeof(xstats_names[i].name),
970 "%s", rte_i40evf_stats_strings[i].name);
972 return I40EVF_NB_XSTATS;
975 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
976 struct rte_eth_xstat *xstats, unsigned n)
980 struct i40e_eth_stats *pstats = NULL;
981 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
982 struct i40e_vsi *vsi = &vf->vsi;
984 if (n < I40EVF_NB_XSTATS)
985 return I40EVF_NB_XSTATS;
987 ret = i40evf_query_stats(dev, &pstats);
994 i40evf_update_stats(vsi, pstats);
996 /* loop over xstats array and values from pstats */
997 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
999 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1000 rte_i40evf_stats_strings[i].offset);
1003 return I40EVF_NB_XSTATS;
1007 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1009 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1010 struct virtchnl_vlan_filter_list *vlan_list;
1011 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1014 struct vf_cmd_info args;
1016 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1017 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1018 vlan_list->num_elements = 1;
1019 vlan_list->vlan_id[0] = vlanid;
1021 args.ops = VIRTCHNL_OP_ADD_VLAN;
1022 args.in_args = (u8 *)&cmd_buffer;
1023 args.in_args_size = sizeof(cmd_buffer);
1024 args.out_buffer = vf->aq_resp;
1025 args.out_size = I40E_AQ_BUF_SZ;
1026 err = i40evf_execute_vf_cmd(dev, &args);
1028 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1034 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1036 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1037 struct virtchnl_vlan_filter_list *vlan_list;
1038 uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1041 struct vf_cmd_info args;
1043 vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1044 vlan_list->vsi_id = vf->vsi_res->vsi_id;
1045 vlan_list->num_elements = 1;
1046 vlan_list->vlan_id[0] = vlanid;
1048 args.ops = VIRTCHNL_OP_DEL_VLAN;
1049 args.in_args = (u8 *)&cmd_buffer;
1050 args.in_args_size = sizeof(cmd_buffer);
1051 args.out_buffer = vf->aq_resp;
1052 args.out_size = I40E_AQ_BUF_SZ;
1053 err = i40evf_execute_vf_cmd(dev, &args);
1055 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1060 static const struct rte_pci_id pci_id_i40evf_map[] = {
1061 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1062 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1063 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1064 { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1065 { .vendor_id = 0, /* sentinel */ },
1069 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1070 struct rte_eth_link *link)
1072 struct rte_eth_link *dst = &(dev->data->dev_link);
1073 struct rte_eth_link *src = link;
1075 if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1076 *(uint64_t *)src) == 0)
1084 i40evf_disable_irq0(struct i40e_hw *hw)
1086 /* Disable all interrupt types */
1087 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1088 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1089 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1090 I40EVF_WRITE_FLUSH(hw);
1095 i40evf_enable_irq0(struct i40e_hw *hw)
1097 /* Enable admin queue interrupt trigger */
1100 i40evf_disable_irq0(hw);
1101 val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1102 val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1103 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1104 I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1106 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1107 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1108 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1109 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1111 I40EVF_WRITE_FLUSH(hw);
1115 i40evf_check_vf_reset_done(struct i40e_hw *hw)
1119 for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1120 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1121 I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1122 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1123 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1124 reset == VIRTCHNL_VFR_COMPLETED)
1129 if (i >= MAX_RESET_WAIT_CNT)
1135 i40evf_reset_vf(struct i40e_hw *hw)
1139 if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1140 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1144 * After issuing vf reset command to pf, pf won't necessarily
1145 * reset vf, it depends on what state it exactly is. If it's not
1146 * initialized yet, it won't have vf reset since it's in a certain
1147 * state. If not, it will try to reset. Even vf is reset, pf will
1148 * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1149 * it to ACTIVE. In this duration, vf may not catch the moment that
1150 * COMPLETE is set. So, for vf, we'll try to wait a long time.
1154 ret = i40evf_check_vf_reset_done(hw);
1156 PMD_INIT_LOG(ERR, "VF is still resetting");
1164 i40evf_init_vf(struct rte_eth_dev *dev)
1167 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1168 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1170 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1172 vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1173 vf->dev_data = dev->data;
1174 err = i40e_set_mac_type(hw);
1176 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1180 err = i40evf_check_vf_reset_done(hw);
1184 i40e_init_adminq_parameter(hw);
1185 err = i40e_init_adminq(hw);
1187 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1191 /* Reset VF and wait until it's complete */
1192 if (i40evf_reset_vf(hw)) {
1193 PMD_INIT_LOG(ERR, "reset NIC failed");
1197 /* VF reset, shutdown admin queue and initialize again */
1198 if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1199 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1203 i40e_init_adminq_parameter(hw);
1204 if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1205 PMD_INIT_LOG(ERR, "init_adminq failed");
1209 vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1211 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1214 if (i40evf_check_api_version(dev) != 0) {
1215 PMD_INIT_LOG(ERR, "check_api version failed");
1218 bufsz = sizeof(struct virtchnl_vf_resource) +
1219 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1220 vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1222 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1226 if (i40evf_get_vf_resource(dev) != 0) {
1227 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1231 /* got VF config message back from PF, now we can parse it */
1232 for (i = 0; i < vf->vf_res->num_vsis; i++) {
1233 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1234 vf->vsi_res = &vf->vf_res->vsi_res[i];
1238 PMD_INIT_LOG(ERR, "no LAN VSI found");
1242 if (hw->mac.type == I40E_MAC_X722_VF)
1243 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1244 vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1246 switch (vf->vsi_res->vsi_type) {
1247 case VIRTCHNL_VSI_SRIOV:
1248 vf->vsi.type = I40E_VSI_SRIOV;
1251 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1254 vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1255 vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1257 /* Store the MAC address configured by host, or generate random one */
1258 if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1259 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1261 eth_random_addr(hw->mac.addr); /* Generate a random one */
1263 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1264 (I40E_ITR_INDEX_DEFAULT <<
1265 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1267 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1268 I40EVF_WRITE_FLUSH(hw);
1273 rte_free(vf->vf_res);
1276 rte_free(vf->aq_resp);
1278 i40e_shutdown_adminq(hw); /* ignore error */
1284 i40evf_uninit_vf(struct rte_eth_dev *dev)
1286 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1287 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1289 PMD_INIT_FUNC_TRACE();
1291 if (hw->adapter_stopped == 0)
1292 i40evf_dev_close(dev);
1293 rte_free(vf->vf_res);
1295 rte_free(vf->aq_resp);
1302 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1303 __rte_unused uint16_t msglen)
1305 struct virtchnl_pf_event *pf_msg =
1306 (struct virtchnl_pf_event *)msg;
1307 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1309 switch (pf_msg->event) {
1310 case VIRTCHNL_EVENT_RESET_IMPENDING:
1311 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1312 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1315 case VIRTCHNL_EVENT_LINK_CHANGE:
1316 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1317 vf->link_up = pf_msg->event_data.link_event.link_status;
1318 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1320 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1321 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1324 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1330 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1332 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1334 struct i40e_arq_event_info info;
1335 uint16_t pending, aq_opc;
1336 enum virtchnl_ops msg_opc;
1337 enum i40e_status_code msg_ret;
1340 info.buf_len = I40E_AQ_BUF_SZ;
1342 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1345 info.msg_buf = vf->aq_resp;
1349 ret = i40e_clean_arq_element(hw, &info, &pending);
1351 if (ret != I40E_SUCCESS) {
1352 PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1356 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1357 /* For the message sent from pf to vf, opcode is stored in
1358 * cookie_high of struct i40e_aq_desc, while return error code
1359 * are stored in cookie_low, Which is done by
1360 * i40e_aq_send_msg_to_vf in PF driver.*/
1361 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1362 info.desc.cookie_high);
1363 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1364 info.desc.cookie_low);
1366 case i40e_aqc_opc_send_msg_to_vf:
1367 if (msg_opc == VIRTCHNL_OP_EVENT)
1369 i40evf_handle_pf_event(dev, info.msg_buf,
1372 /* read message and it's expected one */
1373 if (msg_opc == vf->pend_cmd) {
1374 vf->cmd_retval = msg_ret;
1375 /* prevent compiler reordering */
1376 rte_compiler_barrier();
1379 PMD_DRV_LOG(ERR, "command mismatch,"
1380 "expect %u, get %u",
1381 vf->pend_cmd, msg_opc);
1382 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1383 " opcode = %d", msg_opc);
1387 PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1395 * Interrupt handler triggered by NIC for handling
1396 * specific interrupt. Only adminq interrupt is processed in VF.
1399 * Pointer to interrupt handle.
1401 * The address of parameter (struct rte_eth_dev *) regsitered before.
1407 i40evf_dev_interrupt_handler(void *param)
1409 struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1410 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1413 i40evf_disable_irq0(hw);
1415 /* read out interrupt causes */
1416 icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1418 /* No interrupt event indicated */
1419 if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1420 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1424 if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1425 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1426 i40evf_handle_aq_msg(dev);
1429 /* Link Status Change interrupt */
1430 if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1431 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1435 i40evf_enable_irq0(hw);
1436 rte_intr_enable(dev->intr_handle);
1440 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1443 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1444 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1446 PMD_INIT_FUNC_TRACE();
1448 /* assign ops func pointer */
1449 eth_dev->dev_ops = &i40evf_eth_dev_ops;
1450 eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1451 eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1454 * For secondary processes, we don't initialise any further as primary
1455 * has already done this work.
1457 if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1458 i40e_set_rx_function(eth_dev);
1459 i40e_set_tx_function(eth_dev);
1462 i40e_set_default_ptype_table(eth_dev);
1463 i40e_set_default_pctype_table(eth_dev);
1464 rte_eth_copy_pci_info(eth_dev, pci_dev);
1466 hw->vendor_id = pci_dev->id.vendor_id;
1467 hw->device_id = pci_dev->id.device_id;
1468 hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1469 hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1470 hw->bus.device = pci_dev->addr.devid;
1471 hw->bus.func = pci_dev->addr.function;
1472 hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1473 hw->adapter_stopped = 0;
1475 if(i40evf_init_vf(eth_dev) != 0) {
1476 PMD_INIT_LOG(ERR, "Init vf failed");
1480 /* register callback func to eal lib */
1481 rte_intr_callback_register(&pci_dev->intr_handle,
1482 i40evf_dev_interrupt_handler, (void *)eth_dev);
1484 /* enable uio intr after callback register */
1485 rte_intr_enable(&pci_dev->intr_handle);
1487 /* configure and enable device interrupt */
1488 i40evf_enable_irq0(hw);
1491 eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1492 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1494 if (eth_dev->data->mac_addrs == NULL) {
1495 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1496 " store MAC addresses",
1497 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1500 ether_addr_copy((struct ether_addr *)hw->mac.addr,
1501 ð_dev->data->mac_addrs[0]);
1507 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1509 PMD_INIT_FUNC_TRACE();
1511 if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1514 eth_dev->dev_ops = NULL;
1515 eth_dev->rx_pkt_burst = NULL;
1516 eth_dev->tx_pkt_burst = NULL;
1518 if (i40evf_uninit_vf(eth_dev) != 0) {
1519 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1523 rte_free(eth_dev->data->mac_addrs);
1524 eth_dev->data->mac_addrs = NULL;
1529 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1530 struct rte_pci_device *pci_dev)
1532 return rte_eth_dev_pci_generic_probe(pci_dev,
1533 sizeof(struct i40e_adapter), i40evf_dev_init);
1536 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1538 return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1542 * virtual function driver struct
1544 static struct rte_pci_driver rte_i40evf_pmd = {
1545 .id_table = pci_id_i40evf_map,
1546 .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1547 .probe = eth_i40evf_pci_probe,
1548 .remove = eth_i40evf_pci_remove,
1551 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1552 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1553 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1556 i40evf_dev_configure(struct rte_eth_dev *dev)
1558 struct i40e_adapter *ad =
1559 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1560 struct rte_eth_conf *conf = &dev->data->dev_conf;
1563 /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1564 * allocation or vector Rx preconditions we will reset it.
1566 ad->rx_bulk_alloc_allowed = true;
1567 ad->rx_vec_allowed = true;
1568 ad->tx_simple_allowed = true;
1569 ad->tx_vec_allowed = true;
1571 /* For non-DPDK PF drivers, VF has no ability to disable HW
1572 * CRC strip, and is implicitly enabled by the PF.
1574 if (!conf->rxmode.hw_strip_crc) {
1575 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1576 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1577 (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1578 /* Peer is running non-DPDK PF driver. */
1579 PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1584 return i40evf_init_vlan(dev);
1588 i40evf_init_vlan(struct rte_eth_dev *dev)
1590 /* Apply vlan offload setting */
1591 return i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1595 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1597 struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1599 /* Vlan stripping setting */
1600 if (mask & ETH_VLAN_STRIP_MASK) {
1601 /* Enable or disable VLAN stripping */
1602 if (dev_conf->rxmode.hw_vlan_strip)
1603 i40evf_enable_vlan_strip(dev);
1605 i40evf_disable_vlan_strip(dev);
1612 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1614 struct i40e_rx_queue *rxq;
1616 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1618 PMD_INIT_FUNC_TRACE();
1620 if (rx_queue_id < dev->data->nb_rx_queues) {
1621 rxq = dev->data->rx_queues[rx_queue_id];
1623 err = i40e_alloc_rx_queue_mbufs(rxq);
1625 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1631 /* Init the RX tail register. */
1632 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1633 I40EVF_WRITE_FLUSH(hw);
1635 /* Ready to switch the queue on */
1636 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1639 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1642 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1649 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1651 struct i40e_rx_queue *rxq;
1654 if (rx_queue_id < dev->data->nb_rx_queues) {
1655 rxq = dev->data->rx_queues[rx_queue_id];
1657 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1660 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1665 i40e_rx_queue_release_mbufs(rxq);
1666 i40e_reset_rx_queue(rxq);
1667 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1674 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1678 PMD_INIT_FUNC_TRACE();
1680 if (tx_queue_id < dev->data->nb_tx_queues) {
1682 /* Ready to switch the queue on */
1683 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1686 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1689 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1696 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1698 struct i40e_tx_queue *txq;
1701 if (tx_queue_id < dev->data->nb_tx_queues) {
1702 txq = dev->data->tx_queues[tx_queue_id];
1704 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1707 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1712 i40e_tx_queue_release_mbufs(txq);
1713 i40e_reset_tx_queue(txq);
1714 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1721 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1726 ret = i40evf_add_vlan(dev, vlan_id);
1728 ret = i40evf_del_vlan(dev,vlan_id);
1734 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1736 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737 struct rte_eth_dev_data *dev_data = dev->data;
1738 struct rte_pktmbuf_pool_private *mbp_priv;
1739 uint16_t buf_size, len;
1741 rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1742 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1743 I40EVF_WRITE_FLUSH(hw);
1745 /* Calculate the maximum packet length allowed */
1746 mbp_priv = rte_mempool_get_priv(rxq->mp);
1747 buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1748 RTE_PKTMBUF_HEADROOM);
1749 rxq->hs_mode = i40e_header_split_none;
1750 rxq->rx_hdr_len = 0;
1751 rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1752 len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1753 rxq->max_pkt_len = RTE_MIN(len,
1754 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1757 * Check if the jumbo frame and maximum packet length are set correctly
1759 if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1760 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1761 rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1762 PMD_DRV_LOG(ERR, "maximum packet length must be "
1763 "larger than %u and smaller than %u, as jumbo "
1764 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1765 (uint32_t)I40E_FRAME_SIZE_MAX);
1766 return I40E_ERR_CONFIG;
1769 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1770 rxq->max_pkt_len > ETHER_MAX_LEN) {
1771 PMD_DRV_LOG(ERR, "maximum packet length must be "
1772 "larger than %u and smaller than %u, as jumbo "
1773 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1774 (uint32_t)ETHER_MAX_LEN);
1775 return I40E_ERR_CONFIG;
1779 if (dev_data->dev_conf.rxmode.enable_scatter ||
1780 (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1781 dev_data->scattered_rx = 1;
1788 i40evf_rx_init(struct rte_eth_dev *dev)
1790 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1792 int ret = I40E_SUCCESS;
1793 struct i40e_rx_queue **rxq =
1794 (struct i40e_rx_queue **)dev->data->rx_queues;
1796 i40evf_config_rss(vf);
1797 for (i = 0; i < dev->data->nb_rx_queues; i++) {
1798 if (!rxq[i] || !rxq[i]->q_set)
1800 ret = i40evf_rxq_init(dev, rxq[i]);
1801 if (ret != I40E_SUCCESS)
1804 if (ret == I40E_SUCCESS)
1805 i40e_set_rx_function(dev);
1811 i40evf_tx_init(struct rte_eth_dev *dev)
1814 struct i40e_tx_queue **txq =
1815 (struct i40e_tx_queue **)dev->data->tx_queues;
1816 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1818 for (i = 0; i < dev->data->nb_tx_queues; i++)
1819 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1821 i40e_set_tx_function(dev);
1825 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1827 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1829 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1831 if (!rte_intr_allow_others(intr_handle)) {
1833 I40E_VFINT_DYN_CTL01,
1834 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1835 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1836 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1837 I40EVF_WRITE_FLUSH(hw);
1841 I40EVF_WRITE_FLUSH(hw);
1845 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1847 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1849 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1851 if (!rte_intr_allow_others(intr_handle)) {
1852 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1853 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1854 I40EVF_WRITE_FLUSH(hw);
1858 I40EVF_WRITE_FLUSH(hw);
1862 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1864 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1865 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1866 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1868 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1871 msix_intr = intr_handle->intr_vec[queue_id];
1872 if (msix_intr == I40E_MISC_VEC_ID)
1873 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1874 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1875 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1876 (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1878 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1881 I40E_VFINT_DYN_CTLN1(msix_intr -
1883 I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1884 I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1885 (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1887 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1889 I40EVF_WRITE_FLUSH(hw);
1891 rte_intr_enable(&pci_dev->intr_handle);
1897 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1899 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1900 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1901 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1904 msix_intr = intr_handle->intr_vec[queue_id];
1905 if (msix_intr == I40E_MISC_VEC_ID)
1906 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1909 I40E_VFINT_DYN_CTLN1(msix_intr -
1913 I40EVF_WRITE_FLUSH(hw);
1919 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1921 struct virtchnl_ether_addr_list *list;
1922 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1927 struct ether_addr *addr;
1928 struct vf_cmd_info args;
1932 len = sizeof(struct virtchnl_ether_addr_list);
1933 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1934 if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1936 len += sizeof(struct virtchnl_ether_addr);
1937 if (len >= I40E_AQ_BUF_SZ) {
1943 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1945 PMD_DRV_LOG(ERR, "fail to allocate memory");
1949 for (i = begin; i < next_begin; i++) {
1950 addr = &dev->data->mac_addrs[i];
1951 if (is_zero_ether_addr(addr))
1953 rte_memcpy(list->list[j].addr, addr->addr_bytes,
1954 sizeof(addr->addr_bytes));
1955 PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1956 addr->addr_bytes[0], addr->addr_bytes[1],
1957 addr->addr_bytes[2], addr->addr_bytes[3],
1958 addr->addr_bytes[4], addr->addr_bytes[5]);
1961 list->vsi_id = vf->vsi_res->vsi_id;
1962 list->num_elements = j;
1963 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1964 VIRTCHNL_OP_DEL_ETH_ADDR;
1965 args.in_args = (uint8_t *)list;
1966 args.in_args_size = len;
1967 args.out_buffer = vf->aq_resp;
1968 args.out_size = I40E_AQ_BUF_SZ;
1969 err = i40evf_execute_vf_cmd(dev, &args);
1971 PMD_DRV_LOG(ERR, "fail to execute command %s",
1972 add ? "OP_ADD_ETHER_ADDRESS" :
1973 "OP_DEL_ETHER_ADDRESS");
1982 } while (begin < I40E_NUM_MACADDR_MAX);
1986 i40evf_dev_start(struct rte_eth_dev *dev)
1988 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1989 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1991 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1992 uint32_t intr_vector = 0;
1994 PMD_INIT_FUNC_TRACE();
1996 hw->adapter_stopped = 0;
1998 vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1999 vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2000 dev->data->nb_tx_queues);
2002 /* check and configure queue intr-vector mapping */
2003 if (dev->data->dev_conf.intr_conf.rxq != 0) {
2004 intr_vector = dev->data->nb_rx_queues;
2005 if (rte_intr_efd_enable(intr_handle, intr_vector))
2009 if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2010 intr_handle->intr_vec =
2011 rte_zmalloc("intr_vec",
2012 dev->data->nb_rx_queues * sizeof(int), 0);
2013 if (!intr_handle->intr_vec) {
2014 PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2015 " intr_vec", dev->data->nb_rx_queues);
2020 if (i40evf_rx_init(dev) != 0){
2021 PMD_DRV_LOG(ERR, "failed to do RX init");
2025 i40evf_tx_init(dev);
2027 if (i40evf_configure_vsi_queues(dev) != 0) {
2028 PMD_DRV_LOG(ERR, "configure queues failed");
2031 if (i40evf_config_irq_map(dev)) {
2032 PMD_DRV_LOG(ERR, "config_irq_map failed");
2036 /* Set all mac addrs */
2037 i40evf_add_del_all_mac_addr(dev, TRUE);
2039 if (i40evf_start_queues(dev) != 0) {
2040 PMD_DRV_LOG(ERR, "enable queues failed");
2044 i40evf_enable_queues_intr(dev);
2048 i40evf_add_del_all_mac_addr(dev, FALSE);
2054 i40evf_dev_stop(struct rte_eth_dev *dev)
2056 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2060 PMD_INIT_FUNC_TRACE();
2062 if (hw->adapter_stopped == 1)
2064 i40evf_stop_queues(dev);
2065 i40evf_disable_queues_intr(dev);
2066 i40e_dev_clear_queues(dev);
2068 /* Clean datapath event and queue/vec mapping */
2069 rte_intr_efd_disable(intr_handle);
2070 if (intr_handle->intr_vec) {
2071 rte_free(intr_handle->intr_vec);
2072 intr_handle->intr_vec = NULL;
2074 /* remove all mac addrs */
2075 i40evf_add_del_all_mac_addr(dev, FALSE);
2076 hw->adapter_stopped = 1;
2081 i40evf_dev_link_update(struct rte_eth_dev *dev,
2082 __rte_unused int wait_to_complete)
2084 struct rte_eth_link new_link;
2085 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2087 * DPDK pf host provide interfacet to acquire link status
2088 * while Linux driver does not
2091 /* Linux driver PF host */
2092 switch (vf->link_speed) {
2093 case I40E_LINK_SPEED_100MB:
2094 new_link.link_speed = ETH_SPEED_NUM_100M;
2096 case I40E_LINK_SPEED_1GB:
2097 new_link.link_speed = ETH_SPEED_NUM_1G;
2099 case I40E_LINK_SPEED_10GB:
2100 new_link.link_speed = ETH_SPEED_NUM_10G;
2102 case I40E_LINK_SPEED_20GB:
2103 new_link.link_speed = ETH_SPEED_NUM_20G;
2105 case I40E_LINK_SPEED_25GB:
2106 new_link.link_speed = ETH_SPEED_NUM_25G;
2108 case I40E_LINK_SPEED_40GB:
2109 new_link.link_speed = ETH_SPEED_NUM_40G;
2112 new_link.link_speed = ETH_SPEED_NUM_100M;
2115 /* full duplex only */
2116 new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2117 new_link.link_status = vf->link_up ? ETH_LINK_UP :
2119 new_link.link_autoneg =
2120 dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED;
2122 i40evf_dev_atomic_write_link_status(dev, &new_link);
2128 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2130 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2133 /* If enabled, just return */
2134 if (vf->promisc_unicast_enabled)
2137 ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2139 vf->promisc_unicast_enabled = TRUE;
2143 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2145 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2148 /* If disabled, just return */
2149 if (!vf->promisc_unicast_enabled)
2152 ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2154 vf->promisc_unicast_enabled = FALSE;
2158 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2160 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2163 /* If enabled, just return */
2164 if (vf->promisc_multicast_enabled)
2167 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2169 vf->promisc_multicast_enabled = TRUE;
2173 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2175 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2178 /* If enabled, just return */
2179 if (!vf->promisc_multicast_enabled)
2182 ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2184 vf->promisc_multicast_enabled = FALSE;
2188 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2190 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2192 memset(dev_info, 0, sizeof(*dev_info));
2193 dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2194 dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2195 dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2196 dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2197 dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2198 dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2199 dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2200 dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2201 dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2202 dev_info->rx_offload_capa =
2203 DEV_RX_OFFLOAD_VLAN_STRIP |
2204 DEV_RX_OFFLOAD_QINQ_STRIP |
2205 DEV_RX_OFFLOAD_IPV4_CKSUM |
2206 DEV_RX_OFFLOAD_UDP_CKSUM |
2207 DEV_RX_OFFLOAD_TCP_CKSUM;
2208 dev_info->tx_offload_capa =
2209 DEV_TX_OFFLOAD_VLAN_INSERT |
2210 DEV_TX_OFFLOAD_QINQ_INSERT |
2211 DEV_TX_OFFLOAD_IPV4_CKSUM |
2212 DEV_TX_OFFLOAD_UDP_CKSUM |
2213 DEV_TX_OFFLOAD_TCP_CKSUM |
2214 DEV_TX_OFFLOAD_SCTP_CKSUM;
2216 dev_info->default_rxconf = (struct rte_eth_rxconf) {
2218 .pthresh = I40E_DEFAULT_RX_PTHRESH,
2219 .hthresh = I40E_DEFAULT_RX_HTHRESH,
2220 .wthresh = I40E_DEFAULT_RX_WTHRESH,
2222 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2226 dev_info->default_txconf = (struct rte_eth_txconf) {
2228 .pthresh = I40E_DEFAULT_TX_PTHRESH,
2229 .hthresh = I40E_DEFAULT_TX_HTHRESH,
2230 .wthresh = I40E_DEFAULT_TX_WTHRESH,
2232 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2233 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2234 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2235 ETH_TXQ_FLAGS_NOOFFLOADS,
2238 dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2239 .nb_max = I40E_MAX_RING_DESC,
2240 .nb_min = I40E_MIN_RING_DESC,
2241 .nb_align = I40E_ALIGN_RING_DESC,
2244 dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2245 .nb_max = I40E_MAX_RING_DESC,
2246 .nb_min = I40E_MIN_RING_DESC,
2247 .nb_align = I40E_ALIGN_RING_DESC,
2252 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2255 struct i40e_eth_stats *pstats = NULL;
2256 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2257 struct i40e_vsi *vsi = &vf->vsi;
2259 ret = i40evf_query_stats(dev, &pstats);
2261 i40evf_update_stats(vsi, pstats);
2263 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2264 pstats->rx_broadcast;
2265 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2267 stats->imissed = pstats->rx_discards;
2268 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2269 stats->ibytes = pstats->rx_bytes;
2270 stats->obytes = pstats->tx_bytes;
2272 PMD_DRV_LOG(ERR, "Get statistics failed");
2278 i40evf_dev_close(struct rte_eth_dev *dev)
2280 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2281 struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2282 struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2284 i40evf_dev_stop(dev);
2285 i40e_dev_free_queues(dev);
2286 i40evf_reset_vf(hw);
2287 i40e_shutdown_adminq(hw);
2288 /* disable uio intr before callback unregister */
2289 rte_intr_disable(intr_handle);
2291 /* unregister callback func from eal lib */
2292 rte_intr_callback_unregister(intr_handle,
2293 i40evf_dev_interrupt_handler, dev);
2294 i40evf_disable_irq0(hw);
2298 * Reset VF device only to re-initialize resources in PMD layer
2301 i40evf_dev_reset(struct rte_eth_dev *dev)
2305 ret = i40evf_dev_uninit(dev);
2309 ret = i40evf_dev_init(dev);
2315 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2317 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2318 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2324 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2325 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2328 PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2332 uint32_t *lut_dw = (uint32_t *)lut;
2333 uint16_t i, lut_size_dw = lut_size / 4;
2335 for (i = 0; i < lut_size_dw; i++)
2336 lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2343 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2352 vf = I40E_VSI_TO_VF(vsi);
2353 hw = I40E_VSI_TO_HW(vsi);
2355 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2356 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2359 PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2363 uint32_t *lut_dw = (uint32_t *)lut;
2364 uint16_t i, lut_size_dw = lut_size / 4;
2366 for (i = 0; i < lut_size_dw; i++)
2367 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2368 I40EVF_WRITE_FLUSH(hw);
2375 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2376 struct rte_eth_rss_reta_entry64 *reta_conf,
2379 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2381 uint16_t i, idx, shift;
2384 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2385 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2386 "(%d) doesn't match the number of hardware can "
2387 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2391 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2393 PMD_DRV_LOG(ERR, "No memory can be allocated");
2396 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2399 for (i = 0; i < reta_size; i++) {
2400 idx = i / RTE_RETA_GROUP_SIZE;
2401 shift = i % RTE_RETA_GROUP_SIZE;
2402 if (reta_conf[idx].mask & (1ULL << shift))
2403 lut[i] = reta_conf[idx].reta[shift];
2405 ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2414 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2415 struct rte_eth_rss_reta_entry64 *reta_conf,
2418 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2419 uint16_t i, idx, shift;
2423 if (reta_size != ETH_RSS_RETA_SIZE_64) {
2424 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2425 "(%d) doesn't match the number of hardware can "
2426 "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2430 lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2432 PMD_DRV_LOG(ERR, "No memory can be allocated");
2436 ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2439 for (i = 0; i < reta_size; i++) {
2440 idx = i / RTE_RETA_GROUP_SIZE;
2441 shift = i % RTE_RETA_GROUP_SIZE;
2442 if (reta_conf[idx].mask & (1ULL << shift))
2443 reta_conf[idx].reta[shift] = lut[i];
2453 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2455 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2456 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2459 if (!key || key_len == 0) {
2460 PMD_DRV_LOG(DEBUG, "No key to be configured");
2462 } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2464 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2468 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2469 struct i40e_aqc_get_set_rss_key_data *key_dw =
2470 (struct i40e_aqc_get_set_rss_key_data *)key;
2472 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2474 PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2477 uint32_t *hash_key = (uint32_t *)key;
2480 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2481 i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2482 I40EVF_WRITE_FLUSH(hw);
2489 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2491 struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2492 struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2495 if (!key || !key_len)
2498 if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2499 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2500 (struct i40e_aqc_get_set_rss_key_data *)key);
2502 PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2506 uint32_t *key_dw = (uint32_t *)key;
2509 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2510 key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2512 *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2518 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2520 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2524 ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2525 rss_conf->rss_key_len);
2529 hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2530 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2531 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2532 I40EVF_WRITE_FLUSH(hw);
2538 i40evf_disable_rss(struct i40e_vf *vf)
2540 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2542 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2543 i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2544 I40EVF_WRITE_FLUSH(hw);
2548 i40evf_config_rss(struct i40e_vf *vf)
2550 struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2551 struct rte_eth_rss_conf rss_conf;
2552 uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2555 if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2556 i40evf_disable_rss(vf);
2557 PMD_DRV_LOG(DEBUG, "RSS not configured");
2561 num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2562 /* Fill out the look up table */
2563 for (i = 0, j = 0; i < nb_q; i++, j++) {
2566 lut = (lut << 8) | j;
2568 I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2571 rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2572 if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2573 i40evf_disable_rss(vf);
2574 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2578 if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2579 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2580 /* Calculate the default hash key */
2581 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2582 rss_key_default[i] = (uint32_t)rte_rand();
2583 rss_conf.rss_key = (uint8_t *)rss_key_default;
2584 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2588 return i40evf_hw_rss_hash_set(vf, &rss_conf);
2592 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2593 struct rte_eth_rss_conf *rss_conf)
2595 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2596 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2597 uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2600 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2601 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2603 if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2604 if (rss_hf != 0) /* Enable RSS */
2610 if (rss_hf == 0) /* Disable RSS */
2613 return i40evf_hw_rss_hash_set(vf, rss_conf);
2617 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2618 struct rte_eth_rss_conf *rss_conf)
2620 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2621 struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2624 i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2625 &rss_conf->rss_key_len);
2627 hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2628 hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2629 rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2635 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2637 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2638 struct rte_eth_dev_data *dev_data = vf->dev_data;
2639 uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2642 /* check if mtu is within the allowed range */
2643 if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2646 /* mtu setting is forbidden if port is start */
2647 if (dev_data->dev_started) {
2648 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2653 if (frame_size > ETHER_MAX_LEN)
2654 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2656 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2658 dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2664 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2665 struct ether_addr *mac_addr)
2667 struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2669 if (!is_valid_assigned_ether_addr(mac_addr)) {
2670 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2674 if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2677 if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2680 i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2682 i40evf_add_mac_addr(dev, mac_addr, 0, 0);