drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_bus_pci.h>
  51 #include <rte_atomic.h>
  52 #include <rte_branch_prediction.h>
  53 #include <rte_memory.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70
  71 /* busy wait delay in msec */
  72 #define I40EVF_BUSY_WAIT_DELAY 10
  73 #define I40EVF_BUSY_WAIT_COUNT 50
  74 #define MAX_RESET_WAIT_CNT     20
  75
  76 struct i40evf_arq_msg_info {
  77         enum virtchnl_ops ops;
  78         enum i40e_status_code result;
  79         uint16_t buf_len;
  80         uint16_t msg_len;
  81         uint8_t *msg;
  82 };
  83
  84 struct vf_cmd_info {
  85         enum virtchnl_ops ops;
  86         uint8_t *in_args;
  87         uint32_t in_args_size;
  88         uint8_t *out_buffer;
  89         /* Input & output type. pass in buffer size and pass out
  90          * actual return result
  91          */
  92         uint32_t out_size;
  93 };
  94
  95 enum i40evf_aq_result {
  96         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  97         I40EVF_MSG_NON,      /* Read nothing from admin queue */
  98         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
  99         I40EVF_MSG_CMD,      /* Read async command result */
 100 };
 101
 102 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 103 static int i40evf_dev_start(struct rte_eth_dev *dev);
 104 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 105 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 106                                 struct rte_eth_dev_info *dev_info);
 107 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 108                                   int wait_to_complete);
 109 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
 110                                 struct rte_eth_stats *stats);
 111 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 112                                  struct rte_eth_xstat *xstats, unsigned n);
 113 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 114                                        struct rte_eth_xstat_name *xstats_names,
 115                                        unsigned limit);
 116 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 117 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 118                                   uint16_t vlan_id, int on);
 119 static int i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 120 static void i40evf_dev_close(struct rte_eth_dev *dev);
 121 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 122 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 123 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 124 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 126 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 127 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 128                                      uint16_t rx_queue_id);
 129 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 130                                     uint16_t rx_queue_id);
 131 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 132                                      uint16_t tx_queue_id);
 133 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 134                                     uint16_t tx_queue_id);
 135 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 136                                struct ether_addr *addr,
 137                                uint32_t index,
 138                                uint32_t pool);
 139 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 140 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 141                         struct rte_eth_rss_reta_entry64 *reta_conf,
 142                         uint16_t reta_size);
 143 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 144                         struct rte_eth_rss_reta_entry64 *reta_conf,
 145                         uint16_t reta_size);
 146 static int i40evf_config_rss(struct i40e_vf *vf);
 147 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 148                                       struct rte_eth_rss_conf *rss_conf);
 149 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 150                                         struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 152 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 153                                         struct ether_addr *mac_addr);
 154 static int
 155 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 156 static int
 157 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 159                                    uint8_t *msg,
 160                                    uint16_t msglen);
 161
 162 /* Default hash key buffer for RSS */
 163 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 164
 165 struct rte_i40evf_xstats_name_off {
 166         char name[RTE_ETH_XSTATS_NAME_SIZE];
 167         unsigned offset;
 168 };
 169
 170 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 171         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 172         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 179         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 180         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 181         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 182         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 183         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 184 };
 185
 186 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 187                 sizeof(rte_i40evf_stats_strings[0]))
 188
 189 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 190         .dev_configure        = i40evf_dev_configure,
 191         .dev_start            = i40evf_dev_start,
 192         .dev_stop             = i40evf_dev_stop,
 193         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 194         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 195         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 196         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 197         .link_update          = i40evf_dev_link_update,
 198         .stats_get            = i40evf_dev_stats_get,
 199         .stats_reset          = i40evf_dev_xstats_reset,
 200         .xstats_get           = i40evf_dev_xstats_get,
 201         .xstats_get_names     = i40evf_dev_xstats_get_names,
 202         .xstats_reset         = i40evf_dev_xstats_reset,
 203         .dev_close            = i40evf_dev_close,
 204         .dev_reset            = i40evf_dev_reset,
 205         .dev_infos_get        = i40evf_dev_info_get,
 206         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 207         .vlan_filter_set      = i40evf_vlan_filter_set,
 208         .vlan_offload_set     = i40evf_vlan_offload_set,
 209         .rx_queue_start       = i40evf_dev_rx_queue_start,
 210         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 211         .tx_queue_start       = i40evf_dev_tx_queue_start,
 212         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 213         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 214         .rx_queue_release     = i40e_dev_rx_queue_release,
 215         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 216         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 217         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 218         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 219         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 220         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 221         .tx_queue_release     = i40e_dev_tx_queue_release,
 222         .rx_queue_count       = i40e_dev_rx_queue_count,
 223         .rxq_info_get         = i40e_rxq_info_get,
 224         .txq_info_get         = i40e_txq_info_get,
 225         .mac_addr_add         = i40evf_add_mac_addr,
 226         .mac_addr_remove      = i40evf_del_mac_addr,
 227         .reta_update          = i40evf_dev_rss_reta_update,
 228         .reta_query           = i40evf_dev_rss_reta_query,
 229         .rss_hash_update      = i40evf_dev_rss_hash_update,
 230         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 231         .mtu_set              = i40evf_dev_mtu_set,
 232         .mac_addr_set         = i40evf_set_default_mac_addr,
 233 };
 234
 235 /*
 236  * Read data in admin queue to get msg from pf driver
 237  */
 238 static enum i40evf_aq_result
 239 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 240 {
 241         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 242         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 243         struct i40e_arq_event_info event;
 244         enum virtchnl_ops opcode;
 245         enum i40e_status_code retval;
 246         int ret;
 247         enum i40evf_aq_result result = I40EVF_MSG_NON;
 248
 249         event.buf_len = data->buf_len;
 250         event.msg_buf = data->msg;
 251         ret = i40e_clean_arq_element(hw, &event, NULL);
 252         /* Can't read any msg from adminQ */
 253         if (ret) {
 254                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 255                         result = I40EVF_MSG_ERR;
 256                 return result;
 257         }
 258
 259         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 260         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 261         /* pf sys event */
 262         if (opcode == VIRTCHNL_OP_EVENT) {
 263                 struct virtchnl_pf_event *vpe =
 264                         (struct virtchnl_pf_event *)event.msg_buf;
 265
 266                 result = I40EVF_MSG_SYS;
 267                 switch (vpe->event) {
 268                 case VIRTCHNL_EVENT_LINK_CHANGE:
 269                         vf->link_up =
 270                                 vpe->event_data.link_event.link_status;
 271                         vf->link_speed =
 272                                 vpe->event_data.link_event.link_speed;
 273                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 274                         PMD_DRV_LOG(INFO, "Link status update:%s",
 275                                     vf->link_up ? "up" : "down");
 276                         break;
 277                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 278                         vf->vf_reset = true;
 279                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 280                         PMD_DRV_LOG(INFO, "vf is reseting");
 281                         break;
 282                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 283                         vf->dev_closed = true;
 284                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 285                         PMD_DRV_LOG(INFO, "PF driver closed");
 286                         break;
 287                 default:
 288                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 289                                     __func__, vpe->event);
 290                 }
 291         } else {
 292                 /* async reply msg on command issued by vf previously */
 293                 result = I40EVF_MSG_CMD;
 294                 /* Actual data length read from PF */
 295                 data->msg_len = event.msg_len;
 296         }
 297
 298         data->result = retval;
 299         data->ops = opcode;
 300
 301         return result;
 302 }
 303
 304 /**
 305  * clear current command. Only call in case execute
 306  * _atomic_set_cmd successfully.
 307  */
 308 static inline void
 309 _clear_cmd(struct i40e_vf *vf)
 310 {
 311         rte_wmb();
 312         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 313 }
 314
 315 /*
 316  * Check there is pending cmd in execution. If none, set new command.
 317  */
 318 static inline int
 319 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 320 {
 321         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 322                         VIRTCHNL_OP_UNKNOWN, ops);
 323
 324         if (!ret)
 325                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 326
 327         return !ret;
 328 }
 329
 330 #define MAX_TRY_TIMES 200
 331 #define ASQ_DELAY_MS  10
 332
 333 static int
 334 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 335 {
 336         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 337         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 338         struct i40evf_arq_msg_info info;
 339         enum i40evf_aq_result ret;
 340         int err, i = 0;
 341
 342         if (_atomic_set_cmd(vf, args->ops))
 343                 return -1;
 344
 345         info.msg = args->out_buffer;
 346         info.buf_len = args->out_size;
 347         info.ops = VIRTCHNL_OP_UNKNOWN;
 348         info.result = I40E_SUCCESS;
 349
 350         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 351                      args->in_args, args->in_args_size, NULL);
 352         if (err) {
 353                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 354                 _clear_cmd(vf);
 355                 return err;
 356         }
 357
 358         switch (args->ops) {
 359         case VIRTCHNL_OP_RESET_VF:
 360                 /*no need to process in this function */
 361                 err = 0;
 362                 break;
 363         case VIRTCHNL_OP_VERSION:
 364         case VIRTCHNL_OP_GET_VF_RESOURCES:
 365                 /* for init adminq commands, need to poll the response */
 366                 err = -1;
 367                 do {
 368                         ret = i40evf_read_pfmsg(dev, &info);
 369                         vf->cmd_retval = info.result;
 370                         if (ret == I40EVF_MSG_CMD) {
 371                                 err = 0;
 372                                 break;
 373                         } else if (ret == I40EVF_MSG_ERR)
 374                                 break;
 375                         rte_delay_ms(ASQ_DELAY_MS);
 376                         /* If don't read msg or read sys event, continue */
 377                 } while (i++ < MAX_TRY_TIMES);
 378                 _clear_cmd(vf);
 379                 break;
 380
 381         default:
 382                 /* for other adminq in running time, waiting the cmd done flag */
 383                 err = -1;
 384                 do {
 385                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 386                                 err = 0;
 387                                 break;
 388                         }
 389                         rte_delay_ms(ASQ_DELAY_MS);
 390                         /* If don't read msg or read sys event, continue */
 391                 } while (i++ < MAX_TRY_TIMES);
 392                 /* If there's no response is received, clear command */
 393                 if (i >= MAX_TRY_TIMES) {
 394                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 395                         _clear_cmd(vf);
 396                 }
 397                 break;
 398         }
 399
 400         return err | vf->cmd_retval;
 401 }
 402
 403 /*
 404  * Check API version with sync wait until version read or fail from admin queue
 405  */
 406 static int
 407 i40evf_check_api_version(struct rte_eth_dev *dev)
 408 {
 409         struct virtchnl_version_info version, *pver;
 410         int err;
 411         struct vf_cmd_info args;
 412         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 413
 414         version.major = VIRTCHNL_VERSION_MAJOR;
 415         version.minor = VIRTCHNL_VERSION_MINOR;
 416
 417         args.ops = VIRTCHNL_OP_VERSION;
 418         args.in_args = (uint8_t *)&version;
 419         args.in_args_size = sizeof(version);
 420         args.out_buffer = vf->aq_resp;
 421         args.out_size = I40E_AQ_BUF_SZ;
 422
 423         err = i40evf_execute_vf_cmd(dev, &args);
 424         if (err) {
 425                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 426                 return err;
 427         }
 428
 429         pver = (struct virtchnl_version_info *)args.out_buffer;
 430         vf->version_major = pver->major;
 431         vf->version_minor = pver->minor;
 432         if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 433                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 434                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 435         else {
 436                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 437                                         vf->version_major, vf->version_minor,
 438                                                 VIRTCHNL_VERSION_MAJOR,
 439                                                 VIRTCHNL_VERSION_MINOR);
 440                 return -1;
 441         }
 442
 443         return 0;
 444 }
 445
 446 static int
 447 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 448 {
 449         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 450         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 451         int err;
 452         struct vf_cmd_info args;
 453         uint32_t caps, len;
 454
 455         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 456         args.out_buffer = vf->aq_resp;
 457         args.out_size = I40E_AQ_BUF_SZ;
 458         if (PF_IS_V11(vf)) {
 459                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 460                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 461                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 462                        VIRTCHNL_VF_OFFLOAD_VLAN |
 463                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 464                 args.in_args = (uint8_t *)&caps;
 465                 args.in_args_size = sizeof(caps);
 466         } else {
 467                 args.in_args = NULL;
 468                 args.in_args_size = 0;
 469         }
 470         err = i40evf_execute_vf_cmd(dev, &args);
 471
 472         if (err) {
 473                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 474                 return err;
 475         }
 476
 477         len =  sizeof(struct virtchnl_vf_resource) +
 478                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 479
 480         rte_memcpy(vf->vf_res, args.out_buffer,
 481                         RTE_MIN(args.out_size, len));
 482         i40e_vf_parse_hw_config(hw, vf->vf_res);
 483
 484         return 0;
 485 }
 486
 487 static int
 488 i40evf_config_promisc(struct rte_eth_dev *dev,
 489                       bool enable_unicast,
 490                       bool enable_multicast)
 491 {
 492         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 493         int err;
 494         struct vf_cmd_info args;
 495         struct virtchnl_promisc_info promisc;
 496
 497         promisc.flags = 0;
 498         promisc.vsi_id = vf->vsi_res->vsi_id;
 499
 500         if (enable_unicast)
 501                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 502
 503         if (enable_multicast)
 504                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 505
 506         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 507         args.in_args = (uint8_t *)&promisc;
 508         args.in_args_size = sizeof(promisc);
 509         args.out_buffer = vf->aq_resp;
 510         args.out_size = I40E_AQ_BUF_SZ;
 511
 512         err = i40evf_execute_vf_cmd(dev, &args);
 513
 514         if (err)
 515                 PMD_DRV_LOG(ERR, "fail to execute command "
 516                             "CONFIG_PROMISCUOUS_MODE");
 517         return err;
 518 }
 519
 520 static int
 521 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 522 {
 523         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 524         struct vf_cmd_info args;
 525         int ret;
 526
 527         memset(&args, 0, sizeof(args));
 528         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 529         args.in_args = NULL;
 530         args.in_args_size = 0;
 531         args.out_buffer = vf->aq_resp;
 532         args.out_size = I40E_AQ_BUF_SZ;
 533         ret = i40evf_execute_vf_cmd(dev, &args);
 534         if (ret)
 535                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 536                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 537
 538         return ret;
 539 }
 540
 541 static int
 542 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 543 {
 544         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 545         struct vf_cmd_info args;
 546         int ret;
 547
 548         memset(&args, 0, sizeof(args));
 549         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 550         args.in_args = NULL;
 551         args.in_args_size = 0;
 552         args.out_buffer = vf->aq_resp;
 553         args.out_size = I40E_AQ_BUF_SZ;
 554         ret = i40evf_execute_vf_cmd(dev, &args);
 555         if (ret)
 556                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 557                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 558
 559         return ret;
 560 }
 561
 562 static void
 563 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 564                                   uint16_t vsi_id,
 565                                   uint16_t queue_id,
 566                                   uint16_t nb_txq,
 567                                   struct i40e_tx_queue *txq)
 568 {
 569         txq_info->vsi_id = vsi_id;
 570         txq_info->queue_id = queue_id;
 571         if (queue_id < nb_txq) {
 572                 txq_info->ring_len = txq->nb_tx_desc;
 573                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 574         }
 575 }
 576
 577 static void
 578 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 579                                   uint16_t vsi_id,
 580                                   uint16_t queue_id,
 581                                   uint16_t nb_rxq,
 582                                   uint32_t max_pkt_size,
 583                                   struct i40e_rx_queue *rxq)
 584 {
 585         rxq_info->vsi_id = vsi_id;
 586         rxq_info->queue_id = queue_id;
 587         rxq_info->max_pkt_size = max_pkt_size;
 588         if (queue_id < nb_rxq) {
 589                 rxq_info->ring_len = rxq->nb_rx_desc;
 590                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 591                 rxq_info->databuffer_size =
 592                         (rte_pktmbuf_data_room_size(rxq->mp) -
 593                                 RTE_PKTMBUF_HEADROOM);
 594         }
 595 }
 596
 597 static int
 598 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 599 {
 600         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 601         struct i40e_rx_queue **rxq =
 602                 (struct i40e_rx_queue **)dev->data->rx_queues;
 603         struct i40e_tx_queue **txq =
 604                 (struct i40e_tx_queue **)dev->data->tx_queues;
 605         struct virtchnl_vsi_queue_config_info *vc_vqci;
 606         struct virtchnl_queue_pair_info *vc_qpi;
 607         struct vf_cmd_info args;
 608         uint16_t i, nb_qp = vf->num_queue_pairs;
 609         const uint32_t size =
 610                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 611         uint8_t buff[size];
 612         int ret;
 613
 614         memset(buff, 0, sizeof(buff));
 615         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 616         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 617         vc_vqci->num_queue_pairs = nb_qp;
 618
 619         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 620                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 621                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 622                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 623                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 624                                         vf->max_pkt_len, rxq[i]);
 625         }
 626         memset(&args, 0, sizeof(args));
 627         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 628         args.in_args = (uint8_t *)vc_vqci;
 629         args.in_args_size = size;
 630         args.out_buffer = vf->aq_resp;
 631         args.out_size = I40E_AQ_BUF_SZ;
 632         ret = i40evf_execute_vf_cmd(dev, &args);
 633         if (ret)
 634                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 635                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 636
 637         return ret;
 638 }
 639
 640 static int
 641 i40evf_config_irq_map(struct rte_eth_dev *dev)
 642 {
 643         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 644         struct vf_cmd_info args;
 645         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 646                 sizeof(struct virtchnl_vector_map)];
 647         struct virtchnl_irq_map_info *map_info;
 648         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 649         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 650         uint32_t vector_id;
 651         int i, err;
 652
 653         if (dev->data->dev_conf.intr_conf.rxq != 0 &&
 654             rte_intr_allow_others(intr_handle))
 655                 vector_id = I40E_RX_VEC_START;
 656         else
 657                 vector_id = I40E_MISC_VEC_ID;
 658
 659         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 660         map_info->num_vectors = 1;
 661         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 662         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 663         /* Alway use default dynamic MSIX interrupt */
 664         map_info->vecmap[0].vector_id = vector_id;
 665         /* Don't map any tx queue */
 666         map_info->vecmap[0].txq_map = 0;
 667         map_info->vecmap[0].rxq_map = 0;
 668         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 669                 map_info->vecmap[0].rxq_map |= 1 << i;
 670                 if (rte_intr_dp_is_en(intr_handle))
 671                         intr_handle->intr_vec[i] = vector_id;
 672         }
 673
 674         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 675         args.in_args = (u8 *)cmd_buffer;
 676         args.in_args_size = sizeof(cmd_buffer);
 677         args.out_buffer = vf->aq_resp;
 678         args.out_size = I40E_AQ_BUF_SZ;
 679         err = i40evf_execute_vf_cmd(dev, &args);
 680         if (err)
 681                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 682
 683         return err;
 684 }
 685
 686 static int
 687 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 688                                 bool on)
 689 {
 690         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 691         struct virtchnl_queue_select queue_select;
 692         int err;
 693         struct vf_cmd_info args;
 694         memset(&queue_select, 0, sizeof(queue_select));
 695         queue_select.vsi_id = vf->vsi_res->vsi_id;
 696
 697         if (isrx)
 698                 queue_select.rx_queues |= 1 << qid;
 699         else
 700                 queue_select.tx_queues |= 1 << qid;
 701
 702         if (on)
 703                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 704         else
 705                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 706         args.in_args = (u8 *)&queue_select;
 707         args.in_args_size = sizeof(queue_select);
 708         args.out_buffer = vf->aq_resp;
 709         args.out_size = I40E_AQ_BUF_SZ;
 710         err = i40evf_execute_vf_cmd(dev, &args);
 711         if (err)
 712                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 713                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 714
 715         return err;
 716 }
 717
 718 static int
 719 i40evf_start_queues(struct rte_eth_dev *dev)
 720 {
 721         struct rte_eth_dev_data *dev_data = dev->data;
 722         int i;
 723         struct i40e_rx_queue *rxq;
 724         struct i40e_tx_queue *txq;
 725
 726         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 727                 rxq = dev_data->rx_queues[i];
 728                 if (rxq->rx_deferred_start)
 729                         continue;
 730                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 731                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 732                         return -1;
 733                 }
 734         }
 735
 736         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 737                 txq = dev_data->tx_queues[i];
 738                 if (txq->tx_deferred_start)
 739                         continue;
 740                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 741                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 742                         return -1;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 i40evf_stop_queues(struct rte_eth_dev *dev)
 751 {
 752         int i;
 753
 754         /* Stop TX queues first */
 755         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 756                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 757                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 758                         return -1;
 759                 }
 760         }
 761
 762         /* Then stop RX queues */
 763         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 764                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 765                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 766                         return -1;
 767                 }
 768         }
 769
 770         return 0;
 771 }
 772
 773 static int
 774 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 775                     struct ether_addr *addr,
 776                     __rte_unused uint32_t index,
 777                     __rte_unused uint32_t pool)
 778 {
 779         struct virtchnl_ether_addr_list *list;
 780         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 781         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 782                         sizeof(struct virtchnl_ether_addr)];
 783         int err;
 784         struct vf_cmd_info args;
 785
 786         if (is_zero_ether_addr(addr)) {
 787                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 788                             addr->addr_bytes[0], addr->addr_bytes[1],
 789                             addr->addr_bytes[2], addr->addr_bytes[3],
 790                             addr->addr_bytes[4], addr->addr_bytes[5]);
 791                 return I40E_ERR_INVALID_MAC_ADDR;
 792         }
 793
 794         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 795         list->vsi_id = vf->vsi_res->vsi_id;
 796         list->num_elements = 1;
 797         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 798                                         sizeof(addr->addr_bytes));
 799
 800         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 801         args.in_args = cmd_buffer;
 802         args.in_args_size = sizeof(cmd_buffer);
 803         args.out_buffer = vf->aq_resp;
 804         args.out_size = I40E_AQ_BUF_SZ;
 805         err = i40evf_execute_vf_cmd(dev, &args);
 806         if (err)
 807                 PMD_DRV_LOG(ERR, "fail to execute command "
 808                             "OP_ADD_ETHER_ADDRESS");
 809         else
 810                 vf->vsi.mac_num++;
 811
 812         return err;
 813 }
 814
 815 static void
 816 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 817                             struct ether_addr *addr)
 818 {
 819         struct virtchnl_ether_addr_list *list;
 820         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 821         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 822                         sizeof(struct virtchnl_ether_addr)];
 823         int err;
 824         struct vf_cmd_info args;
 825
 826         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 827                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 828                             addr->addr_bytes[0], addr->addr_bytes[1],
 829                             addr->addr_bytes[2], addr->addr_bytes[3],
 830                             addr->addr_bytes[4], addr->addr_bytes[5]);
 831                 return;
 832         }
 833
 834         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 835         list->vsi_id = vf->vsi_res->vsi_id;
 836         list->num_elements = 1;
 837         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 838                         sizeof(addr->addr_bytes));
 839
 840         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 841         args.in_args = cmd_buffer;
 842         args.in_args_size = sizeof(cmd_buffer);
 843         args.out_buffer = vf->aq_resp;
 844         args.out_size = I40E_AQ_BUF_SZ;
 845         err = i40evf_execute_vf_cmd(dev, &args);
 846         if (err)
 847                 PMD_DRV_LOG(ERR, "fail to execute command "
 848                             "OP_DEL_ETHER_ADDRESS");
 849         else
 850                 vf->vsi.mac_num--;
 851         return;
 852 }
 853
 854 static void
 855 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 856 {
 857         struct rte_eth_dev_data *data = dev->data;
 858         struct ether_addr *addr;
 859
 860         addr = &data->mac_addrs[index];
 861
 862         i40evf_del_mac_addr_by_addr(dev, addr);
 863 }
 864
 865 static int
 866 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 867 {
 868         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 869         struct virtchnl_queue_select q_stats;
 870         int err;
 871         struct vf_cmd_info args;
 872
 873         memset(&q_stats, 0, sizeof(q_stats));
 874         q_stats.vsi_id = vf->vsi_res->vsi_id;
 875         args.ops = VIRTCHNL_OP_GET_STATS;
 876         args.in_args = (u8 *)&q_stats;
 877         args.in_args_size = sizeof(q_stats);
 878         args.out_buffer = vf->aq_resp;
 879         args.out_size = I40E_AQ_BUF_SZ;
 880
 881         err = i40evf_execute_vf_cmd(dev, &args);
 882         if (err) {
 883                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 884                 *pstats = NULL;
 885                 return err;
 886         }
 887         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 888         return 0;
 889 }
 890
 891 static void
 892 i40evf_stat_update_48(uint64_t *offset,
 893                    uint64_t *stat)
 894 {
 895         if (*stat >= *offset)
 896                 *stat = *stat - *offset;
 897         else
 898                 *stat = (uint64_t)((*stat +
 899                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
 900
 901         *stat &= I40E_48_BIT_MASK;
 902 }
 903
 904 static void
 905 i40evf_stat_update_32(uint64_t *offset,
 906                    uint64_t *stat)
 907 {
 908         if (*stat >= *offset)
 909                 *stat = (uint64_t)(*stat - *offset);
 910         else
 911                 *stat = (uint64_t)((*stat +
 912                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
 913 }
 914
 915 static void
 916 i40evf_update_stats(struct i40e_vsi *vsi,
 917                                         struct i40e_eth_stats *nes)
 918 {
 919         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 920
 921         i40evf_stat_update_48(&oes->rx_bytes,
 922                             &nes->rx_bytes);
 923         i40evf_stat_update_48(&oes->rx_unicast,
 924                             &nes->rx_unicast);
 925         i40evf_stat_update_48(&oes->rx_multicast,
 926                             &nes->rx_multicast);
 927         i40evf_stat_update_48(&oes->rx_broadcast,
 928                             &nes->rx_broadcast);
 929         i40evf_stat_update_32(&oes->rx_discards,
 930                                 &nes->rx_discards);
 931         i40evf_stat_update_32(&oes->rx_unknown_protocol,
 932                             &nes->rx_unknown_protocol);
 933         i40evf_stat_update_48(&oes->tx_bytes,
 934                             &nes->tx_bytes);
 935         i40evf_stat_update_48(&oes->tx_unicast,
 936                             &nes->tx_unicast);
 937         i40evf_stat_update_48(&oes->tx_multicast,
 938                             &nes->tx_multicast);
 939         i40evf_stat_update_48(&oes->tx_broadcast,
 940                             &nes->tx_broadcast);
 941         i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
 942         i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
 943 }
 944
 945 static void
 946 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 947 {
 948         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 949         struct i40e_eth_stats *pstats = NULL;
 950
 951         /* read stat values to clear hardware registers */
 952         i40evf_query_stats(dev, &pstats);
 953
 954         /* set stats offset base on current values */
 955         vf->vsi.eth_stats_offset = *pstats;
 956 }
 957
 958 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 959                                       struct rte_eth_xstat_name *xstats_names,
 960                                       __rte_unused unsigned limit)
 961 {
 962         unsigned i;
 963
 964         if (xstats_names != NULL)
 965                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 966                         snprintf(xstats_names[i].name,
 967                                 sizeof(xstats_names[i].name),
 968                                 "%s", rte_i40evf_stats_strings[i].name);
 969                 }
 970         return I40EVF_NB_XSTATS;
 971 }
 972
 973 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 974                                  struct rte_eth_xstat *xstats, unsigned n)
 975 {
 976         int ret;
 977         unsigned i;
 978         struct i40e_eth_stats *pstats = NULL;
 979         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 980         struct i40e_vsi *vsi = &vf->vsi;
 981
 982         if (n < I40EVF_NB_XSTATS)
 983                 return I40EVF_NB_XSTATS;
 984
 985         ret = i40evf_query_stats(dev, &pstats);
 986         if (ret != 0)
 987                 return 0;
 988
 989         if (!xstats)
 990                 return 0;
 991
 992         i40evf_update_stats(vsi, pstats);
 993
 994         /* loop over xstats array and values from pstats */
 995         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 996                 xstats[i].id = i;
 997                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
 998                         rte_i40evf_stats_strings[i].offset);
 999         }
1000
1001         return I40EVF_NB_XSTATS;
1002 }
1003
1004 static int
1005 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1006 {
1007         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1008         struct virtchnl_vlan_filter_list *vlan_list;
1009         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1010                                                         sizeof(uint16_t)];
1011         int err;
1012         struct vf_cmd_info args;
1013
1014         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1015         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1016         vlan_list->num_elements = 1;
1017         vlan_list->vlan_id[0] = vlanid;
1018
1019         args.ops = VIRTCHNL_OP_ADD_VLAN;
1020         args.in_args = (u8 *)&cmd_buffer;
1021         args.in_args_size = sizeof(cmd_buffer);
1022         args.out_buffer = vf->aq_resp;
1023         args.out_size = I40E_AQ_BUF_SZ;
1024         err = i40evf_execute_vf_cmd(dev, &args);
1025         if (err)
1026                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1027
1028         return err;
1029 }
1030
1031 static int
1032 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1033 {
1034         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1035         struct virtchnl_vlan_filter_list *vlan_list;
1036         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1037                                                         sizeof(uint16_t)];
1038         int err;
1039         struct vf_cmd_info args;
1040
1041         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1042         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1043         vlan_list->num_elements = 1;
1044         vlan_list->vlan_id[0] = vlanid;
1045
1046         args.ops = VIRTCHNL_OP_DEL_VLAN;
1047         args.in_args = (u8 *)&cmd_buffer;
1048         args.in_args_size = sizeof(cmd_buffer);
1049         args.out_buffer = vf->aq_resp;
1050         args.out_size = I40E_AQ_BUF_SZ;
1051         err = i40evf_execute_vf_cmd(dev, &args);
1052         if (err)
1053                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1054
1055         return err;
1056 }
1057
1058 static const struct rte_pci_id pci_id_i40evf_map[] = {
1059         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1060         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1061         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1062         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1063         { .vendor_id = 0, /* sentinel */ },
1064 };
1065
1066 static inline int
1067 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1068                                     struct rte_eth_link *link)
1069 {
1070         struct rte_eth_link *dst = &(dev->data->dev_link);
1071         struct rte_eth_link *src = link;
1072
1073         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1074                                         *(uint64_t *)src) == 0)
1075                 return -1;
1076
1077         return 0;
1078 }
1079
1080 /* Disable IRQ0 */
1081 static inline void
1082 i40evf_disable_irq0(struct i40e_hw *hw)
1083 {
1084         /* Disable all interrupt types */
1085         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1086         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1087                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1088         I40EVF_WRITE_FLUSH(hw);
1089 }
1090
1091 /* Enable IRQ0 */
1092 static inline void
1093 i40evf_enable_irq0(struct i40e_hw *hw)
1094 {
1095         /* Enable admin queue interrupt trigger */
1096         uint32_t val;
1097
1098         i40evf_disable_irq0(hw);
1099         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1100         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1101                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1102         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1103
1104         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1105                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1106                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1107                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1108
1109         I40EVF_WRITE_FLUSH(hw);
1110 }
1111
1112 static int
1113 i40evf_check_vf_reset_done(struct i40e_hw *hw)
1114 {
1115         int i, reset;
1116
1117         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1118                 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1119                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1120                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1121                 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1122                     reset == VIRTCHNL_VFR_COMPLETED)
1123                         break;
1124                 rte_delay_ms(50);
1125         }
1126
1127         if (i >= MAX_RESET_WAIT_CNT)
1128                 return -1;
1129
1130         return 0;
1131 }
1132 static int
1133 i40evf_reset_vf(struct i40e_hw *hw)
1134 {
1135         int ret;
1136
1137         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1138                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1139                 return -1;
1140         }
1141         /**
1142           * After issuing vf reset command to pf, pf won't necessarily
1143           * reset vf, it depends on what state it exactly is. If it's not
1144           * initialized yet, it won't have vf reset since it's in a certain
1145           * state. If not, it will try to reset. Even vf is reset, pf will
1146           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1147           * it to ACTIVE. In this duration, vf may not catch the moment that
1148           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1149           */
1150         rte_delay_ms(200);
1151
1152         ret = i40evf_check_vf_reset_done(hw);
1153         if (ret) {
1154                 PMD_INIT_LOG(ERR, "VF is still resetting");
1155                 return ret;
1156         }
1157
1158         return 0;
1159 }
1160
1161 static int
1162 i40evf_init_vf(struct rte_eth_dev *dev)
1163 {
1164         int i, err, bufsz;
1165         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1166         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1167         uint16_t interval =
1168                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1169
1170         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1171         vf->dev_data = dev->data;
1172         err = i40e_set_mac_type(hw);
1173         if (err) {
1174                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1175                 goto err;
1176         }
1177
1178         err = i40evf_check_vf_reset_done(hw);
1179         if (err)
1180                 goto err;
1181
1182         i40e_init_adminq_parameter(hw);
1183         err = i40e_init_adminq(hw);
1184         if (err) {
1185                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1186                 goto err;
1187         }
1188
1189         /* Reset VF and wait until it's complete */
1190         if (i40evf_reset_vf(hw)) {
1191                 PMD_INIT_LOG(ERR, "reset NIC failed");
1192                 goto err_aq;
1193         }
1194
1195         /* VF reset, shutdown admin queue and initialize again */
1196         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1197                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1198                 goto err;
1199         }
1200
1201         i40e_init_adminq_parameter(hw);
1202         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1203                 PMD_INIT_LOG(ERR, "init_adminq failed");
1204                 goto err;
1205         }
1206
1207         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1208         if (!vf->aq_resp) {
1209                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1210                 goto err_aq;
1211         }
1212         if (i40evf_check_api_version(dev) != 0) {
1213                 PMD_INIT_LOG(ERR, "check_api version failed");
1214                 goto err_api;
1215         }
1216         bufsz = sizeof(struct virtchnl_vf_resource) +
1217                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1218         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1219         if (!vf->vf_res) {
1220                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1221                 goto err_api;
1222         }
1223
1224         if (i40evf_get_vf_resource(dev) != 0) {
1225                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1226                 goto err_alloc;
1227         }
1228
1229         /* got VF config message back from PF, now we can parse it */
1230         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1231                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1232                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1233         }
1234
1235         if (!vf->vsi_res) {
1236                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1237                 goto err_alloc;
1238         }
1239
1240         if (hw->mac.type == I40E_MAC_X722_VF)
1241                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1242         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1243
1244         switch (vf->vsi_res->vsi_type) {
1245         case VIRTCHNL_VSI_SRIOV:
1246                 vf->vsi.type = I40E_VSI_SRIOV;
1247                 break;
1248         default:
1249                 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1250                 break;
1251         }
1252         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1253         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1254
1255         /* Store the MAC address configured by host, or generate random one */
1256         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1257                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1258         else
1259                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1260
1261         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1262                        (I40E_ITR_INDEX_DEFAULT <<
1263                         I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1264                        (interval <<
1265                         I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1266         I40EVF_WRITE_FLUSH(hw);
1267
1268         return 0;
1269
1270 err_alloc:
1271         rte_free(vf->vf_res);
1272         vf->vsi_res = NULL;
1273 err_api:
1274         rte_free(vf->aq_resp);
1275 err_aq:
1276         i40e_shutdown_adminq(hw); /* ignore error */
1277 err:
1278         return -1;
1279 }
1280
1281 static int
1282 i40evf_uninit_vf(struct rte_eth_dev *dev)
1283 {
1284         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1285         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1286
1287         PMD_INIT_FUNC_TRACE();
1288
1289         if (hw->adapter_stopped == 0)
1290                 i40evf_dev_close(dev);
1291         rte_free(vf->vf_res);
1292         vf->vf_res = NULL;
1293         rte_free(vf->aq_resp);
1294         vf->aq_resp = NULL;
1295
1296         return 0;
1297 }
1298
1299 static void
1300 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1301                 __rte_unused uint16_t msglen)
1302 {
1303         struct virtchnl_pf_event *pf_msg =
1304                         (struct virtchnl_pf_event *)msg;
1305         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1306
1307         switch (pf_msg->event) {
1308         case VIRTCHNL_EVENT_RESET_IMPENDING:
1309                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1310                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1311                                               NULL, NULL);
1312                 break;
1313         case VIRTCHNL_EVENT_LINK_CHANGE:
1314                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1315                 vf->link_up = pf_msg->event_data.link_event.link_status;
1316                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1317                 break;
1318         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1319                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1320                 break;
1321         default:
1322                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1323                 break;
1324         }
1325 }
1326
1327 static void
1328 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1329 {
1330         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1331         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1332         struct i40e_arq_event_info info;
1333         uint16_t pending, aq_opc;
1334         enum virtchnl_ops msg_opc;
1335         enum i40e_status_code msg_ret;
1336         int ret;
1337
1338         info.buf_len = I40E_AQ_BUF_SZ;
1339         if (!vf->aq_resp) {
1340                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1341                 return;
1342         }
1343         info.msg_buf = vf->aq_resp;
1344
1345         pending = 1;
1346         while (pending) {
1347                 ret = i40e_clean_arq_element(hw, &info, &pending);
1348
1349                 if (ret != I40E_SUCCESS) {
1350                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1351                                     "ret: %d", ret);
1352                         break;
1353                 }
1354                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1355                 /* For the message sent from pf to vf, opcode is stored in
1356                  * cookie_high of struct i40e_aq_desc, while return error code
1357                  * are stored in cookie_low, Which is done by
1358                  * i40e_aq_send_msg_to_vf in PF driver.*/
1359                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1360                                                   info.desc.cookie_high);
1361                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1362                                                   info.desc.cookie_low);
1363                 switch (aq_opc) {
1364                 case i40e_aqc_opc_send_msg_to_vf:
1365                         if (msg_opc == VIRTCHNL_OP_EVENT)
1366                                 /* process event*/
1367                                 i40evf_handle_pf_event(dev, info.msg_buf,
1368                                                        info.msg_len);
1369                         else {
1370                                 /* read message and it's expected one */
1371                                 if (msg_opc == vf->pend_cmd) {
1372                                         vf->cmd_retval = msg_ret;
1373                                         /* prevent compiler reordering */
1374                                         rte_compiler_barrier();
1375                                         _clear_cmd(vf);
1376                                 } else
1377                                         PMD_DRV_LOG(ERR, "command mismatch,"
1378                                                 "expect %u, get %u",
1379                                                 vf->pend_cmd, msg_opc);
1380                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1381                                              " opcode = %d", msg_opc);
1382                         }
1383                         break;
1384                 default:
1385                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1386                                     aq_opc);
1387                         break;
1388                 }
1389         }
1390 }
1391
1392 /**
1393  * Interrupt handler triggered by NIC  for handling
1394  * specific interrupt. Only adminq interrupt is processed in VF.
1395  *
1396  * @param handle
1397  *  Pointer to interrupt handle.
1398  * @param param
1399  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1400  *
1401  * @return
1402  *  void
1403  */
1404 static void
1405 i40evf_dev_interrupt_handler(void *param)
1406 {
1407         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1408         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1409         uint32_t icr0;
1410
1411         i40evf_disable_irq0(hw);
1412
1413         /* read out interrupt causes */
1414         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1415
1416         /* No interrupt event indicated */
1417         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1418                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1419                 goto done;
1420         }
1421
1422         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1423                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1424                 i40evf_handle_aq_msg(dev);
1425         }
1426
1427         /* Link Status Change interrupt */
1428         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1429                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1430                                    " do nothing");
1431
1432 done:
1433         i40evf_enable_irq0(hw);
1434 }
1435
1436 static int
1437 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1438 {
1439         struct i40e_hw *hw
1440                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1441         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1442
1443         PMD_INIT_FUNC_TRACE();
1444
1445         /* assign ops func pointer */
1446         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1447         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1448         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1449
1450         /*
1451          * For secondary processes, we don't initialise any further as primary
1452          * has already done this work.
1453          */
1454         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1455                 i40e_set_rx_function(eth_dev);
1456                 i40e_set_tx_function(eth_dev);
1457                 return 0;
1458         }
1459         i40e_set_default_ptype_table(eth_dev);
1460         i40e_set_default_pctype_table(eth_dev);
1461         rte_eth_copy_pci_info(eth_dev, pci_dev);
1462
1463         hw->vendor_id = pci_dev->id.vendor_id;
1464         hw->device_id = pci_dev->id.device_id;
1465         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1466         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1467         hw->bus.device = pci_dev->addr.devid;
1468         hw->bus.func = pci_dev->addr.function;
1469         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1470         hw->adapter_stopped = 0;
1471
1472         if(i40evf_init_vf(eth_dev) != 0) {
1473                 PMD_INIT_LOG(ERR, "Init vf failed");
1474                 return -1;
1475         }
1476
1477         /* register callback func to eal lib */
1478         rte_intr_callback_register(&pci_dev->intr_handle,
1479                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1480
1481         /* enable uio intr after callback register */
1482         rte_intr_enable(&pci_dev->intr_handle);
1483
1484         /* configure and enable device interrupt */
1485         i40evf_enable_irq0(hw);
1486
1487         /* copy mac addr */
1488         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1489                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1490                                         0);
1491         if (eth_dev->data->mac_addrs == NULL) {
1492                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1493                                 " store MAC addresses",
1494                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1495                 return -ENOMEM;
1496         }
1497         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1498                         &eth_dev->data->mac_addrs[0]);
1499
1500         return 0;
1501 }
1502
1503 static int
1504 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1505 {
1506         PMD_INIT_FUNC_TRACE();
1507
1508         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1509                 return -EPERM;
1510
1511         eth_dev->dev_ops = NULL;
1512         eth_dev->rx_pkt_burst = NULL;
1513         eth_dev->tx_pkt_burst = NULL;
1514
1515         if (i40evf_uninit_vf(eth_dev) != 0) {
1516                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1517                 return -1;
1518         }
1519
1520         rte_free(eth_dev->data->mac_addrs);
1521         eth_dev->data->mac_addrs = NULL;
1522
1523         return 0;
1524 }
1525
1526 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1527         struct rte_pci_device *pci_dev)
1528 {
1529         return rte_eth_dev_pci_generic_probe(pci_dev,
1530                 sizeof(struct i40e_adapter), i40evf_dev_init);
1531 }
1532
1533 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1534 {
1535         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1536 }
1537
1538 /*
1539  * virtual function driver struct
1540  */
1541 static struct rte_pci_driver rte_i40evf_pmd = {
1542         .id_table = pci_id_i40evf_map,
1543         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1544         .probe = eth_i40evf_pci_probe,
1545         .remove = eth_i40evf_pci_remove,
1546 };
1547
1548 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1549 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1550 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1551
1552 static int
1553 i40evf_dev_configure(struct rte_eth_dev *dev)
1554 {
1555         struct i40e_adapter *ad =
1556                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1557         struct rte_eth_conf *conf = &dev->data->dev_conf;
1558         struct i40e_vf *vf;
1559
1560         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1561          * allocation or vector Rx preconditions we will reset it.
1562          */
1563         ad->rx_bulk_alloc_allowed = true;
1564         ad->rx_vec_allowed = true;
1565         ad->tx_simple_allowed = true;
1566         ad->tx_vec_allowed = true;
1567
1568         /* For non-DPDK PF drivers, VF has no ability to disable HW
1569          * CRC strip, and is implicitly enabled by the PF.
1570          */
1571         if (!conf->rxmode.hw_strip_crc) {
1572                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1573                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1574                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1575                         /* Peer is running non-DPDK PF driver. */
1576                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1577                         return -EINVAL;
1578                 }
1579         }
1580
1581         return i40evf_init_vlan(dev);
1582 }
1583
1584 static int
1585 i40evf_init_vlan(struct rte_eth_dev *dev)
1586 {
1587         /* Apply vlan offload setting */
1588         return i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1589 }
1590
1591 static int
1592 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1593 {
1594         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1595
1596         /* Vlan stripping setting */
1597         if (mask & ETH_VLAN_STRIP_MASK) {
1598                 /* Enable or disable VLAN stripping */
1599                 if (dev_conf->rxmode.hw_vlan_strip)
1600                         i40evf_enable_vlan_strip(dev);
1601                 else
1602                         i40evf_disable_vlan_strip(dev);
1603         }
1604
1605         return 0;
1606 }
1607
1608 static int
1609 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1610 {
1611         struct i40e_rx_queue *rxq;
1612         int err = 0;
1613         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1614
1615         PMD_INIT_FUNC_TRACE();
1616
1617         if (rx_queue_id < dev->data->nb_rx_queues) {
1618                 rxq = dev->data->rx_queues[rx_queue_id];
1619
1620                 err = i40e_alloc_rx_queue_mbufs(rxq);
1621                 if (err) {
1622                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1623                         return err;
1624                 }
1625
1626                 rte_wmb();
1627
1628                 /* Init the RX tail register. */
1629                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1630                 I40EVF_WRITE_FLUSH(hw);
1631
1632                 /* Ready to switch the queue on */
1633                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1634
1635                 if (err)
1636                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1637                                     rx_queue_id);
1638                 else
1639                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1640         }
1641
1642         return err;
1643 }
1644
1645 static int
1646 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1647 {
1648         struct i40e_rx_queue *rxq;
1649         int err;
1650
1651         if (rx_queue_id < dev->data->nb_rx_queues) {
1652                 rxq = dev->data->rx_queues[rx_queue_id];
1653
1654                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1655
1656                 if (err) {
1657                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1658                                     rx_queue_id);
1659                         return err;
1660                 }
1661
1662                 i40e_rx_queue_release_mbufs(rxq);
1663                 i40e_reset_rx_queue(rxq);
1664                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1665         }
1666
1667         return 0;
1668 }
1669
1670 static int
1671 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1672 {
1673         int err = 0;
1674
1675         PMD_INIT_FUNC_TRACE();
1676
1677         if (tx_queue_id < dev->data->nb_tx_queues) {
1678
1679                 /* Ready to switch the queue on */
1680                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1681
1682                 if (err)
1683                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1684                                     tx_queue_id);
1685                 else
1686                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1687         }
1688
1689         return err;
1690 }
1691
1692 static int
1693 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1694 {
1695         struct i40e_tx_queue *txq;
1696         int err;
1697
1698         if (tx_queue_id < dev->data->nb_tx_queues) {
1699                 txq = dev->data->tx_queues[tx_queue_id];
1700
1701                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1702
1703                 if (err) {
1704                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1705                                     tx_queue_id);
1706                         return err;
1707                 }
1708
1709                 i40e_tx_queue_release_mbufs(txq);
1710                 i40e_reset_tx_queue(txq);
1711                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1712         }
1713
1714         return 0;
1715 }
1716
1717 static int
1718 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1719 {
1720         int ret;
1721
1722         if (on)
1723                 ret = i40evf_add_vlan(dev, vlan_id);
1724         else
1725                 ret = i40evf_del_vlan(dev,vlan_id);
1726
1727         return ret;
1728 }
1729
1730 static int
1731 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1732 {
1733         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1734         struct rte_eth_dev_data *dev_data = dev->data;
1735         struct rte_pktmbuf_pool_private *mbp_priv;
1736         uint16_t buf_size, len;
1737
1738         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1739         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1740         I40EVF_WRITE_FLUSH(hw);
1741
1742         /* Calculate the maximum packet length allowed */
1743         mbp_priv = rte_mempool_get_priv(rxq->mp);
1744         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1745                                         RTE_PKTMBUF_HEADROOM);
1746         rxq->hs_mode = i40e_header_split_none;
1747         rxq->rx_hdr_len = 0;
1748         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1749         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1750         rxq->max_pkt_len = RTE_MIN(len,
1751                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1752
1753         /**
1754          * Check if the jumbo frame and maximum packet length are set correctly
1755          */
1756         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1757                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1758                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1759                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1760                                 "larger than %u and smaller than %u, as jumbo "
1761                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1762                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1763                         return I40E_ERR_CONFIG;
1764                 }
1765         } else {
1766                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1767                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1768                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1769                                 "larger than %u and smaller than %u, as jumbo "
1770                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1771                                                 (uint32_t)ETHER_MAX_LEN);
1772                         return I40E_ERR_CONFIG;
1773                 }
1774         }
1775
1776         if (dev_data->dev_conf.rxmode.enable_scatter ||
1777             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1778                 dev_data->scattered_rx = 1;
1779         }
1780
1781         return 0;
1782 }
1783
1784 static int
1785 i40evf_rx_init(struct rte_eth_dev *dev)
1786 {
1787         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1788         uint16_t i;
1789         int ret = I40E_SUCCESS;
1790         struct i40e_rx_queue **rxq =
1791                 (struct i40e_rx_queue **)dev->data->rx_queues;
1792
1793         i40evf_config_rss(vf);
1794         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1795                 if (!rxq[i] || !rxq[i]->q_set)
1796                         continue;
1797                 ret = i40evf_rxq_init(dev, rxq[i]);
1798                 if (ret != I40E_SUCCESS)
1799                         break;
1800         }
1801         if (ret == I40E_SUCCESS)
1802                 i40e_set_rx_function(dev);
1803
1804         return ret;
1805 }
1806
1807 static void
1808 i40evf_tx_init(struct rte_eth_dev *dev)
1809 {
1810         uint16_t i;
1811         struct i40e_tx_queue **txq =
1812                 (struct i40e_tx_queue **)dev->data->tx_queues;
1813         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1814
1815         for (i = 0; i < dev->data->nb_tx_queues; i++)
1816                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1817
1818         i40e_set_tx_function(dev);
1819 }
1820
1821 static inline void
1822 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1823 {
1824         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1825         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1826         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1827
1828         if (!rte_intr_allow_others(intr_handle)) {
1829                 I40E_WRITE_REG(hw,
1830                                I40E_VFINT_DYN_CTL01,
1831                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1832                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1833                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1834                 I40EVF_WRITE_FLUSH(hw);
1835                 return;
1836         }
1837
1838         I40EVF_WRITE_FLUSH(hw);
1839 }
1840
1841 static inline void
1842 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1843 {
1844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1846         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1847
1848         if (!rte_intr_allow_others(intr_handle)) {
1849                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1850                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1851                 I40EVF_WRITE_FLUSH(hw);
1852                 return;
1853         }
1854
1855         I40EVF_WRITE_FLUSH(hw);
1856 }
1857
1858 static int
1859 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1860 {
1861         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1862         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1863         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1864         uint16_t interval =
1865                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1866         uint16_t msix_intr;
1867
1868         msix_intr = intr_handle->intr_vec[queue_id];
1869         if (msix_intr == I40E_MISC_VEC_ID)
1870                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1871                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1872                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1873                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1874                                (interval <<
1875                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1876         else
1877                 I40E_WRITE_REG(hw,
1878                                I40E_VFINT_DYN_CTLN1(msix_intr -
1879                                                     I40E_RX_VEC_START),
1880                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1881                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1882                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1883                                (interval <<
1884                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1885
1886         I40EVF_WRITE_FLUSH(hw);
1887
1888         rte_intr_enable(&pci_dev->intr_handle);
1889
1890         return 0;
1891 }
1892
1893 static int
1894 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1895 {
1896         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1897         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1898         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1899         uint16_t msix_intr;
1900
1901         msix_intr = intr_handle->intr_vec[queue_id];
1902         if (msix_intr == I40E_MISC_VEC_ID)
1903                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1904         else
1905                 I40E_WRITE_REG(hw,
1906                                I40E_VFINT_DYN_CTLN1(msix_intr -
1907                                                     I40E_RX_VEC_START),
1908                                0);
1909
1910         I40EVF_WRITE_FLUSH(hw);
1911
1912         return 0;
1913 }
1914
1915 static void
1916 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1917 {
1918         struct virtchnl_ether_addr_list *list;
1919         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1920         int err, i, j;
1921         int next_begin = 0;
1922         int begin = 0;
1923         uint32_t len;
1924         struct ether_addr *addr;
1925         struct vf_cmd_info args;
1926
1927         do {
1928                 j = 0;
1929                 len = sizeof(struct virtchnl_ether_addr_list);
1930                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1931                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1932                                 continue;
1933                         len += sizeof(struct virtchnl_ether_addr);
1934                         if (len >= I40E_AQ_BUF_SZ) {
1935                                 next_begin = i + 1;
1936                                 break;
1937                         }
1938                 }
1939
1940                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1941                 if (!list) {
1942                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1943                         return;
1944                 }
1945
1946                 for (i = begin; i < next_begin; i++) {
1947                         addr = &dev->data->mac_addrs[i];
1948                         if (is_zero_ether_addr(addr))
1949                                 continue;
1950                         rte_memcpy(list->list[j].addr, addr->addr_bytes,
1951                                          sizeof(addr->addr_bytes));
1952                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1953                                     addr->addr_bytes[0], addr->addr_bytes[1],
1954                                     addr->addr_bytes[2], addr->addr_bytes[3],
1955                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1956                         j++;
1957                 }
1958                 list->vsi_id = vf->vsi_res->vsi_id;
1959                 list->num_elements = j;
1960                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1961                            VIRTCHNL_OP_DEL_ETH_ADDR;
1962                 args.in_args = (uint8_t *)list;
1963                 args.in_args_size = len;
1964                 args.out_buffer = vf->aq_resp;
1965                 args.out_size = I40E_AQ_BUF_SZ;
1966                 err = i40evf_execute_vf_cmd(dev, &args);
1967                 if (err) {
1968                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1969                                     add ? "OP_ADD_ETHER_ADDRESS" :
1970                                     "OP_DEL_ETHER_ADDRESS");
1971                 } else {
1972                         if (add)
1973                                 vf->vsi.mac_num++;
1974                         else
1975                                 vf->vsi.mac_num--;
1976                 }
1977                 rte_free(list);
1978                 begin = next_begin;
1979         } while (begin < I40E_NUM_MACADDR_MAX);
1980 }
1981
1982 static int
1983 i40evf_dev_start(struct rte_eth_dev *dev)
1984 {
1985         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1986         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1987         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1988         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1989         uint32_t intr_vector = 0;
1990
1991         PMD_INIT_FUNC_TRACE();
1992
1993         hw->adapter_stopped = 0;
1994
1995         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1996         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1997                                         dev->data->nb_tx_queues);
1998
1999         /* check and configure queue intr-vector mapping */
2000         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2001                 intr_vector = dev->data->nb_rx_queues;
2002                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2003                         return -1;
2004         }
2005
2006         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2007                 intr_handle->intr_vec =
2008                         rte_zmalloc("intr_vec",
2009                                     dev->data->nb_rx_queues * sizeof(int), 0);
2010                 if (!intr_handle->intr_vec) {
2011                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2012                                      " intr_vec", dev->data->nb_rx_queues);
2013                         return -ENOMEM;
2014                 }
2015         }
2016
2017         if (i40evf_rx_init(dev) != 0){
2018                 PMD_DRV_LOG(ERR, "failed to do RX init");
2019                 return -1;
2020         }
2021
2022         i40evf_tx_init(dev);
2023
2024         if (i40evf_configure_vsi_queues(dev) != 0) {
2025                 PMD_DRV_LOG(ERR, "configure queues failed");
2026                 goto err_queue;
2027         }
2028         if (i40evf_config_irq_map(dev)) {
2029                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2030                 goto err_queue;
2031         }
2032
2033         /* Set all mac addrs */
2034         i40evf_add_del_all_mac_addr(dev, TRUE);
2035
2036         if (i40evf_start_queues(dev) != 0) {
2037                 PMD_DRV_LOG(ERR, "enable queues failed");
2038                 goto err_mac;
2039         }
2040
2041         /* When a VF port is bound to VFIO-PCI, only miscellaneous interrupt
2042          * is mapped to VFIO vector 0 in i40evf_dev_init( ).
2043          * If previous VFIO interrupt mapping set in i40evf_dev_init( ) is
2044          * not cleared, it will fail when rte_intr_enable( ) tries to map Rx
2045          * queue interrupt to other VFIO vectors.
2046          * So clear uio/vfio intr/evevnfd first to avoid failure.
2047          */
2048         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2049                 rte_intr_disable(intr_handle);
2050                 rte_intr_enable(intr_handle);
2051         }
2052
2053         i40evf_enable_queues_intr(dev);
2054
2055         return 0;
2056
2057 err_mac:
2058         i40evf_add_del_all_mac_addr(dev, FALSE);
2059 err_queue:
2060         return -1;
2061 }
2062
2063 static void
2064 i40evf_dev_stop(struct rte_eth_dev *dev)
2065 {
2066         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2067         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2068         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2069
2070         PMD_INIT_FUNC_TRACE();
2071
2072         if (hw->adapter_stopped == 1)
2073                 return;
2074         i40evf_stop_queues(dev);
2075         i40evf_disable_queues_intr(dev);
2076         i40e_dev_clear_queues(dev);
2077
2078         /* Clean datapath event and queue/vec mapping */
2079         rte_intr_efd_disable(intr_handle);
2080         if (intr_handle->intr_vec) {
2081                 rte_free(intr_handle->intr_vec);
2082                 intr_handle->intr_vec = NULL;
2083         }
2084         /* remove all mac addrs */
2085         i40evf_add_del_all_mac_addr(dev, FALSE);
2086         hw->adapter_stopped = 1;
2087
2088 }
2089
2090 static int
2091 i40evf_dev_link_update(struct rte_eth_dev *dev,
2092                        __rte_unused int wait_to_complete)
2093 {
2094         struct rte_eth_link new_link;
2095         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2096         /*
2097          * DPDK pf host provide interfacet to acquire link status
2098          * while Linux driver does not
2099          */
2100
2101         /* Linux driver PF host */
2102         switch (vf->link_speed) {
2103         case I40E_LINK_SPEED_100MB:
2104                 new_link.link_speed = ETH_SPEED_NUM_100M;
2105                 break;
2106         case I40E_LINK_SPEED_1GB:
2107                 new_link.link_speed = ETH_SPEED_NUM_1G;
2108                 break;
2109         case I40E_LINK_SPEED_10GB:
2110                 new_link.link_speed = ETH_SPEED_NUM_10G;
2111                 break;
2112         case I40E_LINK_SPEED_20GB:
2113                 new_link.link_speed = ETH_SPEED_NUM_20G;
2114                 break;
2115         case I40E_LINK_SPEED_25GB:
2116                 new_link.link_speed = ETH_SPEED_NUM_25G;
2117                 break;
2118         case I40E_LINK_SPEED_40GB:
2119                 new_link.link_speed = ETH_SPEED_NUM_40G;
2120                 break;
2121         default:
2122                 new_link.link_speed = ETH_SPEED_NUM_100M;
2123                 break;
2124         }
2125         /* full duplex only */
2126         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2127         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2128                                              ETH_LINK_DOWN;
2129         new_link.link_autoneg =
2130                 dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED;
2131
2132         i40evf_dev_atomic_write_link_status(dev, &new_link);
2133
2134         return 0;
2135 }
2136
2137 static void
2138 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2139 {
2140         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2141         int ret;
2142
2143         /* If enabled, just return */
2144         if (vf->promisc_unicast_enabled)
2145                 return;
2146
2147         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2148         if (ret == 0)
2149                 vf->promisc_unicast_enabled = TRUE;
2150 }
2151
2152 static void
2153 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2154 {
2155         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2156         int ret;
2157
2158         /* If disabled, just return */
2159         if (!vf->promisc_unicast_enabled)
2160                 return;
2161
2162         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2163         if (ret == 0)
2164                 vf->promisc_unicast_enabled = FALSE;
2165 }
2166
2167 static void
2168 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2169 {
2170         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2171         int ret;
2172
2173         /* If enabled, just return */
2174         if (vf->promisc_multicast_enabled)
2175                 return;
2176
2177         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2178         if (ret == 0)
2179                 vf->promisc_multicast_enabled = TRUE;
2180 }
2181
2182 static void
2183 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2184 {
2185         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2186         int ret;
2187
2188         /* If enabled, just return */
2189         if (!vf->promisc_multicast_enabled)
2190                 return;
2191
2192         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2193         if (ret == 0)
2194                 vf->promisc_multicast_enabled = FALSE;
2195 }
2196
2197 static void
2198 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2199 {
2200         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2201
2202         memset(dev_info, 0, sizeof(*dev_info));
2203         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2204         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2205         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2206         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2207         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2208         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2209         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2210         dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2211         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2212         dev_info->rx_offload_capa =
2213                 DEV_RX_OFFLOAD_VLAN_STRIP |
2214                 DEV_RX_OFFLOAD_QINQ_STRIP |
2215                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2216                 DEV_RX_OFFLOAD_UDP_CKSUM |
2217                 DEV_RX_OFFLOAD_TCP_CKSUM;
2218         dev_info->tx_offload_capa =
2219                 DEV_TX_OFFLOAD_VLAN_INSERT |
2220                 DEV_TX_OFFLOAD_QINQ_INSERT |
2221                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2222                 DEV_TX_OFFLOAD_UDP_CKSUM |
2223                 DEV_TX_OFFLOAD_TCP_CKSUM |
2224                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2225
2226         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2227                 .rx_thresh = {
2228                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2229                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2230                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2231                 },
2232                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2233                 .rx_drop_en = 0,
2234         };
2235
2236         dev_info->default_txconf = (struct rte_eth_txconf) {
2237                 .tx_thresh = {
2238                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2239                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2240                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2241                 },
2242                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2243                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2244                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2245                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2246         };
2247
2248         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2249                 .nb_max = I40E_MAX_RING_DESC,
2250                 .nb_min = I40E_MIN_RING_DESC,
2251                 .nb_align = I40E_ALIGN_RING_DESC,
2252         };
2253
2254         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2255                 .nb_max = I40E_MAX_RING_DESC,
2256                 .nb_min = I40E_MIN_RING_DESC,
2257                 .nb_align = I40E_ALIGN_RING_DESC,
2258         };
2259 }
2260
2261 static int
2262 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2263 {
2264         int ret;
2265         struct i40e_eth_stats *pstats = NULL;
2266         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2267         struct i40e_vsi *vsi = &vf->vsi;
2268
2269         ret = i40evf_query_stats(dev, &pstats);
2270         if (ret == 0) {
2271                 i40evf_update_stats(vsi, pstats);
2272
2273                 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2274                                                 pstats->rx_broadcast;
2275                 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2276                                                 pstats->tx_unicast;
2277                 stats->imissed = pstats->rx_discards;
2278                 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2279                 stats->ibytes = pstats->rx_bytes;
2280                 stats->obytes = pstats->tx_bytes;
2281         } else {
2282                 PMD_DRV_LOG(ERR, "Get statistics failed");
2283         }
2284         return ret;
2285 }
2286
2287 static void
2288 i40evf_dev_close(struct rte_eth_dev *dev)
2289 {
2290         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2291         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2292         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2293
2294         i40evf_dev_stop(dev);
2295         i40e_dev_free_queues(dev);
2296         i40evf_reset_vf(hw);
2297         i40e_shutdown_adminq(hw);
2298         /* disable uio intr before callback unregister */
2299         rte_intr_disable(intr_handle);
2300
2301         /* unregister callback func from eal lib */
2302         rte_intr_callback_unregister(intr_handle,
2303                                      i40evf_dev_interrupt_handler, dev);
2304         i40evf_disable_irq0(hw);
2305 }
2306
2307 /*
2308  * Reset VF device only to re-initialize resources in PMD layer
2309  */
2310 static int
2311 i40evf_dev_reset(struct rte_eth_dev *dev)
2312 {
2313         int ret;
2314
2315         ret = i40evf_dev_uninit(dev);
2316         if (ret)
2317                 return ret;
2318
2319         ret = i40evf_dev_init(dev);
2320
2321         return ret;
2322 }
2323
2324 static int
2325 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2326 {
2327         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2328         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2329         int ret;
2330
2331         if (!lut)
2332                 return -EINVAL;
2333
2334         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2335                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2336                                           lut, lut_size);
2337                 if (ret) {
2338                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2339                         return ret;
2340                 }
2341         } else {
2342                 uint32_t *lut_dw = (uint32_t *)lut;
2343                 uint16_t i, lut_size_dw = lut_size / 4;
2344
2345                 for (i = 0; i < lut_size_dw; i++)
2346                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2347         }
2348
2349         return 0;
2350 }
2351
2352 static int
2353 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2354 {
2355         struct i40e_vf *vf;
2356         struct i40e_hw *hw;
2357         int ret;
2358
2359         if (!vsi || !lut)
2360                 return -EINVAL;
2361
2362         vf = I40E_VSI_TO_VF(vsi);
2363         hw = I40E_VSI_TO_HW(vsi);
2364
2365         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2366                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2367                                           lut, lut_size);
2368                 if (ret) {
2369                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2370                         return ret;
2371                 }
2372         } else {
2373                 uint32_t *lut_dw = (uint32_t *)lut;
2374                 uint16_t i, lut_size_dw = lut_size / 4;
2375
2376                 for (i = 0; i < lut_size_dw; i++)
2377                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2378                 I40EVF_WRITE_FLUSH(hw);
2379         }
2380
2381         return 0;
2382 }
2383
2384 static int
2385 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2386                            struct rte_eth_rss_reta_entry64 *reta_conf,
2387                            uint16_t reta_size)
2388 {
2389         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2390         uint8_t *lut;
2391         uint16_t i, idx, shift;
2392         int ret;
2393
2394         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2395                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2396                         "(%d) doesn't match the number of hardware can "
2397                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2398                 return -EINVAL;
2399         }
2400
2401         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2402         if (!lut) {
2403                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2404                 return -ENOMEM;
2405         }
2406         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2407         if (ret)
2408                 goto out;
2409         for (i = 0; i < reta_size; i++) {
2410                 idx = i / RTE_RETA_GROUP_SIZE;
2411                 shift = i % RTE_RETA_GROUP_SIZE;
2412                 if (reta_conf[idx].mask & (1ULL << shift))
2413                         lut[i] = reta_conf[idx].reta[shift];
2414         }
2415         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2416
2417 out:
2418         rte_free(lut);
2419
2420         return ret;
2421 }
2422
2423 static int
2424 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2425                           struct rte_eth_rss_reta_entry64 *reta_conf,
2426                           uint16_t reta_size)
2427 {
2428         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2429         uint16_t i, idx, shift;
2430         uint8_t *lut;
2431         int ret;
2432
2433         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2434                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2435                         "(%d) doesn't match the number of hardware can "
2436                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2437                 return -EINVAL;
2438         }
2439
2440         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2441         if (!lut) {
2442                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2443                 return -ENOMEM;
2444         }
2445
2446         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2447         if (ret)
2448                 goto out;
2449         for (i = 0; i < reta_size; i++) {
2450                 idx = i / RTE_RETA_GROUP_SIZE;
2451                 shift = i % RTE_RETA_GROUP_SIZE;
2452                 if (reta_conf[idx].mask & (1ULL << shift))
2453                         reta_conf[idx].reta[shift] = lut[i];
2454         }
2455
2456 out:
2457         rte_free(lut);
2458
2459         return ret;
2460 }
2461
2462 static int
2463 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2464 {
2465         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2466         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2467         int ret = 0;
2468
2469         if (!key || key_len == 0) {
2470                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2471                 return 0;
2472         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2473                 sizeof(uint32_t)) {
2474                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2475                 return -EINVAL;
2476         }
2477
2478         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2479                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2480                         (struct i40e_aqc_get_set_rss_key_data *)key;
2481
2482                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2483                 if (ret)
2484                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2485                                      "via AQ");
2486         } else {
2487                 uint32_t *hash_key = (uint32_t *)key;
2488                 uint16_t i;
2489
2490                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2491                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2492                 I40EVF_WRITE_FLUSH(hw);
2493         }
2494
2495         return ret;
2496 }
2497
2498 static int
2499 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2500 {
2501         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2502         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2503         int ret;
2504
2505         if (!key || !key_len)
2506                 return -EINVAL;
2507
2508         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2509                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2510                         (struct i40e_aqc_get_set_rss_key_data *)key);
2511                 if (ret) {
2512                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2513                         return ret;
2514                 }
2515         } else {
2516                 uint32_t *key_dw = (uint32_t *)key;
2517                 uint16_t i;
2518
2519                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2520                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2521         }
2522         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2523
2524         return 0;
2525 }
2526
2527 static int
2528 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2529 {
2530         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2531         uint64_t hena;
2532         int ret;
2533
2534         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2535                                  rss_conf->rss_key_len);
2536         if (ret)
2537                 return ret;
2538
2539         hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2540         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2541         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2542         I40EVF_WRITE_FLUSH(hw);
2543
2544         return 0;
2545 }
2546
2547 static void
2548 i40evf_disable_rss(struct i40e_vf *vf)
2549 {
2550         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2551
2552         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2553         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2554         I40EVF_WRITE_FLUSH(hw);
2555 }
2556
2557 static int
2558 i40evf_config_rss(struct i40e_vf *vf)
2559 {
2560         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2561         struct rte_eth_rss_conf rss_conf;
2562         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2563         uint16_t num;
2564
2565         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2566                 i40evf_disable_rss(vf);
2567                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2568                 return 0;
2569         }
2570
2571         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2572         /* Fill out the look up table */
2573         for (i = 0, j = 0; i < nb_q; i++, j++) {
2574                 if (j >= num)
2575                         j = 0;
2576                 lut = (lut << 8) | j;
2577                 if ((i & 3) == 3)
2578                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2579         }
2580
2581         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2582         if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2583                 i40evf_disable_rss(vf);
2584                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2585                 return 0;
2586         }
2587
2588         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2589                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2590                 /* Calculate the default hash key */
2591                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2592                         rss_key_default[i] = (uint32_t)rte_rand();
2593                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2594                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2595                         sizeof(uint32_t);
2596         }
2597
2598         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2599 }
2600
2601 static int
2602 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2603                            struct rte_eth_rss_conf *rss_conf)
2604 {
2605         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2606         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2607         uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2608         uint64_t hena;
2609
2610         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2611         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2612
2613         if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2614                 if (rss_hf != 0) /* Enable RSS */
2615                         return -EINVAL;
2616                 return 0;
2617         }
2618
2619         /* RSS enabled */
2620         if (rss_hf == 0) /* Disable RSS */
2621                 return -EINVAL;
2622
2623         return i40evf_hw_rss_hash_set(vf, rss_conf);
2624 }
2625
2626 static int
2627 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2628                              struct rte_eth_rss_conf *rss_conf)
2629 {
2630         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2631         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2632         uint64_t hena;
2633
2634         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2635                            &rss_conf->rss_key_len);
2636
2637         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2638         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2639         rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2640
2641         return 0;
2642 }
2643
2644 static int
2645 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2646 {
2647         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2648         struct rte_eth_dev_data *dev_data = vf->dev_data;
2649         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2650         int ret = 0;
2651
2652         /* check if mtu is within the allowed range */
2653         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2654                 return -EINVAL;
2655
2656         /* mtu setting is forbidden if port is start */
2657         if (dev_data->dev_started) {
2658                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2659                             dev_data->port_id);
2660                 return -EBUSY;
2661         }
2662
2663         if (frame_size > ETHER_MAX_LEN)
2664                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2665         else
2666                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2667
2668         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2669
2670         return ret;
2671 }
2672
2673 static void
2674 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2675                             struct ether_addr *mac_addr)
2676 {
2677         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2678
2679         if (!is_valid_assigned_ether_addr(mac_addr)) {
2680                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2681                 return;
2682         }
2683
2684         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2685                 return;
2686
2687         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2688                 return;
2689
2690         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2691
2692         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2693 }