drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   int wait_to_complete);
 111 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static void i40evf_dev_close(struct rte_eth_dev *dev);
 123 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 130                                      uint16_t rx_queue_id);
 131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 132                                     uint16_t rx_queue_id);
 133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 134                                      uint16_t tx_queue_id);
 135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 136                                     uint16_t tx_queue_id);
 137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 138                                struct ether_addr *addr,
 139                                uint32_t index,
 140                                uint32_t pool);
 141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 143                         struct rte_eth_rss_reta_entry64 *reta_conf,
 144                         uint16_t reta_size);
 145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                         struct rte_eth_rss_reta_entry64 *reta_conf,
 147                         uint16_t reta_size);
 148 static int i40evf_config_rss(struct i40e_vf *vf);
 149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 150                                       struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 152                                         struct rte_eth_rss_conf *rss_conf);
 153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 155                                         struct ether_addr *mac_addr);
 156 static int
 157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static int
 159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 161                                    uint8_t *msg,
 162                                    uint16_t msglen);
 163
 164 /* Default hash key buffer for RSS */
 165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 166
 167 struct rte_i40evf_xstats_name_off {
 168         char name[RTE_ETH_XSTATS_NAME_SIZE];
 169         unsigned offset;
 170 };
 171
 172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 173         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 174         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 175         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 176         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 177         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 178         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 179                 rx_unknown_protocol)},
 180         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 182         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 183         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 184         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 185         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 186 };
 187
 188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 189                 sizeof(rte_i40evf_stats_strings[0]))
 190
 191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 192         .dev_configure        = i40evf_dev_configure,
 193         .dev_start            = i40evf_dev_start,
 194         .dev_stop             = i40evf_dev_stop,
 195         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 196         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 197         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 198         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 199         .link_update          = i40evf_dev_link_update,
 200         .stats_get            = i40evf_dev_stats_get,
 201         .stats_reset          = i40evf_dev_xstats_reset,
 202         .xstats_get           = i40evf_dev_xstats_get,
 203         .xstats_get_names     = i40evf_dev_xstats_get_names,
 204         .xstats_reset         = i40evf_dev_xstats_reset,
 205         .dev_close            = i40evf_dev_close,
 206         .dev_reset            = i40evf_dev_reset,
 207         .dev_infos_get        = i40evf_dev_info_get,
 208         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 209         .vlan_filter_set      = i40evf_vlan_filter_set,
 210         .vlan_offload_set     = i40evf_vlan_offload_set,
 211         .rx_queue_start       = i40evf_dev_rx_queue_start,
 212         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 213         .tx_queue_start       = i40evf_dev_tx_queue_start,
 214         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 215         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 216         .rx_queue_release     = i40e_dev_rx_queue_release,
 217         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 218         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 219         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 220         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 221         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 222         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 223         .tx_queue_release     = i40e_dev_tx_queue_release,
 224         .rx_queue_count       = i40e_dev_rx_queue_count,
 225         .rxq_info_get         = i40e_rxq_info_get,
 226         .txq_info_get         = i40e_txq_info_get,
 227         .mac_addr_add         = i40evf_add_mac_addr,
 228         .mac_addr_remove      = i40evf_del_mac_addr,
 229         .reta_update          = i40evf_dev_rss_reta_update,
 230         .reta_query           = i40evf_dev_rss_reta_query,
 231         .rss_hash_update      = i40evf_dev_rss_hash_update,
 232         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 233         .mtu_set              = i40evf_dev_mtu_set,
 234         .mac_addr_set         = i40evf_set_default_mac_addr,
 235 };
 236
 237 /*
 238  * Read data in admin queue to get msg from pf driver
 239  */
 240 static enum i40evf_aq_result
 241 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 242 {
 243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 245         struct i40e_arq_event_info event;
 246         enum virtchnl_ops opcode;
 247         enum i40e_status_code retval;
 248         int ret;
 249         enum i40evf_aq_result result = I40EVF_MSG_NON;
 250
 251         event.buf_len = data->buf_len;
 252         event.msg_buf = data->msg;
 253         ret = i40e_clean_arq_element(hw, &event, NULL);
 254         /* Can't read any msg from adminQ */
 255         if (ret) {
 256                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 257                         result = I40EVF_MSG_ERR;
 258                 return result;
 259         }
 260
 261         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 262         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 263         /* pf sys event */
 264         if (opcode == VIRTCHNL_OP_EVENT) {
 265                 struct virtchnl_pf_event *vpe =
 266                         (struct virtchnl_pf_event *)event.msg_buf;
 267
 268                 result = I40EVF_MSG_SYS;
 269                 switch (vpe->event) {
 270                 case VIRTCHNL_EVENT_LINK_CHANGE:
 271                         vf->link_up =
 272                                 vpe->event_data.link_event.link_status;
 273                         vf->link_speed =
 274                                 vpe->event_data.link_event.link_speed;
 275                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 276                         PMD_DRV_LOG(INFO, "Link status update:%s",
 277                                     vf->link_up ? "up" : "down");
 278                         break;
 279                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 280                         vf->vf_reset = true;
 281                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 282                         PMD_DRV_LOG(INFO, "vf is reseting");
 283                         break;
 284                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 285                         vf->dev_closed = true;
 286                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 287                         PMD_DRV_LOG(INFO, "PF driver closed");
 288                         break;
 289                 default:
 290                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 291                                     __func__, vpe->event);
 292                 }
 293         } else {
 294                 /* async reply msg on command issued by vf previously */
 295                 result = I40EVF_MSG_CMD;
 296                 /* Actual data length read from PF */
 297                 data->msg_len = event.msg_len;
 298         }
 299
 300         data->result = retval;
 301         data->ops = opcode;
 302
 303         return result;
 304 }
 305
 306 /**
 307  * clear current command. Only call in case execute
 308  * _atomic_set_cmd successfully.
 309  */
 310 static inline void
 311 _clear_cmd(struct i40e_vf *vf)
 312 {
 313         rte_wmb();
 314         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 315 }
 316
 317 /*
 318  * Check there is pending cmd in execution. If none, set new command.
 319  */
 320 static inline int
 321 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 322 {
 323         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 324                         VIRTCHNL_OP_UNKNOWN, ops);
 325
 326         if (!ret)
 327                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 328
 329         return !ret;
 330 }
 331
 332 #define MAX_TRY_TIMES 200
 333 #define ASQ_DELAY_MS  10
 334
 335 static int
 336 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 337 {
 338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 340         struct i40evf_arq_msg_info info;
 341         enum i40evf_aq_result ret;
 342         int err, i = 0;
 343
 344         if (_atomic_set_cmd(vf, args->ops))
 345                 return -1;
 346
 347         info.msg = args->out_buffer;
 348         info.buf_len = args->out_size;
 349         info.ops = VIRTCHNL_OP_UNKNOWN;
 350         info.result = I40E_SUCCESS;
 351
 352         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 353                      args->in_args, args->in_args_size, NULL);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 356                 _clear_cmd(vf);
 357                 return err;
 358         }
 359
 360         switch (args->ops) {
 361         case VIRTCHNL_OP_RESET_VF:
 362                 /*no need to process in this function */
 363                 err = 0;
 364                 break;
 365         case VIRTCHNL_OP_VERSION:
 366         case VIRTCHNL_OP_GET_VF_RESOURCES:
 367                 /* for init adminq commands, need to poll the response */
 368                 err = -1;
 369                 do {
 370                         ret = i40evf_read_pfmsg(dev, &info);
 371                         vf->cmd_retval = info.result;
 372                         if (ret == I40EVF_MSG_CMD) {
 373                                 err = 0;
 374                                 break;
 375                         } else if (ret == I40EVF_MSG_ERR)
 376                                 break;
 377                         rte_delay_ms(ASQ_DELAY_MS);
 378                         /* If don't read msg or read sys event, continue */
 379                 } while (i++ < MAX_TRY_TIMES);
 380                 _clear_cmd(vf);
 381                 break;
 382
 383         default:
 384                 /* for other adminq in running time, waiting the cmd done flag */
 385                 err = -1;
 386                 do {
 387                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 388                                 err = 0;
 389                                 break;
 390                         }
 391                         rte_delay_ms(ASQ_DELAY_MS);
 392                         /* If don't read msg or read sys event, continue */
 393                 } while (i++ < MAX_TRY_TIMES);
 394                 /* If there's no response is received, clear command */
 395                 if (i >= MAX_TRY_TIMES) {
 396                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 397                         _clear_cmd(vf);
 398                 }
 399                 break;
 400         }
 401
 402         return err | vf->cmd_retval;
 403 }
 404
 405 /*
 406  * Check API version with sync wait until version read or fail from admin queue
 407  */
 408 static int
 409 i40evf_check_api_version(struct rte_eth_dev *dev)
 410 {
 411         struct virtchnl_version_info version, *pver;
 412         int err;
 413         struct vf_cmd_info args;
 414         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 415
 416         version.major = VIRTCHNL_VERSION_MAJOR;
 417         version.minor = VIRTCHNL_VERSION_MINOR;
 418
 419         args.ops = VIRTCHNL_OP_VERSION;
 420         args.in_args = (uint8_t *)&version;
 421         args.in_args_size = sizeof(version);
 422         args.out_buffer = vf->aq_resp;
 423         args.out_size = I40E_AQ_BUF_SZ;
 424
 425         err = i40evf_execute_vf_cmd(dev, &args);
 426         if (err) {
 427                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 428                 return err;
 429         }
 430
 431         pver = (struct virtchnl_version_info *)args.out_buffer;
 432         vf->version_major = pver->major;
 433         vf->version_minor = pver->minor;
 434         if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 435                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 436                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 437         else {
 438                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 439                                         vf->version_major, vf->version_minor,
 440                                                 VIRTCHNL_VERSION_MAJOR,
 441                                                 VIRTCHNL_VERSION_MINOR);
 442                 return -1;
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int
 449 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 450 {
 451         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 452         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 453         int err;
 454         struct vf_cmd_info args;
 455         uint32_t caps, len;
 456
 457         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 458         args.out_buffer = vf->aq_resp;
 459         args.out_size = I40E_AQ_BUF_SZ;
 460         if (PF_IS_V11(vf)) {
 461                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 462                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 463                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 464                        VIRTCHNL_VF_OFFLOAD_VLAN |
 465                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 466                 args.in_args = (uint8_t *)&caps;
 467                 args.in_args_size = sizeof(caps);
 468         } else {
 469                 args.in_args = NULL;
 470                 args.in_args_size = 0;
 471         }
 472         err = i40evf_execute_vf_cmd(dev, &args);
 473
 474         if (err) {
 475                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 476                 return err;
 477         }
 478
 479         len =  sizeof(struct virtchnl_vf_resource) +
 480                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 481
 482         rte_memcpy(vf->vf_res, args.out_buffer,
 483                         RTE_MIN(args.out_size, len));
 484         i40e_vf_parse_hw_config(hw, vf->vf_res);
 485
 486         return 0;
 487 }
 488
 489 static int
 490 i40evf_config_promisc(struct rte_eth_dev *dev,
 491                       bool enable_unicast,
 492                       bool enable_multicast)
 493 {
 494         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 495         int err;
 496         struct vf_cmd_info args;
 497         struct virtchnl_promisc_info promisc;
 498
 499         promisc.flags = 0;
 500         promisc.vsi_id = vf->vsi_res->vsi_id;
 501
 502         if (enable_unicast)
 503                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 504
 505         if (enable_multicast)
 506                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 507
 508         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 509         args.in_args = (uint8_t *)&promisc;
 510         args.in_args_size = sizeof(promisc);
 511         args.out_buffer = vf->aq_resp;
 512         args.out_size = I40E_AQ_BUF_SZ;
 513
 514         err = i40evf_execute_vf_cmd(dev, &args);
 515
 516         if (err)
 517                 PMD_DRV_LOG(ERR, "fail to execute command "
 518                             "CONFIG_PROMISCUOUS_MODE");
 519         return err;
 520 }
 521
 522 static int
 523 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 524 {
 525         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 526         struct vf_cmd_info args;
 527         int ret;
 528
 529         memset(&args, 0, sizeof(args));
 530         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 531         args.in_args = NULL;
 532         args.in_args_size = 0;
 533         args.out_buffer = vf->aq_resp;
 534         args.out_size = I40E_AQ_BUF_SZ;
 535         ret = i40evf_execute_vf_cmd(dev, &args);
 536         if (ret)
 537                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 538                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 539
 540         return ret;
 541 }
 542
 543 static int
 544 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 545 {
 546         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 547         struct vf_cmd_info args;
 548         int ret;
 549
 550         memset(&args, 0, sizeof(args));
 551         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 552         args.in_args = NULL;
 553         args.in_args_size = 0;
 554         args.out_buffer = vf->aq_resp;
 555         args.out_size = I40E_AQ_BUF_SZ;
 556         ret = i40evf_execute_vf_cmd(dev, &args);
 557         if (ret)
 558                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 559                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 560
 561         return ret;
 562 }
 563
 564 static void
 565 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 566                                   uint16_t vsi_id,
 567                                   uint16_t queue_id,
 568                                   uint16_t nb_txq,
 569                                   struct i40e_tx_queue *txq)
 570 {
 571         txq_info->vsi_id = vsi_id;
 572         txq_info->queue_id = queue_id;
 573         if (queue_id < nb_txq) {
 574                 txq_info->ring_len = txq->nb_tx_desc;
 575                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 576         }
 577 }
 578
 579 static void
 580 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 581                                   uint16_t vsi_id,
 582                                   uint16_t queue_id,
 583                                   uint16_t nb_rxq,
 584                                   uint32_t max_pkt_size,
 585                                   struct i40e_rx_queue *rxq)
 586 {
 587         rxq_info->vsi_id = vsi_id;
 588         rxq_info->queue_id = queue_id;
 589         rxq_info->max_pkt_size = max_pkt_size;
 590         if (queue_id < nb_rxq) {
 591                 rxq_info->ring_len = rxq->nb_rx_desc;
 592                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 593                 rxq_info->databuffer_size =
 594                         (rte_pktmbuf_data_room_size(rxq->mp) -
 595                                 RTE_PKTMBUF_HEADROOM);
 596         }
 597 }
 598
 599 static int
 600 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 601 {
 602         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 603         struct i40e_rx_queue **rxq =
 604                 (struct i40e_rx_queue **)dev->data->rx_queues;
 605         struct i40e_tx_queue **txq =
 606                 (struct i40e_tx_queue **)dev->data->tx_queues;
 607         struct virtchnl_vsi_queue_config_info *vc_vqci;
 608         struct virtchnl_queue_pair_info *vc_qpi;
 609         struct vf_cmd_info args;
 610         uint16_t i, nb_qp = vf->num_queue_pairs;
 611         const uint32_t size =
 612                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 613         uint8_t buff[size];
 614         int ret;
 615
 616         memset(buff, 0, sizeof(buff));
 617         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 618         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 619         vc_vqci->num_queue_pairs = nb_qp;
 620
 621         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 622                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 623                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 624                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 625                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 626                                         vf->max_pkt_len, rxq[i]);
 627         }
 628         memset(&args, 0, sizeof(args));
 629         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 630         args.in_args = (uint8_t *)vc_vqci;
 631         args.in_args_size = size;
 632         args.out_buffer = vf->aq_resp;
 633         args.out_size = I40E_AQ_BUF_SZ;
 634         ret = i40evf_execute_vf_cmd(dev, &args);
 635         if (ret)
 636                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 637                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 638
 639         return ret;
 640 }
 641
 642 static int
 643 i40evf_config_irq_map(struct rte_eth_dev *dev)
 644 {
 645         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 646         struct vf_cmd_info args;
 647         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 648                 sizeof(struct virtchnl_vector_map)];
 649         struct virtchnl_irq_map_info *map_info;
 650         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 651         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 652         uint32_t vector_id;
 653         int i, err;
 654
 655         if (rte_intr_allow_others(intr_handle))
 656                 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 657         else
 658                 vector_id = I40E_MISC_VEC_ID;
 659
 660         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 661         map_info->num_vectors = 1;
 662         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 663         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 664         /* Alway use default dynamic MSIX interrupt */
 665         map_info->vecmap[0].vector_id = vector_id;
 666         /* Don't map any tx queue */
 667         map_info->vecmap[0].txq_map = 0;
 668         map_info->vecmap[0].rxq_map = 0;
 669         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 670                 map_info->vecmap[0].rxq_map |= 1 << i;
 671                 if (rte_intr_dp_is_en(intr_handle))
 672                         intr_handle->intr_vec[i] = vector_id;
 673         }
 674
 675         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 676         args.in_args = (u8 *)cmd_buffer;
 677         args.in_args_size = sizeof(cmd_buffer);
 678         args.out_buffer = vf->aq_resp;
 679         args.out_size = I40E_AQ_BUF_SZ;
 680         err = i40evf_execute_vf_cmd(dev, &args);
 681         if (err)
 682                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 683
 684         return err;
 685 }
 686
 687 static int
 688 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 689                                 bool on)
 690 {
 691         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 692         struct virtchnl_queue_select queue_select;
 693         int err;
 694         struct vf_cmd_info args;
 695         memset(&queue_select, 0, sizeof(queue_select));
 696         queue_select.vsi_id = vf->vsi_res->vsi_id;
 697
 698         if (isrx)
 699                 queue_select.rx_queues |= 1 << qid;
 700         else
 701                 queue_select.tx_queues |= 1 << qid;
 702
 703         if (on)
 704                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 705         else
 706                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 707         args.in_args = (u8 *)&queue_select;
 708         args.in_args_size = sizeof(queue_select);
 709         args.out_buffer = vf->aq_resp;
 710         args.out_size = I40E_AQ_BUF_SZ;
 711         err = i40evf_execute_vf_cmd(dev, &args);
 712         if (err)
 713                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 714                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 715
 716         return err;
 717 }
 718
 719 static int
 720 i40evf_start_queues(struct rte_eth_dev *dev)
 721 {
 722         struct rte_eth_dev_data *dev_data = dev->data;
 723         int i;
 724         struct i40e_rx_queue *rxq;
 725         struct i40e_tx_queue *txq;
 726
 727         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 728                 rxq = dev_data->rx_queues[i];
 729                 if (rxq->rx_deferred_start)
 730                         continue;
 731                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 732                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 733                         return -1;
 734                 }
 735         }
 736
 737         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 738                 txq = dev_data->tx_queues[i];
 739                 if (txq->tx_deferred_start)
 740                         continue;
 741                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 742                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 743                         return -1;
 744                 }
 745         }
 746
 747         return 0;
 748 }
 749
 750 static int
 751 i40evf_stop_queues(struct rte_eth_dev *dev)
 752 {
 753         int i;
 754
 755         /* Stop TX queues first */
 756         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 757                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 758                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 759                         return -1;
 760                 }
 761         }
 762
 763         /* Then stop RX queues */
 764         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 765                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 766                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 767                         return -1;
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 static int
 775 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 776                     struct ether_addr *addr,
 777                     __rte_unused uint32_t index,
 778                     __rte_unused uint32_t pool)
 779 {
 780         struct virtchnl_ether_addr_list *list;
 781         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 782         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 783                         sizeof(struct virtchnl_ether_addr)];
 784         int err;
 785         struct vf_cmd_info args;
 786
 787         if (is_zero_ether_addr(addr)) {
 788                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 789                             addr->addr_bytes[0], addr->addr_bytes[1],
 790                             addr->addr_bytes[2], addr->addr_bytes[3],
 791                             addr->addr_bytes[4], addr->addr_bytes[5]);
 792                 return I40E_ERR_INVALID_MAC_ADDR;
 793         }
 794
 795         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 796         list->vsi_id = vf->vsi_res->vsi_id;
 797         list->num_elements = 1;
 798         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 799                                         sizeof(addr->addr_bytes));
 800
 801         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 802         args.in_args = cmd_buffer;
 803         args.in_args_size = sizeof(cmd_buffer);
 804         args.out_buffer = vf->aq_resp;
 805         args.out_size = I40E_AQ_BUF_SZ;
 806         err = i40evf_execute_vf_cmd(dev, &args);
 807         if (err)
 808                 PMD_DRV_LOG(ERR, "fail to execute command "
 809                             "OP_ADD_ETHER_ADDRESS");
 810         else
 811                 vf->vsi.mac_num++;
 812
 813         return err;
 814 }
 815
 816 static void
 817 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 818                             struct ether_addr *addr)
 819 {
 820         struct virtchnl_ether_addr_list *list;
 821         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 822         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 823                         sizeof(struct virtchnl_ether_addr)];
 824         int err;
 825         struct vf_cmd_info args;
 826
 827         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 828                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 829                             addr->addr_bytes[0], addr->addr_bytes[1],
 830                             addr->addr_bytes[2], addr->addr_bytes[3],
 831                             addr->addr_bytes[4], addr->addr_bytes[5]);
 832                 return;
 833         }
 834
 835         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 836         list->vsi_id = vf->vsi_res->vsi_id;
 837         list->num_elements = 1;
 838         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 839                         sizeof(addr->addr_bytes));
 840
 841         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 842         args.in_args = cmd_buffer;
 843         args.in_args_size = sizeof(cmd_buffer);
 844         args.out_buffer = vf->aq_resp;
 845         args.out_size = I40E_AQ_BUF_SZ;
 846         err = i40evf_execute_vf_cmd(dev, &args);
 847         if (err)
 848                 PMD_DRV_LOG(ERR, "fail to execute command "
 849                             "OP_DEL_ETHER_ADDRESS");
 850         else
 851                 vf->vsi.mac_num--;
 852         return;
 853 }
 854
 855 static void
 856 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 857 {
 858         struct rte_eth_dev_data *data = dev->data;
 859         struct ether_addr *addr;
 860
 861         addr = &data->mac_addrs[index];
 862
 863         i40evf_del_mac_addr_by_addr(dev, addr);
 864 }
 865
 866 static int
 867 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 868 {
 869         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 870         struct virtchnl_queue_select q_stats;
 871         int err;
 872         struct vf_cmd_info args;
 873
 874         memset(&q_stats, 0, sizeof(q_stats));
 875         q_stats.vsi_id = vf->vsi_res->vsi_id;
 876         args.ops = VIRTCHNL_OP_GET_STATS;
 877         args.in_args = (u8 *)&q_stats;
 878         args.in_args_size = sizeof(q_stats);
 879         args.out_buffer = vf->aq_resp;
 880         args.out_size = I40E_AQ_BUF_SZ;
 881
 882         err = i40evf_execute_vf_cmd(dev, &args);
 883         if (err) {
 884                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 885                 *pstats = NULL;
 886                 return err;
 887         }
 888         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 889         return 0;
 890 }
 891
 892 static void
 893 i40evf_stat_update_48(uint64_t *offset,
 894                    uint64_t *stat)
 895 {
 896         if (*stat >= *offset)
 897                 *stat = *stat - *offset;
 898         else
 899                 *stat = (uint64_t)((*stat +
 900                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
 901
 902         *stat &= I40E_48_BIT_MASK;
 903 }
 904
 905 static void
 906 i40evf_stat_update_32(uint64_t *offset,
 907                    uint64_t *stat)
 908 {
 909         if (*stat >= *offset)
 910                 *stat = (uint64_t)(*stat - *offset);
 911         else
 912                 *stat = (uint64_t)((*stat +
 913                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
 914 }
 915
 916 static void
 917 i40evf_update_stats(struct i40e_vsi *vsi,
 918                                         struct i40e_eth_stats *nes)
 919 {
 920         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 921
 922         i40evf_stat_update_48(&oes->rx_bytes,
 923                             &nes->rx_bytes);
 924         i40evf_stat_update_48(&oes->rx_unicast,
 925                             &nes->rx_unicast);
 926         i40evf_stat_update_48(&oes->rx_multicast,
 927                             &nes->rx_multicast);
 928         i40evf_stat_update_48(&oes->rx_broadcast,
 929                             &nes->rx_broadcast);
 930         i40evf_stat_update_32(&oes->rx_discards,
 931                                 &nes->rx_discards);
 932         i40evf_stat_update_32(&oes->rx_unknown_protocol,
 933                             &nes->rx_unknown_protocol);
 934         i40evf_stat_update_48(&oes->tx_bytes,
 935                             &nes->tx_bytes);
 936         i40evf_stat_update_48(&oes->tx_unicast,
 937                             &nes->tx_unicast);
 938         i40evf_stat_update_48(&oes->tx_multicast,
 939                             &nes->tx_multicast);
 940         i40evf_stat_update_48(&oes->tx_broadcast,
 941                             &nes->tx_broadcast);
 942         i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
 943         i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
 944 }
 945
 946 static void
 947 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 948 {
 949         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 950         struct i40e_eth_stats *pstats = NULL;
 951
 952         /* read stat values to clear hardware registers */
 953         i40evf_query_stats(dev, &pstats);
 954
 955         /* set stats offset base on current values */
 956         vf->vsi.eth_stats_offset = *pstats;
 957 }
 958
 959 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 960                                       struct rte_eth_xstat_name *xstats_names,
 961                                       __rte_unused unsigned limit)
 962 {
 963         unsigned i;
 964
 965         if (xstats_names != NULL)
 966                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 967                         snprintf(xstats_names[i].name,
 968                                 sizeof(xstats_names[i].name),
 969                                 "%s", rte_i40evf_stats_strings[i].name);
 970                 }
 971         return I40EVF_NB_XSTATS;
 972 }
 973
 974 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 975                                  struct rte_eth_xstat *xstats, unsigned n)
 976 {
 977         int ret;
 978         unsigned i;
 979         struct i40e_eth_stats *pstats = NULL;
 980         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 981         struct i40e_vsi *vsi = &vf->vsi;
 982
 983         if (n < I40EVF_NB_XSTATS)
 984                 return I40EVF_NB_XSTATS;
 985
 986         ret = i40evf_query_stats(dev, &pstats);
 987         if (ret != 0)
 988                 return 0;
 989
 990         if (!xstats)
 991                 return 0;
 992
 993         i40evf_update_stats(vsi, pstats);
 994
 995         /* loop over xstats array and values from pstats */
 996         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 997                 xstats[i].id = i;
 998                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
 999                         rte_i40evf_stats_strings[i].offset);
1000         }
1001
1002         return I40EVF_NB_XSTATS;
1003 }
1004
1005 static int
1006 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1007 {
1008         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1009         struct virtchnl_vlan_filter_list *vlan_list;
1010         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1011                                                         sizeof(uint16_t)];
1012         int err;
1013         struct vf_cmd_info args;
1014
1015         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1016         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1017         vlan_list->num_elements = 1;
1018         vlan_list->vlan_id[0] = vlanid;
1019
1020         args.ops = VIRTCHNL_OP_ADD_VLAN;
1021         args.in_args = (u8 *)&cmd_buffer;
1022         args.in_args_size = sizeof(cmd_buffer);
1023         args.out_buffer = vf->aq_resp;
1024         args.out_size = I40E_AQ_BUF_SZ;
1025         err = i40evf_execute_vf_cmd(dev, &args);
1026         if (err)
1027                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1028
1029         return err;
1030 }
1031
1032 static int
1033 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1034 {
1035         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1036         struct virtchnl_vlan_filter_list *vlan_list;
1037         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1038                                                         sizeof(uint16_t)];
1039         int err;
1040         struct vf_cmd_info args;
1041
1042         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1043         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1044         vlan_list->num_elements = 1;
1045         vlan_list->vlan_id[0] = vlanid;
1046
1047         args.ops = VIRTCHNL_OP_DEL_VLAN;
1048         args.in_args = (u8 *)&cmd_buffer;
1049         args.in_args_size = sizeof(cmd_buffer);
1050         args.out_buffer = vf->aq_resp;
1051         args.out_size = I40E_AQ_BUF_SZ;
1052         err = i40evf_execute_vf_cmd(dev, &args);
1053         if (err)
1054                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1055
1056         return err;
1057 }
1058
1059 static const struct rte_pci_id pci_id_i40evf_map[] = {
1060         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1061         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1062         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1063         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1064         { .vendor_id = 0, /* sentinel */ },
1065 };
1066
1067 static inline int
1068 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1069                                     struct rte_eth_link *link)
1070 {
1071         struct rte_eth_link *dst = &(dev->data->dev_link);
1072         struct rte_eth_link *src = link;
1073
1074         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1075                                         *(uint64_t *)src) == 0)
1076                 return -1;
1077
1078         return 0;
1079 }
1080
1081 /* Disable IRQ0 */
1082 static inline void
1083 i40evf_disable_irq0(struct i40e_hw *hw)
1084 {
1085         /* Disable all interrupt types */
1086         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1087         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1088                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1089         I40EVF_WRITE_FLUSH(hw);
1090 }
1091
1092 /* Enable IRQ0 */
1093 static inline void
1094 i40evf_enable_irq0(struct i40e_hw *hw)
1095 {
1096         /* Enable admin queue interrupt trigger */
1097         uint32_t val;
1098
1099         i40evf_disable_irq0(hw);
1100         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1101         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1102                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1103         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1104
1105         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1106                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1107                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1108                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1109
1110         I40EVF_WRITE_FLUSH(hw);
1111 }
1112
1113 static int
1114 i40evf_check_vf_reset_done(struct i40e_hw *hw)
1115 {
1116         int i, reset;
1117
1118         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1119                 reset = I40E_READ_REG(hw, I40E_VFGEN_RSTAT) &
1120                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1121                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1122                 if (reset == VIRTCHNL_VFR_VFACTIVE ||
1123                     reset == VIRTCHNL_VFR_COMPLETED)
1124                         break;
1125                 rte_delay_ms(50);
1126         }
1127
1128         if (i >= MAX_RESET_WAIT_CNT)
1129                 return -1;
1130
1131         return 0;
1132 }
1133 static int
1134 i40evf_reset_vf(struct i40e_hw *hw)
1135 {
1136         int ret;
1137
1138         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1139                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1140                 return -1;
1141         }
1142         /**
1143           * After issuing vf reset command to pf, pf won't necessarily
1144           * reset vf, it depends on what state it exactly is. If it's not
1145           * initialized yet, it won't have vf reset since it's in a certain
1146           * state. If not, it will try to reset. Even vf is reset, pf will
1147           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1148           * it to ACTIVE. In this duration, vf may not catch the moment that
1149           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1150           */
1151         rte_delay_ms(200);
1152
1153         ret = i40evf_check_vf_reset_done(hw);
1154         if (ret) {
1155                 PMD_INIT_LOG(ERR, "VF is still resetting");
1156                 return ret;
1157         }
1158
1159         return 0;
1160 }
1161
1162 static int
1163 i40evf_init_vf(struct rte_eth_dev *dev)
1164 {
1165         int i, err, bufsz;
1166         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1167         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1168         uint16_t interval =
1169                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1170
1171         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1172         vf->dev_data = dev->data;
1173         err = i40e_set_mac_type(hw);
1174         if (err) {
1175                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1176                 goto err;
1177         }
1178
1179         err = i40evf_check_vf_reset_done(hw);
1180         if (err)
1181                 goto err;
1182
1183         i40e_init_adminq_parameter(hw);
1184         err = i40e_init_adminq(hw);
1185         if (err) {
1186                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1187                 goto err;
1188         }
1189
1190         /* Reset VF and wait until it's complete */
1191         if (i40evf_reset_vf(hw)) {
1192                 PMD_INIT_LOG(ERR, "reset NIC failed");
1193                 goto err_aq;
1194         }
1195
1196         /* VF reset, shutdown admin queue and initialize again */
1197         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1198                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1199                 goto err;
1200         }
1201
1202         i40e_init_adminq_parameter(hw);
1203         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1204                 PMD_INIT_LOG(ERR, "init_adminq failed");
1205                 goto err;
1206         }
1207
1208         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1209         if (!vf->aq_resp) {
1210                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1211                 goto err_aq;
1212         }
1213         if (i40evf_check_api_version(dev) != 0) {
1214                 PMD_INIT_LOG(ERR, "check_api version failed");
1215                 goto err_api;
1216         }
1217         bufsz = sizeof(struct virtchnl_vf_resource) +
1218                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1219         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1220         if (!vf->vf_res) {
1221                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1222                 goto err_api;
1223         }
1224
1225         if (i40evf_get_vf_resource(dev) != 0) {
1226                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1227                 goto err_alloc;
1228         }
1229
1230         /* got VF config message back from PF, now we can parse it */
1231         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1232                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1233                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1234         }
1235
1236         if (!vf->vsi_res) {
1237                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1238                 goto err_alloc;
1239         }
1240
1241         if (hw->mac.type == I40E_MAC_X722_VF)
1242                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1243         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1244
1245         switch (vf->vsi_res->vsi_type) {
1246         case VIRTCHNL_VSI_SRIOV:
1247                 vf->vsi.type = I40E_VSI_SRIOV;
1248                 break;
1249         default:
1250                 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1251                 break;
1252         }
1253         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1254         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1255
1256         /* Store the MAC address configured by host, or generate random one */
1257         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1258                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1259         else
1260                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1261
1262         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1263                        (I40E_ITR_INDEX_DEFAULT <<
1264                         I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1265                        (interval <<
1266                         I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1267         I40EVF_WRITE_FLUSH(hw);
1268
1269         return 0;
1270
1271 err_alloc:
1272         rte_free(vf->vf_res);
1273         vf->vsi_res = NULL;
1274 err_api:
1275         rte_free(vf->aq_resp);
1276 err_aq:
1277         i40e_shutdown_adminq(hw); /* ignore error */
1278 err:
1279         return -1;
1280 }
1281
1282 static int
1283 i40evf_uninit_vf(struct rte_eth_dev *dev)
1284 {
1285         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1286         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1287
1288         PMD_INIT_FUNC_TRACE();
1289
1290         if (hw->adapter_stopped == 0)
1291                 i40evf_dev_close(dev);
1292         rte_free(vf->vf_res);
1293         vf->vf_res = NULL;
1294         rte_free(vf->aq_resp);
1295         vf->aq_resp = NULL;
1296
1297         return 0;
1298 }
1299
1300 static void
1301 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1302                 __rte_unused uint16_t msglen)
1303 {
1304         struct virtchnl_pf_event *pf_msg =
1305                         (struct virtchnl_pf_event *)msg;
1306         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1307
1308         switch (pf_msg->event) {
1309         case VIRTCHNL_EVENT_RESET_IMPENDING:
1310                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1311                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1312                                               NULL, NULL);
1313                 break;
1314         case VIRTCHNL_EVENT_LINK_CHANGE:
1315                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1316                 vf->link_up = pf_msg->event_data.link_event.link_status;
1317                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1318                 break;
1319         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1320                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1321                 break;
1322         default:
1323                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1324                 break;
1325         }
1326 }
1327
1328 static void
1329 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1330 {
1331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1332         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1333         struct i40e_arq_event_info info;
1334         uint16_t pending, aq_opc;
1335         enum virtchnl_ops msg_opc;
1336         enum i40e_status_code msg_ret;
1337         int ret;
1338
1339         info.buf_len = I40E_AQ_BUF_SZ;
1340         if (!vf->aq_resp) {
1341                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1342                 return;
1343         }
1344         info.msg_buf = vf->aq_resp;
1345
1346         pending = 1;
1347         while (pending) {
1348                 ret = i40e_clean_arq_element(hw, &info, &pending);
1349
1350                 if (ret != I40E_SUCCESS) {
1351                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1352                                     "ret: %d", ret);
1353                         break;
1354                 }
1355                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1356                 /* For the message sent from pf to vf, opcode is stored in
1357                  * cookie_high of struct i40e_aq_desc, while return error code
1358                  * are stored in cookie_low, Which is done by
1359                  * i40e_aq_send_msg_to_vf in PF driver.*/
1360                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1361                                                   info.desc.cookie_high);
1362                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1363                                                   info.desc.cookie_low);
1364                 switch (aq_opc) {
1365                 case i40e_aqc_opc_send_msg_to_vf:
1366                         if (msg_opc == VIRTCHNL_OP_EVENT)
1367                                 /* process event*/
1368                                 i40evf_handle_pf_event(dev, info.msg_buf,
1369                                                        info.msg_len);
1370                         else {
1371                                 /* read message and it's expected one */
1372                                 if (msg_opc == vf->pend_cmd) {
1373                                         vf->cmd_retval = msg_ret;
1374                                         /* prevent compiler reordering */
1375                                         rte_compiler_barrier();
1376                                         _clear_cmd(vf);
1377                                 } else
1378                                         PMD_DRV_LOG(ERR, "command mismatch,"
1379                                                 "expect %u, get %u",
1380                                                 vf->pend_cmd, msg_opc);
1381                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1382                                              " opcode = %d", msg_opc);
1383                         }
1384                         break;
1385                 default:
1386                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1387                                     aq_opc);
1388                         break;
1389                 }
1390         }
1391 }
1392
1393 /**
1394  * Interrupt handler triggered by NIC  for handling
1395  * specific interrupt. Only adminq interrupt is processed in VF.
1396  *
1397  * @param handle
1398  *  Pointer to interrupt handle.
1399  * @param param
1400  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1401  *
1402  * @return
1403  *  void
1404  */
1405 static void
1406 i40evf_dev_interrupt_handler(void *param)
1407 {
1408         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1409         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1410         uint32_t icr0;
1411
1412         i40evf_disable_irq0(hw);
1413
1414         /* read out interrupt causes */
1415         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1416
1417         /* No interrupt event indicated */
1418         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1419                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1420                 goto done;
1421         }
1422
1423         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1424                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1425                 i40evf_handle_aq_msg(dev);
1426         }
1427
1428         /* Link Status Change interrupt */
1429         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1430                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1431                                    " do nothing");
1432
1433 done:
1434         i40evf_enable_irq0(hw);
1435         rte_intr_enable(dev->intr_handle);
1436 }
1437
1438 static int
1439 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1440 {
1441         struct i40e_hw *hw
1442                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1443         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1444
1445         PMD_INIT_FUNC_TRACE();
1446
1447         /* assign ops func pointer */
1448         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1449         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1450         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1451
1452         /*
1453          * For secondary processes, we don't initialise any further as primary
1454          * has already done this work.
1455          */
1456         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1457                 i40e_set_rx_function(eth_dev);
1458                 i40e_set_tx_function(eth_dev);
1459                 return 0;
1460         }
1461         i40e_set_default_ptype_table(eth_dev);
1462         i40e_set_default_pctype_table(eth_dev);
1463         rte_eth_copy_pci_info(eth_dev, pci_dev);
1464
1465         hw->vendor_id = pci_dev->id.vendor_id;
1466         hw->device_id = pci_dev->id.device_id;
1467         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1468         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1469         hw->bus.device = pci_dev->addr.devid;
1470         hw->bus.func = pci_dev->addr.function;
1471         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1472         hw->adapter_stopped = 0;
1473
1474         if(i40evf_init_vf(eth_dev) != 0) {
1475                 PMD_INIT_LOG(ERR, "Init vf failed");
1476                 return -1;
1477         }
1478
1479         /* register callback func to eal lib */
1480         rte_intr_callback_register(&pci_dev->intr_handle,
1481                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1482
1483         /* enable uio intr after callback register */
1484         rte_intr_enable(&pci_dev->intr_handle);
1485
1486         /* configure and enable device interrupt */
1487         i40evf_enable_irq0(hw);
1488
1489         /* copy mac addr */
1490         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1491                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1492                                         0);
1493         if (eth_dev->data->mac_addrs == NULL) {
1494                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1495                                 " store MAC addresses",
1496                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1497                 return -ENOMEM;
1498         }
1499         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1500                         &eth_dev->data->mac_addrs[0]);
1501
1502         return 0;
1503 }
1504
1505 static int
1506 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1507 {
1508         PMD_INIT_FUNC_TRACE();
1509
1510         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1511                 return -EPERM;
1512
1513         eth_dev->dev_ops = NULL;
1514         eth_dev->rx_pkt_burst = NULL;
1515         eth_dev->tx_pkt_burst = NULL;
1516
1517         if (i40evf_uninit_vf(eth_dev) != 0) {
1518                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1519                 return -1;
1520         }
1521
1522         rte_free(eth_dev->data->mac_addrs);
1523         eth_dev->data->mac_addrs = NULL;
1524
1525         return 0;
1526 }
1527
1528 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1529         struct rte_pci_device *pci_dev)
1530 {
1531         return rte_eth_dev_pci_generic_probe(pci_dev,
1532                 sizeof(struct i40e_adapter), i40evf_dev_init);
1533 }
1534
1535 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1536 {
1537         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1538 }
1539
1540 /*
1541  * virtual function driver struct
1542  */
1543 static struct rte_pci_driver rte_i40evf_pmd = {
1544         .id_table = pci_id_i40evf_map,
1545         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1546         .probe = eth_i40evf_pci_probe,
1547         .remove = eth_i40evf_pci_remove,
1548 };
1549
1550 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1551 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1552 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1553
1554 static int
1555 i40evf_dev_configure(struct rte_eth_dev *dev)
1556 {
1557         struct i40e_adapter *ad =
1558                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1559         struct rte_eth_conf *conf = &dev->data->dev_conf;
1560         struct i40e_vf *vf;
1561
1562         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1563          * allocation or vector Rx preconditions we will reset it.
1564          */
1565         ad->rx_bulk_alloc_allowed = true;
1566         ad->rx_vec_allowed = true;
1567         ad->tx_simple_allowed = true;
1568         ad->tx_vec_allowed = true;
1569
1570         /* For non-DPDK PF drivers, VF has no ability to disable HW
1571          * CRC strip, and is implicitly enabled by the PF.
1572          */
1573         if (!conf->rxmode.hw_strip_crc) {
1574                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1575                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1576                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1577                         /* Peer is running non-DPDK PF driver. */
1578                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1579                         return -EINVAL;
1580                 }
1581         }
1582
1583         return i40evf_init_vlan(dev);
1584 }
1585
1586 static int
1587 i40evf_init_vlan(struct rte_eth_dev *dev)
1588 {
1589         /* Apply vlan offload setting */
1590         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1591
1592         return I40E_SUCCESS;
1593 }
1594
1595 static void
1596 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1597 {
1598         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1599
1600         /* Vlan stripping setting */
1601         if (mask & ETH_VLAN_STRIP_MASK) {
1602                 /* Enable or disable VLAN stripping */
1603                 if (dev_conf->rxmode.hw_vlan_strip)
1604                         i40evf_enable_vlan_strip(dev);
1605                 else
1606                         i40evf_disable_vlan_strip(dev);
1607         }
1608 }
1609
1610 static int
1611 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1612 {
1613         struct i40e_rx_queue *rxq;
1614         int err = 0;
1615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1616
1617         PMD_INIT_FUNC_TRACE();
1618
1619         if (rx_queue_id < dev->data->nb_rx_queues) {
1620                 rxq = dev->data->rx_queues[rx_queue_id];
1621
1622                 err = i40e_alloc_rx_queue_mbufs(rxq);
1623                 if (err) {
1624                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1625                         return err;
1626                 }
1627
1628                 rte_wmb();
1629
1630                 /* Init the RX tail register. */
1631                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1632                 I40EVF_WRITE_FLUSH(hw);
1633
1634                 /* Ready to switch the queue on */
1635                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1636
1637                 if (err)
1638                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1639                                     rx_queue_id);
1640                 else
1641                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1642         }
1643
1644         return err;
1645 }
1646
1647 static int
1648 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1649 {
1650         struct i40e_rx_queue *rxq;
1651         int err;
1652
1653         if (rx_queue_id < dev->data->nb_rx_queues) {
1654                 rxq = dev->data->rx_queues[rx_queue_id];
1655
1656                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1657
1658                 if (err) {
1659                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1660                                     rx_queue_id);
1661                         return err;
1662                 }
1663
1664                 i40e_rx_queue_release_mbufs(rxq);
1665                 i40e_reset_rx_queue(rxq);
1666                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1667         }
1668
1669         return 0;
1670 }
1671
1672 static int
1673 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1674 {
1675         int err = 0;
1676
1677         PMD_INIT_FUNC_TRACE();
1678
1679         if (tx_queue_id < dev->data->nb_tx_queues) {
1680
1681                 /* Ready to switch the queue on */
1682                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1683
1684                 if (err)
1685                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1686                                     tx_queue_id);
1687                 else
1688                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1689         }
1690
1691         return err;
1692 }
1693
1694 static int
1695 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1696 {
1697         struct i40e_tx_queue *txq;
1698         int err;
1699
1700         if (tx_queue_id < dev->data->nb_tx_queues) {
1701                 txq = dev->data->tx_queues[tx_queue_id];
1702
1703                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1704
1705                 if (err) {
1706                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1707                                     tx_queue_id);
1708                         return err;
1709                 }
1710
1711                 i40e_tx_queue_release_mbufs(txq);
1712                 i40e_reset_tx_queue(txq);
1713                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1714         }
1715
1716         return 0;
1717 }
1718
1719 static int
1720 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1721 {
1722         int ret;
1723
1724         if (on)
1725                 ret = i40evf_add_vlan(dev, vlan_id);
1726         else
1727                 ret = i40evf_del_vlan(dev,vlan_id);
1728
1729         return ret;
1730 }
1731
1732 static int
1733 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1734 {
1735         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1736         struct rte_eth_dev_data *dev_data = dev->data;
1737         struct rte_pktmbuf_pool_private *mbp_priv;
1738         uint16_t buf_size, len;
1739
1740         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1741         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1742         I40EVF_WRITE_FLUSH(hw);
1743
1744         /* Calculate the maximum packet length allowed */
1745         mbp_priv = rte_mempool_get_priv(rxq->mp);
1746         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1747                                         RTE_PKTMBUF_HEADROOM);
1748         rxq->hs_mode = i40e_header_split_none;
1749         rxq->rx_hdr_len = 0;
1750         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1751         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1752         rxq->max_pkt_len = RTE_MIN(len,
1753                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1754
1755         /**
1756          * Check if the jumbo frame and maximum packet length are set correctly
1757          */
1758         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1759                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1760                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1761                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1762                                 "larger than %u and smaller than %u, as jumbo "
1763                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1764                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1765                         return I40E_ERR_CONFIG;
1766                 }
1767         } else {
1768                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1769                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1770                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1771                                 "larger than %u and smaller than %u, as jumbo "
1772                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1773                                                 (uint32_t)ETHER_MAX_LEN);
1774                         return I40E_ERR_CONFIG;
1775                 }
1776         }
1777
1778         if (dev_data->dev_conf.rxmode.enable_scatter ||
1779             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1780                 dev_data->scattered_rx = 1;
1781         }
1782
1783         return 0;
1784 }
1785
1786 static int
1787 i40evf_rx_init(struct rte_eth_dev *dev)
1788 {
1789         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1790         uint16_t i;
1791         int ret = I40E_SUCCESS;
1792         struct i40e_rx_queue **rxq =
1793                 (struct i40e_rx_queue **)dev->data->rx_queues;
1794
1795         i40evf_config_rss(vf);
1796         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1797                 if (!rxq[i] || !rxq[i]->q_set)
1798                         continue;
1799                 ret = i40evf_rxq_init(dev, rxq[i]);
1800                 if (ret != I40E_SUCCESS)
1801                         break;
1802         }
1803         if (ret == I40E_SUCCESS)
1804                 i40e_set_rx_function(dev);
1805
1806         return ret;
1807 }
1808
1809 static void
1810 i40evf_tx_init(struct rte_eth_dev *dev)
1811 {
1812         uint16_t i;
1813         struct i40e_tx_queue **txq =
1814                 (struct i40e_tx_queue **)dev->data->tx_queues;
1815         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1816
1817         for (i = 0; i < dev->data->nb_tx_queues; i++)
1818                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1819
1820         i40e_set_tx_function(dev);
1821 }
1822
1823 static inline void
1824 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1825 {
1826         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1827         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1828         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1829
1830         if (!rte_intr_allow_others(intr_handle)) {
1831                 I40E_WRITE_REG(hw,
1832                                I40E_VFINT_DYN_CTL01,
1833                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1834                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1835                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1836                 I40EVF_WRITE_FLUSH(hw);
1837                 return;
1838         }
1839
1840         I40EVF_WRITE_FLUSH(hw);
1841 }
1842
1843 static inline void
1844 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1845 {
1846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1848         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1849
1850         if (!rte_intr_allow_others(intr_handle)) {
1851                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1852                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1853                 I40EVF_WRITE_FLUSH(hw);
1854                 return;
1855         }
1856
1857         I40EVF_WRITE_FLUSH(hw);
1858 }
1859
1860 static int
1861 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1862 {
1863         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1864         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1865         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866         uint16_t interval =
1867                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1868         uint16_t msix_intr;
1869
1870         msix_intr = intr_handle->intr_vec[queue_id];
1871         if (msix_intr == I40E_MISC_VEC_ID)
1872                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1873                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1874                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1875                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1876                                (interval <<
1877                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1878         else
1879                 I40E_WRITE_REG(hw,
1880                                I40E_VFINT_DYN_CTLN1(msix_intr -
1881                                                     I40E_RX_VEC_START),
1882                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1883                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1884                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1885                                (interval <<
1886                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1887
1888         I40EVF_WRITE_FLUSH(hw);
1889
1890         rte_intr_enable(&pci_dev->intr_handle);
1891
1892         return 0;
1893 }
1894
1895 static int
1896 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1897 {
1898         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1899         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1900         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1901         uint16_t msix_intr;
1902
1903         msix_intr = intr_handle->intr_vec[queue_id];
1904         if (msix_intr == I40E_MISC_VEC_ID)
1905                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1906         else
1907                 I40E_WRITE_REG(hw,
1908                                I40E_VFINT_DYN_CTLN1(msix_intr -
1909                                                     I40E_RX_VEC_START),
1910                                0);
1911
1912         I40EVF_WRITE_FLUSH(hw);
1913
1914         return 0;
1915 }
1916
1917 static void
1918 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1919 {
1920         struct virtchnl_ether_addr_list *list;
1921         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1922         int err, i, j;
1923         int next_begin = 0;
1924         int begin = 0;
1925         uint32_t len;
1926         struct ether_addr *addr;
1927         struct vf_cmd_info args;
1928
1929         do {
1930                 j = 0;
1931                 len = sizeof(struct virtchnl_ether_addr_list);
1932                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1933                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1934                                 continue;
1935                         len += sizeof(struct virtchnl_ether_addr);
1936                         if (len >= I40E_AQ_BUF_SZ) {
1937                                 next_begin = i + 1;
1938                                 break;
1939                         }
1940                 }
1941
1942                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1943                 if (!list) {
1944                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1945                         return;
1946                 }
1947
1948                 for (i = begin; i < next_begin; i++) {
1949                         addr = &dev->data->mac_addrs[i];
1950                         if (is_zero_ether_addr(addr))
1951                                 continue;
1952                         rte_memcpy(list->list[j].addr, addr->addr_bytes,
1953                                          sizeof(addr->addr_bytes));
1954                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1955                                     addr->addr_bytes[0], addr->addr_bytes[1],
1956                                     addr->addr_bytes[2], addr->addr_bytes[3],
1957                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1958                         j++;
1959                 }
1960                 list->vsi_id = vf->vsi_res->vsi_id;
1961                 list->num_elements = j;
1962                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1963                            VIRTCHNL_OP_DEL_ETH_ADDR;
1964                 args.in_args = (uint8_t *)list;
1965                 args.in_args_size = len;
1966                 args.out_buffer = vf->aq_resp;
1967                 args.out_size = I40E_AQ_BUF_SZ;
1968                 err = i40evf_execute_vf_cmd(dev, &args);
1969                 if (err) {
1970                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1971                                     add ? "OP_ADD_ETHER_ADDRESS" :
1972                                     "OP_DEL_ETHER_ADDRESS");
1973                 } else {
1974                         if (add)
1975                                 vf->vsi.mac_num++;
1976                         else
1977                                 vf->vsi.mac_num--;
1978                 }
1979                 rte_free(list);
1980                 begin = next_begin;
1981         } while (begin < I40E_NUM_MACADDR_MAX);
1982 }
1983
1984 static int
1985 i40evf_dev_start(struct rte_eth_dev *dev)
1986 {
1987         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1988         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1989         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1990         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1991         uint32_t intr_vector = 0;
1992
1993         PMD_INIT_FUNC_TRACE();
1994
1995         hw->adapter_stopped = 0;
1996
1997         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1998         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1999                                         dev->data->nb_tx_queues);
2000
2001         /* check and configure queue intr-vector mapping */
2002         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2003                 intr_vector = dev->data->nb_rx_queues;
2004                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2005                         return -1;
2006         }
2007
2008         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2009                 intr_handle->intr_vec =
2010                         rte_zmalloc("intr_vec",
2011                                     dev->data->nb_rx_queues * sizeof(int), 0);
2012                 if (!intr_handle->intr_vec) {
2013                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2014                                      " intr_vec", dev->data->nb_rx_queues);
2015                         return -ENOMEM;
2016                 }
2017         }
2018
2019         if (i40evf_rx_init(dev) != 0){
2020                 PMD_DRV_LOG(ERR, "failed to do RX init");
2021                 return -1;
2022         }
2023
2024         i40evf_tx_init(dev);
2025
2026         if (i40evf_configure_vsi_queues(dev) != 0) {
2027                 PMD_DRV_LOG(ERR, "configure queues failed");
2028                 goto err_queue;
2029         }
2030         if (i40evf_config_irq_map(dev)) {
2031                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2032                 goto err_queue;
2033         }
2034
2035         /* Set all mac addrs */
2036         i40evf_add_del_all_mac_addr(dev, TRUE);
2037
2038         if (i40evf_start_queues(dev) != 0) {
2039                 PMD_DRV_LOG(ERR, "enable queues failed");
2040                 goto err_mac;
2041         }
2042
2043         i40evf_enable_queues_intr(dev);
2044         return 0;
2045
2046 err_mac:
2047         i40evf_add_del_all_mac_addr(dev, FALSE);
2048 err_queue:
2049         return -1;
2050 }
2051
2052 static void
2053 i40evf_dev_stop(struct rte_eth_dev *dev)
2054 {
2055         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2056         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2057         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2058
2059         PMD_INIT_FUNC_TRACE();
2060
2061         if (hw->adapter_stopped == 1)
2062                 return;
2063         i40evf_stop_queues(dev);
2064         i40evf_disable_queues_intr(dev);
2065         i40e_dev_clear_queues(dev);
2066
2067         /* Clean datapath event and queue/vec mapping */
2068         rte_intr_efd_disable(intr_handle);
2069         if (intr_handle->intr_vec) {
2070                 rte_free(intr_handle->intr_vec);
2071                 intr_handle->intr_vec = NULL;
2072         }
2073         /* remove all mac addrs */
2074         i40evf_add_del_all_mac_addr(dev, FALSE);
2075         hw->adapter_stopped = 1;
2076
2077 }
2078
2079 static int
2080 i40evf_dev_link_update(struct rte_eth_dev *dev,
2081                        __rte_unused int wait_to_complete)
2082 {
2083         struct rte_eth_link new_link;
2084         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2085         /*
2086          * DPDK pf host provide interfacet to acquire link status
2087          * while Linux driver does not
2088          */
2089
2090         /* Linux driver PF host */
2091         switch (vf->link_speed) {
2092         case I40E_LINK_SPEED_100MB:
2093                 new_link.link_speed = ETH_SPEED_NUM_100M;
2094                 break;
2095         case I40E_LINK_SPEED_1GB:
2096                 new_link.link_speed = ETH_SPEED_NUM_1G;
2097                 break;
2098         case I40E_LINK_SPEED_10GB:
2099                 new_link.link_speed = ETH_SPEED_NUM_10G;
2100                 break;
2101         case I40E_LINK_SPEED_20GB:
2102                 new_link.link_speed = ETH_SPEED_NUM_20G;
2103                 break;
2104         case I40E_LINK_SPEED_25GB:
2105                 new_link.link_speed = ETH_SPEED_NUM_25G;
2106                 break;
2107         case I40E_LINK_SPEED_40GB:
2108                 new_link.link_speed = ETH_SPEED_NUM_40G;
2109                 break;
2110         default:
2111                 new_link.link_speed = ETH_SPEED_NUM_100M;
2112                 break;
2113         }
2114         /* full duplex only */
2115         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2116         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2117                                              ETH_LINK_DOWN;
2118         new_link.link_autoneg =
2119                 dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED;
2120
2121         i40evf_dev_atomic_write_link_status(dev, &new_link);
2122
2123         return 0;
2124 }
2125
2126 static void
2127 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2128 {
2129         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2130         int ret;
2131
2132         /* If enabled, just return */
2133         if (vf->promisc_unicast_enabled)
2134                 return;
2135
2136         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2137         if (ret == 0)
2138                 vf->promisc_unicast_enabled = TRUE;
2139 }
2140
2141 static void
2142 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2143 {
2144         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2145         int ret;
2146
2147         /* If disabled, just return */
2148         if (!vf->promisc_unicast_enabled)
2149                 return;
2150
2151         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2152         if (ret == 0)
2153                 vf->promisc_unicast_enabled = FALSE;
2154 }
2155
2156 static void
2157 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2158 {
2159         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2160         int ret;
2161
2162         /* If enabled, just return */
2163         if (vf->promisc_multicast_enabled)
2164                 return;
2165
2166         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2167         if (ret == 0)
2168                 vf->promisc_multicast_enabled = TRUE;
2169 }
2170
2171 static void
2172 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2173 {
2174         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2175         int ret;
2176
2177         /* If enabled, just return */
2178         if (!vf->promisc_multicast_enabled)
2179                 return;
2180
2181         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2182         if (ret == 0)
2183                 vf->promisc_multicast_enabled = FALSE;
2184 }
2185
2186 static void
2187 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2188 {
2189         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2190
2191         memset(dev_info, 0, sizeof(*dev_info));
2192         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2193         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2194         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2195         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2196         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2197         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2198         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2199         dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2200         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2201         dev_info->rx_offload_capa =
2202                 DEV_RX_OFFLOAD_VLAN_STRIP |
2203                 DEV_RX_OFFLOAD_QINQ_STRIP |
2204                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2205                 DEV_RX_OFFLOAD_UDP_CKSUM |
2206                 DEV_RX_OFFLOAD_TCP_CKSUM;
2207         dev_info->tx_offload_capa =
2208                 DEV_TX_OFFLOAD_VLAN_INSERT |
2209                 DEV_TX_OFFLOAD_QINQ_INSERT |
2210                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2211                 DEV_TX_OFFLOAD_UDP_CKSUM |
2212                 DEV_TX_OFFLOAD_TCP_CKSUM |
2213                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2214
2215         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2216                 .rx_thresh = {
2217                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2218                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2219                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2220                 },
2221                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2222                 .rx_drop_en = 0,
2223         };
2224
2225         dev_info->default_txconf = (struct rte_eth_txconf) {
2226                 .tx_thresh = {
2227                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2228                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2229                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2230                 },
2231                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2232                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2233                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2234                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2235         };
2236
2237         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2238                 .nb_max = I40E_MAX_RING_DESC,
2239                 .nb_min = I40E_MIN_RING_DESC,
2240                 .nb_align = I40E_ALIGN_RING_DESC,
2241         };
2242
2243         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2244                 .nb_max = I40E_MAX_RING_DESC,
2245                 .nb_min = I40E_MIN_RING_DESC,
2246                 .nb_align = I40E_ALIGN_RING_DESC,
2247         };
2248 }
2249
2250 static int
2251 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2252 {
2253         int ret;
2254         struct i40e_eth_stats *pstats = NULL;
2255         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2256         struct i40e_vsi *vsi = &vf->vsi;
2257
2258         ret = i40evf_query_stats(dev, &pstats);
2259         if (ret == 0) {
2260                 i40evf_update_stats(vsi, pstats);
2261
2262                 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2263                                                 pstats->rx_broadcast;
2264                 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2265                                                 pstats->tx_unicast;
2266                 stats->imissed = pstats->rx_discards;
2267                 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2268                 stats->ibytes = pstats->rx_bytes;
2269                 stats->obytes = pstats->tx_bytes;
2270         } else {
2271                 PMD_DRV_LOG(ERR, "Get statistics failed");
2272         }
2273         return ret;
2274 }
2275
2276 static void
2277 i40evf_dev_close(struct rte_eth_dev *dev)
2278 {
2279         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2280         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2281         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2282
2283         i40evf_dev_stop(dev);
2284         i40e_dev_free_queues(dev);
2285         i40evf_reset_vf(hw);
2286         i40e_shutdown_adminq(hw);
2287         /* disable uio intr before callback unregister */
2288         rte_intr_disable(intr_handle);
2289
2290         /* unregister callback func from eal lib */
2291         rte_intr_callback_unregister(intr_handle,
2292                                      i40evf_dev_interrupt_handler, dev);
2293         i40evf_disable_irq0(hw);
2294 }
2295
2296 /*
2297  * Reset VF device only to re-initialize resources in PMD layer
2298  */
2299 static int
2300 i40evf_dev_reset(struct rte_eth_dev *dev)
2301 {
2302         int ret;
2303
2304         ret = i40evf_dev_uninit(dev);
2305         if (ret)
2306                 return ret;
2307
2308         ret = i40evf_dev_init(dev);
2309
2310         return ret;
2311 }
2312
2313 static int
2314 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2315 {
2316         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2317         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2318         int ret;
2319
2320         if (!lut)
2321                 return -EINVAL;
2322
2323         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2324                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2325                                           lut, lut_size);
2326                 if (ret) {
2327                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2328                         return ret;
2329                 }
2330         } else {
2331                 uint32_t *lut_dw = (uint32_t *)lut;
2332                 uint16_t i, lut_size_dw = lut_size / 4;
2333
2334                 for (i = 0; i < lut_size_dw; i++)
2335                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2336         }
2337
2338         return 0;
2339 }
2340
2341 static int
2342 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2343 {
2344         struct i40e_vf *vf;
2345         struct i40e_hw *hw;
2346         int ret;
2347
2348         if (!vsi || !lut)
2349                 return -EINVAL;
2350
2351         vf = I40E_VSI_TO_VF(vsi);
2352         hw = I40E_VSI_TO_HW(vsi);
2353
2354         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2355                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2356                                           lut, lut_size);
2357                 if (ret) {
2358                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2359                         return ret;
2360                 }
2361         } else {
2362                 uint32_t *lut_dw = (uint32_t *)lut;
2363                 uint16_t i, lut_size_dw = lut_size / 4;
2364
2365                 for (i = 0; i < lut_size_dw; i++)
2366                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2367                 I40EVF_WRITE_FLUSH(hw);
2368         }
2369
2370         return 0;
2371 }
2372
2373 static int
2374 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2375                            struct rte_eth_rss_reta_entry64 *reta_conf,
2376                            uint16_t reta_size)
2377 {
2378         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2379         uint8_t *lut;
2380         uint16_t i, idx, shift;
2381         int ret;
2382
2383         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2384                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2385                         "(%d) doesn't match the number of hardware can "
2386                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2387                 return -EINVAL;
2388         }
2389
2390         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2391         if (!lut) {
2392                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2393                 return -ENOMEM;
2394         }
2395         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2396         if (ret)
2397                 goto out;
2398         for (i = 0; i < reta_size; i++) {
2399                 idx = i / RTE_RETA_GROUP_SIZE;
2400                 shift = i % RTE_RETA_GROUP_SIZE;
2401                 if (reta_conf[idx].mask & (1ULL << shift))
2402                         lut[i] = reta_conf[idx].reta[shift];
2403         }
2404         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2405
2406 out:
2407         rte_free(lut);
2408
2409         return ret;
2410 }
2411
2412 static int
2413 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2414                           struct rte_eth_rss_reta_entry64 *reta_conf,
2415                           uint16_t reta_size)
2416 {
2417         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2418         uint16_t i, idx, shift;
2419         uint8_t *lut;
2420         int ret;
2421
2422         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2423                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2424                         "(%d) doesn't match the number of hardware can "
2425                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2426                 return -EINVAL;
2427         }
2428
2429         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2430         if (!lut) {
2431                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2432                 return -ENOMEM;
2433         }
2434
2435         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2436         if (ret)
2437                 goto out;
2438         for (i = 0; i < reta_size; i++) {
2439                 idx = i / RTE_RETA_GROUP_SIZE;
2440                 shift = i % RTE_RETA_GROUP_SIZE;
2441                 if (reta_conf[idx].mask & (1ULL << shift))
2442                         reta_conf[idx].reta[shift] = lut[i];
2443         }
2444
2445 out:
2446         rte_free(lut);
2447
2448         return ret;
2449 }
2450
2451 static int
2452 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2453 {
2454         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2455         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2456         int ret = 0;
2457
2458         if (!key || key_len == 0) {
2459                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2460                 return 0;
2461         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2462                 sizeof(uint32_t)) {
2463                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2464                 return -EINVAL;
2465         }
2466
2467         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2468                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2469                         (struct i40e_aqc_get_set_rss_key_data *)key;
2470
2471                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2472                 if (ret)
2473                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2474                                      "via AQ");
2475         } else {
2476                 uint32_t *hash_key = (uint32_t *)key;
2477                 uint16_t i;
2478
2479                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2480                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2481                 I40EVF_WRITE_FLUSH(hw);
2482         }
2483
2484         return ret;
2485 }
2486
2487 static int
2488 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2489 {
2490         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2491         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2492         int ret;
2493
2494         if (!key || !key_len)
2495                 return -EINVAL;
2496
2497         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2498                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2499                         (struct i40e_aqc_get_set_rss_key_data *)key);
2500                 if (ret) {
2501                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2502                         return ret;
2503                 }
2504         } else {
2505                 uint32_t *key_dw = (uint32_t *)key;
2506                 uint16_t i;
2507
2508                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2509                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2510         }
2511         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2512
2513         return 0;
2514 }
2515
2516 static int
2517 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2518 {
2519         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2520         uint64_t hena;
2521         int ret;
2522
2523         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2524                                  rss_conf->rss_key_len);
2525         if (ret)
2526                 return ret;
2527
2528         hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2529         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2530         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2531         I40EVF_WRITE_FLUSH(hw);
2532
2533         return 0;
2534 }
2535
2536 static void
2537 i40evf_disable_rss(struct i40e_vf *vf)
2538 {
2539         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2540
2541         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2542         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2543         I40EVF_WRITE_FLUSH(hw);
2544 }
2545
2546 static int
2547 i40evf_config_rss(struct i40e_vf *vf)
2548 {
2549         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2550         struct rte_eth_rss_conf rss_conf;
2551         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2552         uint16_t num;
2553
2554         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2555                 i40evf_disable_rss(vf);
2556                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2557                 return 0;
2558         }
2559
2560         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2561         /* Fill out the look up table */
2562         for (i = 0, j = 0; i < nb_q; i++, j++) {
2563                 if (j >= num)
2564                         j = 0;
2565                 lut = (lut << 8) | j;
2566                 if ((i & 3) == 3)
2567                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2568         }
2569
2570         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2571         if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2572                 i40evf_disable_rss(vf);
2573                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2574                 return 0;
2575         }
2576
2577         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2578                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2579                 /* Calculate the default hash key */
2580                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2581                         rss_key_default[i] = (uint32_t)rte_rand();
2582                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2583                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2584                         sizeof(uint32_t);
2585         }
2586
2587         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2588 }
2589
2590 static int
2591 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2592                            struct rte_eth_rss_conf *rss_conf)
2593 {
2594         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2595         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2596         uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2597         uint64_t hena;
2598
2599         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2600         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2601
2602         if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2603                 if (rss_hf != 0) /* Enable RSS */
2604                         return -EINVAL;
2605                 return 0;
2606         }
2607
2608         /* RSS enabled */
2609         if (rss_hf == 0) /* Disable RSS */
2610                 return -EINVAL;
2611
2612         return i40evf_hw_rss_hash_set(vf, rss_conf);
2613 }
2614
2615 static int
2616 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2617                              struct rte_eth_rss_conf *rss_conf)
2618 {
2619         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2620         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2621         uint64_t hena;
2622
2623         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2624                            &rss_conf->rss_key_len);
2625
2626         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2627         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2628         rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2629
2630         return 0;
2631 }
2632
2633 static int
2634 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2635 {
2636         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2637         struct rte_eth_dev_data *dev_data = vf->dev_data;
2638         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2639         int ret = 0;
2640
2641         /* check if mtu is within the allowed range */
2642         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2643                 return -EINVAL;
2644
2645         /* mtu setting is forbidden if port is start */
2646         if (dev_data->dev_started) {
2647                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2648                             dev_data->port_id);
2649                 return -EBUSY;
2650         }
2651
2652         if (frame_size > ETHER_MAX_LEN)
2653                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2654         else
2655                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2656
2657         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2658
2659         return ret;
2660 }
2661
2662 static void
2663 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2664                             struct ether_addr *mac_addr)
2665 {
2666         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2667
2668         if (!is_valid_assigned_ether_addr(mac_addr)) {
2669                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2670                 return;
2671         }
2672
2673         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2674                 return;
2675
2676         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2677                 return;
2678
2679         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2680
2681         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2682 }