drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_atomic.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum i40e_virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum i40e_virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   __rte_unused int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
 123                                 int on);
 124 static void i40evf_dev_close(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 131                                      uint16_t rx_queue_id);
 132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 133                                     uint16_t rx_queue_id);
 134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 135                                      uint16_t tx_queue_id);
 136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 137                                     uint16_t tx_queue_id);
 138 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
 139                                 struct ether_addr *addr,
 140                                 uint32_t index,
 141                                 uint32_t pool);
 142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 144                         struct rte_eth_rss_reta_entry64 *reta_conf,
 145                         uint16_t reta_size);
 146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 147                         struct rte_eth_rss_reta_entry64 *reta_conf,
 148                         uint16_t reta_size);
 149 static int i40evf_config_rss(struct i40e_vf *vf);
 150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 151                                       struct rte_eth_rss_conf *rss_conf);
 152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 153                                         struct rte_eth_rss_conf *rss_conf);
 154 static int
 155 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 156 static int
 157 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
 159                                    uint8_t *msg,
 160                                    uint16_t msglen);
 161
 162 /* Default hash key buffer for RSS */
 163 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 164
 165 struct rte_i40evf_xstats_name_off {
 166         char name[RTE_ETH_XSTATS_NAME_SIZE];
 167         unsigned offset;
 168 };
 169
 170 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 171         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 172         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 173         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 174         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 175         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 176         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 177                 rx_unknown_protocol)},
 178         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 179         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 180         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 182         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 183         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_bytes)},
 184 };
 185
 186 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 187                 sizeof(rte_i40evf_stats_strings[0]))
 188
 189 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 190         .dev_configure        = i40evf_dev_configure,
 191         .dev_start            = i40evf_dev_start,
 192         .dev_stop             = i40evf_dev_stop,
 193         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 194         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 195         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 196         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 197         .link_update          = i40evf_dev_link_update,
 198         .stats_get            = i40evf_dev_stats_get,
 199         .xstats_get           = i40evf_dev_xstats_get,
 200         .xstats_get_names     = i40evf_dev_xstats_get_names,
 201         .xstats_reset         = i40evf_dev_xstats_reset,
 202         .dev_close            = i40evf_dev_close,
 203         .dev_infos_get        = i40evf_dev_info_get,
 204         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 205         .vlan_filter_set      = i40evf_vlan_filter_set,
 206         .vlan_offload_set     = i40evf_vlan_offload_set,
 207         .vlan_pvid_set        = i40evf_vlan_pvid_set,
 208         .rx_queue_start       = i40evf_dev_rx_queue_start,
 209         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 210         .tx_queue_start       = i40evf_dev_tx_queue_start,
 211         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 212         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 213         .rx_queue_release     = i40e_dev_rx_queue_release,
 214         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 215         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 216         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 217         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 218         .tx_queue_release     = i40e_dev_tx_queue_release,
 219         .rx_queue_count       = i40e_dev_rx_queue_count,
 220         .rxq_info_get         = i40e_rxq_info_get,
 221         .txq_info_get         = i40e_txq_info_get,
 222         .mac_addr_add         = i40evf_add_mac_addr,
 223         .mac_addr_remove      = i40evf_del_mac_addr,
 224         .reta_update          = i40evf_dev_rss_reta_update,
 225         .reta_query           = i40evf_dev_rss_reta_query,
 226         .rss_hash_update      = i40evf_dev_rss_hash_update,
 227         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 228 };
 229
 230 /*
 231  * Read data in admin queue to get msg from pf driver
 232  */
 233 static enum i40evf_aq_result
 234 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 235 {
 236         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 237         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 238         struct i40e_arq_event_info event;
 239         enum i40e_virtchnl_ops opcode;
 240         enum i40e_status_code retval;
 241         int ret;
 242         enum i40evf_aq_result result = I40EVF_MSG_NON;
 243
 244         event.buf_len = data->buf_len;
 245         event.msg_buf = data->msg;
 246         ret = i40e_clean_arq_element(hw, &event, NULL);
 247         /* Can't read any msg from adminQ */
 248         if (ret) {
 249                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 250                         result = I40EVF_MSG_ERR;
 251                 return result;
 252         }
 253
 254         opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 255         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 256         /* pf sys event */
 257         if (opcode == I40E_VIRTCHNL_OP_EVENT) {
 258                 struct i40e_virtchnl_pf_event *vpe =
 259                         (struct i40e_virtchnl_pf_event *)event.msg_buf;
 260
 261                 result = I40EVF_MSG_SYS;
 262                 switch (vpe->event) {
 263                 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
 264                         vf->link_up =
 265                                 vpe->event_data.link_event.link_status;
 266                         vf->link_speed =
 267                                 vpe->event_data.link_event.link_speed;
 268                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 269                         PMD_DRV_LOG(INFO, "Link status update:%s",
 270                                     vf->link_up ? "up" : "down");
 271                         break;
 272                 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
 273                         vf->vf_reset = true;
 274                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 275                         PMD_DRV_LOG(INFO, "vf is reseting");
 276                         break;
 277                 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 278                         vf->dev_closed = true;
 279                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 280                         PMD_DRV_LOG(INFO, "PF driver closed");
 281                         break;
 282                 default:
 283                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 284                                     __func__, vpe->event);
 285                 }
 286         } else {
 287                 /* async reply msg on command issued by vf previously */
 288                 result = I40EVF_MSG_CMD;
 289                 /* Actual data length read from PF */
 290                 data->msg_len = event.msg_len;
 291         }
 292
 293         data->result = retval;
 294         data->ops = opcode;
 295
 296         return result;
 297 }
 298
 299 /**
 300  * clear current command. Only call in case execute
 301  * _atomic_set_cmd successfully.
 302  */
 303 static inline void
 304 _clear_cmd(struct i40e_vf *vf)
 305 {
 306         rte_wmb();
 307         vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
 308 }
 309
 310 /*
 311  * Check there is pending cmd in execution. If none, set new command.
 312  */
 313 static inline int
 314 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
 315 {
 316         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 317                         I40E_VIRTCHNL_OP_UNKNOWN, ops);
 318
 319         if (!ret)
 320                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 321
 322         return !ret;
 323 }
 324
 325 #define MAX_TRY_TIMES 200
 326 #define ASQ_DELAY_MS  10
 327
 328 static int
 329 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 330 {
 331         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 332         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 333         struct i40evf_arq_msg_info info;
 334         enum i40evf_aq_result ret;
 335         int err, i = 0;
 336
 337         if (_atomic_set_cmd(vf, args->ops))
 338                 return -1;
 339
 340         info.msg = args->out_buffer;
 341         info.buf_len = args->out_size;
 342         info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
 343         info.result = I40E_SUCCESS;
 344
 345         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 346                      args->in_args, args->in_args_size, NULL);
 347         if (err) {
 348                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 349                 _clear_cmd(vf);
 350                 return err;
 351         }
 352
 353         switch (args->ops) {
 354         case I40E_VIRTCHNL_OP_RESET_VF:
 355                 /*no need to process in this function */
 356                 err = 0;
 357                 break;
 358         case I40E_VIRTCHNL_OP_VERSION:
 359         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 360                 /* for init adminq commands, need to poll the response */
 361                 err = -1;
 362                 do {
 363                         ret = i40evf_read_pfmsg(dev, &info);
 364                         if (ret == I40EVF_MSG_CMD) {
 365                                 err = 0;
 366                                 break;
 367                         } else if (ret == I40EVF_MSG_ERR)
 368                                 break;
 369                         rte_delay_ms(ASQ_DELAY_MS);
 370                         /* If don't read msg or read sys event, continue */
 371                 } while (i++ < MAX_TRY_TIMES);
 372                 _clear_cmd(vf);
 373                 break;
 374
 375         default:
 376                 /* for other adminq in running time, waiting the cmd done flag */
 377                 err = -1;
 378                 do {
 379                         if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
 380                                 err = 0;
 381                                 break;
 382                         }
 383                         rte_delay_ms(ASQ_DELAY_MS);
 384                         /* If don't read msg or read sys event, continue */
 385                 } while (i++ < MAX_TRY_TIMES);
 386                 break;
 387         }
 388
 389         return err | vf->cmd_retval;
 390 }
 391
 392 /*
 393  * Check API version with sync wait until version read or fail from admin queue
 394  */
 395 static int
 396 i40evf_check_api_version(struct rte_eth_dev *dev)
 397 {
 398         struct i40e_virtchnl_version_info version, *pver;
 399         int err;
 400         struct vf_cmd_info args;
 401         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 402
 403         version.major = I40E_VIRTCHNL_VERSION_MAJOR;
 404         version.minor = I40E_VIRTCHNL_VERSION_MINOR;
 405
 406         args.ops = I40E_VIRTCHNL_OP_VERSION;
 407         args.in_args = (uint8_t *)&version;
 408         args.in_args_size = sizeof(version);
 409         args.out_buffer = vf->aq_resp;
 410         args.out_size = I40E_AQ_BUF_SZ;
 411
 412         err = i40evf_execute_vf_cmd(dev, &args);
 413         if (err) {
 414                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 415                 return err;
 416         }
 417
 418         pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
 419         vf->version_major = pver->major;
 420         vf->version_minor = pver->minor;
 421         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 422                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 423         else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
 424                 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
 425                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 426         else {
 427                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 428                                         vf->version_major, vf->version_minor,
 429                                                 I40E_VIRTCHNL_VERSION_MAJOR,
 430                                                 I40E_VIRTCHNL_VERSION_MINOR);
 431                 return -1;
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int
 438 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 439 {
 440         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 441         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 442         int err;
 443         struct vf_cmd_info args;
 444         uint32_t caps, len;
 445
 446         args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
 447         args.out_buffer = vf->aq_resp;
 448         args.out_size = I40E_AQ_BUF_SZ;
 449         if (PF_IS_V11(vf)) {
 450                 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 451                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 452                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
 453                        I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
 454                        I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 455                 args.in_args = (uint8_t *)&caps;
 456                 args.in_args_size = sizeof(caps);
 457         } else {
 458                 args.in_args = NULL;
 459                 args.in_args_size = 0;
 460         }
 461         err = i40evf_execute_vf_cmd(dev, &args);
 462
 463         if (err) {
 464                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 465                 return err;
 466         }
 467
 468         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 469                 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
 470
 471         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 472                         RTE_MIN(args.out_size, len));
 473         i40e_vf_parse_hw_config(hw, vf->vf_res);
 474
 475         return 0;
 476 }
 477
 478 static int
 479 i40evf_config_promisc(struct rte_eth_dev *dev,
 480                       bool enable_unicast,
 481                       bool enable_multicast)
 482 {
 483         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 484         int err;
 485         struct vf_cmd_info args;
 486         struct i40e_virtchnl_promisc_info promisc;
 487
 488         promisc.flags = 0;
 489         promisc.vsi_id = vf->vsi_res->vsi_id;
 490
 491         if (enable_unicast)
 492                 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
 493
 494         if (enable_multicast)
 495                 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 496
 497         args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 498         args.in_args = (uint8_t *)&promisc;
 499         args.in_args_size = sizeof(promisc);
 500         args.out_buffer = vf->aq_resp;
 501         args.out_size = I40E_AQ_BUF_SZ;
 502
 503         err = i40evf_execute_vf_cmd(dev, &args);
 504
 505         if (err)
 506                 PMD_DRV_LOG(ERR, "fail to execute command "
 507                             "CONFIG_PROMISCUOUS_MODE");
 508         return err;
 509 }
 510
 511 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
 512 static int
 513 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
 514                                 bool enable_vlan_strip)
 515 {
 516         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 517         int err;
 518         struct vf_cmd_info args;
 519         struct i40e_virtchnl_vlan_offload_info offload;
 520
 521         offload.vsi_id = vf->vsi_res->vsi_id;
 522         offload.enable_vlan_strip = enable_vlan_strip;
 523
 524         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
 525         args.in_args = (uint8_t *)&offload;
 526         args.in_args_size = sizeof(offload);
 527         args.out_buffer = vf->aq_resp;
 528         args.out_size = I40E_AQ_BUF_SZ;
 529
 530         err = i40evf_execute_vf_cmd(dev, &args);
 531         if (err)
 532                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
 533
 534         return err;
 535 }
 536
 537 static int
 538 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 539                                 struct i40e_vsi_vlan_pvid_info *info)
 540 {
 541         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 542         int err;
 543         struct vf_cmd_info args;
 544         struct i40e_virtchnl_pvid_info tpid_info;
 545
 546         if (info == NULL) {
 547                 PMD_DRV_LOG(ERR, "invalid parameters");
 548                 return I40E_ERR_PARAM;
 549         }
 550
 551         memset(&tpid_info, 0, sizeof(tpid_info));
 552         tpid_info.vsi_id = vf->vsi_res->vsi_id;
 553         (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
 554
 555         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
 556         args.in_args = (uint8_t *)&tpid_info;
 557         args.in_args_size = sizeof(tpid_info);
 558         args.out_buffer = vf->aq_resp;
 559         args.out_size = I40E_AQ_BUF_SZ;
 560
 561         err = i40evf_execute_vf_cmd(dev, &args);
 562         if (err)
 563                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
 564
 565         return err;
 566 }
 567
 568 static void
 569 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
 570                                   uint16_t vsi_id,
 571                                   uint16_t queue_id,
 572                                   uint16_t nb_txq,
 573                                   struct i40e_tx_queue *txq)
 574 {
 575         txq_info->vsi_id = vsi_id;
 576         txq_info->queue_id = queue_id;
 577         if (queue_id < nb_txq) {
 578                 txq_info->ring_len = txq->nb_tx_desc;
 579                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 580         }
 581 }
 582
 583 static void
 584 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
 585                                   uint16_t vsi_id,
 586                                   uint16_t queue_id,
 587                                   uint16_t nb_rxq,
 588                                   uint32_t max_pkt_size,
 589                                   struct i40e_rx_queue *rxq)
 590 {
 591         rxq_info->vsi_id = vsi_id;
 592         rxq_info->queue_id = queue_id;
 593         rxq_info->max_pkt_size = max_pkt_size;
 594         if (queue_id < nb_rxq) {
 595                 rxq_info->ring_len = rxq->nb_rx_desc;
 596                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 597                 rxq_info->databuffer_size =
 598                         (rte_pktmbuf_data_room_size(rxq->mp) -
 599                                 RTE_PKTMBUF_HEADROOM);
 600         }
 601 }
 602
 603 /* It configures VSI queues to co-work with Linux PF host */
 604 static int
 605 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 606 {
 607         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 608         struct i40e_rx_queue **rxq =
 609                 (struct i40e_rx_queue **)dev->data->rx_queues;
 610         struct i40e_tx_queue **txq =
 611                 (struct i40e_tx_queue **)dev->data->tx_queues;
 612         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
 613         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 614         struct vf_cmd_info args;
 615         uint16_t i, nb_qp = vf->num_queue_pairs;
 616         const uint32_t size =
 617                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 618         uint8_t buff[size];
 619         int ret;
 620
 621         memset(buff, 0, sizeof(buff));
 622         vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
 623         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 624         vc_vqci->num_queue_pairs = nb_qp;
 625
 626         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 627                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 628                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 629                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 630                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 631                                         vf->max_pkt_len, rxq[i]);
 632         }
 633         memset(&args, 0, sizeof(args));
 634         args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 635         args.in_args = (uint8_t *)vc_vqci;
 636         args.in_args_size = size;
 637         args.out_buffer = vf->aq_resp;
 638         args.out_size = I40E_AQ_BUF_SZ;
 639         ret = i40evf_execute_vf_cmd(dev, &args);
 640         if (ret)
 641                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 642                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES\n");
 643
 644         return ret;
 645 }
 646
 647 /* It configures VSI queues to co-work with DPDK PF host */
 648 static int
 649 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
 650 {
 651         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 652         struct i40e_rx_queue **rxq =
 653                 (struct i40e_rx_queue **)dev->data->rx_queues;
 654         struct i40e_tx_queue **txq =
 655                 (struct i40e_tx_queue **)dev->data->tx_queues;
 656         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
 657         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 658         struct vf_cmd_info args;
 659         uint16_t i, nb_qp = vf->num_queue_pairs;
 660         const uint32_t size =
 661                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
 662         uint8_t buff[size];
 663         int ret;
 664
 665         memset(buff, 0, sizeof(buff));
 666         vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
 667         vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
 668         vc_vqcei->num_queue_pairs = nb_qp;
 669         vc_qpei = vc_vqcei->qpair;
 670         for (i = 0; i < nb_qp; i++, vc_qpei++) {
 671                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
 672                         vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 673                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
 674                         vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
 675                                         vf->max_pkt_len, rxq[i]);
 676                 if (i < dev->data->nb_rx_queues)
 677                         /*
 678                          * It adds extra info for configuring VSI queues, which
 679                          * is needed to enable the configurable crc stripping
 680                          * in VF.
 681                          */
 682                         vc_qpei->rxq_ext.crcstrip =
 683                                 dev->data->dev_conf.rxmode.hw_strip_crc;
 684         }
 685         memset(&args, 0, sizeof(args));
 686         args.ops =
 687                 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
 688         args.in_args = (uint8_t *)vc_vqcei;
 689         args.in_args_size = size;
 690         args.out_buffer = vf->aq_resp;
 691         args.out_size = I40E_AQ_BUF_SZ;
 692         ret = i40evf_execute_vf_cmd(dev, &args);
 693         if (ret)
 694                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 695                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT\n");
 696
 697         return ret;
 698 }
 699
 700 static int
 701 i40evf_configure_queues(struct rte_eth_dev *dev)
 702 {
 703         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 704
 705         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 706                 /* To support DPDK PF host */
 707                 return i40evf_configure_vsi_queues_ext(dev);
 708         else
 709                 /* To support Linux PF host */
 710                 return i40evf_configure_vsi_queues(dev);
 711 }
 712
 713 static int
 714 i40evf_config_irq_map(struct rte_eth_dev *dev)
 715 {
 716         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 717         struct vf_cmd_info args;
 718         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
 719                 sizeof(struct i40e_virtchnl_vector_map)];
 720         struct i40e_virtchnl_irq_map_info *map_info;
 721         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 722         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 723         uint32_t vector_id;
 724         int i, err;
 725
 726         if (rte_intr_allow_others(intr_handle)) {
 727                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 728                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 729                 else
 730                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 731         } else {
 732                 vector_id = I40E_MISC_VEC_ID;
 733         }
 734
 735         map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
 736         map_info->num_vectors = 1;
 737         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 738         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 739         /* Alway use default dynamic MSIX interrupt */
 740         map_info->vecmap[0].vector_id = vector_id;
 741         /* Don't map any tx queue */
 742         map_info->vecmap[0].txq_map = 0;
 743         map_info->vecmap[0].rxq_map = 0;
 744         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 745                 map_info->vecmap[0].rxq_map |= 1 << i;
 746                 if (rte_intr_dp_is_en(intr_handle))
 747                         intr_handle->intr_vec[i] = vector_id;
 748         }
 749
 750         args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
 751         args.in_args = (u8 *)cmd_buffer;
 752         args.in_args_size = sizeof(cmd_buffer);
 753         args.out_buffer = vf->aq_resp;
 754         args.out_size = I40E_AQ_BUF_SZ;
 755         err = i40evf_execute_vf_cmd(dev, &args);
 756         if (err)
 757                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 758
 759         return err;
 760 }
 761
 762 static int
 763 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 764                                 bool on)
 765 {
 766         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 767         struct i40e_virtchnl_queue_select queue_select;
 768         int err;
 769         struct vf_cmd_info args;
 770         memset(&queue_select, 0, sizeof(queue_select));
 771         queue_select.vsi_id = vf->vsi_res->vsi_id;
 772
 773         if (isrx)
 774                 queue_select.rx_queues |= 1 << qid;
 775         else
 776                 queue_select.tx_queues |= 1 << qid;
 777
 778         if (on)
 779                 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
 780         else
 781                 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
 782         args.in_args = (u8 *)&queue_select;
 783         args.in_args_size = sizeof(queue_select);
 784         args.out_buffer = vf->aq_resp;
 785         args.out_size = I40E_AQ_BUF_SZ;
 786         err = i40evf_execute_vf_cmd(dev, &args);
 787         if (err)
 788                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 789                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 790
 791         return err;
 792 }
 793
 794 static int
 795 i40evf_start_queues(struct rte_eth_dev *dev)
 796 {
 797         struct rte_eth_dev_data *dev_data = dev->data;
 798         int i;
 799         struct i40e_rx_queue *rxq;
 800         struct i40e_tx_queue *txq;
 801
 802         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 803                 rxq = dev_data->rx_queues[i];
 804                 if (rxq->rx_deferred_start)
 805                         continue;
 806                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 807                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 808                         return -1;
 809                 }
 810         }
 811
 812         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 813                 txq = dev_data->tx_queues[i];
 814                 if (txq->tx_deferred_start)
 815                         continue;
 816                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 817                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 818                         return -1;
 819                 }
 820         }
 821
 822         return 0;
 823 }
 824
 825 static int
 826 i40evf_stop_queues(struct rte_eth_dev *dev)
 827 {
 828         int i;
 829
 830         /* Stop TX queues first */
 831         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 832                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 833                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 834                         return -1;
 835                 }
 836         }
 837
 838         /* Then stop RX queues */
 839         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 840                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 841                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 842                         return -1;
 843                 }
 844         }
 845
 846         return 0;
 847 }
 848
 849 static void
 850 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 851                     struct ether_addr *addr,
 852                     __rte_unused uint32_t index,
 853                     __rte_unused uint32_t pool)
 854 {
 855         struct i40e_virtchnl_ether_addr_list *list;
 856         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 857         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 858                         sizeof(struct i40e_virtchnl_ether_addr)];
 859         int err;
 860         struct vf_cmd_info args;
 861
 862         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 863                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 864                             addr->addr_bytes[0], addr->addr_bytes[1],
 865                             addr->addr_bytes[2], addr->addr_bytes[3],
 866                             addr->addr_bytes[4], addr->addr_bytes[5]);
 867                 return;
 868         }
 869
 870         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 871         list->vsi_id = vf->vsi_res->vsi_id;
 872         list->num_elements = 1;
 873         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 874                                         sizeof(addr->addr_bytes));
 875
 876         args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
 877         args.in_args = cmd_buffer;
 878         args.in_args_size = sizeof(cmd_buffer);
 879         args.out_buffer = vf->aq_resp;
 880         args.out_size = I40E_AQ_BUF_SZ;
 881         err = i40evf_execute_vf_cmd(dev, &args);
 882         if (err)
 883                 PMD_DRV_LOG(ERR, "fail to execute command "
 884                             "OP_ADD_ETHER_ADDRESS");
 885
 886         return;
 887 }
 888
 889 static void
 890 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 891 {
 892         struct i40e_virtchnl_ether_addr_list *list;
 893         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 894         struct rte_eth_dev_data *data = dev->data;
 895         struct ether_addr *addr;
 896         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 897                         sizeof(struct i40e_virtchnl_ether_addr)];
 898         int err;
 899         struct vf_cmd_info args;
 900
 901         addr = &(data->mac_addrs[index]);
 902
 903         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 904                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 905                             addr->addr_bytes[0], addr->addr_bytes[1],
 906                             addr->addr_bytes[2], addr->addr_bytes[3],
 907                             addr->addr_bytes[4], addr->addr_bytes[5]);
 908                 return;
 909         }
 910
 911         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 912         list->vsi_id = vf->vsi_res->vsi_id;
 913         list->num_elements = 1;
 914         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 915                         sizeof(addr->addr_bytes));
 916
 917         args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
 918         args.in_args = cmd_buffer;
 919         args.in_args_size = sizeof(cmd_buffer);
 920         args.out_buffer = vf->aq_resp;
 921         args.out_size = I40E_AQ_BUF_SZ;
 922         err = i40evf_execute_vf_cmd(dev, &args);
 923         if (err)
 924                 PMD_DRV_LOG(ERR, "fail to execute command "
 925                             "OP_DEL_ETHER_ADDRESS");
 926         return;
 927 }
 928
 929 static int
 930 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 931 {
 932         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 933         struct i40e_virtchnl_queue_select q_stats;
 934         int err;
 935         struct vf_cmd_info args;
 936
 937         memset(&q_stats, 0, sizeof(q_stats));
 938         q_stats.vsi_id = vf->vsi_res->vsi_id;
 939         args.ops = I40E_VIRTCHNL_OP_GET_STATS;
 940         args.in_args = (u8 *)&q_stats;
 941         args.in_args_size = sizeof(q_stats);
 942         args.out_buffer = vf->aq_resp;
 943         args.out_size = I40E_AQ_BUF_SZ;
 944
 945         err = i40evf_execute_vf_cmd(dev, &args);
 946         if (err) {
 947                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 948                 *pstats = NULL;
 949                 return err;
 950         }
 951         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 952         return 0;
 953 }
 954
 955 static int
 956 i40evf_get_statics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 957 {
 958         int ret;
 959         struct i40e_eth_stats *pstats = NULL;
 960
 961         ret = i40evf_update_stats(dev, &pstats);
 962         if (ret != 0)
 963                 return 0;
 964
 965         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 966                                                 pstats->rx_broadcast;
 967         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 968                                                 pstats->tx_unicast;
 969         stats->ierrors = pstats->rx_discards;
 970         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 971         stats->ibytes = pstats->rx_bytes;
 972         stats->obytes = pstats->tx_bytes;
 973
 974         return 0;
 975 }
 976
 977 static void
 978 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 979 {
 980         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 981         struct i40e_eth_stats *pstats = NULL;
 982
 983         /* read stat values to clear hardware registers */
 984         i40evf_update_stats(dev, &pstats);
 985
 986         /* set stats offset base on current values */
 987         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
 988 }
 989
 990 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 991                                       struct rte_eth_xstat_name *xstats_names,
 992                                       __rte_unused unsigned limit)
 993 {
 994         unsigned i;
 995
 996         if (xstats_names != NULL)
 997                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 998                         snprintf(xstats_names[i].name,
 999                                 sizeof(xstats_names[i].name),
1000                                 "%s", rte_i40evf_stats_strings[i].name);
1001                 }
1002         return I40EVF_NB_XSTATS;
1003 }
1004
1005 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1006                                  struct rte_eth_xstat *xstats, unsigned n)
1007 {
1008         int ret;
1009         unsigned i;
1010         struct i40e_eth_stats *pstats = NULL;
1011
1012         if (n < I40EVF_NB_XSTATS)
1013                 return I40EVF_NB_XSTATS;
1014
1015         ret = i40evf_update_stats(dev, &pstats);
1016         if (ret != 0)
1017                 return 0;
1018
1019         if (!xstats)
1020                 return 0;
1021
1022         /* loop over xstats array and values from pstats */
1023         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1024                 xstats[i].id = i;
1025                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1026                         rte_i40evf_stats_strings[i].offset);
1027         }
1028
1029         return I40EVF_NB_XSTATS;
1030 }
1031
1032 static int
1033 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1034 {
1035         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1036         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1037         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1038                                                         sizeof(uint16_t)];
1039         int err;
1040         struct vf_cmd_info args;
1041
1042         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1043         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1044         vlan_list->num_elements = 1;
1045         vlan_list->vlan_id[0] = vlanid;
1046
1047         args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1048         args.in_args = (u8 *)&cmd_buffer;
1049         args.in_args_size = sizeof(cmd_buffer);
1050         args.out_buffer = vf->aq_resp;
1051         args.out_size = I40E_AQ_BUF_SZ;
1052         err = i40evf_execute_vf_cmd(dev, &args);
1053         if (err)
1054                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1055
1056         return err;
1057 }
1058
1059 static int
1060 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1061 {
1062         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1063         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1064         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1065                                                         sizeof(uint16_t)];
1066         int err;
1067         struct vf_cmd_info args;
1068
1069         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1070         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1071         vlan_list->num_elements = 1;
1072         vlan_list->vlan_id[0] = vlanid;
1073
1074         args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1075         args.in_args = (u8 *)&cmd_buffer;
1076         args.in_args_size = sizeof(cmd_buffer);
1077         args.out_buffer = vf->aq_resp;
1078         args.out_size = I40E_AQ_BUF_SZ;
1079         err = i40evf_execute_vf_cmd(dev, &args);
1080         if (err)
1081                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1082
1083         return err;
1084 }
1085
1086 static const struct rte_pci_id pci_id_i40evf_map[] = {
1087         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1088         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1089         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1090         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1091         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF_HV) },
1092         { .vendor_id = 0, /* sentinel */ },
1093 };
1094
1095 static inline int
1096 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1097                                     struct rte_eth_link *link)
1098 {
1099         struct rte_eth_link *dst = &(dev->data->dev_link);
1100         struct rte_eth_link *src = link;
1101
1102         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1103                                         *(uint64_t *)src) == 0)
1104                 return -1;
1105
1106         return 0;
1107 }
1108
1109 /* Disable IRQ0 */
1110 static inline void
1111 i40evf_disable_irq0(struct i40e_hw *hw)
1112 {
1113         /* Disable all interrupt types */
1114         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1115         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1116                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1117         I40EVF_WRITE_FLUSH(hw);
1118 }
1119
1120 /* Enable IRQ0 */
1121 static inline void
1122 i40evf_enable_irq0(struct i40e_hw *hw)
1123 {
1124         /* Enable admin queue interrupt trigger */
1125         uint32_t val;
1126
1127         i40evf_disable_irq0(hw);
1128         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1129         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1130                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1131         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1132
1133         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1134                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1135                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1136                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1137
1138         I40EVF_WRITE_FLUSH(hw);
1139 }
1140
1141 static int
1142 i40evf_reset_vf(struct i40e_hw *hw)
1143 {
1144         int i, reset;
1145
1146         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1147                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1148                 return -1;
1149         }
1150         /**
1151           * After issuing vf reset command to pf, pf won't necessarily
1152           * reset vf, it depends on what state it exactly is. If it's not
1153           * initialized yet, it won't have vf reset since it's in a certain
1154           * state. If not, it will try to reset. Even vf is reset, pf will
1155           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1156           * it to ACTIVE. In this duration, vf may not catch the moment that
1157           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1158           */
1159         rte_delay_ms(200);
1160
1161         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1162                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1163                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1164                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1165                 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1166                         break;
1167                 else
1168                         rte_delay_ms(50);
1169         }
1170
1171         if (i >= MAX_RESET_WAIT_CNT) {
1172                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1173                 return -1;
1174         }
1175
1176         return 0;
1177 }
1178
1179 static int
1180 i40evf_init_vf(struct rte_eth_dev *dev)
1181 {
1182         int i, err, bufsz;
1183         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1184         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1185         struct ether_addr *p_mac_addr;
1186         uint16_t interval =
1187                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1188
1189         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1190         vf->dev_data = dev->data;
1191         err = i40e_set_mac_type(hw);
1192         if (err) {
1193                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1194                 goto err;
1195         }
1196
1197         i40e_init_adminq_parameter(hw);
1198         err = i40e_init_adminq(hw);
1199         if (err) {
1200                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1201                 goto err;
1202         }
1203
1204         /* Reset VF and wait until it's complete */
1205         if (i40evf_reset_vf(hw)) {
1206                 PMD_INIT_LOG(ERR, "reset NIC failed");
1207                 goto err_aq;
1208         }
1209
1210         /* VF reset, shutdown admin queue and initialize again */
1211         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1212                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1213                 return -1;
1214         }
1215
1216         i40e_init_adminq_parameter(hw);
1217         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1218                 PMD_INIT_LOG(ERR, "init_adminq failed");
1219                 return -1;
1220         }
1221         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1222         if (!vf->aq_resp) {
1223                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1224                         goto err_aq;
1225         }
1226         if (i40evf_check_api_version(dev) != 0) {
1227                 PMD_INIT_LOG(ERR, "check_api version failed");
1228                 goto err_aq;
1229         }
1230         bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1231                 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1232         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1233         if (!vf->vf_res) {
1234                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1235                         goto err_aq;
1236         }
1237
1238         if (i40evf_get_vf_resource(dev) != 0) {
1239                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1240                 goto err_alloc;
1241         }
1242
1243         /* got VF config message back from PF, now we can parse it */
1244         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1245                 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1246                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1247         }
1248
1249         if (!vf->vsi_res) {
1250                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1251                 goto err_alloc;
1252         }
1253
1254         if (hw->mac.type == I40E_MAC_X722_VF)
1255                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1256         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1257         vf->vsi.type = vf->vsi_res->vsi_type;
1258         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1259         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1260
1261         /* Store the MAC address configured by host, or generate random one */
1262         p_mac_addr = (struct ether_addr *)(vf->vsi_res->default_mac_addr);
1263         if (is_valid_assigned_ether_addr(p_mac_addr)) /* Configured by host */
1264                 ether_addr_copy(p_mac_addr, (struct ether_addr *)hw->mac.addr);
1265         else
1266                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1267
1268         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1269         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1270                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1271                                (I40E_ITR_INDEX_DEFAULT <<
1272                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1273                                (interval <<
1274                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1275                 I40EVF_WRITE_FLUSH(hw);
1276         }
1277
1278         return 0;
1279
1280 err_alloc:
1281         rte_free(vf->vf_res);
1282 err_aq:
1283         i40e_shutdown_adminq(hw); /* ignore error */
1284 err:
1285         return -1;
1286 }
1287
1288 static int
1289 i40evf_uninit_vf(struct rte_eth_dev *dev)
1290 {
1291         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1292         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1293
1294         PMD_INIT_FUNC_TRACE();
1295
1296         if (hw->adapter_stopped == 0)
1297                 i40evf_dev_close(dev);
1298         rte_free(vf->vf_res);
1299         vf->vf_res = NULL;
1300         rte_free(vf->aq_resp);
1301         vf->aq_resp = NULL;
1302
1303         return 0;
1304 }
1305
1306 static void
1307 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1308                            uint8_t *msg,
1309                            __rte_unused uint16_t msglen)
1310 {
1311         struct i40e_virtchnl_pf_event *pf_msg =
1312                         (struct i40e_virtchnl_pf_event *)msg;
1313         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1314
1315         switch (pf_msg->event) {
1316         case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1317                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event\n");
1318                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1319                 break;
1320         case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1321                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event\n");
1322                 vf->link_up = pf_msg->event_data.link_event.link_status;
1323                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1324                 break;
1325         case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1326                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event\n");
1327                 break;
1328         default:
1329                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1330                 break;
1331         }
1332 }
1333
1334 static void
1335 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1336 {
1337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1338         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1339         struct i40e_arq_event_info info;
1340         struct i40e_virtchnl_msg *v_msg;
1341         uint16_t pending, opcode;
1342         int ret;
1343
1344         info.buf_len = I40E_AQ_BUF_SZ;
1345         if (!vf->aq_resp) {
1346                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1347                 return;
1348         }
1349         info.msg_buf = vf->aq_resp;
1350         v_msg = (struct i40e_virtchnl_msg *)&info.desc;
1351
1352         pending = 1;
1353         while (pending) {
1354                 ret = i40e_clean_arq_element(hw, &info, &pending);
1355
1356                 if (ret != I40E_SUCCESS) {
1357                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1358                                     "ret: %d", ret);
1359                         break;
1360                 }
1361                 opcode = rte_le_to_cpu_16(info.desc.opcode);
1362
1363                 switch (opcode) {
1364                 case i40e_aqc_opc_send_msg_to_vf:
1365                         if (v_msg->v_opcode == I40E_VIRTCHNL_OP_EVENT)
1366                                 /* process event*/
1367                                 i40evf_handle_pf_event(dev, info.msg_buf,
1368                                                        info.msg_len);
1369                         else {
1370                                 /* read message and it's expected one */
1371                                 if (v_msg->v_opcode == vf->pend_cmd) {
1372                                         vf->cmd_retval = v_msg->v_retval;
1373                                         /* prevent compiler reordering */
1374                                         rte_compiler_barrier();
1375                                         _clear_cmd(vf);
1376                                 } else
1377                                         PMD_DRV_LOG(ERR, "command mismatch,"
1378                                                 "expect %u, get %u",
1379                                                 vf->pend_cmd, v_msg->v_opcode);
1380                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1381                                              " opcode = %d\n", v_msg->v_opcode);
1382                         }
1383                         break;
1384                 default:
1385                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1386                                     opcode);
1387                         break;
1388                 }
1389         }
1390 }
1391
1392 /**
1393  * Interrupt handler triggered by NIC  for handling
1394  * specific interrupt. Only adminq interrupt is processed in VF.
1395  *
1396  * @param handle
1397  *  Pointer to interrupt handle.
1398  * @param param
1399  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1400  *
1401  * @return
1402  *  void
1403  */
1404 static void
1405 i40evf_dev_interrupt_handler(struct rte_intr_handle *intr_handle,
1406                              void *param)
1407 {
1408         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1409         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1410         uint32_t icr0;
1411
1412         i40evf_disable_irq0(hw);
1413
1414         /* read out interrupt causes */
1415         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1416
1417         /* No interrupt event indicated */
1418         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1419                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do\n");
1420                 goto done;
1421         }
1422
1423         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1424                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported\n");
1425                 i40evf_handle_aq_msg(dev);
1426         }
1427
1428         /* Link Status Change interrupt */
1429         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1430                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1431                                    " do nothing\n");
1432
1433 done:
1434         i40evf_enable_irq0(hw);
1435         rte_intr_enable(intr_handle);
1436 }
1437
1438 static int
1439 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1440 {
1441         struct i40e_hw *hw
1442                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1443         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(eth_dev);
1444
1445         PMD_INIT_FUNC_TRACE();
1446
1447         /* assign ops func pointer */
1448         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1449         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1450         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1451
1452         /*
1453          * For secondary processes, we don't initialise any further as primary
1454          * has already done this work.
1455          */
1456         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1457                 i40e_set_rx_function(eth_dev);
1458                 i40e_set_tx_function(eth_dev);
1459                 return 0;
1460         }
1461
1462         rte_eth_copy_pci_info(eth_dev, pci_dev);
1463         eth_dev->data->dev_flags = RTE_ETH_DEV_DETACHABLE;
1464
1465         hw->vendor_id = pci_dev->id.vendor_id;
1466         hw->device_id = pci_dev->id.device_id;
1467         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1468         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1469         hw->bus.device = pci_dev->addr.devid;
1470         hw->bus.func = pci_dev->addr.function;
1471         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1472         hw->adapter_stopped = 0;
1473
1474         if(i40evf_init_vf(eth_dev) != 0) {
1475                 PMD_INIT_LOG(ERR, "Init vf failed");
1476                 return -1;
1477         }
1478
1479         /* register callback func to eal lib */
1480         rte_intr_callback_register(&pci_dev->intr_handle,
1481                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1482
1483         /* enable uio intr after callback register */
1484         rte_intr_enable(&pci_dev->intr_handle);
1485
1486         /* configure and enable device interrupt */
1487         i40evf_enable_irq0(hw);
1488
1489         /* copy mac addr */
1490         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1491                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1492                                         0);
1493         if (eth_dev->data->mac_addrs == NULL) {
1494                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1495                                 " store MAC addresses",
1496                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1497                 return -ENOMEM;
1498         }
1499         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1500                         &eth_dev->data->mac_addrs[0]);
1501
1502         return 0;
1503 }
1504
1505 static int
1506 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1507 {
1508         PMD_INIT_FUNC_TRACE();
1509
1510         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1511                 return -EPERM;
1512
1513         eth_dev->dev_ops = NULL;
1514         eth_dev->rx_pkt_burst = NULL;
1515         eth_dev->tx_pkt_burst = NULL;
1516
1517         if (i40evf_uninit_vf(eth_dev) != 0) {
1518                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1519                 return -1;
1520         }
1521
1522         rte_free(eth_dev->data->mac_addrs);
1523         eth_dev->data->mac_addrs = NULL;
1524
1525         return 0;
1526 }
1527 /*
1528  * virtual function driver struct
1529  */
1530 static struct eth_driver rte_i40evf_pmd = {
1531         .pci_drv = {
1532                 .id_table = pci_id_i40evf_map,
1533                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1534                 .probe = rte_eth_dev_pci_probe,
1535                 .remove = rte_eth_dev_pci_remove,
1536         },
1537         .eth_dev_init = i40evf_dev_init,
1538         .eth_dev_uninit = i40evf_dev_uninit,
1539         .dev_private_size = sizeof(struct i40e_adapter),
1540 };
1541
1542 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1543 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1544 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio");
1545
1546 static int
1547 i40evf_dev_configure(struct rte_eth_dev *dev)
1548 {
1549         struct i40e_adapter *ad =
1550                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1551         struct rte_eth_conf *conf = &dev->data->dev_conf;
1552         struct i40e_vf *vf;
1553
1554         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1555          * allocation or vector Rx preconditions we will reset it.
1556          */
1557         ad->rx_bulk_alloc_allowed = true;
1558         ad->rx_vec_allowed = true;
1559         ad->tx_simple_allowed = true;
1560         ad->tx_vec_allowed = true;
1561
1562         /* For non-DPDK PF drivers, VF has no ability to disable HW
1563          * CRC strip, and is implicitly enabled by the PF.
1564          */
1565         if (!conf->rxmode.hw_strip_crc) {
1566                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1567                 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1568                     (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1569                         /* Peer is running non-DPDK PF driver. */
1570                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1571                         return -EINVAL;
1572                 }
1573         }
1574
1575         return i40evf_init_vlan(dev);
1576 }
1577
1578 static int
1579 i40evf_init_vlan(struct rte_eth_dev *dev)
1580 {
1581         struct rte_eth_dev_data *data = dev->data;
1582         int ret;
1583
1584         /* Apply vlan offload setting */
1585         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1586
1587         /* Apply pvid setting */
1588         ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1589                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
1590         return ret;
1591 }
1592
1593 static void
1594 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1595 {
1596         bool enable_vlan_strip = 0;
1597         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1598         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1599
1600         /* Linux pf host doesn't support vlan offload yet */
1601         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1602                 /* Vlan stripping setting */
1603                 if (mask & ETH_VLAN_STRIP_MASK) {
1604                         /* Enable or disable VLAN stripping */
1605                         if (dev_conf->rxmode.hw_vlan_strip)
1606                                 enable_vlan_strip = 1;
1607                         else
1608                                 enable_vlan_strip = 0;
1609
1610                         i40evf_config_vlan_offload(dev, enable_vlan_strip);
1611                 }
1612         }
1613 }
1614
1615 static int
1616 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1617 {
1618         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1619         struct i40e_vsi_vlan_pvid_info info;
1620         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1621
1622         memset(&info, 0, sizeof(info));
1623         info.on = on;
1624
1625         /* Linux pf host don't support vlan offload yet */
1626         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1627                 if (info.on)
1628                         info.config.pvid = pvid;
1629                 else {
1630                         info.config.reject.tagged =
1631                                 dev_conf->txmode.hw_vlan_reject_tagged;
1632                         info.config.reject.untagged =
1633                                 dev_conf->txmode.hw_vlan_reject_untagged;
1634                 }
1635                 return i40evf_config_vlan_pvid(dev, &info);
1636         }
1637
1638         return 0;
1639 }
1640
1641 static int
1642 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1643 {
1644         struct i40e_rx_queue *rxq;
1645         int err = 0;
1646         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1647
1648         PMD_INIT_FUNC_TRACE();
1649
1650         if (rx_queue_id < dev->data->nb_rx_queues) {
1651                 rxq = dev->data->rx_queues[rx_queue_id];
1652
1653                 err = i40e_alloc_rx_queue_mbufs(rxq);
1654                 if (err) {
1655                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1656                         return err;
1657                 }
1658
1659                 rte_wmb();
1660
1661                 /* Init the RX tail register. */
1662                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1663                 I40EVF_WRITE_FLUSH(hw);
1664
1665                 /* Ready to switch the queue on */
1666                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1667
1668                 if (err)
1669                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1670                                     rx_queue_id);
1671                 else
1672                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1673         }
1674
1675         return err;
1676 }
1677
1678 static int
1679 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1680 {
1681         struct i40e_rx_queue *rxq;
1682         int err;
1683
1684         if (rx_queue_id < dev->data->nb_rx_queues) {
1685                 rxq = dev->data->rx_queues[rx_queue_id];
1686
1687                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1688
1689                 if (err) {
1690                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1691                                     rx_queue_id);
1692                         return err;
1693                 }
1694
1695                 i40e_rx_queue_release_mbufs(rxq);
1696                 i40e_reset_rx_queue(rxq);
1697                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1698         }
1699
1700         return 0;
1701 }
1702
1703 static int
1704 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1705 {
1706         int err = 0;
1707
1708         PMD_INIT_FUNC_TRACE();
1709
1710         if (tx_queue_id < dev->data->nb_tx_queues) {
1711
1712                 /* Ready to switch the queue on */
1713                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1714
1715                 if (err)
1716                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1717                                     tx_queue_id);
1718                 else
1719                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1720         }
1721
1722         return err;
1723 }
1724
1725 static int
1726 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1727 {
1728         struct i40e_tx_queue *txq;
1729         int err;
1730
1731         if (tx_queue_id < dev->data->nb_tx_queues) {
1732                 txq = dev->data->tx_queues[tx_queue_id];
1733
1734                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1735
1736                 if (err) {
1737                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1738                                     tx_queue_id);
1739                         return err;
1740                 }
1741
1742                 i40e_tx_queue_release_mbufs(txq);
1743                 i40e_reset_tx_queue(txq);
1744                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1745         }
1746
1747         return 0;
1748 }
1749
1750 static int
1751 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1752 {
1753         int ret;
1754
1755         if (on)
1756                 ret = i40evf_add_vlan(dev, vlan_id);
1757         else
1758                 ret = i40evf_del_vlan(dev,vlan_id);
1759
1760         return ret;
1761 }
1762
1763 static int
1764 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1765 {
1766         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1767         struct rte_eth_dev_data *dev_data = dev->data;
1768         struct rte_pktmbuf_pool_private *mbp_priv;
1769         uint16_t buf_size, len;
1770
1771         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1772         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1773         I40EVF_WRITE_FLUSH(hw);
1774
1775         /* Calculate the maximum packet length allowed */
1776         mbp_priv = rte_mempool_get_priv(rxq->mp);
1777         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1778                                         RTE_PKTMBUF_HEADROOM);
1779         rxq->hs_mode = i40e_header_split_none;
1780         rxq->rx_hdr_len = 0;
1781         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1782         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1783         rxq->max_pkt_len = RTE_MIN(len,
1784                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1785
1786         /**
1787          * Check if the jumbo frame and maximum packet length are set correctly
1788          */
1789         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1790                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1791                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1792                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1793                                 "larger than %u and smaller than %u, as jumbo "
1794                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1795                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1796                         return I40E_ERR_CONFIG;
1797                 }
1798         } else {
1799                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1800                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1801                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1802                                 "larger than %u and smaller than %u, as jumbo "
1803                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1804                                                 (uint32_t)ETHER_MAX_LEN);
1805                         return I40E_ERR_CONFIG;
1806                 }
1807         }
1808
1809         if (dev_data->dev_conf.rxmode.enable_scatter ||
1810             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1811                 dev_data->scattered_rx = 1;
1812         }
1813
1814         return 0;
1815 }
1816
1817 static int
1818 i40evf_rx_init(struct rte_eth_dev *dev)
1819 {
1820         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1821         uint16_t i;
1822         int ret = I40E_SUCCESS;
1823         struct i40e_rx_queue **rxq =
1824                 (struct i40e_rx_queue **)dev->data->rx_queues;
1825
1826         i40evf_config_rss(vf);
1827         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1828                 if (!rxq[i] || !rxq[i]->q_set)
1829                         continue;
1830                 ret = i40evf_rxq_init(dev, rxq[i]);
1831                 if (ret != I40E_SUCCESS)
1832                         break;
1833         }
1834         if (ret == I40E_SUCCESS)
1835                 i40e_set_rx_function(dev);
1836
1837         return ret;
1838 }
1839
1840 static void
1841 i40evf_tx_init(struct rte_eth_dev *dev)
1842 {
1843         uint16_t i;
1844         struct i40e_tx_queue **txq =
1845                 (struct i40e_tx_queue **)dev->data->tx_queues;
1846         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1847
1848         for (i = 0; i < dev->data->nb_tx_queues; i++)
1849                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1850
1851         i40e_set_tx_function(dev);
1852 }
1853
1854 static inline void
1855 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1856 {
1857         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1858         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1859         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1860         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1861
1862         if (!rte_intr_allow_others(intr_handle)) {
1863                 I40E_WRITE_REG(hw,
1864                                I40E_VFINT_DYN_CTL01,
1865                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1866                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1867                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1868                 I40EVF_WRITE_FLUSH(hw);
1869                 return;
1870         }
1871
1872         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1873                 /* To support DPDK PF host */
1874                 I40E_WRITE_REG(hw,
1875                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1876                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1877                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1878         /* If host driver is kernel driver, do nothing.
1879          * Interrupt 0 is used for rx packets, but don't set
1880          * I40E_VFINT_DYN_CTL01,
1881          * because it is already done in i40evf_enable_irq0.
1882          */
1883
1884         I40EVF_WRITE_FLUSH(hw);
1885 }
1886
1887 static inline void
1888 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1889 {
1890         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1891         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1892         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1893         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1894
1895         if (!rte_intr_allow_others(intr_handle)) {
1896                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1897                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1898                 I40EVF_WRITE_FLUSH(hw);
1899                 return;
1900         }
1901
1902         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1903                 I40E_WRITE_REG(hw,
1904                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1905                                                     - 1),
1906                                0);
1907         /* If host driver is kernel driver, do nothing.
1908          * Interrupt 0 is used for rx packets, but don't zero
1909          * I40E_VFINT_DYN_CTL01,
1910          * because interrupt 0 is also used for adminq processing.
1911          */
1912
1913         I40EVF_WRITE_FLUSH(hw);
1914 }
1915
1916 static int
1917 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1918 {
1919         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1920         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1921         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1922         uint16_t interval =
1923                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1924         uint16_t msix_intr;
1925
1926         msix_intr = intr_handle->intr_vec[queue_id];
1927         if (msix_intr == I40E_MISC_VEC_ID)
1928                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1929                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1930                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1931                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1932                                (interval <<
1933                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1934         else
1935                 I40E_WRITE_REG(hw,
1936                                I40E_VFINT_DYN_CTLN1(msix_intr -
1937                                                     I40E_RX_VEC_START),
1938                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1939                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1940                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1941                                (interval <<
1942                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1943
1944         I40EVF_WRITE_FLUSH(hw);
1945
1946         rte_intr_enable(&pci_dev->intr_handle);
1947
1948         return 0;
1949 }
1950
1951 static int
1952 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1953 {
1954         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1955         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1957         uint16_t msix_intr;
1958
1959         msix_intr = intr_handle->intr_vec[queue_id];
1960         if (msix_intr == I40E_MISC_VEC_ID)
1961                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1962         else
1963                 I40E_WRITE_REG(hw,
1964                                I40E_VFINT_DYN_CTLN1(msix_intr -
1965                                                     I40E_RX_VEC_START),
1966                                0);
1967
1968         I40EVF_WRITE_FLUSH(hw);
1969
1970         return 0;
1971 }
1972
1973 static void
1974 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1975 {
1976         struct i40e_virtchnl_ether_addr_list *list;
1977         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1978         int err, i, j;
1979         int next_begin = 0;
1980         int begin = 0;
1981         uint32_t len;
1982         struct ether_addr *addr;
1983         struct vf_cmd_info args;
1984
1985         do {
1986                 j = 0;
1987                 len = sizeof(struct i40e_virtchnl_ether_addr_list);
1988                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1989                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1990                                 continue;
1991                         len += sizeof(struct i40e_virtchnl_ether_addr);
1992                         if (len >= I40E_AQ_BUF_SZ) {
1993                                 next_begin = i + 1;
1994                                 break;
1995                         }
1996                 }
1997
1998                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1999
2000                 for (i = begin; i < next_begin; i++) {
2001                         addr = &dev->data->mac_addrs[i];
2002                         if (is_zero_ether_addr(addr))
2003                                 continue;
2004                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2005                                          sizeof(addr->addr_bytes));
2006                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2007                                     addr->addr_bytes[0], addr->addr_bytes[1],
2008                                     addr->addr_bytes[2], addr->addr_bytes[3],
2009                                     addr->addr_bytes[4], addr->addr_bytes[5]);
2010                         j++;
2011                 }
2012                 list->vsi_id = vf->vsi_res->vsi_id;
2013                 list->num_elements = j;
2014                 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2015                            I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2016                 args.in_args = (uint8_t *)list;
2017                 args.in_args_size = len;
2018                 args.out_buffer = vf->aq_resp;
2019                 args.out_size = I40E_AQ_BUF_SZ;
2020                 err = i40evf_execute_vf_cmd(dev, &args);
2021                 if (err)
2022                         PMD_DRV_LOG(ERR, "fail to execute command %s",
2023                                     add ? "OP_ADD_ETHER_ADDRESS" :
2024                                     "OP_DEL_ETHER_ADDRESS");
2025                 rte_free(list);
2026                 begin = next_begin;
2027         } while (begin < I40E_NUM_MACADDR_MAX);
2028 }
2029
2030 static int
2031 i40evf_dev_start(struct rte_eth_dev *dev)
2032 {
2033         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2034         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2035         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2036         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2037         uint32_t intr_vector = 0;
2038
2039         PMD_INIT_FUNC_TRACE();
2040
2041         hw->adapter_stopped = 0;
2042
2043         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2044         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2045                                         dev->data->nb_tx_queues);
2046
2047         /* check and configure queue intr-vector mapping */
2048         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2049                 intr_vector = dev->data->nb_rx_queues;
2050                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2051                         return -1;
2052         }
2053
2054         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2055                 intr_handle->intr_vec =
2056                         rte_zmalloc("intr_vec",
2057                                     dev->data->nb_rx_queues * sizeof(int), 0);
2058                 if (!intr_handle->intr_vec) {
2059                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2060                                      " intr_vec\n", dev->data->nb_rx_queues);
2061                         return -ENOMEM;
2062                 }
2063         }
2064
2065         if (i40evf_rx_init(dev) != 0){
2066                 PMD_DRV_LOG(ERR, "failed to do RX init");
2067                 return -1;
2068         }
2069
2070         i40evf_tx_init(dev);
2071
2072         if (i40evf_configure_queues(dev) != 0) {
2073                 PMD_DRV_LOG(ERR, "configure queues failed");
2074                 goto err_queue;
2075         }
2076         if (i40evf_config_irq_map(dev)) {
2077                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2078                 goto err_queue;
2079         }
2080
2081         /* Set all mac addrs */
2082         i40evf_add_del_all_mac_addr(dev, TRUE);
2083
2084         if (i40evf_start_queues(dev) != 0) {
2085                 PMD_DRV_LOG(ERR, "enable queues failed");
2086                 goto err_mac;
2087         }
2088
2089         i40evf_enable_queues_intr(dev);
2090         return 0;
2091
2092 err_mac:
2093         i40evf_add_del_all_mac_addr(dev, FALSE);
2094 err_queue:
2095         return -1;
2096 }
2097
2098 static void
2099 i40evf_dev_stop(struct rte_eth_dev *dev)
2100 {
2101         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2102         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2103
2104         PMD_INIT_FUNC_TRACE();
2105
2106         i40evf_stop_queues(dev);
2107         i40evf_disable_queues_intr(dev);
2108         i40e_dev_clear_queues(dev);
2109
2110         /* Clean datapath event and queue/vec mapping */
2111         rte_intr_efd_disable(intr_handle);
2112         if (intr_handle->intr_vec) {
2113                 rte_free(intr_handle->intr_vec);
2114                 intr_handle->intr_vec = NULL;
2115         }
2116         /* remove all mac addrs */
2117         i40evf_add_del_all_mac_addr(dev, FALSE);
2118
2119 }
2120
2121 static int
2122 i40evf_dev_link_update(struct rte_eth_dev *dev,
2123                        __rte_unused int wait_to_complete)
2124 {
2125         struct rte_eth_link new_link;
2126         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2127         /*
2128          * DPDK pf host provide interfacet to acquire link status
2129          * while Linux driver does not
2130          */
2131
2132         /* Linux driver PF host */
2133         switch (vf->link_speed) {
2134         case I40E_LINK_SPEED_100MB:
2135                 new_link.link_speed = ETH_SPEED_NUM_100M;
2136                 break;
2137         case I40E_LINK_SPEED_1GB:
2138                 new_link.link_speed = ETH_SPEED_NUM_1G;
2139                 break;
2140         case I40E_LINK_SPEED_10GB:
2141                 new_link.link_speed = ETH_SPEED_NUM_10G;
2142                 break;
2143         case I40E_LINK_SPEED_20GB:
2144                 new_link.link_speed = ETH_SPEED_NUM_20G;
2145                 break;
2146         case I40E_LINK_SPEED_40GB:
2147                 new_link.link_speed = ETH_SPEED_NUM_40G;
2148                 break;
2149         default:
2150                 new_link.link_speed = ETH_SPEED_NUM_100M;
2151                 break;
2152         }
2153         /* full duplex only */
2154         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2155         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2156                                              ETH_LINK_DOWN;
2157
2158         i40evf_dev_atomic_write_link_status(dev, &new_link);
2159
2160         return 0;
2161 }
2162
2163 static void
2164 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2165 {
2166         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2167         int ret;
2168
2169         /* If enabled, just return */
2170         if (vf->promisc_unicast_enabled)
2171                 return;
2172
2173         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2174         if (ret == 0)
2175                 vf->promisc_unicast_enabled = TRUE;
2176 }
2177
2178 static void
2179 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2180 {
2181         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2182         int ret;
2183
2184         /* If disabled, just return */
2185         if (!vf->promisc_unicast_enabled)
2186                 return;
2187
2188         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2189         if (ret == 0)
2190                 vf->promisc_unicast_enabled = FALSE;
2191 }
2192
2193 static void
2194 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2195 {
2196         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2197         int ret;
2198
2199         /* If enabled, just return */
2200         if (vf->promisc_multicast_enabled)
2201                 return;
2202
2203         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2204         if (ret == 0)
2205                 vf->promisc_multicast_enabled = TRUE;
2206 }
2207
2208 static void
2209 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2210 {
2211         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2212         int ret;
2213
2214         /* If enabled, just return */
2215         if (!vf->promisc_multicast_enabled)
2216                 return;
2217
2218         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2219         if (ret == 0)
2220                 vf->promisc_multicast_enabled = FALSE;
2221 }
2222
2223 static void
2224 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2225 {
2226         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2227
2228         memset(dev_info, 0, sizeof(*dev_info));
2229         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2230         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2231         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2232         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2233         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2234         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2235         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2236         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2237         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2238         dev_info->rx_offload_capa =
2239                 DEV_RX_OFFLOAD_VLAN_STRIP |
2240                 DEV_RX_OFFLOAD_QINQ_STRIP |
2241                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2242                 DEV_RX_OFFLOAD_UDP_CKSUM |
2243                 DEV_RX_OFFLOAD_TCP_CKSUM;
2244         dev_info->tx_offload_capa =
2245                 DEV_TX_OFFLOAD_VLAN_INSERT |
2246                 DEV_TX_OFFLOAD_QINQ_INSERT |
2247                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2248                 DEV_TX_OFFLOAD_UDP_CKSUM |
2249                 DEV_TX_OFFLOAD_TCP_CKSUM |
2250                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2251
2252         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2253                 .rx_thresh = {
2254                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2255                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2256                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2257                 },
2258                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2259                 .rx_drop_en = 0,
2260         };
2261
2262         dev_info->default_txconf = (struct rte_eth_txconf) {
2263                 .tx_thresh = {
2264                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2265                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2266                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2267                 },
2268                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2269                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2270                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2271                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2272         };
2273
2274         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2275                 .nb_max = I40E_MAX_RING_DESC,
2276                 .nb_min = I40E_MIN_RING_DESC,
2277                 .nb_align = I40E_ALIGN_RING_DESC,
2278         };
2279
2280         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2281                 .nb_max = I40E_MAX_RING_DESC,
2282                 .nb_min = I40E_MIN_RING_DESC,
2283                 .nb_align = I40E_ALIGN_RING_DESC,
2284         };
2285 }
2286
2287 static void
2288 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2289 {
2290         if (i40evf_get_statics(dev, stats))
2291                 PMD_DRV_LOG(ERR, "Get statics failed");
2292 }
2293
2294 static void
2295 i40evf_dev_close(struct rte_eth_dev *dev)
2296 {
2297         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2298         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2299         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2300
2301         i40evf_dev_stop(dev);
2302         hw->adapter_stopped = 1;
2303         i40e_dev_free_queues(dev);
2304         i40evf_reset_vf(hw);
2305         i40e_shutdown_adminq(hw);
2306         /* disable uio intr before callback unregister */
2307         rte_intr_disable(intr_handle);
2308
2309         /* unregister callback func from eal lib */
2310         rte_intr_callback_unregister(intr_handle,
2311                                      i40evf_dev_interrupt_handler, dev);
2312         i40evf_disable_irq0(hw);
2313 }
2314
2315 static int
2316 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2317 {
2318         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2319         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2320         int ret;
2321
2322         if (!lut)
2323                 return -EINVAL;
2324
2325         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2326                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2327                                           lut, lut_size);
2328                 if (ret) {
2329                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2330                         return ret;
2331                 }
2332         } else {
2333                 uint32_t *lut_dw = (uint32_t *)lut;
2334                 uint16_t i, lut_size_dw = lut_size / 4;
2335
2336                 for (i = 0; i < lut_size_dw; i++)
2337                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2338         }
2339
2340         return 0;
2341 }
2342
2343 static int
2344 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2345 {
2346         struct i40e_vf *vf;
2347         struct i40e_hw *hw;
2348         int ret;
2349
2350         if (!vsi || !lut)
2351                 return -EINVAL;
2352
2353         vf = I40E_VSI_TO_VF(vsi);
2354         hw = I40E_VSI_TO_HW(vsi);
2355
2356         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2357                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2358                                           lut, lut_size);
2359                 if (ret) {
2360                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2361                         return ret;
2362                 }
2363         } else {
2364                 uint32_t *lut_dw = (uint32_t *)lut;
2365                 uint16_t i, lut_size_dw = lut_size / 4;
2366
2367                 for (i = 0; i < lut_size_dw; i++)
2368                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2369                 I40EVF_WRITE_FLUSH(hw);
2370         }
2371
2372         return 0;
2373 }
2374
2375 static int
2376 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2377                            struct rte_eth_rss_reta_entry64 *reta_conf,
2378                            uint16_t reta_size)
2379 {
2380         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2381         uint8_t *lut;
2382         uint16_t i, idx, shift;
2383         int ret;
2384
2385         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2386                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2387                         "(%d) doesn't match the number of hardware can "
2388                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2389                 return -EINVAL;
2390         }
2391
2392         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2393         if (!lut) {
2394                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2395                 return -ENOMEM;
2396         }
2397         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2398         if (ret)
2399                 goto out;
2400         for (i = 0; i < reta_size; i++) {
2401                 idx = i / RTE_RETA_GROUP_SIZE;
2402                 shift = i % RTE_RETA_GROUP_SIZE;
2403                 if (reta_conf[idx].mask & (1ULL << shift))
2404                         lut[i] = reta_conf[idx].reta[shift];
2405         }
2406         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2407
2408 out:
2409         rte_free(lut);
2410
2411         return ret;
2412 }
2413
2414 static int
2415 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2416                           struct rte_eth_rss_reta_entry64 *reta_conf,
2417                           uint16_t reta_size)
2418 {
2419         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2420         uint16_t i, idx, shift;
2421         uint8_t *lut;
2422         int ret;
2423
2424         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2425                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2426                         "(%d) doesn't match the number of hardware can "
2427                         "support (%d)\n", reta_size, ETH_RSS_RETA_SIZE_64);
2428                 return -EINVAL;
2429         }
2430
2431         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2432         if (!lut) {
2433                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2434                 return -ENOMEM;
2435         }
2436
2437         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2438         if (ret)
2439                 goto out;
2440         for (i = 0; i < reta_size; i++) {
2441                 idx = i / RTE_RETA_GROUP_SIZE;
2442                 shift = i % RTE_RETA_GROUP_SIZE;
2443                 if (reta_conf[idx].mask & (1ULL << shift))
2444                         reta_conf[idx].reta[shift] = lut[i];
2445         }
2446
2447 out:
2448         rte_free(lut);
2449
2450         return ret;
2451 }
2452
2453 static int
2454 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2455 {
2456         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2457         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2458         int ret = 0;
2459
2460         if (!key || key_len == 0) {
2461                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2462                 return 0;
2463         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2464                 sizeof(uint32_t)) {
2465                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2466                 return -EINVAL;
2467         }
2468
2469         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2470                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2471                         (struct i40e_aqc_get_set_rss_key_data *)key;
2472
2473                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2474                 if (ret)
2475                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2476                                      "via AQ");
2477         } else {
2478                 uint32_t *hash_key = (uint32_t *)key;
2479                 uint16_t i;
2480
2481                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2482                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2483                 I40EVF_WRITE_FLUSH(hw);
2484         }
2485
2486         return ret;
2487 }
2488
2489 static int
2490 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2491 {
2492         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2493         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2494         int ret;
2495
2496         if (!key || !key_len)
2497                 return -EINVAL;
2498
2499         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2500                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2501                         (struct i40e_aqc_get_set_rss_key_data *)key);
2502                 if (ret) {
2503                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2504                         return ret;
2505                 }
2506         } else {
2507                 uint32_t *key_dw = (uint32_t *)key;
2508                 uint16_t i;
2509
2510                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2511                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2512         }
2513         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2514
2515         return 0;
2516 }
2517
2518 static int
2519 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2520 {
2521         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2522         uint64_t rss_hf, hena;
2523         int ret;
2524
2525         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2526                                  rss_conf->rss_key_len);
2527         if (ret)
2528                 return ret;
2529
2530         rss_hf = rss_conf->rss_hf;
2531         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2532         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2533         if (hw->mac.type == I40E_MAC_X722)
2534                 hena &= ~I40E_RSS_HENA_ALL_X722;
2535         else
2536                 hena &= ~I40E_RSS_HENA_ALL;
2537         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2538         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2539         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2540         I40EVF_WRITE_FLUSH(hw);
2541
2542         return 0;
2543 }
2544
2545 static void
2546 i40evf_disable_rss(struct i40e_vf *vf)
2547 {
2548         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2549         uint64_t hena;
2550
2551         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2552         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2553         if (hw->mac.type == I40E_MAC_X722)
2554                 hena &= ~I40E_RSS_HENA_ALL_X722;
2555         else
2556                 hena &= ~I40E_RSS_HENA_ALL;
2557         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2558         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2559         I40EVF_WRITE_FLUSH(hw);
2560 }
2561
2562 static int
2563 i40evf_config_rss(struct i40e_vf *vf)
2564 {
2565         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2566         struct rte_eth_rss_conf rss_conf;
2567         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2568         uint16_t num;
2569
2570         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2571                 i40evf_disable_rss(vf);
2572                 PMD_DRV_LOG(DEBUG, "RSS not configured\n");
2573                 return 0;
2574         }
2575
2576         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2577         /* Fill out the look up table */
2578         for (i = 0, j = 0; i < nb_q; i++, j++) {
2579                 if (j >= num)
2580                         j = 0;
2581                 lut = (lut << 8) | j;
2582                 if ((i & 3) == 3)
2583                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2584         }
2585
2586         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2587         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2588                 i40evf_disable_rss(vf);
2589                 PMD_DRV_LOG(DEBUG, "No hash flag is set\n");
2590                 return 0;
2591         }
2592
2593         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2594                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2595                 /* Calculate the default hash key */
2596                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2597                         rss_key_default[i] = (uint32_t)rte_rand();
2598                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2599                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2600                         sizeof(uint32_t);
2601         }
2602
2603         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2604 }
2605
2606 static int
2607 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2608                            struct rte_eth_rss_conf *rss_conf)
2609 {
2610         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2611         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2612         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2613         uint64_t hena;
2614
2615         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2616         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2617         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2618                  ? I40E_RSS_HENA_ALL_X722
2619                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2620                 if (rss_hf != 0) /* Enable RSS */
2621                         return -EINVAL;
2622                 return 0;
2623         }
2624
2625         /* RSS enabled */
2626         if (rss_hf == 0) /* Disable RSS */
2627                 return -EINVAL;
2628
2629         return i40evf_hw_rss_hash_set(vf, rss_conf);
2630 }
2631
2632 static int
2633 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2634                              struct rte_eth_rss_conf *rss_conf)
2635 {
2636         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2637         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2638         uint64_t hena;
2639
2640         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2641                            &rss_conf->rss_key_len);
2642
2643         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2644         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2645         rss_conf->rss_hf = i40e_parse_hena(hena);
2646
2647         return 0;
2648 }