drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static void i40evf_dev_close(struct rte_eth_dev *dev);
 123 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 130                                      uint16_t rx_queue_id);
 131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 132                                     uint16_t rx_queue_id);
 133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 134                                      uint16_t tx_queue_id);
 135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 136                                     uint16_t tx_queue_id);
 137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 138                                struct ether_addr *addr,
 139                                uint32_t index,
 140                                uint32_t pool);
 141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 143                         struct rte_eth_rss_reta_entry64 *reta_conf,
 144                         uint16_t reta_size);
 145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                         struct rte_eth_rss_reta_entry64 *reta_conf,
 147                         uint16_t reta_size);
 148 static int i40evf_config_rss(struct i40e_vf *vf);
 149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 150                                       struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 152                                         struct rte_eth_rss_conf *rss_conf);
 153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 155                                         struct ether_addr *mac_addr);
 156 static int
 157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static int
 159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 161                                    uint8_t *msg,
 162                                    uint16_t msglen);
 163
 164 /* Default hash key buffer for RSS */
 165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 166
 167 struct rte_i40evf_xstats_name_off {
 168         char name[RTE_ETH_XSTATS_NAME_SIZE];
 169         unsigned offset;
 170 };
 171
 172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 173         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 174         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 175         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 176         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 177         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 178         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 179                 rx_unknown_protocol)},
 180         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 182         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 183         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 184         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 185         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 186 };
 187
 188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 189                 sizeof(rte_i40evf_stats_strings[0]))
 190
 191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 192         .dev_configure        = i40evf_dev_configure,
 193         .dev_start            = i40evf_dev_start,
 194         .dev_stop             = i40evf_dev_stop,
 195         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 196         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 197         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 198         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 199         .link_update          = i40evf_dev_link_update,
 200         .stats_get            = i40evf_dev_stats_get,
 201         .xstats_get           = i40evf_dev_xstats_get,
 202         .xstats_get_names     = i40evf_dev_xstats_get_names,
 203         .xstats_reset         = i40evf_dev_xstats_reset,
 204         .dev_close            = i40evf_dev_close,
 205         .dev_reset            = i40evf_dev_reset,
 206         .dev_infos_get        = i40evf_dev_info_get,
 207         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 208         .vlan_filter_set      = i40evf_vlan_filter_set,
 209         .vlan_offload_set     = i40evf_vlan_offload_set,
 210         .rx_queue_start       = i40evf_dev_rx_queue_start,
 211         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 212         .tx_queue_start       = i40evf_dev_tx_queue_start,
 213         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 214         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 215         .rx_queue_release     = i40e_dev_rx_queue_release,
 216         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 217         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 218         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 219         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 220         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 221         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 222         .tx_queue_release     = i40e_dev_tx_queue_release,
 223         .rx_queue_count       = i40e_dev_rx_queue_count,
 224         .rxq_info_get         = i40e_rxq_info_get,
 225         .txq_info_get         = i40e_txq_info_get,
 226         .mac_addr_add         = i40evf_add_mac_addr,
 227         .mac_addr_remove      = i40evf_del_mac_addr,
 228         .reta_update          = i40evf_dev_rss_reta_update,
 229         .reta_query           = i40evf_dev_rss_reta_query,
 230         .rss_hash_update      = i40evf_dev_rss_hash_update,
 231         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 232         .mtu_set              = i40evf_dev_mtu_set,
 233         .mac_addr_set         = i40evf_set_default_mac_addr,
 234 };
 235
 236 /*
 237  * Read data in admin queue to get msg from pf driver
 238  */
 239 static enum i40evf_aq_result
 240 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 241 {
 242         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 243         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 244         struct i40e_arq_event_info event;
 245         enum virtchnl_ops opcode;
 246         enum i40e_status_code retval;
 247         int ret;
 248         enum i40evf_aq_result result = I40EVF_MSG_NON;
 249
 250         event.buf_len = data->buf_len;
 251         event.msg_buf = data->msg;
 252         ret = i40e_clean_arq_element(hw, &event, NULL);
 253         /* Can't read any msg from adminQ */
 254         if (ret) {
 255                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 256                         result = I40EVF_MSG_ERR;
 257                 return result;
 258         }
 259
 260         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 261         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 262         /* pf sys event */
 263         if (opcode == VIRTCHNL_OP_EVENT) {
 264                 struct virtchnl_pf_event *vpe =
 265                         (struct virtchnl_pf_event *)event.msg_buf;
 266
 267                 result = I40EVF_MSG_SYS;
 268                 switch (vpe->event) {
 269                 case VIRTCHNL_EVENT_LINK_CHANGE:
 270                         vf->link_up =
 271                                 vpe->event_data.link_event.link_status;
 272                         vf->link_speed =
 273                                 vpe->event_data.link_event.link_speed;
 274                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 275                         PMD_DRV_LOG(INFO, "Link status update:%s",
 276                                     vf->link_up ? "up" : "down");
 277                         break;
 278                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 279                         vf->vf_reset = true;
 280                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 281                         PMD_DRV_LOG(INFO, "vf is reseting");
 282                         break;
 283                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 284                         vf->dev_closed = true;
 285                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 286                         PMD_DRV_LOG(INFO, "PF driver closed");
 287                         break;
 288                 default:
 289                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 290                                     __func__, vpe->event);
 291                 }
 292         } else {
 293                 /* async reply msg on command issued by vf previously */
 294                 result = I40EVF_MSG_CMD;
 295                 /* Actual data length read from PF */
 296                 data->msg_len = event.msg_len;
 297         }
 298
 299         data->result = retval;
 300         data->ops = opcode;
 301
 302         return result;
 303 }
 304
 305 /**
 306  * clear current command. Only call in case execute
 307  * _atomic_set_cmd successfully.
 308  */
 309 static inline void
 310 _clear_cmd(struct i40e_vf *vf)
 311 {
 312         rte_wmb();
 313         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 314 }
 315
 316 /*
 317  * Check there is pending cmd in execution. If none, set new command.
 318  */
 319 static inline int
 320 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 321 {
 322         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 323                         VIRTCHNL_OP_UNKNOWN, ops);
 324
 325         if (!ret)
 326                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 327
 328         return !ret;
 329 }
 330
 331 #define MAX_TRY_TIMES 200
 332 #define ASQ_DELAY_MS  10
 333
 334 static int
 335 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 336 {
 337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 338         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 339         struct i40evf_arq_msg_info info;
 340         enum i40evf_aq_result ret;
 341         int err, i = 0;
 342
 343         if (_atomic_set_cmd(vf, args->ops))
 344                 return -1;
 345
 346         info.msg = args->out_buffer;
 347         info.buf_len = args->out_size;
 348         info.ops = VIRTCHNL_OP_UNKNOWN;
 349         info.result = I40E_SUCCESS;
 350
 351         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 352                      args->in_args, args->in_args_size, NULL);
 353         if (err) {
 354                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 355                 _clear_cmd(vf);
 356                 return err;
 357         }
 358
 359         switch (args->ops) {
 360         case VIRTCHNL_OP_RESET_VF:
 361                 /*no need to process in this function */
 362                 err = 0;
 363                 break;
 364         case VIRTCHNL_OP_VERSION:
 365         case VIRTCHNL_OP_GET_VF_RESOURCES:
 366                 /* for init adminq commands, need to poll the response */
 367                 err = -1;
 368                 do {
 369                         ret = i40evf_read_pfmsg(dev, &info);
 370                         vf->cmd_retval = info.result;
 371                         if (ret == I40EVF_MSG_CMD) {
 372                                 err = 0;
 373                                 break;
 374                         } else if (ret == I40EVF_MSG_ERR)
 375                                 break;
 376                         rte_delay_ms(ASQ_DELAY_MS);
 377                         /* If don't read msg or read sys event, continue */
 378                 } while (i++ < MAX_TRY_TIMES);
 379                 _clear_cmd(vf);
 380                 break;
 381
 382         default:
 383                 /* for other adminq in running time, waiting the cmd done flag */
 384                 err = -1;
 385                 do {
 386                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 387                                 err = 0;
 388                                 break;
 389                         }
 390                         rte_delay_ms(ASQ_DELAY_MS);
 391                         /* If don't read msg or read sys event, continue */
 392                 } while (i++ < MAX_TRY_TIMES);
 393                 /* If there's no response is received, clear command */
 394                 if (i >= MAX_TRY_TIMES) {
 395                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 396                         _clear_cmd(vf);
 397                 }
 398                 break;
 399         }
 400
 401         return err | vf->cmd_retval;
 402 }
 403
 404 /*
 405  * Check API version with sync wait until version read or fail from admin queue
 406  */
 407 static int
 408 i40evf_check_api_version(struct rte_eth_dev *dev)
 409 {
 410         struct virtchnl_version_info version, *pver;
 411         int err;
 412         struct vf_cmd_info args;
 413         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 414
 415         version.major = VIRTCHNL_VERSION_MAJOR;
 416         version.minor = VIRTCHNL_VERSION_MINOR;
 417
 418         args.ops = VIRTCHNL_OP_VERSION;
 419         args.in_args = (uint8_t *)&version;
 420         args.in_args_size = sizeof(version);
 421         args.out_buffer = vf->aq_resp;
 422         args.out_size = I40E_AQ_BUF_SZ;
 423
 424         err = i40evf_execute_vf_cmd(dev, &args);
 425         if (err) {
 426                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 427                 return err;
 428         }
 429
 430         pver = (struct virtchnl_version_info *)args.out_buffer;
 431         vf->version_major = pver->major;
 432         vf->version_minor = pver->minor;
 433         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 434                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 435         else if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 436                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 437                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 438         else {
 439                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 440                                         vf->version_major, vf->version_minor,
 441                                                 VIRTCHNL_VERSION_MAJOR,
 442                                                 VIRTCHNL_VERSION_MINOR);
 443                 return -1;
 444         }
 445
 446         return 0;
 447 }
 448
 449 static int
 450 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 451 {
 452         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 453         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 454         int err;
 455         struct vf_cmd_info args;
 456         uint32_t caps, len;
 457
 458         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 459         args.out_buffer = vf->aq_resp;
 460         args.out_size = I40E_AQ_BUF_SZ;
 461         if (PF_IS_V11(vf)) {
 462                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 463                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 464                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 465                        VIRTCHNL_VF_OFFLOAD_VLAN |
 466                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 467                 args.in_args = (uint8_t *)&caps;
 468                 args.in_args_size = sizeof(caps);
 469         } else {
 470                 args.in_args = NULL;
 471                 args.in_args_size = 0;
 472         }
 473         err = i40evf_execute_vf_cmd(dev, &args);
 474
 475         if (err) {
 476                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 477                 return err;
 478         }
 479
 480         len =  sizeof(struct virtchnl_vf_resource) +
 481                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 482
 483         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 484                         RTE_MIN(args.out_size, len));
 485         i40e_vf_parse_hw_config(hw, vf->vf_res);
 486
 487         return 0;
 488 }
 489
 490 static int
 491 i40evf_config_promisc(struct rte_eth_dev *dev,
 492                       bool enable_unicast,
 493                       bool enable_multicast)
 494 {
 495         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 496         int err;
 497         struct vf_cmd_info args;
 498         struct virtchnl_promisc_info promisc;
 499
 500         promisc.flags = 0;
 501         promisc.vsi_id = vf->vsi_res->vsi_id;
 502
 503         if (enable_unicast)
 504                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 505
 506         if (enable_multicast)
 507                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 508
 509         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 510         args.in_args = (uint8_t *)&promisc;
 511         args.in_args_size = sizeof(promisc);
 512         args.out_buffer = vf->aq_resp;
 513         args.out_size = I40E_AQ_BUF_SZ;
 514
 515         err = i40evf_execute_vf_cmd(dev, &args);
 516
 517         if (err)
 518                 PMD_DRV_LOG(ERR, "fail to execute command "
 519                             "CONFIG_PROMISCUOUS_MODE");
 520         return err;
 521 }
 522
 523 static int
 524 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 525 {
 526         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 527         struct vf_cmd_info args;
 528         int ret;
 529
 530         memset(&args, 0, sizeof(args));
 531         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 532         args.in_args = NULL;
 533         args.in_args_size = 0;
 534         args.out_buffer = vf->aq_resp;
 535         args.out_size = I40E_AQ_BUF_SZ;
 536         ret = i40evf_execute_vf_cmd(dev, &args);
 537         if (ret)
 538                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 539                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 540
 541         return ret;
 542 }
 543
 544 static int
 545 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 546 {
 547         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 548         struct vf_cmd_info args;
 549         int ret;
 550
 551         memset(&args, 0, sizeof(args));
 552         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 553         args.in_args = NULL;
 554         args.in_args_size = 0;
 555         args.out_buffer = vf->aq_resp;
 556         args.out_size = I40E_AQ_BUF_SZ;
 557         ret = i40evf_execute_vf_cmd(dev, &args);
 558         if (ret)
 559                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 560                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 561
 562         return ret;
 563 }
 564
 565 static void
 566 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 567                                   uint16_t vsi_id,
 568                                   uint16_t queue_id,
 569                                   uint16_t nb_txq,
 570                                   struct i40e_tx_queue *txq)
 571 {
 572         txq_info->vsi_id = vsi_id;
 573         txq_info->queue_id = queue_id;
 574         if (queue_id < nb_txq) {
 575                 txq_info->ring_len = txq->nb_tx_desc;
 576                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 577         }
 578 }
 579
 580 static void
 581 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 582                                   uint16_t vsi_id,
 583                                   uint16_t queue_id,
 584                                   uint16_t nb_rxq,
 585                                   uint32_t max_pkt_size,
 586                                   struct i40e_rx_queue *rxq)
 587 {
 588         rxq_info->vsi_id = vsi_id;
 589         rxq_info->queue_id = queue_id;
 590         rxq_info->max_pkt_size = max_pkt_size;
 591         if (queue_id < nb_rxq) {
 592                 rxq_info->ring_len = rxq->nb_rx_desc;
 593                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 594                 rxq_info->databuffer_size =
 595                         (rte_pktmbuf_data_room_size(rxq->mp) -
 596                                 RTE_PKTMBUF_HEADROOM);
 597         }
 598 }
 599
 600 static int
 601 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 602 {
 603         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 604         struct i40e_rx_queue **rxq =
 605                 (struct i40e_rx_queue **)dev->data->rx_queues;
 606         struct i40e_tx_queue **txq =
 607                 (struct i40e_tx_queue **)dev->data->tx_queues;
 608         struct virtchnl_vsi_queue_config_info *vc_vqci;
 609         struct virtchnl_queue_pair_info *vc_qpi;
 610         struct vf_cmd_info args;
 611         uint16_t i, nb_qp = vf->num_queue_pairs;
 612         const uint32_t size =
 613                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 614         uint8_t buff[size];
 615         int ret;
 616
 617         memset(buff, 0, sizeof(buff));
 618         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 619         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 620         vc_vqci->num_queue_pairs = nb_qp;
 621
 622         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 623                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 624                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 625                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 626                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 627                                         vf->max_pkt_len, rxq[i]);
 628         }
 629         memset(&args, 0, sizeof(args));
 630         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 631         args.in_args = (uint8_t *)vc_vqci;
 632         args.in_args_size = size;
 633         args.out_buffer = vf->aq_resp;
 634         args.out_size = I40E_AQ_BUF_SZ;
 635         ret = i40evf_execute_vf_cmd(dev, &args);
 636         if (ret)
 637                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 638                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 639
 640         return ret;
 641 }
 642
 643 static int
 644 i40evf_config_irq_map(struct rte_eth_dev *dev)
 645 {
 646         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 647         struct vf_cmd_info args;
 648         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 649                 sizeof(struct virtchnl_vector_map)];
 650         struct virtchnl_irq_map_info *map_info;
 651         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 652         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 653         uint32_t vector_id;
 654         int i, err;
 655
 656         if (rte_intr_allow_others(intr_handle)) {
 657                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 658                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 659                 else
 660                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 661         } else {
 662                 vector_id = I40E_MISC_VEC_ID;
 663         }
 664
 665         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 666         map_info->num_vectors = 1;
 667         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 668         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 669         /* Alway use default dynamic MSIX interrupt */
 670         map_info->vecmap[0].vector_id = vector_id;
 671         /* Don't map any tx queue */
 672         map_info->vecmap[0].txq_map = 0;
 673         map_info->vecmap[0].rxq_map = 0;
 674         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 675                 map_info->vecmap[0].rxq_map |= 1 << i;
 676                 if (rte_intr_dp_is_en(intr_handle))
 677                         intr_handle->intr_vec[i] = vector_id;
 678         }
 679
 680         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 681         args.in_args = (u8 *)cmd_buffer;
 682         args.in_args_size = sizeof(cmd_buffer);
 683         args.out_buffer = vf->aq_resp;
 684         args.out_size = I40E_AQ_BUF_SZ;
 685         err = i40evf_execute_vf_cmd(dev, &args);
 686         if (err)
 687                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 688
 689         return err;
 690 }
 691
 692 static int
 693 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 694                                 bool on)
 695 {
 696         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 697         struct virtchnl_queue_select queue_select;
 698         int err;
 699         struct vf_cmd_info args;
 700         memset(&queue_select, 0, sizeof(queue_select));
 701         queue_select.vsi_id = vf->vsi_res->vsi_id;
 702
 703         if (isrx)
 704                 queue_select.rx_queues |= 1 << qid;
 705         else
 706                 queue_select.tx_queues |= 1 << qid;
 707
 708         if (on)
 709                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 710         else
 711                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 712         args.in_args = (u8 *)&queue_select;
 713         args.in_args_size = sizeof(queue_select);
 714         args.out_buffer = vf->aq_resp;
 715         args.out_size = I40E_AQ_BUF_SZ;
 716         err = i40evf_execute_vf_cmd(dev, &args);
 717         if (err)
 718                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 719                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 720
 721         return err;
 722 }
 723
 724 static int
 725 i40evf_start_queues(struct rte_eth_dev *dev)
 726 {
 727         struct rte_eth_dev_data *dev_data = dev->data;
 728         int i;
 729         struct i40e_rx_queue *rxq;
 730         struct i40e_tx_queue *txq;
 731
 732         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 733                 rxq = dev_data->rx_queues[i];
 734                 if (rxq->rx_deferred_start)
 735                         continue;
 736                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 737                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 738                         return -1;
 739                 }
 740         }
 741
 742         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 743                 txq = dev_data->tx_queues[i];
 744                 if (txq->tx_deferred_start)
 745                         continue;
 746                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 747                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 748                         return -1;
 749                 }
 750         }
 751
 752         return 0;
 753 }
 754
 755 static int
 756 i40evf_stop_queues(struct rte_eth_dev *dev)
 757 {
 758         int i;
 759
 760         /* Stop TX queues first */
 761         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 762                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 763                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 764                         return -1;
 765                 }
 766         }
 767
 768         /* Then stop RX queues */
 769         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 770                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 771                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 772                         return -1;
 773                 }
 774         }
 775
 776         return 0;
 777 }
 778
 779 static int
 780 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 781                     struct ether_addr *addr,
 782                     __rte_unused uint32_t index,
 783                     __rte_unused uint32_t pool)
 784 {
 785         struct virtchnl_ether_addr_list *list;
 786         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 787         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 788                         sizeof(struct virtchnl_ether_addr)];
 789         int err;
 790         struct vf_cmd_info args;
 791
 792         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 793                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 794                             addr->addr_bytes[0], addr->addr_bytes[1],
 795                             addr->addr_bytes[2], addr->addr_bytes[3],
 796                             addr->addr_bytes[4], addr->addr_bytes[5]);
 797                 return I40E_ERR_INVALID_MAC_ADDR;
 798         }
 799
 800         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 801         list->vsi_id = vf->vsi_res->vsi_id;
 802         list->num_elements = 1;
 803         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 804                                         sizeof(addr->addr_bytes));
 805
 806         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 807         args.in_args = cmd_buffer;
 808         args.in_args_size = sizeof(cmd_buffer);
 809         args.out_buffer = vf->aq_resp;
 810         args.out_size = I40E_AQ_BUF_SZ;
 811         err = i40evf_execute_vf_cmd(dev, &args);
 812         if (err)
 813                 PMD_DRV_LOG(ERR, "fail to execute command "
 814                             "OP_ADD_ETHER_ADDRESS");
 815         else
 816                 vf->vsi.mac_num++;
 817
 818         return err;
 819 }
 820
 821 static void
 822 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 823                             struct ether_addr *addr)
 824 {
 825         struct virtchnl_ether_addr_list *list;
 826         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 827         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 828                         sizeof(struct virtchnl_ether_addr)];
 829         int err;
 830         struct vf_cmd_info args;
 831
 832         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 833                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 834                             addr->addr_bytes[0], addr->addr_bytes[1],
 835                             addr->addr_bytes[2], addr->addr_bytes[3],
 836                             addr->addr_bytes[4], addr->addr_bytes[5]);
 837                 return;
 838         }
 839
 840         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 841         list->vsi_id = vf->vsi_res->vsi_id;
 842         list->num_elements = 1;
 843         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 844                         sizeof(addr->addr_bytes));
 845
 846         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 847         args.in_args = cmd_buffer;
 848         args.in_args_size = sizeof(cmd_buffer);
 849         args.out_buffer = vf->aq_resp;
 850         args.out_size = I40E_AQ_BUF_SZ;
 851         err = i40evf_execute_vf_cmd(dev, &args);
 852         if (err)
 853                 PMD_DRV_LOG(ERR, "fail to execute command "
 854                             "OP_DEL_ETHER_ADDRESS");
 855         else
 856                 vf->vsi.mac_num--;
 857         return;
 858 }
 859
 860 static void
 861 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 862 {
 863         struct rte_eth_dev_data *data = dev->data;
 864         struct ether_addr *addr;
 865
 866         addr = &data->mac_addrs[index];
 867
 868         i40evf_del_mac_addr_by_addr(dev, addr);
 869 }
 870
 871 static int
 872 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 873 {
 874         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 875         struct virtchnl_queue_select q_stats;
 876         int err;
 877         struct vf_cmd_info args;
 878
 879         memset(&q_stats, 0, sizeof(q_stats));
 880         q_stats.vsi_id = vf->vsi_res->vsi_id;
 881         args.ops = VIRTCHNL_OP_GET_STATS;
 882         args.in_args = (u8 *)&q_stats;
 883         args.in_args_size = sizeof(q_stats);
 884         args.out_buffer = vf->aq_resp;
 885         args.out_size = I40E_AQ_BUF_SZ;
 886
 887         err = i40evf_execute_vf_cmd(dev, &args);
 888         if (err) {
 889                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 890                 *pstats = NULL;
 891                 return err;
 892         }
 893         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 894         return 0;
 895 }
 896
 897 static int
 898 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 899 {
 900         int ret;
 901         struct i40e_eth_stats *pstats = NULL;
 902
 903         ret = i40evf_update_stats(dev, &pstats);
 904         if (ret != 0)
 905                 return 0;
 906
 907         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 908                                                 pstats->rx_broadcast;
 909         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 910                                                 pstats->tx_unicast;
 911         stats->imissed = pstats->rx_discards;
 912         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 913         stats->ibytes = pstats->rx_bytes;
 914         stats->obytes = pstats->tx_bytes;
 915
 916         return 0;
 917 }
 918
 919 static void
 920 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 921 {
 922         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 923         struct i40e_eth_stats *pstats = NULL;
 924
 925         /* read stat values to clear hardware registers */
 926         i40evf_update_stats(dev, &pstats);
 927
 928         /* set stats offset base on current values */
 929         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
 930 }
 931
 932 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 933                                       struct rte_eth_xstat_name *xstats_names,
 934                                       __rte_unused unsigned limit)
 935 {
 936         unsigned i;
 937
 938         if (xstats_names != NULL)
 939                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 940                         snprintf(xstats_names[i].name,
 941                                 sizeof(xstats_names[i].name),
 942                                 "%s", rte_i40evf_stats_strings[i].name);
 943                 }
 944         return I40EVF_NB_XSTATS;
 945 }
 946
 947 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 948                                  struct rte_eth_xstat *xstats, unsigned n)
 949 {
 950         int ret;
 951         unsigned i;
 952         struct i40e_eth_stats *pstats = NULL;
 953
 954         if (n < I40EVF_NB_XSTATS)
 955                 return I40EVF_NB_XSTATS;
 956
 957         ret = i40evf_update_stats(dev, &pstats);
 958         if (ret != 0)
 959                 return 0;
 960
 961         if (!xstats)
 962                 return 0;
 963
 964         /* loop over xstats array and values from pstats */
 965         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 966                 xstats[i].id = i;
 967                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
 968                         rte_i40evf_stats_strings[i].offset);
 969         }
 970
 971         return I40EVF_NB_XSTATS;
 972 }
 973
 974 static int
 975 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
 976 {
 977         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 978         struct virtchnl_vlan_filter_list *vlan_list;
 979         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
 980                                                         sizeof(uint16_t)];
 981         int err;
 982         struct vf_cmd_info args;
 983
 984         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
 985         vlan_list->vsi_id = vf->vsi_res->vsi_id;
 986         vlan_list->num_elements = 1;
 987         vlan_list->vlan_id[0] = vlanid;
 988
 989         args.ops = VIRTCHNL_OP_ADD_VLAN;
 990         args.in_args = (u8 *)&cmd_buffer;
 991         args.in_args_size = sizeof(cmd_buffer);
 992         args.out_buffer = vf->aq_resp;
 993         args.out_size = I40E_AQ_BUF_SZ;
 994         err = i40evf_execute_vf_cmd(dev, &args);
 995         if (err)
 996                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
 997
 998         return err;
 999 }
1000
1001 static int
1002 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1003 {
1004         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1005         struct virtchnl_vlan_filter_list *vlan_list;
1006         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1007                                                         sizeof(uint16_t)];
1008         int err;
1009         struct vf_cmd_info args;
1010
1011         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1012         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1013         vlan_list->num_elements = 1;
1014         vlan_list->vlan_id[0] = vlanid;
1015
1016         args.ops = VIRTCHNL_OP_DEL_VLAN;
1017         args.in_args = (u8 *)&cmd_buffer;
1018         args.in_args_size = sizeof(cmd_buffer);
1019         args.out_buffer = vf->aq_resp;
1020         args.out_size = I40E_AQ_BUF_SZ;
1021         err = i40evf_execute_vf_cmd(dev, &args);
1022         if (err)
1023                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1024
1025         return err;
1026 }
1027
1028 static const struct rte_pci_id pci_id_i40evf_map[] = {
1029         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1030         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1031         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1032         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1033         { .vendor_id = 0, /* sentinel */ },
1034 };
1035
1036 static inline int
1037 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1038                                     struct rte_eth_link *link)
1039 {
1040         struct rte_eth_link *dst = &(dev->data->dev_link);
1041         struct rte_eth_link *src = link;
1042
1043         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1044                                         *(uint64_t *)src) == 0)
1045                 return -1;
1046
1047         return 0;
1048 }
1049
1050 /* Disable IRQ0 */
1051 static inline void
1052 i40evf_disable_irq0(struct i40e_hw *hw)
1053 {
1054         /* Disable all interrupt types */
1055         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1056         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1057                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1058         I40EVF_WRITE_FLUSH(hw);
1059 }
1060
1061 /* Enable IRQ0 */
1062 static inline void
1063 i40evf_enable_irq0(struct i40e_hw *hw)
1064 {
1065         /* Enable admin queue interrupt trigger */
1066         uint32_t val;
1067
1068         i40evf_disable_irq0(hw);
1069         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1070         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1071                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1072         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1073
1074         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1075                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1076                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1077                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1078
1079         I40EVF_WRITE_FLUSH(hw);
1080 }
1081
1082 static int
1083 i40evf_reset_vf(struct i40e_hw *hw)
1084 {
1085         int i, reset;
1086
1087         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1088                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1089                 return -1;
1090         }
1091         /**
1092           * After issuing vf reset command to pf, pf won't necessarily
1093           * reset vf, it depends on what state it exactly is. If it's not
1094           * initialized yet, it won't have vf reset since it's in a certain
1095           * state. If not, it will try to reset. Even vf is reset, pf will
1096           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1097           * it to ACTIVE. In this duration, vf may not catch the moment that
1098           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1099           */
1100         rte_delay_ms(200);
1101
1102         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1103                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1104                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1105                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1106                 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1107                         break;
1108                 else
1109                         rte_delay_ms(50);
1110         }
1111
1112         if (i >= MAX_RESET_WAIT_CNT) {
1113                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1114                 return -1;
1115         }
1116
1117         return 0;
1118 }
1119
1120 static int
1121 i40evf_init_vf(struct rte_eth_dev *dev)
1122 {
1123         int i, err, bufsz;
1124         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1125         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1126         uint16_t interval =
1127                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1128
1129         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1130         vf->dev_data = dev->data;
1131         err = i40e_set_mac_type(hw);
1132         if (err) {
1133                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1134                 goto err;
1135         }
1136
1137         i40e_init_adminq_parameter(hw);
1138         err = i40e_init_adminq(hw);
1139         if (err) {
1140                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1141                 goto err;
1142         }
1143
1144         /* Reset VF and wait until it's complete */
1145         if (i40evf_reset_vf(hw)) {
1146                 PMD_INIT_LOG(ERR, "reset NIC failed");
1147                 goto err_aq;
1148         }
1149
1150         /* VF reset, shutdown admin queue and initialize again */
1151         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1152                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1153                 return -1;
1154         }
1155
1156         i40e_init_adminq_parameter(hw);
1157         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1158                 PMD_INIT_LOG(ERR, "init_adminq failed");
1159                 return -1;
1160         }
1161         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1162         if (!vf->aq_resp) {
1163                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1164                         goto err_aq;
1165         }
1166         if (i40evf_check_api_version(dev) != 0) {
1167                 PMD_INIT_LOG(ERR, "check_api version failed");
1168                 goto err_aq;
1169         }
1170         bufsz = sizeof(struct virtchnl_vf_resource) +
1171                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1172         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1173         if (!vf->vf_res) {
1174                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1175                         goto err_aq;
1176         }
1177
1178         if (i40evf_get_vf_resource(dev) != 0) {
1179                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1180                 goto err_alloc;
1181         }
1182
1183         /* got VF config message back from PF, now we can parse it */
1184         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1185                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1186                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1187         }
1188
1189         if (!vf->vsi_res) {
1190                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1191                 goto err_alloc;
1192         }
1193
1194         if (hw->mac.type == I40E_MAC_X722_VF)
1195                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1196         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1197         vf->vsi.type = (enum i40e_vsi_type)vf->vsi_res->vsi_type;
1198         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1199         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1200
1201         /* Store the MAC address configured by host, or generate random one */
1202         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1203                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1204         else
1205                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1206
1207         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1208         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1209                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1210                                (I40E_ITR_INDEX_DEFAULT <<
1211                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1212                                (interval <<
1213                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1214                 I40EVF_WRITE_FLUSH(hw);
1215         }
1216
1217         return 0;
1218
1219 err_alloc:
1220         rte_free(vf->vf_res);
1221 err_aq:
1222         i40e_shutdown_adminq(hw); /* ignore error */
1223 err:
1224         return -1;
1225 }
1226
1227 static int
1228 i40evf_uninit_vf(struct rte_eth_dev *dev)
1229 {
1230         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1231         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1232
1233         PMD_INIT_FUNC_TRACE();
1234
1235         if (hw->adapter_stopped == 0)
1236                 i40evf_dev_close(dev);
1237         rte_free(vf->vf_res);
1238         vf->vf_res = NULL;
1239         rte_free(vf->aq_resp);
1240         vf->aq_resp = NULL;
1241
1242         return 0;
1243 }
1244
1245 static void
1246 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1247                 __rte_unused uint16_t msglen)
1248 {
1249         struct virtchnl_pf_event *pf_msg =
1250                         (struct virtchnl_pf_event *)msg;
1251         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1252
1253         switch (pf_msg->event) {
1254         case VIRTCHNL_EVENT_RESET_IMPENDING:
1255                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1256                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1257                                               NULL, NULL);
1258                 break;
1259         case VIRTCHNL_EVENT_LINK_CHANGE:
1260                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1261                 vf->link_up = pf_msg->event_data.link_event.link_status;
1262                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1263                 break;
1264         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1265                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1266                 break;
1267         default:
1268                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1269                 break;
1270         }
1271 }
1272
1273 static void
1274 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1275 {
1276         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1277         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1278         struct i40e_arq_event_info info;
1279         uint16_t pending, aq_opc;
1280         enum virtchnl_ops msg_opc;
1281         enum i40e_status_code msg_ret;
1282         int ret;
1283
1284         info.buf_len = I40E_AQ_BUF_SZ;
1285         if (!vf->aq_resp) {
1286                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1287                 return;
1288         }
1289         info.msg_buf = vf->aq_resp;
1290
1291         pending = 1;
1292         while (pending) {
1293                 ret = i40e_clean_arq_element(hw, &info, &pending);
1294
1295                 if (ret != I40E_SUCCESS) {
1296                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1297                                     "ret: %d", ret);
1298                         break;
1299                 }
1300                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1301                 /* For the message sent from pf to vf, opcode is stored in
1302                  * cookie_high of struct i40e_aq_desc, while return error code
1303                  * are stored in cookie_low, Which is done by
1304                  * i40e_aq_send_msg_to_vf in PF driver.*/
1305                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1306                                                   info.desc.cookie_high);
1307                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1308                                                   info.desc.cookie_low);
1309                 switch (aq_opc) {
1310                 case i40e_aqc_opc_send_msg_to_vf:
1311                         if (msg_opc == VIRTCHNL_OP_EVENT)
1312                                 /* process event*/
1313                                 i40evf_handle_pf_event(dev, info.msg_buf,
1314                                                        info.msg_len);
1315                         else {
1316                                 /* read message and it's expected one */
1317                                 if (msg_opc == vf->pend_cmd) {
1318                                         vf->cmd_retval = msg_ret;
1319                                         /* prevent compiler reordering */
1320                                         rte_compiler_barrier();
1321                                         _clear_cmd(vf);
1322                                 } else
1323                                         PMD_DRV_LOG(ERR, "command mismatch,"
1324                                                 "expect %u, get %u",
1325                                                 vf->pend_cmd, msg_opc);
1326                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1327                                              " opcode = %d", msg_opc);
1328                         }
1329                         break;
1330                 default:
1331                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1332                                     aq_opc);
1333                         break;
1334                 }
1335         }
1336 }
1337
1338 /**
1339  * Interrupt handler triggered by NIC  for handling
1340  * specific interrupt. Only adminq interrupt is processed in VF.
1341  *
1342  * @param handle
1343  *  Pointer to interrupt handle.
1344  * @param param
1345  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1346  *
1347  * @return
1348  *  void
1349  */
1350 static void
1351 i40evf_dev_interrupt_handler(void *param)
1352 {
1353         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1354         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1355         uint32_t icr0;
1356
1357         i40evf_disable_irq0(hw);
1358
1359         /* read out interrupt causes */
1360         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1361
1362         /* No interrupt event indicated */
1363         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1364                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1365                 goto done;
1366         }
1367
1368         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1369                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1370                 i40evf_handle_aq_msg(dev);
1371         }
1372
1373         /* Link Status Change interrupt */
1374         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1375                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1376                                    " do nothing");
1377
1378 done:
1379         i40evf_enable_irq0(hw);
1380         rte_intr_enable(dev->intr_handle);
1381 }
1382
1383 static int
1384 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1385 {
1386         struct i40e_hw *hw
1387                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1388         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1389
1390         PMD_INIT_FUNC_TRACE();
1391
1392         /* assign ops func pointer */
1393         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1394         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1395         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1396
1397         /*
1398          * For secondary processes, we don't initialise any further as primary
1399          * has already done this work.
1400          */
1401         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1402                 i40e_set_rx_function(eth_dev);
1403                 i40e_set_tx_function(eth_dev);
1404                 return 0;
1405         }
1406         i40e_set_default_ptype_table(eth_dev);
1407         rte_eth_copy_pci_info(eth_dev, pci_dev);
1408         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1409
1410         hw->vendor_id = pci_dev->id.vendor_id;
1411         hw->device_id = pci_dev->id.device_id;
1412         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1413         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1414         hw->bus.device = pci_dev->addr.devid;
1415         hw->bus.func = pci_dev->addr.function;
1416         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1417         hw->adapter_stopped = 0;
1418
1419         if(i40evf_init_vf(eth_dev) != 0) {
1420                 PMD_INIT_LOG(ERR, "Init vf failed");
1421                 return -1;
1422         }
1423
1424         /* register callback func to eal lib */
1425         rte_intr_callback_register(&pci_dev->intr_handle,
1426                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1427
1428         /* enable uio intr after callback register */
1429         rte_intr_enable(&pci_dev->intr_handle);
1430
1431         /* configure and enable device interrupt */
1432         i40evf_enable_irq0(hw);
1433
1434         /* copy mac addr */
1435         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1436                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1437                                         0);
1438         if (eth_dev->data->mac_addrs == NULL) {
1439                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1440                                 " store MAC addresses",
1441                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1442                 return -ENOMEM;
1443         }
1444         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1445                         &eth_dev->data->mac_addrs[0]);
1446
1447         return 0;
1448 }
1449
1450 static int
1451 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1452 {
1453         PMD_INIT_FUNC_TRACE();
1454
1455         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1456                 return -EPERM;
1457
1458         eth_dev->dev_ops = NULL;
1459         eth_dev->rx_pkt_burst = NULL;
1460         eth_dev->tx_pkt_burst = NULL;
1461
1462         if (i40evf_uninit_vf(eth_dev) != 0) {
1463                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1464                 return -1;
1465         }
1466
1467         rte_free(eth_dev->data->mac_addrs);
1468         eth_dev->data->mac_addrs = NULL;
1469
1470         return 0;
1471 }
1472
1473 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1474         struct rte_pci_device *pci_dev)
1475 {
1476         return rte_eth_dev_pci_generic_probe(pci_dev,
1477                 sizeof(struct i40e_adapter), i40evf_dev_init);
1478 }
1479
1480 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1481 {
1482         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1483 }
1484
1485 /*
1486  * virtual function driver struct
1487  */
1488 static struct rte_pci_driver rte_i40evf_pmd = {
1489         .id_table = pci_id_i40evf_map,
1490         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1491         .probe = eth_i40evf_pci_probe,
1492         .remove = eth_i40evf_pci_remove,
1493 };
1494
1495 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1496 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1497 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1498
1499 static int
1500 i40evf_dev_configure(struct rte_eth_dev *dev)
1501 {
1502         struct i40e_adapter *ad =
1503                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1504         struct rte_eth_conf *conf = &dev->data->dev_conf;
1505         struct i40e_vf *vf;
1506
1507         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1508          * allocation or vector Rx preconditions we will reset it.
1509          */
1510         ad->rx_bulk_alloc_allowed = true;
1511         ad->rx_vec_allowed = true;
1512         ad->tx_simple_allowed = true;
1513         ad->tx_vec_allowed = true;
1514
1515         /* For non-DPDK PF drivers, VF has no ability to disable HW
1516          * CRC strip, and is implicitly enabled by the PF.
1517          */
1518         if (!conf->rxmode.hw_strip_crc) {
1519                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1520                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1521                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1522                         /* Peer is running non-DPDK PF driver. */
1523                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1524                         return -EINVAL;
1525                 }
1526         }
1527
1528         return i40evf_init_vlan(dev);
1529 }
1530
1531 static int
1532 i40evf_init_vlan(struct rte_eth_dev *dev)
1533 {
1534         /* Apply vlan offload setting */
1535         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1536
1537         return I40E_SUCCESS;
1538 }
1539
1540 static void
1541 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1542 {
1543         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1544
1545         /* Vlan stripping setting */
1546         if (mask & ETH_VLAN_STRIP_MASK) {
1547                 /* Enable or disable VLAN stripping */
1548                 if (dev_conf->rxmode.hw_vlan_strip)
1549                         i40evf_enable_vlan_strip(dev);
1550                 else
1551                         i40evf_disable_vlan_strip(dev);
1552         }
1553 }
1554
1555 static int
1556 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1557 {
1558         struct i40e_rx_queue *rxq;
1559         int err = 0;
1560         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1561
1562         PMD_INIT_FUNC_TRACE();
1563
1564         if (rx_queue_id < dev->data->nb_rx_queues) {
1565                 rxq = dev->data->rx_queues[rx_queue_id];
1566
1567                 err = i40e_alloc_rx_queue_mbufs(rxq);
1568                 if (err) {
1569                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1570                         return err;
1571                 }
1572
1573                 rte_wmb();
1574
1575                 /* Init the RX tail register. */
1576                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1577                 I40EVF_WRITE_FLUSH(hw);
1578
1579                 /* Ready to switch the queue on */
1580                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1581
1582                 if (err)
1583                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1584                                     rx_queue_id);
1585                 else
1586                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1587         }
1588
1589         return err;
1590 }
1591
1592 static int
1593 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1594 {
1595         struct i40e_rx_queue *rxq;
1596         int err;
1597
1598         if (rx_queue_id < dev->data->nb_rx_queues) {
1599                 rxq = dev->data->rx_queues[rx_queue_id];
1600
1601                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1602
1603                 if (err) {
1604                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1605                                     rx_queue_id);
1606                         return err;
1607                 }
1608
1609                 i40e_rx_queue_release_mbufs(rxq);
1610                 i40e_reset_rx_queue(rxq);
1611                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1612         }
1613
1614         return 0;
1615 }
1616
1617 static int
1618 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1619 {
1620         int err = 0;
1621
1622         PMD_INIT_FUNC_TRACE();
1623
1624         if (tx_queue_id < dev->data->nb_tx_queues) {
1625
1626                 /* Ready to switch the queue on */
1627                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1628
1629                 if (err)
1630                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1631                                     tx_queue_id);
1632                 else
1633                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1634         }
1635
1636         return err;
1637 }
1638
1639 static int
1640 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1641 {
1642         struct i40e_tx_queue *txq;
1643         int err;
1644
1645         if (tx_queue_id < dev->data->nb_tx_queues) {
1646                 txq = dev->data->tx_queues[tx_queue_id];
1647
1648                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1649
1650                 if (err) {
1651                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1652                                     tx_queue_id);
1653                         return err;
1654                 }
1655
1656                 i40e_tx_queue_release_mbufs(txq);
1657                 i40e_reset_tx_queue(txq);
1658                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1659         }
1660
1661         return 0;
1662 }
1663
1664 static int
1665 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1666 {
1667         int ret;
1668
1669         if (on)
1670                 ret = i40evf_add_vlan(dev, vlan_id);
1671         else
1672                 ret = i40evf_del_vlan(dev,vlan_id);
1673
1674         return ret;
1675 }
1676
1677 static int
1678 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1679 {
1680         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1681         struct rte_eth_dev_data *dev_data = dev->data;
1682         struct rte_pktmbuf_pool_private *mbp_priv;
1683         uint16_t buf_size, len;
1684
1685         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1686         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1687         I40EVF_WRITE_FLUSH(hw);
1688
1689         /* Calculate the maximum packet length allowed */
1690         mbp_priv = rte_mempool_get_priv(rxq->mp);
1691         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1692                                         RTE_PKTMBUF_HEADROOM);
1693         rxq->hs_mode = i40e_header_split_none;
1694         rxq->rx_hdr_len = 0;
1695         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1696         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1697         rxq->max_pkt_len = RTE_MIN(len,
1698                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1699
1700         /**
1701          * Check if the jumbo frame and maximum packet length are set correctly
1702          */
1703         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1704                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1705                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1706                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1707                                 "larger than %u and smaller than %u, as jumbo "
1708                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1709                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1710                         return I40E_ERR_CONFIG;
1711                 }
1712         } else {
1713                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1714                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1715                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1716                                 "larger than %u and smaller than %u, as jumbo "
1717                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1718                                                 (uint32_t)ETHER_MAX_LEN);
1719                         return I40E_ERR_CONFIG;
1720                 }
1721         }
1722
1723         if (dev_data->dev_conf.rxmode.enable_scatter ||
1724             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1725                 dev_data->scattered_rx = 1;
1726         }
1727
1728         return 0;
1729 }
1730
1731 static int
1732 i40evf_rx_init(struct rte_eth_dev *dev)
1733 {
1734         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1735         uint16_t i;
1736         int ret = I40E_SUCCESS;
1737         struct i40e_rx_queue **rxq =
1738                 (struct i40e_rx_queue **)dev->data->rx_queues;
1739
1740         i40evf_config_rss(vf);
1741         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1742                 if (!rxq[i] || !rxq[i]->q_set)
1743                         continue;
1744                 ret = i40evf_rxq_init(dev, rxq[i]);
1745                 if (ret != I40E_SUCCESS)
1746                         break;
1747         }
1748         if (ret == I40E_SUCCESS)
1749                 i40e_set_rx_function(dev);
1750
1751         return ret;
1752 }
1753
1754 static void
1755 i40evf_tx_init(struct rte_eth_dev *dev)
1756 {
1757         uint16_t i;
1758         struct i40e_tx_queue **txq =
1759                 (struct i40e_tx_queue **)dev->data->tx_queues;
1760         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1761
1762         for (i = 0; i < dev->data->nb_tx_queues; i++)
1763                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1764
1765         i40e_set_tx_function(dev);
1766 }
1767
1768 static inline void
1769 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1770 {
1771         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1772         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1773         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1774         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1775
1776         if (!rte_intr_allow_others(intr_handle)) {
1777                 I40E_WRITE_REG(hw,
1778                                I40E_VFINT_DYN_CTL01,
1779                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1780                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1781                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1782                 I40EVF_WRITE_FLUSH(hw);
1783                 return;
1784         }
1785
1786         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1787                 /* To support DPDK PF host */
1788                 I40E_WRITE_REG(hw,
1789                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1790                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1791                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1792         /* If host driver is kernel driver, do nothing.
1793          * Interrupt 0 is used for rx packets, but don't set
1794          * I40E_VFINT_DYN_CTL01,
1795          * because it is already done in i40evf_enable_irq0.
1796          */
1797
1798         I40EVF_WRITE_FLUSH(hw);
1799 }
1800
1801 static inline void
1802 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1803 {
1804         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1805         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1806         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1807         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1808
1809         if (!rte_intr_allow_others(intr_handle)) {
1810                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1811                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1812                 I40EVF_WRITE_FLUSH(hw);
1813                 return;
1814         }
1815
1816         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1817                 I40E_WRITE_REG(hw,
1818                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1819                                                     - 1),
1820                                0);
1821         /* If host driver is kernel driver, do nothing.
1822          * Interrupt 0 is used for rx packets, but don't zero
1823          * I40E_VFINT_DYN_CTL01,
1824          * because interrupt 0 is also used for adminq processing.
1825          */
1826
1827         I40EVF_WRITE_FLUSH(hw);
1828 }
1829
1830 static int
1831 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1832 {
1833         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1834         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1836         uint16_t interval =
1837                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1838         uint16_t msix_intr;
1839
1840         msix_intr = intr_handle->intr_vec[queue_id];
1841         if (msix_intr == I40E_MISC_VEC_ID)
1842                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1843                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1844                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1845                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1846                                (interval <<
1847                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1848         else
1849                 I40E_WRITE_REG(hw,
1850                                I40E_VFINT_DYN_CTLN1(msix_intr -
1851                                                     I40E_RX_VEC_START),
1852                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1853                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1854                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1855                                (interval <<
1856                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1857
1858         I40EVF_WRITE_FLUSH(hw);
1859
1860         rte_intr_enable(&pci_dev->intr_handle);
1861
1862         return 0;
1863 }
1864
1865 static int
1866 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1867 {
1868         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1869         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1870         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1871         uint16_t msix_intr;
1872
1873         msix_intr = intr_handle->intr_vec[queue_id];
1874         if (msix_intr == I40E_MISC_VEC_ID)
1875                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1876         else
1877                 I40E_WRITE_REG(hw,
1878                                I40E_VFINT_DYN_CTLN1(msix_intr -
1879                                                     I40E_RX_VEC_START),
1880                                0);
1881
1882         I40EVF_WRITE_FLUSH(hw);
1883
1884         return 0;
1885 }
1886
1887 static void
1888 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1889 {
1890         struct virtchnl_ether_addr_list *list;
1891         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1892         int err, i, j;
1893         int next_begin = 0;
1894         int begin = 0;
1895         uint32_t len;
1896         struct ether_addr *addr;
1897         struct vf_cmd_info args;
1898
1899         do {
1900                 j = 0;
1901                 len = sizeof(struct virtchnl_ether_addr_list);
1902                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1903                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1904                                 continue;
1905                         len += sizeof(struct virtchnl_ether_addr);
1906                         if (len >= I40E_AQ_BUF_SZ) {
1907                                 next_begin = i + 1;
1908                                 break;
1909                         }
1910                 }
1911
1912                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1913                 if (!list) {
1914                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1915                         return;
1916                 }
1917
1918                 for (i = begin; i < next_begin; i++) {
1919                         addr = &dev->data->mac_addrs[i];
1920                         if (is_zero_ether_addr(addr))
1921                                 continue;
1922                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
1923                                          sizeof(addr->addr_bytes));
1924                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1925                                     addr->addr_bytes[0], addr->addr_bytes[1],
1926                                     addr->addr_bytes[2], addr->addr_bytes[3],
1927                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1928                         j++;
1929                 }
1930                 list->vsi_id = vf->vsi_res->vsi_id;
1931                 list->num_elements = j;
1932                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1933                            VIRTCHNL_OP_DEL_ETH_ADDR;
1934                 args.in_args = (uint8_t *)list;
1935                 args.in_args_size = len;
1936                 args.out_buffer = vf->aq_resp;
1937                 args.out_size = I40E_AQ_BUF_SZ;
1938                 err = i40evf_execute_vf_cmd(dev, &args);
1939                 if (err) {
1940                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1941                                     add ? "OP_ADD_ETHER_ADDRESS" :
1942                                     "OP_DEL_ETHER_ADDRESS");
1943                 } else {
1944                         if (add)
1945                                 vf->vsi.mac_num++;
1946                         else
1947                                 vf->vsi.mac_num--;
1948                 }
1949                 rte_free(list);
1950                 begin = next_begin;
1951         } while (begin < I40E_NUM_MACADDR_MAX);
1952 }
1953
1954 static int
1955 i40evf_dev_start(struct rte_eth_dev *dev)
1956 {
1957         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1958         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1959         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1960         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1961         uint32_t intr_vector = 0;
1962
1963         PMD_INIT_FUNC_TRACE();
1964
1965         hw->adapter_stopped = 0;
1966
1967         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1968         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1969                                         dev->data->nb_tx_queues);
1970
1971         /* check and configure queue intr-vector mapping */
1972         if (dev->data->dev_conf.intr_conf.rxq != 0) {
1973                 intr_vector = dev->data->nb_rx_queues;
1974                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1975                         return -1;
1976         }
1977
1978         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1979                 intr_handle->intr_vec =
1980                         rte_zmalloc("intr_vec",
1981                                     dev->data->nb_rx_queues * sizeof(int), 0);
1982                 if (!intr_handle->intr_vec) {
1983                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1984                                      " intr_vec", dev->data->nb_rx_queues);
1985                         return -ENOMEM;
1986                 }
1987         }
1988
1989         if (i40evf_rx_init(dev) != 0){
1990                 PMD_DRV_LOG(ERR, "failed to do RX init");
1991                 return -1;
1992         }
1993
1994         i40evf_tx_init(dev);
1995
1996         if (i40evf_configure_vsi_queues(dev) != 0) {
1997                 PMD_DRV_LOG(ERR, "configure queues failed");
1998                 goto err_queue;
1999         }
2000         if (i40evf_config_irq_map(dev)) {
2001                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2002                 goto err_queue;
2003         }
2004
2005         /* Set all mac addrs */
2006         i40evf_add_del_all_mac_addr(dev, TRUE);
2007
2008         if (i40evf_start_queues(dev) != 0) {
2009                 PMD_DRV_LOG(ERR, "enable queues failed");
2010                 goto err_mac;
2011         }
2012
2013         i40evf_enable_queues_intr(dev);
2014         return 0;
2015
2016 err_mac:
2017         i40evf_add_del_all_mac_addr(dev, FALSE);
2018 err_queue:
2019         return -1;
2020 }
2021
2022 static void
2023 i40evf_dev_stop(struct rte_eth_dev *dev)
2024 {
2025         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2026         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2027         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev);
2028
2029         PMD_INIT_FUNC_TRACE();
2030
2031         if (hw->adapter_stopped == 1)
2032                 return;
2033         i40evf_stop_queues(dev);
2034         i40evf_disable_queues_intr(dev);
2035         i40e_dev_clear_queues(dev);
2036
2037         /* Clean datapath event and queue/vec mapping */
2038         rte_intr_efd_disable(intr_handle);
2039         if (intr_handle->intr_vec) {
2040                 rte_free(intr_handle->intr_vec);
2041                 intr_handle->intr_vec = NULL;
2042         }
2043         /* remove all mac addrs */
2044         i40evf_add_del_all_mac_addr(dev, FALSE);
2045         hw->adapter_stopped = 1;
2046
2047 }
2048
2049 static int
2050 i40evf_dev_link_update(struct rte_eth_dev *dev,
2051                        __rte_unused int wait_to_complete)
2052 {
2053         struct rte_eth_link new_link;
2054         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2055         /*
2056          * DPDK pf host provide interfacet to acquire link status
2057          * while Linux driver does not
2058          */
2059
2060         /* Linux driver PF host */
2061         switch (vf->link_speed) {
2062         case I40E_LINK_SPEED_100MB:
2063                 new_link.link_speed = ETH_SPEED_NUM_100M;
2064                 break;
2065         case I40E_LINK_SPEED_1GB:
2066                 new_link.link_speed = ETH_SPEED_NUM_1G;
2067                 break;
2068         case I40E_LINK_SPEED_10GB:
2069                 new_link.link_speed = ETH_SPEED_NUM_10G;
2070                 break;
2071         case I40E_LINK_SPEED_20GB:
2072                 new_link.link_speed = ETH_SPEED_NUM_20G;
2073                 break;
2074         case I40E_LINK_SPEED_25GB:
2075                 new_link.link_speed = ETH_SPEED_NUM_25G;
2076                 break;
2077         case I40E_LINK_SPEED_40GB:
2078                 new_link.link_speed = ETH_SPEED_NUM_40G;
2079                 break;
2080         default:
2081                 new_link.link_speed = ETH_SPEED_NUM_100M;
2082                 break;
2083         }
2084         /* full duplex only */
2085         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2086         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2087                                              ETH_LINK_DOWN;
2088
2089         i40evf_dev_atomic_write_link_status(dev, &new_link);
2090
2091         return 0;
2092 }
2093
2094 static void
2095 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2096 {
2097         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2098         int ret;
2099
2100         /* If enabled, just return */
2101         if (vf->promisc_unicast_enabled)
2102                 return;
2103
2104         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2105         if (ret == 0)
2106                 vf->promisc_unicast_enabled = TRUE;
2107 }
2108
2109 static void
2110 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2111 {
2112         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2113         int ret;
2114
2115         /* If disabled, just return */
2116         if (!vf->promisc_unicast_enabled)
2117                 return;
2118
2119         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2120         if (ret == 0)
2121                 vf->promisc_unicast_enabled = FALSE;
2122 }
2123
2124 static void
2125 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2126 {
2127         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2128         int ret;
2129
2130         /* If enabled, just return */
2131         if (vf->promisc_multicast_enabled)
2132                 return;
2133
2134         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2135         if (ret == 0)
2136                 vf->promisc_multicast_enabled = TRUE;
2137 }
2138
2139 static void
2140 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2141 {
2142         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2143         int ret;
2144
2145         /* If enabled, just return */
2146         if (!vf->promisc_multicast_enabled)
2147                 return;
2148
2149         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2150         if (ret == 0)
2151                 vf->promisc_multicast_enabled = FALSE;
2152 }
2153
2154 static void
2155 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2156 {
2157         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2158
2159         memset(dev_info, 0, sizeof(*dev_info));
2160         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2161         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2162         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2163         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2164         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2165         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2166         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2167         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2168         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2169         dev_info->rx_offload_capa =
2170                 DEV_RX_OFFLOAD_VLAN_STRIP |
2171                 DEV_RX_OFFLOAD_QINQ_STRIP |
2172                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2173                 DEV_RX_OFFLOAD_UDP_CKSUM |
2174                 DEV_RX_OFFLOAD_TCP_CKSUM;
2175         dev_info->tx_offload_capa =
2176                 DEV_TX_OFFLOAD_VLAN_INSERT |
2177                 DEV_TX_OFFLOAD_QINQ_INSERT |
2178                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2179                 DEV_TX_OFFLOAD_UDP_CKSUM |
2180                 DEV_TX_OFFLOAD_TCP_CKSUM |
2181                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2182
2183         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2184                 .rx_thresh = {
2185                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2186                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2187                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2188                 },
2189                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2190                 .rx_drop_en = 0,
2191         };
2192
2193         dev_info->default_txconf = (struct rte_eth_txconf) {
2194                 .tx_thresh = {
2195                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2196                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2197                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2198                 },
2199                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2200                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2201                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2202                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2203         };
2204
2205         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2206                 .nb_max = I40E_MAX_RING_DESC,
2207                 .nb_min = I40E_MIN_RING_DESC,
2208                 .nb_align = I40E_ALIGN_RING_DESC,
2209         };
2210
2211         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2212                 .nb_max = I40E_MAX_RING_DESC,
2213                 .nb_min = I40E_MIN_RING_DESC,
2214                 .nb_align = I40E_ALIGN_RING_DESC,
2215         };
2216 }
2217
2218 static void
2219 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2220 {
2221         if (i40evf_get_statistics(dev, stats))
2222                 PMD_DRV_LOG(ERR, "Get statistics failed");
2223 }
2224
2225 static void
2226 i40evf_dev_close(struct rte_eth_dev *dev)
2227 {
2228         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2229         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2230         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2231
2232         i40evf_dev_stop(dev);
2233         i40e_dev_free_queues(dev);
2234         i40evf_reset_vf(hw);
2235         i40e_shutdown_adminq(hw);
2236         /* disable uio intr before callback unregister */
2237         rte_intr_disable(intr_handle);
2238
2239         /* unregister callback func from eal lib */
2240         rte_intr_callback_unregister(intr_handle,
2241                                      i40evf_dev_interrupt_handler, dev);
2242         i40evf_disable_irq0(hw);
2243 }
2244
2245 /*
2246  * Reset VF device only to re-initialize resources in PMD layer
2247  */
2248 static int
2249 i40evf_dev_reset(struct rte_eth_dev *dev)
2250 {
2251         int ret;
2252
2253         ret = i40evf_dev_uninit(dev);
2254         if (ret)
2255                 return ret;
2256
2257         ret = i40evf_dev_init(dev);
2258
2259         return ret;
2260 }
2261
2262 static int
2263 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2264 {
2265         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2266         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2267         int ret;
2268
2269         if (!lut)
2270                 return -EINVAL;
2271
2272         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2273                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2274                                           lut, lut_size);
2275                 if (ret) {
2276                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2277                         return ret;
2278                 }
2279         } else {
2280                 uint32_t *lut_dw = (uint32_t *)lut;
2281                 uint16_t i, lut_size_dw = lut_size / 4;
2282
2283                 for (i = 0; i < lut_size_dw; i++)
2284                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2285         }
2286
2287         return 0;
2288 }
2289
2290 static int
2291 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2292 {
2293         struct i40e_vf *vf;
2294         struct i40e_hw *hw;
2295         int ret;
2296
2297         if (!vsi || !lut)
2298                 return -EINVAL;
2299
2300         vf = I40E_VSI_TO_VF(vsi);
2301         hw = I40E_VSI_TO_HW(vsi);
2302
2303         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2304                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2305                                           lut, lut_size);
2306                 if (ret) {
2307                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2308                         return ret;
2309                 }
2310         } else {
2311                 uint32_t *lut_dw = (uint32_t *)lut;
2312                 uint16_t i, lut_size_dw = lut_size / 4;
2313
2314                 for (i = 0; i < lut_size_dw; i++)
2315                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2316                 I40EVF_WRITE_FLUSH(hw);
2317         }
2318
2319         return 0;
2320 }
2321
2322 static int
2323 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2324                            struct rte_eth_rss_reta_entry64 *reta_conf,
2325                            uint16_t reta_size)
2326 {
2327         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2328         uint8_t *lut;
2329         uint16_t i, idx, shift;
2330         int ret;
2331
2332         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2333                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2334                         "(%d) doesn't match the number of hardware can "
2335                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2336                 return -EINVAL;
2337         }
2338
2339         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2340         if (!lut) {
2341                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2342                 return -ENOMEM;
2343         }
2344         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2345         if (ret)
2346                 goto out;
2347         for (i = 0; i < reta_size; i++) {
2348                 idx = i / RTE_RETA_GROUP_SIZE;
2349                 shift = i % RTE_RETA_GROUP_SIZE;
2350                 if (reta_conf[idx].mask & (1ULL << shift))
2351                         lut[i] = reta_conf[idx].reta[shift];
2352         }
2353         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2354
2355 out:
2356         rte_free(lut);
2357
2358         return ret;
2359 }
2360
2361 static int
2362 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2363                           struct rte_eth_rss_reta_entry64 *reta_conf,
2364                           uint16_t reta_size)
2365 {
2366         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2367         uint16_t i, idx, shift;
2368         uint8_t *lut;
2369         int ret;
2370
2371         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2372                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2373                         "(%d) doesn't match the number of hardware can "
2374                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2375                 return -EINVAL;
2376         }
2377
2378         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2379         if (!lut) {
2380                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2381                 return -ENOMEM;
2382         }
2383
2384         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2385         if (ret)
2386                 goto out;
2387         for (i = 0; i < reta_size; i++) {
2388                 idx = i / RTE_RETA_GROUP_SIZE;
2389                 shift = i % RTE_RETA_GROUP_SIZE;
2390                 if (reta_conf[idx].mask & (1ULL << shift))
2391                         reta_conf[idx].reta[shift] = lut[i];
2392         }
2393
2394 out:
2395         rte_free(lut);
2396
2397         return ret;
2398 }
2399
2400 static int
2401 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2402 {
2403         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2404         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2405         int ret = 0;
2406
2407         if (!key || key_len == 0) {
2408                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2409                 return 0;
2410         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2411                 sizeof(uint32_t)) {
2412                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2413                 return -EINVAL;
2414         }
2415
2416         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2417                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2418                         (struct i40e_aqc_get_set_rss_key_data *)key;
2419
2420                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2421                 if (ret)
2422                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2423                                      "via AQ");
2424         } else {
2425                 uint32_t *hash_key = (uint32_t *)key;
2426                 uint16_t i;
2427
2428                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2429                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2430                 I40EVF_WRITE_FLUSH(hw);
2431         }
2432
2433         return ret;
2434 }
2435
2436 static int
2437 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2438 {
2439         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2440         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2441         int ret;
2442
2443         if (!key || !key_len)
2444                 return -EINVAL;
2445
2446         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2447                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2448                         (struct i40e_aqc_get_set_rss_key_data *)key);
2449                 if (ret) {
2450                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2451                         return ret;
2452                 }
2453         } else {
2454                 uint32_t *key_dw = (uint32_t *)key;
2455                 uint16_t i;
2456
2457                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2458                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2459         }
2460         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2461
2462         return 0;
2463 }
2464
2465 static int
2466 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2467 {
2468         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2469         uint64_t rss_hf, hena;
2470         int ret;
2471
2472         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2473                                  rss_conf->rss_key_len);
2474         if (ret)
2475                 return ret;
2476
2477         rss_hf = rss_conf->rss_hf;
2478         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2479         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2480         if (hw->mac.type == I40E_MAC_X722)
2481                 hena &= ~I40E_RSS_HENA_ALL_X722;
2482         else
2483                 hena &= ~I40E_RSS_HENA_ALL;
2484         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2485         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2486         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2487         I40EVF_WRITE_FLUSH(hw);
2488
2489         return 0;
2490 }
2491
2492 static void
2493 i40evf_disable_rss(struct i40e_vf *vf)
2494 {
2495         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2496         uint64_t hena;
2497
2498         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2499         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2500         if (hw->mac.type == I40E_MAC_X722)
2501                 hena &= ~I40E_RSS_HENA_ALL_X722;
2502         else
2503                 hena &= ~I40E_RSS_HENA_ALL;
2504         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2505         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2506         I40EVF_WRITE_FLUSH(hw);
2507 }
2508
2509 static int
2510 i40evf_config_rss(struct i40e_vf *vf)
2511 {
2512         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2513         struct rte_eth_rss_conf rss_conf;
2514         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2515         uint16_t num;
2516
2517         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2518                 i40evf_disable_rss(vf);
2519                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2520                 return 0;
2521         }
2522
2523         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2524         /* Fill out the look up table */
2525         for (i = 0, j = 0; i < nb_q; i++, j++) {
2526                 if (j >= num)
2527                         j = 0;
2528                 lut = (lut << 8) | j;
2529                 if ((i & 3) == 3)
2530                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2531         }
2532
2533         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2534         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2535                 i40evf_disable_rss(vf);
2536                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2537                 return 0;
2538         }
2539
2540         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2541                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2542                 /* Calculate the default hash key */
2543                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2544                         rss_key_default[i] = (uint32_t)rte_rand();
2545                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2546                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2547                         sizeof(uint32_t);
2548         }
2549
2550         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2551 }
2552
2553 static int
2554 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2555                            struct rte_eth_rss_conf *rss_conf)
2556 {
2557         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2558         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2559         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2560         uint64_t hena;
2561
2562         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2563         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2564         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2565                  ? I40E_RSS_HENA_ALL_X722
2566                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2567                 if (rss_hf != 0) /* Enable RSS */
2568                         return -EINVAL;
2569                 return 0;
2570         }
2571
2572         /* RSS enabled */
2573         if (rss_hf == 0) /* Disable RSS */
2574                 return -EINVAL;
2575
2576         return i40evf_hw_rss_hash_set(vf, rss_conf);
2577 }
2578
2579 static int
2580 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2581                              struct rte_eth_rss_conf *rss_conf)
2582 {
2583         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2584         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2585         uint64_t hena;
2586
2587         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2588                            &rss_conf->rss_key_len);
2589
2590         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2591         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2592         rss_conf->rss_hf = i40e_parse_hena(hena);
2593
2594         return 0;
2595 }
2596
2597 static int
2598 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2599 {
2600         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2601         struct rte_eth_dev_data *dev_data = vf->dev_data;
2602         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2603         int ret = 0;
2604
2605         /* check if mtu is within the allowed range */
2606         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2607                 return -EINVAL;
2608
2609         /* mtu setting is forbidden if port is start */
2610         if (dev_data->dev_started) {
2611                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2612                             dev_data->port_id);
2613                 return -EBUSY;
2614         }
2615
2616         if (frame_size > ETHER_MAX_LEN)
2617                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2618         else
2619                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2620
2621         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2622
2623         return ret;
2624 }
2625
2626 static void
2627 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2628                             struct ether_addr *mac_addr)
2629 {
2630         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2631
2632         if (!is_valid_assigned_ether_addr(mac_addr)) {
2633                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2634                 return;
2635         }
2636
2637         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2638                 return;
2639
2640         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2641                 return;
2642
2643         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2644
2645         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2646 }