drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static void i40evf_dev_close(struct rte_eth_dev *dev);
 123 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 130                                      uint16_t rx_queue_id);
 131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 132                                     uint16_t rx_queue_id);
 133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 134                                      uint16_t tx_queue_id);
 135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 136                                     uint16_t tx_queue_id);
 137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 138                                struct ether_addr *addr,
 139                                uint32_t index,
 140                                uint32_t pool);
 141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 143                         struct rte_eth_rss_reta_entry64 *reta_conf,
 144                         uint16_t reta_size);
 145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                         struct rte_eth_rss_reta_entry64 *reta_conf,
 147                         uint16_t reta_size);
 148 static int i40evf_config_rss(struct i40e_vf *vf);
 149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 150                                       struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 152                                         struct rte_eth_rss_conf *rss_conf);
 153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 155                                         struct ether_addr *mac_addr);
 156 static int
 157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static int
 159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 161                                    uint8_t *msg,
 162                                    uint16_t msglen);
 163
 164 /* Default hash key buffer for RSS */
 165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 166
 167 struct rte_i40evf_xstats_name_off {
 168         char name[RTE_ETH_XSTATS_NAME_SIZE];
 169         unsigned offset;
 170 };
 171
 172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 173         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 174         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 175         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 176         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 177         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 178         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 179                 rx_unknown_protocol)},
 180         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 182         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 183         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 184         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 185         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 186 };
 187
 188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 189                 sizeof(rte_i40evf_stats_strings[0]))
 190
 191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 192         .dev_configure        = i40evf_dev_configure,
 193         .dev_start            = i40evf_dev_start,
 194         .dev_stop             = i40evf_dev_stop,
 195         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 196         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 197         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 198         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 199         .link_update          = i40evf_dev_link_update,
 200         .stats_get            = i40evf_dev_stats_get,
 201         .xstats_get           = i40evf_dev_xstats_get,
 202         .xstats_get_names     = i40evf_dev_xstats_get_names,
 203         .xstats_reset         = i40evf_dev_xstats_reset,
 204         .dev_close            = i40evf_dev_close,
 205         .dev_reset            = i40evf_dev_reset,
 206         .dev_infos_get        = i40evf_dev_info_get,
 207         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 208         .vlan_filter_set      = i40evf_vlan_filter_set,
 209         .vlan_offload_set     = i40evf_vlan_offload_set,
 210         .rx_queue_start       = i40evf_dev_rx_queue_start,
 211         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 212         .tx_queue_start       = i40evf_dev_tx_queue_start,
 213         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 214         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 215         .rx_queue_release     = i40e_dev_rx_queue_release,
 216         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 217         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 218         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 219         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 220         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 221         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 222         .tx_queue_release     = i40e_dev_tx_queue_release,
 223         .rx_queue_count       = i40e_dev_rx_queue_count,
 224         .rxq_info_get         = i40e_rxq_info_get,
 225         .txq_info_get         = i40e_txq_info_get,
 226         .mac_addr_add         = i40evf_add_mac_addr,
 227         .mac_addr_remove      = i40evf_del_mac_addr,
 228         .reta_update          = i40evf_dev_rss_reta_update,
 229         .reta_query           = i40evf_dev_rss_reta_query,
 230         .rss_hash_update      = i40evf_dev_rss_hash_update,
 231         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 232         .mtu_set              = i40evf_dev_mtu_set,
 233         .mac_addr_set         = i40evf_set_default_mac_addr,
 234 };
 235
 236 /*
 237  * Read data in admin queue to get msg from pf driver
 238  */
 239 static enum i40evf_aq_result
 240 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 241 {
 242         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 243         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 244         struct i40e_arq_event_info event;
 245         enum virtchnl_ops opcode;
 246         enum i40e_status_code retval;
 247         int ret;
 248         enum i40evf_aq_result result = I40EVF_MSG_NON;
 249
 250         event.buf_len = data->buf_len;
 251         event.msg_buf = data->msg;
 252         ret = i40e_clean_arq_element(hw, &event, NULL);
 253         /* Can't read any msg from adminQ */
 254         if (ret) {
 255                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 256                         result = I40EVF_MSG_ERR;
 257                 return result;
 258         }
 259
 260         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 261         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 262         /* pf sys event */
 263         if (opcode == VIRTCHNL_OP_EVENT) {
 264                 struct virtchnl_pf_event *vpe =
 265                         (struct virtchnl_pf_event *)event.msg_buf;
 266
 267                 result = I40EVF_MSG_SYS;
 268                 switch (vpe->event) {
 269                 case VIRTCHNL_EVENT_LINK_CHANGE:
 270                         vf->link_up =
 271                                 vpe->event_data.link_event.link_status;
 272                         vf->link_speed =
 273                                 vpe->event_data.link_event.link_speed;
 274                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 275                         PMD_DRV_LOG(INFO, "Link status update:%s",
 276                                     vf->link_up ? "up" : "down");
 277                         break;
 278                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 279                         vf->vf_reset = true;
 280                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 281                         PMD_DRV_LOG(INFO, "vf is reseting");
 282                         break;
 283                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 284                         vf->dev_closed = true;
 285                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 286                         PMD_DRV_LOG(INFO, "PF driver closed");
 287                         break;
 288                 default:
 289                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 290                                     __func__, vpe->event);
 291                 }
 292         } else {
 293                 /* async reply msg on command issued by vf previously */
 294                 result = I40EVF_MSG_CMD;
 295                 /* Actual data length read from PF */
 296                 data->msg_len = event.msg_len;
 297         }
 298
 299         data->result = retval;
 300         data->ops = opcode;
 301
 302         return result;
 303 }
 304
 305 /**
 306  * clear current command. Only call in case execute
 307  * _atomic_set_cmd successfully.
 308  */
 309 static inline void
 310 _clear_cmd(struct i40e_vf *vf)
 311 {
 312         rte_wmb();
 313         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 314 }
 315
 316 /*
 317  * Check there is pending cmd in execution. If none, set new command.
 318  */
 319 static inline int
 320 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 321 {
 322         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 323                         VIRTCHNL_OP_UNKNOWN, ops);
 324
 325         if (!ret)
 326                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 327
 328         return !ret;
 329 }
 330
 331 #define MAX_TRY_TIMES 200
 332 #define ASQ_DELAY_MS  10
 333
 334 static int
 335 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 336 {
 337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 338         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 339         struct i40evf_arq_msg_info info;
 340         enum i40evf_aq_result ret;
 341         int err, i = 0;
 342
 343         if (_atomic_set_cmd(vf, args->ops))
 344                 return -1;
 345
 346         info.msg = args->out_buffer;
 347         info.buf_len = args->out_size;
 348         info.ops = VIRTCHNL_OP_UNKNOWN;
 349         info.result = I40E_SUCCESS;
 350
 351         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 352                      args->in_args, args->in_args_size, NULL);
 353         if (err) {
 354                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 355                 _clear_cmd(vf);
 356                 return err;
 357         }
 358
 359         switch (args->ops) {
 360         case VIRTCHNL_OP_RESET_VF:
 361                 /*no need to process in this function */
 362                 err = 0;
 363                 break;
 364         case VIRTCHNL_OP_VERSION:
 365         case VIRTCHNL_OP_GET_VF_RESOURCES:
 366                 /* for init adminq commands, need to poll the response */
 367                 err = -1;
 368                 do {
 369                         ret = i40evf_read_pfmsg(dev, &info);
 370                         vf->cmd_retval = info.result;
 371                         if (ret == I40EVF_MSG_CMD) {
 372                                 err = 0;
 373                                 break;
 374                         } else if (ret == I40EVF_MSG_ERR)
 375                                 break;
 376                         rte_delay_ms(ASQ_DELAY_MS);
 377                         /* If don't read msg or read sys event, continue */
 378                 } while (i++ < MAX_TRY_TIMES);
 379                 _clear_cmd(vf);
 380                 break;
 381
 382         default:
 383                 /* for other adminq in running time, waiting the cmd done flag */
 384                 err = -1;
 385                 do {
 386                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 387                                 err = 0;
 388                                 break;
 389                         }
 390                         rte_delay_ms(ASQ_DELAY_MS);
 391                         /* If don't read msg or read sys event, continue */
 392                 } while (i++ < MAX_TRY_TIMES);
 393                 /* If there's no response is received, clear command */
 394                 if (i >= MAX_TRY_TIMES) {
 395                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 396                         _clear_cmd(vf);
 397                 }
 398                 break;
 399         }
 400
 401         return err | vf->cmd_retval;
 402 }
 403
 404 /*
 405  * Check API version with sync wait until version read or fail from admin queue
 406  */
 407 static int
 408 i40evf_check_api_version(struct rte_eth_dev *dev)
 409 {
 410         struct virtchnl_version_info version, *pver;
 411         int err;
 412         struct vf_cmd_info args;
 413         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 414
 415         version.major = VIRTCHNL_VERSION_MAJOR;
 416         version.minor = VIRTCHNL_VERSION_MINOR;
 417
 418         args.ops = VIRTCHNL_OP_VERSION;
 419         args.in_args = (uint8_t *)&version;
 420         args.in_args_size = sizeof(version);
 421         args.out_buffer = vf->aq_resp;
 422         args.out_size = I40E_AQ_BUF_SZ;
 423
 424         err = i40evf_execute_vf_cmd(dev, &args);
 425         if (err) {
 426                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 427                 return err;
 428         }
 429
 430         pver = (struct virtchnl_version_info *)args.out_buffer;
 431         vf->version_major = pver->major;
 432         vf->version_minor = pver->minor;
 433         if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 434                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 435                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 436         else {
 437                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 438                                         vf->version_major, vf->version_minor,
 439                                                 VIRTCHNL_VERSION_MAJOR,
 440                                                 VIRTCHNL_VERSION_MINOR);
 441                 return -1;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int
 448 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 449 {
 450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 451         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 452         int err;
 453         struct vf_cmd_info args;
 454         uint32_t caps, len;
 455
 456         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 457         args.out_buffer = vf->aq_resp;
 458         args.out_size = I40E_AQ_BUF_SZ;
 459         if (PF_IS_V11(vf)) {
 460                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 461                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 462                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 463                        VIRTCHNL_VF_OFFLOAD_VLAN |
 464                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 465                 args.in_args = (uint8_t *)&caps;
 466                 args.in_args_size = sizeof(caps);
 467         } else {
 468                 args.in_args = NULL;
 469                 args.in_args_size = 0;
 470         }
 471         err = i40evf_execute_vf_cmd(dev, &args);
 472
 473         if (err) {
 474                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 475                 return err;
 476         }
 477
 478         len =  sizeof(struct virtchnl_vf_resource) +
 479                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 480
 481         rte_memcpy(vf->vf_res, args.out_buffer,
 482                         RTE_MIN(args.out_size, len));
 483         i40e_vf_parse_hw_config(hw, vf->vf_res);
 484
 485         return 0;
 486 }
 487
 488 static int
 489 i40evf_config_promisc(struct rte_eth_dev *dev,
 490                       bool enable_unicast,
 491                       bool enable_multicast)
 492 {
 493         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 494         int err;
 495         struct vf_cmd_info args;
 496         struct virtchnl_promisc_info promisc;
 497
 498         promisc.flags = 0;
 499         promisc.vsi_id = vf->vsi_res->vsi_id;
 500
 501         if (enable_unicast)
 502                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 503
 504         if (enable_multicast)
 505                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 506
 507         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 508         args.in_args = (uint8_t *)&promisc;
 509         args.in_args_size = sizeof(promisc);
 510         args.out_buffer = vf->aq_resp;
 511         args.out_size = I40E_AQ_BUF_SZ;
 512
 513         err = i40evf_execute_vf_cmd(dev, &args);
 514
 515         if (err)
 516                 PMD_DRV_LOG(ERR, "fail to execute command "
 517                             "CONFIG_PROMISCUOUS_MODE");
 518         return err;
 519 }
 520
 521 static int
 522 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 523 {
 524         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 525         struct vf_cmd_info args;
 526         int ret;
 527
 528         memset(&args, 0, sizeof(args));
 529         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 530         args.in_args = NULL;
 531         args.in_args_size = 0;
 532         args.out_buffer = vf->aq_resp;
 533         args.out_size = I40E_AQ_BUF_SZ;
 534         ret = i40evf_execute_vf_cmd(dev, &args);
 535         if (ret)
 536                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 537                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 538
 539         return ret;
 540 }
 541
 542 static int
 543 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 544 {
 545         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 546         struct vf_cmd_info args;
 547         int ret;
 548
 549         memset(&args, 0, sizeof(args));
 550         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 551         args.in_args = NULL;
 552         args.in_args_size = 0;
 553         args.out_buffer = vf->aq_resp;
 554         args.out_size = I40E_AQ_BUF_SZ;
 555         ret = i40evf_execute_vf_cmd(dev, &args);
 556         if (ret)
 557                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 558                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 559
 560         return ret;
 561 }
 562
 563 static void
 564 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 565                                   uint16_t vsi_id,
 566                                   uint16_t queue_id,
 567                                   uint16_t nb_txq,
 568                                   struct i40e_tx_queue *txq)
 569 {
 570         txq_info->vsi_id = vsi_id;
 571         txq_info->queue_id = queue_id;
 572         if (queue_id < nb_txq) {
 573                 txq_info->ring_len = txq->nb_tx_desc;
 574                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 575         }
 576 }
 577
 578 static void
 579 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 580                                   uint16_t vsi_id,
 581                                   uint16_t queue_id,
 582                                   uint16_t nb_rxq,
 583                                   uint32_t max_pkt_size,
 584                                   struct i40e_rx_queue *rxq)
 585 {
 586         rxq_info->vsi_id = vsi_id;
 587         rxq_info->queue_id = queue_id;
 588         rxq_info->max_pkt_size = max_pkt_size;
 589         if (queue_id < nb_rxq) {
 590                 rxq_info->ring_len = rxq->nb_rx_desc;
 591                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 592                 rxq_info->databuffer_size =
 593                         (rte_pktmbuf_data_room_size(rxq->mp) -
 594                                 RTE_PKTMBUF_HEADROOM);
 595         }
 596 }
 597
 598 static int
 599 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 600 {
 601         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 602         struct i40e_rx_queue **rxq =
 603                 (struct i40e_rx_queue **)dev->data->rx_queues;
 604         struct i40e_tx_queue **txq =
 605                 (struct i40e_tx_queue **)dev->data->tx_queues;
 606         struct virtchnl_vsi_queue_config_info *vc_vqci;
 607         struct virtchnl_queue_pair_info *vc_qpi;
 608         struct vf_cmd_info args;
 609         uint16_t i, nb_qp = vf->num_queue_pairs;
 610         const uint32_t size =
 611                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 612         uint8_t buff[size];
 613         int ret;
 614
 615         memset(buff, 0, sizeof(buff));
 616         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 617         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 618         vc_vqci->num_queue_pairs = nb_qp;
 619
 620         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 621                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 622                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 623                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 624                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 625                                         vf->max_pkt_len, rxq[i]);
 626         }
 627         memset(&args, 0, sizeof(args));
 628         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 629         args.in_args = (uint8_t *)vc_vqci;
 630         args.in_args_size = size;
 631         args.out_buffer = vf->aq_resp;
 632         args.out_size = I40E_AQ_BUF_SZ;
 633         ret = i40evf_execute_vf_cmd(dev, &args);
 634         if (ret)
 635                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 636                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 637
 638         return ret;
 639 }
 640
 641 static int
 642 i40evf_config_irq_map(struct rte_eth_dev *dev)
 643 {
 644         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 645         struct vf_cmd_info args;
 646         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 647                 sizeof(struct virtchnl_vector_map)];
 648         struct virtchnl_irq_map_info *map_info;
 649         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 650         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 651         uint32_t vector_id;
 652         int i, err;
 653
 654         if (rte_intr_allow_others(intr_handle))
 655                 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 656         else
 657                 vector_id = I40E_MISC_VEC_ID;
 658
 659         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 660         map_info->num_vectors = 1;
 661         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 662         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 663         /* Alway use default dynamic MSIX interrupt */
 664         map_info->vecmap[0].vector_id = vector_id;
 665         /* Don't map any tx queue */
 666         map_info->vecmap[0].txq_map = 0;
 667         map_info->vecmap[0].rxq_map = 0;
 668         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 669                 map_info->vecmap[0].rxq_map |= 1 << i;
 670                 if (rte_intr_dp_is_en(intr_handle))
 671                         intr_handle->intr_vec[i] = vector_id;
 672         }
 673
 674         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 675         args.in_args = (u8 *)cmd_buffer;
 676         args.in_args_size = sizeof(cmd_buffer);
 677         args.out_buffer = vf->aq_resp;
 678         args.out_size = I40E_AQ_BUF_SZ;
 679         err = i40evf_execute_vf_cmd(dev, &args);
 680         if (err)
 681                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 682
 683         return err;
 684 }
 685
 686 static int
 687 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 688                                 bool on)
 689 {
 690         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 691         struct virtchnl_queue_select queue_select;
 692         int err;
 693         struct vf_cmd_info args;
 694         memset(&queue_select, 0, sizeof(queue_select));
 695         queue_select.vsi_id = vf->vsi_res->vsi_id;
 696
 697         if (isrx)
 698                 queue_select.rx_queues |= 1 << qid;
 699         else
 700                 queue_select.tx_queues |= 1 << qid;
 701
 702         if (on)
 703                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 704         else
 705                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 706         args.in_args = (u8 *)&queue_select;
 707         args.in_args_size = sizeof(queue_select);
 708         args.out_buffer = vf->aq_resp;
 709         args.out_size = I40E_AQ_BUF_SZ;
 710         err = i40evf_execute_vf_cmd(dev, &args);
 711         if (err)
 712                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 713                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 714
 715         return err;
 716 }
 717
 718 static int
 719 i40evf_start_queues(struct rte_eth_dev *dev)
 720 {
 721         struct rte_eth_dev_data *dev_data = dev->data;
 722         int i;
 723         struct i40e_rx_queue *rxq;
 724         struct i40e_tx_queue *txq;
 725
 726         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 727                 rxq = dev_data->rx_queues[i];
 728                 if (rxq->rx_deferred_start)
 729                         continue;
 730                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 731                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 732                         return -1;
 733                 }
 734         }
 735
 736         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 737                 txq = dev_data->tx_queues[i];
 738                 if (txq->tx_deferred_start)
 739                         continue;
 740                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 741                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 742                         return -1;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 i40evf_stop_queues(struct rte_eth_dev *dev)
 751 {
 752         int i;
 753
 754         /* Stop TX queues first */
 755         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 756                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 757                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 758                         return -1;
 759                 }
 760         }
 761
 762         /* Then stop RX queues */
 763         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 764                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 765                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 766                         return -1;
 767                 }
 768         }
 769
 770         return 0;
 771 }
 772
 773 static int
 774 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 775                     struct ether_addr *addr,
 776                     __rte_unused uint32_t index,
 777                     __rte_unused uint32_t pool)
 778 {
 779         struct virtchnl_ether_addr_list *list;
 780         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 781         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 782                         sizeof(struct virtchnl_ether_addr)];
 783         int err;
 784         struct vf_cmd_info args;
 785
 786         if (is_zero_ether_addr(addr)) {
 787                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 788                             addr->addr_bytes[0], addr->addr_bytes[1],
 789                             addr->addr_bytes[2], addr->addr_bytes[3],
 790                             addr->addr_bytes[4], addr->addr_bytes[5]);
 791                 return I40E_ERR_INVALID_MAC_ADDR;
 792         }
 793
 794         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 795         list->vsi_id = vf->vsi_res->vsi_id;
 796         list->num_elements = 1;
 797         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 798                                         sizeof(addr->addr_bytes));
 799
 800         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 801         args.in_args = cmd_buffer;
 802         args.in_args_size = sizeof(cmd_buffer);
 803         args.out_buffer = vf->aq_resp;
 804         args.out_size = I40E_AQ_BUF_SZ;
 805         err = i40evf_execute_vf_cmd(dev, &args);
 806         if (err)
 807                 PMD_DRV_LOG(ERR, "fail to execute command "
 808                             "OP_ADD_ETHER_ADDRESS");
 809         else
 810                 vf->vsi.mac_num++;
 811
 812         return err;
 813 }
 814
 815 static void
 816 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 817                             struct ether_addr *addr)
 818 {
 819         struct virtchnl_ether_addr_list *list;
 820         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 821         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 822                         sizeof(struct virtchnl_ether_addr)];
 823         int err;
 824         struct vf_cmd_info args;
 825
 826         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 827                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 828                             addr->addr_bytes[0], addr->addr_bytes[1],
 829                             addr->addr_bytes[2], addr->addr_bytes[3],
 830                             addr->addr_bytes[4], addr->addr_bytes[5]);
 831                 return;
 832         }
 833
 834         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 835         list->vsi_id = vf->vsi_res->vsi_id;
 836         list->num_elements = 1;
 837         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 838                         sizeof(addr->addr_bytes));
 839
 840         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 841         args.in_args = cmd_buffer;
 842         args.in_args_size = sizeof(cmd_buffer);
 843         args.out_buffer = vf->aq_resp;
 844         args.out_size = I40E_AQ_BUF_SZ;
 845         err = i40evf_execute_vf_cmd(dev, &args);
 846         if (err)
 847                 PMD_DRV_LOG(ERR, "fail to execute command "
 848                             "OP_DEL_ETHER_ADDRESS");
 849         else
 850                 vf->vsi.mac_num--;
 851         return;
 852 }
 853
 854 static void
 855 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 856 {
 857         struct rte_eth_dev_data *data = dev->data;
 858         struct ether_addr *addr;
 859
 860         addr = &data->mac_addrs[index];
 861
 862         i40evf_del_mac_addr_by_addr(dev, addr);
 863 }
 864
 865 static int
 866 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 867 {
 868         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 869         struct virtchnl_queue_select q_stats;
 870         int err;
 871         struct vf_cmd_info args;
 872
 873         memset(&q_stats, 0, sizeof(q_stats));
 874         q_stats.vsi_id = vf->vsi_res->vsi_id;
 875         args.ops = VIRTCHNL_OP_GET_STATS;
 876         args.in_args = (u8 *)&q_stats;
 877         args.in_args_size = sizeof(q_stats);
 878         args.out_buffer = vf->aq_resp;
 879         args.out_size = I40E_AQ_BUF_SZ;
 880
 881         err = i40evf_execute_vf_cmd(dev, &args);
 882         if (err) {
 883                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 884                 *pstats = NULL;
 885                 return err;
 886         }
 887         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 888         return 0;
 889 }
 890
 891 static void
 892 i40evf_stat_update_48(uint64_t *offset,
 893                    uint64_t *stat)
 894 {
 895         if (*stat >= *offset)
 896                 *stat = *stat - *offset;
 897         else
 898                 *stat = (uint64_t)((*stat +
 899                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
 900
 901         *stat &= I40E_48_BIT_MASK;
 902 }
 903
 904 static void
 905 i40evf_stat_update_32(uint64_t *offset,
 906                    uint64_t *stat)
 907 {
 908         if (*stat >= *offset)
 909                 *stat = (uint64_t)(*stat - *offset);
 910         else
 911                 *stat = (uint64_t)((*stat +
 912                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
 913 }
 914
 915 static void
 916 i40evf_update_vsi_stats(struct i40e_vsi *vsi,
 917                                         struct i40e_eth_stats *nes)
 918 {
 919         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 920
 921         i40evf_stat_update_48(&oes->rx_bytes,
 922                             &nes->rx_bytes);
 923         i40evf_stat_update_48(&oes->rx_unicast,
 924                             &nes->rx_unicast);
 925         i40evf_stat_update_48(&oes->rx_multicast,
 926                             &nes->rx_multicast);
 927         i40evf_stat_update_48(&oes->rx_broadcast,
 928                             &nes->rx_broadcast);
 929         i40evf_stat_update_32(&oes->rx_discards,
 930                                 &nes->rx_discards);
 931         i40evf_stat_update_32(&oes->rx_unknown_protocol,
 932                             &nes->rx_unknown_protocol);
 933         i40evf_stat_update_48(&oes->tx_bytes,
 934                             &nes->tx_bytes);
 935         i40evf_stat_update_48(&oes->tx_unicast,
 936                             &nes->tx_unicast);
 937         i40evf_stat_update_48(&oes->tx_multicast,
 938                             &nes->tx_multicast);
 939         i40evf_stat_update_48(&oes->tx_broadcast,
 940                             &nes->tx_broadcast);
 941         i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
 942         i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
 943 }
 944
 945 static int
 946 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 947 {
 948         int ret;
 949         struct i40e_eth_stats *pstats = NULL;
 950         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 951         struct i40e_vsi *vsi = &vf->vsi;
 952
 953         ret = i40evf_update_stats(dev, &pstats);
 954         if (ret != 0)
 955                 return 0;
 956
 957         i40evf_update_vsi_stats(vsi, pstats);
 958
 959         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 960                                                 pstats->rx_broadcast;
 961         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 962                                                 pstats->tx_unicast;
 963         stats->imissed = pstats->rx_discards;
 964         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 965         stats->ibytes = pstats->rx_bytes;
 966         stats->obytes = pstats->tx_bytes;
 967
 968         return 0;
 969 }
 970
 971 static void
 972 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 973 {
 974         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 975         struct i40e_eth_stats *pstats = NULL;
 976
 977         /* read stat values to clear hardware registers */
 978         i40evf_update_stats(dev, &pstats);
 979
 980         /* set stats offset base on current values */
 981         vf->vsi.eth_stats_offset = *pstats;
 982 }
 983
 984 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 985                                       struct rte_eth_xstat_name *xstats_names,
 986                                       __rte_unused unsigned limit)
 987 {
 988         unsigned i;
 989
 990         if (xstats_names != NULL)
 991                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 992                         snprintf(xstats_names[i].name,
 993                                 sizeof(xstats_names[i].name),
 994                                 "%s", rte_i40evf_stats_strings[i].name);
 995                 }
 996         return I40EVF_NB_XSTATS;
 997 }
 998
 999 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1000                                  struct rte_eth_xstat *xstats, unsigned n)
1001 {
1002         int ret;
1003         unsigned i;
1004         struct i40e_eth_stats *pstats = NULL;
1005         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1006         struct i40e_vsi *vsi = &vf->vsi;
1007
1008         if (n < I40EVF_NB_XSTATS)
1009                 return I40EVF_NB_XSTATS;
1010
1011         ret = i40evf_update_stats(dev, &pstats);
1012         if (ret != 0)
1013                 return 0;
1014
1015         if (!xstats)
1016                 return 0;
1017
1018         i40evf_update_vsi_stats(vsi, pstats);
1019
1020         /* loop over xstats array and values from pstats */
1021         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1022                 xstats[i].id = i;
1023                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1024                         rte_i40evf_stats_strings[i].offset);
1025         }
1026
1027         return I40EVF_NB_XSTATS;
1028 }
1029
1030 static int
1031 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1032 {
1033         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1034         struct virtchnl_vlan_filter_list *vlan_list;
1035         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1036                                                         sizeof(uint16_t)];
1037         int err;
1038         struct vf_cmd_info args;
1039
1040         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1041         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1042         vlan_list->num_elements = 1;
1043         vlan_list->vlan_id[0] = vlanid;
1044
1045         args.ops = VIRTCHNL_OP_ADD_VLAN;
1046         args.in_args = (u8 *)&cmd_buffer;
1047         args.in_args_size = sizeof(cmd_buffer);
1048         args.out_buffer = vf->aq_resp;
1049         args.out_size = I40E_AQ_BUF_SZ;
1050         err = i40evf_execute_vf_cmd(dev, &args);
1051         if (err)
1052                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1053
1054         return err;
1055 }
1056
1057 static int
1058 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1059 {
1060         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1061         struct virtchnl_vlan_filter_list *vlan_list;
1062         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1063                                                         sizeof(uint16_t)];
1064         int err;
1065         struct vf_cmd_info args;
1066
1067         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1068         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1069         vlan_list->num_elements = 1;
1070         vlan_list->vlan_id[0] = vlanid;
1071
1072         args.ops = VIRTCHNL_OP_DEL_VLAN;
1073         args.in_args = (u8 *)&cmd_buffer;
1074         args.in_args_size = sizeof(cmd_buffer);
1075         args.out_buffer = vf->aq_resp;
1076         args.out_size = I40E_AQ_BUF_SZ;
1077         err = i40evf_execute_vf_cmd(dev, &args);
1078         if (err)
1079                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1080
1081         return err;
1082 }
1083
1084 static const struct rte_pci_id pci_id_i40evf_map[] = {
1085         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1086         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1087         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1088         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1089         { .vendor_id = 0, /* sentinel */ },
1090 };
1091
1092 static inline int
1093 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1094                                     struct rte_eth_link *link)
1095 {
1096         struct rte_eth_link *dst = &(dev->data->dev_link);
1097         struct rte_eth_link *src = link;
1098
1099         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1100                                         *(uint64_t *)src) == 0)
1101                 return -1;
1102
1103         return 0;
1104 }
1105
1106 /* Disable IRQ0 */
1107 static inline void
1108 i40evf_disable_irq0(struct i40e_hw *hw)
1109 {
1110         /* Disable all interrupt types */
1111         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1112         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1113                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1114         I40EVF_WRITE_FLUSH(hw);
1115 }
1116
1117 /* Enable IRQ0 */
1118 static inline void
1119 i40evf_enable_irq0(struct i40e_hw *hw)
1120 {
1121         /* Enable admin queue interrupt trigger */
1122         uint32_t val;
1123
1124         i40evf_disable_irq0(hw);
1125         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1126         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1127                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1128         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1129
1130         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1131                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1132                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1133                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1134
1135         I40EVF_WRITE_FLUSH(hw);
1136 }
1137
1138 static int
1139 i40evf_reset_vf(struct i40e_hw *hw)
1140 {
1141         int i, reset;
1142
1143         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1144                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1145                 return -1;
1146         }
1147         /**
1148           * After issuing vf reset command to pf, pf won't necessarily
1149           * reset vf, it depends on what state it exactly is. If it's not
1150           * initialized yet, it won't have vf reset since it's in a certain
1151           * state. If not, it will try to reset. Even vf is reset, pf will
1152           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1153           * it to ACTIVE. In this duration, vf may not catch the moment that
1154           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1155           */
1156         rte_delay_ms(200);
1157
1158         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1159                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1160                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1161                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1162                 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1163                         break;
1164                 else
1165                         rte_delay_ms(50);
1166         }
1167
1168         if (i >= MAX_RESET_WAIT_CNT) {
1169                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1170                 return -1;
1171         }
1172
1173         return 0;
1174 }
1175
1176 static int
1177 i40evf_init_vf(struct rte_eth_dev *dev)
1178 {
1179         int i, err, bufsz;
1180         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1181         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1182         uint16_t interval =
1183                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1184
1185         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1186         vf->dev_data = dev->data;
1187         err = i40e_set_mac_type(hw);
1188         if (err) {
1189                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1190                 goto err;
1191         }
1192
1193         i40e_init_adminq_parameter(hw);
1194         err = i40e_init_adminq(hw);
1195         if (err) {
1196                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1197                 goto err;
1198         }
1199
1200         /* Reset VF and wait until it's complete */
1201         if (i40evf_reset_vf(hw)) {
1202                 PMD_INIT_LOG(ERR, "reset NIC failed");
1203                 goto err_aq;
1204         }
1205
1206         /* VF reset, shutdown admin queue and initialize again */
1207         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1208                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1209                 goto err;
1210         }
1211
1212         i40e_init_adminq_parameter(hw);
1213         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1214                 PMD_INIT_LOG(ERR, "init_adminq failed");
1215                 goto err;
1216         }
1217         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1218         if (!vf->aq_resp) {
1219                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1220                 goto err_aq;
1221         }
1222         if (i40evf_check_api_version(dev) != 0) {
1223                 PMD_INIT_LOG(ERR, "check_api version failed");
1224                 goto err_api;
1225         }
1226         bufsz = sizeof(struct virtchnl_vf_resource) +
1227                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1228         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1229         if (!vf->vf_res) {
1230                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1231                 goto err_api;
1232         }
1233
1234         if (i40evf_get_vf_resource(dev) != 0) {
1235                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1236                 goto err_alloc;
1237         }
1238
1239         /* got VF config message back from PF, now we can parse it */
1240         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1241                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1242                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1243         }
1244
1245         if (!vf->vsi_res) {
1246                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1247                 goto err_alloc;
1248         }
1249
1250         if (hw->mac.type == I40E_MAC_X722_VF)
1251                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1252         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1253         vf->vsi.type = (enum i40e_vsi_type)vf->vsi_res->vsi_type;
1254         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1255         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1256
1257         /* Store the MAC address configured by host, or generate random one */
1258         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1259                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1260         else
1261                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1262
1263         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1264                        (I40E_ITR_INDEX_DEFAULT <<
1265                         I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1266                        (interval <<
1267                         I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1268         I40EVF_WRITE_FLUSH(hw);
1269
1270         return 0;
1271
1272 err_alloc:
1273         rte_free(vf->vf_res);
1274         vf->vsi_res = NULL;
1275 err_api:
1276         rte_free(vf->aq_resp);
1277 err_aq:
1278         i40e_shutdown_adminq(hw); /* ignore error */
1279 err:
1280         return -1;
1281 }
1282
1283 static int
1284 i40evf_uninit_vf(struct rte_eth_dev *dev)
1285 {
1286         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1287         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1288
1289         PMD_INIT_FUNC_TRACE();
1290
1291         if (hw->adapter_stopped == 0)
1292                 i40evf_dev_close(dev);
1293         rte_free(vf->vf_res);
1294         vf->vf_res = NULL;
1295         rte_free(vf->aq_resp);
1296         vf->aq_resp = NULL;
1297
1298         return 0;
1299 }
1300
1301 static void
1302 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1303                 __rte_unused uint16_t msglen)
1304 {
1305         struct virtchnl_pf_event *pf_msg =
1306                         (struct virtchnl_pf_event *)msg;
1307         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1308
1309         switch (pf_msg->event) {
1310         case VIRTCHNL_EVENT_RESET_IMPENDING:
1311                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1312                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1313                                               NULL, NULL);
1314                 break;
1315         case VIRTCHNL_EVENT_LINK_CHANGE:
1316                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1317                 vf->link_up = pf_msg->event_data.link_event.link_status;
1318                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1319                 break;
1320         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1321                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1322                 break;
1323         default:
1324                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1325                 break;
1326         }
1327 }
1328
1329 static void
1330 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1331 {
1332         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1333         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1334         struct i40e_arq_event_info info;
1335         uint16_t pending, aq_opc;
1336         enum virtchnl_ops msg_opc;
1337         enum i40e_status_code msg_ret;
1338         int ret;
1339
1340         info.buf_len = I40E_AQ_BUF_SZ;
1341         if (!vf->aq_resp) {
1342                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1343                 return;
1344         }
1345         info.msg_buf = vf->aq_resp;
1346
1347         pending = 1;
1348         while (pending) {
1349                 ret = i40e_clean_arq_element(hw, &info, &pending);
1350
1351                 if (ret != I40E_SUCCESS) {
1352                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1353                                     "ret: %d", ret);
1354                         break;
1355                 }
1356                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1357                 /* For the message sent from pf to vf, opcode is stored in
1358                  * cookie_high of struct i40e_aq_desc, while return error code
1359                  * are stored in cookie_low, Which is done by
1360                  * i40e_aq_send_msg_to_vf in PF driver.*/
1361                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1362                                                   info.desc.cookie_high);
1363                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1364                                                   info.desc.cookie_low);
1365                 switch (aq_opc) {
1366                 case i40e_aqc_opc_send_msg_to_vf:
1367                         if (msg_opc == VIRTCHNL_OP_EVENT)
1368                                 /* process event*/
1369                                 i40evf_handle_pf_event(dev, info.msg_buf,
1370                                                        info.msg_len);
1371                         else {
1372                                 /* read message and it's expected one */
1373                                 if (msg_opc == vf->pend_cmd) {
1374                                         vf->cmd_retval = msg_ret;
1375                                         /* prevent compiler reordering */
1376                                         rte_compiler_barrier();
1377                                         _clear_cmd(vf);
1378                                 } else
1379                                         PMD_DRV_LOG(ERR, "command mismatch,"
1380                                                 "expect %u, get %u",
1381                                                 vf->pend_cmd, msg_opc);
1382                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1383                                              " opcode = %d", msg_opc);
1384                         }
1385                         break;
1386                 default:
1387                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1388                                     aq_opc);
1389                         break;
1390                 }
1391         }
1392 }
1393
1394 /**
1395  * Interrupt handler triggered by NIC  for handling
1396  * specific interrupt. Only adminq interrupt is processed in VF.
1397  *
1398  * @param handle
1399  *  Pointer to interrupt handle.
1400  * @param param
1401  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1402  *
1403  * @return
1404  *  void
1405  */
1406 static void
1407 i40evf_dev_interrupt_handler(void *param)
1408 {
1409         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1410         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1411         uint32_t icr0;
1412
1413         i40evf_disable_irq0(hw);
1414
1415         /* read out interrupt causes */
1416         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1417
1418         /* No interrupt event indicated */
1419         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1420                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1421                 goto done;
1422         }
1423
1424         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1425                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1426                 i40evf_handle_aq_msg(dev);
1427         }
1428
1429         /* Link Status Change interrupt */
1430         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1431                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1432                                    " do nothing");
1433
1434 done:
1435         i40evf_enable_irq0(hw);
1436         rte_intr_enable(dev->intr_handle);
1437 }
1438
1439 static int
1440 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1441 {
1442         struct i40e_hw *hw
1443                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1444         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1445
1446         PMD_INIT_FUNC_TRACE();
1447
1448         /* assign ops func pointer */
1449         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1450         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1451         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1452
1453         /*
1454          * For secondary processes, we don't initialise any further as primary
1455          * has already done this work.
1456          */
1457         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1458                 i40e_set_rx_function(eth_dev);
1459                 i40e_set_tx_function(eth_dev);
1460                 return 0;
1461         }
1462         i40e_set_default_ptype_table(eth_dev);
1463         rte_eth_copy_pci_info(eth_dev, pci_dev);
1464         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1465
1466         hw->vendor_id = pci_dev->id.vendor_id;
1467         hw->device_id = pci_dev->id.device_id;
1468         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1469         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1470         hw->bus.device = pci_dev->addr.devid;
1471         hw->bus.func = pci_dev->addr.function;
1472         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1473         hw->adapter_stopped = 0;
1474
1475         if(i40evf_init_vf(eth_dev) != 0) {
1476                 PMD_INIT_LOG(ERR, "Init vf failed");
1477                 return -1;
1478         }
1479
1480         /* register callback func to eal lib */
1481         rte_intr_callback_register(&pci_dev->intr_handle,
1482                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1483
1484         /* enable uio intr after callback register */
1485         rte_intr_enable(&pci_dev->intr_handle);
1486
1487         /* configure and enable device interrupt */
1488         i40evf_enable_irq0(hw);
1489
1490         /* copy mac addr */
1491         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1492                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1493                                         0);
1494         if (eth_dev->data->mac_addrs == NULL) {
1495                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1496                                 " store MAC addresses",
1497                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1498                 return -ENOMEM;
1499         }
1500         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1501                         &eth_dev->data->mac_addrs[0]);
1502
1503         return 0;
1504 }
1505
1506 static int
1507 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1508 {
1509         PMD_INIT_FUNC_TRACE();
1510
1511         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1512                 return -EPERM;
1513
1514         eth_dev->dev_ops = NULL;
1515         eth_dev->rx_pkt_burst = NULL;
1516         eth_dev->tx_pkt_burst = NULL;
1517
1518         if (i40evf_uninit_vf(eth_dev) != 0) {
1519                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1520                 return -1;
1521         }
1522
1523         rte_free(eth_dev->data->mac_addrs);
1524         eth_dev->data->mac_addrs = NULL;
1525
1526         return 0;
1527 }
1528
1529 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1530         struct rte_pci_device *pci_dev)
1531 {
1532         return rte_eth_dev_pci_generic_probe(pci_dev,
1533                 sizeof(struct i40e_adapter), i40evf_dev_init);
1534 }
1535
1536 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1537 {
1538         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1539 }
1540
1541 /*
1542  * virtual function driver struct
1543  */
1544 static struct rte_pci_driver rte_i40evf_pmd = {
1545         .id_table = pci_id_i40evf_map,
1546         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1547         .probe = eth_i40evf_pci_probe,
1548         .remove = eth_i40evf_pci_remove,
1549 };
1550
1551 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1552 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1553 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1554
1555 static int
1556 i40evf_dev_configure(struct rte_eth_dev *dev)
1557 {
1558         struct i40e_adapter *ad =
1559                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1560         struct rte_eth_conf *conf = &dev->data->dev_conf;
1561         struct i40e_vf *vf;
1562
1563         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1564          * allocation or vector Rx preconditions we will reset it.
1565          */
1566         ad->rx_bulk_alloc_allowed = true;
1567         ad->rx_vec_allowed = true;
1568         ad->tx_simple_allowed = true;
1569         ad->tx_vec_allowed = true;
1570
1571         /* For non-DPDK PF drivers, VF has no ability to disable HW
1572          * CRC strip, and is implicitly enabled by the PF.
1573          */
1574         if (!conf->rxmode.hw_strip_crc) {
1575                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1576                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1577                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1578                         /* Peer is running non-DPDK PF driver. */
1579                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1580                         return -EINVAL;
1581                 }
1582         }
1583
1584         return i40evf_init_vlan(dev);
1585 }
1586
1587 static int
1588 i40evf_init_vlan(struct rte_eth_dev *dev)
1589 {
1590         /* Apply vlan offload setting */
1591         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1592
1593         return I40E_SUCCESS;
1594 }
1595
1596 static void
1597 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1598 {
1599         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1600
1601         /* Vlan stripping setting */
1602         if (mask & ETH_VLAN_STRIP_MASK) {
1603                 /* Enable or disable VLAN stripping */
1604                 if (dev_conf->rxmode.hw_vlan_strip)
1605                         i40evf_enable_vlan_strip(dev);
1606                 else
1607                         i40evf_disable_vlan_strip(dev);
1608         }
1609 }
1610
1611 static int
1612 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1613 {
1614         struct i40e_rx_queue *rxq;
1615         int err = 0;
1616         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1617
1618         PMD_INIT_FUNC_TRACE();
1619
1620         if (rx_queue_id < dev->data->nb_rx_queues) {
1621                 rxq = dev->data->rx_queues[rx_queue_id];
1622
1623                 err = i40e_alloc_rx_queue_mbufs(rxq);
1624                 if (err) {
1625                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1626                         return err;
1627                 }
1628
1629                 rte_wmb();
1630
1631                 /* Init the RX tail register. */
1632                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1633                 I40EVF_WRITE_FLUSH(hw);
1634
1635                 /* Ready to switch the queue on */
1636                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1637
1638                 if (err)
1639                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1640                                     rx_queue_id);
1641                 else
1642                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1643         }
1644
1645         return err;
1646 }
1647
1648 static int
1649 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1650 {
1651         struct i40e_rx_queue *rxq;
1652         int err;
1653
1654         if (rx_queue_id < dev->data->nb_rx_queues) {
1655                 rxq = dev->data->rx_queues[rx_queue_id];
1656
1657                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1658
1659                 if (err) {
1660                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1661                                     rx_queue_id);
1662                         return err;
1663                 }
1664
1665                 i40e_rx_queue_release_mbufs(rxq);
1666                 i40e_reset_rx_queue(rxq);
1667                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1668         }
1669
1670         return 0;
1671 }
1672
1673 static int
1674 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1675 {
1676         int err = 0;
1677
1678         PMD_INIT_FUNC_TRACE();
1679
1680         if (tx_queue_id < dev->data->nb_tx_queues) {
1681
1682                 /* Ready to switch the queue on */
1683                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1684
1685                 if (err)
1686                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1687                                     tx_queue_id);
1688                 else
1689                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1690         }
1691
1692         return err;
1693 }
1694
1695 static int
1696 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1697 {
1698         struct i40e_tx_queue *txq;
1699         int err;
1700
1701         if (tx_queue_id < dev->data->nb_tx_queues) {
1702                 txq = dev->data->tx_queues[tx_queue_id];
1703
1704                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1705
1706                 if (err) {
1707                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1708                                     tx_queue_id);
1709                         return err;
1710                 }
1711
1712                 i40e_tx_queue_release_mbufs(txq);
1713                 i40e_reset_tx_queue(txq);
1714                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1715         }
1716
1717         return 0;
1718 }
1719
1720 static int
1721 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1722 {
1723         int ret;
1724
1725         if (on)
1726                 ret = i40evf_add_vlan(dev, vlan_id);
1727         else
1728                 ret = i40evf_del_vlan(dev,vlan_id);
1729
1730         return ret;
1731 }
1732
1733 static int
1734 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1735 {
1736         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1737         struct rte_eth_dev_data *dev_data = dev->data;
1738         struct rte_pktmbuf_pool_private *mbp_priv;
1739         uint16_t buf_size, len;
1740
1741         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1742         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1743         I40EVF_WRITE_FLUSH(hw);
1744
1745         /* Calculate the maximum packet length allowed */
1746         mbp_priv = rte_mempool_get_priv(rxq->mp);
1747         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1748                                         RTE_PKTMBUF_HEADROOM);
1749         rxq->hs_mode = i40e_header_split_none;
1750         rxq->rx_hdr_len = 0;
1751         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1752         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1753         rxq->max_pkt_len = RTE_MIN(len,
1754                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1755
1756         /**
1757          * Check if the jumbo frame and maximum packet length are set correctly
1758          */
1759         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1760                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1761                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1762                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1763                                 "larger than %u and smaller than %u, as jumbo "
1764                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1765                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1766                         return I40E_ERR_CONFIG;
1767                 }
1768         } else {
1769                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1770                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1771                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1772                                 "larger than %u and smaller than %u, as jumbo "
1773                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1774                                                 (uint32_t)ETHER_MAX_LEN);
1775                         return I40E_ERR_CONFIG;
1776                 }
1777         }
1778
1779         if (dev_data->dev_conf.rxmode.enable_scatter ||
1780             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1781                 dev_data->scattered_rx = 1;
1782         }
1783
1784         return 0;
1785 }
1786
1787 static int
1788 i40evf_rx_init(struct rte_eth_dev *dev)
1789 {
1790         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1791         uint16_t i;
1792         int ret = I40E_SUCCESS;
1793         struct i40e_rx_queue **rxq =
1794                 (struct i40e_rx_queue **)dev->data->rx_queues;
1795
1796         i40evf_config_rss(vf);
1797         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1798                 if (!rxq[i] || !rxq[i]->q_set)
1799                         continue;
1800                 ret = i40evf_rxq_init(dev, rxq[i]);
1801                 if (ret != I40E_SUCCESS)
1802                         break;
1803         }
1804         if (ret == I40E_SUCCESS)
1805                 i40e_set_rx_function(dev);
1806
1807         return ret;
1808 }
1809
1810 static void
1811 i40evf_tx_init(struct rte_eth_dev *dev)
1812 {
1813         uint16_t i;
1814         struct i40e_tx_queue **txq =
1815                 (struct i40e_tx_queue **)dev->data->tx_queues;
1816         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1817
1818         for (i = 0; i < dev->data->nb_tx_queues; i++)
1819                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1820
1821         i40e_set_tx_function(dev);
1822 }
1823
1824 static inline void
1825 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1826 {
1827         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1828         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1829         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1830
1831         if (!rte_intr_allow_others(intr_handle)) {
1832                 I40E_WRITE_REG(hw,
1833                                I40E_VFINT_DYN_CTL01,
1834                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1835                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1836                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1837                 I40EVF_WRITE_FLUSH(hw);
1838                 return;
1839         }
1840
1841         I40EVF_WRITE_FLUSH(hw);
1842 }
1843
1844 static inline void
1845 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1846 {
1847         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1848         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1849         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1850
1851         if (!rte_intr_allow_others(intr_handle)) {
1852                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1853                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1854                 I40EVF_WRITE_FLUSH(hw);
1855                 return;
1856         }
1857
1858         I40EVF_WRITE_FLUSH(hw);
1859 }
1860
1861 static int
1862 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1863 {
1864         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1865         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1866         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1867         uint16_t interval =
1868                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1869         uint16_t msix_intr;
1870
1871         msix_intr = intr_handle->intr_vec[queue_id];
1872         if (msix_intr == I40E_MISC_VEC_ID)
1873                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1874                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1875                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1876                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1877                                (interval <<
1878                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1879         else
1880                 I40E_WRITE_REG(hw,
1881                                I40E_VFINT_DYN_CTLN1(msix_intr -
1882                                                     I40E_RX_VEC_START),
1883                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1884                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1885                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1886                                (interval <<
1887                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1888
1889         I40EVF_WRITE_FLUSH(hw);
1890
1891         rte_intr_enable(&pci_dev->intr_handle);
1892
1893         return 0;
1894 }
1895
1896 static int
1897 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1898 {
1899         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1900         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1901         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1902         uint16_t msix_intr;
1903
1904         msix_intr = intr_handle->intr_vec[queue_id];
1905         if (msix_intr == I40E_MISC_VEC_ID)
1906                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1907         else
1908                 I40E_WRITE_REG(hw,
1909                                I40E_VFINT_DYN_CTLN1(msix_intr -
1910                                                     I40E_RX_VEC_START),
1911                                0);
1912
1913         I40EVF_WRITE_FLUSH(hw);
1914
1915         return 0;
1916 }
1917
1918 static void
1919 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1920 {
1921         struct virtchnl_ether_addr_list *list;
1922         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1923         int err, i, j;
1924         int next_begin = 0;
1925         int begin = 0;
1926         uint32_t len;
1927         struct ether_addr *addr;
1928         struct vf_cmd_info args;
1929
1930         do {
1931                 j = 0;
1932                 len = sizeof(struct virtchnl_ether_addr_list);
1933                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1934                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1935                                 continue;
1936                         len += sizeof(struct virtchnl_ether_addr);
1937                         if (len >= I40E_AQ_BUF_SZ) {
1938                                 next_begin = i + 1;
1939                                 break;
1940                         }
1941                 }
1942
1943                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1944                 if (!list) {
1945                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1946                         return;
1947                 }
1948
1949                 for (i = begin; i < next_begin; i++) {
1950                         addr = &dev->data->mac_addrs[i];
1951                         if (is_zero_ether_addr(addr))
1952                                 continue;
1953                         rte_memcpy(list->list[j].addr, addr->addr_bytes,
1954                                          sizeof(addr->addr_bytes));
1955                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1956                                     addr->addr_bytes[0], addr->addr_bytes[1],
1957                                     addr->addr_bytes[2], addr->addr_bytes[3],
1958                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1959                         j++;
1960                 }
1961                 list->vsi_id = vf->vsi_res->vsi_id;
1962                 list->num_elements = j;
1963                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1964                            VIRTCHNL_OP_DEL_ETH_ADDR;
1965                 args.in_args = (uint8_t *)list;
1966                 args.in_args_size = len;
1967                 args.out_buffer = vf->aq_resp;
1968                 args.out_size = I40E_AQ_BUF_SZ;
1969                 err = i40evf_execute_vf_cmd(dev, &args);
1970                 if (err) {
1971                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1972                                     add ? "OP_ADD_ETHER_ADDRESS" :
1973                                     "OP_DEL_ETHER_ADDRESS");
1974                 } else {
1975                         if (add)
1976                                 vf->vsi.mac_num++;
1977                         else
1978                                 vf->vsi.mac_num--;
1979                 }
1980                 rte_free(list);
1981                 begin = next_begin;
1982         } while (begin < I40E_NUM_MACADDR_MAX);
1983 }
1984
1985 static int
1986 i40evf_dev_start(struct rte_eth_dev *dev)
1987 {
1988         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1989         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1990         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1991         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1992         uint32_t intr_vector = 0;
1993
1994         PMD_INIT_FUNC_TRACE();
1995
1996         hw->adapter_stopped = 0;
1997
1998         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1999         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2000                                         dev->data->nb_tx_queues);
2001
2002         /* check and configure queue intr-vector mapping */
2003         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2004                 intr_vector = dev->data->nb_rx_queues;
2005                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2006                         return -1;
2007         }
2008
2009         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2010                 intr_handle->intr_vec =
2011                         rte_zmalloc("intr_vec",
2012                                     dev->data->nb_rx_queues * sizeof(int), 0);
2013                 if (!intr_handle->intr_vec) {
2014                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2015                                      " intr_vec", dev->data->nb_rx_queues);
2016                         return -ENOMEM;
2017                 }
2018         }
2019
2020         if (i40evf_rx_init(dev) != 0){
2021                 PMD_DRV_LOG(ERR, "failed to do RX init");
2022                 return -1;
2023         }
2024
2025         i40evf_tx_init(dev);
2026
2027         if (i40evf_configure_vsi_queues(dev) != 0) {
2028                 PMD_DRV_LOG(ERR, "configure queues failed");
2029                 goto err_queue;
2030         }
2031         if (i40evf_config_irq_map(dev)) {
2032                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2033                 goto err_queue;
2034         }
2035
2036         /* Set all mac addrs */
2037         i40evf_add_del_all_mac_addr(dev, TRUE);
2038
2039         if (i40evf_start_queues(dev) != 0) {
2040                 PMD_DRV_LOG(ERR, "enable queues failed");
2041                 goto err_mac;
2042         }
2043
2044         i40evf_enable_queues_intr(dev);
2045         return 0;
2046
2047 err_mac:
2048         i40evf_add_del_all_mac_addr(dev, FALSE);
2049 err_queue:
2050         return -1;
2051 }
2052
2053 static void
2054 i40evf_dev_stop(struct rte_eth_dev *dev)
2055 {
2056         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2057         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2058         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2059
2060         PMD_INIT_FUNC_TRACE();
2061
2062         if (hw->adapter_stopped == 1)
2063                 return;
2064         i40evf_stop_queues(dev);
2065         i40evf_disable_queues_intr(dev);
2066         i40e_dev_clear_queues(dev);
2067
2068         /* Clean datapath event and queue/vec mapping */
2069         rte_intr_efd_disable(intr_handle);
2070         if (intr_handle->intr_vec) {
2071                 rte_free(intr_handle->intr_vec);
2072                 intr_handle->intr_vec = NULL;
2073         }
2074         /* remove all mac addrs */
2075         i40evf_add_del_all_mac_addr(dev, FALSE);
2076         hw->adapter_stopped = 1;
2077
2078 }
2079
2080 static int
2081 i40evf_dev_link_update(struct rte_eth_dev *dev,
2082                        __rte_unused int wait_to_complete)
2083 {
2084         struct rte_eth_link new_link;
2085         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2086         /*
2087          * DPDK pf host provide interfacet to acquire link status
2088          * while Linux driver does not
2089          */
2090
2091         /* Linux driver PF host */
2092         switch (vf->link_speed) {
2093         case I40E_LINK_SPEED_100MB:
2094                 new_link.link_speed = ETH_SPEED_NUM_100M;
2095                 break;
2096         case I40E_LINK_SPEED_1GB:
2097                 new_link.link_speed = ETH_SPEED_NUM_1G;
2098                 break;
2099         case I40E_LINK_SPEED_10GB:
2100                 new_link.link_speed = ETH_SPEED_NUM_10G;
2101                 break;
2102         case I40E_LINK_SPEED_20GB:
2103                 new_link.link_speed = ETH_SPEED_NUM_20G;
2104                 break;
2105         case I40E_LINK_SPEED_25GB:
2106                 new_link.link_speed = ETH_SPEED_NUM_25G;
2107                 break;
2108         case I40E_LINK_SPEED_40GB:
2109                 new_link.link_speed = ETH_SPEED_NUM_40G;
2110                 break;
2111         default:
2112                 new_link.link_speed = ETH_SPEED_NUM_100M;
2113                 break;
2114         }
2115         /* full duplex only */
2116         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2117         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2118                                              ETH_LINK_DOWN;
2119
2120         i40evf_dev_atomic_write_link_status(dev, &new_link);
2121
2122         return 0;
2123 }
2124
2125 static void
2126 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2127 {
2128         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2129         int ret;
2130
2131         /* If enabled, just return */
2132         if (vf->promisc_unicast_enabled)
2133                 return;
2134
2135         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2136         if (ret == 0)
2137                 vf->promisc_unicast_enabled = TRUE;
2138 }
2139
2140 static void
2141 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2142 {
2143         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2144         int ret;
2145
2146         /* If disabled, just return */
2147         if (!vf->promisc_unicast_enabled)
2148                 return;
2149
2150         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2151         if (ret == 0)
2152                 vf->promisc_unicast_enabled = FALSE;
2153 }
2154
2155 static void
2156 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2157 {
2158         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2159         int ret;
2160
2161         /* If enabled, just return */
2162         if (vf->promisc_multicast_enabled)
2163                 return;
2164
2165         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2166         if (ret == 0)
2167                 vf->promisc_multicast_enabled = TRUE;
2168 }
2169
2170 static void
2171 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2172 {
2173         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2174         int ret;
2175
2176         /* If enabled, just return */
2177         if (!vf->promisc_multicast_enabled)
2178                 return;
2179
2180         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2181         if (ret == 0)
2182                 vf->promisc_multicast_enabled = FALSE;
2183 }
2184
2185 static void
2186 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2187 {
2188         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2189
2190         memset(dev_info, 0, sizeof(*dev_info));
2191         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2192         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2193         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2194         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2195         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2196         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2197         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2198         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2199         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2200         dev_info->rx_offload_capa =
2201                 DEV_RX_OFFLOAD_VLAN_STRIP |
2202                 DEV_RX_OFFLOAD_QINQ_STRIP |
2203                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2204                 DEV_RX_OFFLOAD_UDP_CKSUM |
2205                 DEV_RX_OFFLOAD_TCP_CKSUM;
2206         dev_info->tx_offload_capa =
2207                 DEV_TX_OFFLOAD_VLAN_INSERT |
2208                 DEV_TX_OFFLOAD_QINQ_INSERT |
2209                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2210                 DEV_TX_OFFLOAD_UDP_CKSUM |
2211                 DEV_TX_OFFLOAD_TCP_CKSUM |
2212                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2213
2214         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2215                 .rx_thresh = {
2216                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2217                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2218                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2219                 },
2220                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2221                 .rx_drop_en = 0,
2222         };
2223
2224         dev_info->default_txconf = (struct rte_eth_txconf) {
2225                 .tx_thresh = {
2226                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2227                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2228                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2229                 },
2230                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2231                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2232                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2233                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2234         };
2235
2236         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2237                 .nb_max = I40E_MAX_RING_DESC,
2238                 .nb_min = I40E_MIN_RING_DESC,
2239                 .nb_align = I40E_ALIGN_RING_DESC,
2240         };
2241
2242         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2243                 .nb_max = I40E_MAX_RING_DESC,
2244                 .nb_min = I40E_MIN_RING_DESC,
2245                 .nb_align = I40E_ALIGN_RING_DESC,
2246         };
2247 }
2248
2249 static void
2250 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2251 {
2252         if (i40evf_get_statistics(dev, stats))
2253                 PMD_DRV_LOG(ERR, "Get statistics failed");
2254 }
2255
2256 static void
2257 i40evf_dev_close(struct rte_eth_dev *dev)
2258 {
2259         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2260         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2261         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2262
2263         i40evf_dev_stop(dev);
2264         i40e_dev_free_queues(dev);
2265         i40evf_reset_vf(hw);
2266         i40e_shutdown_adminq(hw);
2267         /* disable uio intr before callback unregister */
2268         rte_intr_disable(intr_handle);
2269
2270         /* unregister callback func from eal lib */
2271         rte_intr_callback_unregister(intr_handle,
2272                                      i40evf_dev_interrupt_handler, dev);
2273         i40evf_disable_irq0(hw);
2274 }
2275
2276 /*
2277  * Reset VF device only to re-initialize resources in PMD layer
2278  */
2279 static int
2280 i40evf_dev_reset(struct rte_eth_dev *dev)
2281 {
2282         int ret;
2283
2284         ret = i40evf_dev_uninit(dev);
2285         if (ret)
2286                 return ret;
2287
2288         ret = i40evf_dev_init(dev);
2289
2290         return ret;
2291 }
2292
2293 static int
2294 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2295 {
2296         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2297         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2298         int ret;
2299
2300         if (!lut)
2301                 return -EINVAL;
2302
2303         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2304                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2305                                           lut, lut_size);
2306                 if (ret) {
2307                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2308                         return ret;
2309                 }
2310         } else {
2311                 uint32_t *lut_dw = (uint32_t *)lut;
2312                 uint16_t i, lut_size_dw = lut_size / 4;
2313
2314                 for (i = 0; i < lut_size_dw; i++)
2315                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2316         }
2317
2318         return 0;
2319 }
2320
2321 static int
2322 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2323 {
2324         struct i40e_vf *vf;
2325         struct i40e_hw *hw;
2326         int ret;
2327
2328         if (!vsi || !lut)
2329                 return -EINVAL;
2330
2331         vf = I40E_VSI_TO_VF(vsi);
2332         hw = I40E_VSI_TO_HW(vsi);
2333
2334         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2335                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2336                                           lut, lut_size);
2337                 if (ret) {
2338                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2339                         return ret;
2340                 }
2341         } else {
2342                 uint32_t *lut_dw = (uint32_t *)lut;
2343                 uint16_t i, lut_size_dw = lut_size / 4;
2344
2345                 for (i = 0; i < lut_size_dw; i++)
2346                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2347                 I40EVF_WRITE_FLUSH(hw);
2348         }
2349
2350         return 0;
2351 }
2352
2353 static int
2354 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2355                            struct rte_eth_rss_reta_entry64 *reta_conf,
2356                            uint16_t reta_size)
2357 {
2358         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2359         uint8_t *lut;
2360         uint16_t i, idx, shift;
2361         int ret;
2362
2363         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2364                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2365                         "(%d) doesn't match the number of hardware can "
2366                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2367                 return -EINVAL;
2368         }
2369
2370         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2371         if (!lut) {
2372                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2373                 return -ENOMEM;
2374         }
2375         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2376         if (ret)
2377                 goto out;
2378         for (i = 0; i < reta_size; i++) {
2379                 idx = i / RTE_RETA_GROUP_SIZE;
2380                 shift = i % RTE_RETA_GROUP_SIZE;
2381                 if (reta_conf[idx].mask & (1ULL << shift))
2382                         lut[i] = reta_conf[idx].reta[shift];
2383         }
2384         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2385
2386 out:
2387         rte_free(lut);
2388
2389         return ret;
2390 }
2391
2392 static int
2393 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2394                           struct rte_eth_rss_reta_entry64 *reta_conf,
2395                           uint16_t reta_size)
2396 {
2397         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2398         uint16_t i, idx, shift;
2399         uint8_t *lut;
2400         int ret;
2401
2402         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2403                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2404                         "(%d) doesn't match the number of hardware can "
2405                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2406                 return -EINVAL;
2407         }
2408
2409         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2410         if (!lut) {
2411                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2412                 return -ENOMEM;
2413         }
2414
2415         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2416         if (ret)
2417                 goto out;
2418         for (i = 0; i < reta_size; i++) {
2419                 idx = i / RTE_RETA_GROUP_SIZE;
2420                 shift = i % RTE_RETA_GROUP_SIZE;
2421                 if (reta_conf[idx].mask & (1ULL << shift))
2422                         reta_conf[idx].reta[shift] = lut[i];
2423         }
2424
2425 out:
2426         rte_free(lut);
2427
2428         return ret;
2429 }
2430
2431 static int
2432 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2433 {
2434         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2435         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2436         int ret = 0;
2437
2438         if (!key || key_len == 0) {
2439                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2440                 return 0;
2441         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2442                 sizeof(uint32_t)) {
2443                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2444                 return -EINVAL;
2445         }
2446
2447         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2448                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2449                         (struct i40e_aqc_get_set_rss_key_data *)key;
2450
2451                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2452                 if (ret)
2453                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2454                                      "via AQ");
2455         } else {
2456                 uint32_t *hash_key = (uint32_t *)key;
2457                 uint16_t i;
2458
2459                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2460                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2461                 I40EVF_WRITE_FLUSH(hw);
2462         }
2463
2464         return ret;
2465 }
2466
2467 static int
2468 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2469 {
2470         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2471         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2472         int ret;
2473
2474         if (!key || !key_len)
2475                 return -EINVAL;
2476
2477         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2478                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2479                         (struct i40e_aqc_get_set_rss_key_data *)key);
2480                 if (ret) {
2481                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2482                         return ret;
2483                 }
2484         } else {
2485                 uint32_t *key_dw = (uint32_t *)key;
2486                 uint16_t i;
2487
2488                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2489                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2490         }
2491         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2492
2493         return 0;
2494 }
2495
2496 static int
2497 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2498 {
2499         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2500         uint64_t rss_hf, hena;
2501         int ret;
2502
2503         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2504                                  rss_conf->rss_key_len);
2505         if (ret)
2506                 return ret;
2507
2508         rss_hf = rss_conf->rss_hf;
2509         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2510         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2511         if (hw->mac.type == I40E_MAC_X722)
2512                 hena &= ~I40E_RSS_HENA_ALL_X722;
2513         else
2514                 hena &= ~I40E_RSS_HENA_ALL;
2515         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2516         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2517         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2518         I40EVF_WRITE_FLUSH(hw);
2519
2520         return 0;
2521 }
2522
2523 static void
2524 i40evf_disable_rss(struct i40e_vf *vf)
2525 {
2526         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2527         uint64_t hena;
2528
2529         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2530         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2531         if (hw->mac.type == I40E_MAC_X722)
2532                 hena &= ~I40E_RSS_HENA_ALL_X722;
2533         else
2534                 hena &= ~I40E_RSS_HENA_ALL;
2535         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2536         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2537         I40EVF_WRITE_FLUSH(hw);
2538 }
2539
2540 static int
2541 i40evf_config_rss(struct i40e_vf *vf)
2542 {
2543         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2544         struct rte_eth_rss_conf rss_conf;
2545         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2546         uint16_t num;
2547
2548         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2549                 i40evf_disable_rss(vf);
2550                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2551                 return 0;
2552         }
2553
2554         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2555         /* Fill out the look up table */
2556         for (i = 0, j = 0; i < nb_q; i++, j++) {
2557                 if (j >= num)
2558                         j = 0;
2559                 lut = (lut << 8) | j;
2560                 if ((i & 3) == 3)
2561                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2562         }
2563
2564         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2565         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2566                 i40evf_disable_rss(vf);
2567                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2568                 return 0;
2569         }
2570
2571         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2572                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2573                 /* Calculate the default hash key */
2574                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2575                         rss_key_default[i] = (uint32_t)rte_rand();
2576                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2577                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2578                         sizeof(uint32_t);
2579         }
2580
2581         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2582 }
2583
2584 static int
2585 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2586                            struct rte_eth_rss_conf *rss_conf)
2587 {
2588         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2589         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2591         uint64_t hena;
2592
2593         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2594         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2595         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2596                  ? I40E_RSS_HENA_ALL_X722
2597                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2598                 if (rss_hf != 0) /* Enable RSS */
2599                         return -EINVAL;
2600                 return 0;
2601         }
2602
2603         /* RSS enabled */
2604         if (rss_hf == 0) /* Disable RSS */
2605                 return -EINVAL;
2606
2607         return i40evf_hw_rss_hash_set(vf, rss_conf);
2608 }
2609
2610 static int
2611 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2612                              struct rte_eth_rss_conf *rss_conf)
2613 {
2614         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2615         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2616         uint64_t hena;
2617
2618         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2619                            &rss_conf->rss_key_len);
2620
2621         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2622         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2623         rss_conf->rss_hf = i40e_parse_hena(hena);
2624
2625         return 0;
2626 }
2627
2628 static int
2629 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2630 {
2631         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2632         struct rte_eth_dev_data *dev_data = vf->dev_data;
2633         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2634         int ret = 0;
2635
2636         /* check if mtu is within the allowed range */
2637         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2638                 return -EINVAL;
2639
2640         /* mtu setting is forbidden if port is start */
2641         if (dev_data->dev_started) {
2642                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2643                             dev_data->port_id);
2644                 return -EBUSY;
2645         }
2646
2647         if (frame_size > ETHER_MAX_LEN)
2648                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2649         else
2650                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2651
2652         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2653
2654         return ret;
2655 }
2656
2657 static void
2658 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2659                             struct ether_addr *mac_addr)
2660 {
2661         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2662
2663         if (!is_valid_assigned_ether_addr(mac_addr)) {
2664                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2665                 return;
2666         }
2667
2668         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2669                 return;
2670
2671         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2672                 return;
2673
2674         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2675
2676         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2677 }