drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_atomic.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum i40e_virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum i40e_virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   __rte_unused int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static int i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid,
 123                                 int on);
 124 static void i40evf_dev_close(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 128 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 129 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 130 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 131                                      uint16_t rx_queue_id);
 132 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 133                                     uint16_t rx_queue_id);
 134 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 135                                      uint16_t tx_queue_id);
 136 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 137                                     uint16_t tx_queue_id);
 138 static void i40evf_add_mac_addr(struct rte_eth_dev *dev,
 139                                 struct ether_addr *addr,
 140                                 uint32_t index,
 141                                 uint32_t pool);
 142 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 143 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 144                         struct rte_eth_rss_reta_entry64 *reta_conf,
 145                         uint16_t reta_size);
 146 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 147                         struct rte_eth_rss_reta_entry64 *reta_conf,
 148                         uint16_t reta_size);
 149 static int i40evf_config_rss(struct i40e_vf *vf);
 150 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 151                                       struct rte_eth_rss_conf *rss_conf);
 152 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 153                                         struct rte_eth_rss_conf *rss_conf);
 154 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 155 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 156                                         struct ether_addr *mac_addr);
 157 static int
 158 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 159 static int
 160 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 161 static void i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
 162                                    uint8_t *msg,
 163                                    uint16_t msglen);
 164
 165 /* Default hash key buffer for RSS */
 166 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 167
 168 struct rte_i40evf_xstats_name_off {
 169         char name[RTE_ETH_XSTATS_NAME_SIZE];
 170         unsigned offset;
 171 };
 172
 173 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 174         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 175         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 176         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 177         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 178         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 179         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 180                 rx_unknown_protocol)},
 181         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 182         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 183         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 184         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 185         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 186         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 187 };
 188
 189 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 190                 sizeof(rte_i40evf_stats_strings[0]))
 191
 192 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 193         .dev_configure        = i40evf_dev_configure,
 194         .dev_start            = i40evf_dev_start,
 195         .dev_stop             = i40evf_dev_stop,
 196         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 197         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 198         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 199         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 200         .link_update          = i40evf_dev_link_update,
 201         .stats_get            = i40evf_dev_stats_get,
 202         .xstats_get           = i40evf_dev_xstats_get,
 203         .xstats_get_names     = i40evf_dev_xstats_get_names,
 204         .xstats_reset         = i40evf_dev_xstats_reset,
 205         .dev_close            = i40evf_dev_close,
 206         .dev_infos_get        = i40evf_dev_info_get,
 207         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 208         .vlan_filter_set      = i40evf_vlan_filter_set,
 209         .vlan_offload_set     = i40evf_vlan_offload_set,
 210         .vlan_pvid_set        = i40evf_vlan_pvid_set,
 211         .rx_queue_start       = i40evf_dev_rx_queue_start,
 212         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 213         .tx_queue_start       = i40evf_dev_tx_queue_start,
 214         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 215         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 216         .rx_queue_release     = i40e_dev_rx_queue_release,
 217         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 218         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 219         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 220         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 221         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 222         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 223         .tx_queue_release     = i40e_dev_tx_queue_release,
 224         .rx_queue_count       = i40e_dev_rx_queue_count,
 225         .rxq_info_get         = i40e_rxq_info_get,
 226         .txq_info_get         = i40e_txq_info_get,
 227         .mac_addr_add         = i40evf_add_mac_addr,
 228         .mac_addr_remove      = i40evf_del_mac_addr,
 229         .reta_update          = i40evf_dev_rss_reta_update,
 230         .reta_query           = i40evf_dev_rss_reta_query,
 231         .rss_hash_update      = i40evf_dev_rss_hash_update,
 232         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 233         .mtu_set              = i40evf_dev_mtu_set,
 234         .mac_addr_set         = i40evf_set_default_mac_addr,
 235 };
 236
 237 /*
 238  * Read data in admin queue to get msg from pf driver
 239  */
 240 static enum i40evf_aq_result
 241 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 242 {
 243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 245         struct i40e_arq_event_info event;
 246         enum i40e_virtchnl_ops opcode;
 247         enum i40e_status_code retval;
 248         int ret;
 249         enum i40evf_aq_result result = I40EVF_MSG_NON;
 250
 251         event.buf_len = data->buf_len;
 252         event.msg_buf = data->msg;
 253         ret = i40e_clean_arq_element(hw, &event, NULL);
 254         /* Can't read any msg from adminQ */
 255         if (ret) {
 256                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 257                         result = I40EVF_MSG_ERR;
 258                 return result;
 259         }
 260
 261         opcode = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 262         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 263         /* pf sys event */
 264         if (opcode == I40E_VIRTCHNL_OP_EVENT) {
 265                 struct i40e_virtchnl_pf_event *vpe =
 266                         (struct i40e_virtchnl_pf_event *)event.msg_buf;
 267
 268                 result = I40EVF_MSG_SYS;
 269                 switch (vpe->event) {
 270                 case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
 271                         vf->link_up =
 272                                 vpe->event_data.link_event.link_status;
 273                         vf->link_speed =
 274                                 vpe->event_data.link_event.link_speed;
 275                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 276                         PMD_DRV_LOG(INFO, "Link status update:%s",
 277                                     vf->link_up ? "up" : "down");
 278                         break;
 279                 case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
 280                         vf->vf_reset = true;
 281                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 282                         PMD_DRV_LOG(INFO, "vf is reseting");
 283                         break;
 284                 case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 285                         vf->dev_closed = true;
 286                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 287                         PMD_DRV_LOG(INFO, "PF driver closed");
 288                         break;
 289                 default:
 290                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 291                                     __func__, vpe->event);
 292                 }
 293         } else {
 294                 /* async reply msg on command issued by vf previously */
 295                 result = I40EVF_MSG_CMD;
 296                 /* Actual data length read from PF */
 297                 data->msg_len = event.msg_len;
 298         }
 299
 300         data->result = retval;
 301         data->ops = opcode;
 302
 303         return result;
 304 }
 305
 306 /**
 307  * clear current command. Only call in case execute
 308  * _atomic_set_cmd successfully.
 309  */
 310 static inline void
 311 _clear_cmd(struct i40e_vf *vf)
 312 {
 313         rte_wmb();
 314         vf->pend_cmd = I40E_VIRTCHNL_OP_UNKNOWN;
 315 }
 316
 317 /*
 318  * Check there is pending cmd in execution. If none, set new command.
 319  */
 320 static inline int
 321 _atomic_set_cmd(struct i40e_vf *vf, enum i40e_virtchnl_ops ops)
 322 {
 323         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 324                         I40E_VIRTCHNL_OP_UNKNOWN, ops);
 325
 326         if (!ret)
 327                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 328
 329         return !ret;
 330 }
 331
 332 #define MAX_TRY_TIMES 200
 333 #define ASQ_DELAY_MS  10
 334
 335 static int
 336 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 337 {
 338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 340         struct i40evf_arq_msg_info info;
 341         enum i40evf_aq_result ret;
 342         int err, i = 0;
 343
 344         if (_atomic_set_cmd(vf, args->ops))
 345                 return -1;
 346
 347         info.msg = args->out_buffer;
 348         info.buf_len = args->out_size;
 349         info.ops = I40E_VIRTCHNL_OP_UNKNOWN;
 350         info.result = I40E_SUCCESS;
 351
 352         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 353                      args->in_args, args->in_args_size, NULL);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 356                 _clear_cmd(vf);
 357                 return err;
 358         }
 359
 360         switch (args->ops) {
 361         case I40E_VIRTCHNL_OP_RESET_VF:
 362                 /*no need to process in this function */
 363                 err = 0;
 364                 break;
 365         case I40E_VIRTCHNL_OP_VERSION:
 366         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 367                 /* for init adminq commands, need to poll the response */
 368                 err = -1;
 369                 do {
 370                         ret = i40evf_read_pfmsg(dev, &info);
 371                         vf->cmd_retval = info.result;
 372                         if (ret == I40EVF_MSG_CMD) {
 373                                 err = 0;
 374                                 break;
 375                         } else if (ret == I40EVF_MSG_ERR)
 376                                 break;
 377                         rte_delay_ms(ASQ_DELAY_MS);
 378                         /* If don't read msg or read sys event, continue */
 379                 } while (i++ < MAX_TRY_TIMES);
 380                 _clear_cmd(vf);
 381                 break;
 382
 383         default:
 384                 /* for other adminq in running time, waiting the cmd done flag */
 385                 err = -1;
 386                 do {
 387                         if (vf->pend_cmd == I40E_VIRTCHNL_OP_UNKNOWN) {
 388                                 err = 0;
 389                                 break;
 390                         }
 391                         rte_delay_ms(ASQ_DELAY_MS);
 392                         /* If don't read msg or read sys event, continue */
 393                 } while (i++ < MAX_TRY_TIMES);
 394                 break;
 395         }
 396
 397         return err | vf->cmd_retval;
 398 }
 399
 400 /*
 401  * Check API version with sync wait until version read or fail from admin queue
 402  */
 403 static int
 404 i40evf_check_api_version(struct rte_eth_dev *dev)
 405 {
 406         struct i40e_virtchnl_version_info version, *pver;
 407         int err;
 408         struct vf_cmd_info args;
 409         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 410
 411         version.major = I40E_VIRTCHNL_VERSION_MAJOR;
 412         version.minor = I40E_VIRTCHNL_VERSION_MINOR;
 413
 414         args.ops = I40E_VIRTCHNL_OP_VERSION;
 415         args.in_args = (uint8_t *)&version;
 416         args.in_args_size = sizeof(version);
 417         args.out_buffer = vf->aq_resp;
 418         args.out_size = I40E_AQ_BUF_SZ;
 419
 420         err = i40evf_execute_vf_cmd(dev, &args);
 421         if (err) {
 422                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 423                 return err;
 424         }
 425
 426         pver = (struct i40e_virtchnl_version_info *)args.out_buffer;
 427         vf->version_major = pver->major;
 428         vf->version_minor = pver->minor;
 429         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 430                 PMD_DRV_LOG(INFO, "Peer is DPDK PF host");
 431         else if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
 432                 (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR))
 433                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 434         else {
 435                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 436                                         vf->version_major, vf->version_minor,
 437                                                 I40E_VIRTCHNL_VERSION_MAJOR,
 438                                                 I40E_VIRTCHNL_VERSION_MINOR);
 439                 return -1;
 440         }
 441
 442         return 0;
 443 }
 444
 445 static int
 446 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 447 {
 448         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 449         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 450         int err;
 451         struct vf_cmd_info args;
 452         uint32_t caps, len;
 453
 454         args.ops = I40E_VIRTCHNL_OP_GET_VF_RESOURCES;
 455         args.out_buffer = vf->aq_resp;
 456         args.out_size = I40E_AQ_BUF_SZ;
 457         if (PF_IS_V11(vf)) {
 458                 caps = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 459                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 460                        I40E_VIRTCHNL_VF_OFFLOAD_RSS_REG |
 461                        I40E_VIRTCHNL_VF_OFFLOAD_VLAN |
 462                        I40E_VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 463                 args.in_args = (uint8_t *)&caps;
 464                 args.in_args_size = sizeof(caps);
 465         } else {
 466                 args.in_args = NULL;
 467                 args.in_args_size = 0;
 468         }
 469         err = i40evf_execute_vf_cmd(dev, &args);
 470
 471         if (err) {
 472                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 473                 return err;
 474         }
 475
 476         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 477                 I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource);
 478
 479         (void)rte_memcpy(vf->vf_res, args.out_buffer,
 480                         RTE_MIN(args.out_size, len));
 481         i40e_vf_parse_hw_config(hw, vf->vf_res);
 482
 483         return 0;
 484 }
 485
 486 static int
 487 i40evf_config_promisc(struct rte_eth_dev *dev,
 488                       bool enable_unicast,
 489                       bool enable_multicast)
 490 {
 491         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 492         int err;
 493         struct vf_cmd_info args;
 494         struct i40e_virtchnl_promisc_info promisc;
 495
 496         promisc.flags = 0;
 497         promisc.vsi_id = vf->vsi_res->vsi_id;
 498
 499         if (enable_unicast)
 500                 promisc.flags |= I40E_FLAG_VF_UNICAST_PROMISC;
 501
 502         if (enable_multicast)
 503                 promisc.flags |= I40E_FLAG_VF_MULTICAST_PROMISC;
 504
 505         args.ops = I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 506         args.in_args = (uint8_t *)&promisc;
 507         args.in_args_size = sizeof(promisc);
 508         args.out_buffer = vf->aq_resp;
 509         args.out_size = I40E_AQ_BUF_SZ;
 510
 511         err = i40evf_execute_vf_cmd(dev, &args);
 512
 513         if (err)
 514                 PMD_DRV_LOG(ERR, "fail to execute command "
 515                             "CONFIG_PROMISCUOUS_MODE");
 516         return err;
 517 }
 518
 519 /* Configure vlan and double vlan offload. Use flag to specify which part to configure */
 520 static int
 521 i40evf_config_vlan_offload(struct rte_eth_dev *dev,
 522                                 bool enable_vlan_strip)
 523 {
 524         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 525         int err;
 526         struct vf_cmd_info args;
 527         struct i40e_virtchnl_vlan_offload_info offload;
 528
 529         offload.vsi_id = vf->vsi_res->vsi_id;
 530         offload.enable_vlan_strip = enable_vlan_strip;
 531
 532         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD;
 533         args.in_args = (uint8_t *)&offload;
 534         args.in_args_size = sizeof(offload);
 535         args.out_buffer = vf->aq_resp;
 536         args.out_size = I40E_AQ_BUF_SZ;
 537
 538         err = i40evf_execute_vf_cmd(dev, &args);
 539         if (err)
 540                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_OFFLOAD");
 541
 542         return err;
 543 }
 544
 545 static int
 546 i40evf_config_vlan_pvid(struct rte_eth_dev *dev,
 547                                 struct i40e_vsi_vlan_pvid_info *info)
 548 {
 549         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 550         int err;
 551         struct vf_cmd_info args;
 552         struct i40e_virtchnl_pvid_info tpid_info;
 553
 554         if (info == NULL) {
 555                 PMD_DRV_LOG(ERR, "invalid parameters");
 556                 return I40E_ERR_PARAM;
 557         }
 558
 559         memset(&tpid_info, 0, sizeof(tpid_info));
 560         tpid_info.vsi_id = vf->vsi_res->vsi_id;
 561         (void)rte_memcpy(&tpid_info.info, info, sizeof(*info));
 562
 563         args.ops = (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CFG_VLAN_PVID;
 564         args.in_args = (uint8_t *)&tpid_info;
 565         args.in_args_size = sizeof(tpid_info);
 566         args.out_buffer = vf->aq_resp;
 567         args.out_size = I40E_AQ_BUF_SZ;
 568
 569         err = i40evf_execute_vf_cmd(dev, &args);
 570         if (err)
 571                 PMD_DRV_LOG(ERR, "fail to execute command CFG_VLAN_PVID");
 572
 573         return err;
 574 }
 575
 576 static void
 577 i40evf_fill_virtchnl_vsi_txq_info(struct i40e_virtchnl_txq_info *txq_info,
 578                                   uint16_t vsi_id,
 579                                   uint16_t queue_id,
 580                                   uint16_t nb_txq,
 581                                   struct i40e_tx_queue *txq)
 582 {
 583         txq_info->vsi_id = vsi_id;
 584         txq_info->queue_id = queue_id;
 585         if (queue_id < nb_txq) {
 586                 txq_info->ring_len = txq->nb_tx_desc;
 587                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 588         }
 589 }
 590
 591 static void
 592 i40evf_fill_virtchnl_vsi_rxq_info(struct i40e_virtchnl_rxq_info *rxq_info,
 593                                   uint16_t vsi_id,
 594                                   uint16_t queue_id,
 595                                   uint16_t nb_rxq,
 596                                   uint32_t max_pkt_size,
 597                                   struct i40e_rx_queue *rxq)
 598 {
 599         rxq_info->vsi_id = vsi_id;
 600         rxq_info->queue_id = queue_id;
 601         rxq_info->max_pkt_size = max_pkt_size;
 602         if (queue_id < nb_rxq) {
 603                 rxq_info->ring_len = rxq->nb_rx_desc;
 604                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 605                 rxq_info->databuffer_size =
 606                         (rte_pktmbuf_data_room_size(rxq->mp) -
 607                                 RTE_PKTMBUF_HEADROOM);
 608         }
 609 }
 610
 611 /* It configures VSI queues to co-work with Linux PF host */
 612 static int
 613 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 614 {
 615         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 616         struct i40e_rx_queue **rxq =
 617                 (struct i40e_rx_queue **)dev->data->rx_queues;
 618         struct i40e_tx_queue **txq =
 619                 (struct i40e_tx_queue **)dev->data->tx_queues;
 620         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci;
 621         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 622         struct vf_cmd_info args;
 623         uint16_t i, nb_qp = vf->num_queue_pairs;
 624         const uint32_t size =
 625                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 626         uint8_t buff[size];
 627         int ret;
 628
 629         memset(buff, 0, sizeof(buff));
 630         vc_vqci = (struct i40e_virtchnl_vsi_queue_config_info *)buff;
 631         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 632         vc_vqci->num_queue_pairs = nb_qp;
 633
 634         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 635                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 636                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 637                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 638                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 639                                         vf->max_pkt_len, rxq[i]);
 640         }
 641         memset(&args, 0, sizeof(args));
 642         args.ops = I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 643         args.in_args = (uint8_t *)vc_vqci;
 644         args.in_args_size = size;
 645         args.out_buffer = vf->aq_resp;
 646         args.out_size = I40E_AQ_BUF_SZ;
 647         ret = i40evf_execute_vf_cmd(dev, &args);
 648         if (ret)
 649                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 650                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 651
 652         return ret;
 653 }
 654
 655 /* It configures VSI queues to co-work with DPDK PF host */
 656 static int
 657 i40evf_configure_vsi_queues_ext(struct rte_eth_dev *dev)
 658 {
 659         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 660         struct i40e_rx_queue **rxq =
 661                 (struct i40e_rx_queue **)dev->data->rx_queues;
 662         struct i40e_tx_queue **txq =
 663                 (struct i40e_tx_queue **)dev->data->tx_queues;
 664         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei;
 665         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 666         struct vf_cmd_info args;
 667         uint16_t i, nb_qp = vf->num_queue_pairs;
 668         const uint32_t size =
 669                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei, nb_qp);
 670         uint8_t buff[size];
 671         int ret;
 672
 673         memset(buff, 0, sizeof(buff));
 674         vc_vqcei = (struct i40e_virtchnl_vsi_queue_config_ext_info *)buff;
 675         vc_vqcei->vsi_id = vf->vsi_res->vsi_id;
 676         vc_vqcei->num_queue_pairs = nb_qp;
 677         vc_qpei = vc_vqcei->qpair;
 678         for (i = 0; i < nb_qp; i++, vc_qpei++) {
 679                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpei->txq,
 680                         vc_vqcei->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 681                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpei->rxq,
 682                         vc_vqcei->vsi_id, i, dev->data->nb_rx_queues,
 683                                         vf->max_pkt_len, rxq[i]);
 684                 if (i < dev->data->nb_rx_queues)
 685                         /*
 686                          * It adds extra info for configuring VSI queues, which
 687                          * is needed to enable the configurable crc stripping
 688                          * in VF.
 689                          */
 690                         vc_qpei->rxq_ext.crcstrip =
 691                                 dev->data->dev_conf.rxmode.hw_strip_crc;
 692         }
 693         memset(&args, 0, sizeof(args));
 694         args.ops =
 695                 (enum i40e_virtchnl_ops)I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT;
 696         args.in_args = (uint8_t *)vc_vqcei;
 697         args.in_args_size = size;
 698         args.out_buffer = vf->aq_resp;
 699         args.out_size = I40E_AQ_BUF_SZ;
 700         ret = i40evf_execute_vf_cmd(dev, &args);
 701         if (ret)
 702                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 703                         "I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT");
 704
 705         return ret;
 706 }
 707
 708 static int
 709 i40evf_configure_queues(struct rte_eth_dev *dev)
 710 {
 711         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 712
 713         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 714                 /* To support DPDK PF host */
 715                 return i40evf_configure_vsi_queues_ext(dev);
 716         else
 717                 /* To support Linux PF host */
 718                 return i40evf_configure_vsi_queues(dev);
 719 }
 720
 721 static int
 722 i40evf_config_irq_map(struct rte_eth_dev *dev)
 723 {
 724         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 725         struct vf_cmd_info args;
 726         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_irq_map_info) + \
 727                 sizeof(struct i40e_virtchnl_vector_map)];
 728         struct i40e_virtchnl_irq_map_info *map_info;
 729         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
 730         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 731         uint32_t vector_id;
 732         int i, err;
 733
 734         if (rte_intr_allow_others(intr_handle)) {
 735                 if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
 736                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR;
 737                 else
 738                         vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 739         } else {
 740                 vector_id = I40E_MISC_VEC_ID;
 741         }
 742
 743         map_info = (struct i40e_virtchnl_irq_map_info *)cmd_buffer;
 744         map_info->num_vectors = 1;
 745         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 746         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 747         /* Alway use default dynamic MSIX interrupt */
 748         map_info->vecmap[0].vector_id = vector_id;
 749         /* Don't map any tx queue */
 750         map_info->vecmap[0].txq_map = 0;
 751         map_info->vecmap[0].rxq_map = 0;
 752         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 753                 map_info->vecmap[0].rxq_map |= 1 << i;
 754                 if (rte_intr_dp_is_en(intr_handle))
 755                         intr_handle->intr_vec[i] = vector_id;
 756         }
 757
 758         args.ops = I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP;
 759         args.in_args = (u8 *)cmd_buffer;
 760         args.in_args_size = sizeof(cmd_buffer);
 761         args.out_buffer = vf->aq_resp;
 762         args.out_size = I40E_AQ_BUF_SZ;
 763         err = i40evf_execute_vf_cmd(dev, &args);
 764         if (err)
 765                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 766
 767         return err;
 768 }
 769
 770 static int
 771 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 772                                 bool on)
 773 {
 774         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 775         struct i40e_virtchnl_queue_select queue_select;
 776         int err;
 777         struct vf_cmd_info args;
 778         memset(&queue_select, 0, sizeof(queue_select));
 779         queue_select.vsi_id = vf->vsi_res->vsi_id;
 780
 781         if (isrx)
 782                 queue_select.rx_queues |= 1 << qid;
 783         else
 784                 queue_select.tx_queues |= 1 << qid;
 785
 786         if (on)
 787                 args.ops = I40E_VIRTCHNL_OP_ENABLE_QUEUES;
 788         else
 789                 args.ops = I40E_VIRTCHNL_OP_DISABLE_QUEUES;
 790         args.in_args = (u8 *)&queue_select;
 791         args.in_args_size = sizeof(queue_select);
 792         args.out_buffer = vf->aq_resp;
 793         args.out_size = I40E_AQ_BUF_SZ;
 794         err = i40evf_execute_vf_cmd(dev, &args);
 795         if (err)
 796                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 797                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 798
 799         return err;
 800 }
 801
 802 static int
 803 i40evf_start_queues(struct rte_eth_dev *dev)
 804 {
 805         struct rte_eth_dev_data *dev_data = dev->data;
 806         int i;
 807         struct i40e_rx_queue *rxq;
 808         struct i40e_tx_queue *txq;
 809
 810         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 811                 rxq = dev_data->rx_queues[i];
 812                 if (rxq->rx_deferred_start)
 813                         continue;
 814                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 815                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 816                         return -1;
 817                 }
 818         }
 819
 820         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 821                 txq = dev_data->tx_queues[i];
 822                 if (txq->tx_deferred_start)
 823                         continue;
 824                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 825                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 826                         return -1;
 827                 }
 828         }
 829
 830         return 0;
 831 }
 832
 833 static int
 834 i40evf_stop_queues(struct rte_eth_dev *dev)
 835 {
 836         int i;
 837
 838         /* Stop TX queues first */
 839         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 840                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 841                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 842                         return -1;
 843                 }
 844         }
 845
 846         /* Then stop RX queues */
 847         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 848                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 849                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 850                         return -1;
 851                 }
 852         }
 853
 854         return 0;
 855 }
 856
 857 static void
 858 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 859                     struct ether_addr *addr,
 860                     __rte_unused uint32_t index,
 861                     __rte_unused uint32_t pool)
 862 {
 863         struct i40e_virtchnl_ether_addr_list *list;
 864         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 865         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 866                         sizeof(struct i40e_virtchnl_ether_addr)];
 867         int err;
 868         struct vf_cmd_info args;
 869
 870         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 871                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 872                             addr->addr_bytes[0], addr->addr_bytes[1],
 873                             addr->addr_bytes[2], addr->addr_bytes[3],
 874                             addr->addr_bytes[4], addr->addr_bytes[5]);
 875                 return;
 876         }
 877
 878         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 879         list->vsi_id = vf->vsi_res->vsi_id;
 880         list->num_elements = 1;
 881         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 882                                         sizeof(addr->addr_bytes));
 883
 884         args.ops = I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS;
 885         args.in_args = cmd_buffer;
 886         args.in_args_size = sizeof(cmd_buffer);
 887         args.out_buffer = vf->aq_resp;
 888         args.out_size = I40E_AQ_BUF_SZ;
 889         err = i40evf_execute_vf_cmd(dev, &args);
 890         if (err)
 891                 PMD_DRV_LOG(ERR, "fail to execute command "
 892                             "OP_ADD_ETHER_ADDRESS");
 893
 894         return;
 895 }
 896
 897 static void
 898 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 899                             struct ether_addr *addr)
 900 {
 901         struct i40e_virtchnl_ether_addr_list *list;
 902         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 903         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_ether_addr_list) + \
 904                         sizeof(struct i40e_virtchnl_ether_addr)];
 905         int err;
 906         struct vf_cmd_info args;
 907
 908         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 909                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 910                             addr->addr_bytes[0], addr->addr_bytes[1],
 911                             addr->addr_bytes[2], addr->addr_bytes[3],
 912                             addr->addr_bytes[4], addr->addr_bytes[5]);
 913                 return;
 914         }
 915
 916         list = (struct i40e_virtchnl_ether_addr_list *)cmd_buffer;
 917         list->vsi_id = vf->vsi_res->vsi_id;
 918         list->num_elements = 1;
 919         (void)rte_memcpy(list->list[0].addr, addr->addr_bytes,
 920                         sizeof(addr->addr_bytes));
 921
 922         args.ops = I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
 923         args.in_args = cmd_buffer;
 924         args.in_args_size = sizeof(cmd_buffer);
 925         args.out_buffer = vf->aq_resp;
 926         args.out_size = I40E_AQ_BUF_SZ;
 927         err = i40evf_execute_vf_cmd(dev, &args);
 928         if (err)
 929                 PMD_DRV_LOG(ERR, "fail to execute command "
 930                             "OP_DEL_ETHER_ADDRESS");
 931         return;
 932 }
 933
 934 static void
 935 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 936 {
 937         struct rte_eth_dev_data *data = dev->data;
 938         struct ether_addr *addr;
 939
 940         addr = &data->mac_addrs[index];
 941
 942         i40evf_del_mac_addr_by_addr(dev, addr);
 943 }
 944
 945 static int
 946 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 947 {
 948         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 949         struct i40e_virtchnl_queue_select q_stats;
 950         int err;
 951         struct vf_cmd_info args;
 952
 953         memset(&q_stats, 0, sizeof(q_stats));
 954         q_stats.vsi_id = vf->vsi_res->vsi_id;
 955         args.ops = I40E_VIRTCHNL_OP_GET_STATS;
 956         args.in_args = (u8 *)&q_stats;
 957         args.in_args_size = sizeof(q_stats);
 958         args.out_buffer = vf->aq_resp;
 959         args.out_size = I40E_AQ_BUF_SZ;
 960
 961         err = i40evf_execute_vf_cmd(dev, &args);
 962         if (err) {
 963                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 964                 *pstats = NULL;
 965                 return err;
 966         }
 967         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 968         return 0;
 969 }
 970
 971 static int
 972 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 973 {
 974         int ret;
 975         struct i40e_eth_stats *pstats = NULL;
 976
 977         ret = i40evf_update_stats(dev, &pstats);
 978         if (ret != 0)
 979                 return 0;
 980
 981         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 982                                                 pstats->rx_broadcast;
 983         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 984                                                 pstats->tx_unicast;
 985         stats->imissed = pstats->rx_discards;
 986         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 987         stats->ibytes = pstats->rx_bytes;
 988         stats->obytes = pstats->tx_bytes;
 989
 990         return 0;
 991 }
 992
 993 static void
 994 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 995 {
 996         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 997         struct i40e_eth_stats *pstats = NULL;
 998
 999         /* read stat values to clear hardware registers */
1000         i40evf_update_stats(dev, &pstats);
1001
1002         /* set stats offset base on current values */
1003         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
1004 }
1005
1006 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
1007                                       struct rte_eth_xstat_name *xstats_names,
1008                                       __rte_unused unsigned limit)
1009 {
1010         unsigned i;
1011
1012         if (xstats_names != NULL)
1013                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1014                         snprintf(xstats_names[i].name,
1015                                 sizeof(xstats_names[i].name),
1016                                 "%s", rte_i40evf_stats_strings[i].name);
1017                 }
1018         return I40EVF_NB_XSTATS;
1019 }
1020
1021 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
1022                                  struct rte_eth_xstat *xstats, unsigned n)
1023 {
1024         int ret;
1025         unsigned i;
1026         struct i40e_eth_stats *pstats = NULL;
1027
1028         if (n < I40EVF_NB_XSTATS)
1029                 return I40EVF_NB_XSTATS;
1030
1031         ret = i40evf_update_stats(dev, &pstats);
1032         if (ret != 0)
1033                 return 0;
1034
1035         if (!xstats)
1036                 return 0;
1037
1038         /* loop over xstats array and values from pstats */
1039         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
1040                 xstats[i].id = i;
1041                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
1042                         rte_i40evf_stats_strings[i].offset);
1043         }
1044
1045         return I40EVF_NB_XSTATS;
1046 }
1047
1048 static int
1049 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1050 {
1051         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1052         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1053         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1054                                                         sizeof(uint16_t)];
1055         int err;
1056         struct vf_cmd_info args;
1057
1058         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1059         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1060         vlan_list->num_elements = 1;
1061         vlan_list->vlan_id[0] = vlanid;
1062
1063         args.ops = I40E_VIRTCHNL_OP_ADD_VLAN;
1064         args.in_args = (u8 *)&cmd_buffer;
1065         args.in_args_size = sizeof(cmd_buffer);
1066         args.out_buffer = vf->aq_resp;
1067         args.out_size = I40E_AQ_BUF_SZ;
1068         err = i40evf_execute_vf_cmd(dev, &args);
1069         if (err)
1070                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1071
1072         return err;
1073 }
1074
1075 static int
1076 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1077 {
1078         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1079         struct i40e_virtchnl_vlan_filter_list *vlan_list;
1080         uint8_t cmd_buffer[sizeof(struct i40e_virtchnl_vlan_filter_list) +
1081                                                         sizeof(uint16_t)];
1082         int err;
1083         struct vf_cmd_info args;
1084
1085         vlan_list = (struct i40e_virtchnl_vlan_filter_list *)cmd_buffer;
1086         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1087         vlan_list->num_elements = 1;
1088         vlan_list->vlan_id[0] = vlanid;
1089
1090         args.ops = I40E_VIRTCHNL_OP_DEL_VLAN;
1091         args.in_args = (u8 *)&cmd_buffer;
1092         args.in_args_size = sizeof(cmd_buffer);
1093         args.out_buffer = vf->aq_resp;
1094         args.out_size = I40E_AQ_BUF_SZ;
1095         err = i40evf_execute_vf_cmd(dev, &args);
1096         if (err)
1097                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1098
1099         return err;
1100 }
1101
1102 static const struct rte_pci_id pci_id_i40evf_map[] = {
1103         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1104         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1105         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1106         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1107         { .vendor_id = 0, /* sentinel */ },
1108 };
1109
1110 static inline int
1111 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1112                                     struct rte_eth_link *link)
1113 {
1114         struct rte_eth_link *dst = &(dev->data->dev_link);
1115         struct rte_eth_link *src = link;
1116
1117         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1118                                         *(uint64_t *)src) == 0)
1119                 return -1;
1120
1121         return 0;
1122 }
1123
1124 /* Disable IRQ0 */
1125 static inline void
1126 i40evf_disable_irq0(struct i40e_hw *hw)
1127 {
1128         /* Disable all interrupt types */
1129         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1130         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1131                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1132         I40EVF_WRITE_FLUSH(hw);
1133 }
1134
1135 /* Enable IRQ0 */
1136 static inline void
1137 i40evf_enable_irq0(struct i40e_hw *hw)
1138 {
1139         /* Enable admin queue interrupt trigger */
1140         uint32_t val;
1141
1142         i40evf_disable_irq0(hw);
1143         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1144         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1145                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1146         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1147
1148         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1149                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1150                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1151                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1152
1153         I40EVF_WRITE_FLUSH(hw);
1154 }
1155
1156 static int
1157 i40evf_reset_vf(struct i40e_hw *hw)
1158 {
1159         int i, reset;
1160
1161         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1162                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1163                 return -1;
1164         }
1165         /**
1166           * After issuing vf reset command to pf, pf won't necessarily
1167           * reset vf, it depends on what state it exactly is. If it's not
1168           * initialized yet, it won't have vf reset since it's in a certain
1169           * state. If not, it will try to reset. Even vf is reset, pf will
1170           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1171           * it to ACTIVE. In this duration, vf may not catch the moment that
1172           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1173           */
1174         rte_delay_ms(200);
1175
1176         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1177                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1178                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1179                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1180                 if (I40E_VFR_COMPLETED == reset || I40E_VFR_VFACTIVE == reset)
1181                         break;
1182                 else
1183                         rte_delay_ms(50);
1184         }
1185
1186         if (i >= MAX_RESET_WAIT_CNT) {
1187                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1188                 return -1;
1189         }
1190
1191         return 0;
1192 }
1193
1194 static int
1195 i40evf_init_vf(struct rte_eth_dev *dev)
1196 {
1197         int i, err, bufsz;
1198         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1199         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1200         uint16_t interval =
1201                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1202
1203         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1204         vf->dev_data = dev->data;
1205         err = i40e_set_mac_type(hw);
1206         if (err) {
1207                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1208                 goto err;
1209         }
1210
1211         i40e_init_adminq_parameter(hw);
1212         err = i40e_init_adminq(hw);
1213         if (err) {
1214                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1215                 goto err;
1216         }
1217
1218         /* Reset VF and wait until it's complete */
1219         if (i40evf_reset_vf(hw)) {
1220                 PMD_INIT_LOG(ERR, "reset NIC failed");
1221                 goto err_aq;
1222         }
1223
1224         /* VF reset, shutdown admin queue and initialize again */
1225         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1226                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1227                 return -1;
1228         }
1229
1230         i40e_init_adminq_parameter(hw);
1231         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1232                 PMD_INIT_LOG(ERR, "init_adminq failed");
1233                 return -1;
1234         }
1235         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1236         if (!vf->aq_resp) {
1237                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1238                         goto err_aq;
1239         }
1240         if (i40evf_check_api_version(dev) != 0) {
1241                 PMD_INIT_LOG(ERR, "check_api version failed");
1242                 goto err_aq;
1243         }
1244         bufsz = sizeof(struct i40e_virtchnl_vf_resource) +
1245                 (I40E_MAX_VF_VSI * sizeof(struct i40e_virtchnl_vsi_resource));
1246         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1247         if (!vf->vf_res) {
1248                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1249                         goto err_aq;
1250         }
1251
1252         if (i40evf_get_vf_resource(dev) != 0) {
1253                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1254                 goto err_alloc;
1255         }
1256
1257         /* got VF config message back from PF, now we can parse it */
1258         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1259                 if (vf->vf_res->vsi_res[i].vsi_type == I40E_VSI_SRIOV)
1260                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1261         }
1262
1263         if (!vf->vsi_res) {
1264                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1265                 goto err_alloc;
1266         }
1267
1268         if (hw->mac.type == I40E_MAC_X722_VF)
1269                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1270         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1271         vf->vsi.type = vf->vsi_res->vsi_type;
1272         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1273         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1274
1275         /* Store the MAC address configured by host, or generate random one */
1276         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1277                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1278         else
1279                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1280
1281         /* If the PF host is not DPDK, set the interval of ITR0 to max*/
1282         if (vf->version_major != I40E_DPDK_VERSION_MAJOR) {
1283                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1284                                (I40E_ITR_INDEX_DEFAULT <<
1285                                 I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1286                                (interval <<
1287                                 I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1288                 I40EVF_WRITE_FLUSH(hw);
1289         }
1290
1291         return 0;
1292
1293 err_alloc:
1294         rte_free(vf->vf_res);
1295 err_aq:
1296         i40e_shutdown_adminq(hw); /* ignore error */
1297 err:
1298         return -1;
1299 }
1300
1301 static int
1302 i40evf_uninit_vf(struct rte_eth_dev *dev)
1303 {
1304         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1305         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1306
1307         PMD_INIT_FUNC_TRACE();
1308
1309         if (hw->adapter_stopped == 0)
1310                 i40evf_dev_close(dev);
1311         rte_free(vf->vf_res);
1312         vf->vf_res = NULL;
1313         rte_free(vf->aq_resp);
1314         vf->aq_resp = NULL;
1315
1316         return 0;
1317 }
1318
1319 static void
1320 i40evf_handle_pf_event(__rte_unused struct rte_eth_dev *dev,
1321                            uint8_t *msg,
1322                            __rte_unused uint16_t msglen)
1323 {
1324         struct i40e_virtchnl_pf_event *pf_msg =
1325                         (struct i40e_virtchnl_pf_event *)msg;
1326         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1327
1328         switch (pf_msg->event) {
1329         case I40E_VIRTCHNL_EVENT_RESET_IMPENDING:
1330                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1331                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET, NULL);
1332                 break;
1333         case I40E_VIRTCHNL_EVENT_LINK_CHANGE:
1334                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1335                 vf->link_up = pf_msg->event_data.link_event.link_status;
1336                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1337                 break;
1338         case I40E_VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1339                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1340                 break;
1341         default:
1342                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1343                 break;
1344         }
1345 }
1346
1347 static void
1348 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1349 {
1350         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1351         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1352         struct i40e_arq_event_info info;
1353         uint16_t pending, aq_opc;
1354         enum i40e_virtchnl_ops msg_opc;
1355         enum i40e_status_code msg_ret;
1356         int ret;
1357
1358         info.buf_len = I40E_AQ_BUF_SZ;
1359         if (!vf->aq_resp) {
1360                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1361                 return;
1362         }
1363         info.msg_buf = vf->aq_resp;
1364
1365         pending = 1;
1366         while (pending) {
1367                 ret = i40e_clean_arq_element(hw, &info, &pending);
1368
1369                 if (ret != I40E_SUCCESS) {
1370                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1371                                     "ret: %d", ret);
1372                         break;
1373                 }
1374                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1375                 /* For the message sent from pf to vf, opcode is stored in
1376                  * cookie_high of struct i40e_aq_desc, while return error code
1377                  * are stored in cookie_low, Which is done by
1378                  * i40e_aq_send_msg_to_vf in PF driver.*/
1379                 msg_opc = (enum i40e_virtchnl_ops)rte_le_to_cpu_32(
1380                                                   info.desc.cookie_high);
1381                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1382                                                   info.desc.cookie_low);
1383                 switch (aq_opc) {
1384                 case i40e_aqc_opc_send_msg_to_vf:
1385                         if (msg_opc == I40E_VIRTCHNL_OP_EVENT)
1386                                 /* process event*/
1387                                 i40evf_handle_pf_event(dev, info.msg_buf,
1388                                                        info.msg_len);
1389                         else {
1390                                 /* read message and it's expected one */
1391                                 if (msg_opc == vf->pend_cmd) {
1392                                         vf->cmd_retval = msg_ret;
1393                                         /* prevent compiler reordering */
1394                                         rte_compiler_barrier();
1395                                         _clear_cmd(vf);
1396                                 } else
1397                                         PMD_DRV_LOG(ERR, "command mismatch,"
1398                                                 "expect %u, get %u",
1399                                                 vf->pend_cmd, msg_opc);
1400                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1401                                              " opcode = %d", msg_opc);
1402                         }
1403                         break;
1404                 default:
1405                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1406                                     aq_opc);
1407                         break;
1408                 }
1409         }
1410 }
1411
1412 /**
1413  * Interrupt handler triggered by NIC  for handling
1414  * specific interrupt. Only adminq interrupt is processed in VF.
1415  *
1416  * @param handle
1417  *  Pointer to interrupt handle.
1418  * @param param
1419  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1420  *
1421  * @return
1422  *  void
1423  */
1424 static void
1425 i40evf_dev_interrupt_handler(void *param)
1426 {
1427         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1428         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1429         uint32_t icr0;
1430
1431         i40evf_disable_irq0(hw);
1432
1433         /* read out interrupt causes */
1434         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1435
1436         /* No interrupt event indicated */
1437         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1438                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1439                 goto done;
1440         }
1441
1442         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1443                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1444                 i40evf_handle_aq_msg(dev);
1445         }
1446
1447         /* Link Status Change interrupt */
1448         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1449                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1450                                    " do nothing");
1451
1452 done:
1453         i40evf_enable_irq0(hw);
1454         rte_intr_enable(dev->intr_handle);
1455 }
1456
1457 static int
1458 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1459 {
1460         struct i40e_hw *hw
1461                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1462         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(eth_dev);
1463
1464         PMD_INIT_FUNC_TRACE();
1465
1466         /* assign ops func pointer */
1467         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1468         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1469         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1470
1471         /*
1472          * For secondary processes, we don't initialise any further as primary
1473          * has already done this work.
1474          */
1475         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1476                 i40e_set_rx_function(eth_dev);
1477                 i40e_set_tx_function(eth_dev);
1478                 return 0;
1479         }
1480
1481         rte_eth_copy_pci_info(eth_dev, pci_dev);
1482         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1483
1484         hw->vendor_id = pci_dev->id.vendor_id;
1485         hw->device_id = pci_dev->id.device_id;
1486         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1487         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1488         hw->bus.device = pci_dev->addr.devid;
1489         hw->bus.func = pci_dev->addr.function;
1490         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1491         hw->adapter_stopped = 0;
1492
1493         if(i40evf_init_vf(eth_dev) != 0) {
1494                 PMD_INIT_LOG(ERR, "Init vf failed");
1495                 return -1;
1496         }
1497
1498         /* register callback func to eal lib */
1499         rte_intr_callback_register(&pci_dev->intr_handle,
1500                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1501
1502         /* enable uio intr after callback register */
1503         rte_intr_enable(&pci_dev->intr_handle);
1504
1505         /* configure and enable device interrupt */
1506         i40evf_enable_irq0(hw);
1507
1508         /* copy mac addr */
1509         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1510                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1511                                         0);
1512         if (eth_dev->data->mac_addrs == NULL) {
1513                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1514                                 " store MAC addresses",
1515                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1516                 return -ENOMEM;
1517         }
1518         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1519                         &eth_dev->data->mac_addrs[0]);
1520
1521         return 0;
1522 }
1523
1524 static int
1525 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1526 {
1527         PMD_INIT_FUNC_TRACE();
1528
1529         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1530                 return -EPERM;
1531
1532         eth_dev->dev_ops = NULL;
1533         eth_dev->rx_pkt_burst = NULL;
1534         eth_dev->tx_pkt_burst = NULL;
1535
1536         if (i40evf_uninit_vf(eth_dev) != 0) {
1537                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1538                 return -1;
1539         }
1540
1541         rte_free(eth_dev->data->mac_addrs);
1542         eth_dev->data->mac_addrs = NULL;
1543
1544         return 0;
1545 }
1546 /*
1547  * virtual function driver struct
1548  */
1549 static struct eth_driver rte_i40evf_pmd = {
1550         .pci_drv = {
1551                 .id_table = pci_id_i40evf_map,
1552                 .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1553                 .probe = rte_eth_dev_pci_probe,
1554                 .remove = rte_eth_dev_pci_remove,
1555         },
1556         .eth_dev_init = i40evf_dev_init,
1557         .eth_dev_uninit = i40evf_dev_uninit,
1558         .dev_private_size = sizeof(struct i40e_adapter),
1559 };
1560
1561 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd.pci_drv);
1562 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1563 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio");
1564
1565 static int
1566 i40evf_dev_configure(struct rte_eth_dev *dev)
1567 {
1568         struct i40e_adapter *ad =
1569                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1570         struct rte_eth_conf *conf = &dev->data->dev_conf;
1571         struct i40e_vf *vf;
1572
1573         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1574          * allocation or vector Rx preconditions we will reset it.
1575          */
1576         ad->rx_bulk_alloc_allowed = true;
1577         ad->rx_vec_allowed = true;
1578         ad->tx_simple_allowed = true;
1579         ad->tx_vec_allowed = true;
1580
1581         /* For non-DPDK PF drivers, VF has no ability to disable HW
1582          * CRC strip, and is implicitly enabled by the PF.
1583          */
1584         if (!conf->rxmode.hw_strip_crc) {
1585                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1586                 if ((vf->version_major == I40E_VIRTCHNL_VERSION_MAJOR) &&
1587                     (vf->version_minor <= I40E_VIRTCHNL_VERSION_MINOR)) {
1588                         /* Peer is running non-DPDK PF driver. */
1589                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1590                         return -EINVAL;
1591                 }
1592         }
1593
1594         return i40evf_init_vlan(dev);
1595 }
1596
1597 static int
1598 i40evf_init_vlan(struct rte_eth_dev *dev)
1599 {
1600         struct rte_eth_dev_data *data = dev->data;
1601         int ret;
1602
1603         /* Apply vlan offload setting */
1604         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1605
1606         /* Apply pvid setting */
1607         ret = i40evf_vlan_pvid_set(dev, data->dev_conf.txmode.pvid,
1608                                 data->dev_conf.txmode.hw_vlan_insert_pvid);
1609         return ret;
1610 }
1611
1612 static void
1613 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1614 {
1615         bool enable_vlan_strip = 0;
1616         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1617         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1618
1619         /* Linux pf host doesn't support vlan offload yet */
1620         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1621                 /* Vlan stripping setting */
1622                 if (mask & ETH_VLAN_STRIP_MASK) {
1623                         /* Enable or disable VLAN stripping */
1624                         if (dev_conf->rxmode.hw_vlan_strip)
1625                                 enable_vlan_strip = 1;
1626                         else
1627                                 enable_vlan_strip = 0;
1628
1629                         i40evf_config_vlan_offload(dev, enable_vlan_strip);
1630                 }
1631         }
1632 }
1633
1634 static int
1635 i40evf_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
1636 {
1637         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1638         struct i40e_vsi_vlan_pvid_info info;
1639         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1640
1641         memset(&info, 0, sizeof(info));
1642         info.on = on;
1643
1644         /* Linux pf host don't support vlan offload yet */
1645         if (vf->version_major == I40E_DPDK_VERSION_MAJOR) {
1646                 if (info.on)
1647                         info.config.pvid = pvid;
1648                 else {
1649                         info.config.reject.tagged =
1650                                 dev_conf->txmode.hw_vlan_reject_tagged;
1651                         info.config.reject.untagged =
1652                                 dev_conf->txmode.hw_vlan_reject_untagged;
1653                 }
1654                 return i40evf_config_vlan_pvid(dev, &info);
1655         }
1656
1657         return 0;
1658 }
1659
1660 static int
1661 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1662 {
1663         struct i40e_rx_queue *rxq;
1664         int err = 0;
1665         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1666
1667         PMD_INIT_FUNC_TRACE();
1668
1669         if (rx_queue_id < dev->data->nb_rx_queues) {
1670                 rxq = dev->data->rx_queues[rx_queue_id];
1671
1672                 err = i40e_alloc_rx_queue_mbufs(rxq);
1673                 if (err) {
1674                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1675                         return err;
1676                 }
1677
1678                 rte_wmb();
1679
1680                 /* Init the RX tail register. */
1681                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1682                 I40EVF_WRITE_FLUSH(hw);
1683
1684                 /* Ready to switch the queue on */
1685                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1686
1687                 if (err)
1688                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1689                                     rx_queue_id);
1690                 else
1691                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1692         }
1693
1694         return err;
1695 }
1696
1697 static int
1698 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1699 {
1700         struct i40e_rx_queue *rxq;
1701         int err;
1702
1703         if (rx_queue_id < dev->data->nb_rx_queues) {
1704                 rxq = dev->data->rx_queues[rx_queue_id];
1705
1706                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1707
1708                 if (err) {
1709                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1710                                     rx_queue_id);
1711                         return err;
1712                 }
1713
1714                 i40e_rx_queue_release_mbufs(rxq);
1715                 i40e_reset_rx_queue(rxq);
1716                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1717         }
1718
1719         return 0;
1720 }
1721
1722 static int
1723 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1724 {
1725         int err = 0;
1726
1727         PMD_INIT_FUNC_TRACE();
1728
1729         if (tx_queue_id < dev->data->nb_tx_queues) {
1730
1731                 /* Ready to switch the queue on */
1732                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1733
1734                 if (err)
1735                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1736                                     tx_queue_id);
1737                 else
1738                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1739         }
1740
1741         return err;
1742 }
1743
1744 static int
1745 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1746 {
1747         struct i40e_tx_queue *txq;
1748         int err;
1749
1750         if (tx_queue_id < dev->data->nb_tx_queues) {
1751                 txq = dev->data->tx_queues[tx_queue_id];
1752
1753                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1754
1755                 if (err) {
1756                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1757                                     tx_queue_id);
1758                         return err;
1759                 }
1760
1761                 i40e_tx_queue_release_mbufs(txq);
1762                 i40e_reset_tx_queue(txq);
1763                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1764         }
1765
1766         return 0;
1767 }
1768
1769 static int
1770 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1771 {
1772         int ret;
1773
1774         if (on)
1775                 ret = i40evf_add_vlan(dev, vlan_id);
1776         else
1777                 ret = i40evf_del_vlan(dev,vlan_id);
1778
1779         return ret;
1780 }
1781
1782 static int
1783 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1784 {
1785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786         struct rte_eth_dev_data *dev_data = dev->data;
1787         struct rte_pktmbuf_pool_private *mbp_priv;
1788         uint16_t buf_size, len;
1789
1790         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1791         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1792         I40EVF_WRITE_FLUSH(hw);
1793
1794         /* Calculate the maximum packet length allowed */
1795         mbp_priv = rte_mempool_get_priv(rxq->mp);
1796         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1797                                         RTE_PKTMBUF_HEADROOM);
1798         rxq->hs_mode = i40e_header_split_none;
1799         rxq->rx_hdr_len = 0;
1800         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1801         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1802         rxq->max_pkt_len = RTE_MIN(len,
1803                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1804
1805         /**
1806          * Check if the jumbo frame and maximum packet length are set correctly
1807          */
1808         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1809                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1810                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1811                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1812                                 "larger than %u and smaller than %u, as jumbo "
1813                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1814                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1815                         return I40E_ERR_CONFIG;
1816                 }
1817         } else {
1818                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1819                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1820                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1821                                 "larger than %u and smaller than %u, as jumbo "
1822                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1823                                                 (uint32_t)ETHER_MAX_LEN);
1824                         return I40E_ERR_CONFIG;
1825                 }
1826         }
1827
1828         if (dev_data->dev_conf.rxmode.enable_scatter ||
1829             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1830                 dev_data->scattered_rx = 1;
1831         }
1832
1833         return 0;
1834 }
1835
1836 static int
1837 i40evf_rx_init(struct rte_eth_dev *dev)
1838 {
1839         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1840         uint16_t i;
1841         int ret = I40E_SUCCESS;
1842         struct i40e_rx_queue **rxq =
1843                 (struct i40e_rx_queue **)dev->data->rx_queues;
1844
1845         i40evf_config_rss(vf);
1846         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1847                 if (!rxq[i] || !rxq[i]->q_set)
1848                         continue;
1849                 ret = i40evf_rxq_init(dev, rxq[i]);
1850                 if (ret != I40E_SUCCESS)
1851                         break;
1852         }
1853         if (ret == I40E_SUCCESS)
1854                 i40e_set_rx_function(dev);
1855
1856         return ret;
1857 }
1858
1859 static void
1860 i40evf_tx_init(struct rte_eth_dev *dev)
1861 {
1862         uint16_t i;
1863         struct i40e_tx_queue **txq =
1864                 (struct i40e_tx_queue **)dev->data->tx_queues;
1865         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1866
1867         for (i = 0; i < dev->data->nb_tx_queues; i++)
1868                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1869
1870         i40e_set_tx_function(dev);
1871 }
1872
1873 static inline void
1874 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1875 {
1876         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1877         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1878         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1879         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1880
1881         if (!rte_intr_allow_others(intr_handle)) {
1882                 I40E_WRITE_REG(hw,
1883                                I40E_VFINT_DYN_CTL01,
1884                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1885                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1886                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1887                 I40EVF_WRITE_FLUSH(hw);
1888                 return;
1889         }
1890
1891         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1892                 /* To support DPDK PF host */
1893                 I40E_WRITE_REG(hw,
1894                         I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR - 1),
1895                         I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1896                         I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
1897         /* If host driver is kernel driver, do nothing.
1898          * Interrupt 0 is used for rx packets, but don't set
1899          * I40E_VFINT_DYN_CTL01,
1900          * because it is already done in i40evf_enable_irq0.
1901          */
1902
1903         I40EVF_WRITE_FLUSH(hw);
1904 }
1905
1906 static inline void
1907 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1908 {
1909         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1910         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1911         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1912         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1913
1914         if (!rte_intr_allow_others(intr_handle)) {
1915                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1916                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1917                 I40EVF_WRITE_FLUSH(hw);
1918                 return;
1919         }
1920
1921         if (vf->version_major == I40E_DPDK_VERSION_MAJOR)
1922                 I40E_WRITE_REG(hw,
1923                                I40E_VFINT_DYN_CTLN1(I40EVF_VSI_DEFAULT_MSIX_INTR
1924                                                     - 1),
1925                                0);
1926         /* If host driver is kernel driver, do nothing.
1927          * Interrupt 0 is used for rx packets, but don't zero
1928          * I40E_VFINT_DYN_CTL01,
1929          * because interrupt 0 is also used for adminq processing.
1930          */
1931
1932         I40EVF_WRITE_FLUSH(hw);
1933 }
1934
1935 static int
1936 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1937 {
1938         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1939         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1940         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1941         uint16_t interval =
1942                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1943         uint16_t msix_intr;
1944
1945         msix_intr = intr_handle->intr_vec[queue_id];
1946         if (msix_intr == I40E_MISC_VEC_ID)
1947                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1948                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1949                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1950                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1951                                (interval <<
1952                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1953         else
1954                 I40E_WRITE_REG(hw,
1955                                I40E_VFINT_DYN_CTLN1(msix_intr -
1956                                                     I40E_RX_VEC_START),
1957                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1958                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1959                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1960                                (interval <<
1961                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1962
1963         I40EVF_WRITE_FLUSH(hw);
1964
1965         rte_intr_enable(&pci_dev->intr_handle);
1966
1967         return 0;
1968 }
1969
1970 static int
1971 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1972 {
1973         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
1974         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1975         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1976         uint16_t msix_intr;
1977
1978         msix_intr = intr_handle->intr_vec[queue_id];
1979         if (msix_intr == I40E_MISC_VEC_ID)
1980                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1981         else
1982                 I40E_WRITE_REG(hw,
1983                                I40E_VFINT_DYN_CTLN1(msix_intr -
1984                                                     I40E_RX_VEC_START),
1985                                0);
1986
1987         I40EVF_WRITE_FLUSH(hw);
1988
1989         return 0;
1990 }
1991
1992 static void
1993 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1994 {
1995         struct i40e_virtchnl_ether_addr_list *list;
1996         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1997         int err, i, j;
1998         int next_begin = 0;
1999         int begin = 0;
2000         uint32_t len;
2001         struct ether_addr *addr;
2002         struct vf_cmd_info args;
2003
2004         do {
2005                 j = 0;
2006                 len = sizeof(struct i40e_virtchnl_ether_addr_list);
2007                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
2008                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
2009                                 continue;
2010                         len += sizeof(struct i40e_virtchnl_ether_addr);
2011                         if (len >= I40E_AQ_BUF_SZ) {
2012                                 next_begin = i + 1;
2013                                 break;
2014                         }
2015                 }
2016
2017                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
2018
2019                 for (i = begin; i < next_begin; i++) {
2020                         addr = &dev->data->mac_addrs[i];
2021                         if (is_zero_ether_addr(addr))
2022                                 continue;
2023                         (void)rte_memcpy(list->list[j].addr, addr->addr_bytes,
2024                                          sizeof(addr->addr_bytes));
2025                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
2026                                     addr->addr_bytes[0], addr->addr_bytes[1],
2027                                     addr->addr_bytes[2], addr->addr_bytes[3],
2028                                     addr->addr_bytes[4], addr->addr_bytes[5]);
2029                         j++;
2030                 }
2031                 list->vsi_id = vf->vsi_res->vsi_id;
2032                 list->num_elements = j;
2033                 args.ops = add ? I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS :
2034                            I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS;
2035                 args.in_args = (uint8_t *)list;
2036                 args.in_args_size = len;
2037                 args.out_buffer = vf->aq_resp;
2038                 args.out_size = I40E_AQ_BUF_SZ;
2039                 err = i40evf_execute_vf_cmd(dev, &args);
2040                 if (err)
2041                         PMD_DRV_LOG(ERR, "fail to execute command %s",
2042                                     add ? "OP_ADD_ETHER_ADDRESS" :
2043                                     "OP_DEL_ETHER_ADDRESS");
2044                 rte_free(list);
2045                 begin = next_begin;
2046         } while (begin < I40E_NUM_MACADDR_MAX);
2047 }
2048
2049 static int
2050 i40evf_dev_start(struct rte_eth_dev *dev)
2051 {
2052         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2053         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2054         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2055         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2056         uint32_t intr_vector = 0;
2057
2058         PMD_INIT_FUNC_TRACE();
2059
2060         hw->adapter_stopped = 0;
2061
2062         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
2063         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
2064                                         dev->data->nb_tx_queues);
2065
2066         /* check and configure queue intr-vector mapping */
2067         if (dev->data->dev_conf.intr_conf.rxq != 0) {
2068                 intr_vector = dev->data->nb_rx_queues;
2069                 if (rte_intr_efd_enable(intr_handle, intr_vector))
2070                         return -1;
2071         }
2072
2073         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
2074                 intr_handle->intr_vec =
2075                         rte_zmalloc("intr_vec",
2076                                     dev->data->nb_rx_queues * sizeof(int), 0);
2077                 if (!intr_handle->intr_vec) {
2078                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
2079                                      " intr_vec", dev->data->nb_rx_queues);
2080                         return -ENOMEM;
2081                 }
2082         }
2083
2084         if (i40evf_rx_init(dev) != 0){
2085                 PMD_DRV_LOG(ERR, "failed to do RX init");
2086                 return -1;
2087         }
2088
2089         i40evf_tx_init(dev);
2090
2091         if (i40evf_configure_queues(dev) != 0) {
2092                 PMD_DRV_LOG(ERR, "configure queues failed");
2093                 goto err_queue;
2094         }
2095         if (i40evf_config_irq_map(dev)) {
2096                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2097                 goto err_queue;
2098         }
2099
2100         /* Set all mac addrs */
2101         i40evf_add_del_all_mac_addr(dev, TRUE);
2102
2103         if (i40evf_start_queues(dev) != 0) {
2104                 PMD_DRV_LOG(ERR, "enable queues failed");
2105                 goto err_mac;
2106         }
2107
2108         i40evf_enable_queues_intr(dev);
2109         return 0;
2110
2111 err_mac:
2112         i40evf_add_del_all_mac_addr(dev, FALSE);
2113 err_queue:
2114         return -1;
2115 }
2116
2117 static void
2118 i40evf_dev_stop(struct rte_eth_dev *dev)
2119 {
2120         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2121         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2122
2123         PMD_INIT_FUNC_TRACE();
2124
2125         i40evf_stop_queues(dev);
2126         i40evf_disable_queues_intr(dev);
2127         i40e_dev_clear_queues(dev);
2128
2129         /* Clean datapath event and queue/vec mapping */
2130         rte_intr_efd_disable(intr_handle);
2131         if (intr_handle->intr_vec) {
2132                 rte_free(intr_handle->intr_vec);
2133                 intr_handle->intr_vec = NULL;
2134         }
2135         /* remove all mac addrs */
2136         i40evf_add_del_all_mac_addr(dev, FALSE);
2137
2138 }
2139
2140 static int
2141 i40evf_dev_link_update(struct rte_eth_dev *dev,
2142                        __rte_unused int wait_to_complete)
2143 {
2144         struct rte_eth_link new_link;
2145         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2146         /*
2147          * DPDK pf host provide interfacet to acquire link status
2148          * while Linux driver does not
2149          */
2150
2151         /* Linux driver PF host */
2152         switch (vf->link_speed) {
2153         case I40E_LINK_SPEED_100MB:
2154                 new_link.link_speed = ETH_SPEED_NUM_100M;
2155                 break;
2156         case I40E_LINK_SPEED_1GB:
2157                 new_link.link_speed = ETH_SPEED_NUM_1G;
2158                 break;
2159         case I40E_LINK_SPEED_10GB:
2160                 new_link.link_speed = ETH_SPEED_NUM_10G;
2161                 break;
2162         case I40E_LINK_SPEED_20GB:
2163                 new_link.link_speed = ETH_SPEED_NUM_20G;
2164                 break;
2165         case I40E_LINK_SPEED_40GB:
2166                 new_link.link_speed = ETH_SPEED_NUM_40G;
2167                 break;
2168         default:
2169                 new_link.link_speed = ETH_SPEED_NUM_100M;
2170                 break;
2171         }
2172         /* full duplex only */
2173         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2174         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2175                                              ETH_LINK_DOWN;
2176
2177         i40evf_dev_atomic_write_link_status(dev, &new_link);
2178
2179         return 0;
2180 }
2181
2182 static void
2183 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2184 {
2185         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2186         int ret;
2187
2188         /* If enabled, just return */
2189         if (vf->promisc_unicast_enabled)
2190                 return;
2191
2192         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2193         if (ret == 0)
2194                 vf->promisc_unicast_enabled = TRUE;
2195 }
2196
2197 static void
2198 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2199 {
2200         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2201         int ret;
2202
2203         /* If disabled, just return */
2204         if (!vf->promisc_unicast_enabled)
2205                 return;
2206
2207         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2208         if (ret == 0)
2209                 vf->promisc_unicast_enabled = FALSE;
2210 }
2211
2212 static void
2213 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2214 {
2215         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2216         int ret;
2217
2218         /* If enabled, just return */
2219         if (vf->promisc_multicast_enabled)
2220                 return;
2221
2222         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2223         if (ret == 0)
2224                 vf->promisc_multicast_enabled = TRUE;
2225 }
2226
2227 static void
2228 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2229 {
2230         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2231         int ret;
2232
2233         /* If enabled, just return */
2234         if (!vf->promisc_multicast_enabled)
2235                 return;
2236
2237         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2238         if (ret == 0)
2239                 vf->promisc_multicast_enabled = FALSE;
2240 }
2241
2242 static void
2243 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2244 {
2245         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2246
2247         memset(dev_info, 0, sizeof(*dev_info));
2248         dev_info->pci_dev = RTE_DEV_TO_PCI(dev->device);
2249         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2250         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2251         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2252         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2253         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2254         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2255         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2256         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2257         dev_info->rx_offload_capa =
2258                 DEV_RX_OFFLOAD_VLAN_STRIP |
2259                 DEV_RX_OFFLOAD_QINQ_STRIP |
2260                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2261                 DEV_RX_OFFLOAD_UDP_CKSUM |
2262                 DEV_RX_OFFLOAD_TCP_CKSUM;
2263         dev_info->tx_offload_capa =
2264                 DEV_TX_OFFLOAD_VLAN_INSERT |
2265                 DEV_TX_OFFLOAD_QINQ_INSERT |
2266                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2267                 DEV_TX_OFFLOAD_UDP_CKSUM |
2268                 DEV_TX_OFFLOAD_TCP_CKSUM |
2269                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2270
2271         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2272                 .rx_thresh = {
2273                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2274                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2275                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2276                 },
2277                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2278                 .rx_drop_en = 0,
2279         };
2280
2281         dev_info->default_txconf = (struct rte_eth_txconf) {
2282                 .tx_thresh = {
2283                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2284                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2285                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2286                 },
2287                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2288                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2289                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2290                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2291         };
2292
2293         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2294                 .nb_max = I40E_MAX_RING_DESC,
2295                 .nb_min = I40E_MIN_RING_DESC,
2296                 .nb_align = I40E_ALIGN_RING_DESC,
2297         };
2298
2299         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2300                 .nb_max = I40E_MAX_RING_DESC,
2301                 .nb_min = I40E_MIN_RING_DESC,
2302                 .nb_align = I40E_ALIGN_RING_DESC,
2303         };
2304 }
2305
2306 static void
2307 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2308 {
2309         if (i40evf_get_statistics(dev, stats))
2310                 PMD_DRV_LOG(ERR, "Get statistics failed");
2311 }
2312
2313 static void
2314 i40evf_dev_close(struct rte_eth_dev *dev)
2315 {
2316         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2317         struct rte_pci_device *pci_dev = I40E_DEV_TO_PCI(dev);
2318         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2319
2320         i40evf_dev_stop(dev);
2321         hw->adapter_stopped = 1;
2322         i40e_dev_free_queues(dev);
2323         i40evf_reset_vf(hw);
2324         i40e_shutdown_adminq(hw);
2325         /* disable uio intr before callback unregister */
2326         rte_intr_disable(intr_handle);
2327
2328         /* unregister callback func from eal lib */
2329         rte_intr_callback_unregister(intr_handle,
2330                                      i40evf_dev_interrupt_handler, dev);
2331         i40evf_disable_irq0(hw);
2332 }
2333
2334 static int
2335 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2336 {
2337         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2338         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2339         int ret;
2340
2341         if (!lut)
2342                 return -EINVAL;
2343
2344         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2345                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2346                                           lut, lut_size);
2347                 if (ret) {
2348                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2349                         return ret;
2350                 }
2351         } else {
2352                 uint32_t *lut_dw = (uint32_t *)lut;
2353                 uint16_t i, lut_size_dw = lut_size / 4;
2354
2355                 for (i = 0; i < lut_size_dw; i++)
2356                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2357         }
2358
2359         return 0;
2360 }
2361
2362 static int
2363 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2364 {
2365         struct i40e_vf *vf;
2366         struct i40e_hw *hw;
2367         int ret;
2368
2369         if (!vsi || !lut)
2370                 return -EINVAL;
2371
2372         vf = I40E_VSI_TO_VF(vsi);
2373         hw = I40E_VSI_TO_HW(vsi);
2374
2375         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2376                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2377                                           lut, lut_size);
2378                 if (ret) {
2379                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2380                         return ret;
2381                 }
2382         } else {
2383                 uint32_t *lut_dw = (uint32_t *)lut;
2384                 uint16_t i, lut_size_dw = lut_size / 4;
2385
2386                 for (i = 0; i < lut_size_dw; i++)
2387                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2388                 I40EVF_WRITE_FLUSH(hw);
2389         }
2390
2391         return 0;
2392 }
2393
2394 static int
2395 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2396                            struct rte_eth_rss_reta_entry64 *reta_conf,
2397                            uint16_t reta_size)
2398 {
2399         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2400         uint8_t *lut;
2401         uint16_t i, idx, shift;
2402         int ret;
2403
2404         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2405                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2406                         "(%d) doesn't match the number of hardware can "
2407                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2408                 return -EINVAL;
2409         }
2410
2411         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2412         if (!lut) {
2413                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2414                 return -ENOMEM;
2415         }
2416         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2417         if (ret)
2418                 goto out;
2419         for (i = 0; i < reta_size; i++) {
2420                 idx = i / RTE_RETA_GROUP_SIZE;
2421                 shift = i % RTE_RETA_GROUP_SIZE;
2422                 if (reta_conf[idx].mask & (1ULL << shift))
2423                         lut[i] = reta_conf[idx].reta[shift];
2424         }
2425         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2426
2427 out:
2428         rte_free(lut);
2429
2430         return ret;
2431 }
2432
2433 static int
2434 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2435                           struct rte_eth_rss_reta_entry64 *reta_conf,
2436                           uint16_t reta_size)
2437 {
2438         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2439         uint16_t i, idx, shift;
2440         uint8_t *lut;
2441         int ret;
2442
2443         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2444                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2445                         "(%d) doesn't match the number of hardware can "
2446                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2447                 return -EINVAL;
2448         }
2449
2450         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2451         if (!lut) {
2452                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2453                 return -ENOMEM;
2454         }
2455
2456         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2457         if (ret)
2458                 goto out;
2459         for (i = 0; i < reta_size; i++) {
2460                 idx = i / RTE_RETA_GROUP_SIZE;
2461                 shift = i % RTE_RETA_GROUP_SIZE;
2462                 if (reta_conf[idx].mask & (1ULL << shift))
2463                         reta_conf[idx].reta[shift] = lut[i];
2464         }
2465
2466 out:
2467         rte_free(lut);
2468
2469         return ret;
2470 }
2471
2472 static int
2473 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2474 {
2475         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2476         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2477         int ret = 0;
2478
2479         if (!key || key_len == 0) {
2480                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2481                 return 0;
2482         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2483                 sizeof(uint32_t)) {
2484                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2485                 return -EINVAL;
2486         }
2487
2488         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2489                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2490                         (struct i40e_aqc_get_set_rss_key_data *)key;
2491
2492                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2493                 if (ret)
2494                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2495                                      "via AQ");
2496         } else {
2497                 uint32_t *hash_key = (uint32_t *)key;
2498                 uint16_t i;
2499
2500                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2501                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2502                 I40EVF_WRITE_FLUSH(hw);
2503         }
2504
2505         return ret;
2506 }
2507
2508 static int
2509 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2510 {
2511         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2512         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2513         int ret;
2514
2515         if (!key || !key_len)
2516                 return -EINVAL;
2517
2518         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2519                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2520                         (struct i40e_aqc_get_set_rss_key_data *)key);
2521                 if (ret) {
2522                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2523                         return ret;
2524                 }
2525         } else {
2526                 uint32_t *key_dw = (uint32_t *)key;
2527                 uint16_t i;
2528
2529                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2530                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2531         }
2532         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2533
2534         return 0;
2535 }
2536
2537 static int
2538 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2539 {
2540         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2541         uint64_t rss_hf, hena;
2542         int ret;
2543
2544         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2545                                  rss_conf->rss_key_len);
2546         if (ret)
2547                 return ret;
2548
2549         rss_hf = rss_conf->rss_hf;
2550         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2551         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2552         if (hw->mac.type == I40E_MAC_X722)
2553                 hena &= ~I40E_RSS_HENA_ALL_X722;
2554         else
2555                 hena &= ~I40E_RSS_HENA_ALL;
2556         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2557         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2558         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2559         I40EVF_WRITE_FLUSH(hw);
2560
2561         return 0;
2562 }
2563
2564 static void
2565 i40evf_disable_rss(struct i40e_vf *vf)
2566 {
2567         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2568         uint64_t hena;
2569
2570         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2571         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2572         if (hw->mac.type == I40E_MAC_X722)
2573                 hena &= ~I40E_RSS_HENA_ALL_X722;
2574         else
2575                 hena &= ~I40E_RSS_HENA_ALL;
2576         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2577         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2578         I40EVF_WRITE_FLUSH(hw);
2579 }
2580
2581 static int
2582 i40evf_config_rss(struct i40e_vf *vf)
2583 {
2584         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2585         struct rte_eth_rss_conf rss_conf;
2586         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2587         uint16_t num;
2588
2589         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2590                 i40evf_disable_rss(vf);
2591                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2592                 return 0;
2593         }
2594
2595         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2596         /* Fill out the look up table */
2597         for (i = 0, j = 0; i < nb_q; i++, j++) {
2598                 if (j >= num)
2599                         j = 0;
2600                 lut = (lut << 8) | j;
2601                 if ((i & 3) == 3)
2602                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2603         }
2604
2605         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2606         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2607                 i40evf_disable_rss(vf);
2608                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2609                 return 0;
2610         }
2611
2612         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2613                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2614                 /* Calculate the default hash key */
2615                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2616                         rss_key_default[i] = (uint32_t)rte_rand();
2617                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2618                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2619                         sizeof(uint32_t);
2620         }
2621
2622         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2623 }
2624
2625 static int
2626 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2627                            struct rte_eth_rss_conf *rss_conf)
2628 {
2629         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2630         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2631         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2632         uint64_t hena;
2633
2634         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2635         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2636         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2637                  ? I40E_RSS_HENA_ALL_X722
2638                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2639                 if (rss_hf != 0) /* Enable RSS */
2640                         return -EINVAL;
2641                 return 0;
2642         }
2643
2644         /* RSS enabled */
2645         if (rss_hf == 0) /* Disable RSS */
2646                 return -EINVAL;
2647
2648         return i40evf_hw_rss_hash_set(vf, rss_conf);
2649 }
2650
2651 static int
2652 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2653                              struct rte_eth_rss_conf *rss_conf)
2654 {
2655         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2656         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2657         uint64_t hena;
2658
2659         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2660                            &rss_conf->rss_key_len);
2661
2662         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2663         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2664         rss_conf->rss_hf = i40e_parse_hena(hena);
2665
2666         return 0;
2667 }
2668
2669 static int
2670 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2671 {
2672         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2673         struct rte_eth_dev_data *dev_data = vf->dev_data;
2674         uint32_t frame_size = mtu + ETHER_HDR_LEN
2675                               + ETHER_CRC_LEN + I40E_VLAN_TAG_SIZE;
2676         int ret = 0;
2677
2678         /* check if mtu is within the allowed range */
2679         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2680                 return -EINVAL;
2681
2682         /* mtu setting is forbidden if port is start */
2683         if (dev_data->dev_started) {
2684                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2685                             dev_data->port_id);
2686                 return -EBUSY;
2687         }
2688
2689         if (frame_size > ETHER_MAX_LEN)
2690                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2691         else
2692                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2693
2694         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2695
2696         return ret;
2697 }
2698
2699 static void
2700 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2701                             struct ether_addr *mac_addr)
2702 {
2703         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2704
2705         if (!is_valid_assigned_ether_addr(mac_addr)) {
2706                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2707                 return;
2708         }
2709
2710         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2711                 return;
2712
2713         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2714                 return;
2715
2716         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2717
2718         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2719 }