drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   int wait_to_complete);
 111 static void i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static void i40evf_dev_close(struct rte_eth_dev *dev);
 123 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 130                                      uint16_t rx_queue_id);
 131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 132                                     uint16_t rx_queue_id);
 133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 134                                      uint16_t tx_queue_id);
 135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 136                                     uint16_t tx_queue_id);
 137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 138                                struct ether_addr *addr,
 139                                uint32_t index,
 140                                uint32_t pool);
 141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 143                         struct rte_eth_rss_reta_entry64 *reta_conf,
 144                         uint16_t reta_size);
 145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                         struct rte_eth_rss_reta_entry64 *reta_conf,
 147                         uint16_t reta_size);
 148 static int i40evf_config_rss(struct i40e_vf *vf);
 149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 150                                       struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 152                                         struct rte_eth_rss_conf *rss_conf);
 153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 155                                         struct ether_addr *mac_addr);
 156 static int
 157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static int
 159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 161                                    uint8_t *msg,
 162                                    uint16_t msglen);
 163
 164 /* Default hash key buffer for RSS */
 165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 166
 167 struct rte_i40evf_xstats_name_off {
 168         char name[RTE_ETH_XSTATS_NAME_SIZE];
 169         unsigned offset;
 170 };
 171
 172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 173         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 174         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 175         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 176         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 177         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 178         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 179                 rx_unknown_protocol)},
 180         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 182         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 183         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 184         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 185         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 186 };
 187
 188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 189                 sizeof(rte_i40evf_stats_strings[0]))
 190
 191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 192         .dev_configure        = i40evf_dev_configure,
 193         .dev_start            = i40evf_dev_start,
 194         .dev_stop             = i40evf_dev_stop,
 195         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 196         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 197         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 198         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 199         .link_update          = i40evf_dev_link_update,
 200         .stats_get            = i40evf_dev_stats_get,
 201         .xstats_get           = i40evf_dev_xstats_get,
 202         .xstats_get_names     = i40evf_dev_xstats_get_names,
 203         .xstats_reset         = i40evf_dev_xstats_reset,
 204         .dev_close            = i40evf_dev_close,
 205         .dev_reset            = i40evf_dev_reset,
 206         .dev_infos_get        = i40evf_dev_info_get,
 207         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 208         .vlan_filter_set      = i40evf_vlan_filter_set,
 209         .vlan_offload_set     = i40evf_vlan_offload_set,
 210         .rx_queue_start       = i40evf_dev_rx_queue_start,
 211         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 212         .tx_queue_start       = i40evf_dev_tx_queue_start,
 213         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 214         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 215         .rx_queue_release     = i40e_dev_rx_queue_release,
 216         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 217         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 218         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 219         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 220         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 221         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 222         .tx_queue_release     = i40e_dev_tx_queue_release,
 223         .rx_queue_count       = i40e_dev_rx_queue_count,
 224         .rxq_info_get         = i40e_rxq_info_get,
 225         .txq_info_get         = i40e_txq_info_get,
 226         .mac_addr_add         = i40evf_add_mac_addr,
 227         .mac_addr_remove      = i40evf_del_mac_addr,
 228         .reta_update          = i40evf_dev_rss_reta_update,
 229         .reta_query           = i40evf_dev_rss_reta_query,
 230         .rss_hash_update      = i40evf_dev_rss_hash_update,
 231         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 232         .mtu_set              = i40evf_dev_mtu_set,
 233         .mac_addr_set         = i40evf_set_default_mac_addr,
 234 };
 235
 236 /*
 237  * Read data in admin queue to get msg from pf driver
 238  */
 239 static enum i40evf_aq_result
 240 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 241 {
 242         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 243         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 244         struct i40e_arq_event_info event;
 245         enum virtchnl_ops opcode;
 246         enum i40e_status_code retval;
 247         int ret;
 248         enum i40evf_aq_result result = I40EVF_MSG_NON;
 249
 250         event.buf_len = data->buf_len;
 251         event.msg_buf = data->msg;
 252         ret = i40e_clean_arq_element(hw, &event, NULL);
 253         /* Can't read any msg from adminQ */
 254         if (ret) {
 255                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 256                         result = I40EVF_MSG_ERR;
 257                 return result;
 258         }
 259
 260         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 261         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 262         /* pf sys event */
 263         if (opcode == VIRTCHNL_OP_EVENT) {
 264                 struct virtchnl_pf_event *vpe =
 265                         (struct virtchnl_pf_event *)event.msg_buf;
 266
 267                 result = I40EVF_MSG_SYS;
 268                 switch (vpe->event) {
 269                 case VIRTCHNL_EVENT_LINK_CHANGE:
 270                         vf->link_up =
 271                                 vpe->event_data.link_event.link_status;
 272                         vf->link_speed =
 273                                 vpe->event_data.link_event.link_speed;
 274                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 275                         PMD_DRV_LOG(INFO, "Link status update:%s",
 276                                     vf->link_up ? "up" : "down");
 277                         break;
 278                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 279                         vf->vf_reset = true;
 280                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 281                         PMD_DRV_LOG(INFO, "vf is reseting");
 282                         break;
 283                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 284                         vf->dev_closed = true;
 285                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 286                         PMD_DRV_LOG(INFO, "PF driver closed");
 287                         break;
 288                 default:
 289                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 290                                     __func__, vpe->event);
 291                 }
 292         } else {
 293                 /* async reply msg on command issued by vf previously */
 294                 result = I40EVF_MSG_CMD;
 295                 /* Actual data length read from PF */
 296                 data->msg_len = event.msg_len;
 297         }
 298
 299         data->result = retval;
 300         data->ops = opcode;
 301
 302         return result;
 303 }
 304
 305 /**
 306  * clear current command. Only call in case execute
 307  * _atomic_set_cmd successfully.
 308  */
 309 static inline void
 310 _clear_cmd(struct i40e_vf *vf)
 311 {
 312         rte_wmb();
 313         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 314 }
 315
 316 /*
 317  * Check there is pending cmd in execution. If none, set new command.
 318  */
 319 static inline int
 320 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 321 {
 322         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 323                         VIRTCHNL_OP_UNKNOWN, ops);
 324
 325         if (!ret)
 326                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 327
 328         return !ret;
 329 }
 330
 331 #define MAX_TRY_TIMES 200
 332 #define ASQ_DELAY_MS  10
 333
 334 static int
 335 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 336 {
 337         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 338         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 339         struct i40evf_arq_msg_info info;
 340         enum i40evf_aq_result ret;
 341         int err, i = 0;
 342
 343         if (_atomic_set_cmd(vf, args->ops))
 344                 return -1;
 345
 346         info.msg = args->out_buffer;
 347         info.buf_len = args->out_size;
 348         info.ops = VIRTCHNL_OP_UNKNOWN;
 349         info.result = I40E_SUCCESS;
 350
 351         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 352                      args->in_args, args->in_args_size, NULL);
 353         if (err) {
 354                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 355                 _clear_cmd(vf);
 356                 return err;
 357         }
 358
 359         switch (args->ops) {
 360         case VIRTCHNL_OP_RESET_VF:
 361                 /*no need to process in this function */
 362                 err = 0;
 363                 break;
 364         case VIRTCHNL_OP_VERSION:
 365         case VIRTCHNL_OP_GET_VF_RESOURCES:
 366                 /* for init adminq commands, need to poll the response */
 367                 err = -1;
 368                 do {
 369                         ret = i40evf_read_pfmsg(dev, &info);
 370                         vf->cmd_retval = info.result;
 371                         if (ret == I40EVF_MSG_CMD) {
 372                                 err = 0;
 373                                 break;
 374                         } else if (ret == I40EVF_MSG_ERR)
 375                                 break;
 376                         rte_delay_ms(ASQ_DELAY_MS);
 377                         /* If don't read msg or read sys event, continue */
 378                 } while (i++ < MAX_TRY_TIMES);
 379                 _clear_cmd(vf);
 380                 break;
 381
 382         default:
 383                 /* for other adminq in running time, waiting the cmd done flag */
 384                 err = -1;
 385                 do {
 386                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 387                                 err = 0;
 388                                 break;
 389                         }
 390                         rte_delay_ms(ASQ_DELAY_MS);
 391                         /* If don't read msg or read sys event, continue */
 392                 } while (i++ < MAX_TRY_TIMES);
 393                 /* If there's no response is received, clear command */
 394                 if (i >= MAX_TRY_TIMES) {
 395                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 396                         _clear_cmd(vf);
 397                 }
 398                 break;
 399         }
 400
 401         return err | vf->cmd_retval;
 402 }
 403
 404 /*
 405  * Check API version with sync wait until version read or fail from admin queue
 406  */
 407 static int
 408 i40evf_check_api_version(struct rte_eth_dev *dev)
 409 {
 410         struct virtchnl_version_info version, *pver;
 411         int err;
 412         struct vf_cmd_info args;
 413         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 414
 415         version.major = VIRTCHNL_VERSION_MAJOR;
 416         version.minor = VIRTCHNL_VERSION_MINOR;
 417
 418         args.ops = VIRTCHNL_OP_VERSION;
 419         args.in_args = (uint8_t *)&version;
 420         args.in_args_size = sizeof(version);
 421         args.out_buffer = vf->aq_resp;
 422         args.out_size = I40E_AQ_BUF_SZ;
 423
 424         err = i40evf_execute_vf_cmd(dev, &args);
 425         if (err) {
 426                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 427                 return err;
 428         }
 429
 430         pver = (struct virtchnl_version_info *)args.out_buffer;
 431         vf->version_major = pver->major;
 432         vf->version_minor = pver->minor;
 433         if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 434                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 435                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 436         else {
 437                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 438                                         vf->version_major, vf->version_minor,
 439                                                 VIRTCHNL_VERSION_MAJOR,
 440                                                 VIRTCHNL_VERSION_MINOR);
 441                 return -1;
 442         }
 443
 444         return 0;
 445 }
 446
 447 static int
 448 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 449 {
 450         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 451         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 452         int err;
 453         struct vf_cmd_info args;
 454         uint32_t caps, len;
 455
 456         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 457         args.out_buffer = vf->aq_resp;
 458         args.out_size = I40E_AQ_BUF_SZ;
 459         if (PF_IS_V11(vf)) {
 460                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 461                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 462                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 463                        VIRTCHNL_VF_OFFLOAD_VLAN |
 464                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 465                 args.in_args = (uint8_t *)&caps;
 466                 args.in_args_size = sizeof(caps);
 467         } else {
 468                 args.in_args = NULL;
 469                 args.in_args_size = 0;
 470         }
 471         err = i40evf_execute_vf_cmd(dev, &args);
 472
 473         if (err) {
 474                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 475                 return err;
 476         }
 477
 478         len =  sizeof(struct virtchnl_vf_resource) +
 479                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 480
 481         rte_memcpy(vf->vf_res, args.out_buffer,
 482                         RTE_MIN(args.out_size, len));
 483         i40e_vf_parse_hw_config(hw, vf->vf_res);
 484
 485         return 0;
 486 }
 487
 488 static int
 489 i40evf_config_promisc(struct rte_eth_dev *dev,
 490                       bool enable_unicast,
 491                       bool enable_multicast)
 492 {
 493         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 494         int err;
 495         struct vf_cmd_info args;
 496         struct virtchnl_promisc_info promisc;
 497
 498         promisc.flags = 0;
 499         promisc.vsi_id = vf->vsi_res->vsi_id;
 500
 501         if (enable_unicast)
 502                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 503
 504         if (enable_multicast)
 505                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 506
 507         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 508         args.in_args = (uint8_t *)&promisc;
 509         args.in_args_size = sizeof(promisc);
 510         args.out_buffer = vf->aq_resp;
 511         args.out_size = I40E_AQ_BUF_SZ;
 512
 513         err = i40evf_execute_vf_cmd(dev, &args);
 514
 515         if (err)
 516                 PMD_DRV_LOG(ERR, "fail to execute command "
 517                             "CONFIG_PROMISCUOUS_MODE");
 518         return err;
 519 }
 520
 521 static int
 522 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 523 {
 524         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 525         struct vf_cmd_info args;
 526         int ret;
 527
 528         memset(&args, 0, sizeof(args));
 529         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 530         args.in_args = NULL;
 531         args.in_args_size = 0;
 532         args.out_buffer = vf->aq_resp;
 533         args.out_size = I40E_AQ_BUF_SZ;
 534         ret = i40evf_execute_vf_cmd(dev, &args);
 535         if (ret)
 536                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 537                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 538
 539         return ret;
 540 }
 541
 542 static int
 543 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 544 {
 545         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 546         struct vf_cmd_info args;
 547         int ret;
 548
 549         memset(&args, 0, sizeof(args));
 550         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 551         args.in_args = NULL;
 552         args.in_args_size = 0;
 553         args.out_buffer = vf->aq_resp;
 554         args.out_size = I40E_AQ_BUF_SZ;
 555         ret = i40evf_execute_vf_cmd(dev, &args);
 556         if (ret)
 557                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 558                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 559
 560         return ret;
 561 }
 562
 563 static void
 564 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 565                                   uint16_t vsi_id,
 566                                   uint16_t queue_id,
 567                                   uint16_t nb_txq,
 568                                   struct i40e_tx_queue *txq)
 569 {
 570         txq_info->vsi_id = vsi_id;
 571         txq_info->queue_id = queue_id;
 572         if (queue_id < nb_txq) {
 573                 txq_info->ring_len = txq->nb_tx_desc;
 574                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 575         }
 576 }
 577
 578 static void
 579 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 580                                   uint16_t vsi_id,
 581                                   uint16_t queue_id,
 582                                   uint16_t nb_rxq,
 583                                   uint32_t max_pkt_size,
 584                                   struct i40e_rx_queue *rxq)
 585 {
 586         rxq_info->vsi_id = vsi_id;
 587         rxq_info->queue_id = queue_id;
 588         rxq_info->max_pkt_size = max_pkt_size;
 589         if (queue_id < nb_rxq) {
 590                 rxq_info->ring_len = rxq->nb_rx_desc;
 591                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 592                 rxq_info->databuffer_size =
 593                         (rte_pktmbuf_data_room_size(rxq->mp) -
 594                                 RTE_PKTMBUF_HEADROOM);
 595         }
 596 }
 597
 598 static int
 599 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 600 {
 601         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 602         struct i40e_rx_queue **rxq =
 603                 (struct i40e_rx_queue **)dev->data->rx_queues;
 604         struct i40e_tx_queue **txq =
 605                 (struct i40e_tx_queue **)dev->data->tx_queues;
 606         struct virtchnl_vsi_queue_config_info *vc_vqci;
 607         struct virtchnl_queue_pair_info *vc_qpi;
 608         struct vf_cmd_info args;
 609         uint16_t i, nb_qp = vf->num_queue_pairs;
 610         const uint32_t size =
 611                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 612         uint8_t buff[size];
 613         int ret;
 614
 615         memset(buff, 0, sizeof(buff));
 616         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 617         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 618         vc_vqci->num_queue_pairs = nb_qp;
 619
 620         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 621                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 622                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 623                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 624                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 625                                         vf->max_pkt_len, rxq[i]);
 626         }
 627         memset(&args, 0, sizeof(args));
 628         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 629         args.in_args = (uint8_t *)vc_vqci;
 630         args.in_args_size = size;
 631         args.out_buffer = vf->aq_resp;
 632         args.out_size = I40E_AQ_BUF_SZ;
 633         ret = i40evf_execute_vf_cmd(dev, &args);
 634         if (ret)
 635                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 636                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 637
 638         return ret;
 639 }
 640
 641 static int
 642 i40evf_config_irq_map(struct rte_eth_dev *dev)
 643 {
 644         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 645         struct vf_cmd_info args;
 646         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 647                 sizeof(struct virtchnl_vector_map)];
 648         struct virtchnl_irq_map_info *map_info;
 649         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 650         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 651         uint32_t vector_id;
 652         int i, err;
 653
 654         if (rte_intr_allow_others(intr_handle))
 655                 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 656         else
 657                 vector_id = I40E_MISC_VEC_ID;
 658
 659         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 660         map_info->num_vectors = 1;
 661         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 662         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 663         /* Alway use default dynamic MSIX interrupt */
 664         map_info->vecmap[0].vector_id = vector_id;
 665         /* Don't map any tx queue */
 666         map_info->vecmap[0].txq_map = 0;
 667         map_info->vecmap[0].rxq_map = 0;
 668         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 669                 map_info->vecmap[0].rxq_map |= 1 << i;
 670                 if (rte_intr_dp_is_en(intr_handle))
 671                         intr_handle->intr_vec[i] = vector_id;
 672         }
 673
 674         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 675         args.in_args = (u8 *)cmd_buffer;
 676         args.in_args_size = sizeof(cmd_buffer);
 677         args.out_buffer = vf->aq_resp;
 678         args.out_size = I40E_AQ_BUF_SZ;
 679         err = i40evf_execute_vf_cmd(dev, &args);
 680         if (err)
 681                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 682
 683         return err;
 684 }
 685
 686 static int
 687 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 688                                 bool on)
 689 {
 690         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 691         struct virtchnl_queue_select queue_select;
 692         int err;
 693         struct vf_cmd_info args;
 694         memset(&queue_select, 0, sizeof(queue_select));
 695         queue_select.vsi_id = vf->vsi_res->vsi_id;
 696
 697         if (isrx)
 698                 queue_select.rx_queues |= 1 << qid;
 699         else
 700                 queue_select.tx_queues |= 1 << qid;
 701
 702         if (on)
 703                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 704         else
 705                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 706         args.in_args = (u8 *)&queue_select;
 707         args.in_args_size = sizeof(queue_select);
 708         args.out_buffer = vf->aq_resp;
 709         args.out_size = I40E_AQ_BUF_SZ;
 710         err = i40evf_execute_vf_cmd(dev, &args);
 711         if (err)
 712                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 713                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 714
 715         return err;
 716 }
 717
 718 static int
 719 i40evf_start_queues(struct rte_eth_dev *dev)
 720 {
 721         struct rte_eth_dev_data *dev_data = dev->data;
 722         int i;
 723         struct i40e_rx_queue *rxq;
 724         struct i40e_tx_queue *txq;
 725
 726         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 727                 rxq = dev_data->rx_queues[i];
 728                 if (rxq->rx_deferred_start)
 729                         continue;
 730                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 731                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 732                         return -1;
 733                 }
 734         }
 735
 736         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 737                 txq = dev_data->tx_queues[i];
 738                 if (txq->tx_deferred_start)
 739                         continue;
 740                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 741                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 742                         return -1;
 743                 }
 744         }
 745
 746         return 0;
 747 }
 748
 749 static int
 750 i40evf_stop_queues(struct rte_eth_dev *dev)
 751 {
 752         int i;
 753
 754         /* Stop TX queues first */
 755         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 756                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 757                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 758                         return -1;
 759                 }
 760         }
 761
 762         /* Then stop RX queues */
 763         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 764                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 765                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 766                         return -1;
 767                 }
 768         }
 769
 770         return 0;
 771 }
 772
 773 static int
 774 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 775                     struct ether_addr *addr,
 776                     __rte_unused uint32_t index,
 777                     __rte_unused uint32_t pool)
 778 {
 779         struct virtchnl_ether_addr_list *list;
 780         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 781         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 782                         sizeof(struct virtchnl_ether_addr)];
 783         int err;
 784         struct vf_cmd_info args;
 785
 786         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 787                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 788                             addr->addr_bytes[0], addr->addr_bytes[1],
 789                             addr->addr_bytes[2], addr->addr_bytes[3],
 790                             addr->addr_bytes[4], addr->addr_bytes[5]);
 791                 return I40E_ERR_INVALID_MAC_ADDR;
 792         }
 793
 794         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 795         list->vsi_id = vf->vsi_res->vsi_id;
 796         list->num_elements = 1;
 797         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 798                                         sizeof(addr->addr_bytes));
 799
 800         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 801         args.in_args = cmd_buffer;
 802         args.in_args_size = sizeof(cmd_buffer);
 803         args.out_buffer = vf->aq_resp;
 804         args.out_size = I40E_AQ_BUF_SZ;
 805         err = i40evf_execute_vf_cmd(dev, &args);
 806         if (err)
 807                 PMD_DRV_LOG(ERR, "fail to execute command "
 808                             "OP_ADD_ETHER_ADDRESS");
 809         else
 810                 vf->vsi.mac_num++;
 811
 812         return err;
 813 }
 814
 815 static void
 816 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 817                             struct ether_addr *addr)
 818 {
 819         struct virtchnl_ether_addr_list *list;
 820         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 821         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 822                         sizeof(struct virtchnl_ether_addr)];
 823         int err;
 824         struct vf_cmd_info args;
 825
 826         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 827                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 828                             addr->addr_bytes[0], addr->addr_bytes[1],
 829                             addr->addr_bytes[2], addr->addr_bytes[3],
 830                             addr->addr_bytes[4], addr->addr_bytes[5]);
 831                 return;
 832         }
 833
 834         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 835         list->vsi_id = vf->vsi_res->vsi_id;
 836         list->num_elements = 1;
 837         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 838                         sizeof(addr->addr_bytes));
 839
 840         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 841         args.in_args = cmd_buffer;
 842         args.in_args_size = sizeof(cmd_buffer);
 843         args.out_buffer = vf->aq_resp;
 844         args.out_size = I40E_AQ_BUF_SZ;
 845         err = i40evf_execute_vf_cmd(dev, &args);
 846         if (err)
 847                 PMD_DRV_LOG(ERR, "fail to execute command "
 848                             "OP_DEL_ETHER_ADDRESS");
 849         else
 850                 vf->vsi.mac_num--;
 851         return;
 852 }
 853
 854 static void
 855 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 856 {
 857         struct rte_eth_dev_data *data = dev->data;
 858         struct ether_addr *addr;
 859
 860         addr = &data->mac_addrs[index];
 861
 862         i40evf_del_mac_addr_by_addr(dev, addr);
 863 }
 864
 865 static int
 866 i40evf_update_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 867 {
 868         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 869         struct virtchnl_queue_select q_stats;
 870         int err;
 871         struct vf_cmd_info args;
 872
 873         memset(&q_stats, 0, sizeof(q_stats));
 874         q_stats.vsi_id = vf->vsi_res->vsi_id;
 875         args.ops = VIRTCHNL_OP_GET_STATS;
 876         args.in_args = (u8 *)&q_stats;
 877         args.in_args_size = sizeof(q_stats);
 878         args.out_buffer = vf->aq_resp;
 879         args.out_size = I40E_AQ_BUF_SZ;
 880
 881         err = i40evf_execute_vf_cmd(dev, &args);
 882         if (err) {
 883                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 884                 *pstats = NULL;
 885                 return err;
 886         }
 887         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 888         return 0;
 889 }
 890
 891 static int
 892 i40evf_get_statistics(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
 893 {
 894         int ret;
 895         struct i40e_eth_stats *pstats = NULL;
 896
 897         ret = i40evf_update_stats(dev, &pstats);
 898         if (ret != 0)
 899                 return 0;
 900
 901         stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
 902                                                 pstats->rx_broadcast;
 903         stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
 904                                                 pstats->tx_unicast;
 905         stats->imissed = pstats->rx_discards;
 906         stats->oerrors = pstats->tx_errors + pstats->tx_discards;
 907         stats->ibytes = pstats->rx_bytes;
 908         stats->obytes = pstats->tx_bytes;
 909
 910         return 0;
 911 }
 912
 913 static void
 914 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 915 {
 916         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 917         struct i40e_eth_stats *pstats = NULL;
 918
 919         /* read stat values to clear hardware registers */
 920         i40evf_update_stats(dev, &pstats);
 921
 922         /* set stats offset base on current values */
 923         vf->vsi.eth_stats_offset = vf->vsi.eth_stats;
 924 }
 925
 926 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 927                                       struct rte_eth_xstat_name *xstats_names,
 928                                       __rte_unused unsigned limit)
 929 {
 930         unsigned i;
 931
 932         if (xstats_names != NULL)
 933                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 934                         snprintf(xstats_names[i].name,
 935                                 sizeof(xstats_names[i].name),
 936                                 "%s", rte_i40evf_stats_strings[i].name);
 937                 }
 938         return I40EVF_NB_XSTATS;
 939 }
 940
 941 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 942                                  struct rte_eth_xstat *xstats, unsigned n)
 943 {
 944         int ret;
 945         unsigned i;
 946         struct i40e_eth_stats *pstats = NULL;
 947
 948         if (n < I40EVF_NB_XSTATS)
 949                 return I40EVF_NB_XSTATS;
 950
 951         ret = i40evf_update_stats(dev, &pstats);
 952         if (ret != 0)
 953                 return 0;
 954
 955         if (!xstats)
 956                 return 0;
 957
 958         /* loop over xstats array and values from pstats */
 959         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 960                 xstats[i].id = i;
 961                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
 962                         rte_i40evf_stats_strings[i].offset);
 963         }
 964
 965         return I40EVF_NB_XSTATS;
 966 }
 967
 968 static int
 969 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
 970 {
 971         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 972         struct virtchnl_vlan_filter_list *vlan_list;
 973         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
 974                                                         sizeof(uint16_t)];
 975         int err;
 976         struct vf_cmd_info args;
 977
 978         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
 979         vlan_list->vsi_id = vf->vsi_res->vsi_id;
 980         vlan_list->num_elements = 1;
 981         vlan_list->vlan_id[0] = vlanid;
 982
 983         args.ops = VIRTCHNL_OP_ADD_VLAN;
 984         args.in_args = (u8 *)&cmd_buffer;
 985         args.in_args_size = sizeof(cmd_buffer);
 986         args.out_buffer = vf->aq_resp;
 987         args.out_size = I40E_AQ_BUF_SZ;
 988         err = i40evf_execute_vf_cmd(dev, &args);
 989         if (err)
 990                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
 991
 992         return err;
 993 }
 994
 995 static int
 996 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
 997 {
 998         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 999         struct virtchnl_vlan_filter_list *vlan_list;
1000         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1001                                                         sizeof(uint16_t)];
1002         int err;
1003         struct vf_cmd_info args;
1004
1005         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1006         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1007         vlan_list->num_elements = 1;
1008         vlan_list->vlan_id[0] = vlanid;
1009
1010         args.ops = VIRTCHNL_OP_DEL_VLAN;
1011         args.in_args = (u8 *)&cmd_buffer;
1012         args.in_args_size = sizeof(cmd_buffer);
1013         args.out_buffer = vf->aq_resp;
1014         args.out_size = I40E_AQ_BUF_SZ;
1015         err = i40evf_execute_vf_cmd(dev, &args);
1016         if (err)
1017                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1018
1019         return err;
1020 }
1021
1022 static const struct rte_pci_id pci_id_i40evf_map[] = {
1023         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1024         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1025         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1026         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1027         { .vendor_id = 0, /* sentinel */ },
1028 };
1029
1030 static inline int
1031 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1032                                     struct rte_eth_link *link)
1033 {
1034         struct rte_eth_link *dst = &(dev->data->dev_link);
1035         struct rte_eth_link *src = link;
1036
1037         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1038                                         *(uint64_t *)src) == 0)
1039                 return -1;
1040
1041         return 0;
1042 }
1043
1044 /* Disable IRQ0 */
1045 static inline void
1046 i40evf_disable_irq0(struct i40e_hw *hw)
1047 {
1048         /* Disable all interrupt types */
1049         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1050         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1051                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1052         I40EVF_WRITE_FLUSH(hw);
1053 }
1054
1055 /* Enable IRQ0 */
1056 static inline void
1057 i40evf_enable_irq0(struct i40e_hw *hw)
1058 {
1059         /* Enable admin queue interrupt trigger */
1060         uint32_t val;
1061
1062         i40evf_disable_irq0(hw);
1063         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1064         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1065                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1066         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1067
1068         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1069                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1070                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1071                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1072
1073         I40EVF_WRITE_FLUSH(hw);
1074 }
1075
1076 static int
1077 i40evf_reset_vf(struct i40e_hw *hw)
1078 {
1079         int i, reset;
1080
1081         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1082                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1083                 return -1;
1084         }
1085         /**
1086           * After issuing vf reset command to pf, pf won't necessarily
1087           * reset vf, it depends on what state it exactly is. If it's not
1088           * initialized yet, it won't have vf reset since it's in a certain
1089           * state. If not, it will try to reset. Even vf is reset, pf will
1090           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1091           * it to ACTIVE. In this duration, vf may not catch the moment that
1092           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1093           */
1094         rte_delay_ms(200);
1095
1096         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1097                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1098                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1099                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1100                 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1101                         break;
1102                 else
1103                         rte_delay_ms(50);
1104         }
1105
1106         if (i >= MAX_RESET_WAIT_CNT) {
1107                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1108                 return -1;
1109         }
1110
1111         return 0;
1112 }
1113
1114 static int
1115 i40evf_init_vf(struct rte_eth_dev *dev)
1116 {
1117         int i, err, bufsz;
1118         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1119         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1120         uint16_t interval =
1121                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1122
1123         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1124         vf->dev_data = dev->data;
1125         err = i40e_set_mac_type(hw);
1126         if (err) {
1127                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1128                 goto err;
1129         }
1130
1131         i40e_init_adminq_parameter(hw);
1132         err = i40e_init_adminq(hw);
1133         if (err) {
1134                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1135                 goto err;
1136         }
1137
1138         /* Reset VF and wait until it's complete */
1139         if (i40evf_reset_vf(hw)) {
1140                 PMD_INIT_LOG(ERR, "reset NIC failed");
1141                 goto err_aq;
1142         }
1143
1144         /* VF reset, shutdown admin queue and initialize again */
1145         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1146                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1147                 goto err;
1148         }
1149
1150         i40e_init_adminq_parameter(hw);
1151         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1152                 PMD_INIT_LOG(ERR, "init_adminq failed");
1153                 goto err;
1154         }
1155         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1156         if (!vf->aq_resp) {
1157                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1158                 goto err_aq;
1159         }
1160         if (i40evf_check_api_version(dev) != 0) {
1161                 PMD_INIT_LOG(ERR, "check_api version failed");
1162                 goto err_api;
1163         }
1164         bufsz = sizeof(struct virtchnl_vf_resource) +
1165                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1166         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1167         if (!vf->vf_res) {
1168                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1169                 goto err_api;
1170         }
1171
1172         if (i40evf_get_vf_resource(dev) != 0) {
1173                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1174                 goto err_alloc;
1175         }
1176
1177         /* got VF config message back from PF, now we can parse it */
1178         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1179                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1180                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1181         }
1182
1183         if (!vf->vsi_res) {
1184                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1185                 goto err_alloc;
1186         }
1187
1188         if (hw->mac.type == I40E_MAC_X722_VF)
1189                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1190         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1191         vf->vsi.type = (enum i40e_vsi_type)vf->vsi_res->vsi_type;
1192         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1193         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1194
1195         /* Store the MAC address configured by host, or generate random one */
1196         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1197                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1198         else
1199                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1200
1201         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1202                        (I40E_ITR_INDEX_DEFAULT <<
1203                         I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1204                        (interval <<
1205                         I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1206         I40EVF_WRITE_FLUSH(hw);
1207
1208         return 0;
1209
1210 err_alloc:
1211         rte_free(vf->vf_res);
1212         vf->vsi_res = NULL;
1213 err_api:
1214         rte_free(vf->aq_resp);
1215 err_aq:
1216         i40e_shutdown_adminq(hw); /* ignore error */
1217 err:
1218         return -1;
1219 }
1220
1221 static int
1222 i40evf_uninit_vf(struct rte_eth_dev *dev)
1223 {
1224         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1225         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1226
1227         PMD_INIT_FUNC_TRACE();
1228
1229         if (hw->adapter_stopped == 0)
1230                 i40evf_dev_close(dev);
1231         rte_free(vf->vf_res);
1232         vf->vf_res = NULL;
1233         rte_free(vf->aq_resp);
1234         vf->aq_resp = NULL;
1235
1236         return 0;
1237 }
1238
1239 static void
1240 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1241                 __rte_unused uint16_t msglen)
1242 {
1243         struct virtchnl_pf_event *pf_msg =
1244                         (struct virtchnl_pf_event *)msg;
1245         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1246
1247         switch (pf_msg->event) {
1248         case VIRTCHNL_EVENT_RESET_IMPENDING:
1249                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1250                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1251                                               NULL, NULL);
1252                 break;
1253         case VIRTCHNL_EVENT_LINK_CHANGE:
1254                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1255                 vf->link_up = pf_msg->event_data.link_event.link_status;
1256                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1257                 break;
1258         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1259                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1260                 break;
1261         default:
1262                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1263                 break;
1264         }
1265 }
1266
1267 static void
1268 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1269 {
1270         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1272         struct i40e_arq_event_info info;
1273         uint16_t pending, aq_opc;
1274         enum virtchnl_ops msg_opc;
1275         enum i40e_status_code msg_ret;
1276         int ret;
1277
1278         info.buf_len = I40E_AQ_BUF_SZ;
1279         if (!vf->aq_resp) {
1280                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1281                 return;
1282         }
1283         info.msg_buf = vf->aq_resp;
1284
1285         pending = 1;
1286         while (pending) {
1287                 ret = i40e_clean_arq_element(hw, &info, &pending);
1288
1289                 if (ret != I40E_SUCCESS) {
1290                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1291                                     "ret: %d", ret);
1292                         break;
1293                 }
1294                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1295                 /* For the message sent from pf to vf, opcode is stored in
1296                  * cookie_high of struct i40e_aq_desc, while return error code
1297                  * are stored in cookie_low, Which is done by
1298                  * i40e_aq_send_msg_to_vf in PF driver.*/
1299                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1300                                                   info.desc.cookie_high);
1301                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1302                                                   info.desc.cookie_low);
1303                 switch (aq_opc) {
1304                 case i40e_aqc_opc_send_msg_to_vf:
1305                         if (msg_opc == VIRTCHNL_OP_EVENT)
1306                                 /* process event*/
1307                                 i40evf_handle_pf_event(dev, info.msg_buf,
1308                                                        info.msg_len);
1309                         else {
1310                                 /* read message and it's expected one */
1311                                 if (msg_opc == vf->pend_cmd) {
1312                                         vf->cmd_retval = msg_ret;
1313                                         /* prevent compiler reordering */
1314                                         rte_compiler_barrier();
1315                                         _clear_cmd(vf);
1316                                 } else
1317                                         PMD_DRV_LOG(ERR, "command mismatch,"
1318                                                 "expect %u, get %u",
1319                                                 vf->pend_cmd, msg_opc);
1320                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1321                                              " opcode = %d", msg_opc);
1322                         }
1323                         break;
1324                 default:
1325                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1326                                     aq_opc);
1327                         break;
1328                 }
1329         }
1330 }
1331
1332 /**
1333  * Interrupt handler triggered by NIC  for handling
1334  * specific interrupt. Only adminq interrupt is processed in VF.
1335  *
1336  * @param handle
1337  *  Pointer to interrupt handle.
1338  * @param param
1339  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1340  *
1341  * @return
1342  *  void
1343  */
1344 static void
1345 i40evf_dev_interrupt_handler(void *param)
1346 {
1347         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1348         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1349         uint32_t icr0;
1350
1351         i40evf_disable_irq0(hw);
1352
1353         /* read out interrupt causes */
1354         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1355
1356         /* No interrupt event indicated */
1357         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1358                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1359                 goto done;
1360         }
1361
1362         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1363                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1364                 i40evf_handle_aq_msg(dev);
1365         }
1366
1367         /* Link Status Change interrupt */
1368         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1369                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1370                                    " do nothing");
1371
1372 done:
1373         i40evf_enable_irq0(hw);
1374         rte_intr_enable(dev->intr_handle);
1375 }
1376
1377 static int
1378 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1379 {
1380         struct i40e_hw *hw
1381                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1382         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1383
1384         PMD_INIT_FUNC_TRACE();
1385
1386         /* assign ops func pointer */
1387         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1388         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1389         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1390
1391         /*
1392          * For secondary processes, we don't initialise any further as primary
1393          * has already done this work.
1394          */
1395         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1396                 i40e_set_rx_function(eth_dev);
1397                 i40e_set_tx_function(eth_dev);
1398                 return 0;
1399         }
1400         i40e_set_default_ptype_table(eth_dev);
1401         rte_eth_copy_pci_info(eth_dev, pci_dev);
1402         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1403
1404         hw->vendor_id = pci_dev->id.vendor_id;
1405         hw->device_id = pci_dev->id.device_id;
1406         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1407         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1408         hw->bus.device = pci_dev->addr.devid;
1409         hw->bus.func = pci_dev->addr.function;
1410         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1411         hw->adapter_stopped = 0;
1412
1413         if(i40evf_init_vf(eth_dev) != 0) {
1414                 PMD_INIT_LOG(ERR, "Init vf failed");
1415                 return -1;
1416         }
1417
1418         /* register callback func to eal lib */
1419         rte_intr_callback_register(&pci_dev->intr_handle,
1420                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1421
1422         /* enable uio intr after callback register */
1423         rte_intr_enable(&pci_dev->intr_handle);
1424
1425         /* configure and enable device interrupt */
1426         i40evf_enable_irq0(hw);
1427
1428         /* copy mac addr */
1429         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1430                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1431                                         0);
1432         if (eth_dev->data->mac_addrs == NULL) {
1433                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1434                                 " store MAC addresses",
1435                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1436                 return -ENOMEM;
1437         }
1438         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1439                         &eth_dev->data->mac_addrs[0]);
1440
1441         return 0;
1442 }
1443
1444 static int
1445 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1446 {
1447         PMD_INIT_FUNC_TRACE();
1448
1449         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1450                 return -EPERM;
1451
1452         eth_dev->dev_ops = NULL;
1453         eth_dev->rx_pkt_burst = NULL;
1454         eth_dev->tx_pkt_burst = NULL;
1455
1456         if (i40evf_uninit_vf(eth_dev) != 0) {
1457                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1458                 return -1;
1459         }
1460
1461         rte_free(eth_dev->data->mac_addrs);
1462         eth_dev->data->mac_addrs = NULL;
1463
1464         return 0;
1465 }
1466
1467 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1468         struct rte_pci_device *pci_dev)
1469 {
1470         return rte_eth_dev_pci_generic_probe(pci_dev,
1471                 sizeof(struct i40e_adapter), i40evf_dev_init);
1472 }
1473
1474 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1475 {
1476         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1477 }
1478
1479 /*
1480  * virtual function driver struct
1481  */
1482 static struct rte_pci_driver rte_i40evf_pmd = {
1483         .id_table = pci_id_i40evf_map,
1484         .drv_flags = RTE_PCI_DRV_NEED_MAPPING,
1485         .probe = eth_i40evf_pci_probe,
1486         .remove = eth_i40evf_pci_remove,
1487 };
1488
1489 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1490 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1491 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1492
1493 static int
1494 i40evf_dev_configure(struct rte_eth_dev *dev)
1495 {
1496         struct i40e_adapter *ad =
1497                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1498         struct rte_eth_conf *conf = &dev->data->dev_conf;
1499         struct i40e_vf *vf;
1500
1501         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1502          * allocation or vector Rx preconditions we will reset it.
1503          */
1504         ad->rx_bulk_alloc_allowed = true;
1505         ad->rx_vec_allowed = true;
1506         ad->tx_simple_allowed = true;
1507         ad->tx_vec_allowed = true;
1508
1509         /* For non-DPDK PF drivers, VF has no ability to disable HW
1510          * CRC strip, and is implicitly enabled by the PF.
1511          */
1512         if (!conf->rxmode.hw_strip_crc) {
1513                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1514                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1515                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1516                         /* Peer is running non-DPDK PF driver. */
1517                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1518                         return -EINVAL;
1519                 }
1520         }
1521
1522         return i40evf_init_vlan(dev);
1523 }
1524
1525 static int
1526 i40evf_init_vlan(struct rte_eth_dev *dev)
1527 {
1528         /* Apply vlan offload setting */
1529         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1530
1531         return I40E_SUCCESS;
1532 }
1533
1534 static void
1535 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1536 {
1537         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1538
1539         /* Vlan stripping setting */
1540         if (mask & ETH_VLAN_STRIP_MASK) {
1541                 /* Enable or disable VLAN stripping */
1542                 if (dev_conf->rxmode.hw_vlan_strip)
1543                         i40evf_enable_vlan_strip(dev);
1544                 else
1545                         i40evf_disable_vlan_strip(dev);
1546         }
1547 }
1548
1549 static int
1550 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1551 {
1552         struct i40e_rx_queue *rxq;
1553         int err = 0;
1554         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1555
1556         PMD_INIT_FUNC_TRACE();
1557
1558         if (rx_queue_id < dev->data->nb_rx_queues) {
1559                 rxq = dev->data->rx_queues[rx_queue_id];
1560
1561                 err = i40e_alloc_rx_queue_mbufs(rxq);
1562                 if (err) {
1563                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1564                         return err;
1565                 }
1566
1567                 rte_wmb();
1568
1569                 /* Init the RX tail register. */
1570                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1571                 I40EVF_WRITE_FLUSH(hw);
1572
1573                 /* Ready to switch the queue on */
1574                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1575
1576                 if (err)
1577                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1578                                     rx_queue_id);
1579                 else
1580                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1581         }
1582
1583         return err;
1584 }
1585
1586 static int
1587 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1588 {
1589         struct i40e_rx_queue *rxq;
1590         int err;
1591
1592         if (rx_queue_id < dev->data->nb_rx_queues) {
1593                 rxq = dev->data->rx_queues[rx_queue_id];
1594
1595                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1596
1597                 if (err) {
1598                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1599                                     rx_queue_id);
1600                         return err;
1601                 }
1602
1603                 i40e_rx_queue_release_mbufs(rxq);
1604                 i40e_reset_rx_queue(rxq);
1605                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1606         }
1607
1608         return 0;
1609 }
1610
1611 static int
1612 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1613 {
1614         int err = 0;
1615
1616         PMD_INIT_FUNC_TRACE();
1617
1618         if (tx_queue_id < dev->data->nb_tx_queues) {
1619
1620                 /* Ready to switch the queue on */
1621                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1622
1623                 if (err)
1624                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1625                                     tx_queue_id);
1626                 else
1627                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1628         }
1629
1630         return err;
1631 }
1632
1633 static int
1634 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1635 {
1636         struct i40e_tx_queue *txq;
1637         int err;
1638
1639         if (tx_queue_id < dev->data->nb_tx_queues) {
1640                 txq = dev->data->tx_queues[tx_queue_id];
1641
1642                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1643
1644                 if (err) {
1645                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1646                                     tx_queue_id);
1647                         return err;
1648                 }
1649
1650                 i40e_tx_queue_release_mbufs(txq);
1651                 i40e_reset_tx_queue(txq);
1652                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1653         }
1654
1655         return 0;
1656 }
1657
1658 static int
1659 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1660 {
1661         int ret;
1662
1663         if (on)
1664                 ret = i40evf_add_vlan(dev, vlan_id);
1665         else
1666                 ret = i40evf_del_vlan(dev,vlan_id);
1667
1668         return ret;
1669 }
1670
1671 static int
1672 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1673 {
1674         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1675         struct rte_eth_dev_data *dev_data = dev->data;
1676         struct rte_pktmbuf_pool_private *mbp_priv;
1677         uint16_t buf_size, len;
1678
1679         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1680         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1681         I40EVF_WRITE_FLUSH(hw);
1682
1683         /* Calculate the maximum packet length allowed */
1684         mbp_priv = rte_mempool_get_priv(rxq->mp);
1685         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1686                                         RTE_PKTMBUF_HEADROOM);
1687         rxq->hs_mode = i40e_header_split_none;
1688         rxq->rx_hdr_len = 0;
1689         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1690         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1691         rxq->max_pkt_len = RTE_MIN(len,
1692                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1693
1694         /**
1695          * Check if the jumbo frame and maximum packet length are set correctly
1696          */
1697         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1698                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1699                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1700                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1701                                 "larger than %u and smaller than %u, as jumbo "
1702                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1703                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1704                         return I40E_ERR_CONFIG;
1705                 }
1706         } else {
1707                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1708                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1709                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1710                                 "larger than %u and smaller than %u, as jumbo "
1711                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1712                                                 (uint32_t)ETHER_MAX_LEN);
1713                         return I40E_ERR_CONFIG;
1714                 }
1715         }
1716
1717         if (dev_data->dev_conf.rxmode.enable_scatter ||
1718             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1719                 dev_data->scattered_rx = 1;
1720         }
1721
1722         return 0;
1723 }
1724
1725 static int
1726 i40evf_rx_init(struct rte_eth_dev *dev)
1727 {
1728         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1729         uint16_t i;
1730         int ret = I40E_SUCCESS;
1731         struct i40e_rx_queue **rxq =
1732                 (struct i40e_rx_queue **)dev->data->rx_queues;
1733
1734         i40evf_config_rss(vf);
1735         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1736                 if (!rxq[i] || !rxq[i]->q_set)
1737                         continue;
1738                 ret = i40evf_rxq_init(dev, rxq[i]);
1739                 if (ret != I40E_SUCCESS)
1740                         break;
1741         }
1742         if (ret == I40E_SUCCESS)
1743                 i40e_set_rx_function(dev);
1744
1745         return ret;
1746 }
1747
1748 static void
1749 i40evf_tx_init(struct rte_eth_dev *dev)
1750 {
1751         uint16_t i;
1752         struct i40e_tx_queue **txq =
1753                 (struct i40e_tx_queue **)dev->data->tx_queues;
1754         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1755
1756         for (i = 0; i < dev->data->nb_tx_queues; i++)
1757                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1758
1759         i40e_set_tx_function(dev);
1760 }
1761
1762 static inline void
1763 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1764 {
1765         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1766         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1767         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1768
1769         if (!rte_intr_allow_others(intr_handle)) {
1770                 I40E_WRITE_REG(hw,
1771                                I40E_VFINT_DYN_CTL01,
1772                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1773                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1774                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1775                 I40EVF_WRITE_FLUSH(hw);
1776                 return;
1777         }
1778
1779         I40EVF_WRITE_FLUSH(hw);
1780 }
1781
1782 static inline void
1783 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1784 {
1785         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1786         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1787         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1788
1789         if (!rte_intr_allow_others(intr_handle)) {
1790                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1791                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1792                 I40EVF_WRITE_FLUSH(hw);
1793                 return;
1794         }
1795
1796         I40EVF_WRITE_FLUSH(hw);
1797 }
1798
1799 static int
1800 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1801 {
1802         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1803         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1804         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805         uint16_t interval =
1806                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1807         uint16_t msix_intr;
1808
1809         msix_intr = intr_handle->intr_vec[queue_id];
1810         if (msix_intr == I40E_MISC_VEC_ID)
1811                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1812                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1813                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1814                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1815                                (interval <<
1816                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1817         else
1818                 I40E_WRITE_REG(hw,
1819                                I40E_VFINT_DYN_CTLN1(msix_intr -
1820                                                     I40E_RX_VEC_START),
1821                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1822                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1823                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1824                                (interval <<
1825                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1826
1827         I40EVF_WRITE_FLUSH(hw);
1828
1829         rte_intr_enable(&pci_dev->intr_handle);
1830
1831         return 0;
1832 }
1833
1834 static int
1835 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1836 {
1837         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1838         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1839         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1840         uint16_t msix_intr;
1841
1842         msix_intr = intr_handle->intr_vec[queue_id];
1843         if (msix_intr == I40E_MISC_VEC_ID)
1844                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1845         else
1846                 I40E_WRITE_REG(hw,
1847                                I40E_VFINT_DYN_CTLN1(msix_intr -
1848                                                     I40E_RX_VEC_START),
1849                                0);
1850
1851         I40EVF_WRITE_FLUSH(hw);
1852
1853         return 0;
1854 }
1855
1856 static void
1857 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1858 {
1859         struct virtchnl_ether_addr_list *list;
1860         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1861         int err, i, j;
1862         int next_begin = 0;
1863         int begin = 0;
1864         uint32_t len;
1865         struct ether_addr *addr;
1866         struct vf_cmd_info args;
1867
1868         do {
1869                 j = 0;
1870                 len = sizeof(struct virtchnl_ether_addr_list);
1871                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1872                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1873                                 continue;
1874                         len += sizeof(struct virtchnl_ether_addr);
1875                         if (len >= I40E_AQ_BUF_SZ) {
1876                                 next_begin = i + 1;
1877                                 break;
1878                         }
1879                 }
1880
1881                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1882                 if (!list) {
1883                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1884                         return;
1885                 }
1886
1887                 for (i = begin; i < next_begin; i++) {
1888                         addr = &dev->data->mac_addrs[i];
1889                         if (is_zero_ether_addr(addr))
1890                                 continue;
1891                         rte_memcpy(list->list[j].addr, addr->addr_bytes,
1892                                          sizeof(addr->addr_bytes));
1893                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1894                                     addr->addr_bytes[0], addr->addr_bytes[1],
1895                                     addr->addr_bytes[2], addr->addr_bytes[3],
1896                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1897                         j++;
1898                 }
1899                 list->vsi_id = vf->vsi_res->vsi_id;
1900                 list->num_elements = j;
1901                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1902                            VIRTCHNL_OP_DEL_ETH_ADDR;
1903                 args.in_args = (uint8_t *)list;
1904                 args.in_args_size = len;
1905                 args.out_buffer = vf->aq_resp;
1906                 args.out_size = I40E_AQ_BUF_SZ;
1907                 err = i40evf_execute_vf_cmd(dev, &args);
1908                 if (err) {
1909                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1910                                     add ? "OP_ADD_ETHER_ADDRESS" :
1911                                     "OP_DEL_ETHER_ADDRESS");
1912                 } else {
1913                         if (add)
1914                                 vf->vsi.mac_num++;
1915                         else
1916                                 vf->vsi.mac_num--;
1917                 }
1918                 rte_free(list);
1919                 begin = next_begin;
1920         } while (begin < I40E_NUM_MACADDR_MAX);
1921 }
1922
1923 static int
1924 i40evf_dev_start(struct rte_eth_dev *dev)
1925 {
1926         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1927         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1928         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1929         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1930         uint32_t intr_vector = 0;
1931
1932         PMD_INIT_FUNC_TRACE();
1933
1934         hw->adapter_stopped = 0;
1935
1936         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1937         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1938                                         dev->data->nb_tx_queues);
1939
1940         /* check and configure queue intr-vector mapping */
1941         if (dev->data->dev_conf.intr_conf.rxq != 0) {
1942                 intr_vector = dev->data->nb_rx_queues;
1943                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1944                         return -1;
1945         }
1946
1947         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1948                 intr_handle->intr_vec =
1949                         rte_zmalloc("intr_vec",
1950                                     dev->data->nb_rx_queues * sizeof(int), 0);
1951                 if (!intr_handle->intr_vec) {
1952                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1953                                      " intr_vec", dev->data->nb_rx_queues);
1954                         return -ENOMEM;
1955                 }
1956         }
1957
1958         if (i40evf_rx_init(dev) != 0){
1959                 PMD_DRV_LOG(ERR, "failed to do RX init");
1960                 return -1;
1961         }
1962
1963         i40evf_tx_init(dev);
1964
1965         if (i40evf_configure_vsi_queues(dev) != 0) {
1966                 PMD_DRV_LOG(ERR, "configure queues failed");
1967                 goto err_queue;
1968         }
1969         if (i40evf_config_irq_map(dev)) {
1970                 PMD_DRV_LOG(ERR, "config_irq_map failed");
1971                 goto err_queue;
1972         }
1973
1974         /* Set all mac addrs */
1975         i40evf_add_del_all_mac_addr(dev, TRUE);
1976
1977         if (i40evf_start_queues(dev) != 0) {
1978                 PMD_DRV_LOG(ERR, "enable queues failed");
1979                 goto err_mac;
1980         }
1981
1982         i40evf_enable_queues_intr(dev);
1983         return 0;
1984
1985 err_mac:
1986         i40evf_add_del_all_mac_addr(dev, FALSE);
1987 err_queue:
1988         return -1;
1989 }
1990
1991 static void
1992 i40evf_dev_stop(struct rte_eth_dev *dev)
1993 {
1994         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1995         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1996         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1997
1998         PMD_INIT_FUNC_TRACE();
1999
2000         if (hw->adapter_stopped == 1)
2001                 return;
2002         i40evf_stop_queues(dev);
2003         i40evf_disable_queues_intr(dev);
2004         i40e_dev_clear_queues(dev);
2005
2006         /* Clean datapath event and queue/vec mapping */
2007         rte_intr_efd_disable(intr_handle);
2008         if (intr_handle->intr_vec) {
2009                 rte_free(intr_handle->intr_vec);
2010                 intr_handle->intr_vec = NULL;
2011         }
2012         /* remove all mac addrs */
2013         i40evf_add_del_all_mac_addr(dev, FALSE);
2014         hw->adapter_stopped = 1;
2015
2016 }
2017
2018 static int
2019 i40evf_dev_link_update(struct rte_eth_dev *dev,
2020                        __rte_unused int wait_to_complete)
2021 {
2022         struct rte_eth_link new_link;
2023         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2024         /*
2025          * DPDK pf host provide interfacet to acquire link status
2026          * while Linux driver does not
2027          */
2028
2029         /* Linux driver PF host */
2030         switch (vf->link_speed) {
2031         case I40E_LINK_SPEED_100MB:
2032                 new_link.link_speed = ETH_SPEED_NUM_100M;
2033                 break;
2034         case I40E_LINK_SPEED_1GB:
2035                 new_link.link_speed = ETH_SPEED_NUM_1G;
2036                 break;
2037         case I40E_LINK_SPEED_10GB:
2038                 new_link.link_speed = ETH_SPEED_NUM_10G;
2039                 break;
2040         case I40E_LINK_SPEED_20GB:
2041                 new_link.link_speed = ETH_SPEED_NUM_20G;
2042                 break;
2043         case I40E_LINK_SPEED_25GB:
2044                 new_link.link_speed = ETH_SPEED_NUM_25G;
2045                 break;
2046         case I40E_LINK_SPEED_40GB:
2047                 new_link.link_speed = ETH_SPEED_NUM_40G;
2048                 break;
2049         default:
2050                 new_link.link_speed = ETH_SPEED_NUM_100M;
2051                 break;
2052         }
2053         /* full duplex only */
2054         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2055         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2056                                              ETH_LINK_DOWN;
2057
2058         i40evf_dev_atomic_write_link_status(dev, &new_link);
2059
2060         return 0;
2061 }
2062
2063 static void
2064 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2065 {
2066         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2067         int ret;
2068
2069         /* If enabled, just return */
2070         if (vf->promisc_unicast_enabled)
2071                 return;
2072
2073         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2074         if (ret == 0)
2075                 vf->promisc_unicast_enabled = TRUE;
2076 }
2077
2078 static void
2079 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2080 {
2081         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2082         int ret;
2083
2084         /* If disabled, just return */
2085         if (!vf->promisc_unicast_enabled)
2086                 return;
2087
2088         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2089         if (ret == 0)
2090                 vf->promisc_unicast_enabled = FALSE;
2091 }
2092
2093 static void
2094 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2095 {
2096         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2097         int ret;
2098
2099         /* If enabled, just return */
2100         if (vf->promisc_multicast_enabled)
2101                 return;
2102
2103         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2104         if (ret == 0)
2105                 vf->promisc_multicast_enabled = TRUE;
2106 }
2107
2108 static void
2109 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2110 {
2111         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2112         int ret;
2113
2114         /* If enabled, just return */
2115         if (!vf->promisc_multicast_enabled)
2116                 return;
2117
2118         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2119         if (ret == 0)
2120                 vf->promisc_multicast_enabled = FALSE;
2121 }
2122
2123 static void
2124 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2125 {
2126         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2127
2128         memset(dev_info, 0, sizeof(*dev_info));
2129         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2130         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2131         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2132         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2133         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2134         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2135         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2136         dev_info->flow_type_rss_offloads = I40E_RSS_OFFLOAD_ALL;
2137         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2138         dev_info->rx_offload_capa =
2139                 DEV_RX_OFFLOAD_VLAN_STRIP |
2140                 DEV_RX_OFFLOAD_QINQ_STRIP |
2141                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2142                 DEV_RX_OFFLOAD_UDP_CKSUM |
2143                 DEV_RX_OFFLOAD_TCP_CKSUM;
2144         dev_info->tx_offload_capa =
2145                 DEV_TX_OFFLOAD_VLAN_INSERT |
2146                 DEV_TX_OFFLOAD_QINQ_INSERT |
2147                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2148                 DEV_TX_OFFLOAD_UDP_CKSUM |
2149                 DEV_TX_OFFLOAD_TCP_CKSUM |
2150                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2151
2152         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2153                 .rx_thresh = {
2154                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2155                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2156                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2157                 },
2158                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2159                 .rx_drop_en = 0,
2160         };
2161
2162         dev_info->default_txconf = (struct rte_eth_txconf) {
2163                 .tx_thresh = {
2164                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2165                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2166                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2167                 },
2168                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2169                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2170                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2171                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2172         };
2173
2174         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2175                 .nb_max = I40E_MAX_RING_DESC,
2176                 .nb_min = I40E_MIN_RING_DESC,
2177                 .nb_align = I40E_ALIGN_RING_DESC,
2178         };
2179
2180         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2181                 .nb_max = I40E_MAX_RING_DESC,
2182                 .nb_min = I40E_MIN_RING_DESC,
2183                 .nb_align = I40E_ALIGN_RING_DESC,
2184         };
2185 }
2186
2187 static void
2188 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2189 {
2190         if (i40evf_get_statistics(dev, stats))
2191                 PMD_DRV_LOG(ERR, "Get statistics failed");
2192 }
2193
2194 static void
2195 i40evf_dev_close(struct rte_eth_dev *dev)
2196 {
2197         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2198         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2199         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2200
2201         i40evf_dev_stop(dev);
2202         i40e_dev_free_queues(dev);
2203         i40evf_reset_vf(hw);
2204         i40e_shutdown_adminq(hw);
2205         /* disable uio intr before callback unregister */
2206         rte_intr_disable(intr_handle);
2207
2208         /* unregister callback func from eal lib */
2209         rte_intr_callback_unregister(intr_handle,
2210                                      i40evf_dev_interrupt_handler, dev);
2211         i40evf_disable_irq0(hw);
2212 }
2213
2214 /*
2215  * Reset VF device only to re-initialize resources in PMD layer
2216  */
2217 static int
2218 i40evf_dev_reset(struct rte_eth_dev *dev)
2219 {
2220         int ret;
2221
2222         ret = i40evf_dev_uninit(dev);
2223         if (ret)
2224                 return ret;
2225
2226         ret = i40evf_dev_init(dev);
2227
2228         return ret;
2229 }
2230
2231 static int
2232 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2233 {
2234         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2235         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2236         int ret;
2237
2238         if (!lut)
2239                 return -EINVAL;
2240
2241         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2242                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2243                                           lut, lut_size);
2244                 if (ret) {
2245                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2246                         return ret;
2247                 }
2248         } else {
2249                 uint32_t *lut_dw = (uint32_t *)lut;
2250                 uint16_t i, lut_size_dw = lut_size / 4;
2251
2252                 for (i = 0; i < lut_size_dw; i++)
2253                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2254         }
2255
2256         return 0;
2257 }
2258
2259 static int
2260 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2261 {
2262         struct i40e_vf *vf;
2263         struct i40e_hw *hw;
2264         int ret;
2265
2266         if (!vsi || !lut)
2267                 return -EINVAL;
2268
2269         vf = I40E_VSI_TO_VF(vsi);
2270         hw = I40E_VSI_TO_HW(vsi);
2271
2272         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2273                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2274                                           lut, lut_size);
2275                 if (ret) {
2276                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2277                         return ret;
2278                 }
2279         } else {
2280                 uint32_t *lut_dw = (uint32_t *)lut;
2281                 uint16_t i, lut_size_dw = lut_size / 4;
2282
2283                 for (i = 0; i < lut_size_dw; i++)
2284                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2285                 I40EVF_WRITE_FLUSH(hw);
2286         }
2287
2288         return 0;
2289 }
2290
2291 static int
2292 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2293                            struct rte_eth_rss_reta_entry64 *reta_conf,
2294                            uint16_t reta_size)
2295 {
2296         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2297         uint8_t *lut;
2298         uint16_t i, idx, shift;
2299         int ret;
2300
2301         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2302                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2303                         "(%d) doesn't match the number of hardware can "
2304                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2305                 return -EINVAL;
2306         }
2307
2308         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2309         if (!lut) {
2310                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2311                 return -ENOMEM;
2312         }
2313         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2314         if (ret)
2315                 goto out;
2316         for (i = 0; i < reta_size; i++) {
2317                 idx = i / RTE_RETA_GROUP_SIZE;
2318                 shift = i % RTE_RETA_GROUP_SIZE;
2319                 if (reta_conf[idx].mask & (1ULL << shift))
2320                         lut[i] = reta_conf[idx].reta[shift];
2321         }
2322         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2323
2324 out:
2325         rte_free(lut);
2326
2327         return ret;
2328 }
2329
2330 static int
2331 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2332                           struct rte_eth_rss_reta_entry64 *reta_conf,
2333                           uint16_t reta_size)
2334 {
2335         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2336         uint16_t i, idx, shift;
2337         uint8_t *lut;
2338         int ret;
2339
2340         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2341                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2342                         "(%d) doesn't match the number of hardware can "
2343                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2344                 return -EINVAL;
2345         }
2346
2347         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2348         if (!lut) {
2349                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2350                 return -ENOMEM;
2351         }
2352
2353         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2354         if (ret)
2355                 goto out;
2356         for (i = 0; i < reta_size; i++) {
2357                 idx = i / RTE_RETA_GROUP_SIZE;
2358                 shift = i % RTE_RETA_GROUP_SIZE;
2359                 if (reta_conf[idx].mask & (1ULL << shift))
2360                         reta_conf[idx].reta[shift] = lut[i];
2361         }
2362
2363 out:
2364         rte_free(lut);
2365
2366         return ret;
2367 }
2368
2369 static int
2370 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2371 {
2372         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2373         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2374         int ret = 0;
2375
2376         if (!key || key_len == 0) {
2377                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2378                 return 0;
2379         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2380                 sizeof(uint32_t)) {
2381                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2382                 return -EINVAL;
2383         }
2384
2385         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2386                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2387                         (struct i40e_aqc_get_set_rss_key_data *)key;
2388
2389                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2390                 if (ret)
2391                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2392                                      "via AQ");
2393         } else {
2394                 uint32_t *hash_key = (uint32_t *)key;
2395                 uint16_t i;
2396
2397                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2398                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2399                 I40EVF_WRITE_FLUSH(hw);
2400         }
2401
2402         return ret;
2403 }
2404
2405 static int
2406 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2407 {
2408         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2409         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2410         int ret;
2411
2412         if (!key || !key_len)
2413                 return -EINVAL;
2414
2415         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2416                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2417                         (struct i40e_aqc_get_set_rss_key_data *)key);
2418                 if (ret) {
2419                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2420                         return ret;
2421                 }
2422         } else {
2423                 uint32_t *key_dw = (uint32_t *)key;
2424                 uint16_t i;
2425
2426                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2427                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2428         }
2429         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2430
2431         return 0;
2432 }
2433
2434 static int
2435 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2436 {
2437         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2438         uint64_t rss_hf, hena;
2439         int ret;
2440
2441         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2442                                  rss_conf->rss_key_len);
2443         if (ret)
2444                 return ret;
2445
2446         rss_hf = rss_conf->rss_hf;
2447         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2448         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2449         if (hw->mac.type == I40E_MAC_X722)
2450                 hena &= ~I40E_RSS_HENA_ALL_X722;
2451         else
2452                 hena &= ~I40E_RSS_HENA_ALL;
2453         hena |= i40e_config_hena(rss_hf, hw->mac.type);
2454         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2455         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2456         I40EVF_WRITE_FLUSH(hw);
2457
2458         return 0;
2459 }
2460
2461 static void
2462 i40evf_disable_rss(struct i40e_vf *vf)
2463 {
2464         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2465         uint64_t hena;
2466
2467         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2468         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2469         if (hw->mac.type == I40E_MAC_X722)
2470                 hena &= ~I40E_RSS_HENA_ALL_X722;
2471         else
2472                 hena &= ~I40E_RSS_HENA_ALL;
2473         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2474         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2475         I40EVF_WRITE_FLUSH(hw);
2476 }
2477
2478 static int
2479 i40evf_config_rss(struct i40e_vf *vf)
2480 {
2481         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2482         struct rte_eth_rss_conf rss_conf;
2483         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2484         uint16_t num;
2485
2486         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2487                 i40evf_disable_rss(vf);
2488                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2489                 return 0;
2490         }
2491
2492         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2493         /* Fill out the look up table */
2494         for (i = 0, j = 0; i < nb_q; i++, j++) {
2495                 if (j >= num)
2496                         j = 0;
2497                 lut = (lut << 8) | j;
2498                 if ((i & 3) == 3)
2499                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2500         }
2501
2502         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2503         if ((rss_conf.rss_hf & I40E_RSS_OFFLOAD_ALL) == 0) {
2504                 i40evf_disable_rss(vf);
2505                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2506                 return 0;
2507         }
2508
2509         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2510                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2511                 /* Calculate the default hash key */
2512                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2513                         rss_key_default[i] = (uint32_t)rte_rand();
2514                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2515                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2516                         sizeof(uint32_t);
2517         }
2518
2519         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2520 }
2521
2522 static int
2523 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2524                            struct rte_eth_rss_conf *rss_conf)
2525 {
2526         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2527         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2528         uint64_t rss_hf = rss_conf->rss_hf & I40E_RSS_OFFLOAD_ALL;
2529         uint64_t hena;
2530
2531         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2532         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2533         if (!(hena & ((hw->mac.type == I40E_MAC_X722)
2534                  ? I40E_RSS_HENA_ALL_X722
2535                  : I40E_RSS_HENA_ALL))) { /* RSS disabled */
2536                 if (rss_hf != 0) /* Enable RSS */
2537                         return -EINVAL;
2538                 return 0;
2539         }
2540
2541         /* RSS enabled */
2542         if (rss_hf == 0) /* Disable RSS */
2543                 return -EINVAL;
2544
2545         return i40evf_hw_rss_hash_set(vf, rss_conf);
2546 }
2547
2548 static int
2549 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2550                              struct rte_eth_rss_conf *rss_conf)
2551 {
2552         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2553         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2554         uint64_t hena;
2555
2556         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2557                            &rss_conf->rss_key_len);
2558
2559         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2560         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2561         rss_conf->rss_hf = i40e_parse_hena(hena);
2562
2563         return 0;
2564 }
2565
2566 static int
2567 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2568 {
2569         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2570         struct rte_eth_dev_data *dev_data = vf->dev_data;
2571         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2572         int ret = 0;
2573
2574         /* check if mtu is within the allowed range */
2575         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2576                 return -EINVAL;
2577
2578         /* mtu setting is forbidden if port is start */
2579         if (dev_data->dev_started) {
2580                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2581                             dev_data->port_id);
2582                 return -EBUSY;
2583         }
2584
2585         if (frame_size > ETHER_MAX_LEN)
2586                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2587         else
2588                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2589
2590         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2591
2592         return ret;
2593 }
2594
2595 static void
2596 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2597                             struct ether_addr *mac_addr)
2598 {
2599         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2600
2601         if (!is_valid_assigned_ether_addr(mac_addr)) {
2602                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2603                 return;
2604         }
2605
2606         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2607                 return;
2608
2609         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2610                 return;
2611
2612         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2613
2614         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2615 }