drivers/net/i40e/i40e_ethdev_vf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42 #include <rte_byteorder.h>
  43 #include <rte_common.h>
  44 #include <rte_cycles.h>
  45
  46 #include <rte_interrupts.h>
  47 #include <rte_log.h>
  48 #include <rte_debug.h>
  49 #include <rte_pci.h>
  50 #include <rte_atomic.h>
  51 #include <rte_branch_prediction.h>
  52 #include <rte_memory.h>
  53 #include <rte_memzone.h>
  54 #include <rte_eal.h>
  55 #include <rte_alarm.h>
  56 #include <rte_ether.h>
  57 #include <rte_ethdev.h>
  58 #include <rte_ethdev_pci.h>
  59 #include <rte_malloc.h>
  60 #include <rte_dev.h>
  61
  62 #include "i40e_logs.h"
  63 #include "base/i40e_prototype.h"
  64 #include "base/i40e_adminq_cmd.h"
  65 #include "base/i40e_type.h"
  66
  67 #include "i40e_rxtx.h"
  68 #include "i40e_ethdev.h"
  69 #include "i40e_pf.h"
  70 #define I40EVF_VSI_DEFAULT_MSIX_INTR     1
  71 #define I40EVF_VSI_DEFAULT_MSIX_INTR_LNX 0
  72
  73 /* busy wait delay in msec */
  74 #define I40EVF_BUSY_WAIT_DELAY 10
  75 #define I40EVF_BUSY_WAIT_COUNT 50
  76 #define MAX_RESET_WAIT_CNT     20
  77
  78 struct i40evf_arq_msg_info {
  79         enum virtchnl_ops ops;
  80         enum i40e_status_code result;
  81         uint16_t buf_len;
  82         uint16_t msg_len;
  83         uint8_t *msg;
  84 };
  85
  86 struct vf_cmd_info {
  87         enum virtchnl_ops ops;
  88         uint8_t *in_args;
  89         uint32_t in_args_size;
  90         uint8_t *out_buffer;
  91         /* Input & output type. pass in buffer size and pass out
  92          * actual return result
  93          */
  94         uint32_t out_size;
  95 };
  96
  97 enum i40evf_aq_result {
  98         I40EVF_MSG_ERR = -1, /* Meet error when accessing admin queue */
  99         I40EVF_MSG_NON,      /* Read nothing from admin queue */
 100         I40EVF_MSG_SYS,      /* Read system msg from admin queue */
 101         I40EVF_MSG_CMD,      /* Read async command result */
 102 };
 103
 104 static int i40evf_dev_configure(struct rte_eth_dev *dev);
 105 static int i40evf_dev_start(struct rte_eth_dev *dev);
 106 static void i40evf_dev_stop(struct rte_eth_dev *dev);
 107 static void i40evf_dev_info_get(struct rte_eth_dev *dev,
 108                                 struct rte_eth_dev_info *dev_info);
 109 static int i40evf_dev_link_update(struct rte_eth_dev *dev,
 110                                   int wait_to_complete);
 111 static int i40evf_dev_stats_get(struct rte_eth_dev *dev,
 112                                 struct rte_eth_stats *stats);
 113 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 114                                  struct rte_eth_xstat *xstats, unsigned n);
 115 static int i40evf_dev_xstats_get_names(struct rte_eth_dev *dev,
 116                                        struct rte_eth_xstat_name *xstats_names,
 117                                        unsigned limit);
 118 static void i40evf_dev_xstats_reset(struct rte_eth_dev *dev);
 119 static int i40evf_vlan_filter_set(struct rte_eth_dev *dev,
 120                                   uint16_t vlan_id, int on);
 121 static void i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask);
 122 static void i40evf_dev_close(struct rte_eth_dev *dev);
 123 static int  i40evf_dev_reset(struct rte_eth_dev *dev);
 124 static void i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev);
 125 static void i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev);
 126 static void i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev);
 127 static void i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev);
 128 static int i40evf_init_vlan(struct rte_eth_dev *dev);
 129 static int i40evf_dev_rx_queue_start(struct rte_eth_dev *dev,
 130                                      uint16_t rx_queue_id);
 131 static int i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev,
 132                                     uint16_t rx_queue_id);
 133 static int i40evf_dev_tx_queue_start(struct rte_eth_dev *dev,
 134                                      uint16_t tx_queue_id);
 135 static int i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev,
 136                                     uint16_t tx_queue_id);
 137 static int i40evf_add_mac_addr(struct rte_eth_dev *dev,
 138                                struct ether_addr *addr,
 139                                uint32_t index,
 140                                uint32_t pool);
 141 static void i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index);
 142 static int i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
 143                         struct rte_eth_rss_reta_entry64 *reta_conf,
 144                         uint16_t reta_size);
 145 static int i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
 146                         struct rte_eth_rss_reta_entry64 *reta_conf,
 147                         uint16_t reta_size);
 148 static int i40evf_config_rss(struct i40e_vf *vf);
 149 static int i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
 150                                       struct rte_eth_rss_conf *rss_conf);
 151 static int i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
 152                                         struct rte_eth_rss_conf *rss_conf);
 153 static int i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
 154 static void i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
 155                                         struct ether_addr *mac_addr);
 156 static int
 157 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id);
 158 static int
 159 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id);
 160 static void i40evf_handle_pf_event(struct rte_eth_dev *dev,
 161                                    uint8_t *msg,
 162                                    uint16_t msglen);
 163
 164 /* Default hash key buffer for RSS */
 165 static uint32_t rss_key_default[I40E_VFQF_HKEY_MAX_INDEX + 1];
 166
 167 struct rte_i40evf_xstats_name_off {
 168         char name[RTE_ETH_XSTATS_NAME_SIZE];
 169         unsigned offset;
 170 };
 171
 172 static const struct rte_i40evf_xstats_name_off rte_i40evf_stats_strings[] = {
 173         {"rx_bytes", offsetof(struct i40e_eth_stats, rx_bytes)},
 174         {"rx_unicast_packets", offsetof(struct i40e_eth_stats, rx_unicast)},
 175         {"rx_multicast_packets", offsetof(struct i40e_eth_stats, rx_multicast)},
 176         {"rx_broadcast_packets", offsetof(struct i40e_eth_stats, rx_broadcast)},
 177         {"rx_dropped_packets", offsetof(struct i40e_eth_stats, rx_discards)},
 178         {"rx_unknown_protocol_packets", offsetof(struct i40e_eth_stats,
 179                 rx_unknown_protocol)},
 180         {"tx_bytes", offsetof(struct i40e_eth_stats, tx_bytes)},
 181         {"tx_unicast_packets", offsetof(struct i40e_eth_stats, tx_unicast)},
 182         {"tx_multicast_packets", offsetof(struct i40e_eth_stats, tx_multicast)},
 183         {"tx_broadcast_packets", offsetof(struct i40e_eth_stats, tx_broadcast)},
 184         {"tx_dropped_packets", offsetof(struct i40e_eth_stats, tx_discards)},
 185         {"tx_error_packets", offsetof(struct i40e_eth_stats, tx_errors)},
 186 };
 187
 188 #define I40EVF_NB_XSTATS (sizeof(rte_i40evf_stats_strings) / \
 189                 sizeof(rte_i40evf_stats_strings[0]))
 190
 191 static const struct eth_dev_ops i40evf_eth_dev_ops = {
 192         .dev_configure        = i40evf_dev_configure,
 193         .dev_start            = i40evf_dev_start,
 194         .dev_stop             = i40evf_dev_stop,
 195         .promiscuous_enable   = i40evf_dev_promiscuous_enable,
 196         .promiscuous_disable  = i40evf_dev_promiscuous_disable,
 197         .allmulticast_enable  = i40evf_dev_allmulticast_enable,
 198         .allmulticast_disable = i40evf_dev_allmulticast_disable,
 199         .link_update          = i40evf_dev_link_update,
 200         .stats_get            = i40evf_dev_stats_get,
 201         .stats_reset          = i40evf_dev_xstats_reset,
 202         .xstats_get           = i40evf_dev_xstats_get,
 203         .xstats_get_names     = i40evf_dev_xstats_get_names,
 204         .xstats_reset         = i40evf_dev_xstats_reset,
 205         .dev_close            = i40evf_dev_close,
 206         .dev_reset            = i40evf_dev_reset,
 207         .dev_infos_get        = i40evf_dev_info_get,
 208         .dev_supported_ptypes_get = i40e_dev_supported_ptypes_get,
 209         .vlan_filter_set      = i40evf_vlan_filter_set,
 210         .vlan_offload_set     = i40evf_vlan_offload_set,
 211         .rx_queue_start       = i40evf_dev_rx_queue_start,
 212         .rx_queue_stop        = i40evf_dev_rx_queue_stop,
 213         .tx_queue_start       = i40evf_dev_tx_queue_start,
 214         .tx_queue_stop        = i40evf_dev_tx_queue_stop,
 215         .rx_queue_setup       = i40e_dev_rx_queue_setup,
 216         .rx_queue_release     = i40e_dev_rx_queue_release,
 217         .rx_queue_intr_enable = i40evf_dev_rx_queue_intr_enable,
 218         .rx_queue_intr_disable = i40evf_dev_rx_queue_intr_disable,
 219         .rx_descriptor_done   = i40e_dev_rx_descriptor_done,
 220         .rx_descriptor_status = i40e_dev_rx_descriptor_status,
 221         .tx_descriptor_status = i40e_dev_tx_descriptor_status,
 222         .tx_queue_setup       = i40e_dev_tx_queue_setup,
 223         .tx_queue_release     = i40e_dev_tx_queue_release,
 224         .rx_queue_count       = i40e_dev_rx_queue_count,
 225         .rxq_info_get         = i40e_rxq_info_get,
 226         .txq_info_get         = i40e_txq_info_get,
 227         .mac_addr_add         = i40evf_add_mac_addr,
 228         .mac_addr_remove      = i40evf_del_mac_addr,
 229         .reta_update          = i40evf_dev_rss_reta_update,
 230         .reta_query           = i40evf_dev_rss_reta_query,
 231         .rss_hash_update      = i40evf_dev_rss_hash_update,
 232         .rss_hash_conf_get    = i40evf_dev_rss_hash_conf_get,
 233         .mtu_set              = i40evf_dev_mtu_set,
 234         .mac_addr_set         = i40evf_set_default_mac_addr,
 235 };
 236
 237 /*
 238  * Read data in admin queue to get msg from pf driver
 239  */
 240 static enum i40evf_aq_result
 241 i40evf_read_pfmsg(struct rte_eth_dev *dev, struct i40evf_arq_msg_info *data)
 242 {
 243         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 244         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 245         struct i40e_arq_event_info event;
 246         enum virtchnl_ops opcode;
 247         enum i40e_status_code retval;
 248         int ret;
 249         enum i40evf_aq_result result = I40EVF_MSG_NON;
 250
 251         event.buf_len = data->buf_len;
 252         event.msg_buf = data->msg;
 253         ret = i40e_clean_arq_element(hw, &event, NULL);
 254         /* Can't read any msg from adminQ */
 255         if (ret) {
 256                 if (ret != I40E_ERR_ADMIN_QUEUE_NO_WORK)
 257                         result = I40EVF_MSG_ERR;
 258                 return result;
 259         }
 260
 261         opcode = (enum virtchnl_ops)rte_le_to_cpu_32(event.desc.cookie_high);
 262         retval = (enum i40e_status_code)rte_le_to_cpu_32(event.desc.cookie_low);
 263         /* pf sys event */
 264         if (opcode == VIRTCHNL_OP_EVENT) {
 265                 struct virtchnl_pf_event *vpe =
 266                         (struct virtchnl_pf_event *)event.msg_buf;
 267
 268                 result = I40EVF_MSG_SYS;
 269                 switch (vpe->event) {
 270                 case VIRTCHNL_EVENT_LINK_CHANGE:
 271                         vf->link_up =
 272                                 vpe->event_data.link_event.link_status;
 273                         vf->link_speed =
 274                                 vpe->event_data.link_event.link_speed;
 275                         vf->pend_msg |= PFMSG_LINK_CHANGE;
 276                         PMD_DRV_LOG(INFO, "Link status update:%s",
 277                                     vf->link_up ? "up" : "down");
 278                         break;
 279                 case VIRTCHNL_EVENT_RESET_IMPENDING:
 280                         vf->vf_reset = true;
 281                         vf->pend_msg |= PFMSG_RESET_IMPENDING;
 282                         PMD_DRV_LOG(INFO, "vf is reseting");
 283                         break;
 284                 case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
 285                         vf->dev_closed = true;
 286                         vf->pend_msg |= PFMSG_DRIVER_CLOSE;
 287                         PMD_DRV_LOG(INFO, "PF driver closed");
 288                         break;
 289                 default:
 290                         PMD_DRV_LOG(ERR, "%s: Unknown event %d from pf",
 291                                     __func__, vpe->event);
 292                 }
 293         } else {
 294                 /* async reply msg on command issued by vf previously */
 295                 result = I40EVF_MSG_CMD;
 296                 /* Actual data length read from PF */
 297                 data->msg_len = event.msg_len;
 298         }
 299
 300         data->result = retval;
 301         data->ops = opcode;
 302
 303         return result;
 304 }
 305
 306 /**
 307  * clear current command. Only call in case execute
 308  * _atomic_set_cmd successfully.
 309  */
 310 static inline void
 311 _clear_cmd(struct i40e_vf *vf)
 312 {
 313         rte_wmb();
 314         vf->pend_cmd = VIRTCHNL_OP_UNKNOWN;
 315 }
 316
 317 /*
 318  * Check there is pending cmd in execution. If none, set new command.
 319  */
 320 static inline int
 321 _atomic_set_cmd(struct i40e_vf *vf, enum virtchnl_ops ops)
 322 {
 323         int ret = rte_atomic32_cmpset(&vf->pend_cmd,
 324                         VIRTCHNL_OP_UNKNOWN, ops);
 325
 326         if (!ret)
 327                 PMD_DRV_LOG(ERR, "There is incomplete cmd %d", vf->pend_cmd);
 328
 329         return !ret;
 330 }
 331
 332 #define MAX_TRY_TIMES 200
 333 #define ASQ_DELAY_MS  10
 334
 335 static int
 336 i40evf_execute_vf_cmd(struct rte_eth_dev *dev, struct vf_cmd_info *args)
 337 {
 338         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 339         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 340         struct i40evf_arq_msg_info info;
 341         enum i40evf_aq_result ret;
 342         int err, i = 0;
 343
 344         if (_atomic_set_cmd(vf, args->ops))
 345                 return -1;
 346
 347         info.msg = args->out_buffer;
 348         info.buf_len = args->out_size;
 349         info.ops = VIRTCHNL_OP_UNKNOWN;
 350         info.result = I40E_SUCCESS;
 351
 352         err = i40e_aq_send_msg_to_pf(hw, args->ops, I40E_SUCCESS,
 353                      args->in_args, args->in_args_size, NULL);
 354         if (err) {
 355                 PMD_DRV_LOG(ERR, "fail to send cmd %d", args->ops);
 356                 _clear_cmd(vf);
 357                 return err;
 358         }
 359
 360         switch (args->ops) {
 361         case VIRTCHNL_OP_RESET_VF:
 362                 /*no need to process in this function */
 363                 err = 0;
 364                 break;
 365         case VIRTCHNL_OP_VERSION:
 366         case VIRTCHNL_OP_GET_VF_RESOURCES:
 367                 /* for init adminq commands, need to poll the response */
 368                 err = -1;
 369                 do {
 370                         ret = i40evf_read_pfmsg(dev, &info);
 371                         vf->cmd_retval = info.result;
 372                         if (ret == I40EVF_MSG_CMD) {
 373                                 err = 0;
 374                                 break;
 375                         } else if (ret == I40EVF_MSG_ERR)
 376                                 break;
 377                         rte_delay_ms(ASQ_DELAY_MS);
 378                         /* If don't read msg or read sys event, continue */
 379                 } while (i++ < MAX_TRY_TIMES);
 380                 _clear_cmd(vf);
 381                 break;
 382
 383         default:
 384                 /* for other adminq in running time, waiting the cmd done flag */
 385                 err = -1;
 386                 do {
 387                         if (vf->pend_cmd == VIRTCHNL_OP_UNKNOWN) {
 388                                 err = 0;
 389                                 break;
 390                         }
 391                         rte_delay_ms(ASQ_DELAY_MS);
 392                         /* If don't read msg or read sys event, continue */
 393                 } while (i++ < MAX_TRY_TIMES);
 394                 /* If there's no response is received, clear command */
 395                 if (i >= MAX_TRY_TIMES) {
 396                         PMD_DRV_LOG(WARNING, "No response for %d", args->ops);
 397                         _clear_cmd(vf);
 398                 }
 399                 break;
 400         }
 401
 402         return err | vf->cmd_retval;
 403 }
 404
 405 /*
 406  * Check API version with sync wait until version read or fail from admin queue
 407  */
 408 static int
 409 i40evf_check_api_version(struct rte_eth_dev *dev)
 410 {
 411         struct virtchnl_version_info version, *pver;
 412         int err;
 413         struct vf_cmd_info args;
 414         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 415
 416         version.major = VIRTCHNL_VERSION_MAJOR;
 417         version.minor = VIRTCHNL_VERSION_MINOR;
 418
 419         args.ops = VIRTCHNL_OP_VERSION;
 420         args.in_args = (uint8_t *)&version;
 421         args.in_args_size = sizeof(version);
 422         args.out_buffer = vf->aq_resp;
 423         args.out_size = I40E_AQ_BUF_SZ;
 424
 425         err = i40evf_execute_vf_cmd(dev, &args);
 426         if (err) {
 427                 PMD_INIT_LOG(ERR, "fail to execute command OP_VERSION");
 428                 return err;
 429         }
 430
 431         pver = (struct virtchnl_version_info *)args.out_buffer;
 432         vf->version_major = pver->major;
 433         vf->version_minor = pver->minor;
 434         if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
 435                 (vf->version_minor <= VIRTCHNL_VERSION_MINOR))
 436                 PMD_DRV_LOG(INFO, "Peer is Linux PF host");
 437         else {
 438                 PMD_INIT_LOG(ERR, "PF/VF API version mismatch:(%u.%u)-(%u.%u)",
 439                                         vf->version_major, vf->version_minor,
 440                                                 VIRTCHNL_VERSION_MAJOR,
 441                                                 VIRTCHNL_VERSION_MINOR);
 442                 return -1;
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int
 449 i40evf_get_vf_resource(struct rte_eth_dev *dev)
 450 {
 451         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 452         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 453         int err;
 454         struct vf_cmd_info args;
 455         uint32_t caps, len;
 456
 457         args.ops = VIRTCHNL_OP_GET_VF_RESOURCES;
 458         args.out_buffer = vf->aq_resp;
 459         args.out_size = I40E_AQ_BUF_SZ;
 460         if (PF_IS_V11(vf)) {
 461                 caps = VIRTCHNL_VF_OFFLOAD_L2 |
 462                        VIRTCHNL_VF_OFFLOAD_RSS_AQ |
 463                        VIRTCHNL_VF_OFFLOAD_RSS_REG |
 464                        VIRTCHNL_VF_OFFLOAD_VLAN |
 465                        VIRTCHNL_VF_OFFLOAD_RX_POLLING;
 466                 args.in_args = (uint8_t *)&caps;
 467                 args.in_args_size = sizeof(caps);
 468         } else {
 469                 args.in_args = NULL;
 470                 args.in_args_size = 0;
 471         }
 472         err = i40evf_execute_vf_cmd(dev, &args);
 473
 474         if (err) {
 475                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_VF_RESOURCE");
 476                 return err;
 477         }
 478
 479         len =  sizeof(struct virtchnl_vf_resource) +
 480                 I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource);
 481
 482         rte_memcpy(vf->vf_res, args.out_buffer,
 483                         RTE_MIN(args.out_size, len));
 484         i40e_vf_parse_hw_config(hw, vf->vf_res);
 485
 486         return 0;
 487 }
 488
 489 static int
 490 i40evf_config_promisc(struct rte_eth_dev *dev,
 491                       bool enable_unicast,
 492                       bool enable_multicast)
 493 {
 494         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 495         int err;
 496         struct vf_cmd_info args;
 497         struct virtchnl_promisc_info promisc;
 498
 499         promisc.flags = 0;
 500         promisc.vsi_id = vf->vsi_res->vsi_id;
 501
 502         if (enable_unicast)
 503                 promisc.flags |= FLAG_VF_UNICAST_PROMISC;
 504
 505         if (enable_multicast)
 506                 promisc.flags |= FLAG_VF_MULTICAST_PROMISC;
 507
 508         args.ops = VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE;
 509         args.in_args = (uint8_t *)&promisc;
 510         args.in_args_size = sizeof(promisc);
 511         args.out_buffer = vf->aq_resp;
 512         args.out_size = I40E_AQ_BUF_SZ;
 513
 514         err = i40evf_execute_vf_cmd(dev, &args);
 515
 516         if (err)
 517                 PMD_DRV_LOG(ERR, "fail to execute command "
 518                             "CONFIG_PROMISCUOUS_MODE");
 519         return err;
 520 }
 521
 522 static int
 523 i40evf_enable_vlan_strip(struct rte_eth_dev *dev)
 524 {
 525         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 526         struct vf_cmd_info args;
 527         int ret;
 528
 529         memset(&args, 0, sizeof(args));
 530         args.ops = VIRTCHNL_OP_ENABLE_VLAN_STRIPPING;
 531         args.in_args = NULL;
 532         args.in_args_size = 0;
 533         args.out_buffer = vf->aq_resp;
 534         args.out_size = I40E_AQ_BUF_SZ;
 535         ret = i40evf_execute_vf_cmd(dev, &args);
 536         if (ret)
 537                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 538                             "VIRTCHNL_OP_ENABLE_VLAN_STRIPPING");
 539
 540         return ret;
 541 }
 542
 543 static int
 544 i40evf_disable_vlan_strip(struct rte_eth_dev *dev)
 545 {
 546         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 547         struct vf_cmd_info args;
 548         int ret;
 549
 550         memset(&args, 0, sizeof(args));
 551         args.ops = VIRTCHNL_OP_DISABLE_VLAN_STRIPPING;
 552         args.in_args = NULL;
 553         args.in_args_size = 0;
 554         args.out_buffer = vf->aq_resp;
 555         args.out_size = I40E_AQ_BUF_SZ;
 556         ret = i40evf_execute_vf_cmd(dev, &args);
 557         if (ret)
 558                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 559                             "VIRTCHNL_OP_DISABLE_VLAN_STRIPPING");
 560
 561         return ret;
 562 }
 563
 564 static void
 565 i40evf_fill_virtchnl_vsi_txq_info(struct virtchnl_txq_info *txq_info,
 566                                   uint16_t vsi_id,
 567                                   uint16_t queue_id,
 568                                   uint16_t nb_txq,
 569                                   struct i40e_tx_queue *txq)
 570 {
 571         txq_info->vsi_id = vsi_id;
 572         txq_info->queue_id = queue_id;
 573         if (queue_id < nb_txq) {
 574                 txq_info->ring_len = txq->nb_tx_desc;
 575                 txq_info->dma_ring_addr = txq->tx_ring_phys_addr;
 576         }
 577 }
 578
 579 static void
 580 i40evf_fill_virtchnl_vsi_rxq_info(struct virtchnl_rxq_info *rxq_info,
 581                                   uint16_t vsi_id,
 582                                   uint16_t queue_id,
 583                                   uint16_t nb_rxq,
 584                                   uint32_t max_pkt_size,
 585                                   struct i40e_rx_queue *rxq)
 586 {
 587         rxq_info->vsi_id = vsi_id;
 588         rxq_info->queue_id = queue_id;
 589         rxq_info->max_pkt_size = max_pkt_size;
 590         if (queue_id < nb_rxq) {
 591                 rxq_info->ring_len = rxq->nb_rx_desc;
 592                 rxq_info->dma_ring_addr = rxq->rx_ring_phys_addr;
 593                 rxq_info->databuffer_size =
 594                         (rte_pktmbuf_data_room_size(rxq->mp) -
 595                                 RTE_PKTMBUF_HEADROOM);
 596         }
 597 }
 598
 599 static int
 600 i40evf_configure_vsi_queues(struct rte_eth_dev *dev)
 601 {
 602         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 603         struct i40e_rx_queue **rxq =
 604                 (struct i40e_rx_queue **)dev->data->rx_queues;
 605         struct i40e_tx_queue **txq =
 606                 (struct i40e_tx_queue **)dev->data->tx_queues;
 607         struct virtchnl_vsi_queue_config_info *vc_vqci;
 608         struct virtchnl_queue_pair_info *vc_qpi;
 609         struct vf_cmd_info args;
 610         uint16_t i, nb_qp = vf->num_queue_pairs;
 611         const uint32_t size =
 612                 I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci, nb_qp);
 613         uint8_t buff[size];
 614         int ret;
 615
 616         memset(buff, 0, sizeof(buff));
 617         vc_vqci = (struct virtchnl_vsi_queue_config_info *)buff;
 618         vc_vqci->vsi_id = vf->vsi_res->vsi_id;
 619         vc_vqci->num_queue_pairs = nb_qp;
 620
 621         for (i = 0, vc_qpi = vc_vqci->qpair; i < nb_qp; i++, vc_qpi++) {
 622                 i40evf_fill_virtchnl_vsi_txq_info(&vc_qpi->txq,
 623                         vc_vqci->vsi_id, i, dev->data->nb_tx_queues, txq[i]);
 624                 i40evf_fill_virtchnl_vsi_rxq_info(&vc_qpi->rxq,
 625                         vc_vqci->vsi_id, i, dev->data->nb_rx_queues,
 626                                         vf->max_pkt_len, rxq[i]);
 627         }
 628         memset(&args, 0, sizeof(args));
 629         args.ops = VIRTCHNL_OP_CONFIG_VSI_QUEUES;
 630         args.in_args = (uint8_t *)vc_vqci;
 631         args.in_args_size = size;
 632         args.out_buffer = vf->aq_resp;
 633         args.out_size = I40E_AQ_BUF_SZ;
 634         ret = i40evf_execute_vf_cmd(dev, &args);
 635         if (ret)
 636                 PMD_DRV_LOG(ERR, "Failed to execute command of "
 637                         "VIRTCHNL_OP_CONFIG_VSI_QUEUES");
 638
 639         return ret;
 640 }
 641
 642 static int
 643 i40evf_config_irq_map(struct rte_eth_dev *dev)
 644 {
 645         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 646         struct vf_cmd_info args;
 647         uint8_t cmd_buffer[sizeof(struct virtchnl_irq_map_info) + \
 648                 sizeof(struct virtchnl_vector_map)];
 649         struct virtchnl_irq_map_info *map_info;
 650         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
 651         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
 652         uint32_t vector_id;
 653         int i, err;
 654
 655         if (rte_intr_allow_others(intr_handle))
 656                 vector_id = I40EVF_VSI_DEFAULT_MSIX_INTR_LNX;
 657         else
 658                 vector_id = I40E_MISC_VEC_ID;
 659
 660         map_info = (struct virtchnl_irq_map_info *)cmd_buffer;
 661         map_info->num_vectors = 1;
 662         map_info->vecmap[0].rxitr_idx = I40E_ITR_INDEX_DEFAULT;
 663         map_info->vecmap[0].vsi_id = vf->vsi_res->vsi_id;
 664         /* Alway use default dynamic MSIX interrupt */
 665         map_info->vecmap[0].vector_id = vector_id;
 666         /* Don't map any tx queue */
 667         map_info->vecmap[0].txq_map = 0;
 668         map_info->vecmap[0].rxq_map = 0;
 669         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 670                 map_info->vecmap[0].rxq_map |= 1 << i;
 671                 if (rte_intr_dp_is_en(intr_handle))
 672                         intr_handle->intr_vec[i] = vector_id;
 673         }
 674
 675         args.ops = VIRTCHNL_OP_CONFIG_IRQ_MAP;
 676         args.in_args = (u8 *)cmd_buffer;
 677         args.in_args_size = sizeof(cmd_buffer);
 678         args.out_buffer = vf->aq_resp;
 679         args.out_size = I40E_AQ_BUF_SZ;
 680         err = i40evf_execute_vf_cmd(dev, &args);
 681         if (err)
 682                 PMD_DRV_LOG(ERR, "fail to execute command OP_ENABLE_QUEUES");
 683
 684         return err;
 685 }
 686
 687 static int
 688 i40evf_switch_queue(struct rte_eth_dev *dev, bool isrx, uint16_t qid,
 689                                 bool on)
 690 {
 691         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 692         struct virtchnl_queue_select queue_select;
 693         int err;
 694         struct vf_cmd_info args;
 695         memset(&queue_select, 0, sizeof(queue_select));
 696         queue_select.vsi_id = vf->vsi_res->vsi_id;
 697
 698         if (isrx)
 699                 queue_select.rx_queues |= 1 << qid;
 700         else
 701                 queue_select.tx_queues |= 1 << qid;
 702
 703         if (on)
 704                 args.ops = VIRTCHNL_OP_ENABLE_QUEUES;
 705         else
 706                 args.ops = VIRTCHNL_OP_DISABLE_QUEUES;
 707         args.in_args = (u8 *)&queue_select;
 708         args.in_args_size = sizeof(queue_select);
 709         args.out_buffer = vf->aq_resp;
 710         args.out_size = I40E_AQ_BUF_SZ;
 711         err = i40evf_execute_vf_cmd(dev, &args);
 712         if (err)
 713                 PMD_DRV_LOG(ERR, "fail to switch %s %u %s",
 714                             isrx ? "RX" : "TX", qid, on ? "on" : "off");
 715
 716         return err;
 717 }
 718
 719 static int
 720 i40evf_start_queues(struct rte_eth_dev *dev)
 721 {
 722         struct rte_eth_dev_data *dev_data = dev->data;
 723         int i;
 724         struct i40e_rx_queue *rxq;
 725         struct i40e_tx_queue *txq;
 726
 727         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 728                 rxq = dev_data->rx_queues[i];
 729                 if (rxq->rx_deferred_start)
 730                         continue;
 731                 if (i40evf_dev_rx_queue_start(dev, i) != 0) {
 732                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 733                         return -1;
 734                 }
 735         }
 736
 737         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 738                 txq = dev_data->tx_queues[i];
 739                 if (txq->tx_deferred_start)
 740                         continue;
 741                 if (i40evf_dev_tx_queue_start(dev, i) != 0) {
 742                         PMD_DRV_LOG(ERR, "Fail to start queue %u", i);
 743                         return -1;
 744                 }
 745         }
 746
 747         return 0;
 748 }
 749
 750 static int
 751 i40evf_stop_queues(struct rte_eth_dev *dev)
 752 {
 753         int i;
 754
 755         /* Stop TX queues first */
 756         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 757                 if (i40evf_dev_tx_queue_stop(dev, i) != 0) {
 758                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 759                         return -1;
 760                 }
 761         }
 762
 763         /* Then stop RX queues */
 764         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 765                 if (i40evf_dev_rx_queue_stop(dev, i) != 0) {
 766                         PMD_DRV_LOG(ERR, "Fail to stop queue %u", i);
 767                         return -1;
 768                 }
 769         }
 770
 771         return 0;
 772 }
 773
 774 static int
 775 i40evf_add_mac_addr(struct rte_eth_dev *dev,
 776                     struct ether_addr *addr,
 777                     __rte_unused uint32_t index,
 778                     __rte_unused uint32_t pool)
 779 {
 780         struct virtchnl_ether_addr_list *list;
 781         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 782         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 783                         sizeof(struct virtchnl_ether_addr)];
 784         int err;
 785         struct vf_cmd_info args;
 786
 787         if (is_zero_ether_addr(addr)) {
 788                 PMD_DRV_LOG(ERR, "Invalid mac:%x:%x:%x:%x:%x:%x",
 789                             addr->addr_bytes[0], addr->addr_bytes[1],
 790                             addr->addr_bytes[2], addr->addr_bytes[3],
 791                             addr->addr_bytes[4], addr->addr_bytes[5]);
 792                 return I40E_ERR_INVALID_MAC_ADDR;
 793         }
 794
 795         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 796         list->vsi_id = vf->vsi_res->vsi_id;
 797         list->num_elements = 1;
 798         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 799                                         sizeof(addr->addr_bytes));
 800
 801         args.ops = VIRTCHNL_OP_ADD_ETH_ADDR;
 802         args.in_args = cmd_buffer;
 803         args.in_args_size = sizeof(cmd_buffer);
 804         args.out_buffer = vf->aq_resp;
 805         args.out_size = I40E_AQ_BUF_SZ;
 806         err = i40evf_execute_vf_cmd(dev, &args);
 807         if (err)
 808                 PMD_DRV_LOG(ERR, "fail to execute command "
 809                             "OP_ADD_ETHER_ADDRESS");
 810         else
 811                 vf->vsi.mac_num++;
 812
 813         return err;
 814 }
 815
 816 static void
 817 i40evf_del_mac_addr_by_addr(struct rte_eth_dev *dev,
 818                             struct ether_addr *addr)
 819 {
 820         struct virtchnl_ether_addr_list *list;
 821         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 822         uint8_t cmd_buffer[sizeof(struct virtchnl_ether_addr_list) + \
 823                         sizeof(struct virtchnl_ether_addr)];
 824         int err;
 825         struct vf_cmd_info args;
 826
 827         if (i40e_validate_mac_addr(addr->addr_bytes) != I40E_SUCCESS) {
 828                 PMD_DRV_LOG(ERR, "Invalid mac:%x-%x-%x-%x-%x-%x",
 829                             addr->addr_bytes[0], addr->addr_bytes[1],
 830                             addr->addr_bytes[2], addr->addr_bytes[3],
 831                             addr->addr_bytes[4], addr->addr_bytes[5]);
 832                 return;
 833         }
 834
 835         list = (struct virtchnl_ether_addr_list *)cmd_buffer;
 836         list->vsi_id = vf->vsi_res->vsi_id;
 837         list->num_elements = 1;
 838         rte_memcpy(list->list[0].addr, addr->addr_bytes,
 839                         sizeof(addr->addr_bytes));
 840
 841         args.ops = VIRTCHNL_OP_DEL_ETH_ADDR;
 842         args.in_args = cmd_buffer;
 843         args.in_args_size = sizeof(cmd_buffer);
 844         args.out_buffer = vf->aq_resp;
 845         args.out_size = I40E_AQ_BUF_SZ;
 846         err = i40evf_execute_vf_cmd(dev, &args);
 847         if (err)
 848                 PMD_DRV_LOG(ERR, "fail to execute command "
 849                             "OP_DEL_ETHER_ADDRESS");
 850         else
 851                 vf->vsi.mac_num--;
 852         return;
 853 }
 854
 855 static void
 856 i40evf_del_mac_addr(struct rte_eth_dev *dev, uint32_t index)
 857 {
 858         struct rte_eth_dev_data *data = dev->data;
 859         struct ether_addr *addr;
 860
 861         addr = &data->mac_addrs[index];
 862
 863         i40evf_del_mac_addr_by_addr(dev, addr);
 864 }
 865
 866 static int
 867 i40evf_query_stats(struct rte_eth_dev *dev, struct i40e_eth_stats **pstats)
 868 {
 869         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 870         struct virtchnl_queue_select q_stats;
 871         int err;
 872         struct vf_cmd_info args;
 873
 874         memset(&q_stats, 0, sizeof(q_stats));
 875         q_stats.vsi_id = vf->vsi_res->vsi_id;
 876         args.ops = VIRTCHNL_OP_GET_STATS;
 877         args.in_args = (u8 *)&q_stats;
 878         args.in_args_size = sizeof(q_stats);
 879         args.out_buffer = vf->aq_resp;
 880         args.out_size = I40E_AQ_BUF_SZ;
 881
 882         err = i40evf_execute_vf_cmd(dev, &args);
 883         if (err) {
 884                 PMD_DRV_LOG(ERR, "fail to execute command OP_GET_STATS");
 885                 *pstats = NULL;
 886                 return err;
 887         }
 888         *pstats = (struct i40e_eth_stats *)args.out_buffer;
 889         return 0;
 890 }
 891
 892 static void
 893 i40evf_stat_update_48(uint64_t *offset,
 894                    uint64_t *stat)
 895 {
 896         if (*stat >= *offset)
 897                 *stat = *stat - *offset;
 898         else
 899                 *stat = (uint64_t)((*stat +
 900                         ((uint64_t)1 << I40E_48_BIT_WIDTH)) - *offset);
 901
 902         *stat &= I40E_48_BIT_MASK;
 903 }
 904
 905 static void
 906 i40evf_stat_update_32(uint64_t *offset,
 907                    uint64_t *stat)
 908 {
 909         if (*stat >= *offset)
 910                 *stat = (uint64_t)(*stat - *offset);
 911         else
 912                 *stat = (uint64_t)((*stat +
 913                         ((uint64_t)1 << I40E_32_BIT_WIDTH)) - *offset);
 914 }
 915
 916 static void
 917 i40evf_update_stats(struct i40e_vsi *vsi,
 918                                         struct i40e_eth_stats *nes)
 919 {
 920         struct i40e_eth_stats *oes = &vsi->eth_stats_offset;
 921
 922         i40evf_stat_update_48(&oes->rx_bytes,
 923                             &nes->rx_bytes);
 924         i40evf_stat_update_48(&oes->rx_unicast,
 925                             &nes->rx_unicast);
 926         i40evf_stat_update_48(&oes->rx_multicast,
 927                             &nes->rx_multicast);
 928         i40evf_stat_update_48(&oes->rx_broadcast,
 929                             &nes->rx_broadcast);
 930         i40evf_stat_update_32(&oes->rx_discards,
 931                                 &nes->rx_discards);
 932         i40evf_stat_update_32(&oes->rx_unknown_protocol,
 933                             &nes->rx_unknown_protocol);
 934         i40evf_stat_update_48(&oes->tx_bytes,
 935                             &nes->tx_bytes);
 936         i40evf_stat_update_48(&oes->tx_unicast,
 937                             &nes->tx_unicast);
 938         i40evf_stat_update_48(&oes->tx_multicast,
 939                             &nes->tx_multicast);
 940         i40evf_stat_update_48(&oes->tx_broadcast,
 941                             &nes->tx_broadcast);
 942         i40evf_stat_update_32(&oes->tx_errors, &nes->tx_errors);
 943         i40evf_stat_update_32(&oes->tx_discards, &nes->tx_discards);
 944 }
 945
 946 static void
 947 i40evf_dev_xstats_reset(struct rte_eth_dev *dev)
 948 {
 949         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 950         struct i40e_eth_stats *pstats = NULL;
 951
 952         /* read stat values to clear hardware registers */
 953         i40evf_query_stats(dev, &pstats);
 954
 955         /* set stats offset base on current values */
 956         vf->vsi.eth_stats_offset = *pstats;
 957 }
 958
 959 static int i40evf_dev_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
 960                                       struct rte_eth_xstat_name *xstats_names,
 961                                       __rte_unused unsigned limit)
 962 {
 963         unsigned i;
 964
 965         if (xstats_names != NULL)
 966                 for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 967                         snprintf(xstats_names[i].name,
 968                                 sizeof(xstats_names[i].name),
 969                                 "%s", rte_i40evf_stats_strings[i].name);
 970                 }
 971         return I40EVF_NB_XSTATS;
 972 }
 973
 974 static int i40evf_dev_xstats_get(struct rte_eth_dev *dev,
 975                                  struct rte_eth_xstat *xstats, unsigned n)
 976 {
 977         int ret;
 978         unsigned i;
 979         struct i40e_eth_stats *pstats = NULL;
 980         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 981         struct i40e_vsi *vsi = &vf->vsi;
 982
 983         if (n < I40EVF_NB_XSTATS)
 984                 return I40EVF_NB_XSTATS;
 985
 986         ret = i40evf_query_stats(dev, &pstats);
 987         if (ret != 0)
 988                 return 0;
 989
 990         if (!xstats)
 991                 return 0;
 992
 993         i40evf_update_stats(vsi, pstats);
 994
 995         /* loop over xstats array and values from pstats */
 996         for (i = 0; i < I40EVF_NB_XSTATS; i++) {
 997                 xstats[i].id = i;
 998                 xstats[i].value = *(uint64_t *)(((char *)pstats) +
 999                         rte_i40evf_stats_strings[i].offset);
1000         }
1001
1002         return I40EVF_NB_XSTATS;
1003 }
1004
1005 static int
1006 i40evf_add_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1007 {
1008         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1009         struct virtchnl_vlan_filter_list *vlan_list;
1010         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1011                                                         sizeof(uint16_t)];
1012         int err;
1013         struct vf_cmd_info args;
1014
1015         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1016         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1017         vlan_list->num_elements = 1;
1018         vlan_list->vlan_id[0] = vlanid;
1019
1020         args.ops = VIRTCHNL_OP_ADD_VLAN;
1021         args.in_args = (u8 *)&cmd_buffer;
1022         args.in_args_size = sizeof(cmd_buffer);
1023         args.out_buffer = vf->aq_resp;
1024         args.out_size = I40E_AQ_BUF_SZ;
1025         err = i40evf_execute_vf_cmd(dev, &args);
1026         if (err)
1027                 PMD_DRV_LOG(ERR, "fail to execute command OP_ADD_VLAN");
1028
1029         return err;
1030 }
1031
1032 static int
1033 i40evf_del_vlan(struct rte_eth_dev *dev, uint16_t vlanid)
1034 {
1035         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1036         struct virtchnl_vlan_filter_list *vlan_list;
1037         uint8_t cmd_buffer[sizeof(struct virtchnl_vlan_filter_list) +
1038                                                         sizeof(uint16_t)];
1039         int err;
1040         struct vf_cmd_info args;
1041
1042         vlan_list = (struct virtchnl_vlan_filter_list *)cmd_buffer;
1043         vlan_list->vsi_id = vf->vsi_res->vsi_id;
1044         vlan_list->num_elements = 1;
1045         vlan_list->vlan_id[0] = vlanid;
1046
1047         args.ops = VIRTCHNL_OP_DEL_VLAN;
1048         args.in_args = (u8 *)&cmd_buffer;
1049         args.in_args_size = sizeof(cmd_buffer);
1050         args.out_buffer = vf->aq_resp;
1051         args.out_size = I40E_AQ_BUF_SZ;
1052         err = i40evf_execute_vf_cmd(dev, &args);
1053         if (err)
1054                 PMD_DRV_LOG(ERR, "fail to execute command OP_DEL_VLAN");
1055
1056         return err;
1057 }
1058
1059 static const struct rte_pci_id pci_id_i40evf_map[] = {
1060         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF) },
1061         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_VF_HV) },
1062         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_A0_VF) },
1063         { RTE_PCI_DEVICE(I40E_INTEL_VENDOR_ID, I40E_DEV_ID_X722_VF) },
1064         { .vendor_id = 0, /* sentinel */ },
1065 };
1066
1067 static inline int
1068 i40evf_dev_atomic_write_link_status(struct rte_eth_dev *dev,
1069                                     struct rte_eth_link *link)
1070 {
1071         struct rte_eth_link *dst = &(dev->data->dev_link);
1072         struct rte_eth_link *src = link;
1073
1074         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
1075                                         *(uint64_t *)src) == 0)
1076                 return -1;
1077
1078         return 0;
1079 }
1080
1081 /* Disable IRQ0 */
1082 static inline void
1083 i40evf_disable_irq0(struct i40e_hw *hw)
1084 {
1085         /* Disable all interrupt types */
1086         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, 0);
1087         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1088                        I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1089         I40EVF_WRITE_FLUSH(hw);
1090 }
1091
1092 /* Enable IRQ0 */
1093 static inline void
1094 i40evf_enable_irq0(struct i40e_hw *hw)
1095 {
1096         /* Enable admin queue interrupt trigger */
1097         uint32_t val;
1098
1099         i40evf_disable_irq0(hw);
1100         val = I40E_READ_REG(hw, I40E_VFINT_ICR0_ENA1);
1101         val |= I40E_VFINT_ICR0_ENA1_ADMINQ_MASK |
1102                 I40E_VFINT_ICR0_ENA1_LINK_STAT_CHANGE_MASK;
1103         I40E_WRITE_REG(hw, I40E_VFINT_ICR0_ENA1, val);
1104
1105         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1106                 I40E_VFINT_DYN_CTL01_INTENA_MASK |
1107                 I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1108                 I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1109
1110         I40EVF_WRITE_FLUSH(hw);
1111 }
1112
1113 static int
1114 i40evf_reset_vf(struct i40e_hw *hw)
1115 {
1116         int i, reset;
1117
1118         if (i40e_vf_reset(hw) != I40E_SUCCESS) {
1119                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1120                 return -1;
1121         }
1122         /**
1123           * After issuing vf reset command to pf, pf won't necessarily
1124           * reset vf, it depends on what state it exactly is. If it's not
1125           * initialized yet, it won't have vf reset since it's in a certain
1126           * state. If not, it will try to reset. Even vf is reset, pf will
1127           * set I40E_VFGEN_RSTAT to COMPLETE first, then wait 10ms and set
1128           * it to ACTIVE. In this duration, vf may not catch the moment that
1129           * COMPLETE is set. So, for vf, we'll try to wait a long time.
1130           */
1131         rte_delay_ms(200);
1132
1133         for (i = 0; i < MAX_RESET_WAIT_CNT; i++) {
1134                 reset = rd32(hw, I40E_VFGEN_RSTAT) &
1135                         I40E_VFGEN_RSTAT_VFR_STATE_MASK;
1136                 reset = reset >> I40E_VFGEN_RSTAT_VFR_STATE_SHIFT;
1137                 if (VIRTCHNL_VFR_COMPLETED == reset || VIRTCHNL_VFR_VFACTIVE == reset)
1138                         break;
1139                 else
1140                         rte_delay_ms(50);
1141         }
1142
1143         if (i >= MAX_RESET_WAIT_CNT) {
1144                 PMD_INIT_LOG(ERR, "Reset VF NIC failed");
1145                 return -1;
1146         }
1147
1148         return 0;
1149 }
1150
1151 static int
1152 i40evf_init_vf(struct rte_eth_dev *dev)
1153 {
1154         int i, err, bufsz;
1155         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1156         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1157         uint16_t interval =
1158                 i40e_calc_itr_interval(I40E_QUEUE_ITR_INTERVAL_MAX);
1159
1160         vf->adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1161         vf->dev_data = dev->data;
1162         err = i40e_set_mac_type(hw);
1163         if (err) {
1164                 PMD_INIT_LOG(ERR, "set_mac_type failed: %d", err);
1165                 goto err;
1166         }
1167
1168         i40e_init_adminq_parameter(hw);
1169         err = i40e_init_adminq(hw);
1170         if (err) {
1171                 PMD_INIT_LOG(ERR, "init_adminq failed: %d", err);
1172                 goto err;
1173         }
1174
1175         /* Reset VF and wait until it's complete */
1176         if (i40evf_reset_vf(hw)) {
1177                 PMD_INIT_LOG(ERR, "reset NIC failed");
1178                 goto err_aq;
1179         }
1180
1181         /* VF reset, shutdown admin queue and initialize again */
1182         if (i40e_shutdown_adminq(hw) != I40E_SUCCESS) {
1183                 PMD_INIT_LOG(ERR, "i40e_shutdown_adminq failed");
1184                 goto err;
1185         }
1186
1187         i40e_init_adminq_parameter(hw);
1188         if (i40e_init_adminq(hw) != I40E_SUCCESS) {
1189                 PMD_INIT_LOG(ERR, "init_adminq failed");
1190                 goto err;
1191         }
1192         vf->aq_resp = rte_zmalloc("vf_aq_resp", I40E_AQ_BUF_SZ, 0);
1193         if (!vf->aq_resp) {
1194                 PMD_INIT_LOG(ERR, "unable to allocate vf_aq_resp memory");
1195                 goto err_aq;
1196         }
1197         if (i40evf_check_api_version(dev) != 0) {
1198                 PMD_INIT_LOG(ERR, "check_api version failed");
1199                 goto err_api;
1200         }
1201         bufsz = sizeof(struct virtchnl_vf_resource) +
1202                 (I40E_MAX_VF_VSI * sizeof(struct virtchnl_vsi_resource));
1203         vf->vf_res = rte_zmalloc("vf_res", bufsz, 0);
1204         if (!vf->vf_res) {
1205                 PMD_INIT_LOG(ERR, "unable to allocate vf_res memory");
1206                 goto err_api;
1207         }
1208
1209         if (i40evf_get_vf_resource(dev) != 0) {
1210                 PMD_INIT_LOG(ERR, "i40evf_get_vf_config failed");
1211                 goto err_alloc;
1212         }
1213
1214         /* got VF config message back from PF, now we can parse it */
1215         for (i = 0; i < vf->vf_res->num_vsis; i++) {
1216                 if (vf->vf_res->vsi_res[i].vsi_type == VIRTCHNL_VSI_SRIOV)
1217                         vf->vsi_res = &vf->vf_res->vsi_res[i];
1218         }
1219
1220         if (!vf->vsi_res) {
1221                 PMD_INIT_LOG(ERR, "no LAN VSI found");
1222                 goto err_alloc;
1223         }
1224
1225         if (hw->mac.type == I40E_MAC_X722_VF)
1226                 vf->flags = I40E_FLAG_RSS_AQ_CAPABLE;
1227         vf->vsi.vsi_id = vf->vsi_res->vsi_id;
1228
1229         switch (vf->vsi_res->vsi_type) {
1230         case VIRTCHNL_VSI_SRIOV:
1231                 vf->vsi.type = I40E_VSI_SRIOV;
1232                 break;
1233         default:
1234                 vf->vsi.type = I40E_VSI_TYPE_UNKNOWN;
1235                 break;
1236         }
1237         vf->vsi.nb_qps = vf->vsi_res->num_queue_pairs;
1238         vf->vsi.adapter = I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1239
1240         /* Store the MAC address configured by host, or generate random one */
1241         if (is_valid_assigned_ether_addr((struct ether_addr *)hw->mac.addr))
1242                 vf->flags |= I40E_FLAG_VF_MAC_BY_PF;
1243         else
1244                 eth_random_addr(hw->mac.addr); /* Generate a random one */
1245
1246         I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1247                        (I40E_ITR_INDEX_DEFAULT <<
1248                         I40E_VFINT_DYN_CTL0_ITR_INDX_SHIFT) |
1249                        (interval <<
1250                         I40E_VFINT_DYN_CTL0_INTERVAL_SHIFT));
1251         I40EVF_WRITE_FLUSH(hw);
1252
1253         return 0;
1254
1255 err_alloc:
1256         rte_free(vf->vf_res);
1257         vf->vsi_res = NULL;
1258 err_api:
1259         rte_free(vf->aq_resp);
1260 err_aq:
1261         i40e_shutdown_adminq(hw); /* ignore error */
1262 err:
1263         return -1;
1264 }
1265
1266 static int
1267 i40evf_uninit_vf(struct rte_eth_dev *dev)
1268 {
1269         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1270         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1271
1272         PMD_INIT_FUNC_TRACE();
1273
1274         if (hw->adapter_stopped == 0)
1275                 i40evf_dev_close(dev);
1276         rte_free(vf->vf_res);
1277         vf->vf_res = NULL;
1278         rte_free(vf->aq_resp);
1279         vf->aq_resp = NULL;
1280
1281         return 0;
1282 }
1283
1284 static void
1285 i40evf_handle_pf_event(struct rte_eth_dev *dev, uint8_t *msg,
1286                 __rte_unused uint16_t msglen)
1287 {
1288         struct virtchnl_pf_event *pf_msg =
1289                         (struct virtchnl_pf_event *)msg;
1290         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1291
1292         switch (pf_msg->event) {
1293         case VIRTCHNL_EVENT_RESET_IMPENDING:
1294                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_RESET_IMPENDING event");
1295                 _rte_eth_dev_callback_process(dev, RTE_ETH_EVENT_INTR_RESET,
1296                                               NULL, NULL);
1297                 break;
1298         case VIRTCHNL_EVENT_LINK_CHANGE:
1299                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_LINK_CHANGE event");
1300                 vf->link_up = pf_msg->event_data.link_event.link_status;
1301                 vf->link_speed = pf_msg->event_data.link_event.link_speed;
1302                 break;
1303         case VIRTCHNL_EVENT_PF_DRIVER_CLOSE:
1304                 PMD_DRV_LOG(DEBUG, "VIRTCHNL_EVENT_PF_DRIVER_CLOSE event");
1305                 break;
1306         default:
1307                 PMD_DRV_LOG(ERR, " unknown event received %u", pf_msg->event);
1308                 break;
1309         }
1310 }
1311
1312 static void
1313 i40evf_handle_aq_msg(struct rte_eth_dev *dev)
1314 {
1315         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1316         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1317         struct i40e_arq_event_info info;
1318         uint16_t pending, aq_opc;
1319         enum virtchnl_ops msg_opc;
1320         enum i40e_status_code msg_ret;
1321         int ret;
1322
1323         info.buf_len = I40E_AQ_BUF_SZ;
1324         if (!vf->aq_resp) {
1325                 PMD_DRV_LOG(ERR, "Buffer for adminq resp should not be NULL");
1326                 return;
1327         }
1328         info.msg_buf = vf->aq_resp;
1329
1330         pending = 1;
1331         while (pending) {
1332                 ret = i40e_clean_arq_element(hw, &info, &pending);
1333
1334                 if (ret != I40E_SUCCESS) {
1335                         PMD_DRV_LOG(INFO, "Failed to read msg from AdminQ,"
1336                                     "ret: %d", ret);
1337                         break;
1338                 }
1339                 aq_opc = rte_le_to_cpu_16(info.desc.opcode);
1340                 /* For the message sent from pf to vf, opcode is stored in
1341                  * cookie_high of struct i40e_aq_desc, while return error code
1342                  * are stored in cookie_low, Which is done by
1343                  * i40e_aq_send_msg_to_vf in PF driver.*/
1344                 msg_opc = (enum virtchnl_ops)rte_le_to_cpu_32(
1345                                                   info.desc.cookie_high);
1346                 msg_ret = (enum i40e_status_code)rte_le_to_cpu_32(
1347                                                   info.desc.cookie_low);
1348                 switch (aq_opc) {
1349                 case i40e_aqc_opc_send_msg_to_vf:
1350                         if (msg_opc == VIRTCHNL_OP_EVENT)
1351                                 /* process event*/
1352                                 i40evf_handle_pf_event(dev, info.msg_buf,
1353                                                        info.msg_len);
1354                         else {
1355                                 /* read message and it's expected one */
1356                                 if (msg_opc == vf->pend_cmd) {
1357                                         vf->cmd_retval = msg_ret;
1358                                         /* prevent compiler reordering */
1359                                         rte_compiler_barrier();
1360                                         _clear_cmd(vf);
1361                                 } else
1362                                         PMD_DRV_LOG(ERR, "command mismatch,"
1363                                                 "expect %u, get %u",
1364                                                 vf->pend_cmd, msg_opc);
1365                                 PMD_DRV_LOG(DEBUG, "adminq response is received,"
1366                                              " opcode = %d", msg_opc);
1367                         }
1368                         break;
1369                 default:
1370                         PMD_DRV_LOG(ERR, "Request %u is not supported yet",
1371                                     aq_opc);
1372                         break;
1373                 }
1374         }
1375 }
1376
1377 /**
1378  * Interrupt handler triggered by NIC  for handling
1379  * specific interrupt. Only adminq interrupt is processed in VF.
1380  *
1381  * @param handle
1382  *  Pointer to interrupt handle.
1383  * @param param
1384  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1385  *
1386  * @return
1387  *  void
1388  */
1389 static void
1390 i40evf_dev_interrupt_handler(void *param)
1391 {
1392         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1393         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1394         uint32_t icr0;
1395
1396         i40evf_disable_irq0(hw);
1397
1398         /* read out interrupt causes */
1399         icr0 = I40E_READ_REG(hw, I40E_VFINT_ICR01);
1400
1401         /* No interrupt event indicated */
1402         if (!(icr0 & I40E_VFINT_ICR01_INTEVENT_MASK)) {
1403                 PMD_DRV_LOG(DEBUG, "No interrupt event, nothing to do");
1404                 goto done;
1405         }
1406
1407         if (icr0 & I40E_VFINT_ICR01_ADMINQ_MASK) {
1408                 PMD_DRV_LOG(DEBUG, "ICR01_ADMINQ is reported");
1409                 i40evf_handle_aq_msg(dev);
1410         }
1411
1412         /* Link Status Change interrupt */
1413         if (icr0 & I40E_VFINT_ICR01_LINK_STAT_CHANGE_MASK)
1414                 PMD_DRV_LOG(DEBUG, "LINK_STAT_CHANGE is reported,"
1415                                    " do nothing");
1416
1417 done:
1418         i40evf_enable_irq0(hw);
1419         rte_intr_enable(dev->intr_handle);
1420 }
1421
1422 static int
1423 i40evf_dev_init(struct rte_eth_dev *eth_dev)
1424 {
1425         struct i40e_hw *hw
1426                 = I40E_DEV_PRIVATE_TO_HW(eth_dev->data->dev_private);
1427         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(eth_dev);
1428
1429         PMD_INIT_FUNC_TRACE();
1430
1431         /* assign ops func pointer */
1432         eth_dev->dev_ops = &i40evf_eth_dev_ops;
1433         eth_dev->rx_pkt_burst = &i40e_recv_pkts;
1434         eth_dev->tx_pkt_burst = &i40e_xmit_pkts;
1435
1436         /*
1437          * For secondary processes, we don't initialise any further as primary
1438          * has already done this work.
1439          */
1440         if (rte_eal_process_type() != RTE_PROC_PRIMARY){
1441                 i40e_set_rx_function(eth_dev);
1442                 i40e_set_tx_function(eth_dev);
1443                 return 0;
1444         }
1445         i40e_set_default_ptype_table(eth_dev);
1446         i40e_set_default_pctype_table(eth_dev);
1447         rte_eth_copy_pci_info(eth_dev, pci_dev);
1448         eth_dev->data->dev_flags |= RTE_ETH_DEV_DETACHABLE;
1449
1450         hw->vendor_id = pci_dev->id.vendor_id;
1451         hw->device_id = pci_dev->id.device_id;
1452         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1453         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1454         hw->bus.device = pci_dev->addr.devid;
1455         hw->bus.func = pci_dev->addr.function;
1456         hw->hw_addr = (void *)pci_dev->mem_resource[0].addr;
1457         hw->adapter_stopped = 0;
1458
1459         if(i40evf_init_vf(eth_dev) != 0) {
1460                 PMD_INIT_LOG(ERR, "Init vf failed");
1461                 return -1;
1462         }
1463
1464         /* register callback func to eal lib */
1465         rte_intr_callback_register(&pci_dev->intr_handle,
1466                 i40evf_dev_interrupt_handler, (void *)eth_dev);
1467
1468         /* enable uio intr after callback register */
1469         rte_intr_enable(&pci_dev->intr_handle);
1470
1471         /* configure and enable device interrupt */
1472         i40evf_enable_irq0(hw);
1473
1474         /* copy mac addr */
1475         eth_dev->data->mac_addrs = rte_zmalloc("i40evf_mac",
1476                                         ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX,
1477                                         0);
1478         if (eth_dev->data->mac_addrs == NULL) {
1479                 PMD_INIT_LOG(ERR, "Failed to allocate %d bytes needed to"
1480                                 " store MAC addresses",
1481                                 ETHER_ADDR_LEN * I40E_NUM_MACADDR_MAX);
1482                 return -ENOMEM;
1483         }
1484         ether_addr_copy((struct ether_addr *)hw->mac.addr,
1485                         &eth_dev->data->mac_addrs[0]);
1486
1487         return 0;
1488 }
1489
1490 static int
1491 i40evf_dev_uninit(struct rte_eth_dev *eth_dev)
1492 {
1493         PMD_INIT_FUNC_TRACE();
1494
1495         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
1496                 return -EPERM;
1497
1498         eth_dev->dev_ops = NULL;
1499         eth_dev->rx_pkt_burst = NULL;
1500         eth_dev->tx_pkt_burst = NULL;
1501
1502         if (i40evf_uninit_vf(eth_dev) != 0) {
1503                 PMD_INIT_LOG(ERR, "i40evf_uninit_vf failed");
1504                 return -1;
1505         }
1506
1507         rte_free(eth_dev->data->mac_addrs);
1508         eth_dev->data->mac_addrs = NULL;
1509
1510         return 0;
1511 }
1512
1513 static int eth_i40evf_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
1514         struct rte_pci_device *pci_dev)
1515 {
1516         return rte_eth_dev_pci_generic_probe(pci_dev,
1517                 sizeof(struct i40e_adapter), i40evf_dev_init);
1518 }
1519
1520 static int eth_i40evf_pci_remove(struct rte_pci_device *pci_dev)
1521 {
1522         return rte_eth_dev_pci_generic_remove(pci_dev, i40evf_dev_uninit);
1523 }
1524
1525 /*
1526  * virtual function driver struct
1527  */
1528 static struct rte_pci_driver rte_i40evf_pmd = {
1529         .id_table = pci_id_i40evf_map,
1530         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_IOVA_AS_VA,
1531         .probe = eth_i40evf_pci_probe,
1532         .remove = eth_i40evf_pci_remove,
1533 };
1534
1535 RTE_PMD_REGISTER_PCI(net_i40e_vf, rte_i40evf_pmd);
1536 RTE_PMD_REGISTER_PCI_TABLE(net_i40e_vf, pci_id_i40evf_map);
1537 RTE_PMD_REGISTER_KMOD_DEP(net_i40e_vf, "* igb_uio | vfio-pci");
1538
1539 static int
1540 i40evf_dev_configure(struct rte_eth_dev *dev)
1541 {
1542         struct i40e_adapter *ad =
1543                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1544         struct rte_eth_conf *conf = &dev->data->dev_conf;
1545         struct i40e_vf *vf;
1546
1547         /* Initialize to TRUE. If any of Rx queues doesn't meet the bulk
1548          * allocation or vector Rx preconditions we will reset it.
1549          */
1550         ad->rx_bulk_alloc_allowed = true;
1551         ad->rx_vec_allowed = true;
1552         ad->tx_simple_allowed = true;
1553         ad->tx_vec_allowed = true;
1554
1555         /* For non-DPDK PF drivers, VF has no ability to disable HW
1556          * CRC strip, and is implicitly enabled by the PF.
1557          */
1558         if (!conf->rxmode.hw_strip_crc) {
1559                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1560                 if ((vf->version_major == VIRTCHNL_VERSION_MAJOR) &&
1561                     (vf->version_minor <= VIRTCHNL_VERSION_MINOR)) {
1562                         /* Peer is running non-DPDK PF driver. */
1563                         PMD_INIT_LOG(ERR, "VF can't disable HW CRC Strip");
1564                         return -EINVAL;
1565                 }
1566         }
1567
1568         return i40evf_init_vlan(dev);
1569 }
1570
1571 static int
1572 i40evf_init_vlan(struct rte_eth_dev *dev)
1573 {
1574         /* Apply vlan offload setting */
1575         i40evf_vlan_offload_set(dev, ETH_VLAN_STRIP_MASK);
1576
1577         return I40E_SUCCESS;
1578 }
1579
1580 static void
1581 i40evf_vlan_offload_set(struct rte_eth_dev *dev, int mask)
1582 {
1583         struct rte_eth_conf *dev_conf = &dev->data->dev_conf;
1584
1585         /* Vlan stripping setting */
1586         if (mask & ETH_VLAN_STRIP_MASK) {
1587                 /* Enable or disable VLAN stripping */
1588                 if (dev_conf->rxmode.hw_vlan_strip)
1589                         i40evf_enable_vlan_strip(dev);
1590                 else
1591                         i40evf_disable_vlan_strip(dev);
1592         }
1593 }
1594
1595 static int
1596 i40evf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1597 {
1598         struct i40e_rx_queue *rxq;
1599         int err = 0;
1600         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1601
1602         PMD_INIT_FUNC_TRACE();
1603
1604         if (rx_queue_id < dev->data->nb_rx_queues) {
1605                 rxq = dev->data->rx_queues[rx_queue_id];
1606
1607                 err = i40e_alloc_rx_queue_mbufs(rxq);
1608                 if (err) {
1609                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1610                         return err;
1611                 }
1612
1613                 rte_wmb();
1614
1615                 /* Init the RX tail register. */
1616                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1617                 I40EVF_WRITE_FLUSH(hw);
1618
1619                 /* Ready to switch the queue on */
1620                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, TRUE);
1621
1622                 if (err)
1623                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1624                                     rx_queue_id);
1625                 else
1626                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1627         }
1628
1629         return err;
1630 }
1631
1632 static int
1633 i40evf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1634 {
1635         struct i40e_rx_queue *rxq;
1636         int err;
1637
1638         if (rx_queue_id < dev->data->nb_rx_queues) {
1639                 rxq = dev->data->rx_queues[rx_queue_id];
1640
1641                 err = i40evf_switch_queue(dev, TRUE, rx_queue_id, FALSE);
1642
1643                 if (err) {
1644                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1645                                     rx_queue_id);
1646                         return err;
1647                 }
1648
1649                 i40e_rx_queue_release_mbufs(rxq);
1650                 i40e_reset_rx_queue(rxq);
1651                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1652         }
1653
1654         return 0;
1655 }
1656
1657 static int
1658 i40evf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1659 {
1660         int err = 0;
1661
1662         PMD_INIT_FUNC_TRACE();
1663
1664         if (tx_queue_id < dev->data->nb_tx_queues) {
1665
1666                 /* Ready to switch the queue on */
1667                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, TRUE);
1668
1669                 if (err)
1670                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1671                                     tx_queue_id);
1672                 else
1673                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1674         }
1675
1676         return err;
1677 }
1678
1679 static int
1680 i40evf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1681 {
1682         struct i40e_tx_queue *txq;
1683         int err;
1684
1685         if (tx_queue_id < dev->data->nb_tx_queues) {
1686                 txq = dev->data->tx_queues[tx_queue_id];
1687
1688                 err = i40evf_switch_queue(dev, FALSE, tx_queue_id, FALSE);
1689
1690                 if (err) {
1691                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
1692                                     tx_queue_id);
1693                         return err;
1694                 }
1695
1696                 i40e_tx_queue_release_mbufs(txq);
1697                 i40e_reset_tx_queue(txq);
1698                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1699         }
1700
1701         return 0;
1702 }
1703
1704 static int
1705 i40evf_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
1706 {
1707         int ret;
1708
1709         if (on)
1710                 ret = i40evf_add_vlan(dev, vlan_id);
1711         else
1712                 ret = i40evf_del_vlan(dev,vlan_id);
1713
1714         return ret;
1715 }
1716
1717 static int
1718 i40evf_rxq_init(struct rte_eth_dev *dev, struct i40e_rx_queue *rxq)
1719 {
1720         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1721         struct rte_eth_dev_data *dev_data = dev->data;
1722         struct rte_pktmbuf_pool_private *mbp_priv;
1723         uint16_t buf_size, len;
1724
1725         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL1(rxq->queue_id);
1726         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1727         I40EVF_WRITE_FLUSH(hw);
1728
1729         /* Calculate the maximum packet length allowed */
1730         mbp_priv = rte_mempool_get_priv(rxq->mp);
1731         buf_size = (uint16_t)(mbp_priv->mbuf_data_room_size -
1732                                         RTE_PKTMBUF_HEADROOM);
1733         rxq->hs_mode = i40e_header_split_none;
1734         rxq->rx_hdr_len = 0;
1735         rxq->rx_buf_len = RTE_ALIGN(buf_size, (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
1736         len = rxq->rx_buf_len * I40E_MAX_CHAINED_RX_BUFFERS;
1737         rxq->max_pkt_len = RTE_MIN(len,
1738                 dev_data->dev_conf.rxmode.max_rx_pkt_len);
1739
1740         /**
1741          * Check if the jumbo frame and maximum packet length are set correctly
1742          */
1743         if (dev_data->dev_conf.rxmode.jumbo_frame == 1) {
1744                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
1745                     rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
1746                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1747                                 "larger than %u and smaller than %u, as jumbo "
1748                                 "frame is enabled", (uint32_t)ETHER_MAX_LEN,
1749                                         (uint32_t)I40E_FRAME_SIZE_MAX);
1750                         return I40E_ERR_CONFIG;
1751                 }
1752         } else {
1753                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
1754                     rxq->max_pkt_len > ETHER_MAX_LEN) {
1755                         PMD_DRV_LOG(ERR, "maximum packet length must be "
1756                                 "larger than %u and smaller than %u, as jumbo "
1757                                 "frame is disabled", (uint32_t)ETHER_MIN_LEN,
1758                                                 (uint32_t)ETHER_MAX_LEN);
1759                         return I40E_ERR_CONFIG;
1760                 }
1761         }
1762
1763         if (dev_data->dev_conf.rxmode.enable_scatter ||
1764             (rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
1765                 dev_data->scattered_rx = 1;
1766         }
1767
1768         return 0;
1769 }
1770
1771 static int
1772 i40evf_rx_init(struct rte_eth_dev *dev)
1773 {
1774         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1775         uint16_t i;
1776         int ret = I40E_SUCCESS;
1777         struct i40e_rx_queue **rxq =
1778                 (struct i40e_rx_queue **)dev->data->rx_queues;
1779
1780         i40evf_config_rss(vf);
1781         for (i = 0; i < dev->data->nb_rx_queues; i++) {
1782                 if (!rxq[i] || !rxq[i]->q_set)
1783                         continue;
1784                 ret = i40evf_rxq_init(dev, rxq[i]);
1785                 if (ret != I40E_SUCCESS)
1786                         break;
1787         }
1788         if (ret == I40E_SUCCESS)
1789                 i40e_set_rx_function(dev);
1790
1791         return ret;
1792 }
1793
1794 static void
1795 i40evf_tx_init(struct rte_eth_dev *dev)
1796 {
1797         uint16_t i;
1798         struct i40e_tx_queue **txq =
1799                 (struct i40e_tx_queue **)dev->data->tx_queues;
1800         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1801
1802         for (i = 0; i < dev->data->nb_tx_queues; i++)
1803                 txq[i]->qtx_tail = hw->hw_addr + I40E_QTX_TAIL1(i);
1804
1805         i40e_set_tx_function(dev);
1806 }
1807
1808 static inline void
1809 i40evf_enable_queues_intr(struct rte_eth_dev *dev)
1810 {
1811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1813         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1814
1815         if (!rte_intr_allow_others(intr_handle)) {
1816                 I40E_WRITE_REG(hw,
1817                                I40E_VFINT_DYN_CTL01,
1818                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1819                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1820                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1821                 I40EVF_WRITE_FLUSH(hw);
1822                 return;
1823         }
1824
1825         I40EVF_WRITE_FLUSH(hw);
1826 }
1827
1828 static inline void
1829 i40evf_disable_queues_intr(struct rte_eth_dev *dev)
1830 {
1831         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1832         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1833         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1834
1835         if (!rte_intr_allow_others(intr_handle)) {
1836                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1837                                I40E_VFINT_DYN_CTL01_ITR_INDX_MASK);
1838                 I40EVF_WRITE_FLUSH(hw);
1839                 return;
1840         }
1841
1842         I40EVF_WRITE_FLUSH(hw);
1843 }
1844
1845 static int
1846 i40evf_dev_rx_queue_intr_enable(struct rte_eth_dev *dev, uint16_t queue_id)
1847 {
1848         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1849         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1850         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1851         uint16_t interval =
1852                 i40e_calc_itr_interval(RTE_LIBRTE_I40E_ITR_INTERVAL);
1853         uint16_t msix_intr;
1854
1855         msix_intr = intr_handle->intr_vec[queue_id];
1856         if (msix_intr == I40E_MISC_VEC_ID)
1857                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01,
1858                                I40E_VFINT_DYN_CTL01_INTENA_MASK |
1859                                I40E_VFINT_DYN_CTL01_CLEARPBA_MASK |
1860                                (0 << I40E_VFINT_DYN_CTL01_ITR_INDX_SHIFT) |
1861                                (interval <<
1862                                 I40E_VFINT_DYN_CTL01_INTERVAL_SHIFT));
1863         else
1864                 I40E_WRITE_REG(hw,
1865                                I40E_VFINT_DYN_CTLN1(msix_intr -
1866                                                     I40E_RX_VEC_START),
1867                                I40E_VFINT_DYN_CTLN1_INTENA_MASK |
1868                                I40E_VFINT_DYN_CTLN1_CLEARPBA_MASK |
1869                                (0 << I40E_VFINT_DYN_CTLN1_ITR_INDX_SHIFT) |
1870                                (interval <<
1871                                 I40E_VFINT_DYN_CTLN1_INTERVAL_SHIFT));
1872
1873         I40EVF_WRITE_FLUSH(hw);
1874
1875         rte_intr_enable(&pci_dev->intr_handle);
1876
1877         return 0;
1878 }
1879
1880 static int
1881 i40evf_dev_rx_queue_intr_disable(struct rte_eth_dev *dev, uint16_t queue_id)
1882 {
1883         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1884         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1885         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1886         uint16_t msix_intr;
1887
1888         msix_intr = intr_handle->intr_vec[queue_id];
1889         if (msix_intr == I40E_MISC_VEC_ID)
1890                 I40E_WRITE_REG(hw, I40E_VFINT_DYN_CTL01, 0);
1891         else
1892                 I40E_WRITE_REG(hw,
1893                                I40E_VFINT_DYN_CTLN1(msix_intr -
1894                                                     I40E_RX_VEC_START),
1895                                0);
1896
1897         I40EVF_WRITE_FLUSH(hw);
1898
1899         return 0;
1900 }
1901
1902 static void
1903 i40evf_add_del_all_mac_addr(struct rte_eth_dev *dev, bool add)
1904 {
1905         struct virtchnl_ether_addr_list *list;
1906         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1907         int err, i, j;
1908         int next_begin = 0;
1909         int begin = 0;
1910         uint32_t len;
1911         struct ether_addr *addr;
1912         struct vf_cmd_info args;
1913
1914         do {
1915                 j = 0;
1916                 len = sizeof(struct virtchnl_ether_addr_list);
1917                 for (i = begin; i < I40E_NUM_MACADDR_MAX; i++, next_begin++) {
1918                         if (is_zero_ether_addr(&dev->data->mac_addrs[i]))
1919                                 continue;
1920                         len += sizeof(struct virtchnl_ether_addr);
1921                         if (len >= I40E_AQ_BUF_SZ) {
1922                                 next_begin = i + 1;
1923                                 break;
1924                         }
1925                 }
1926
1927                 list = rte_zmalloc("i40evf_del_mac_buffer", len, 0);
1928                 if (!list) {
1929                         PMD_DRV_LOG(ERR, "fail to allocate memory");
1930                         return;
1931                 }
1932
1933                 for (i = begin; i < next_begin; i++) {
1934                         addr = &dev->data->mac_addrs[i];
1935                         if (is_zero_ether_addr(addr))
1936                                 continue;
1937                         rte_memcpy(list->list[j].addr, addr->addr_bytes,
1938                                          sizeof(addr->addr_bytes));
1939                         PMD_DRV_LOG(DEBUG, "add/rm mac:%x:%x:%x:%x:%x:%x",
1940                                     addr->addr_bytes[0], addr->addr_bytes[1],
1941                                     addr->addr_bytes[2], addr->addr_bytes[3],
1942                                     addr->addr_bytes[4], addr->addr_bytes[5]);
1943                         j++;
1944                 }
1945                 list->vsi_id = vf->vsi_res->vsi_id;
1946                 list->num_elements = j;
1947                 args.ops = add ? VIRTCHNL_OP_ADD_ETH_ADDR :
1948                            VIRTCHNL_OP_DEL_ETH_ADDR;
1949                 args.in_args = (uint8_t *)list;
1950                 args.in_args_size = len;
1951                 args.out_buffer = vf->aq_resp;
1952                 args.out_size = I40E_AQ_BUF_SZ;
1953                 err = i40evf_execute_vf_cmd(dev, &args);
1954                 if (err) {
1955                         PMD_DRV_LOG(ERR, "fail to execute command %s",
1956                                     add ? "OP_ADD_ETHER_ADDRESS" :
1957                                     "OP_DEL_ETHER_ADDRESS");
1958                 } else {
1959                         if (add)
1960                                 vf->vsi.mac_num++;
1961                         else
1962                                 vf->vsi.mac_num--;
1963                 }
1964                 rte_free(list);
1965                 begin = next_begin;
1966         } while (begin < I40E_NUM_MACADDR_MAX);
1967 }
1968
1969 static int
1970 i40evf_dev_start(struct rte_eth_dev *dev)
1971 {
1972         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1973         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1974         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1975         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1976         uint32_t intr_vector = 0;
1977
1978         PMD_INIT_FUNC_TRACE();
1979
1980         hw->adapter_stopped = 0;
1981
1982         vf->max_pkt_len = dev->data->dev_conf.rxmode.max_rx_pkt_len;
1983         vf->num_queue_pairs = RTE_MAX(dev->data->nb_rx_queues,
1984                                         dev->data->nb_tx_queues);
1985
1986         /* check and configure queue intr-vector mapping */
1987         if (dev->data->dev_conf.intr_conf.rxq != 0) {
1988                 intr_vector = dev->data->nb_rx_queues;
1989                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1990                         return -1;
1991         }
1992
1993         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1994                 intr_handle->intr_vec =
1995                         rte_zmalloc("intr_vec",
1996                                     dev->data->nb_rx_queues * sizeof(int), 0);
1997                 if (!intr_handle->intr_vec) {
1998                         PMD_INIT_LOG(ERR, "Failed to allocate %d rx_queues"
1999                                      " intr_vec", dev->data->nb_rx_queues);
2000                         return -ENOMEM;
2001                 }
2002         }
2003
2004         if (i40evf_rx_init(dev) != 0){
2005                 PMD_DRV_LOG(ERR, "failed to do RX init");
2006                 return -1;
2007         }
2008
2009         i40evf_tx_init(dev);
2010
2011         if (i40evf_configure_vsi_queues(dev) != 0) {
2012                 PMD_DRV_LOG(ERR, "configure queues failed");
2013                 goto err_queue;
2014         }
2015         if (i40evf_config_irq_map(dev)) {
2016                 PMD_DRV_LOG(ERR, "config_irq_map failed");
2017                 goto err_queue;
2018         }
2019
2020         /* Set all mac addrs */
2021         i40evf_add_del_all_mac_addr(dev, TRUE);
2022
2023         if (i40evf_start_queues(dev) != 0) {
2024                 PMD_DRV_LOG(ERR, "enable queues failed");
2025                 goto err_mac;
2026         }
2027
2028         i40evf_enable_queues_intr(dev);
2029         return 0;
2030
2031 err_mac:
2032         i40evf_add_del_all_mac_addr(dev, FALSE);
2033 err_queue:
2034         return -1;
2035 }
2036
2037 static void
2038 i40evf_dev_stop(struct rte_eth_dev *dev)
2039 {
2040         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2041         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2042         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2043
2044         PMD_INIT_FUNC_TRACE();
2045
2046         if (hw->adapter_stopped == 1)
2047                 return;
2048         i40evf_stop_queues(dev);
2049         i40evf_disable_queues_intr(dev);
2050         i40e_dev_clear_queues(dev);
2051
2052         /* Clean datapath event and queue/vec mapping */
2053         rte_intr_efd_disable(intr_handle);
2054         if (intr_handle->intr_vec) {
2055                 rte_free(intr_handle->intr_vec);
2056                 intr_handle->intr_vec = NULL;
2057         }
2058         /* remove all mac addrs */
2059         i40evf_add_del_all_mac_addr(dev, FALSE);
2060         hw->adapter_stopped = 1;
2061
2062 }
2063
2064 static int
2065 i40evf_dev_link_update(struct rte_eth_dev *dev,
2066                        __rte_unused int wait_to_complete)
2067 {
2068         struct rte_eth_link new_link;
2069         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2070         /*
2071          * DPDK pf host provide interfacet to acquire link status
2072          * while Linux driver does not
2073          */
2074
2075         /* Linux driver PF host */
2076         switch (vf->link_speed) {
2077         case I40E_LINK_SPEED_100MB:
2078                 new_link.link_speed = ETH_SPEED_NUM_100M;
2079                 break;
2080         case I40E_LINK_SPEED_1GB:
2081                 new_link.link_speed = ETH_SPEED_NUM_1G;
2082                 break;
2083         case I40E_LINK_SPEED_10GB:
2084                 new_link.link_speed = ETH_SPEED_NUM_10G;
2085                 break;
2086         case I40E_LINK_SPEED_20GB:
2087                 new_link.link_speed = ETH_SPEED_NUM_20G;
2088                 break;
2089         case I40E_LINK_SPEED_25GB:
2090                 new_link.link_speed = ETH_SPEED_NUM_25G;
2091                 break;
2092         case I40E_LINK_SPEED_40GB:
2093                 new_link.link_speed = ETH_SPEED_NUM_40G;
2094                 break;
2095         default:
2096                 new_link.link_speed = ETH_SPEED_NUM_100M;
2097                 break;
2098         }
2099         /* full duplex only */
2100         new_link.link_duplex = ETH_LINK_FULL_DUPLEX;
2101         new_link.link_status = vf->link_up ? ETH_LINK_UP :
2102                                              ETH_LINK_DOWN;
2103         new_link.link_autoneg =
2104                 dev->data->dev_conf.link_speeds & ETH_LINK_SPEED_FIXED;
2105
2106         i40evf_dev_atomic_write_link_status(dev, &new_link);
2107
2108         return 0;
2109 }
2110
2111 static void
2112 i40evf_dev_promiscuous_enable(struct rte_eth_dev *dev)
2113 {
2114         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2115         int ret;
2116
2117         /* If enabled, just return */
2118         if (vf->promisc_unicast_enabled)
2119                 return;
2120
2121         ret = i40evf_config_promisc(dev, 1, vf->promisc_multicast_enabled);
2122         if (ret == 0)
2123                 vf->promisc_unicast_enabled = TRUE;
2124 }
2125
2126 static void
2127 i40evf_dev_promiscuous_disable(struct rte_eth_dev *dev)
2128 {
2129         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2130         int ret;
2131
2132         /* If disabled, just return */
2133         if (!vf->promisc_unicast_enabled)
2134                 return;
2135
2136         ret = i40evf_config_promisc(dev, 0, vf->promisc_multicast_enabled);
2137         if (ret == 0)
2138                 vf->promisc_unicast_enabled = FALSE;
2139 }
2140
2141 static void
2142 i40evf_dev_allmulticast_enable(struct rte_eth_dev *dev)
2143 {
2144         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2145         int ret;
2146
2147         /* If enabled, just return */
2148         if (vf->promisc_multicast_enabled)
2149                 return;
2150
2151         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 1);
2152         if (ret == 0)
2153                 vf->promisc_multicast_enabled = TRUE;
2154 }
2155
2156 static void
2157 i40evf_dev_allmulticast_disable(struct rte_eth_dev *dev)
2158 {
2159         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2160         int ret;
2161
2162         /* If enabled, just return */
2163         if (!vf->promisc_multicast_enabled)
2164                 return;
2165
2166         ret = i40evf_config_promisc(dev, vf->promisc_unicast_enabled, 0);
2167         if (ret == 0)
2168                 vf->promisc_multicast_enabled = FALSE;
2169 }
2170
2171 static void
2172 i40evf_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2173 {
2174         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2175
2176         memset(dev_info, 0, sizeof(*dev_info));
2177         dev_info->pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2178         dev_info->max_rx_queues = vf->vsi_res->num_queue_pairs;
2179         dev_info->max_tx_queues = vf->vsi_res->num_queue_pairs;
2180         dev_info->min_rx_bufsize = I40E_BUF_SIZE_MIN;
2181         dev_info->max_rx_pktlen = I40E_FRAME_SIZE_MAX;
2182         dev_info->hash_key_size = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2183         dev_info->reta_size = ETH_RSS_RETA_SIZE_64;
2184         dev_info->flow_type_rss_offloads = vf->adapter->flow_types_mask;
2185         dev_info->max_mac_addrs = I40E_NUM_MACADDR_MAX;
2186         dev_info->rx_offload_capa =
2187                 DEV_RX_OFFLOAD_VLAN_STRIP |
2188                 DEV_RX_OFFLOAD_QINQ_STRIP |
2189                 DEV_RX_OFFLOAD_IPV4_CKSUM |
2190                 DEV_RX_OFFLOAD_UDP_CKSUM |
2191                 DEV_RX_OFFLOAD_TCP_CKSUM;
2192         dev_info->tx_offload_capa =
2193                 DEV_TX_OFFLOAD_VLAN_INSERT |
2194                 DEV_TX_OFFLOAD_QINQ_INSERT |
2195                 DEV_TX_OFFLOAD_IPV4_CKSUM |
2196                 DEV_TX_OFFLOAD_UDP_CKSUM |
2197                 DEV_TX_OFFLOAD_TCP_CKSUM |
2198                 DEV_TX_OFFLOAD_SCTP_CKSUM;
2199
2200         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2201                 .rx_thresh = {
2202                         .pthresh = I40E_DEFAULT_RX_PTHRESH,
2203                         .hthresh = I40E_DEFAULT_RX_HTHRESH,
2204                         .wthresh = I40E_DEFAULT_RX_WTHRESH,
2205                 },
2206                 .rx_free_thresh = I40E_DEFAULT_RX_FREE_THRESH,
2207                 .rx_drop_en = 0,
2208         };
2209
2210         dev_info->default_txconf = (struct rte_eth_txconf) {
2211                 .tx_thresh = {
2212                         .pthresh = I40E_DEFAULT_TX_PTHRESH,
2213                         .hthresh = I40E_DEFAULT_TX_HTHRESH,
2214                         .wthresh = I40E_DEFAULT_TX_WTHRESH,
2215                 },
2216                 .tx_free_thresh = I40E_DEFAULT_TX_FREE_THRESH,
2217                 .tx_rs_thresh = I40E_DEFAULT_TX_RSBIT_THRESH,
2218                 .txq_flags = ETH_TXQ_FLAGS_NOMULTSEGS |
2219                                 ETH_TXQ_FLAGS_NOOFFLOADS,
2220         };
2221
2222         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2223                 .nb_max = I40E_MAX_RING_DESC,
2224                 .nb_min = I40E_MIN_RING_DESC,
2225                 .nb_align = I40E_ALIGN_RING_DESC,
2226         };
2227
2228         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2229                 .nb_max = I40E_MAX_RING_DESC,
2230                 .nb_min = I40E_MIN_RING_DESC,
2231                 .nb_align = I40E_ALIGN_RING_DESC,
2232         };
2233 }
2234
2235 static int
2236 i40evf_dev_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
2237 {
2238         int ret;
2239         struct i40e_eth_stats *pstats = NULL;
2240         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2241         struct i40e_vsi *vsi = &vf->vsi;
2242
2243         ret = i40evf_query_stats(dev, &pstats);
2244         if (ret == 0) {
2245                 i40evf_update_stats(vsi, pstats);
2246
2247                 stats->ipackets = pstats->rx_unicast + pstats->rx_multicast +
2248                                                 pstats->rx_broadcast;
2249                 stats->opackets = pstats->tx_broadcast + pstats->tx_multicast +
2250                                                 pstats->tx_unicast;
2251                 stats->imissed = pstats->rx_discards;
2252                 stats->oerrors = pstats->tx_errors + pstats->tx_discards;
2253                 stats->ibytes = pstats->rx_bytes;
2254                 stats->obytes = pstats->tx_bytes;
2255         } else {
2256                 PMD_DRV_LOG(ERR, "Get statistics failed");
2257         }
2258         return ret;
2259 }
2260
2261 static void
2262 i40evf_dev_close(struct rte_eth_dev *dev)
2263 {
2264         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2265         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2266         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2267
2268         i40evf_dev_stop(dev);
2269         i40e_dev_free_queues(dev);
2270         i40evf_reset_vf(hw);
2271         i40e_shutdown_adminq(hw);
2272         /* disable uio intr before callback unregister */
2273         rte_intr_disable(intr_handle);
2274
2275         /* unregister callback func from eal lib */
2276         rte_intr_callback_unregister(intr_handle,
2277                                      i40evf_dev_interrupt_handler, dev);
2278         i40evf_disable_irq0(hw);
2279 }
2280
2281 /*
2282  * Reset VF device only to re-initialize resources in PMD layer
2283  */
2284 static int
2285 i40evf_dev_reset(struct rte_eth_dev *dev)
2286 {
2287         int ret;
2288
2289         ret = i40evf_dev_uninit(dev);
2290         if (ret)
2291                 return ret;
2292
2293         ret = i40evf_dev_init(dev);
2294
2295         return ret;
2296 }
2297
2298 static int
2299 i40evf_get_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2300 {
2301         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2302         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2303         int ret;
2304
2305         if (!lut)
2306                 return -EINVAL;
2307
2308         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2309                 ret = i40e_aq_get_rss_lut(hw, vsi->vsi_id, FALSE,
2310                                           lut, lut_size);
2311                 if (ret) {
2312                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2313                         return ret;
2314                 }
2315         } else {
2316                 uint32_t *lut_dw = (uint32_t *)lut;
2317                 uint16_t i, lut_size_dw = lut_size / 4;
2318
2319                 for (i = 0; i < lut_size_dw; i++)
2320                         lut_dw[i] = I40E_READ_REG(hw, I40E_VFQF_HLUT(i));
2321         }
2322
2323         return 0;
2324 }
2325
2326 static int
2327 i40evf_set_rss_lut(struct i40e_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2328 {
2329         struct i40e_vf *vf;
2330         struct i40e_hw *hw;
2331         int ret;
2332
2333         if (!vsi || !lut)
2334                 return -EINVAL;
2335
2336         vf = I40E_VSI_TO_VF(vsi);
2337         hw = I40E_VSI_TO_HW(vsi);
2338
2339         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2340                 ret = i40e_aq_set_rss_lut(hw, vsi->vsi_id, FALSE,
2341                                           lut, lut_size);
2342                 if (ret) {
2343                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2344                         return ret;
2345                 }
2346         } else {
2347                 uint32_t *lut_dw = (uint32_t *)lut;
2348                 uint16_t i, lut_size_dw = lut_size / 4;
2349
2350                 for (i = 0; i < lut_size_dw; i++)
2351                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i), lut_dw[i]);
2352                 I40EVF_WRITE_FLUSH(hw);
2353         }
2354
2355         return 0;
2356 }
2357
2358 static int
2359 i40evf_dev_rss_reta_update(struct rte_eth_dev *dev,
2360                            struct rte_eth_rss_reta_entry64 *reta_conf,
2361                            uint16_t reta_size)
2362 {
2363         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2364         uint8_t *lut;
2365         uint16_t i, idx, shift;
2366         int ret;
2367
2368         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2369                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2370                         "(%d) doesn't match the number of hardware can "
2371                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2372                 return -EINVAL;
2373         }
2374
2375         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2376         if (!lut) {
2377                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2378                 return -ENOMEM;
2379         }
2380         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2381         if (ret)
2382                 goto out;
2383         for (i = 0; i < reta_size; i++) {
2384                 idx = i / RTE_RETA_GROUP_SIZE;
2385                 shift = i % RTE_RETA_GROUP_SIZE;
2386                 if (reta_conf[idx].mask & (1ULL << shift))
2387                         lut[i] = reta_conf[idx].reta[shift];
2388         }
2389         ret = i40evf_set_rss_lut(&vf->vsi, lut, reta_size);
2390
2391 out:
2392         rte_free(lut);
2393
2394         return ret;
2395 }
2396
2397 static int
2398 i40evf_dev_rss_reta_query(struct rte_eth_dev *dev,
2399                           struct rte_eth_rss_reta_entry64 *reta_conf,
2400                           uint16_t reta_size)
2401 {
2402         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2403         uint16_t i, idx, shift;
2404         uint8_t *lut;
2405         int ret;
2406
2407         if (reta_size != ETH_RSS_RETA_SIZE_64) {
2408                 PMD_DRV_LOG(ERR, "The size of hash lookup table configured "
2409                         "(%d) doesn't match the number of hardware can "
2410                         "support (%d)", reta_size, ETH_RSS_RETA_SIZE_64);
2411                 return -EINVAL;
2412         }
2413
2414         lut = rte_zmalloc("i40e_rss_lut", reta_size, 0);
2415         if (!lut) {
2416                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2417                 return -ENOMEM;
2418         }
2419
2420         ret = i40evf_get_rss_lut(&vf->vsi, lut, reta_size);
2421         if (ret)
2422                 goto out;
2423         for (i = 0; i < reta_size; i++) {
2424                 idx = i / RTE_RETA_GROUP_SIZE;
2425                 shift = i % RTE_RETA_GROUP_SIZE;
2426                 if (reta_conf[idx].mask & (1ULL << shift))
2427                         reta_conf[idx].reta[shift] = lut[i];
2428         }
2429
2430 out:
2431         rte_free(lut);
2432
2433         return ret;
2434 }
2435
2436 static int
2437 i40evf_set_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t key_len)
2438 {
2439         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2440         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2441         int ret = 0;
2442
2443         if (!key || key_len == 0) {
2444                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2445                 return 0;
2446         } else if (key_len != (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2447                 sizeof(uint32_t)) {
2448                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2449                 return -EINVAL;
2450         }
2451
2452         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2453                 struct i40e_aqc_get_set_rss_key_data *key_dw =
2454                         (struct i40e_aqc_get_set_rss_key_data *)key;
2455
2456                 ret = i40e_aq_set_rss_key(hw, vsi->vsi_id, key_dw);
2457                 if (ret)
2458                         PMD_INIT_LOG(ERR, "Failed to configure RSS key "
2459                                      "via AQ");
2460         } else {
2461                 uint32_t *hash_key = (uint32_t *)key;
2462                 uint16_t i;
2463
2464                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2465                         i40e_write_rx_ctl(hw, I40E_VFQF_HKEY(i), hash_key[i]);
2466                 I40EVF_WRITE_FLUSH(hw);
2467         }
2468
2469         return ret;
2470 }
2471
2472 static int
2473 i40evf_get_rss_key(struct i40e_vsi *vsi, uint8_t *key, uint8_t *key_len)
2474 {
2475         struct i40e_vf *vf = I40E_VSI_TO_VF(vsi);
2476         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2477         int ret;
2478
2479         if (!key || !key_len)
2480                 return -EINVAL;
2481
2482         if (vf->flags & I40E_FLAG_RSS_AQ_CAPABLE) {
2483                 ret = i40e_aq_get_rss_key(hw, vsi->vsi_id,
2484                         (struct i40e_aqc_get_set_rss_key_data *)key);
2485                 if (ret) {
2486                         PMD_INIT_LOG(ERR, "Failed to get RSS key via AQ");
2487                         return ret;
2488                 }
2489         } else {
2490                 uint32_t *key_dw = (uint32_t *)key;
2491                 uint16_t i;
2492
2493                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2494                         key_dw[i] = i40e_read_rx_ctl(hw, I40E_VFQF_HKEY(i));
2495         }
2496         *key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2497
2498         return 0;
2499 }
2500
2501 static int
2502 i40evf_hw_rss_hash_set(struct i40e_vf *vf, struct rte_eth_rss_conf *rss_conf)
2503 {
2504         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2505         uint64_t hena;
2506         int ret;
2507
2508         ret = i40evf_set_rss_key(&vf->vsi, rss_conf->rss_key,
2509                                  rss_conf->rss_key_len);
2510         if (ret)
2511                 return ret;
2512
2513         hena = i40e_config_hena(vf->adapter, rss_conf->rss_hf);
2514         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), (uint32_t)hena);
2515         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), (uint32_t)(hena >> 32));
2516         I40EVF_WRITE_FLUSH(hw);
2517
2518         return 0;
2519 }
2520
2521 static void
2522 i40evf_disable_rss(struct i40e_vf *vf)
2523 {
2524         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2525
2526         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(0), 0);
2527         i40e_write_rx_ctl(hw, I40E_VFQF_HENA(1), 0);
2528         I40EVF_WRITE_FLUSH(hw);
2529 }
2530
2531 static int
2532 i40evf_config_rss(struct i40e_vf *vf)
2533 {
2534         struct i40e_hw *hw = I40E_VF_TO_HW(vf);
2535         struct rte_eth_rss_conf rss_conf;
2536         uint32_t i, j, lut = 0, nb_q = (I40E_VFQF_HLUT_MAX_INDEX + 1) * 4;
2537         uint16_t num;
2538
2539         if (vf->dev_data->dev_conf.rxmode.mq_mode != ETH_MQ_RX_RSS) {
2540                 i40evf_disable_rss(vf);
2541                 PMD_DRV_LOG(DEBUG, "RSS not configured");
2542                 return 0;
2543         }
2544
2545         num = RTE_MIN(vf->dev_data->nb_rx_queues, I40E_MAX_QP_NUM_PER_VF);
2546         /* Fill out the look up table */
2547         for (i = 0, j = 0; i < nb_q; i++, j++) {
2548                 if (j >= num)
2549                         j = 0;
2550                 lut = (lut << 8) | j;
2551                 if ((i & 3) == 3)
2552                         I40E_WRITE_REG(hw, I40E_VFQF_HLUT(i >> 2), lut);
2553         }
2554
2555         rss_conf = vf->dev_data->dev_conf.rx_adv_conf.rss_conf;
2556         if ((rss_conf.rss_hf & vf->adapter->flow_types_mask) == 0) {
2557                 i40evf_disable_rss(vf);
2558                 PMD_DRV_LOG(DEBUG, "No hash flag is set");
2559                 return 0;
2560         }
2561
2562         if (rss_conf.rss_key == NULL || rss_conf.rss_key_len <
2563                 (I40E_VFQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t)) {
2564                 /* Calculate the default hash key */
2565                 for (i = 0; i <= I40E_VFQF_HKEY_MAX_INDEX; i++)
2566                         rss_key_default[i] = (uint32_t)rte_rand();
2567                 rss_conf.rss_key = (uint8_t *)rss_key_default;
2568                 rss_conf.rss_key_len = (I40E_VFQF_HKEY_MAX_INDEX + 1) *
2569                         sizeof(uint32_t);
2570         }
2571
2572         return i40evf_hw_rss_hash_set(vf, &rss_conf);
2573 }
2574
2575 static int
2576 i40evf_dev_rss_hash_update(struct rte_eth_dev *dev,
2577                            struct rte_eth_rss_conf *rss_conf)
2578 {
2579         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2580         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2581         uint64_t rss_hf = rss_conf->rss_hf & vf->adapter->flow_types_mask;
2582         uint64_t hena;
2583
2584         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2585         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2586
2587         if (!(hena & vf->adapter->pctypes_mask)) { /* RSS disabled */
2588                 if (rss_hf != 0) /* Enable RSS */
2589                         return -EINVAL;
2590                 return 0;
2591         }
2592
2593         /* RSS enabled */
2594         if (rss_hf == 0) /* Disable RSS */
2595                 return -EINVAL;
2596
2597         return i40evf_hw_rss_hash_set(vf, rss_conf);
2598 }
2599
2600 static int
2601 i40evf_dev_rss_hash_conf_get(struct rte_eth_dev *dev,
2602                              struct rte_eth_rss_conf *rss_conf)
2603 {
2604         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2605         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2606         uint64_t hena;
2607
2608         i40evf_get_rss_key(&vf->vsi, rss_conf->rss_key,
2609                            &rss_conf->rss_key_len);
2610
2611         hena = (uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(0));
2612         hena |= ((uint64_t)i40e_read_rx_ctl(hw, I40E_VFQF_HENA(1))) << 32;
2613         rss_conf->rss_hf = i40e_parse_hena(vf->adapter, hena);
2614
2615         return 0;
2616 }
2617
2618 static int
2619 i40evf_dev_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2620 {
2621         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2622         struct rte_eth_dev_data *dev_data = vf->dev_data;
2623         uint32_t frame_size = mtu + I40E_ETH_OVERHEAD;
2624         int ret = 0;
2625
2626         /* check if mtu is within the allowed range */
2627         if ((mtu < ETHER_MIN_MTU) || (frame_size > I40E_FRAME_SIZE_MAX))
2628                 return -EINVAL;
2629
2630         /* mtu setting is forbidden if port is start */
2631         if (dev_data->dev_started) {
2632                 PMD_DRV_LOG(ERR, "port %d must be stopped before configuration",
2633                             dev_data->port_id);
2634                 return -EBUSY;
2635         }
2636
2637         if (frame_size > ETHER_MAX_LEN)
2638                 dev_data->dev_conf.rxmode.jumbo_frame = 1;
2639         else
2640                 dev_data->dev_conf.rxmode.jumbo_frame = 0;
2641
2642         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2643
2644         return ret;
2645 }
2646
2647 static void
2648 i40evf_set_default_mac_addr(struct rte_eth_dev *dev,
2649                             struct ether_addr *mac_addr)
2650 {
2651         struct i40e_vf *vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2652
2653         if (!is_valid_assigned_ether_addr(mac_addr)) {
2654                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2655                 return;
2656         }
2657
2658         if (is_same_ether_addr(mac_addr, dev->data->mac_addrs))
2659                 return;
2660
2661         if (vf->flags & I40E_FLAG_VF_MAC_BY_PF)
2662                 return;
2663
2664         i40evf_del_mac_addr_by_addr(dev, dev->data->mac_addrs);
2665
2666         i40evf_add_mac_addr(dev, mac_addr, 0, 0);
2667 }