drivers/net/i40e/i40e_fdir.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_ether.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_log.h>
  16 #include <rte_memzone.h>
  17 #include <rte_malloc.h>
  18 #include <rte_arp.h>
  19 #include <rte_ip.h>
  20 #include <rte_udp.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_hash_crc.h>
  24
  25 #include "i40e_logs.h"
  26 #include "base/i40e_type.h"
  27 #include "base/i40e_prototype.h"
  28 #include "i40e_ethdev.h"
  29 #include "i40e_rxtx.h"
  30
  31 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  32 #ifndef IPV6_ADDR_LEN
  33 #define IPV6_ADDR_LEN              16
  34 #endif
  35
  36 #define I40E_FDIR_PKT_LEN                   512
  37 #define I40E_FDIR_IP_DEFAULT_LEN            420
  38 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  39 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  40 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  41 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  42
  43 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  44 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  45 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  46 #define I40E_FDIR_GTP_DEFAULT_LEN           384
  47 #define I40E_FDIR_INNER_IP_DEFAULT_LEN      384
  48 #define I40E_FDIR_INNER_IPV6_DEFAULT_LEN    344
  49
  50 #define I40E_FDIR_GTPC_DST_PORT             2123
  51 #define I40E_FDIR_GTPU_DST_PORT             2152
  52 #define I40E_FDIR_GTP_VER_FLAG_0X30         0x30
  53 #define I40E_FDIR_GTP_VER_FLAG_0X32         0x32
  54 #define I40E_FDIR_GTP_MSG_TYPE_0X01         0x01
  55 #define I40E_FDIR_GTP_MSG_TYPE_0XFF         0xFF
  56
  57 /* Wait time for fdir filter programming */
  58 #define I40E_FDIR_MAX_WAIT_US 10000
  59
  60 /* Wait count and interval for fdir filter flush */
  61 #define I40E_FDIR_FLUSH_RETRY       50
  62 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  63
  64 #define I40E_COUNTER_PF           2
  65 /* Statistic counter index for one pf */
  66 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  67
  68 #define I40E_FDIR_FLOWS ( \
  69         (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \
  70         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  71         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  72         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  73         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  74         (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \
  75         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  76         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  77         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  78         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
  79         (1ULL << RTE_ETH_FLOW_L2_PAYLOAD))
  80
  81 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
  82                         enum i40e_filter_pctype pctype,
  83                         const struct rte_eth_fdir_filter *filter,
  84                         bool add);
  85 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
  86                          struct i40e_fdir_filter *filter);
  87 static struct i40e_fdir_filter *
  88 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
  89                         const struct i40e_fdir_input *input);
  90 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
  91                                    struct i40e_fdir_filter *filter);
  92 static int
  93 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
  94                                   enum i40e_filter_pctype pctype,
  95                                   const struct i40e_fdir_filter_conf *filter,
  96                                   bool add);
  97
  98 static int
  99 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 100 {
 101         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 102         struct i40e_hmc_obj_rxq rx_ctx;
 103         int err = I40E_SUCCESS;
 104
 105         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 106         /* Init the RX queue in hardware */
 107         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 108         rx_ctx.hbuff = 0;
 109         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 110         rx_ctx.qlen = rxq->nb_rx_desc;
 111 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 112         rx_ctx.dsize = 1;
 113 #endif
 114         rx_ctx.dtype = i40e_header_split_none;
 115         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 116         rx_ctx.rxmax = ETHER_MAX_LEN;
 117         rx_ctx.tphrdesc_ena = 1;
 118         rx_ctx.tphwdesc_ena = 1;
 119         rx_ctx.tphdata_ena = 1;
 120         rx_ctx.tphhead_ena = 1;
 121         rx_ctx.lrxqthresh = 2;
 122         rx_ctx.crcstrip = 0;
 123         rx_ctx.l2tsel = 1;
 124         rx_ctx.showiv = 0;
 125         rx_ctx.prefena = 1;
 126
 127         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 128         if (err != I40E_SUCCESS) {
 129                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 130                 return err;
 131         }
 132         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 133         if (err != I40E_SUCCESS) {
 134                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 135                 return err;
 136         }
 137         rxq->qrx_tail = hw->hw_addr +
 138                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 139
 140         rte_wmb();
 141         /* Init the RX tail regieter. */
 142         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 143
 144         return err;
 145 }
 146
 147 /*
 148  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 149  * @pf: board private structure
 150  */
 151 int
 152 i40e_fdir_setup(struct i40e_pf *pf)
 153 {
 154         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 155         struct i40e_vsi *vsi;
 156         int err = I40E_SUCCESS;
 157         char z_name[RTE_MEMZONE_NAMESIZE];
 158         const struct rte_memzone *mz = NULL;
 159         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 160
 161         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 162                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 163                 return I40E_NOT_SUPPORTED;
 164         }
 165
 166         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 167                         " num_filters_best_effort = %u.",
 168                         hw->func_caps.fd_filters_guaranteed,
 169                         hw->func_caps.fd_filters_best_effort);
 170
 171         vsi = pf->fdir.fdir_vsi;
 172         if (vsi) {
 173                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 174                 return I40E_SUCCESS;
 175         }
 176         /* make new FDIR VSI */
 177         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 178         if (!vsi) {
 179                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 180                 return I40E_ERR_NO_AVAILABLE_VSI;
 181         }
 182         pf->fdir.fdir_vsi = vsi;
 183
 184         /*Fdir tx queue setup*/
 185         err = i40e_fdir_setup_tx_resources(pf);
 186         if (err) {
 187                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 188                 goto fail_setup_tx;
 189         }
 190
 191         /*Fdir rx queue setup*/
 192         err = i40e_fdir_setup_rx_resources(pf);
 193         if (err) {
 194                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 195                 goto fail_setup_rx;
 196         }
 197
 198         err = i40e_tx_queue_init(pf->fdir.txq);
 199         if (err) {
 200                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 201                 goto fail_mem;
 202         }
 203
 204         /* need switch on before dev start*/
 205         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 206         if (err) {
 207                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 208                 goto fail_mem;
 209         }
 210
 211         /* Init the rx queue in hardware */
 212         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 213         if (err) {
 214                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 215                 goto fail_mem;
 216         }
 217
 218         /* switch on rx queue */
 219         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 220         if (err) {
 221                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 222                 goto fail_mem;
 223         }
 224
 225         /* reserve memory for the fdir programming packet */
 226         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 227                         eth_dev->device->driver->name,
 228                         I40E_FDIR_MZ_NAME,
 229                         eth_dev->data->port_id);
 230         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 231         if (!mz) {
 232                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 233                                  "flow director program packet.");
 234                 err = I40E_ERR_NO_MEMORY;
 235                 goto fail_mem;
 236         }
 237         pf->fdir.prg_pkt = mz->addr;
 238         pf->fdir.dma_addr = mz->iova;
 239
 240         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 241         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 242                     vsi->base_queue);
 243         return I40E_SUCCESS;
 244
 245 fail_mem:
 246         i40e_dev_rx_queue_release(pf->fdir.rxq);
 247         pf->fdir.rxq = NULL;
 248 fail_setup_rx:
 249         i40e_dev_tx_queue_release(pf->fdir.txq);
 250         pf->fdir.txq = NULL;
 251 fail_setup_tx:
 252         i40e_vsi_release(vsi);
 253         pf->fdir.fdir_vsi = NULL;
 254         return err;
 255 }
 256
 257 /*
 258  * i40e_fdir_teardown - release the Flow Director resources
 259  * @pf: board private structure
 260  */
 261 void
 262 i40e_fdir_teardown(struct i40e_pf *pf)
 263 {
 264         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 265         struct i40e_vsi *vsi;
 266
 267         vsi = pf->fdir.fdir_vsi;
 268         if (!vsi)
 269                 return;
 270         int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 271         if (err)
 272                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
 273         err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 274         if (err)
 275                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
 276         i40e_dev_rx_queue_release(pf->fdir.rxq);
 277         pf->fdir.rxq = NULL;
 278         i40e_dev_tx_queue_release(pf->fdir.txq);
 279         pf->fdir.txq = NULL;
 280         i40e_vsi_release(vsi);
 281         pf->fdir.fdir_vsi = NULL;
 282 }
 283
 284 /* check whether the flow director table in empty */
 285 static inline int
 286 i40e_fdir_empty(struct i40e_hw *hw)
 287 {
 288         uint32_t guarant_cnt, best_cnt;
 289
 290         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 291                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 292                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 293         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 294                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 295                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 296         if (best_cnt + guarant_cnt > 0)
 297                 return -1;
 298
 299         return 0;
 300 }
 301
 302 /*
 303  * Initialize the configuration about bytes stream extracted as flexible payload
 304  * and mask setting
 305  */
 306 static inline void
 307 i40e_init_flx_pld(struct i40e_pf *pf)
 308 {
 309         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 310         uint8_t pctype;
 311         int i, index;
 312         uint16_t flow_type;
 313
 314         /*
 315          * Define the bytes stream extracted as flexible payload in
 316          * field vector. By default, select 8 words from the beginning
 317          * of payload as flexible payload.
 318          */
 319         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 320                 index = i * I40E_MAX_FLXPLD_FIED;
 321                 pf->fdir.flex_set[index].src_offset = 0;
 322                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 323                 pf->fdir.flex_set[index].dst_offset = 0;
 324                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 325                 I40E_WRITE_REG(hw,
 326                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 327                 I40E_WRITE_REG(hw,
 328                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 329         }
 330
 331         /* initialize the masks */
 332         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 333              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 334                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
 335
 336                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
 337                         continue;
 338                 pf->fdir.flex_mask[pctype].word_mask = 0;
 339                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 340                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 341                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 342                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 343                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 344                 }
 345         }
 346 }
 347
 348 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 349         if ((flex_pit2).src_offset < \
 350                 (flex_pit1).src_offset + (flex_pit1).size) { \
 351                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 352                         " less than than previous offset" \
 353                         " + previous FSIZE."); \
 354                 return -EINVAL; \
 355         } \
 356 } while (0)
 357
 358 /*
 359  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 360  * and the flex_pit will be sorted by it's src_offset value
 361  */
 362 static inline uint16_t
 363 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 364                         struct i40e_fdir_flex_pit *flex_pit)
 365 {
 366         uint16_t src_tmp, size, num = 0;
 367         uint16_t i, k, j = 0;
 368
 369         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 370                 size = 1;
 371                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 372                         if (src_offset[j + 1] == src_offset[j] + 1)
 373                                 size++;
 374                         else
 375                                 break;
 376                 }
 377                 src_tmp = src_offset[j] + 1 - size;
 378                 /* the flex_pit need to be sort by src_offset */
 379                 for (i = 0; i < num; i++) {
 380                         if (src_tmp < flex_pit[i].src_offset)
 381                                 break;
 382                 }
 383                 /* if insert required, move backward */
 384                 for (k = num; k > i; k--)
 385                         flex_pit[k] = flex_pit[k - 1];
 386                 /* insert */
 387                 flex_pit[i].dst_offset = j + 1 - size;
 388                 flex_pit[i].src_offset = src_tmp;
 389                 flex_pit[i].size = size;
 390                 j++;
 391                 num++;
 392         }
 393         return num;
 394 }
 395
 396 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 397 static inline int
 398 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 399 {
 400         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 401         uint16_t num, i;
 402
 403         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 404                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 405                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 406                         return -EINVAL;
 407                 }
 408         }
 409
 410         memset(flex_pit, 0, sizeof(flex_pit));
 411         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 412         if (num > I40E_MAX_FLXPLD_FIED) {
 413                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 414                 return -EINVAL;
 415         }
 416         for (i = 0; i < num; i++) {
 417                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 418                         flex_pit[i].src_offset & 0x01) {
 419                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 420                                 " in word");
 421                         return -EINVAL;
 422                 }
 423                 if (i != num - 1)
 424                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 425         }
 426         return 0;
 427 }
 428
 429 /*
 430  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 431  * arguments are valid
 432  */
 433 static int
 434 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
 435                           const struct rte_eth_fdir_flex_conf *conf)
 436 {
 437         const struct rte_eth_flex_payload_cfg *flex_cfg;
 438         const struct rte_eth_fdir_flex_mask *flex_mask;
 439         uint16_t mask_tmp;
 440         uint8_t nb_bitmask;
 441         uint16_t i, j;
 442         int ret = 0;
 443         enum i40e_filter_pctype pctype;
 444
 445         if (conf == NULL) {
 446                 PMD_DRV_LOG(INFO, "NULL pointer.");
 447                 return -EINVAL;
 448         }
 449         /* check flexible payload setting configuration */
 450         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 451                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 452                 return -EINVAL;
 453         }
 454         for (i = 0; i < conf->nb_payloads; i++) {
 455                 flex_cfg = &conf->flex_set[i];
 456                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 457                         PMD_DRV_LOG(ERR, "invalid payload type.");
 458                         return -EINVAL;
 459                 }
 460                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 461                 if (ret < 0) {
 462                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 463                         return -EINVAL;
 464                 }
 465         }
 466
 467         /* check flex mask setting configuration */
 468         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 469                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 470                 return -EINVAL;
 471         }
 472         for (i = 0; i < conf->nb_flexmasks; i++) {
 473                 flex_mask = &conf->flex_mask[i];
 474                 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
 475                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
 476                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 477                         return -EINVAL;
 478                 }
 479                 nb_bitmask = 0;
 480                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 481                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 482                                              flex_mask->mask[j + 1]);
 483                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 484                                 nb_bitmask++;
 485                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 486                                         PMD_DRV_LOG(ERR, " exceed maximal"
 487                                                 " number of bitmasks.");
 488                                         return -EINVAL;
 489                                 }
 490                         }
 491                 }
 492         }
 493         return 0;
 494 }
 495
 496 /*
 497  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 498  * @pf: board private structure
 499  * @cfg: the rule how bytes stream is extracted as flexible payload
 500  */
 501 static void
 502 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 503                          const struct rte_eth_flex_payload_cfg *cfg)
 504 {
 505         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 506         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 507         uint32_t flx_pit, flx_ort;
 508         uint16_t num, min_next_off;  /* in words */
 509         uint8_t field_idx = 0;
 510         uint8_t layer_idx = 0;
 511         uint16_t i;
 512
 513         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 514                 layer_idx = I40E_FLXPLD_L2_IDX;
 515         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 516                 layer_idx = I40E_FLXPLD_L3_IDX;
 517         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 518                 layer_idx = I40E_FLXPLD_L4_IDX;
 519
 520         memset(flex_pit, 0, sizeof(flex_pit));
 521         num = RTE_MIN(i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit),
 522                       RTE_DIM(flex_pit));
 523
 524         if (num) {
 525                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
 526                           (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
 527                           (layer_idx * I40E_MAX_FLXPLD_FIED);
 528                 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
 529         }
 530
 531         for (i = 0; i < num; i++) {
 532                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 533                 /* record the info in fdir structure */
 534                 pf->fdir.flex_set[field_idx].src_offset =
 535                         flex_pit[i].src_offset / sizeof(uint16_t);
 536                 pf->fdir.flex_set[field_idx].size =
 537                         flex_pit[i].size / sizeof(uint16_t);
 538                 pf->fdir.flex_set[field_idx].dst_offset =
 539                         flex_pit[i].dst_offset / sizeof(uint16_t);
 540                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 541                                 pf->fdir.flex_set[field_idx].size,
 542                                 pf->fdir.flex_set[field_idx].dst_offset);
 543
 544                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 545         }
 546         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 547                                 pf->fdir.flex_set[field_idx].size;
 548
 549         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 550                 /* set the non-used register obeying register's constrain */
 551                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 552                            NONUSE_FLX_PIT_DEST_OFF);
 553                 I40E_WRITE_REG(hw,
 554                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 555                         flx_pit);
 556                 min_next_off++;
 557         }
 558 }
 559
 560 /*
 561  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 562  * @pf: board private structure
 563  * @pctype: packet classify type
 564  * @flex_masks: mask for flexible payload
 565  */
 566 static void
 567 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 568                 enum i40e_filter_pctype pctype,
 569                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 570 {
 571         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 572         struct i40e_fdir_flex_mask *flex_mask;
 573         uint32_t flxinset, fd_mask;
 574         uint16_t mask_tmp;
 575         uint8_t i, nb_bitmask = 0;
 576
 577         flex_mask = &pf->fdir.flex_mask[pctype];
 578         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 579         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 580                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 581                 if (mask_tmp != 0x0) {
 582                         flex_mask->word_mask |=
 583                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 584                         if (mask_tmp != UINT16_MAX) {
 585                                 /* set bit mask */
 586                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 587                                 flex_mask->bitmask[nb_bitmask].offset =
 588                                         i / sizeof(uint16_t);
 589                                 nb_bitmask++;
 590                         }
 591                 }
 592         }
 593         /* write mask to hw */
 594         flxinset = (flex_mask->word_mask <<
 595                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 596                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 597         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 598
 599         for (i = 0; i < nb_bitmask; i++) {
 600                 fd_mask = (flex_mask->bitmask[i].mask <<
 601                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 602                         I40E_PRTQF_FD_MSK_MASK_MASK;
 603                 fd_mask |= ((flex_mask->bitmask[i].offset +
 604                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 605                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 606                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 607                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 608         }
 609 }
 610
 611 /*
 612  * Configure flow director related setting
 613  */
 614 int
 615 i40e_fdir_configure(struct rte_eth_dev *dev)
 616 {
 617         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 618         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 619         struct rte_eth_fdir_flex_conf *conf;
 620         enum i40e_filter_pctype pctype;
 621         uint32_t val;
 622         uint8_t i;
 623         int ret = 0;
 624
 625         /*
 626         * configuration need to be done before
 627         * flow director filters are added
 628         * If filters exist, flush them.
 629         */
 630         if (i40e_fdir_empty(hw) < 0) {
 631                 ret = i40e_fdir_flush(dev);
 632                 if (ret) {
 633                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 634                         return ret;
 635                 }
 636         }
 637
 638         /* enable FDIR filter */
 639         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 640         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 641         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 642
 643         i40e_init_flx_pld(pf); /* set flex config to default value */
 644
 645         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 646         ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
 647         if (ret < 0) {
 648                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 649                 return -EINVAL;
 650         }
 651
 652         if (!pf->support_multi_driver) {
 653                 /* configure flex payload */
 654                 for (i = 0; i < conf->nb_payloads; i++)
 655                         i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 656                 /* configure flex mask*/
 657                 for (i = 0; i < conf->nb_flexmasks; i++) {
 658                         if (hw->mac.type == I40E_MAC_X722) {
 659                                 /* get pctype value in fd pctype register */
 660                                 pctype = (enum i40e_filter_pctype)
 661                                           i40e_read_rx_ctl(hw,
 662                                                 I40E_GLQF_FD_PCTYPES(
 663                                                 (int)i40e_flowtype_to_pctype(
 664                                                 pf->adapter,
 665                                                 conf->flex_mask[i].flow_type)));
 666                         } else {
 667                                 pctype = i40e_flowtype_to_pctype(pf->adapter,
 668                                                   conf->flex_mask[i].flow_type);
 669                         }
 670
 671                         i40e_set_flex_mask_on_pctype(pf, pctype,
 672                                                      &conf->flex_mask[i]);
 673                 }
 674         } else {
 675                 PMD_DRV_LOG(ERR, "Not support flexible payload.");
 676         }
 677
 678         return ret;
 679 }
 680
 681 static inline int
 682 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 683                            unsigned char *raw_pkt,
 684                            bool vlan)
 685 {
 686         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 687         uint16_t *ether_type;
 688         uint8_t len = 2 * sizeof(struct ether_addr);
 689         struct ipv4_hdr *ip;
 690         struct ipv6_hdr *ip6;
 691         static const uint8_t next_proto[] = {
 692                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 693                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 694                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 695                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 696                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 697                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 698                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 699                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 700                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 701                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 702         };
 703
 704         raw_pkt += 2 * sizeof(struct ether_addr);
 705         if (vlan && fdir_input->flow_ext.vlan_tci) {
 706                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 707                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 708                            &fdir_input->flow_ext.vlan_tci,
 709                            sizeof(uint16_t));
 710                 raw_pkt += sizeof(vlan_frame);
 711                 len += sizeof(vlan_frame);
 712         }
 713         ether_type = (uint16_t *)raw_pkt;
 714         raw_pkt += sizeof(uint16_t);
 715         len += sizeof(uint16_t);
 716
 717         switch (fdir_input->flow_type) {
 718         case RTE_ETH_FLOW_L2_PAYLOAD:
 719                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 720                 break;
 721         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 722         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 723         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 724         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 725         case RTE_ETH_FLOW_FRAG_IPV4:
 726                 ip = (struct ipv4_hdr *)raw_pkt;
 727
 728                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 729                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 730                 /* set len to by default */
 731                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 732                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 733                                         fdir_input->flow.ip4_flow.proto :
 734                                         next_proto[fdir_input->flow_type];
 735                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 736                                         fdir_input->flow.ip4_flow.ttl :
 737                                         I40E_FDIR_IP_DEFAULT_TTL;
 738                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 739                 /*
 740                  * The source and destination fields in the transmitted packet
 741                  * need to be presented in a reversed order with respect
 742                  * to the expected received packets.
 743                  */
 744                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 745                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 746                 len += sizeof(struct ipv4_hdr);
 747                 break;
 748         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 749         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 750         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 751         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 752         case RTE_ETH_FLOW_FRAG_IPV6:
 753                 ip6 = (struct ipv6_hdr *)raw_pkt;
 754
 755                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 756                 ip6->vtc_flow =
 757                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 758                                          (fdir_input->flow.ipv6_flow.tc <<
 759                                           I40E_FDIR_IPv6_TC_OFFSET));
 760                 ip6->payload_len =
 761                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 762                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 763                                         fdir_input->flow.ipv6_flow.proto :
 764                                         next_proto[fdir_input->flow_type];
 765                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 766                                         fdir_input->flow.ipv6_flow.hop_limits :
 767                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 768                 /*
 769                  * The source and destination fields in the transmitted packet
 770                  * need to be presented in a reversed order with respect
 771                  * to the expected received packets.
 772                  */
 773                 rte_memcpy(&(ip6->src_addr),
 774                            &(fdir_input->flow.ipv6_flow.dst_ip),
 775                            IPV6_ADDR_LEN);
 776                 rte_memcpy(&(ip6->dst_addr),
 777                            &(fdir_input->flow.ipv6_flow.src_ip),
 778                            IPV6_ADDR_LEN);
 779                 len += sizeof(struct ipv6_hdr);
 780                 break;
 781         default:
 782                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 783                             fdir_input->flow_type);
 784                 return -1;
 785         }
 786         return len;
 787 }
 788
 789
 790 /*
 791  * i40e_fdir_construct_pkt - construct packet based on fields in input
 792  * @pf: board private structure
 793  * @fdir_input: input set of the flow director entry
 794  * @raw_pkt: a packet to be constructed
 795  */
 796 static int
 797 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 798                              const struct rte_eth_fdir_input *fdir_input,
 799                              unsigned char *raw_pkt)
 800 {
 801         unsigned char *payload, *ptr;
 802         struct udp_hdr *udp;
 803         struct tcp_hdr *tcp;
 804         struct sctp_hdr *sctp;
 805         uint8_t size, dst = 0;
 806         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 807         int len;
 808
 809         /* fill the ethernet and IP head */
 810         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 811                                          !!fdir_input->flow_ext.vlan_tci);
 812         if (len < 0)
 813                 return -EINVAL;
 814
 815         /* fill the L4 head */
 816         switch (fdir_input->flow_type) {
 817         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 818                 udp = (struct udp_hdr *)(raw_pkt + len);
 819                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 820                 /*
 821                  * The source and destination fields in the transmitted packet
 822                  * need to be presented in a reversed order with respect
 823                  * to the expected received packets.
 824                  */
 825                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 826                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 827                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 828                 break;
 829
 830         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 831                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 832                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 833                 /*
 834                  * The source and destination fields in the transmitted packet
 835                  * need to be presented in a reversed order with respect
 836                  * to the expected received packets.
 837                  */
 838                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 839                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 840                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 841                 break;
 842
 843         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 844                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 845                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 846                 /*
 847                  * The source and destination fields in the transmitted packet
 848                  * need to be presented in a reversed order with respect
 849                  * to the expected received packets.
 850                  */
 851                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 852                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 853                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 854                 break;
 855
 856         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 857         case RTE_ETH_FLOW_FRAG_IPV4:
 858                 payload = raw_pkt + len;
 859                 set_idx = I40E_FLXPLD_L3_IDX;
 860                 break;
 861
 862         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 863                 udp = (struct udp_hdr *)(raw_pkt + len);
 864                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 865                 /*
 866                  * The source and destination fields in the transmitted packet
 867                  * need to be presented in a reversed order with respect
 868                  * to the expected received packets.
 869                  */
 870                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 871                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 872                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 873                 break;
 874
 875         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 876                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 877                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 878                 /*
 879                  * The source and destination fields in the transmitted packet
 880                  * need to be presented in a reversed order with respect
 881                  * to the expected received packets.
 882                  */
 883                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 884                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 885                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 886                 break;
 887
 888         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 889                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 890                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 891                 /*
 892                  * The source and destination fields in the transmitted packet
 893                  * need to be presented in a reversed order with respect
 894                  * to the expected received packets.
 895                  */
 896                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 897                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 898                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 899                 break;
 900
 901         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 902         case RTE_ETH_FLOW_FRAG_IPV6:
 903                 payload = raw_pkt + len;
 904                 set_idx = I40E_FLXPLD_L3_IDX;
 905                 break;
 906         case RTE_ETH_FLOW_L2_PAYLOAD:
 907                 payload = raw_pkt + len;
 908                 /*
 909                  * ARP packet is a special case on which the payload
 910                  * starts after the whole ARP header
 911                  */
 912                 if (fdir_input->flow.l2_flow.ether_type ==
 913                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 914                         payload += sizeof(struct arp_hdr);
 915                 set_idx = I40E_FLXPLD_L2_IDX;
 916                 break;
 917         default:
 918                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 919                 return -EINVAL;
 920         }
 921
 922         /* fill the flexbytes to payload */
 923         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 924                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 925                 size = pf->fdir.flex_set[pit_idx].size;
 926                 if (size == 0)
 927                         continue;
 928                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 929                 ptr = payload +
 930                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 931                 rte_memcpy(ptr,
 932                                  &fdir_input->flow_ext.flexbytes[dst],
 933                                  size * sizeof(uint16_t));
 934         }
 935
 936         return 0;
 937 }
 938
 939 static struct i40e_customized_pctype *
 940 i40e_flow_fdir_find_customized_pctype(struct i40e_pf *pf, uint8_t pctype)
 941 {
 942         struct i40e_customized_pctype *cus_pctype;
 943         enum i40e_new_pctype i = I40E_CUSTOMIZED_GTPC;
 944
 945         for (; i < I40E_CUSTOMIZED_MAX; i++) {
 946                 cus_pctype = &pf->customized_pctype[i];
 947                 if (pctype == cus_pctype->pctype)
 948                         return cus_pctype;
 949         }
 950         return NULL;
 951 }
 952
 953 static inline int
 954 i40e_flow_fdir_fill_eth_ip_head(struct i40e_pf *pf,
 955                                 const struct i40e_fdir_input *fdir_input,
 956                                 unsigned char *raw_pkt,
 957                                 bool vlan)
 958 {
 959         struct i40e_customized_pctype *cus_pctype = NULL;
 960         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 961         uint16_t *ether_type;
 962         uint8_t len = 2 * sizeof(struct ether_addr);
 963         struct ipv4_hdr *ip;
 964         struct ipv6_hdr *ip6;
 965         uint8_t pctype = fdir_input->pctype;
 966         bool is_customized_pctype = fdir_input->flow_ext.customized_pctype;
 967         static const uint8_t next_proto[] = {
 968                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
 969                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
 970                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
 971                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
 972                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
 973                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
 974                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
 975                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
 976                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
 977                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
 978         };
 979
 980         raw_pkt += 2 * sizeof(struct ether_addr);
 981         if (vlan && fdir_input->flow_ext.vlan_tci) {
 982                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 983                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 984                            &fdir_input->flow_ext.vlan_tci,
 985                            sizeof(uint16_t));
 986                 raw_pkt += sizeof(vlan_frame);
 987                 len += sizeof(vlan_frame);
 988         }
 989         ether_type = (uint16_t *)raw_pkt;
 990         raw_pkt += sizeof(uint16_t);
 991         len += sizeof(uint16_t);
 992
 993         if (is_customized_pctype) {
 994                 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
 995                 if (!cus_pctype) {
 996                         PMD_DRV_LOG(ERR, "unknown pctype %u.",
 997                                     fdir_input->pctype);
 998                         return -1;
 999                 }
1000         }
1001
1002         if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD)
1003                 *ether_type = fdir_input->flow.l2_flow.ether_type;
1004         else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
1005                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
1006                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
1007                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1008                  pctype == I40E_FILTER_PCTYPE_FRAG_IPV4 ||
1009                  is_customized_pctype) {
1010                 ip = (struct ipv4_hdr *)raw_pkt;
1011
1012                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
1013                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1014                 /* set len to by default */
1015                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
1016                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
1017                         fdir_input->flow.ip4_flow.ttl :
1018                         I40E_FDIR_IP_DEFAULT_TTL;
1019                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
1020                 /**
1021                  * The source and destination fields in the transmitted packet
1022                  * need to be presented in a reversed order with respect
1023                  * to the expected received packets.
1024                  */
1025                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1026                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1027
1028                 if (!is_customized_pctype)
1029                         ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
1030                                 fdir_input->flow.ip4_flow.proto :
1031                                 next_proto[fdir_input->pctype];
1032                 else if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1033                          cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1034                          cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1035                          cus_pctype->index == I40E_CUSTOMIZED_GTPU)
1036                         ip->next_proto_id = IPPROTO_UDP;
1037                 len += sizeof(struct ipv4_hdr);
1038         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1039                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1040                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1041                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1042                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1043                 ip6 = (struct ipv6_hdr *)raw_pkt;
1044
1045                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
1046                 ip6->vtc_flow =
1047                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1048                                          (fdir_input->flow.ipv6_flow.tc <<
1049                                           I40E_FDIR_IPv6_TC_OFFSET));
1050                 ip6->payload_len =
1051                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1052                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
1053                         fdir_input->flow.ipv6_flow.proto :
1054                         next_proto[fdir_input->pctype];
1055                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
1056                         fdir_input->flow.ipv6_flow.hop_limits :
1057                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1058                 /**
1059                  * The source and destination fields in the transmitted packet
1060                  * need to be presented in a reversed order with respect
1061                  * to the expected received packets.
1062                  */
1063                 rte_memcpy(&ip6->src_addr,
1064                            &fdir_input->flow.ipv6_flow.dst_ip,
1065                            IPV6_ADDR_LEN);
1066                 rte_memcpy(&ip6->dst_addr,
1067                            &fdir_input->flow.ipv6_flow.src_ip,
1068                            IPV6_ADDR_LEN);
1069                 len += sizeof(struct ipv6_hdr);
1070         } else {
1071                 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1072                             fdir_input->pctype);
1073                 return -1;
1074         }
1075
1076         return len;
1077 }
1078
1079 /**
1080  * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1081  * @pf: board private structure
1082  * @fdir_input: input set of the flow director entry
1083  * @raw_pkt: a packet to be constructed
1084  */
1085 static int
1086 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1087                              const struct i40e_fdir_input *fdir_input,
1088                              unsigned char *raw_pkt)
1089 {
1090         unsigned char *payload = NULL;
1091         unsigned char *ptr;
1092         struct udp_hdr *udp;
1093         struct tcp_hdr *tcp;
1094         struct sctp_hdr *sctp;
1095         struct rte_flow_item_gtp *gtp;
1096         struct ipv4_hdr *gtp_ipv4;
1097         struct ipv6_hdr *gtp_ipv6;
1098         uint8_t size, dst = 0;
1099         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1100         int len;
1101         uint8_t pctype = fdir_input->pctype;
1102         struct i40e_customized_pctype *cus_pctype;
1103
1104         /* raw pcket template - just copy contents of the raw packet */
1105         if (fdir_input->flow_ext.pkt_template) {
1106                 memcpy(raw_pkt, fdir_input->flow.raw_flow.packet,
1107                        fdir_input->flow.raw_flow.length);
1108                 return 0;
1109         }
1110
1111         /* fill the ethernet and IP head */
1112         len = i40e_flow_fdir_fill_eth_ip_head(pf, fdir_input, raw_pkt,
1113                                               !!fdir_input->flow_ext.vlan_tci);
1114         if (len < 0)
1115                 return -EINVAL;
1116
1117         /* fill the L4 head */
1118         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
1119                 udp = (struct udp_hdr *)(raw_pkt + len);
1120                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1121                 /**
1122                  * The source and destination fields in the transmitted packet
1123                  * need to be presented in a reversed order with respect
1124                  * to the expected received packets.
1125                  */
1126                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1127                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1128                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1129         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
1130                 tcp = (struct tcp_hdr *)(raw_pkt + len);
1131                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1132                 /**
1133                  * The source and destination fields in the transmitted packet
1134                  * need to be presented in a reversed order with respect
1135                  * to the expected received packets.
1136                  */
1137                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1138                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1139                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1140         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) {
1141                 sctp = (struct sctp_hdr *)(raw_pkt + len);
1142                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1143                 /**
1144                  * The source and destination fields in the transmitted packet
1145                  * need to be presented in a reversed order with respect
1146                  * to the expected received packets.
1147                  */
1148                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1149                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1150                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1151         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1152                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1153                 payload = raw_pkt + len;
1154                 set_idx = I40E_FLXPLD_L3_IDX;
1155         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
1156                 udp = (struct udp_hdr *)(raw_pkt + len);
1157                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1158                 /**
1159                  * The source and destination fields in the transmitted packet
1160                  * need to be presented in a reversed order with respect
1161                  * to the expected received packets.
1162                  */
1163                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1164                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1165                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1166         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
1167                 tcp = (struct tcp_hdr *)(raw_pkt + len);
1168                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1169                 /**
1170                  * The source and destination fields in the transmitted packet
1171                  * need to be presented in a reversed order with respect
1172                  * to the expected received packets.
1173                  */
1174                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1175                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1176                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1177         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) {
1178                 sctp = (struct sctp_hdr *)(raw_pkt + len);
1179                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1180                 /**
1181                  * The source and destination fields in the transmitted packet
1182                  * need to be presented in a reversed order with respect
1183                  * to the expected received packets.
1184                  */
1185                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1186                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1187                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1188         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1189                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1190                 payload = raw_pkt + len;
1191                 set_idx = I40E_FLXPLD_L3_IDX;
1192         } else if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD) {
1193                 payload = raw_pkt + len;
1194                 /**
1195                  * ARP packet is a special case on which the payload
1196                  * starts after the whole ARP header
1197                  */
1198                 if (fdir_input->flow.l2_flow.ether_type ==
1199                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
1200                         payload += sizeof(struct arp_hdr);
1201                 set_idx = I40E_FLXPLD_L2_IDX;
1202         } else if (fdir_input->flow_ext.customized_pctype) {
1203                 /* If customized pctype is used */
1204                 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1205                 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1206                     cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1207                     cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1208                     cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1209                         udp = (struct udp_hdr *)(raw_pkt + len);
1210                         udp->dgram_len =
1211                                 rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1212
1213                         gtp = (struct rte_flow_item_gtp *)
1214                                 ((unsigned char *)udp + sizeof(struct udp_hdr));
1215                         gtp->msg_len =
1216                                 rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);
1217                         gtp->teid = fdir_input->flow.gtp_flow.teid;
1218                         gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0X01;
1219
1220                         /* GTP-C message type is not supported. */
1221                         if (cus_pctype->index == I40E_CUSTOMIZED_GTPC) {
1222                                 udp->dst_port =
1223                                       rte_cpu_to_be_16(I40E_FDIR_GTPC_DST_PORT);
1224                                 gtp->v_pt_rsv_flags =
1225                                         I40E_FDIR_GTP_VER_FLAG_0X32;
1226                         } else {
1227                                 udp->dst_port =
1228                                       rte_cpu_to_be_16(I40E_FDIR_GTPU_DST_PORT);
1229                                 gtp->v_pt_rsv_flags =
1230                                         I40E_FDIR_GTP_VER_FLAG_0X30;
1231                         }
1232
1233                         if (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) {
1234                                 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1235                                 gtp_ipv4 = (struct ipv4_hdr *)
1236                                         ((unsigned char *)gtp +
1237                                          sizeof(struct rte_flow_item_gtp));
1238                                 gtp_ipv4->version_ihl =
1239                                         I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1240                                 gtp_ipv4->next_proto_id = IPPROTO_IP;
1241                                 gtp_ipv4->total_length =
1242                                         rte_cpu_to_be_16(
1243                                                 I40E_FDIR_INNER_IP_DEFAULT_LEN);
1244                                 payload = (unsigned char *)gtp_ipv4 +
1245                                         sizeof(struct ipv4_hdr);
1246                         } else if (cus_pctype->index ==
1247                                    I40E_CUSTOMIZED_GTPU_IPV6) {
1248                                 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1249                                 gtp_ipv6 = (struct ipv6_hdr *)
1250                                         ((unsigned char *)gtp +
1251                                          sizeof(struct rte_flow_item_gtp));
1252                                 gtp_ipv6->vtc_flow =
1253                                         rte_cpu_to_be_32(
1254                                                I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1255                                                (0 << I40E_FDIR_IPv6_TC_OFFSET));
1256                                 gtp_ipv6->proto = IPPROTO_NONE;
1257                                 gtp_ipv6->payload_len =
1258                                         rte_cpu_to_be_16(
1259                                               I40E_FDIR_INNER_IPV6_DEFAULT_LEN);
1260                                 gtp_ipv6->hop_limits =
1261                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1262                                 payload = (unsigned char *)gtp_ipv6 +
1263                                         sizeof(struct ipv6_hdr);
1264                         } else
1265                                 payload = (unsigned char *)gtp +
1266                                         sizeof(struct rte_flow_item_gtp);
1267                 }
1268         } else {
1269                 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1270                             fdir_input->pctype);
1271                 return -1;
1272         }
1273
1274         /* fill the flexbytes to payload */
1275         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1276                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1277                 size = pf->fdir.flex_set[pit_idx].size;
1278                 if (size == 0)
1279                         continue;
1280                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1281                 ptr = payload +
1282                       pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1283                 (void)rte_memcpy(ptr,
1284                                  &fdir_input->flow_ext.flexbytes[dst],
1285                                  size * sizeof(uint16_t));
1286         }
1287
1288         return 0;
1289 }
1290
1291 /* Construct the tx flags */
1292 static inline uint64_t
1293 i40e_build_ctob(uint32_t td_cmd,
1294                 uint32_t td_offset,
1295                 unsigned int size,
1296                 uint32_t td_tag)
1297 {
1298         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1299                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
1300                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1301                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1302                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
1303 }
1304
1305 /*
1306  * check the programming status descriptor in rx queue.
1307  * done after Programming Flow Director is programmed on
1308  * tx queue
1309  */
1310 static inline int
1311 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1312 {
1313         volatile union i40e_rx_desc *rxdp;
1314         uint64_t qword1;
1315         uint32_t rx_status;
1316         uint32_t len, id;
1317         uint32_t error;
1318         int ret = 0;
1319
1320         rxdp = &rxq->rx_ring[rxq->rx_tail];
1321         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1322         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1323                         >> I40E_RXD_QW1_STATUS_SHIFT;
1324
1325         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1326                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1327                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1328                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1329
1330                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1331                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1332                         error = (qword1 &
1333                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1334                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1335                         if (error == (0x1 <<
1336                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1337                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1338                                             " (FD_ID %u): programming status"
1339                                             " reported.",
1340                                             rxdp->wb.qword0.hi_dword.fd_id);
1341                                 ret = -1;
1342                         } else if (error == (0x1 <<
1343                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1344                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1345                                             " (FD_ID %u): programming status"
1346                                             " reported.",
1347                                             rxdp->wb.qword0.hi_dword.fd_id);
1348                                 ret = -1;
1349                         } else
1350                                 PMD_DRV_LOG(ERR, "invalid programming status"
1351                                             " reported, error = %u.", error);
1352                 } else
1353                         PMD_DRV_LOG(INFO, "unknown programming status"
1354                                     " reported, len = %d, id = %u.", len, id);
1355                 rxdp->wb.qword1.status_error_len = 0;
1356                 rxq->rx_tail++;
1357                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1358                         rxq->rx_tail = 0;
1359                 if (rxq->rx_tail == 0)
1360                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1361                 else
1362                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1363         } else {
1364                 ret = -1;
1365         }
1366
1367         return ret;
1368 }
1369
1370 static int
1371 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1372                          struct i40e_fdir_filter *filter)
1373 {
1374         rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1375         if (input->input.flow_ext.pkt_template) {
1376                 filter->fdir.input.flow.raw_flow.packet = NULL;
1377                 filter->fdir.input.flow.raw_flow.length =
1378                         rte_hash_crc(input->input.flow.raw_flow.packet,
1379                                      input->input.flow.raw_flow.length,
1380                                      input->input.flow.raw_flow.pctype);
1381         }
1382         return 0;
1383 }
1384
1385 /* Check if there exists the flow director filter */
1386 static struct i40e_fdir_filter *
1387 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1388                         const struct i40e_fdir_input *input)
1389 {
1390         int ret;
1391
1392         if (input->flow_ext.pkt_template)
1393                 ret = rte_hash_lookup_with_hash(fdir_info->hash_table,
1394                                                 (const void *)input,
1395                                                 input->flow.raw_flow.length);
1396         else
1397                 ret = rte_hash_lookup(fdir_info->hash_table,
1398                                       (const void *)input);
1399         if (ret < 0)
1400                 return NULL;
1401
1402         return fdir_info->hash_map[ret];
1403 }
1404
1405 /* Add a flow director filter into the SW list */
1406 static int
1407 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1408 {
1409         struct i40e_fdir_info *fdir_info = &pf->fdir;
1410         int ret;
1411
1412         if (filter->fdir.input.flow_ext.pkt_template)
1413                 ret = rte_hash_add_key_with_hash(fdir_info->hash_table,
1414                                  &filter->fdir.input,
1415                                  filter->fdir.input.flow.raw_flow.length);
1416         else
1417                 ret = rte_hash_add_key(fdir_info->hash_table,
1418                                        &filter->fdir.input);
1419         if (ret < 0) {
1420                 PMD_DRV_LOG(ERR,
1421                             "Failed to insert fdir filter to hash table %d!",
1422                             ret);
1423                 return ret;
1424         }
1425         fdir_info->hash_map[ret] = filter;
1426
1427         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1428
1429         return 0;
1430 }
1431
1432 /* Delete a flow director filter from the SW list */
1433 int
1434 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1435 {
1436         struct i40e_fdir_info *fdir_info = &pf->fdir;
1437         struct i40e_fdir_filter *filter;
1438         int ret;
1439
1440         if (input->flow_ext.pkt_template)
1441                 ret = rte_hash_del_key_with_hash(fdir_info->hash_table,
1442                                                  input,
1443                                                  input->flow.raw_flow.length);
1444         else
1445                 ret = rte_hash_del_key(fdir_info->hash_table, input);
1446         if (ret < 0) {
1447                 PMD_DRV_LOG(ERR,
1448                             "Failed to delete fdir filter to hash table %d!",
1449                             ret);
1450                 return ret;
1451         }
1452         filter = fdir_info->hash_map[ret];
1453         fdir_info->hash_map[ret] = NULL;
1454
1455         TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1456         rte_free(filter);
1457
1458         return 0;
1459 }
1460
1461 /*
1462  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1463  * @pf: board private structure
1464  * @filter: fdir filter entry
1465  * @add: 0 - delete, 1 - add
1466  */
1467 int
1468 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1469                          const struct rte_eth_fdir_filter *filter,
1470                          bool add)
1471 {
1472         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1473         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1474         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1475         enum i40e_filter_pctype pctype;
1476         int ret = 0;
1477
1478         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1479                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1480                         " check the mode in fdir_conf.");
1481                 return -ENOTSUP;
1482         }
1483
1484         pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1485         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1486                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1487                 return -EINVAL;
1488         }
1489         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1490                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1491                 return -EINVAL;
1492         }
1493         if (filter->input.flow_ext.is_vf &&
1494                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1495                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1496                 return -EINVAL;
1497         }
1498
1499         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1500
1501         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1502         if (ret < 0) {
1503                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1504                 return ret;
1505         }
1506
1507         if (hw->mac.type == I40E_MAC_X722) {
1508                 /* get translated pctype value in fd pctype register */
1509                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1510                         hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1511         }
1512
1513         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1514         if (ret < 0) {
1515                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1516                             pctype);
1517                 return ret;
1518         }
1519
1520         return ret;
1521 }
1522
1523 /**
1524  * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1525  * @pf: board private structure
1526  * @filter: fdir filter entry
1527  * @add: 0 - delete, 1 - add
1528  */
1529 int
1530 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1531                               const struct i40e_fdir_filter_conf *filter,
1532                               bool add)
1533 {
1534         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1535         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1536         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1537         enum i40e_filter_pctype pctype;
1538         struct i40e_fdir_info *fdir_info = &pf->fdir;
1539         struct i40e_fdir_filter *fdir_filter, *node;
1540         struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1541         int ret = 0;
1542
1543         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1544                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please check the mode in fdir_conf.");
1545                 return -ENOTSUP;
1546         }
1547
1548         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1549                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1550                 return -EINVAL;
1551         }
1552         if (filter->input.flow_ext.is_vf &&
1553             filter->input.flow_ext.dst_id >= pf->vf_num) {
1554                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1555                 return -EINVAL;
1556         }
1557         if (filter->input.flow_ext.pkt_template) {
1558                 if (filter->input.flow.raw_flow.length > I40E_FDIR_PKT_LEN ||
1559                     !filter->input.flow.raw_flow.packet) {
1560                         PMD_DRV_LOG(ERR, "Invalid raw packet template"
1561                                 " flow filter parameters!");
1562                         return -EINVAL;
1563                 }
1564                 pctype = filter->input.flow.raw_flow.pctype;
1565         } else {
1566                 pctype = filter->input.pctype;
1567         }
1568
1569         /* Check if there is the filter in SW list */
1570         memset(&check_filter, 0, sizeof(check_filter));
1571         i40e_fdir_filter_convert(filter, &check_filter);
1572         node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1573         if (add && node) {
1574                 PMD_DRV_LOG(ERR,
1575                             "Conflict with existing flow director rules!");
1576                 return -EINVAL;
1577         }
1578
1579         if (!add && !node) {
1580                 PMD_DRV_LOG(ERR,
1581                             "There's no corresponding flow firector filter!");
1582                 return -EINVAL;
1583         }
1584
1585         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1586
1587         ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1588         if (ret < 0) {
1589                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1590                 return ret;
1591         }
1592
1593         if (hw->mac.type == I40E_MAC_X722) {
1594                 /* get translated pctype value in fd pctype register */
1595                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1596                         hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1597         }
1598
1599         ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add);
1600         if (ret < 0) {
1601                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1602                             pctype);
1603                 return ret;
1604         }
1605
1606         if (add) {
1607                 fdir_filter = rte_zmalloc("fdir_filter",
1608                                           sizeof(*fdir_filter), 0);
1609                 if (fdir_filter == NULL) {
1610                         PMD_DRV_LOG(ERR, "Failed to alloc memory.");
1611                         return -ENOMEM;
1612                 }
1613
1614                 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1615                 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1616                 if (ret < 0)
1617                         rte_free(fdir_filter);
1618         } else {
1619                 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1620         }
1621
1622         return ret;
1623 }
1624
1625 /*
1626  * i40e_fdir_filter_programming - Program a flow director filter rule.
1627  * Is done by Flow Director Programming Descriptor followed by packet
1628  * structure that contains the filter fields need to match.
1629  * @pf: board private structure
1630  * @pctype: pctype
1631  * @filter: fdir filter entry
1632  * @add: 0 - delete, 1 - add
1633  */
1634 static int
1635 i40e_fdir_filter_programming(struct i40e_pf *pf,
1636                         enum i40e_filter_pctype pctype,
1637                         const struct rte_eth_fdir_filter *filter,
1638                         bool add)
1639 {
1640         struct i40e_tx_queue *txq = pf->fdir.txq;
1641         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1642         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1643         volatile struct i40e_tx_desc *txdp;
1644         volatile struct i40e_filter_program_desc *fdirdp;
1645         uint32_t td_cmd;
1646         uint16_t vsi_id, i;
1647         uint8_t dest;
1648
1649         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1650         fdirdp = (volatile struct i40e_filter_program_desc *)
1651                         (&(txq->tx_ring[txq->tx_tail]));
1652
1653         fdirdp->qindex_flex_ptype_vsi =
1654                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1655                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1656                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1657
1658         fdirdp->qindex_flex_ptype_vsi |=
1659                         rte_cpu_to_le_32((fdir_action->flex_off <<
1660                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1661                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1662
1663         fdirdp->qindex_flex_ptype_vsi |=
1664                         rte_cpu_to_le_32((pctype <<
1665                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1666                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1667
1668         if (filter->input.flow_ext.is_vf)
1669                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1670         else
1671                 /* Use LAN VSI Id by default */
1672                 vsi_id = pf->main_vsi->vsi_id;
1673         fdirdp->qindex_flex_ptype_vsi |=
1674                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1675                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1676                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1677
1678         fdirdp->dtype_cmd_cntindex =
1679                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1680
1681         if (add)
1682                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1683                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1684                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1685         else
1686                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1687                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1688                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1689
1690         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1691                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1692         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1693                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1694         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1695                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1696         else {
1697                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1698                             " unsupported fdir behavior.");
1699                 return -EINVAL;
1700         }
1701
1702         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1703                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1704                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1705
1706         fdirdp->dtype_cmd_cntindex |=
1707                 rte_cpu_to_le_32((fdir_action->report_status<<
1708                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1709                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1710
1711         fdirdp->dtype_cmd_cntindex |=
1712                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1713         fdirdp->dtype_cmd_cntindex |=
1714                         rte_cpu_to_le_32(
1715                         ((uint32_t)pf->fdir.match_counter_index <<
1716                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1717                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1718
1719         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1720
1721         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1722         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1723         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1724         td_cmd = I40E_TX_DESC_CMD_EOP |
1725                  I40E_TX_DESC_CMD_RS  |
1726                  I40E_TX_DESC_CMD_DUMMY;
1727
1728         txdp->cmd_type_offset_bsz =
1729                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1730
1731         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1732         if (txq->tx_tail >= txq->nb_tx_desc)
1733                 txq->tx_tail = 0;
1734         /* Update the tx tail register */
1735         rte_wmb();
1736         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1737         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1738                 if ((txdp->cmd_type_offset_bsz &
1739                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1740                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1741                         break;
1742                 rte_delay_us(1);
1743         }
1744         if (i >= I40E_FDIR_MAX_WAIT_US) {
1745                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1746                             " time out to get DD on tx queue.");
1747                 return -ETIMEDOUT;
1748         }
1749         /* totally delay 10 ms to check programming status*/
1750         for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1751                 if (i40e_check_fdir_programming_status(rxq) >= 0)
1752                         return 0;
1753                 rte_delay_us(1);
1754         }
1755         PMD_DRV_LOG(ERR,
1756                 "Failed to program FDIR filter: programming status reported.");
1757         return -ETIMEDOUT;
1758 }
1759
1760 /*
1761  * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1762  * Is done by Flow Director Programming Descriptor followed by packet
1763  * structure that contains the filter fields need to match.
1764  * @pf: board private structure
1765  * @pctype: pctype
1766  * @filter: fdir filter entry
1767  * @add: 0 - delete, 1 - add
1768  */
1769 static int
1770 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1771                                   enum i40e_filter_pctype pctype,
1772                                   const struct i40e_fdir_filter_conf *filter,
1773                                   bool add)
1774 {
1775         struct i40e_tx_queue *txq = pf->fdir.txq;
1776         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1777         const struct i40e_fdir_action *fdir_action = &filter->action;
1778         volatile struct i40e_tx_desc *txdp;
1779         volatile struct i40e_filter_program_desc *fdirdp;
1780         uint32_t td_cmd;
1781         uint16_t vsi_id, i;
1782         uint8_t dest;
1783
1784         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1785         fdirdp = (volatile struct i40e_filter_program_desc *)
1786                                 (&txq->tx_ring[txq->tx_tail]);
1787
1788         fdirdp->qindex_flex_ptype_vsi =
1789                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1790                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1791                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1792
1793         fdirdp->qindex_flex_ptype_vsi |=
1794                         rte_cpu_to_le_32((fdir_action->flex_off <<
1795                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1796                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1797
1798         fdirdp->qindex_flex_ptype_vsi |=
1799                         rte_cpu_to_le_32((pctype <<
1800                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1801                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1802
1803         if (filter->input.flow_ext.is_vf)
1804                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1805         else
1806                 /* Use LAN VSI Id by default */
1807                 vsi_id = pf->main_vsi->vsi_id;
1808         fdirdp->qindex_flex_ptype_vsi |=
1809                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1810                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1811                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1812
1813         fdirdp->dtype_cmd_cntindex =
1814                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1815
1816         if (add)
1817                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1818                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1819                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1820         else
1821                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1822                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1823                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1824
1825         if (fdir_action->behavior == I40E_FDIR_REJECT)
1826                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1827         else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1828                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1829         else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1830                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1831         else {
1832                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1833                 return -EINVAL;
1834         }
1835
1836         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1837                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1838                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1839
1840         fdirdp->dtype_cmd_cntindex |=
1841                 rte_cpu_to_le_32((fdir_action->report_status <<
1842                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1843                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1844
1845         fdirdp->dtype_cmd_cntindex |=
1846                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1847         fdirdp->dtype_cmd_cntindex |=
1848                         rte_cpu_to_le_32(
1849                         ((uint32_t)pf->fdir.match_counter_index <<
1850                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1851                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1852
1853         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1854
1855         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1856         txdp = &txq->tx_ring[txq->tx_tail + 1];
1857         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1858         td_cmd = I40E_TX_DESC_CMD_EOP |
1859                  I40E_TX_DESC_CMD_RS  |
1860                  I40E_TX_DESC_CMD_DUMMY;
1861
1862         txdp->cmd_type_offset_bsz =
1863                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1864
1865         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1866         if (txq->tx_tail >= txq->nb_tx_desc)
1867                 txq->tx_tail = 0;
1868         /* Update the tx tail register */
1869         rte_wmb();
1870         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1871         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1872                 if ((txdp->cmd_type_offset_bsz &
1873                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1874                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1875                         break;
1876                 rte_delay_us(1);
1877         }
1878         if (i >= I40E_FDIR_MAX_WAIT_US) {
1879                 PMD_DRV_LOG(ERR,
1880                     "Failed to program FDIR filter: time out to get DD on tx queue.");
1881                 return -ETIMEDOUT;
1882         }
1883         /* totally delay 10 ms to check programming status*/
1884         rte_delay_us(I40E_FDIR_MAX_WAIT_US);
1885         if (i40e_check_fdir_programming_status(rxq) < 0) {
1886                 PMD_DRV_LOG(ERR,
1887                     "Failed to program FDIR filter: programming status reported.");
1888                 return -ETIMEDOUT;
1889         }
1890
1891         return 0;
1892 }
1893
1894 /*
1895  * i40e_fdir_flush - clear all filters of Flow Director table
1896  * @pf: board private structure
1897  */
1898 int
1899 i40e_fdir_flush(struct rte_eth_dev *dev)
1900 {
1901         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1902         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1903         uint32_t reg;
1904         uint16_t guarant_cnt, best_cnt;
1905         uint16_t i;
1906
1907         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1908         I40E_WRITE_FLUSH(hw);
1909
1910         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1911                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1912                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1913                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1914                         break;
1915         }
1916         if (i >= I40E_FDIR_FLUSH_RETRY) {
1917                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1918                 return -ETIMEDOUT;
1919         }
1920         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1921                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1922                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1923         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1924                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1925                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1926         if (guarant_cnt != 0 || best_cnt != 0) {
1927                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1928                 return -ENOSYS;
1929         } else
1930                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1931         return 0;
1932 }
1933
1934 static inline void
1935 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1936                         struct rte_eth_flex_payload_cfg *flex_set,
1937                         uint16_t *num)
1938 {
1939         struct i40e_fdir_flex_pit *flex_pit;
1940         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1941         uint16_t src, dst, size, j, k;
1942         uint8_t i, layer_idx;
1943
1944         for (layer_idx = I40E_FLXPLD_L2_IDX;
1945              layer_idx <= I40E_FLXPLD_L4_IDX;
1946              layer_idx++) {
1947                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1948                         ptr->type = RTE_ETH_L2_PAYLOAD;
1949                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1950                         ptr->type = RTE_ETH_L3_PAYLOAD;
1951                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1952                         ptr->type = RTE_ETH_L4_PAYLOAD;
1953
1954                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1955                         flex_pit = &pf->fdir.flex_set[layer_idx *
1956                                 I40E_MAX_FLXPLD_FIED + i];
1957                         if (flex_pit->size == 0)
1958                                 continue;
1959                         src = flex_pit->src_offset * sizeof(uint16_t);
1960                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1961                         size = flex_pit->size * sizeof(uint16_t);
1962                         for (j = src, k = dst; j < src + size; j++, k++)
1963                                 ptr->src_offset[k] = j;
1964                 }
1965                 (*num)++;
1966                 ptr++;
1967         }
1968 }
1969
1970 static inline void
1971 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1972                         struct rte_eth_fdir_flex_mask *flex_mask,
1973                         uint16_t *num)
1974 {
1975         struct i40e_fdir_flex_mask *mask;
1976         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1977         uint16_t flow_type;
1978         uint8_t i, j;
1979         uint16_t off_bytes, mask_tmp;
1980
1981         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1982              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1983              i++) {
1984                 mask =  &pf->fdir.flex_mask[i];
1985                 flow_type = i40e_pctype_to_flowtype(pf->adapter,
1986                                                     (enum i40e_filter_pctype)i);
1987                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
1988                         continue;
1989
1990                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1991                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1992                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1993                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1994                         } else {
1995                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1996                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1997                         }
1998                 }
1999                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
2000                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
2001                         mask_tmp = ~mask->bitmask[j].mask;
2002                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
2003                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
2004                 }
2005                 ptr->flow_type = flow_type;
2006                 ptr++;
2007                 (*num)++;
2008         }
2009 }
2010
2011 /*
2012  * i40e_fdir_info_get - get information of Flow Director
2013  * @pf: ethernet device to get info from
2014  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
2015  *    the flow director information.
2016  */
2017 static void
2018 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
2019 {
2020         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2021         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2022         uint16_t num_flex_set = 0;
2023         uint16_t num_flex_mask = 0;
2024         uint16_t i;
2025
2026         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
2027                 fdir->mode = RTE_FDIR_MODE_PERFECT;
2028         else
2029                 fdir->mode = RTE_FDIR_MODE_NONE;
2030
2031         fdir->guarant_spc =
2032                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
2033         fdir->best_spc =
2034                 (uint32_t)hw->func_caps.fd_filters_best_effort;
2035         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
2036         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
2037         for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
2038                 fdir->flow_types_mask[i] = 0ULL;
2039         fdir->flex_payload_unit = sizeof(uint16_t);
2040         fdir->flex_bitmask_unit = sizeof(uint16_t);
2041         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
2042         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
2043         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
2044
2045         i40e_fdir_info_get_flex_set(pf,
2046                                 fdir->flex_conf.flex_set,
2047                                 &num_flex_set);
2048         i40e_fdir_info_get_flex_mask(pf,
2049                                 fdir->flex_conf.flex_mask,
2050                                 &num_flex_mask);
2051
2052         fdir->flex_conf.nb_payloads = num_flex_set;
2053         fdir->flex_conf.nb_flexmasks = num_flex_mask;
2054 }
2055
2056 /*
2057  * i40e_fdir_stat_get - get statistics of Flow Director
2058  * @pf: ethernet device to get info from
2059  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
2060  *    the flow director statistics.
2061  */
2062 static void
2063 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2067         uint32_t fdstat;
2068
2069         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2070         stat->guarant_cnt =
2071                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2072                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2073         stat->best_cnt =
2074                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2075                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2076 }
2077
2078 static int
2079 i40e_fdir_filter_set(struct rte_eth_dev *dev,
2080                      struct rte_eth_fdir_filter_info *info)
2081 {
2082         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2083         int ret = 0;
2084
2085         if (!info) {
2086                 PMD_DRV_LOG(ERR, "Invalid pointer");
2087                 return -EFAULT;
2088         }
2089
2090         switch (info->info_type) {
2091         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
2092                 ret = i40e_fdir_filter_inset_select(pf,
2093                                 &(info->info.input_set_conf));
2094                 break;
2095         default:
2096                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
2097                             info->info_type);
2098                 return -EINVAL;
2099         }
2100
2101         return ret;
2102 }
2103
2104 /*
2105  * i40e_fdir_ctrl_func - deal with all operations on flow director.
2106  * @pf: board private structure
2107  * @filter_op:operation will be taken.
2108  * @arg: a pointer to specific structure corresponding to the filter_op
2109  */
2110 int
2111 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
2112                        enum rte_filter_op filter_op,
2113                        void *arg)
2114 {
2115         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2116         int ret = 0;
2117
2118         if ((pf->flags & I40E_FLAG_FDIR) == 0)
2119                 return -ENOTSUP;
2120
2121         if (filter_op == RTE_ETH_FILTER_NOP)
2122                 return 0;
2123
2124         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2125                 return -EINVAL;
2126
2127         switch (filter_op) {
2128         case RTE_ETH_FILTER_ADD:
2129                 ret = i40e_add_del_fdir_filter(dev,
2130                         (struct rte_eth_fdir_filter *)arg,
2131                         TRUE);
2132                 break;
2133         case RTE_ETH_FILTER_DELETE:
2134                 ret = i40e_add_del_fdir_filter(dev,
2135                         (struct rte_eth_fdir_filter *)arg,
2136                         FALSE);
2137                 break;
2138         case RTE_ETH_FILTER_FLUSH:
2139                 ret = i40e_fdir_flush(dev);
2140                 break;
2141         case RTE_ETH_FILTER_INFO:
2142                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2143                 break;
2144         case RTE_ETH_FILTER_SET:
2145                 ret = i40e_fdir_filter_set(dev,
2146                         (struct rte_eth_fdir_filter_info *)arg);
2147                 break;
2148         case RTE_ETH_FILTER_STATS:
2149                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2150                 break;
2151         default:
2152                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2153                 ret = -EINVAL;
2154                 break;
2155         }
2156         return ret;
2157 }
2158
2159 /* Restore flow director filter */
2160 void
2161 i40e_fdir_filter_restore(struct i40e_pf *pf)
2162 {
2163         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2164         struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2165         struct i40e_fdir_filter *f;
2166         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2167         uint32_t fdstat;
2168         uint32_t guarant_cnt;  /**< Number of filters in guaranteed spaces. */
2169         uint32_t best_cnt;     /**< Number of filters in best effort spaces. */
2170
2171         TAILQ_FOREACH(f, fdir_list, rules)
2172                 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2173
2174         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2175         guarant_cnt =
2176                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2177                            I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2178         best_cnt =
2179                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2180                            I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2181
2182         PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d,  Best count: %d",
2183                     guarant_cnt, best_cnt);
2184 }