drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "base/i40e_prototype.h"
  56 #include "i40e_ethdev.h"
  57 #include "i40e_rxtx.h"
  58
  59 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  60 #ifndef IPV6_ADDR_LEN
  61 #define IPV6_ADDR_LEN              16
  62 #endif
  63
  64 #define I40E_FDIR_PKT_LEN                   512
  65 #define I40E_FDIR_IP_DEFAULT_LEN            420
  66 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  70
  71 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  72 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  73 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  74
  75 /* Wait time for fdir filter programming */
  76 #define I40E_FDIR_MAX_WAIT_US 10000
  77
  78 /* Wait count and interval for fdir filter flush */
  79 #define I40E_FDIR_FLUSH_RETRY       50
  80 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  81
  82 #define I40E_COUNTER_PF           2
  83 /* Statistic counter index for one pf */
  84 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  85
  86 #define I40E_FDIR_FLOWS ( \
  87         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
  88         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  89         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  90         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  91         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  92         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
  93         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  94         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  95         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  96         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
  97         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
  98
  99 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 100                         enum i40e_filter_pctype pctype,
 101                         const struct rte_eth_fdir_filter *filter,
 102                         bool add);
 103 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
 104                          struct i40e_fdir_filter *filter);
 105 static struct i40e_fdir_filter *
 106 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
 107                         const struct i40e_fdir_input *input);
 108 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
 109                                    struct i40e_fdir_filter *filter);
 110 static int
 111 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
 112                                   enum i40e_filter_pctype pctype,
 113                                   const struct i40e_fdir_filter_conf *filter,
 114                                   bool add);
 115
 116 static int
 117 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 118 {
 119         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 120         struct i40e_hmc_obj_rxq rx_ctx;
 121         int err = I40E_SUCCESS;
 122
 123         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 124         /* Init the RX queue in hardware */
 125         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 126         rx_ctx.hbuff = 0;
 127         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 128         rx_ctx.qlen = rxq->nb_rx_desc;
 129 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 130         rx_ctx.dsize = 1;
 131 #endif
 132         rx_ctx.dtype = i40e_header_split_none;
 133         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 134         rx_ctx.rxmax = ETHER_MAX_LEN;
 135         rx_ctx.tphrdesc_ena = 1;
 136         rx_ctx.tphwdesc_ena = 1;
 137         rx_ctx.tphdata_ena = 1;
 138         rx_ctx.tphhead_ena = 1;
 139         rx_ctx.lrxqthresh = 2;
 140         rx_ctx.crcstrip = 0;
 141         rx_ctx.l2tsel = 1;
 142         rx_ctx.showiv = 0;
 143         rx_ctx.prefena = 1;
 144
 145         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 146         if (err != I40E_SUCCESS) {
 147                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 148                 return err;
 149         }
 150         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 151         if (err != I40E_SUCCESS) {
 152                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 153                 return err;
 154         }
 155         rxq->qrx_tail = hw->hw_addr +
 156                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 157
 158         rte_wmb();
 159         /* Init the RX tail regieter. */
 160         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 161         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 162
 163         return err;
 164 }
 165
 166 /*
 167  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 168  * @pf: board private structure
 169  */
 170 int
 171 i40e_fdir_setup(struct i40e_pf *pf)
 172 {
 173         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 174         struct i40e_vsi *vsi;
 175         int err = I40E_SUCCESS;
 176         char z_name[RTE_MEMZONE_NAMESIZE];
 177         const struct rte_memzone *mz = NULL;
 178         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 179
 180         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 181                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 182                 return I40E_NOT_SUPPORTED;
 183         }
 184
 185         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 186                         " num_filters_best_effort = %u.",
 187                         hw->func_caps.fd_filters_guaranteed,
 188                         hw->func_caps.fd_filters_best_effort);
 189
 190         vsi = pf->fdir.fdir_vsi;
 191         if (vsi) {
 192                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 193                 return I40E_SUCCESS;
 194         }
 195         /* make new FDIR VSI */
 196         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 197         if (!vsi) {
 198                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 199                 return I40E_ERR_NO_AVAILABLE_VSI;
 200         }
 201         pf->fdir.fdir_vsi = vsi;
 202
 203         /*Fdir tx queue setup*/
 204         err = i40e_fdir_setup_tx_resources(pf);
 205         if (err) {
 206                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 207                 goto fail_setup_tx;
 208         }
 209
 210         /*Fdir rx queue setup*/
 211         err = i40e_fdir_setup_rx_resources(pf);
 212         if (err) {
 213                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 214                 goto fail_setup_rx;
 215         }
 216
 217         err = i40e_tx_queue_init(pf->fdir.txq);
 218         if (err) {
 219                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 220                 goto fail_mem;
 221         }
 222
 223         /* need switch on before dev start*/
 224         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 225         if (err) {
 226                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 227                 goto fail_mem;
 228         }
 229
 230         /* Init the rx queue in hardware */
 231         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 232         if (err) {
 233                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 234                 goto fail_mem;
 235         }
 236
 237         /* switch on rx queue */
 238         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 239         if (err) {
 240                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 241                 goto fail_mem;
 242         }
 243
 244         /* reserve memory for the fdir programming packet */
 245         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 246                         eth_dev->device->driver->name,
 247                         I40E_FDIR_MZ_NAME,
 248                         eth_dev->data->port_id);
 249         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 250         if (!mz) {
 251                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 252                                  "flow director program packet.");
 253                 err = I40E_ERR_NO_MEMORY;
 254                 goto fail_mem;
 255         }
 256         pf->fdir.prg_pkt = mz->addr;
 257         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 258
 259         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 260         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 261                     vsi->base_queue);
 262         return I40E_SUCCESS;
 263
 264 fail_mem:
 265         i40e_dev_rx_queue_release(pf->fdir.rxq);
 266         pf->fdir.rxq = NULL;
 267 fail_setup_rx:
 268         i40e_dev_tx_queue_release(pf->fdir.txq);
 269         pf->fdir.txq = NULL;
 270 fail_setup_tx:
 271         i40e_vsi_release(vsi);
 272         pf->fdir.fdir_vsi = NULL;
 273         return err;
 274 }
 275
 276 /*
 277  * i40e_fdir_teardown - release the Flow Director resources
 278  * @pf: board private structure
 279  */
 280 void
 281 i40e_fdir_teardown(struct i40e_pf *pf)
 282 {
 283         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 284         struct i40e_vsi *vsi;
 285
 286         vsi = pf->fdir.fdir_vsi;
 287         if (!vsi)
 288                 return;
 289         int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 290         if (err)
 291                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
 292         err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 293         if (err)
 294                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
 295         i40e_dev_rx_queue_release(pf->fdir.rxq);
 296         pf->fdir.rxq = NULL;
 297         i40e_dev_tx_queue_release(pf->fdir.txq);
 298         pf->fdir.txq = NULL;
 299         i40e_vsi_release(vsi);
 300         pf->fdir.fdir_vsi = NULL;
 301 }
 302
 303 /* check whether the flow director table in empty */
 304 static inline int
 305 i40e_fdir_empty(struct i40e_hw *hw)
 306 {
 307         uint32_t guarant_cnt, best_cnt;
 308
 309         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 310                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 311                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 312         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 313                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 314                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 315         if (best_cnt + guarant_cnt > 0)
 316                 return -1;
 317
 318         return 0;
 319 }
 320
 321 /*
 322  * Initialize the configuration about bytes stream extracted as flexible payload
 323  * and mask setting
 324  */
 325 static inline void
 326 i40e_init_flx_pld(struct i40e_pf *pf)
 327 {
 328         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 329         uint8_t pctype;
 330         int i, index;
 331         uint16_t flow_type;
 332
 333         /*
 334          * Define the bytes stream extracted as flexible payload in
 335          * field vector. By default, select 8 words from the beginning
 336          * of payload as flexible payload.
 337          */
 338         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 339                 index = i * I40E_MAX_FLXPLD_FIED;
 340                 pf->fdir.flex_set[index].src_offset = 0;
 341                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 342                 pf->fdir.flex_set[index].dst_offset = 0;
 343                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 344                 I40E_WRITE_REG(hw,
 345                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 346                 I40E_WRITE_REG(hw,
 347                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 348         }
 349
 350         /* initialize the masks */
 351         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 352              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 353                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
 354
 355                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
 356                         continue;
 357                 pf->fdir.flex_mask[pctype].word_mask = 0;
 358                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 359                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 360                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 361                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 362                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 363                 }
 364         }
 365 }
 366
 367 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 368         if ((flex_pit2).src_offset < \
 369                 (flex_pit1).src_offset + (flex_pit1).size) { \
 370                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 371                         " less than than previous offset" \
 372                         " + previous FSIZE."); \
 373                 return -EINVAL; \
 374         } \
 375 } while (0)
 376
 377 /*
 378  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 379  * and the flex_pit will be sorted by it's src_offset value
 380  */
 381 static inline uint16_t
 382 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 383                         struct i40e_fdir_flex_pit *flex_pit)
 384 {
 385         uint16_t src_tmp, size, num = 0;
 386         uint16_t i, k, j = 0;
 387
 388         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 389                 size = 1;
 390                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 391                         if (src_offset[j + 1] == src_offset[j] + 1)
 392                                 size++;
 393                         else
 394                                 break;
 395                 }
 396                 src_tmp = src_offset[j] + 1 - size;
 397                 /* the flex_pit need to be sort by src_offset */
 398                 for (i = 0; i < num; i++) {
 399                         if (src_tmp < flex_pit[i].src_offset)
 400                                 break;
 401                 }
 402                 /* if insert required, move backward */
 403                 for (k = num; k > i; k--)
 404                         flex_pit[k] = flex_pit[k - 1];
 405                 /* insert */
 406                 flex_pit[i].dst_offset = j + 1 - size;
 407                 flex_pit[i].src_offset = src_tmp;
 408                 flex_pit[i].size = size;
 409                 j++;
 410                 num++;
 411         }
 412         return num;
 413 }
 414
 415 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 416 static inline int
 417 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 418 {
 419         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 420         uint16_t num, i;
 421
 422         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 423                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 424                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 425                         return -EINVAL;
 426                 }
 427         }
 428
 429         memset(flex_pit, 0, sizeof(flex_pit));
 430         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 431         if (num > I40E_MAX_FLXPLD_FIED) {
 432                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 433                 return -EINVAL;
 434         }
 435         for (i = 0; i < num; i++) {
 436                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 437                         flex_pit[i].src_offset & 0x01) {
 438                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 439                                 " in word");
 440                         return -EINVAL;
 441                 }
 442                 if (i != num - 1)
 443                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 444         }
 445         return 0;
 446 }
 447
 448 /*
 449  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 450  * arguments are valid
 451  */
 452 static int
 453 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
 454                           const struct rte_eth_fdir_flex_conf *conf)
 455 {
 456         const struct rte_eth_flex_payload_cfg *flex_cfg;
 457         const struct rte_eth_fdir_flex_mask *flex_mask;
 458         uint16_t mask_tmp;
 459         uint8_t nb_bitmask;
 460         uint16_t i, j;
 461         int ret = 0;
 462         enum i40e_filter_pctype pctype;
 463
 464         if (conf == NULL) {
 465                 PMD_DRV_LOG(INFO, "NULL pointer.");
 466                 return -EINVAL;
 467         }
 468         /* check flexible payload setting configuration */
 469         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 470                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 471                 return -EINVAL;
 472         }
 473         for (i = 0; i < conf->nb_payloads; i++) {
 474                 flex_cfg = &conf->flex_set[i];
 475                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 476                         PMD_DRV_LOG(ERR, "invalid payload type.");
 477                         return -EINVAL;
 478                 }
 479                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 480                 if (ret < 0) {
 481                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 482                         return -EINVAL;
 483                 }
 484         }
 485
 486         /* check flex mask setting configuration */
 487         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 488                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 489                 return -EINVAL;
 490         }
 491         for (i = 0; i < conf->nb_flexmasks; i++) {
 492                 flex_mask = &conf->flex_mask[i];
 493                 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
 494                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
 495                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 496                         return -EINVAL;
 497                 }
 498                 nb_bitmask = 0;
 499                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 500                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 501                                              flex_mask->mask[j + 1]);
 502                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 503                                 nb_bitmask++;
 504                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 505                                         PMD_DRV_LOG(ERR, " exceed maximal"
 506                                                 " number of bitmasks.");
 507                                         return -EINVAL;
 508                                 }
 509                         }
 510                 }
 511         }
 512         return 0;
 513 }
 514
 515 /*
 516  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 517  * @pf: board private structure
 518  * @cfg: the rule how bytes stream is extracted as flexible payload
 519  */
 520 static void
 521 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 522                          const struct rte_eth_flex_payload_cfg *cfg)
 523 {
 524         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 525         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 526         uint32_t flx_pit;
 527         uint16_t num, min_next_off;  /* in words */
 528         uint8_t field_idx = 0;
 529         uint8_t layer_idx = 0;
 530         uint16_t i;
 531
 532         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 533                 layer_idx = I40E_FLXPLD_L2_IDX;
 534         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 535                 layer_idx = I40E_FLXPLD_L3_IDX;
 536         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 537                 layer_idx = I40E_FLXPLD_L4_IDX;
 538
 539         memset(flex_pit, 0, sizeof(flex_pit));
 540         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 541
 542         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 543                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 544                 /* record the info in fdir structure */
 545                 pf->fdir.flex_set[field_idx].src_offset =
 546                         flex_pit[i].src_offset / sizeof(uint16_t);
 547                 pf->fdir.flex_set[field_idx].size =
 548                         flex_pit[i].size / sizeof(uint16_t);
 549                 pf->fdir.flex_set[field_idx].dst_offset =
 550                         flex_pit[i].dst_offset / sizeof(uint16_t);
 551                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 552                                 pf->fdir.flex_set[field_idx].size,
 553                                 pf->fdir.flex_set[field_idx].dst_offset);
 554
 555                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 556         }
 557         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 558                                 pf->fdir.flex_set[field_idx].size;
 559
 560         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 561                 /* set the non-used register obeying register's constrain */
 562                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 563                            NONUSE_FLX_PIT_DEST_OFF);
 564                 I40E_WRITE_REG(hw,
 565                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 566                         flx_pit);
 567                 min_next_off++;
 568         }
 569 }
 570
 571 /*
 572  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 573  * @pf: board private structure
 574  * @pctype: packet classify type
 575  * @flex_masks: mask for flexible payload
 576  */
 577 static void
 578 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 579                 enum i40e_filter_pctype pctype,
 580                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 581 {
 582         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 583         struct i40e_fdir_flex_mask *flex_mask;
 584         uint32_t flxinset, fd_mask;
 585         uint16_t mask_tmp;
 586         uint8_t i, nb_bitmask = 0;
 587
 588         flex_mask = &pf->fdir.flex_mask[pctype];
 589         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 590         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 591                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 592                 if (mask_tmp != 0x0) {
 593                         flex_mask->word_mask |=
 594                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 595                         if (mask_tmp != UINT16_MAX) {
 596                                 /* set bit mask */
 597                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 598                                 flex_mask->bitmask[nb_bitmask].offset =
 599                                         i / sizeof(uint16_t);
 600                                 nb_bitmask++;
 601                         }
 602                 }
 603         }
 604         /* write mask to hw */
 605         flxinset = (flex_mask->word_mask <<
 606                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 607                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 608         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 609
 610         for (i = 0; i < nb_bitmask; i++) {
 611                 fd_mask = (flex_mask->bitmask[i].mask <<
 612                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 613                         I40E_PRTQF_FD_MSK_MASK_MASK;
 614                 fd_mask |= ((flex_mask->bitmask[i].offset +
 615                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 616                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 617                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 618                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 619         }
 620 }
 621
 622 /*
 623  * Configure flow director related setting
 624  */
 625 int
 626 i40e_fdir_configure(struct rte_eth_dev *dev)
 627 {
 628         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 629         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 630         struct rte_eth_fdir_flex_conf *conf;
 631         enum i40e_filter_pctype pctype;
 632         uint32_t val;
 633         uint8_t i;
 634         int ret = 0;
 635
 636         /*
 637         * configuration need to be done before
 638         * flow director filters are added
 639         * If filters exist, flush them.
 640         */
 641         if (i40e_fdir_empty(hw) < 0) {
 642                 ret = i40e_fdir_flush(dev);
 643                 if (ret) {
 644                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 645                         return ret;
 646                 }
 647         }
 648
 649         /* enable FDIR filter */
 650         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 651         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 652         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 653
 654         i40e_init_flx_pld(pf); /* set flex config to default value */
 655
 656         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 657         ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
 658         if (ret < 0) {
 659                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 660                 return -EINVAL;
 661         }
 662         /* configure flex payload */
 663         for (i = 0; i < conf->nb_payloads; i++)
 664                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 665         /* configure flex mask*/
 666         for (i = 0; i < conf->nb_flexmasks; i++) {
 667                 if (hw->mac.type == I40E_MAC_X722) {
 668                         /* get translated pctype value in fd pctype register */
 669                         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
 670                                 hw, I40E_GLQF_FD_PCTYPES(
 671                                 (int)i40e_flowtype_to_pctype(pf->adapter,
 672                                 conf->flex_mask[i].flow_type)));
 673                 } else
 674                         pctype = i40e_flowtype_to_pctype(pf->adapter,
 675                                                 conf->flex_mask[i].flow_type);
 676
 677                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 678         }
 679
 680         return ret;
 681 }
 682
 683 static inline int
 684 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 685                            unsigned char *raw_pkt,
 686                            bool vlan)
 687 {
 688         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 689         uint16_t *ether_type;
 690         uint8_t len = 2 * sizeof(struct ether_addr);
 691         struct ipv4_hdr *ip;
 692         struct ipv6_hdr *ip6;
 693         static const uint8_t next_proto[] = {
 694                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 695                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 696                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 697                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 698                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 699                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 700                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 701                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 702                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 703                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 704         };
 705
 706         raw_pkt += 2 * sizeof(struct ether_addr);
 707         if (vlan && fdir_input->flow_ext.vlan_tci) {
 708                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 709                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 710                            &fdir_input->flow_ext.vlan_tci,
 711                            sizeof(uint16_t));
 712                 raw_pkt += sizeof(vlan_frame);
 713                 len += sizeof(vlan_frame);
 714         }
 715         ether_type = (uint16_t *)raw_pkt;
 716         raw_pkt += sizeof(uint16_t);
 717         len += sizeof(uint16_t);
 718
 719         switch (fdir_input->flow_type) {
 720         case RTE_ETH_FLOW_L2_PAYLOAD:
 721                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 722                 break;
 723         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 724         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 725         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 726         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 727         case RTE_ETH_FLOW_FRAG_IPV4:
 728                 ip = (struct ipv4_hdr *)raw_pkt;
 729
 730                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 731                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 732                 /* set len to by default */
 733                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 734                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 735                                         fdir_input->flow.ip4_flow.proto :
 736                                         next_proto[fdir_input->flow_type];
 737                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 738                                         fdir_input->flow.ip4_flow.ttl :
 739                                         I40E_FDIR_IP_DEFAULT_TTL;
 740                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 741                 /*
 742                  * The source and destination fields in the transmitted packet
 743                  * need to be presented in a reversed order with respect
 744                  * to the expected received packets.
 745                  */
 746                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 747                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 748                 len += sizeof(struct ipv4_hdr);
 749                 break;
 750         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 751         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 752         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 753         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 754         case RTE_ETH_FLOW_FRAG_IPV6:
 755                 ip6 = (struct ipv6_hdr *)raw_pkt;
 756
 757                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 758                 ip6->vtc_flow =
 759                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 760                                          (fdir_input->flow.ipv6_flow.tc <<
 761                                           I40E_FDIR_IPv6_TC_OFFSET));
 762                 ip6->payload_len =
 763                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 764                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 765                                         fdir_input->flow.ipv6_flow.proto :
 766                                         next_proto[fdir_input->flow_type];
 767                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 768                                         fdir_input->flow.ipv6_flow.hop_limits :
 769                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 770                 /*
 771                  * The source and destination fields in the transmitted packet
 772                  * need to be presented in a reversed order with respect
 773                  * to the expected received packets.
 774                  */
 775                 rte_memcpy(&(ip6->src_addr),
 776                            &(fdir_input->flow.ipv6_flow.dst_ip),
 777                            IPV6_ADDR_LEN);
 778                 rte_memcpy(&(ip6->dst_addr),
 779                            &(fdir_input->flow.ipv6_flow.src_ip),
 780                            IPV6_ADDR_LEN);
 781                 len += sizeof(struct ipv6_hdr);
 782                 break;
 783         default:
 784                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 785                             fdir_input->flow_type);
 786                 return -1;
 787         }
 788         return len;
 789 }
 790
 791
 792 /*
 793  * i40e_fdir_construct_pkt - construct packet based on fields in input
 794  * @pf: board private structure
 795  * @fdir_input: input set of the flow director entry
 796  * @raw_pkt: a packet to be constructed
 797  */
 798 static int
 799 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 800                              const struct rte_eth_fdir_input *fdir_input,
 801                              unsigned char *raw_pkt)
 802 {
 803         unsigned char *payload, *ptr;
 804         struct udp_hdr *udp;
 805         struct tcp_hdr *tcp;
 806         struct sctp_hdr *sctp;
 807         uint8_t size, dst = 0;
 808         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 809         int len;
 810
 811         /* fill the ethernet and IP head */
 812         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 813                                          !!fdir_input->flow_ext.vlan_tci);
 814         if (len < 0)
 815                 return -EINVAL;
 816
 817         /* fill the L4 head */
 818         switch (fdir_input->flow_type) {
 819         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 820                 udp = (struct udp_hdr *)(raw_pkt + len);
 821                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 822                 /*
 823                  * The source and destination fields in the transmitted packet
 824                  * need to be presented in a reversed order with respect
 825                  * to the expected received packets.
 826                  */
 827                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 828                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 829                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 830                 break;
 831
 832         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 833                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 834                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 835                 /*
 836                  * The source and destination fields in the transmitted packet
 837                  * need to be presented in a reversed order with respect
 838                  * to the expected received packets.
 839                  */
 840                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 841                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 842                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 843                 break;
 844
 845         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 846                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 847                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 848                 /*
 849                  * The source and destination fields in the transmitted packet
 850                  * need to be presented in a reversed order with respect
 851                  * to the expected received packets.
 852                  */
 853                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 854                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 855                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 856                 break;
 857
 858         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 859         case RTE_ETH_FLOW_FRAG_IPV4:
 860                 payload = raw_pkt + len;
 861                 set_idx = I40E_FLXPLD_L3_IDX;
 862                 break;
 863
 864         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 865                 udp = (struct udp_hdr *)(raw_pkt + len);
 866                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 867                 /*
 868                  * The source and destination fields in the transmitted packet
 869                  * need to be presented in a reversed order with respect
 870                  * to the expected received packets.
 871                  */
 872                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 873                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 874                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 875                 break;
 876
 877         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 878                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 879                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 880                 /*
 881                  * The source and destination fields in the transmitted packet
 882                  * need to be presented in a reversed order with respect
 883                  * to the expected received packets.
 884                  */
 885                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 886                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 887                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 888                 break;
 889
 890         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 891                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 892                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 893                 /*
 894                  * The source and destination fields in the transmitted packet
 895                  * need to be presented in a reversed order with respect
 896                  * to the expected received packets.
 897                  */
 898                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 899                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 900                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 901                 break;
 902
 903         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 904         case RTE_ETH_FLOW_FRAG_IPV6:
 905                 payload = raw_pkt + len;
 906                 set_idx = I40E_FLXPLD_L3_IDX;
 907                 break;
 908         case RTE_ETH_FLOW_L2_PAYLOAD:
 909                 payload = raw_pkt + len;
 910                 /*
 911                  * ARP packet is a special case on which the payload
 912                  * starts after the whole ARP header
 913                  */
 914                 if (fdir_input->flow.l2_flow.ether_type ==
 915                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 916                         payload += sizeof(struct arp_hdr);
 917                 set_idx = I40E_FLXPLD_L2_IDX;
 918                 break;
 919         default:
 920                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 921                 return -EINVAL;
 922         }
 923
 924         /* fill the flexbytes to payload */
 925         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 926                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 927                 size = pf->fdir.flex_set[pit_idx].size;
 928                 if (size == 0)
 929                         continue;
 930                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 931                 ptr = payload +
 932                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 933                 rte_memcpy(ptr,
 934                                  &fdir_input->flow_ext.flexbytes[dst],
 935                                  size * sizeof(uint16_t));
 936         }
 937
 938         return 0;
 939 }
 940
 941 static inline int
 942 i40e_flow_fdir_fill_eth_ip_head(const struct i40e_fdir_input *fdir_input,
 943                                 unsigned char *raw_pkt,
 944                                 bool vlan)
 945 {
 946         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 947         uint16_t *ether_type;
 948         uint8_t len = 2 * sizeof(struct ether_addr);
 949         struct ipv4_hdr *ip;
 950         struct ipv6_hdr *ip6;
 951         static const uint8_t next_proto[] = {
 952                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
 953                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
 954                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
 955                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
 956                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
 957                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
 958                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
 959                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
 960                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
 961                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
 962         };
 963
 964         raw_pkt += 2 * sizeof(struct ether_addr);
 965         if (vlan && fdir_input->flow_ext.vlan_tci) {
 966                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 967                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 968                            &fdir_input->flow_ext.vlan_tci,
 969                            sizeof(uint16_t));
 970                 raw_pkt += sizeof(vlan_frame);
 971                 len += sizeof(vlan_frame);
 972         }
 973         ether_type = (uint16_t *)raw_pkt;
 974         raw_pkt += sizeof(uint16_t);
 975         len += sizeof(uint16_t);
 976
 977         switch (fdir_input->pctype) {
 978         case I40E_FILTER_PCTYPE_L2_PAYLOAD:
 979                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 980                 break;
 981         case I40E_FILTER_PCTYPE_NONF_IPV4_TCP:
 982         case I40E_FILTER_PCTYPE_NONF_IPV4_UDP:
 983         case I40E_FILTER_PCTYPE_NONF_IPV4_SCTP:
 984         case I40E_FILTER_PCTYPE_NONF_IPV4_OTHER:
 985         case I40E_FILTER_PCTYPE_FRAG_IPV4:
 986                 ip = (struct ipv4_hdr *)raw_pkt;
 987
 988                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 989                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 990                 /* set len to by default */
 991                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 992                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 993                                         fdir_input->flow.ip4_flow.proto :
 994                                         next_proto[fdir_input->pctype];
 995                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 996                                         fdir_input->flow.ip4_flow.ttl :
 997                                         I40E_FDIR_IP_DEFAULT_TTL;
 998                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 999                 /**
1000                  * The source and destination fields in the transmitted packet
1001                  * need to be presented in a reversed order with respect
1002                  * to the expected received packets.
1003                  */
1004                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1005                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1006                 len += sizeof(struct ipv4_hdr);
1007                 break;
1008         case I40E_FILTER_PCTYPE_NONF_IPV6_TCP:
1009         case I40E_FILTER_PCTYPE_NONF_IPV6_UDP:
1010         case I40E_FILTER_PCTYPE_NONF_IPV6_SCTP:
1011         case I40E_FILTER_PCTYPE_NONF_IPV6_OTHER:
1012         case I40E_FILTER_PCTYPE_FRAG_IPV6:
1013                 ip6 = (struct ipv6_hdr *)raw_pkt;
1014
1015                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
1016                 ip6->vtc_flow =
1017                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1018                                          (fdir_input->flow.ipv6_flow.tc <<
1019                                           I40E_FDIR_IPv6_TC_OFFSET));
1020                 ip6->payload_len =
1021                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1022                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
1023                                         fdir_input->flow.ipv6_flow.proto :
1024                                         next_proto[fdir_input->pctype];
1025                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
1026                                         fdir_input->flow.ipv6_flow.hop_limits :
1027                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1028                 /**
1029                  * The source and destination fields in the transmitted packet
1030                  * need to be presented in a reversed order with respect
1031                  * to the expected received packets.
1032                  */
1033                 rte_memcpy(&ip6->src_addr,
1034                            &fdir_input->flow.ipv6_flow.dst_ip,
1035                            IPV6_ADDR_LEN);
1036                 rte_memcpy(&ip6->dst_addr,
1037                            &fdir_input->flow.ipv6_flow.src_ip,
1038                            IPV6_ADDR_LEN);
1039                 len += sizeof(struct ipv6_hdr);
1040                 break;
1041         default:
1042                 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1043                             fdir_input->pctype);
1044                 return -1;
1045         }
1046         return len;
1047 }
1048
1049 /**
1050  * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1051  * @pf: board private structure
1052  * @fdir_input: input set of the flow director entry
1053  * @raw_pkt: a packet to be constructed
1054  */
1055 static int
1056 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1057                              const struct i40e_fdir_input *fdir_input,
1058                              unsigned char *raw_pkt)
1059 {
1060         unsigned char *payload, *ptr;
1061         struct udp_hdr *udp;
1062         struct tcp_hdr *tcp;
1063         struct sctp_hdr *sctp;
1064         uint8_t size, dst = 0;
1065         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1066         int len;
1067
1068         /* fill the ethernet and IP head */
1069         len = i40e_flow_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
1070                                               !!fdir_input->flow_ext.vlan_tci);
1071         if (len < 0)
1072                 return -EINVAL;
1073
1074         /* fill the L4 head */
1075         switch (fdir_input->pctype) {
1076         case I40E_FILTER_PCTYPE_NONF_IPV4_UDP:
1077                 udp = (struct udp_hdr *)(raw_pkt + len);
1078                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1079                 /**
1080                  * The source and destination fields in the transmitted packet
1081                  * need to be presented in a reversed order with respect
1082                  * to the expected received packets.
1083                  */
1084                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1085                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1086                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1087                 break;
1088
1089         case I40E_FILTER_PCTYPE_NONF_IPV4_TCP:
1090                 tcp = (struct tcp_hdr *)(raw_pkt + len);
1091                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1092                 /**
1093                  * The source and destination fields in the transmitted packet
1094                  * need to be presented in a reversed order with respect
1095                  * to the expected received packets.
1096                  */
1097                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1098                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1099                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1100                 break;
1101
1102         case I40E_FILTER_PCTYPE_NONF_IPV4_SCTP:
1103                 sctp = (struct sctp_hdr *)(raw_pkt + len);
1104                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1105                 /**
1106                  * The source and destination fields in the transmitted packet
1107                  * need to be presented in a reversed order with respect
1108                  * to the expected received packets.
1109                  */
1110                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1111                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1112                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1113                 break;
1114
1115         case I40E_FILTER_PCTYPE_NONF_IPV4_OTHER:
1116         case I40E_FILTER_PCTYPE_FRAG_IPV4:
1117                 payload = raw_pkt + len;
1118                 set_idx = I40E_FLXPLD_L3_IDX;
1119                 break;
1120
1121         case I40E_FILTER_PCTYPE_NONF_IPV6_UDP:
1122                 udp = (struct udp_hdr *)(raw_pkt + len);
1123                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1124                 /**
1125                  * The source and destination fields in the transmitted packet
1126                  * need to be presented in a reversed order with respect
1127                  * to the expected received packets.
1128                  */
1129                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1130                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1131                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1132                 break;
1133
1134         case I40E_FILTER_PCTYPE_NONF_IPV6_TCP:
1135                 tcp = (struct tcp_hdr *)(raw_pkt + len);
1136                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1137                 /**
1138                  * The source and destination fields in the transmitted packet
1139                  * need to be presented in a reversed order with respect
1140                  * to the expected received packets.
1141                  */
1142                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1143                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1144                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1145                 break;
1146
1147         case I40E_FILTER_PCTYPE_NONF_IPV6_SCTP:
1148                 sctp = (struct sctp_hdr *)(raw_pkt + len);
1149                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1150                 /**
1151                  * The source and destination fields in the transmitted packet
1152                  * need to be presented in a reversed order with respect
1153                  * to the expected received packets.
1154                  */
1155                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1156                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1157                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1158                 break;
1159
1160         case I40E_FILTER_PCTYPE_NONF_IPV6_OTHER:
1161         case I40E_FILTER_PCTYPE_FRAG_IPV6:
1162                 payload = raw_pkt + len;
1163                 set_idx = I40E_FLXPLD_L3_IDX;
1164                 break;
1165         case I40E_FILTER_PCTYPE_L2_PAYLOAD:
1166                 payload = raw_pkt + len;
1167                 /**
1168                  * ARP packet is a special case on which the payload
1169                  * starts after the whole ARP header
1170                  */
1171                 if (fdir_input->flow.l2_flow.ether_type ==
1172                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
1173                         payload += sizeof(struct arp_hdr);
1174                 set_idx = I40E_FLXPLD_L2_IDX;
1175                 break;
1176         default:
1177                 PMD_DRV_LOG(ERR, "unknown pctype %u.", fdir_input->pctype);
1178                 return -EINVAL;
1179         }
1180
1181         /* fill the flexbytes to payload */
1182         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1183                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1184                 size = pf->fdir.flex_set[pit_idx].size;
1185                 if (size == 0)
1186                         continue;
1187                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1188                 ptr = payload +
1189                       pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1190                 (void)rte_memcpy(ptr,
1191                                  &fdir_input->flow_ext.flexbytes[dst],
1192                                  size * sizeof(uint16_t));
1193         }
1194
1195         return 0;
1196 }
1197
1198 /* Construct the tx flags */
1199 static inline uint64_t
1200 i40e_build_ctob(uint32_t td_cmd,
1201                 uint32_t td_offset,
1202                 unsigned int size,
1203                 uint32_t td_tag)
1204 {
1205         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1206                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
1207                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1208                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1209                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
1210 }
1211
1212 /*
1213  * check the programming status descriptor in rx queue.
1214  * done after Programming Flow Director is programmed on
1215  * tx queue
1216  */
1217 static inline int
1218 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1219 {
1220         volatile union i40e_rx_desc *rxdp;
1221         uint64_t qword1;
1222         uint32_t rx_status;
1223         uint32_t len, id;
1224         uint32_t error;
1225         int ret = 0;
1226
1227         rxdp = &rxq->rx_ring[rxq->rx_tail];
1228         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1229         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1230                         >> I40E_RXD_QW1_STATUS_SHIFT;
1231
1232         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1233                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1234                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1235                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1236
1237                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1238                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1239                         error = (qword1 &
1240                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1241                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1242                         if (error == (0x1 <<
1243                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1244                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1245                                             " (FD_ID %u): programming status"
1246                                             " reported.",
1247                                             rxdp->wb.qword0.hi_dword.fd_id);
1248                                 ret = -1;
1249                         } else if (error == (0x1 <<
1250                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1251                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1252                                             " (FD_ID %u): programming status"
1253                                             " reported.",
1254                                             rxdp->wb.qword0.hi_dword.fd_id);
1255                                 ret = -1;
1256                         } else
1257                                 PMD_DRV_LOG(ERR, "invalid programming status"
1258                                             " reported, error = %u.", error);
1259                 } else
1260                         PMD_DRV_LOG(ERR, "unknown programming status"
1261                                     " reported, len = %d, id = %u.", len, id);
1262                 rxdp->wb.qword1.status_error_len = 0;
1263                 rxq->rx_tail++;
1264                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1265                         rxq->rx_tail = 0;
1266         }
1267         return ret;
1268 }
1269
1270 static int
1271 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1272                          struct i40e_fdir_filter *filter)
1273 {
1274         rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1275         return 0;
1276 }
1277
1278 /* Check if there exists the flow director filter */
1279 static struct i40e_fdir_filter *
1280 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1281                         const struct i40e_fdir_input *input)
1282 {
1283         int ret;
1284
1285         ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1286         if (ret < 0)
1287                 return NULL;
1288
1289         return fdir_info->hash_map[ret];
1290 }
1291
1292 /* Add a flow director filter into the SW list */
1293 static int
1294 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1295 {
1296         struct i40e_fdir_info *fdir_info = &pf->fdir;
1297         int ret;
1298
1299         ret = rte_hash_add_key(fdir_info->hash_table,
1300                                &filter->fdir.input);
1301         if (ret < 0) {
1302                 PMD_DRV_LOG(ERR,
1303                             "Failed to insert fdir filter to hash table %d!",
1304                             ret);
1305                 return ret;
1306         }
1307         fdir_info->hash_map[ret] = filter;
1308
1309         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1310
1311         return 0;
1312 }
1313
1314 /* Delete a flow director filter from the SW list */
1315 int
1316 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1317 {
1318         struct i40e_fdir_info *fdir_info = &pf->fdir;
1319         struct i40e_fdir_filter *filter;
1320         int ret;
1321
1322         ret = rte_hash_del_key(fdir_info->hash_table, input);
1323         if (ret < 0) {
1324                 PMD_DRV_LOG(ERR,
1325                             "Failed to delete fdir filter to hash table %d!",
1326                             ret);
1327                 return ret;
1328         }
1329         filter = fdir_info->hash_map[ret];
1330         fdir_info->hash_map[ret] = NULL;
1331
1332         TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1333         rte_free(filter);
1334
1335         return 0;
1336 }
1337
1338 /*
1339  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1340  * @pf: board private structure
1341  * @filter: fdir filter entry
1342  * @add: 0 - delete, 1 - add
1343  */
1344 int
1345 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1346                          const struct rte_eth_fdir_filter *filter,
1347                          bool add)
1348 {
1349         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1350         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1351         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1352         enum i40e_filter_pctype pctype;
1353         int ret = 0;
1354
1355         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1356                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1357                         " check the mode in fdir_conf.");
1358                 return -ENOTSUP;
1359         }
1360
1361         pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1362         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1363                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1364                 return -EINVAL;
1365         }
1366         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1367                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1368                 return -EINVAL;
1369         }
1370         if (filter->input.flow_ext.is_vf &&
1371                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1372                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1373                 return -EINVAL;
1374         }
1375
1376         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1377
1378         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1379         if (ret < 0) {
1380                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1381                 return ret;
1382         }
1383
1384         if (hw->mac.type == I40E_MAC_X722) {
1385                 /* get translated pctype value in fd pctype register */
1386                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1387                         hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1388         }
1389
1390         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1391         if (ret < 0) {
1392                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1393                             pctype);
1394                 return ret;
1395         }
1396
1397         return ret;
1398 }
1399
1400 /**
1401  * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1402  * @pf: board private structure
1403  * @filter: fdir filter entry
1404  * @add: 0 - delete, 1 - add
1405  */
1406 int
1407 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1408                               const struct i40e_fdir_filter_conf *filter,
1409                               bool add)
1410 {
1411         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1412         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1413         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1414         enum i40e_filter_pctype pctype;
1415         struct i40e_fdir_info *fdir_info = &pf->fdir;
1416         struct i40e_fdir_filter *fdir_filter, *node;
1417         struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1418         int ret = 0;
1419
1420         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1421                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please check the mode in fdir_conf.");
1422                 return -ENOTSUP;
1423         }
1424
1425         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1426                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1427                 return -EINVAL;
1428         }
1429         if (filter->input.flow_ext.is_vf &&
1430             filter->input.flow_ext.dst_id >= pf->vf_num) {
1431                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1432                 return -EINVAL;
1433         }
1434
1435         /* Check if there is the filter in SW list */
1436         memset(&check_filter, 0, sizeof(check_filter));
1437         i40e_fdir_filter_convert(filter, &check_filter);
1438         node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1439         if (add && node) {
1440                 PMD_DRV_LOG(ERR,
1441                             "Conflict with existing flow director rules!");
1442                 return -EINVAL;
1443         }
1444
1445         if (!add && !node) {
1446                 PMD_DRV_LOG(ERR,
1447                             "There's no corresponding flow firector filter!");
1448                 return -EINVAL;
1449         }
1450
1451         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1452
1453         ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1454         if (ret < 0) {
1455                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1456                 return ret;
1457         }
1458
1459         if (hw->mac.type == I40E_MAC_X722) {
1460                 /* get translated pctype value in fd pctype register */
1461                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1462                         hw, I40E_GLQF_FD_PCTYPES(
1463                                 (int)filter->input.pctype));
1464         } else
1465                 pctype = filter->input.pctype;
1466
1467         ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add);
1468         if (ret < 0) {
1469                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1470                             pctype);
1471                 return ret;
1472         }
1473
1474         if (add) {
1475                 fdir_filter = rte_zmalloc("fdir_filter",
1476                                           sizeof(*fdir_filter), 0);
1477                 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1478                 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1479         } else {
1480                 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1481         }
1482
1483         return ret;
1484 }
1485
1486 /*
1487  * i40e_fdir_filter_programming - Program a flow director filter rule.
1488  * Is done by Flow Director Programming Descriptor followed by packet
1489  * structure that contains the filter fields need to match.
1490  * @pf: board private structure
1491  * @pctype: pctype
1492  * @filter: fdir filter entry
1493  * @add: 0 - delete, 1 - add
1494  */
1495 static int
1496 i40e_fdir_filter_programming(struct i40e_pf *pf,
1497                         enum i40e_filter_pctype pctype,
1498                         const struct rte_eth_fdir_filter *filter,
1499                         bool add)
1500 {
1501         struct i40e_tx_queue *txq = pf->fdir.txq;
1502         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1503         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1504         volatile struct i40e_tx_desc *txdp;
1505         volatile struct i40e_filter_program_desc *fdirdp;
1506         uint32_t td_cmd;
1507         uint16_t vsi_id, i;
1508         uint8_t dest;
1509
1510         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1511         fdirdp = (volatile struct i40e_filter_program_desc *)
1512                         (&(txq->tx_ring[txq->tx_tail]));
1513
1514         fdirdp->qindex_flex_ptype_vsi =
1515                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1516                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1517                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1518
1519         fdirdp->qindex_flex_ptype_vsi |=
1520                         rte_cpu_to_le_32((fdir_action->flex_off <<
1521                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1522                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1523
1524         fdirdp->qindex_flex_ptype_vsi |=
1525                         rte_cpu_to_le_32((pctype <<
1526                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1527                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1528
1529         if (filter->input.flow_ext.is_vf)
1530                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1531         else
1532                 /* Use LAN VSI Id by default */
1533                 vsi_id = pf->main_vsi->vsi_id;
1534         fdirdp->qindex_flex_ptype_vsi |=
1535                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1536                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1537                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1538
1539         fdirdp->dtype_cmd_cntindex =
1540                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1541
1542         if (add)
1543                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1544                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1545                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1546         else
1547                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1548                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1549                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1550
1551         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1552                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1553         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1554                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1555         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1556                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1557         else {
1558                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1559                             " unsupported fdir behavior.");
1560                 return -EINVAL;
1561         }
1562
1563         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1564                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1565                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1566
1567         fdirdp->dtype_cmd_cntindex |=
1568                 rte_cpu_to_le_32((fdir_action->report_status<<
1569                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1570                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1571
1572         fdirdp->dtype_cmd_cntindex |=
1573                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1574         fdirdp->dtype_cmd_cntindex |=
1575                         rte_cpu_to_le_32(
1576                         ((uint32_t)pf->fdir.match_counter_index <<
1577                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1578                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1579
1580         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1581
1582         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1583         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1584         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1585         td_cmd = I40E_TX_DESC_CMD_EOP |
1586                  I40E_TX_DESC_CMD_RS  |
1587                  I40E_TX_DESC_CMD_DUMMY;
1588
1589         txdp->cmd_type_offset_bsz =
1590                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1591
1592         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1593         if (txq->tx_tail >= txq->nb_tx_desc)
1594                 txq->tx_tail = 0;
1595         /* Update the tx tail register */
1596         rte_wmb();
1597         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1598         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1599                 if ((txdp->cmd_type_offset_bsz &
1600                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1601                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1602                         break;
1603                 rte_delay_us(1);
1604         }
1605         if (i >= I40E_FDIR_MAX_WAIT_US) {
1606                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1607                             " time out to get DD on tx queue.");
1608                 return -ETIMEDOUT;
1609         }
1610         /* totally delay 10 ms to check programming status*/
1611         for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1612                 if (i40e_check_fdir_programming_status(rxq) >= 0)
1613                         return 0;
1614                 rte_delay_us(1);
1615         }
1616         PMD_DRV_LOG(ERR,
1617                 "Failed to program FDIR filter: programming status reported.");
1618         return -ETIMEDOUT;
1619 }
1620
1621 /*
1622  * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1623  * Is done by Flow Director Programming Descriptor followed by packet
1624  * structure that contains the filter fields need to match.
1625  * @pf: board private structure
1626  * @pctype: pctype
1627  * @filter: fdir filter entry
1628  * @add: 0 - delete, 1 - add
1629  */
1630 static int
1631 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1632                                   enum i40e_filter_pctype pctype,
1633                                   const struct i40e_fdir_filter_conf *filter,
1634                                   bool add)
1635 {
1636         struct i40e_tx_queue *txq = pf->fdir.txq;
1637         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1638         const struct i40e_fdir_action *fdir_action = &filter->action;
1639         volatile struct i40e_tx_desc *txdp;
1640         volatile struct i40e_filter_program_desc *fdirdp;
1641         uint32_t td_cmd;
1642         uint16_t vsi_id, i;
1643         uint8_t dest;
1644
1645         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1646         fdirdp = (volatile struct i40e_filter_program_desc *)
1647                                 (&txq->tx_ring[txq->tx_tail]);
1648
1649         fdirdp->qindex_flex_ptype_vsi =
1650                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1651                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1652                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1653
1654         fdirdp->qindex_flex_ptype_vsi |=
1655                         rte_cpu_to_le_32((fdir_action->flex_off <<
1656                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1657                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1658
1659         fdirdp->qindex_flex_ptype_vsi |=
1660                         rte_cpu_to_le_32((pctype <<
1661                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1662                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1663
1664         if (filter->input.flow_ext.is_vf)
1665                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1666         else
1667                 /* Use LAN VSI Id by default */
1668                 vsi_id = pf->main_vsi->vsi_id;
1669         fdirdp->qindex_flex_ptype_vsi |=
1670                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1671                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1672                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1673
1674         fdirdp->dtype_cmd_cntindex =
1675                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1676
1677         if (add)
1678                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1679                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1680                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1681         else
1682                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1683                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1684                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1685
1686         if (fdir_action->behavior == I40E_FDIR_REJECT)
1687                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1688         else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1689                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1690         else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1691                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1692         else {
1693                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1694                 return -EINVAL;
1695         }
1696
1697         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1698                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1699                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1700
1701         fdirdp->dtype_cmd_cntindex |=
1702                 rte_cpu_to_le_32((fdir_action->report_status <<
1703                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1704                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1705
1706         fdirdp->dtype_cmd_cntindex |=
1707                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1708         fdirdp->dtype_cmd_cntindex |=
1709                         rte_cpu_to_le_32(
1710                         ((uint32_t)pf->fdir.match_counter_index <<
1711                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1712                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1713
1714         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1715
1716         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1717         txdp = &txq->tx_ring[txq->tx_tail + 1];
1718         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1719         td_cmd = I40E_TX_DESC_CMD_EOP |
1720                  I40E_TX_DESC_CMD_RS  |
1721                  I40E_TX_DESC_CMD_DUMMY;
1722
1723         txdp->cmd_type_offset_bsz =
1724                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1725
1726         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1727         if (txq->tx_tail >= txq->nb_tx_desc)
1728                 txq->tx_tail = 0;
1729         /* Update the tx tail register */
1730         rte_wmb();
1731         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1732         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1733                 if ((txdp->cmd_type_offset_bsz &
1734                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1735                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1736                         break;
1737                 rte_delay_us(1);
1738         }
1739         if (i >= I40E_FDIR_MAX_WAIT_US) {
1740                 PMD_DRV_LOG(ERR,
1741                     "Failed to program FDIR filter: time out to get DD on tx queue.");
1742                 return -ETIMEDOUT;
1743         }
1744         /* totally delay 10 ms to check programming status*/
1745         rte_delay_us(I40E_FDIR_MAX_WAIT_US);
1746         if (i40e_check_fdir_programming_status(rxq) < 0) {
1747                 PMD_DRV_LOG(ERR,
1748                     "Failed to program FDIR filter: programming status reported.");
1749                 return -ETIMEDOUT;
1750         }
1751
1752         return 0;
1753 }
1754
1755 /*
1756  * i40e_fdir_flush - clear all filters of Flow Director table
1757  * @pf: board private structure
1758  */
1759 int
1760 i40e_fdir_flush(struct rte_eth_dev *dev)
1761 {
1762         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1763         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1764         uint32_t reg;
1765         uint16_t guarant_cnt, best_cnt;
1766         uint16_t i;
1767
1768         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1769         I40E_WRITE_FLUSH(hw);
1770
1771         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1772                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1773                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1774                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1775                         break;
1776         }
1777         if (i >= I40E_FDIR_FLUSH_RETRY) {
1778                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1779                 return -ETIMEDOUT;
1780         }
1781         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1782                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1783                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1784         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1785                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1786                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1787         if (guarant_cnt != 0 || best_cnt != 0) {
1788                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1789                 return -ENOSYS;
1790         } else
1791                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1792         return 0;
1793 }
1794
1795 static inline void
1796 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1797                         struct rte_eth_flex_payload_cfg *flex_set,
1798                         uint16_t *num)
1799 {
1800         struct i40e_fdir_flex_pit *flex_pit;
1801         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1802         uint16_t src, dst, size, j, k;
1803         uint8_t i, layer_idx;
1804
1805         for (layer_idx = I40E_FLXPLD_L2_IDX;
1806              layer_idx <= I40E_FLXPLD_L4_IDX;
1807              layer_idx++) {
1808                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1809                         ptr->type = RTE_ETH_L2_PAYLOAD;
1810                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1811                         ptr->type = RTE_ETH_L3_PAYLOAD;
1812                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1813                         ptr->type = RTE_ETH_L4_PAYLOAD;
1814
1815                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1816                         flex_pit = &pf->fdir.flex_set[layer_idx *
1817                                 I40E_MAX_FLXPLD_FIED + i];
1818                         if (flex_pit->size == 0)
1819                                 continue;
1820                         src = flex_pit->src_offset * sizeof(uint16_t);
1821                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1822                         size = flex_pit->size * sizeof(uint16_t);
1823                         for (j = src, k = dst; j < src + size; j++, k++)
1824                                 ptr->src_offset[k] = j;
1825                 }
1826                 (*num)++;
1827                 ptr++;
1828         }
1829 }
1830
1831 static inline void
1832 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1833                         struct rte_eth_fdir_flex_mask *flex_mask,
1834                         uint16_t *num)
1835 {
1836         struct i40e_fdir_flex_mask *mask;
1837         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1838         uint16_t flow_type;
1839         uint8_t i, j;
1840         uint16_t off_bytes, mask_tmp;
1841
1842         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1843              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1844              i++) {
1845                 mask =  &pf->fdir.flex_mask[i];
1846                 flow_type = i40e_pctype_to_flowtype(pf->adapter,
1847                                                     (enum i40e_filter_pctype)i);
1848                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
1849                         continue;
1850
1851                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1852                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1853                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1854                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1855                         } else {
1856                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1857                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1858                         }
1859                 }
1860                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1861                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1862                         mask_tmp = ~mask->bitmask[j].mask;
1863                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1864                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1865                 }
1866                 ptr->flow_type = flow_type;
1867                 ptr++;
1868                 (*num)++;
1869         }
1870 }
1871
1872 /*
1873  * i40e_fdir_info_get - get information of Flow Director
1874  * @pf: ethernet device to get info from
1875  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1876  *    the flow director information.
1877  */
1878 static void
1879 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1880 {
1881         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1882         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1883         uint16_t num_flex_set = 0;
1884         uint16_t num_flex_mask = 0;
1885
1886         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1887                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1888         else
1889                 fdir->mode = RTE_FDIR_MODE_NONE;
1890
1891         fdir->guarant_spc =
1892                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1893         fdir->best_spc =
1894                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1895         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1896         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1897         fdir->flex_payload_unit = sizeof(uint16_t);
1898         fdir->flex_bitmask_unit = sizeof(uint16_t);
1899         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1900         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1901         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1902
1903         i40e_fdir_info_get_flex_set(pf,
1904                                 fdir->flex_conf.flex_set,
1905                                 &num_flex_set);
1906         i40e_fdir_info_get_flex_mask(pf,
1907                                 fdir->flex_conf.flex_mask,
1908                                 &num_flex_mask);
1909
1910         fdir->flex_conf.nb_payloads = num_flex_set;
1911         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1912 }
1913
1914 /*
1915  * i40e_fdir_stat_get - get statistics of Flow Director
1916  * @pf: ethernet device to get info from
1917  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1918  *    the flow director statistics.
1919  */
1920 static void
1921 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1922 {
1923         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1924         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1925         uint32_t fdstat;
1926
1927         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1928         stat->guarant_cnt =
1929                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1930                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1931         stat->best_cnt =
1932                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1933                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1934 }
1935
1936 static int
1937 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1938                      struct rte_eth_fdir_filter_info *info)
1939 {
1940         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1941         int ret = 0;
1942
1943         if (!info) {
1944                 PMD_DRV_LOG(ERR, "Invalid pointer");
1945                 return -EFAULT;
1946         }
1947
1948         switch (info->info_type) {
1949         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1950                 ret = i40e_fdir_filter_inset_select(pf,
1951                                 &(info->info.input_set_conf));
1952                 break;
1953         default:
1954                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1955                             info->info_type);
1956                 return -EINVAL;
1957         }
1958
1959         return ret;
1960 }
1961
1962 /*
1963  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1964  * @pf: board private structure
1965  * @filter_op:operation will be taken.
1966  * @arg: a pointer to specific structure corresponding to the filter_op
1967  */
1968 int
1969 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1970                        enum rte_filter_op filter_op,
1971                        void *arg)
1972 {
1973         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1974         int ret = 0;
1975
1976         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1977                 return -ENOTSUP;
1978
1979         if (filter_op == RTE_ETH_FILTER_NOP)
1980                 return 0;
1981
1982         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1983                 return -EINVAL;
1984
1985         switch (filter_op) {
1986         case RTE_ETH_FILTER_ADD:
1987                 ret = i40e_add_del_fdir_filter(dev,
1988                         (struct rte_eth_fdir_filter *)arg,
1989                         TRUE);
1990                 break;
1991         case RTE_ETH_FILTER_DELETE:
1992                 ret = i40e_add_del_fdir_filter(dev,
1993                         (struct rte_eth_fdir_filter *)arg,
1994                         FALSE);
1995                 break;
1996         case RTE_ETH_FILTER_FLUSH:
1997                 ret = i40e_fdir_flush(dev);
1998                 break;
1999         case RTE_ETH_FILTER_INFO:
2000                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2001                 break;
2002         case RTE_ETH_FILTER_SET:
2003                 ret = i40e_fdir_filter_set(dev,
2004                         (struct rte_eth_fdir_filter_info *)arg);
2005                 break;
2006         case RTE_ETH_FILTER_STATS:
2007                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2008                 break;
2009         default:
2010                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2011                 ret = -EINVAL;
2012                 break;
2013         }
2014         return ret;
2015 }
2016
2017 /* Restore flow director filter */
2018 void
2019 i40e_fdir_filter_restore(struct i40e_pf *pf)
2020 {
2021         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2022         struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2023         struct i40e_fdir_filter *f;
2024         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2025         uint32_t fdstat;
2026         uint32_t guarant_cnt;  /**< Number of filters in guaranteed spaces. */
2027         uint32_t best_cnt;     /**< Number of filters in best effort spaces. */
2028
2029         TAILQ_FOREACH(f, fdir_list, rules)
2030                 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2031
2032         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2033         guarant_cnt =
2034                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2035                            I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2036         best_cnt =
2037                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2038                            I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2039
2040         PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d,  Best count: %d",
2041                     guarant_cnt, best_cnt);
2042 }