drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "base/i40e_prototype.h"
  56 #include "i40e_ethdev.h"
  57 #include "i40e_rxtx.h"
  58
  59 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  60 #ifndef IPV6_ADDR_LEN
  61 #define IPV6_ADDR_LEN              16
  62 #endif
  63
  64 #define I40E_FDIR_PKT_LEN                   512
  65 #define I40E_FDIR_IP_DEFAULT_LEN            420
  66 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  67 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  68 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  69 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  70 #define I40E_FDIR_IPv6_TC_OFFSET            20
  71
  72 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  73 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  74 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  75
  76 /* Wait time for fdir filter programming */
  77 #define I40E_FDIR_MAX_WAIT_US 10000
  78
  79 /* Wait count and interval for fdir filter flush */
  80 #define I40E_FDIR_FLUSH_RETRY       50
  81 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  82
  83 #define I40E_COUNTER_PF           2
  84 /* Statistic counter index for one pf */
  85 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  86 #define I40E_MAX_FLX_SOURCE_OFF           480
  87 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  88
  89 #define NONUSE_FLX_PIT_DEST_OFF 63
  90 #define NONUSE_FLX_PIT_FSIZE    1
  91 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  92         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  93                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  94         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  95                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  96         ((((dst_offset) == NONUSE_FLX_PIT_DEST_OFF ? \
  97                         NONUSE_FLX_PIT_DEST_OFF : \
  98                         ((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR)) << \
  99                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
 100                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
 101
 102 #define I40E_FDIR_FLOWS ( \
 103         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
 104         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 108         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 109         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 110         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 111         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 112         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 113         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
 114
 115 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 116
 117 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 118                         enum i40e_filter_pctype pctype,
 119                         const struct rte_eth_fdir_filter *filter,
 120                         bool add);
 121 static int i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
 122                          struct i40e_fdir_filter *filter);
 123 static struct i40e_fdir_filter *
 124 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
 125                         const struct rte_eth_fdir_input *input);
 126 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
 127                                    struct i40e_fdir_filter *filter);
 128
 129 static int
 130 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 131 {
 132         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 133         struct i40e_hmc_obj_rxq rx_ctx;
 134         int err = I40E_SUCCESS;
 135
 136         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 137         /* Init the RX queue in hardware */
 138         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 139         rx_ctx.hbuff = 0;
 140         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 141         rx_ctx.qlen = rxq->nb_rx_desc;
 142 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 143         rx_ctx.dsize = 1;
 144 #endif
 145         rx_ctx.dtype = i40e_header_split_none;
 146         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 147         rx_ctx.rxmax = ETHER_MAX_LEN;
 148         rx_ctx.tphrdesc_ena = 1;
 149         rx_ctx.tphwdesc_ena = 1;
 150         rx_ctx.tphdata_ena = 1;
 151         rx_ctx.tphhead_ena = 1;
 152         rx_ctx.lrxqthresh = 2;
 153         rx_ctx.crcstrip = 0;
 154         rx_ctx.l2tsel = 1;
 155         rx_ctx.showiv = 0;
 156         rx_ctx.prefena = 1;
 157
 158         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 159         if (err != I40E_SUCCESS) {
 160                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 161                 return err;
 162         }
 163         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 164         if (err != I40E_SUCCESS) {
 165                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 166                 return err;
 167         }
 168         rxq->qrx_tail = hw->hw_addr +
 169                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 170
 171         rte_wmb();
 172         /* Init the RX tail regieter. */
 173         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 174         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 175
 176         return err;
 177 }
 178
 179 /*
 180  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 181  * @pf: board private structure
 182  */
 183 int
 184 i40e_fdir_setup(struct i40e_pf *pf)
 185 {
 186         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 187         struct i40e_vsi *vsi;
 188         int err = I40E_SUCCESS;
 189         char z_name[RTE_MEMZONE_NAMESIZE];
 190         const struct rte_memzone *mz = NULL;
 191         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 192
 193         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 194                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 195                 return I40E_NOT_SUPPORTED;
 196         }
 197
 198         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 199                         " num_filters_best_effort = %u.",
 200                         hw->func_caps.fd_filters_guaranteed,
 201                         hw->func_caps.fd_filters_best_effort);
 202
 203         vsi = pf->fdir.fdir_vsi;
 204         if (vsi) {
 205                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 206                 return I40E_SUCCESS;
 207         }
 208         /* make new FDIR VSI */
 209         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 210         if (!vsi) {
 211                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 212                 return I40E_ERR_NO_AVAILABLE_VSI;
 213         }
 214         pf->fdir.fdir_vsi = vsi;
 215
 216         /*Fdir tx queue setup*/
 217         err = i40e_fdir_setup_tx_resources(pf);
 218         if (err) {
 219                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 220                 goto fail_setup_tx;
 221         }
 222
 223         /*Fdir rx queue setup*/
 224         err = i40e_fdir_setup_rx_resources(pf);
 225         if (err) {
 226                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 227                 goto fail_setup_rx;
 228         }
 229
 230         err = i40e_tx_queue_init(pf->fdir.txq);
 231         if (err) {
 232                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 233                 goto fail_mem;
 234         }
 235
 236         /* need switch on before dev start*/
 237         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 238         if (err) {
 239                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 240                 goto fail_mem;
 241         }
 242
 243         /* Init the rx queue in hardware */
 244         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 245         if (err) {
 246                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 247                 goto fail_mem;
 248         }
 249
 250         /* switch on rx queue */
 251         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 252         if (err) {
 253                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 254                 goto fail_mem;
 255         }
 256
 257         /* reserve memory for the fdir programming packet */
 258         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 259                         eth_dev->data->drv_name,
 260                         I40E_FDIR_MZ_NAME,
 261                         eth_dev->data->port_id);
 262         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 263         if (!mz) {
 264                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 265                                  "flow director program packet.");
 266                 err = I40E_ERR_NO_MEMORY;
 267                 goto fail_mem;
 268         }
 269         pf->fdir.prg_pkt = mz->addr;
 270         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 271
 272         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 273         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 274                     vsi->base_queue);
 275         return I40E_SUCCESS;
 276
 277 fail_mem:
 278         i40e_dev_rx_queue_release(pf->fdir.rxq);
 279         pf->fdir.rxq = NULL;
 280 fail_setup_rx:
 281         i40e_dev_tx_queue_release(pf->fdir.txq);
 282         pf->fdir.txq = NULL;
 283 fail_setup_tx:
 284         i40e_vsi_release(vsi);
 285         pf->fdir.fdir_vsi = NULL;
 286         return err;
 287 }
 288
 289 /*
 290  * i40e_fdir_teardown - release the Flow Director resources
 291  * @pf: board private structure
 292  */
 293 void
 294 i40e_fdir_teardown(struct i40e_pf *pf)
 295 {
 296         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 297         struct i40e_vsi *vsi;
 298
 299         vsi = pf->fdir.fdir_vsi;
 300         if (!vsi)
 301                 return;
 302         int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 303         if (err)
 304                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
 305         err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 306         if (err)
 307                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
 308         i40e_dev_rx_queue_release(pf->fdir.rxq);
 309         pf->fdir.rxq = NULL;
 310         i40e_dev_tx_queue_release(pf->fdir.txq);
 311         pf->fdir.txq = NULL;
 312         i40e_vsi_release(vsi);
 313         pf->fdir.fdir_vsi = NULL;
 314 }
 315
 316 /* check whether the flow director table in empty */
 317 static inline int
 318 i40e_fdir_empty(struct i40e_hw *hw)
 319 {
 320         uint32_t guarant_cnt, best_cnt;
 321
 322         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 323                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 324                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 325         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 326                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 327                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 328         if (best_cnt + guarant_cnt > 0)
 329                 return -1;
 330
 331         return 0;
 332 }
 333
 334 /*
 335  * Initialize the configuration about bytes stream extracted as flexible payload
 336  * and mask setting
 337  */
 338 static inline void
 339 i40e_init_flx_pld(struct i40e_pf *pf)
 340 {
 341         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 342         uint8_t pctype;
 343         int i, index;
 344
 345         /*
 346          * Define the bytes stream extracted as flexible payload in
 347          * field vector. By default, select 8 words from the beginning
 348          * of payload as flexible payload.
 349          */
 350         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 351                 index = i * I40E_MAX_FLXPLD_FIED;
 352                 pf->fdir.flex_set[index].src_offset = 0;
 353                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 354                 pf->fdir.flex_set[index].dst_offset = 0;
 355                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 356                 I40E_WRITE_REG(hw,
 357                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 358                 I40E_WRITE_REG(hw,
 359                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 360         }
 361
 362         /* initialize the masks */
 363         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 364              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 365                 if (hw->mac.type == I40E_MAC_X722) {
 366                         if (!I40E_VALID_PCTYPE_X722(
 367                                  (enum i40e_filter_pctype)pctype))
 368                                 continue;
 369                 } else {
 370                         if (!I40E_VALID_PCTYPE(
 371                                  (enum i40e_filter_pctype)pctype))
 372                                 continue;
 373                 }
 374                 pf->fdir.flex_mask[pctype].word_mask = 0;
 375                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 376                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 377                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 378                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 379                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 380                 }
 381         }
 382 }
 383
 384 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 385
 386 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 387         if ((flex_pit2).src_offset < \
 388                 (flex_pit1).src_offset + (flex_pit1).size) { \
 389                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 390                         " less than than previous offset" \
 391                         " + previous FSIZE."); \
 392                 return -EINVAL; \
 393         } \
 394 } while (0)
 395
 396 /*
 397  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 398  * and the flex_pit will be sorted by it's src_offset value
 399  */
 400 static inline uint16_t
 401 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 402                         struct i40e_fdir_flex_pit *flex_pit)
 403 {
 404         uint16_t src_tmp, size, num = 0;
 405         uint16_t i, k, j = 0;
 406
 407         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 408                 size = 1;
 409                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 410                         if (src_offset[j + 1] == src_offset[j] + 1)
 411                                 size++;
 412                         else
 413                                 break;
 414                 }
 415                 src_tmp = src_offset[j] + 1 - size;
 416                 /* the flex_pit need to be sort by src_offset */
 417                 for (i = 0; i < num; i++) {
 418                         if (src_tmp < flex_pit[i].src_offset)
 419                                 break;
 420                 }
 421                 /* if insert required, move backward */
 422                 for (k = num; k > i; k--)
 423                         flex_pit[k] = flex_pit[k - 1];
 424                 /* insert */
 425                 flex_pit[i].dst_offset = j + 1 - size;
 426                 flex_pit[i].src_offset = src_tmp;
 427                 flex_pit[i].size = size;
 428                 j++;
 429                 num++;
 430         }
 431         return num;
 432 }
 433
 434 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 435 static inline int
 436 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 437 {
 438         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 439         uint16_t num, i;
 440
 441         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 442                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 443                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 444                         return -EINVAL;
 445                 }
 446         }
 447
 448         memset(flex_pit, 0, sizeof(flex_pit));
 449         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 450         if (num > I40E_MAX_FLXPLD_FIED) {
 451                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 452                 return -EINVAL;
 453         }
 454         for (i = 0; i < num; i++) {
 455                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 456                         flex_pit[i].src_offset & 0x01) {
 457                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 458                                 " in word");
 459                         return -EINVAL;
 460                 }
 461                 if (i != num - 1)
 462                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 463         }
 464         return 0;
 465 }
 466
 467 /*
 468  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 469  * arguments are valid
 470  */
 471 static int
 472 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 473 {
 474         const struct rte_eth_flex_payload_cfg *flex_cfg;
 475         const struct rte_eth_fdir_flex_mask *flex_mask;
 476         uint16_t mask_tmp;
 477         uint8_t nb_bitmask;
 478         uint16_t i, j;
 479         int ret = 0;
 480
 481         if (conf == NULL) {
 482                 PMD_DRV_LOG(INFO, "NULL pointer.");
 483                 return -EINVAL;
 484         }
 485         /* check flexible payload setting configuration */
 486         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 487                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 488                 return -EINVAL;
 489         }
 490         for (i = 0; i < conf->nb_payloads; i++) {
 491                 flex_cfg = &conf->flex_set[i];
 492                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 493                         PMD_DRV_LOG(ERR, "invalid payload type.");
 494                         return -EINVAL;
 495                 }
 496                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 497                 if (ret < 0) {
 498                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 499                         return -EINVAL;
 500                 }
 501         }
 502
 503         /* check flex mask setting configuration */
 504         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 505                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 506                 return -EINVAL;
 507         }
 508         for (i = 0; i < conf->nb_flexmasks; i++) {
 509                 flex_mask = &conf->flex_mask[i];
 510                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 511                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 512                         return -EINVAL;
 513                 }
 514                 nb_bitmask = 0;
 515                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 516                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 517                                              flex_mask->mask[j + 1]);
 518                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 519                                 nb_bitmask++;
 520                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 521                                         PMD_DRV_LOG(ERR, " exceed maximal"
 522                                                 " number of bitmasks.");
 523                                         return -EINVAL;
 524                                 }
 525                         }
 526                 }
 527         }
 528         return 0;
 529 }
 530
 531 /*
 532  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 533  * @pf: board private structure
 534  * @cfg: the rule how bytes stream is extracted as flexible payload
 535  */
 536 static void
 537 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 538                          const struct rte_eth_flex_payload_cfg *cfg)
 539 {
 540         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 541         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 542         uint32_t flx_pit;
 543         uint16_t num, min_next_off;  /* in words */
 544         uint8_t field_idx = 0;
 545         uint8_t layer_idx = 0;
 546         uint16_t i;
 547
 548         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 549                 layer_idx = I40E_FLXPLD_L2_IDX;
 550         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 551                 layer_idx = I40E_FLXPLD_L3_IDX;
 552         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 553                 layer_idx = I40E_FLXPLD_L4_IDX;
 554
 555         memset(flex_pit, 0, sizeof(flex_pit));
 556         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 557
 558         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 559                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 560                 /* record the info in fdir structure */
 561                 pf->fdir.flex_set[field_idx].src_offset =
 562                         flex_pit[i].src_offset / sizeof(uint16_t);
 563                 pf->fdir.flex_set[field_idx].size =
 564                         flex_pit[i].size / sizeof(uint16_t);
 565                 pf->fdir.flex_set[field_idx].dst_offset =
 566                         flex_pit[i].dst_offset / sizeof(uint16_t);
 567                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 568                                 pf->fdir.flex_set[field_idx].size,
 569                                 pf->fdir.flex_set[field_idx].dst_offset);
 570
 571                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 572         }
 573         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 574                                 pf->fdir.flex_set[field_idx].size;
 575
 576         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 577                 /* set the non-used register obeying register's constrain */
 578                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 579                            NONUSE_FLX_PIT_DEST_OFF);
 580                 I40E_WRITE_REG(hw,
 581                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 582                         flx_pit);
 583                 min_next_off++;
 584         }
 585 }
 586
 587 /*
 588  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 589  * @pf: board private structure
 590  * @pctype: packet classify type
 591  * @flex_masks: mask for flexible payload
 592  */
 593 static void
 594 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 595                 enum i40e_filter_pctype pctype,
 596                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 597 {
 598         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 599         struct i40e_fdir_flex_mask *flex_mask;
 600         uint32_t flxinset, fd_mask;
 601         uint16_t mask_tmp;
 602         uint8_t i, nb_bitmask = 0;
 603
 604         flex_mask = &pf->fdir.flex_mask[pctype];
 605         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 606         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 607                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 608                 if (mask_tmp != 0x0) {
 609                         flex_mask->word_mask |=
 610                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 611                         if (mask_tmp != UINT16_MAX) {
 612                                 /* set bit mask */
 613                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 614                                 flex_mask->bitmask[nb_bitmask].offset =
 615                                         i / sizeof(uint16_t);
 616                                 nb_bitmask++;
 617                         }
 618                 }
 619         }
 620         /* write mask to hw */
 621         flxinset = (flex_mask->word_mask <<
 622                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 623                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 624         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 625
 626         for (i = 0; i < nb_bitmask; i++) {
 627                 fd_mask = (flex_mask->bitmask[i].mask <<
 628                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 629                         I40E_PRTQF_FD_MSK_MASK_MASK;
 630                 fd_mask |= ((flex_mask->bitmask[i].offset +
 631                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 632                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 633                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 634                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 635         }
 636 }
 637
 638 /*
 639  * Configure flow director related setting
 640  */
 641 int
 642 i40e_fdir_configure(struct rte_eth_dev *dev)
 643 {
 644         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 646         struct rte_eth_fdir_flex_conf *conf;
 647         enum i40e_filter_pctype pctype;
 648         uint32_t val;
 649         uint8_t i;
 650         int ret = 0;
 651
 652         /*
 653         * configuration need to be done before
 654         * flow director filters are added
 655         * If filters exist, flush them.
 656         */
 657         if (i40e_fdir_empty(hw) < 0) {
 658                 ret = i40e_fdir_flush(dev);
 659                 if (ret) {
 660                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 661                         return ret;
 662                 }
 663         }
 664
 665         /* enable FDIR filter */
 666         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 667         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 668         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 669
 670         i40e_init_flx_pld(pf); /* set flex config to default value */
 671
 672         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 673         ret = i40e_check_fdir_flex_conf(conf);
 674         if (ret < 0) {
 675                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 676                 return -EINVAL;
 677         }
 678         /* configure flex payload */
 679         for (i = 0; i < conf->nb_payloads; i++)
 680                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 681         /* configure flex mask*/
 682         for (i = 0; i < conf->nb_flexmasks; i++) {
 683                 if (hw->mac.type == I40E_MAC_X722) {
 684                         /* get translated pctype value in fd pctype register */
 685                         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
 686                                 hw, I40E_GLQF_FD_PCTYPES(
 687                                 (int)i40e_flowtype_to_pctype(
 688                                 conf->flex_mask[i].flow_type)));
 689                 } else
 690                         pctype = i40e_flowtype_to_pctype(
 691                                 conf->flex_mask[i].flow_type);
 692
 693                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 694         }
 695
 696         return ret;
 697 }
 698
 699 static inline int
 700 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 701                            unsigned char *raw_pkt,
 702                            bool vlan)
 703 {
 704         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 705         uint16_t *ether_type;
 706         uint8_t len = 2 * sizeof(struct ether_addr);
 707         struct ipv4_hdr *ip;
 708         struct ipv6_hdr *ip6;
 709         static const uint8_t next_proto[] = {
 710                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 711                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 712                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 713                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 714                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 715                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 716                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 717                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 718                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 719                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 720         };
 721
 722         raw_pkt += 2 * sizeof(struct ether_addr);
 723         if (vlan && fdir_input->flow_ext.vlan_tci) {
 724                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 725                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 726                            &fdir_input->flow_ext.vlan_tci,
 727                            sizeof(uint16_t));
 728                 raw_pkt += sizeof(vlan_frame);
 729                 len += sizeof(vlan_frame);
 730         }
 731         ether_type = (uint16_t *)raw_pkt;
 732         raw_pkt += sizeof(uint16_t);
 733         len += sizeof(uint16_t);
 734
 735         switch (fdir_input->flow_type) {
 736         case RTE_ETH_FLOW_L2_PAYLOAD:
 737                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 738                 break;
 739         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 740         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 741         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 742         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 743         case RTE_ETH_FLOW_FRAG_IPV4:
 744                 ip = (struct ipv4_hdr *)raw_pkt;
 745
 746                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 747                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 748                 /* set len to by default */
 749                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 750                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 751                                         fdir_input->flow.ip4_flow.proto :
 752                                         next_proto[fdir_input->flow_type];
 753                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 754                                         fdir_input->flow.ip4_flow.ttl :
 755                                         I40E_FDIR_IP_DEFAULT_TTL;
 756                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 757                 /*
 758                  * The source and destination fields in the transmitted packet
 759                  * need to be presented in a reversed order with respect
 760                  * to the expected received packets.
 761                  */
 762                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 763                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 764                 len += sizeof(struct ipv4_hdr);
 765                 break;
 766         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 767         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 768         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 769         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 770         case RTE_ETH_FLOW_FRAG_IPV6:
 771                 ip6 = (struct ipv6_hdr *)raw_pkt;
 772
 773                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 774                 ip6->vtc_flow =
 775                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 776                                          (fdir_input->flow.ipv6_flow.tc <<
 777                                           I40E_FDIR_IPv6_TC_OFFSET));
 778                 ip6->payload_len =
 779                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 780                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 781                                         fdir_input->flow.ipv6_flow.proto :
 782                                         next_proto[fdir_input->flow_type];
 783                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 784                                         fdir_input->flow.ipv6_flow.hop_limits :
 785                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 786                 /*
 787                  * The source and destination fields in the transmitted packet
 788                  * need to be presented in a reversed order with respect
 789                  * to the expected received packets.
 790                  */
 791                 rte_memcpy(&(ip6->src_addr),
 792                            &(fdir_input->flow.ipv6_flow.dst_ip),
 793                            IPV6_ADDR_LEN);
 794                 rte_memcpy(&(ip6->dst_addr),
 795                            &(fdir_input->flow.ipv6_flow.src_ip),
 796                            IPV6_ADDR_LEN);
 797                 len += sizeof(struct ipv6_hdr);
 798                 break;
 799         default:
 800                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 801                             fdir_input->flow_type);
 802                 return -1;
 803         }
 804         return len;
 805 }
 806
 807
 808 /*
 809  * i40e_fdir_construct_pkt - construct packet based on fields in input
 810  * @pf: board private structure
 811  * @fdir_input: input set of the flow director entry
 812  * @raw_pkt: a packet to be constructed
 813  */
 814 static int
 815 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 816                              const struct rte_eth_fdir_input *fdir_input,
 817                              unsigned char *raw_pkt)
 818 {
 819         unsigned char *payload, *ptr;
 820         struct udp_hdr *udp;
 821         struct tcp_hdr *tcp;
 822         struct sctp_hdr *sctp;
 823         uint8_t size, dst = 0;
 824         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 825         int len;
 826
 827         /* fill the ethernet and IP head */
 828         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 829                                          !!fdir_input->flow_ext.vlan_tci);
 830         if (len < 0)
 831                 return -EINVAL;
 832
 833         /* fill the L4 head */
 834         switch (fdir_input->flow_type) {
 835         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 836                 udp = (struct udp_hdr *)(raw_pkt + len);
 837                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 838                 /*
 839                  * The source and destination fields in the transmitted packet
 840                  * need to be presented in a reversed order with respect
 841                  * to the expected received packets.
 842                  */
 843                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 844                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 845                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 846                 break;
 847
 848         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 849                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 850                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 851                 /*
 852                  * The source and destination fields in the transmitted packet
 853                  * need to be presented in a reversed order with respect
 854                  * to the expected received packets.
 855                  */
 856                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 857                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 858                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 859                 break;
 860
 861         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 862                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 863                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 864                 /*
 865                  * The source and destination fields in the transmitted packet
 866                  * need to be presented in a reversed order with respect
 867                  * to the expected received packets.
 868                  */
 869                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 870                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 871                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 872                 break;
 873
 874         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 875         case RTE_ETH_FLOW_FRAG_IPV4:
 876                 payload = raw_pkt + len;
 877                 set_idx = I40E_FLXPLD_L3_IDX;
 878                 break;
 879
 880         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 881                 udp = (struct udp_hdr *)(raw_pkt + len);
 882                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 883                 /*
 884                  * The source and destination fields in the transmitted packet
 885                  * need to be presented in a reversed order with respect
 886                  * to the expected received packets.
 887                  */
 888                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 889                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 890                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 891                 break;
 892
 893         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 894                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 895                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 896                 /*
 897                  * The source and destination fields in the transmitted packet
 898                  * need to be presented in a reversed order with respect
 899                  * to the expected received packets.
 900                  */
 901                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 902                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 903                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 904                 break;
 905
 906         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 907                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 908                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 909                 /*
 910                  * The source and destination fields in the transmitted packet
 911                  * need to be presented in a reversed order with respect
 912                  * to the expected received packets.
 913                  */
 914                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 915                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 916                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 917                 break;
 918
 919         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 920         case RTE_ETH_FLOW_FRAG_IPV6:
 921                 payload = raw_pkt + len;
 922                 set_idx = I40E_FLXPLD_L3_IDX;
 923                 break;
 924         case RTE_ETH_FLOW_L2_PAYLOAD:
 925                 payload = raw_pkt + len;
 926                 /*
 927                  * ARP packet is a special case on which the payload
 928                  * starts after the whole ARP header
 929                  */
 930                 if (fdir_input->flow.l2_flow.ether_type ==
 931                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 932                         payload += sizeof(struct arp_hdr);
 933                 set_idx = I40E_FLXPLD_L2_IDX;
 934                 break;
 935         default:
 936                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 937                 return -EINVAL;
 938         }
 939
 940         /* fill the flexbytes to payload */
 941         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 942                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 943                 size = pf->fdir.flex_set[pit_idx].size;
 944                 if (size == 0)
 945                         continue;
 946                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 947                 ptr = payload +
 948                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 949                 (void)rte_memcpy(ptr,
 950                                  &fdir_input->flow_ext.flexbytes[dst],
 951                                  size * sizeof(uint16_t));
 952         }
 953
 954         return 0;
 955 }
 956
 957 /* Construct the tx flags */
 958 static inline uint64_t
 959 i40e_build_ctob(uint32_t td_cmd,
 960                 uint32_t td_offset,
 961                 unsigned int size,
 962                 uint32_t td_tag)
 963 {
 964         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 965                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 966                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 967                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 968                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 969 }
 970
 971 /*
 972  * check the programming status descriptor in rx queue.
 973  * done after Programming Flow Director is programmed on
 974  * tx queue
 975  */
 976 static inline int
 977 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 978 {
 979         volatile union i40e_rx_desc *rxdp;
 980         uint64_t qword1;
 981         uint32_t rx_status;
 982         uint32_t len, id;
 983         uint32_t error;
 984         int ret = 0;
 985
 986         rxdp = &rxq->rx_ring[rxq->rx_tail];
 987         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 988         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 989                         >> I40E_RXD_QW1_STATUS_SHIFT;
 990
 991         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 992                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 993                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 994                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 995
 996                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 997                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 998                         error = (qword1 &
 999                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1000                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1001                         if (error == (0x1 <<
1002                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1003                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1004                                             " (FD_ID %u): programming status"
1005                                             " reported.",
1006                                             rxdp->wb.qword0.hi_dword.fd_id);
1007                                 ret = -1;
1008                         } else if (error == (0x1 <<
1009                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1010                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1011                                             " (FD_ID %u): programming status"
1012                                             " reported.",
1013                                             rxdp->wb.qword0.hi_dword.fd_id);
1014                                 ret = -1;
1015                         } else
1016                                 PMD_DRV_LOG(ERR, "invalid programming status"
1017                                             " reported, error = %u.", error);
1018                 } else
1019                         PMD_DRV_LOG(ERR, "unknown programming status"
1020                                     " reported, len = %d, id = %u.", len, id);
1021                 rxdp->wb.qword1.status_error_len = 0;
1022                 rxq->rx_tail++;
1023                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1024                         rxq->rx_tail = 0;
1025         }
1026         return ret;
1027 }
1028
1029 static int
1030 i40e_fdir_filter_convert(const struct rte_eth_fdir_filter *input,
1031                          struct i40e_fdir_filter *filter)
1032 {
1033         rte_memcpy(&filter->fdir, input, sizeof(struct rte_eth_fdir_filter));
1034         return 0;
1035 }
1036
1037 /* Check if there exists the flow director filter */
1038 static struct i40e_fdir_filter *
1039 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1040                         const struct rte_eth_fdir_input *input)
1041 {
1042         int ret;
1043
1044         ret = rte_hash_lookup(fdir_info->hash_table, (const void *)input);
1045         if (ret < 0)
1046                 return NULL;
1047
1048         return fdir_info->hash_map[ret];
1049 }
1050
1051 /* Add a flow director filter into the SW list */
1052 static int
1053 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1054 {
1055         struct i40e_fdir_info *fdir_info = &pf->fdir;
1056         int ret;
1057
1058         ret = rte_hash_add_key(fdir_info->hash_table,
1059                                &filter->fdir.input);
1060         if (ret < 0) {
1061                 PMD_DRV_LOG(ERR,
1062                             "Failed to insert fdir filter to hash table %d!",
1063                             ret);
1064                 return ret;
1065         }
1066         fdir_info->hash_map[ret] = filter;
1067
1068         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1069
1070         return 0;
1071 }
1072
1073 /* Delete a flow director filter from the SW list */
1074 int
1075 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct rte_eth_fdir_input *input)
1076 {
1077         struct i40e_fdir_info *fdir_info = &pf->fdir;
1078         struct i40e_fdir_filter *filter;
1079         int ret;
1080
1081         ret = rte_hash_del_key(fdir_info->hash_table, input);
1082         if (ret < 0) {
1083                 PMD_DRV_LOG(ERR,
1084                             "Failed to delete fdir filter to hash table %d!",
1085                             ret);
1086                 return ret;
1087         }
1088         filter = fdir_info->hash_map[ret];
1089         fdir_info->hash_map[ret] = NULL;
1090
1091         TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1092         rte_free(filter);
1093
1094         return 0;
1095 }
1096
1097 /*
1098  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1099  * @pf: board private structure
1100  * @filter: fdir filter entry
1101  * @add: 0 - delete, 1 - add
1102  */
1103 int
1104 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1105                             const struct rte_eth_fdir_filter *filter,
1106                             bool add)
1107 {
1108         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1110         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1111         enum i40e_filter_pctype pctype;
1112         struct i40e_fdir_info *fdir_info = &pf->fdir;
1113         struct i40e_fdir_filter *fdir_filter, *node;
1114         struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1115         int ret = 0;
1116
1117         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1118                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1119                         " check the mode in fdir_conf.");
1120                 return -ENOTSUP;
1121         }
1122
1123         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1124                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1125                 return -EINVAL;
1126         }
1127         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1128                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1129                 return -EINVAL;
1130         }
1131         if (filter->input.flow_ext.is_vf &&
1132                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1133                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1134                 return -EINVAL;
1135         }
1136
1137         /* Check if there is the filter in SW list */
1138         memset(&check_filter, 0, sizeof(check_filter));
1139         i40e_fdir_filter_convert(filter, &check_filter);
1140         node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1141         if (add && node) {
1142                 PMD_DRV_LOG(ERR,
1143                             "Conflict with existing flow director rules!");
1144                 return -EINVAL;
1145         }
1146
1147         if (!add && !node) {
1148                 PMD_DRV_LOG(ERR,
1149                             "There's no corresponding flow firector filter!");
1150                 return -EINVAL;
1151         }
1152
1153         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1154
1155         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1156         if (ret < 0) {
1157                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1158                 return ret;
1159         }
1160
1161         if (hw->mac.type == I40E_MAC_X722) {
1162                 /* get translated pctype value in fd pctype register */
1163                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1164                         hw, I40E_GLQF_FD_PCTYPES(
1165                         (int)i40e_flowtype_to_pctype(
1166                         filter->input.flow_type)));
1167         } else
1168                 pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1169
1170         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1171         if (ret < 0) {
1172                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1173                             pctype);
1174                 return ret;
1175         }
1176
1177         if (add) {
1178                 fdir_filter = rte_zmalloc("fdir_filter",
1179                                           sizeof(*fdir_filter), 0);
1180                 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1181                 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1182         } else {
1183                 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1184         }
1185
1186         return ret;
1187 }
1188
1189 /*
1190  * i40e_fdir_filter_programming - Program a flow director filter rule.
1191  * Is done by Flow Director Programming Descriptor followed by packet
1192  * structure that contains the filter fields need to match.
1193  * @pf: board private structure
1194  * @pctype: pctype
1195  * @filter: fdir filter entry
1196  * @add: 0 - delete, 1 - add
1197  */
1198 static int
1199 i40e_fdir_filter_programming(struct i40e_pf *pf,
1200                         enum i40e_filter_pctype pctype,
1201                         const struct rte_eth_fdir_filter *filter,
1202                         bool add)
1203 {
1204         struct i40e_tx_queue *txq = pf->fdir.txq;
1205         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1206         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1207         volatile struct i40e_tx_desc *txdp;
1208         volatile struct i40e_filter_program_desc *fdirdp;
1209         uint32_t td_cmd;
1210         uint16_t vsi_id, i;
1211         uint8_t dest;
1212
1213         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1214         fdirdp = (volatile struct i40e_filter_program_desc *)
1215                         (&(txq->tx_ring[txq->tx_tail]));
1216
1217         fdirdp->qindex_flex_ptype_vsi =
1218                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1219                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1220                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1221
1222         fdirdp->qindex_flex_ptype_vsi |=
1223                         rte_cpu_to_le_32((fdir_action->flex_off <<
1224                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1225                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1226
1227         fdirdp->qindex_flex_ptype_vsi |=
1228                         rte_cpu_to_le_32((pctype <<
1229                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1230                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1231
1232         if (filter->input.flow_ext.is_vf)
1233                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1234         else
1235                 /* Use LAN VSI Id by default */
1236                 vsi_id = pf->main_vsi->vsi_id;
1237         fdirdp->qindex_flex_ptype_vsi |=
1238                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1239                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1240                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1241
1242         fdirdp->dtype_cmd_cntindex =
1243                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1244
1245         if (add)
1246                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1247                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1248                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1249         else
1250                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1251                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1252                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1253
1254         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1255                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1256         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1257                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1258         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1259                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1260         else {
1261                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1262                             " unsupported fdir behavior.");
1263                 return -EINVAL;
1264         }
1265
1266         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1267                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1268                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1269
1270         fdirdp->dtype_cmd_cntindex |=
1271                 rte_cpu_to_le_32((fdir_action->report_status<<
1272                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1273                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1274
1275         fdirdp->dtype_cmd_cntindex |=
1276                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1277         fdirdp->dtype_cmd_cntindex |=
1278                         rte_cpu_to_le_32(
1279                         ((uint32_t)pf->fdir.match_counter_index <<
1280                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1281                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1282
1283         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1284
1285         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1286         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1287         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1288         td_cmd = I40E_TX_DESC_CMD_EOP |
1289                  I40E_TX_DESC_CMD_RS  |
1290                  I40E_TX_DESC_CMD_DUMMY;
1291
1292         txdp->cmd_type_offset_bsz =
1293                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1294
1295         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1296         if (txq->tx_tail >= txq->nb_tx_desc)
1297                 txq->tx_tail = 0;
1298         /* Update the tx tail register */
1299         rte_wmb();
1300         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1301         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1302                 if ((txdp->cmd_type_offset_bsz &
1303                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1304                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1305                         break;
1306                 rte_delay_us(1);
1307         }
1308         if (i >= I40E_FDIR_MAX_WAIT_US) {
1309                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1310                             " time out to get DD on tx queue.");
1311                 return -ETIMEDOUT;
1312         }
1313         /* totally delay 10 ms to check programming status*/
1314         for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1315                 if (i40e_check_fdir_programming_status(rxq) >= 0)
1316                         return 0;
1317                 rte_delay_us(1);
1318         }
1319         PMD_DRV_LOG(ERR,
1320                 "Failed to program FDIR filter: programming status reported.");
1321         return -ETIMEDOUT;
1322 }
1323
1324 /*
1325  * i40e_fdir_flush - clear all filters of Flow Director table
1326  * @pf: board private structure
1327  */
1328 int
1329 i40e_fdir_flush(struct rte_eth_dev *dev)
1330 {
1331         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1332         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1333         uint32_t reg;
1334         uint16_t guarant_cnt, best_cnt;
1335         uint16_t i;
1336
1337         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1338         I40E_WRITE_FLUSH(hw);
1339
1340         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1341                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1342                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1343                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1344                         break;
1345         }
1346         if (i >= I40E_FDIR_FLUSH_RETRY) {
1347                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1348                 return -ETIMEDOUT;
1349         }
1350         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1351                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1352                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1353         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1354                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1355                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1356         if (guarant_cnt != 0 || best_cnt != 0) {
1357                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1358                 return -ENOSYS;
1359         } else
1360                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1361         return 0;
1362 }
1363
1364 static inline void
1365 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1366                         struct rte_eth_flex_payload_cfg *flex_set,
1367                         uint16_t *num)
1368 {
1369         struct i40e_fdir_flex_pit *flex_pit;
1370         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1371         uint16_t src, dst, size, j, k;
1372         uint8_t i, layer_idx;
1373
1374         for (layer_idx = I40E_FLXPLD_L2_IDX;
1375              layer_idx <= I40E_FLXPLD_L4_IDX;
1376              layer_idx++) {
1377                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1378                         ptr->type = RTE_ETH_L2_PAYLOAD;
1379                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1380                         ptr->type = RTE_ETH_L3_PAYLOAD;
1381                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1382                         ptr->type = RTE_ETH_L4_PAYLOAD;
1383
1384                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1385                         flex_pit = &pf->fdir.flex_set[layer_idx *
1386                                 I40E_MAX_FLXPLD_FIED + i];
1387                         if (flex_pit->size == 0)
1388                                 continue;
1389                         src = flex_pit->src_offset * sizeof(uint16_t);
1390                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1391                         size = flex_pit->size * sizeof(uint16_t);
1392                         for (j = src, k = dst; j < src + size; j++, k++)
1393                                 ptr->src_offset[k] = j;
1394                 }
1395                 (*num)++;
1396                 ptr++;
1397         }
1398 }
1399
1400 static inline void
1401 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1402                         struct rte_eth_fdir_flex_mask *flex_mask,
1403                         uint16_t *num)
1404 {
1405         struct i40e_fdir_flex_mask *mask;
1406         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1407         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1408         uint16_t flow_type;
1409         uint8_t i, j;
1410         uint16_t off_bytes, mask_tmp;
1411
1412         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1413              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1414              i++) {
1415                 mask =  &pf->fdir.flex_mask[i];
1416                 if (hw->mac.type == I40E_MAC_X722) {
1417                         if (!I40E_VALID_PCTYPE_X722((enum i40e_filter_pctype)i))
1418                                 continue;
1419                 } else {
1420                         if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1421                                 continue;
1422                 }
1423                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1424                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1425                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1426                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1427                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1428                         } else {
1429                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1430                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1431                         }
1432                 }
1433                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1434                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1435                         mask_tmp = ~mask->bitmask[j].mask;
1436                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1437                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1438                 }
1439                 ptr->flow_type = flow_type;
1440                 ptr++;
1441                 (*num)++;
1442         }
1443 }
1444
1445 /*
1446  * i40e_fdir_info_get - get information of Flow Director
1447  * @pf: ethernet device to get info from
1448  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1449  *    the flow director information.
1450  */
1451 static void
1452 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1453 {
1454         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1455         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1456         uint16_t num_flex_set = 0;
1457         uint16_t num_flex_mask = 0;
1458
1459         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1460                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1461         else
1462                 fdir->mode = RTE_FDIR_MODE_NONE;
1463
1464         fdir->guarant_spc =
1465                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1466         fdir->best_spc =
1467                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1468         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1469         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1470         fdir->flex_payload_unit = sizeof(uint16_t);
1471         fdir->flex_bitmask_unit = sizeof(uint16_t);
1472         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1473         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1474         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1475
1476         i40e_fdir_info_get_flex_set(pf,
1477                                 fdir->flex_conf.flex_set,
1478                                 &num_flex_set);
1479         i40e_fdir_info_get_flex_mask(pf,
1480                                 fdir->flex_conf.flex_mask,
1481                                 &num_flex_mask);
1482
1483         fdir->flex_conf.nb_payloads = num_flex_set;
1484         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1485 }
1486
1487 /*
1488  * i40e_fdir_stat_get - get statistics of Flow Director
1489  * @pf: ethernet device to get info from
1490  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1491  *    the flow director statistics.
1492  */
1493 static void
1494 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1495 {
1496         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1497         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1498         uint32_t fdstat;
1499
1500         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1501         stat->guarant_cnt =
1502                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1503                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1504         stat->best_cnt =
1505                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1506                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1507 }
1508
1509 static int
1510 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1511                      struct rte_eth_fdir_filter_info *info)
1512 {
1513         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1514         int ret = 0;
1515
1516         if (!info) {
1517                 PMD_DRV_LOG(ERR, "Invalid pointer");
1518                 return -EFAULT;
1519         }
1520
1521         switch (info->info_type) {
1522         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1523                 ret = i40e_fdir_filter_inset_select(pf,
1524                                 &(info->info.input_set_conf));
1525                 break;
1526         default:
1527                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1528                             info->info_type);
1529                 return -EINVAL;
1530         }
1531
1532         return ret;
1533 }
1534
1535 /*
1536  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1537  * @pf: board private structure
1538  * @filter_op:operation will be taken.
1539  * @arg: a pointer to specific structure corresponding to the filter_op
1540  */
1541 int
1542 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1543                        enum rte_filter_op filter_op,
1544                        void *arg)
1545 {
1546         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1547         int ret = 0;
1548
1549         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1550                 return -ENOTSUP;
1551
1552         if (filter_op == RTE_ETH_FILTER_NOP)
1553                 return 0;
1554
1555         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1556                 return -EINVAL;
1557
1558         switch (filter_op) {
1559         case RTE_ETH_FILTER_ADD:
1560                 ret = i40e_add_del_fdir_filter(dev,
1561                         (struct rte_eth_fdir_filter *)arg,
1562                         TRUE);
1563                 break;
1564         case RTE_ETH_FILTER_DELETE:
1565                 ret = i40e_add_del_fdir_filter(dev,
1566                         (struct rte_eth_fdir_filter *)arg,
1567                         FALSE);
1568                 break;
1569         case RTE_ETH_FILTER_FLUSH:
1570                 ret = i40e_fdir_flush(dev);
1571                 break;
1572         case RTE_ETH_FILTER_INFO:
1573                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1574                 break;
1575         case RTE_ETH_FILTER_SET:
1576                 ret = i40e_fdir_filter_set(dev,
1577                         (struct rte_eth_fdir_filter_info *)arg);
1578                 break;
1579         case RTE_ETH_FILTER_STATS:
1580                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1581                 break;
1582         default:
1583                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1584                 ret = -EINVAL;
1585                 break;
1586         }
1587         return ret;
1588 }
1589
1590 /* Restore flow director filter */
1591 void
1592 i40e_fdir_filter_restore(struct i40e_pf *pf)
1593 {
1594         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
1595         struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
1596         struct i40e_fdir_filter *f;
1597         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1598         uint32_t fdstat;
1599         uint32_t guarant_cnt;  /**< Number of filters in guaranteed spaces. */
1600         uint32_t best_cnt;     /**< Number of filters in best effort spaces. */
1601
1602         TAILQ_FOREACH(f, fdir_list, rules)
1603                 i40e_add_del_fdir_filter(dev, &f->fdir, TRUE);
1604
1605         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1606         guarant_cnt =
1607                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1608                            I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1609         best_cnt =
1610                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1611                            I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1612
1613         PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d,  Best count: %d",
1614                     guarant_cnt, best_cnt);
1615 }