drivers/net/i40e/i40e_fdir.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41
  42 #include <rte_ether.h>
  43 #include <rte_ethdev.h>
  44 #include <rte_log.h>
  45 #include <rte_memzone.h>
  46 #include <rte_malloc.h>
  47 #include <rte_arp.h>
  48 #include <rte_ip.h>
  49 #include <rte_udp.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52
  53 #include "i40e_logs.h"
  54 #include "base/i40e_type.h"
  55 #include "i40e_ethdev.h"
  56 #include "i40e_rxtx.h"
  57
  58 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  59 #ifndef IPV6_ADDR_LEN
  60 #define IPV6_ADDR_LEN              16
  61 #endif
  62
  63 #define I40E_FDIR_PKT_LEN                   512
  64 #define I40E_FDIR_IP_DEFAULT_LEN            420
  65 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  66 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  67 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  68 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60300000
  69 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  70 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  71 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  72
  73 /* Wait count and interval for fdir filter programming */
  74 #define I40E_FDIR_WAIT_COUNT       10
  75 #define I40E_FDIR_WAIT_INTERVAL_US 1000
  76
  77 /* Wait count and interval for fdir filter flush */
  78 #define I40E_FDIR_FLUSH_RETRY       50
  79 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  80
  81 #define I40E_COUNTER_PF           2
  82 /* Statistic counter index for one pf */
  83 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  84 #define I40E_MAX_FLX_SOURCE_OFF           480
  85 #define I40E_FLX_OFFSET_IN_FIELD_VECTOR   50
  86
  87 #define NONUSE_FLX_PIT_DEST_OFF 63
  88 #define NONUSE_FLX_PIT_FSIZE    1
  89 #define MK_FLX_PIT(src_offset, fsize, dst_offset) ( \
  90         (((src_offset) << I40E_PRTQF_FLX_PIT_SOURCE_OFF_SHIFT) & \
  91                 I40E_PRTQF_FLX_PIT_SOURCE_OFF_MASK) | \
  92         (((fsize) << I40E_PRTQF_FLX_PIT_FSIZE_SHIFT) & \
  93                         I40E_PRTQF_FLX_PIT_FSIZE_MASK) | \
  94         ((((dst_offset) + I40E_FLX_OFFSET_IN_FIELD_VECTOR) << \
  95                         I40E_PRTQF_FLX_PIT_DEST_OFF_SHIFT) & \
  96                         I40E_PRTQF_FLX_PIT_DEST_OFF_MASK))
  97
  98 #define I40E_FDIR_FLOWS ( \
  99         (1 << RTE_ETH_FLOW_FRAG_IPV4) | \
 100         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
 101         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
 102         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
 103         (1 << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
 104         (1 << RTE_ETH_FLOW_FRAG_IPV6) | \
 105         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
 106         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
 107         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
 108         (1 << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
 109         (1 << RTE_ETH_FLOW_L2_PAYLOAD))
 110
 111 #define I40E_FLEX_WORD_MASK(off) (0x80 >> (off))
 112
 113 static int i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq);
 114 static int i40e_check_fdir_flex_conf(
 115         const struct rte_eth_fdir_flex_conf *conf);
 116 static void i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 117                          const struct rte_eth_flex_payload_cfg *cfg);
 118 static void i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 119                 enum i40e_filter_pctype pctype,
 120                 const struct rte_eth_fdir_flex_mask *mask_cfg);
 121 static int i40e_fdir_construct_pkt(struct i40e_pf *pf,
 122                                      const struct rte_eth_fdir_input *fdir_input,
 123                                      unsigned char *raw_pkt);
 124 static int i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
 125                             const struct rte_eth_fdir_filter *filter,
 126                             bool add);
 127 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
 128                         enum i40e_filter_pctype pctype,
 129                         const struct rte_eth_fdir_filter *filter,
 130                         bool add);
 131 static int i40e_fdir_flush(struct rte_eth_dev *dev);
 132 static void i40e_fdir_info_get(struct rte_eth_dev *dev,
 133                            struct rte_eth_fdir_info *fdir);
 134 static void i40e_fdir_stats_get(struct rte_eth_dev *dev,
 135                            struct rte_eth_fdir_stats *stat);
 136
 137 static int
 138 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 139 {
 140         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 141         struct i40e_hmc_obj_rxq rx_ctx;
 142         int err = I40E_SUCCESS;
 143
 144         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 145         /* Init the RX queue in hardware */
 146         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 147         rx_ctx.hbuff = 0;
 148         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 149         rx_ctx.qlen = rxq->nb_rx_desc;
 150 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 151         rx_ctx.dsize = 1;
 152 #endif
 153         rx_ctx.dtype = i40e_header_split_none;
 154         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 155         rx_ctx.rxmax = ETHER_MAX_LEN;
 156         rx_ctx.tphrdesc_ena = 1;
 157         rx_ctx.tphwdesc_ena = 1;
 158         rx_ctx.tphdata_ena = 1;
 159         rx_ctx.tphhead_ena = 1;
 160         rx_ctx.lrxqthresh = 2;
 161         rx_ctx.crcstrip = 0;
 162         rx_ctx.l2tsel = 1;
 163         rx_ctx.showiv = 1;
 164         rx_ctx.prefena = 1;
 165
 166         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 167         if (err != I40E_SUCCESS) {
 168                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 169                 return err;
 170         }
 171         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 172         if (err != I40E_SUCCESS) {
 173                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 174                 return err;
 175         }
 176         rxq->qrx_tail = hw->hw_addr +
 177                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 178
 179         rte_wmb();
 180         /* Init the RX tail regieter. */
 181         I40E_PCI_REG_WRITE(rxq->qrx_tail, 0);
 182         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 183
 184         return err;
 185 }
 186
 187 /*
 188  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 189  * @pf: board private structure
 190  */
 191 int
 192 i40e_fdir_setup(struct i40e_pf *pf)
 193 {
 194         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 195         struct i40e_vsi *vsi;
 196         int err = I40E_SUCCESS;
 197         char z_name[RTE_MEMZONE_NAMESIZE];
 198         const struct rte_memzone *mz = NULL;
 199         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 200
 201         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 202                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 203                 return I40E_NOT_SUPPORTED;
 204         }
 205
 206         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 207                         " num_filters_best_effort = %u.",
 208                         hw->func_caps.fd_filters_guaranteed,
 209                         hw->func_caps.fd_filters_best_effort);
 210
 211         vsi = pf->fdir.fdir_vsi;
 212         if (vsi) {
 213                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 214                 return I40E_SUCCESS;
 215         }
 216         /* make new FDIR VSI */
 217         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 218         if (!vsi) {
 219                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 220                 return I40E_ERR_NO_AVAILABLE_VSI;
 221         }
 222         pf->fdir.fdir_vsi = vsi;
 223
 224         /*Fdir tx queue setup*/
 225         err = i40e_fdir_setup_tx_resources(pf);
 226         if (err) {
 227                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 228                 goto fail_setup_tx;
 229         }
 230
 231         /*Fdir rx queue setup*/
 232         err = i40e_fdir_setup_rx_resources(pf);
 233         if (err) {
 234                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 235                 goto fail_setup_rx;
 236         }
 237
 238         err = i40e_tx_queue_init(pf->fdir.txq);
 239         if (err) {
 240                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 241                 goto fail_mem;
 242         }
 243
 244         /* need switch on before dev start*/
 245         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 246         if (err) {
 247                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 248                 goto fail_mem;
 249         }
 250
 251         /* Init the rx queue in hardware */
 252         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 253         if (err) {
 254                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 255                 goto fail_mem;
 256         }
 257
 258         /* switch on rx queue */
 259         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 260         if (err) {
 261                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 262                 goto fail_mem;
 263         }
 264
 265         /* reserve memory for the fdir programming packet */
 266         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 267                         eth_dev->driver->pci_drv.name,
 268                         I40E_FDIR_MZ_NAME,
 269                         eth_dev->data->port_id);
 270         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 271         if (!mz) {
 272                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 273                                  "flow director program packet.");
 274                 err = I40E_ERR_NO_MEMORY;
 275                 goto fail_mem;
 276         }
 277         pf->fdir.prg_pkt = mz->addr;
 278 #ifdef RTE_LIBRTE_XEN_DOM0
 279         pf->fdir.dma_addr = rte_mem_phy2mch(mz->memseg_id, mz->phys_addr);
 280 #else
 281         pf->fdir.dma_addr = (uint64_t)mz->phys_addr;
 282 #endif
 283         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 284         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 285                     vsi->base_queue);
 286         return I40E_SUCCESS;
 287
 288 fail_mem:
 289         i40e_dev_rx_queue_release(pf->fdir.rxq);
 290         pf->fdir.rxq = NULL;
 291 fail_setup_rx:
 292         i40e_dev_tx_queue_release(pf->fdir.txq);
 293         pf->fdir.txq = NULL;
 294 fail_setup_tx:
 295         i40e_vsi_release(vsi);
 296         pf->fdir.fdir_vsi = NULL;
 297         return err;
 298 }
 299
 300 /*
 301  * i40e_fdir_teardown - release the Flow Director resources
 302  * @pf: board private structure
 303  */
 304 void
 305 i40e_fdir_teardown(struct i40e_pf *pf)
 306 {
 307         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 308         struct i40e_vsi *vsi;
 309
 310         vsi = pf->fdir.fdir_vsi;
 311         if (!vsi)
 312                 return;
 313         i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 314         i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 315         i40e_dev_rx_queue_release(pf->fdir.rxq);
 316         pf->fdir.rxq = NULL;
 317         i40e_dev_tx_queue_release(pf->fdir.txq);
 318         pf->fdir.txq = NULL;
 319         i40e_vsi_release(vsi);
 320         pf->fdir.fdir_vsi = NULL;
 321 }
 322
 323 /* check whether the flow director table in empty */
 324 static inline int
 325 i40e_fdir_empty(struct i40e_hw *hw)
 326 {
 327         uint32_t guarant_cnt, best_cnt;
 328
 329         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 330                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 331                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 332         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 333                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 334                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 335         if (best_cnt + guarant_cnt > 0)
 336                 return -1;
 337
 338         return 0;
 339 }
 340
 341 /*
 342  * Initialize the configuration about bytes stream extracted as flexible payload
 343  * and mask setting
 344  */
 345 static inline void
 346 i40e_init_flx_pld(struct i40e_pf *pf)
 347 {
 348         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 349         uint8_t pctype;
 350         int i, index;
 351
 352         /*
 353          * Define the bytes stream extracted as flexible payload in
 354          * field vector. By default, select 8 words from the beginning
 355          * of payload as flexible payload.
 356          */
 357         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 358                 index = i * I40E_MAX_FLXPLD_FIED;
 359                 pf->fdir.flex_set[index].src_offset = 0;
 360                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 361                 pf->fdir.flex_set[index].dst_offset = 0;
 362                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 363                 I40E_WRITE_REG(hw,
 364                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 365                 I40E_WRITE_REG(hw,
 366                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 367         }
 368
 369         /* initialize the masks */
 370         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 371              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 372                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)pctype))
 373                         continue;
 374                 pf->fdir.flex_mask[pctype].word_mask = 0;
 375                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 376                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 377                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 378                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 379                         I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 380                 }
 381         }
 382 }
 383
 384 #define I40E_WORD(hi, lo) (uint16_t)((((hi) << 8) & 0xFF00) | ((lo) & 0xFF))
 385
 386 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 387         if ((flex_pit2).src_offset < \
 388                 (flex_pit1).src_offset + (flex_pit1).size) { \
 389                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 390                         " less than than previous offset" \
 391                         " + previous FSIZE."); \
 392                 return -EINVAL; \
 393         } \
 394 } while (0)
 395
 396 /*
 397  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 398  * and the flex_pit will be sorted by it's src_offset value
 399  */
 400 static inline uint16_t
 401 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 402                         struct i40e_fdir_flex_pit *flex_pit)
 403 {
 404         uint16_t src_tmp, size, num = 0;
 405         uint16_t i, k, j = 0;
 406
 407         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 408                 size = 1;
 409                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 410                         if (src_offset[j + 1] == src_offset[j] + 1)
 411                                 size++;
 412                         else
 413                                 break;
 414                 }
 415                 src_tmp = src_offset[j] + 1 - size;
 416                 /* the flex_pit need to be sort by src_offset */
 417                 for (i = 0; i < num; i++) {
 418                         if (src_tmp < flex_pit[i].src_offset)
 419                                 break;
 420                 }
 421                 /* if insert required, move backward */
 422                 for (k = num; k > i; k--)
 423                         flex_pit[k] = flex_pit[k - 1];
 424                 /* insert */
 425                 flex_pit[i].dst_offset = j + 1 - size;
 426                 flex_pit[i].src_offset = src_tmp;
 427                 flex_pit[i].size = size;
 428                 j++;
 429                 num++;
 430         }
 431         return num;
 432 }
 433
 434 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 435 static inline int
 436 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 437 {
 438         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 439         uint16_t num, i;
 440
 441         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 442                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 443                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 444                         return -EINVAL;
 445                 }
 446         }
 447
 448         memset(flex_pit, 0, sizeof(flex_pit));
 449         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 450         if (num > I40E_MAX_FLXPLD_FIED) {
 451                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 452                 return -EINVAL;
 453         }
 454         for (i = 0; i < num; i++) {
 455                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 456                         flex_pit[i].src_offset & 0x01) {
 457                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 458                                 " in word");
 459                         return -EINVAL;
 460                 }
 461                 if (i != num - 1)
 462                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 463         }
 464         return 0;
 465 }
 466
 467 /*
 468  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 469  * arguments are valid
 470  */
 471 static int
 472 i40e_check_fdir_flex_conf(const struct rte_eth_fdir_flex_conf *conf)
 473 {
 474         const struct rte_eth_flex_payload_cfg *flex_cfg;
 475         const struct rte_eth_fdir_flex_mask *flex_mask;
 476         uint16_t mask_tmp;
 477         uint8_t nb_bitmask;
 478         uint16_t i, j;
 479         int ret = 0;
 480
 481         if (conf == NULL) {
 482                 PMD_DRV_LOG(INFO, "NULL pointer.");
 483                 return -EINVAL;
 484         }
 485         /* check flexible payload setting configuration */
 486         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 487                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 488                 return -EINVAL;
 489         }
 490         for (i = 0; i < conf->nb_payloads; i++) {
 491                 flex_cfg = &conf->flex_set[i];
 492                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 493                         PMD_DRV_LOG(ERR, "invalid payload type.");
 494                         return -EINVAL;
 495                 }
 496                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 497                 if (ret < 0) {
 498                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 499                         return -EINVAL;
 500                 }
 501         }
 502
 503         /* check flex mask setting configuration */
 504         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 505                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 506                 return -EINVAL;
 507         }
 508         for (i = 0; i < conf->nb_flexmasks; i++) {
 509                 flex_mask = &conf->flex_mask[i];
 510                 if (!I40E_VALID_FLOW(flex_mask->flow_type)) {
 511                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 512                         return -EINVAL;
 513                 }
 514                 nb_bitmask = 0;
 515                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 516                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 517                                              flex_mask->mask[j + 1]);
 518                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 519                                 nb_bitmask++;
 520                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 521                                         PMD_DRV_LOG(ERR, " exceed maximal"
 522                                                 " number of bitmasks.");
 523                                         return -EINVAL;
 524                                 }
 525                         }
 526                 }
 527         }
 528         return 0;
 529 }
 530
 531 /*
 532  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 533  * @pf: board private structure
 534  * @cfg: the rule how bytes stream is extracted as flexible payload
 535  */
 536 static void
 537 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 538                          const struct rte_eth_flex_payload_cfg *cfg)
 539 {
 540         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 541         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 542         uint32_t flx_pit;
 543         uint16_t num, min_next_off;  /* in words */
 544         uint8_t field_idx = 0;
 545         uint8_t layer_idx = 0;
 546         uint16_t i;
 547
 548         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 549                 layer_idx = I40E_FLXPLD_L2_IDX;
 550         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 551                 layer_idx = I40E_FLXPLD_L3_IDX;
 552         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 553                 layer_idx = I40E_FLXPLD_L4_IDX;
 554
 555         memset(flex_pit, 0, sizeof(flex_pit));
 556         num = i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit);
 557
 558         for (i = 0; i < RTE_MIN(num, RTE_DIM(flex_pit)); i++) {
 559                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 560                 /* record the info in fdir structure */
 561                 pf->fdir.flex_set[field_idx].src_offset =
 562                         flex_pit[i].src_offset / sizeof(uint16_t);
 563                 pf->fdir.flex_set[field_idx].size =
 564                         flex_pit[i].size / sizeof(uint16_t);
 565                 pf->fdir.flex_set[field_idx].dst_offset =
 566                         flex_pit[i].dst_offset / sizeof(uint16_t);
 567                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 568                                 pf->fdir.flex_set[field_idx].size,
 569                                 pf->fdir.flex_set[field_idx].dst_offset);
 570
 571                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 572         }
 573         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 574                                 pf->fdir.flex_set[field_idx].size;
 575
 576         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 577                 /* set the non-used register obeying register's constrain */
 578                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 579                            NONUSE_FLX_PIT_DEST_OFF);
 580                 I40E_WRITE_REG(hw,
 581                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 582                         flx_pit);
 583                 min_next_off++;
 584         }
 585 }
 586
 587 /*
 588  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 589  * @pf: board private structure
 590  * @pctype: packet classify type
 591  * @flex_masks: mask for flexible payload
 592  */
 593 static void
 594 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 595                 enum i40e_filter_pctype pctype,
 596                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 597 {
 598         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 599         struct i40e_fdir_flex_mask *flex_mask;
 600         uint32_t flxinset, fd_mask;
 601         uint16_t mask_tmp;
 602         uint8_t i, nb_bitmask = 0;
 603
 604         flex_mask = &pf->fdir.flex_mask[pctype];
 605         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 606         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 607                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 608                 if (mask_tmp != 0x0) {
 609                         flex_mask->word_mask |=
 610                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 611                         if (mask_tmp != UINT16_MAX) {
 612                                 /* set bit mask */
 613                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 614                                 flex_mask->bitmask[nb_bitmask].offset =
 615                                         i / sizeof(uint16_t);
 616                                 nb_bitmask++;
 617                         }
 618                 }
 619         }
 620         /* write mask to hw */
 621         flxinset = (flex_mask->word_mask <<
 622                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 623                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 624         I40E_WRITE_REG(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 625
 626         for (i = 0; i < nb_bitmask; i++) {
 627                 fd_mask = (flex_mask->bitmask[i].mask <<
 628                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 629                         I40E_PRTQF_FD_MSK_MASK_MASK;
 630                 fd_mask |= ((flex_mask->bitmask[i].offset +
 631                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 632                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 633                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 634                 I40E_WRITE_REG(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 635         }
 636 }
 637
 638 /*
 639  * Configure flow director related setting
 640  */
 641 int
 642 i40e_fdir_configure(struct rte_eth_dev *dev)
 643 {
 644         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 645         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 646         struct rte_eth_fdir_flex_conf *conf;
 647         enum i40e_filter_pctype pctype;
 648         uint32_t val;
 649         uint8_t i;
 650         int ret = 0;
 651
 652         /*
 653         * configuration need to be done before
 654         * flow director filters are added
 655         * If filters exist, flush them.
 656         */
 657         if (i40e_fdir_empty(hw) < 0) {
 658                 ret = i40e_fdir_flush(dev);
 659                 if (ret) {
 660                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 661                         return ret;
 662                 }
 663         }
 664
 665         /* enable FDIR filter */
 666         val = I40E_READ_REG(hw, I40E_PFQF_CTL_0);
 667         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 668         I40E_WRITE_REG(hw, I40E_PFQF_CTL_0, val);
 669
 670         i40e_init_flx_pld(pf); /* set flex config to default value */
 671
 672         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 673         ret = i40e_check_fdir_flex_conf(conf);
 674         if (ret < 0) {
 675                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 676                 return -EINVAL;
 677         }
 678         /* configure flex payload */
 679         for (i = 0; i < conf->nb_payloads; i++)
 680                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 681         /* configure flex mask*/
 682         for (i = 0; i < conf->nb_flexmasks; i++) {
 683                 pctype = i40e_flowtype_to_pctype(conf->flex_mask[i].flow_type);
 684                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 685         }
 686
 687         return ret;
 688 }
 689
 690 static inline void
 691 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 692                                unsigned char *raw_pkt)
 693 {
 694         struct ether_hdr *ether = (struct ether_hdr *)raw_pkt;
 695         struct ipv4_hdr *ip;
 696         struct ipv6_hdr *ip6;
 697         static const uint8_t next_proto[] = {
 698                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 699                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 700                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 701                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 702                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 703                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 704                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 705                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 706                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 707                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 708         };
 709
 710         switch (fdir_input->flow_type) {
 711         case RTE_ETH_FLOW_L2_PAYLOAD:
 712                 ether->ether_type = fdir_input->flow.l2_flow.ether_type;
 713                 break;
 714         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 715         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 716         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 717         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 718         case RTE_ETH_FLOW_FRAG_IPV4:
 719                 ip = (struct ipv4_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 720
 721                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 722                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 723                 /* set len to by default */
 724                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 725                 ip->time_to_live = I40E_FDIR_IP_DEFAULT_TTL;
 726                 /*
 727                  * The source and destination fields in the transmitted packet
 728                  * need to be presented in a reversed order with respect
 729                  * to the expected received packets.
 730                  */
 731                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 732                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 733                 ip->next_proto_id = next_proto[fdir_input->flow_type];
 734                 break;
 735         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 736         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 737         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 738         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 739         case RTE_ETH_FLOW_FRAG_IPV6:
 740                 ip6 = (struct ipv6_hdr *)(raw_pkt + sizeof(struct ether_hdr));
 741
 742                 ether->ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 743                 ip6->vtc_flow =
 744                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW);
 745                 ip6->payload_len =
 746                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 747                 ip6->hop_limits = I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 748
 749                 /*
 750                  * The source and destination fields in the transmitted packet
 751                  * need to be presented in a reversed order with respect
 752                  * to the expected received packets.
 753                  */
 754                 rte_memcpy(&(ip6->src_addr),
 755                            &(fdir_input->flow.ipv6_flow.dst_ip),
 756                            IPV6_ADDR_LEN);
 757                 rte_memcpy(&(ip6->dst_addr),
 758                            &(fdir_input->flow.ipv6_flow.src_ip),
 759                            IPV6_ADDR_LEN);
 760                 ip6->proto = next_proto[fdir_input->flow_type];
 761                 break;
 762         default:
 763                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 764                             fdir_input->flow_type);
 765                 break;
 766         }
 767 }
 768
 769
 770 /*
 771  * i40e_fdir_construct_pkt - construct packet based on fields in input
 772  * @pf: board private structure
 773  * @fdir_input: input set of the flow director entry
 774  * @raw_pkt: a packet to be constructed
 775  */
 776 static int
 777 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 778                              const struct rte_eth_fdir_input *fdir_input,
 779                              unsigned char *raw_pkt)
 780 {
 781         unsigned char *payload, *ptr;
 782         struct udp_hdr *udp;
 783         struct tcp_hdr *tcp;
 784         struct sctp_hdr *sctp;
 785         uint8_t size, dst = 0;
 786         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 787
 788         /* fill the ethernet and IP head */
 789         i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt);
 790
 791         /* fill the L4 head */
 792         switch (fdir_input->flow_type) {
 793         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 794                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 795                                 sizeof(struct ipv4_hdr));
 796                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 797                 /*
 798                  * The source and destination fields in the transmitted packet
 799                  * need to be presented in a reversed order with respect
 800                  * to the expected received packets.
 801                  */
 802                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 803                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 804                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 805                 break;
 806
 807         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 808                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 809                                          sizeof(struct ipv4_hdr));
 810                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 811                 /*
 812                  * The source and destination fields in the transmitted packet
 813                  * need to be presented in a reversed order with respect
 814                  * to the expected received packets.
 815                  */
 816                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 817                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 818                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 819                 break;
 820
 821         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 822                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 823                                            sizeof(struct ipv4_hdr));
 824                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 825                 /*
 826                  * The source and destination fields in the transmitted packet
 827                  * need to be presented in a reversed order with respect
 828                  * to the expected received packets.
 829                  */
 830                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 831                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 832                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 833                 break;
 834
 835         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 836         case RTE_ETH_FLOW_FRAG_IPV4:
 837                 payload = raw_pkt + sizeof(struct ether_hdr) +
 838                           sizeof(struct ipv4_hdr);
 839                 set_idx = I40E_FLXPLD_L3_IDX;
 840                 break;
 841
 842         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 843                 udp = (struct udp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 844                                          sizeof(struct ipv6_hdr));
 845                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 846                 /*
 847                  * The source and destination fields in the transmitted packet
 848                  * need to be presented in a reversed order with respect
 849                  * to the expected received packets.
 850                  */
 851                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 852                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 853                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 854                 break;
 855
 856         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 857                 tcp = (struct tcp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 858                                          sizeof(struct ipv6_hdr));
 859                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 860                 /*
 861                  * The source and destination fields in the transmitted packet
 862                  * need to be presented in a reversed order with respect
 863                  * to the expected received packets.
 864                  */
 865                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 866                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 867                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 868                 break;
 869
 870         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 871                 sctp = (struct sctp_hdr *)(raw_pkt + sizeof(struct ether_hdr) +
 872                                            sizeof(struct ipv6_hdr));
 873                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 874                 /*
 875                  * The source and destination fields in the transmitted packet
 876                  * need to be presented in a reversed order with respect
 877                  * to the expected received packets.
 878                  */
 879                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 880                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 881                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 882                 break;
 883
 884         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 885         case RTE_ETH_FLOW_FRAG_IPV6:
 886                 payload = raw_pkt + sizeof(struct ether_hdr) +
 887                           sizeof(struct ipv6_hdr);
 888                 set_idx = I40E_FLXPLD_L3_IDX;
 889                 break;
 890         case RTE_ETH_FLOW_L2_PAYLOAD:
 891                 payload = raw_pkt + sizeof(struct ether_hdr);
 892                 /*
 893                  * ARP packet is a special case on which the payload
 894                  * starts after the whole ARP header
 895                  */
 896                 if (fdir_input->flow.l2_flow.ether_type ==
 897                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 898                         payload += sizeof(struct arp_hdr);
 899                 set_idx = I40E_FLXPLD_L2_IDX;
 900                 break;
 901         default:
 902                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 903                 return -EINVAL;
 904         }
 905
 906         /* fill the flexbytes to payload */
 907         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 908                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 909                 size = pf->fdir.flex_set[pit_idx].size;
 910                 if (size == 0)
 911                         continue;
 912                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 913                 ptr = payload +
 914                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 915                 (void)rte_memcpy(ptr,
 916                                  &fdir_input->flow_ext.flexbytes[dst],
 917                                  size * sizeof(uint16_t));
 918         }
 919
 920         return 0;
 921 }
 922
 923 /* Construct the tx flags */
 924 static inline uint64_t
 925 i40e_build_ctob(uint32_t td_cmd,
 926                 uint32_t td_offset,
 927                 unsigned int size,
 928                 uint32_t td_tag)
 929 {
 930         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 931                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 932                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 933                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 934                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 935 }
 936
 937 /*
 938  * check the programming status descriptor in rx queue.
 939  * done after Programming Flow Director is programmed on
 940  * tx queue
 941  */
 942 static inline int
 943 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
 944 {
 945         volatile union i40e_rx_desc *rxdp;
 946         uint64_t qword1;
 947         uint32_t rx_status;
 948         uint32_t len, id;
 949         uint32_t error;
 950         int ret = 0;
 951
 952         rxdp = &rxq->rx_ring[rxq->rx_tail];
 953         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 954         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 955                         >> I40E_RXD_QW1_STATUS_SHIFT;
 956
 957         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
 958                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
 959                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
 960                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
 961
 962                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
 963                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
 964                         error = (qword1 &
 965                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
 966                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
 967                         if (error == (0x1 <<
 968                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
 969                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
 970                                             " (FD_ID %u): programming status"
 971                                             " reported.",
 972                                             rxdp->wb.qword0.hi_dword.fd_id);
 973                                 ret = -1;
 974                         } else if (error == (0x1 <<
 975                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
 976                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
 977                                             " (FD_ID %u): programming status"
 978                                             " reported.",
 979                                             rxdp->wb.qword0.hi_dword.fd_id);
 980                                 ret = -1;
 981                         } else
 982                                 PMD_DRV_LOG(ERR, "invalid programming status"
 983                                             " reported, error = %u.", error);
 984                 } else
 985                         PMD_DRV_LOG(ERR, "unknown programming status"
 986                                     " reported, len = %d, id = %u.", len, id);
 987                 rxdp->wb.qword1.status_error_len = 0;
 988                 rxq->rx_tail++;
 989                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
 990                         rxq->rx_tail = 0;
 991         }
 992         return ret;
 993 }
 994
 995 /*
 996  * i40e_add_del_fdir_filter - add or remove a flow director filter.
 997  * @pf: board private structure
 998  * @filter: fdir filter entry
 999  * @add: 0 - delete, 1 - add
1000  */
1001 static int
1002 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1003                             const struct rte_eth_fdir_filter *filter,
1004                             bool add)
1005 {
1006         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1007         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1008         enum i40e_filter_pctype pctype;
1009         int ret = 0;
1010
1011         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1012                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1013                         " check the mode in fdir_conf.");
1014                 return -ENOTSUP;
1015         }
1016
1017         if (!I40E_VALID_FLOW(filter->input.flow_type)) {
1018                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1019                 return -EINVAL;
1020         }
1021         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1022                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1023                 return -EINVAL;
1024         }
1025         if (filter->input.flow_ext.is_vf &&
1026                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1027                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1028                 return -EINVAL;
1029         }
1030
1031         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1032
1033         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1034         if (ret < 0) {
1035                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1036                 return ret;
1037         }
1038         pctype = i40e_flowtype_to_pctype(filter->input.flow_type);
1039         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1040         if (ret < 0) {
1041                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1042                             pctype);
1043                 return ret;
1044         }
1045         return ret;
1046 }
1047
1048 /*
1049  * i40e_fdir_filter_programming - Program a flow director filter rule.
1050  * Is done by Flow Director Programming Descriptor followed by packet
1051  * structure that contains the filter fields need to match.
1052  * @pf: board private structure
1053  * @pctype: pctype
1054  * @filter: fdir filter entry
1055  * @add: 0 - delelet, 1 - add
1056  */
1057 static int
1058 i40e_fdir_filter_programming(struct i40e_pf *pf,
1059                         enum i40e_filter_pctype pctype,
1060                         const struct rte_eth_fdir_filter *filter,
1061                         bool add)
1062 {
1063         struct i40e_tx_queue *txq = pf->fdir.txq;
1064         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1065         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1066         volatile struct i40e_tx_desc *txdp;
1067         volatile struct i40e_filter_program_desc *fdirdp;
1068         uint32_t td_cmd;
1069         uint16_t vsi_id, i;
1070         uint8_t dest;
1071
1072         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1073         fdirdp = (volatile struct i40e_filter_program_desc *)
1074                         (&(txq->tx_ring[txq->tx_tail]));
1075
1076         fdirdp->qindex_flex_ptype_vsi =
1077                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1078                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1079                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1080
1081         fdirdp->qindex_flex_ptype_vsi |=
1082                         rte_cpu_to_le_32((fdir_action->flex_off <<
1083                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1084                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1085
1086         fdirdp->qindex_flex_ptype_vsi |=
1087                         rte_cpu_to_le_32((pctype <<
1088                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1089                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1090
1091         if (filter->input.flow_ext.is_vf)
1092                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1093         else
1094                 /* Use LAN VSI Id by default */
1095                 vsi_id = pf->main_vsi->vsi_id;
1096         fdirdp->qindex_flex_ptype_vsi |=
1097                 rte_cpu_to_le_32((vsi_id <<
1098                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1099                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1100
1101         fdirdp->dtype_cmd_cntindex =
1102                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1103
1104         if (add)
1105                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1106                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1107                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1108         else
1109                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1110                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1111                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1112
1113         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1114                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1115         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1116                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1117         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1118                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1119         else {
1120                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1121                             " unsupported fdir behavior.");
1122                 return -EINVAL;
1123         }
1124
1125         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1126                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1127                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1128
1129         fdirdp->dtype_cmd_cntindex |=
1130                 rte_cpu_to_le_32((fdir_action->report_status<<
1131                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1132                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1133
1134         fdirdp->dtype_cmd_cntindex |=
1135                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1136         fdirdp->dtype_cmd_cntindex |=
1137                         rte_cpu_to_le_32((pf->fdir.match_counter_index <<
1138                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1139                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1140
1141         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1142
1143         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1144         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1145         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1146         td_cmd = I40E_TX_DESC_CMD_EOP |
1147                  I40E_TX_DESC_CMD_RS  |
1148                  I40E_TX_DESC_CMD_DUMMY;
1149
1150         txdp->cmd_type_offset_bsz =
1151                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1152
1153         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1154         if (txq->tx_tail >= txq->nb_tx_desc)
1155                 txq->tx_tail = 0;
1156         /* Update the tx tail register */
1157         rte_wmb();
1158         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1159
1160         for (i = 0; i < I40E_FDIR_WAIT_COUNT; i++) {
1161                 rte_delay_us(I40E_FDIR_WAIT_INTERVAL_US);
1162                 if ((txdp->cmd_type_offset_bsz &
1163                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1164                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1165                         break;
1166         }
1167         if (i >= I40E_FDIR_WAIT_COUNT) {
1168                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1169                             " time out to get DD on tx queue.");
1170                 return -ETIMEDOUT;
1171         }
1172         /* totally delay 10 ms to check programming status*/
1173         rte_delay_us((I40E_FDIR_WAIT_COUNT - i) * I40E_FDIR_WAIT_INTERVAL_US);
1174         if (i40e_check_fdir_programming_status(rxq) < 0) {
1175                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1176                             " programming status reported.");
1177                 return -ENOSYS;
1178         }
1179
1180         return 0;
1181 }
1182
1183 /*
1184  * i40e_fdir_flush - clear all filters of Flow Director table
1185  * @pf: board private structure
1186  */
1187 static int
1188 i40e_fdir_flush(struct rte_eth_dev *dev)
1189 {
1190         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1191         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1192         uint32_t reg;
1193         uint16_t guarant_cnt, best_cnt;
1194         uint16_t i;
1195
1196         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1197         I40E_WRITE_FLUSH(hw);
1198
1199         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1200                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1201                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1202                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1203                         break;
1204         }
1205         if (i >= I40E_FDIR_FLUSH_RETRY) {
1206                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1207                 return -ETIMEDOUT;
1208         }
1209         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1210                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1211                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1212         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1213                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1214                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1215         if (guarant_cnt != 0 || best_cnt != 0) {
1216                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1217                 return -ENOSYS;
1218         } else
1219                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1220         return 0;
1221 }
1222
1223 static inline void
1224 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1225                         struct rte_eth_flex_payload_cfg *flex_set,
1226                         uint16_t *num)
1227 {
1228         struct i40e_fdir_flex_pit *flex_pit;
1229         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1230         uint16_t src, dst, size, j, k;
1231         uint8_t i, layer_idx;
1232
1233         for (layer_idx = I40E_FLXPLD_L2_IDX;
1234              layer_idx <= I40E_FLXPLD_L4_IDX;
1235              layer_idx++) {
1236                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1237                         ptr->type = RTE_ETH_L2_PAYLOAD;
1238                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1239                         ptr->type = RTE_ETH_L3_PAYLOAD;
1240                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1241                         ptr->type = RTE_ETH_L4_PAYLOAD;
1242
1243                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1244                         flex_pit = &pf->fdir.flex_set[layer_idx *
1245                                 I40E_MAX_FLXPLD_FIED + i];
1246                         if (flex_pit->size == 0)
1247                                 continue;
1248                         src = flex_pit->src_offset * sizeof(uint16_t);
1249                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1250                         size = flex_pit->size * sizeof(uint16_t);
1251                         for (j = src, k = dst; j < src + size; j++, k++)
1252                                 ptr->src_offset[k] = j;
1253                 }
1254                 (*num)++;
1255                 ptr++;
1256         }
1257 }
1258
1259 static inline void
1260 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1261                         struct rte_eth_fdir_flex_mask *flex_mask,
1262                         uint16_t *num)
1263 {
1264         struct i40e_fdir_flex_mask *mask;
1265         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1266         uint16_t flow_type;
1267         uint8_t i, j;
1268         uint16_t off_bytes, mask_tmp;
1269
1270         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1271              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1272              i++) {
1273                 mask =  &pf->fdir.flex_mask[i];
1274                 if (!I40E_VALID_PCTYPE((enum i40e_filter_pctype)i))
1275                         continue;
1276                 flow_type = i40e_pctype_to_flowtype((enum i40e_filter_pctype)i);
1277                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1278                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1279                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1280                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1281                         } else {
1282                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1283                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1284                         }
1285                 }
1286                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1287                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1288                         mask_tmp = ~mask->bitmask[j].mask;
1289                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1290                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1291                 }
1292                 ptr->flow_type = flow_type;
1293                 ptr++;
1294                 (*num)++;
1295         }
1296 }
1297
1298 /*
1299  * i40e_fdir_info_get - get information of Flow Director
1300  * @pf: ethernet device to get info from
1301  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1302  *    the flow director information.
1303  */
1304 static void
1305 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
1306 {
1307         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1308         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1309         uint16_t num_flex_set = 0;
1310         uint16_t num_flex_mask = 0;
1311
1312         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
1313                 fdir->mode = RTE_FDIR_MODE_PERFECT;
1314         else
1315                 fdir->mode = RTE_FDIR_MODE_NONE;
1316
1317         fdir->guarant_spc =
1318                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
1319         fdir->best_spc =
1320                 (uint32_t)hw->func_caps.fd_filters_best_effort;
1321         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
1322         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
1323         fdir->flex_payload_unit = sizeof(uint16_t);
1324         fdir->flex_bitmask_unit = sizeof(uint16_t);
1325         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
1326         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
1327         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
1328
1329         i40e_fdir_info_get_flex_set(pf,
1330                                 fdir->flex_conf.flex_set,
1331                                 &num_flex_set);
1332         i40e_fdir_info_get_flex_mask(pf,
1333                                 fdir->flex_conf.flex_mask,
1334                                 &num_flex_mask);
1335
1336         fdir->flex_conf.nb_payloads = num_flex_set;
1337         fdir->flex_conf.nb_flexmasks = num_flex_mask;
1338 }
1339
1340 /*
1341  * i40e_fdir_stat_get - get statistics of Flow Director
1342  * @pf: ethernet device to get info from
1343  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
1344  *    the flow director statistics.
1345  */
1346 static void
1347 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
1348 {
1349         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1350         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1351         uint32_t fdstat;
1352
1353         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
1354         stat->guarant_cnt =
1355                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1356                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1357         stat->best_cnt =
1358                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1359                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1360 }
1361
1362 static int
1363 i40e_fdir_filter_set(struct rte_eth_dev *dev,
1364                      struct rte_eth_fdir_filter_info *info)
1365 {
1366         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1367         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1368         int ret = 0;
1369
1370         if (!info) {
1371                 PMD_DRV_LOG(ERR, "Invalid pointer");
1372                 return -EFAULT;
1373         }
1374
1375         switch (info->info_type) {
1376         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
1377                 ret = i40e_filter_inset_select(hw,
1378                         &(info->info.input_set_conf), RTE_ETH_FILTER_FDIR);
1379                 break;
1380         default:
1381                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
1382                             info->info_type);
1383                 return -EINVAL;
1384         }
1385
1386         return ret;
1387 }
1388
1389 /*
1390  * i40e_fdir_ctrl_func - deal with all operations on flow director.
1391  * @pf: board private structure
1392  * @filter_op:operation will be taken.
1393  * @arg: a pointer to specific structure corresponding to the filter_op
1394  */
1395 int
1396 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
1397                        enum rte_filter_op filter_op,
1398                        void *arg)
1399 {
1400         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1401         int ret = 0;
1402
1403         if ((pf->flags & I40E_FLAG_FDIR) == 0)
1404                 return -ENOTSUP;
1405
1406         if (filter_op == RTE_ETH_FILTER_NOP)
1407                 return 0;
1408
1409         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
1410                 return -EINVAL;
1411
1412         switch (filter_op) {
1413         case RTE_ETH_FILTER_ADD:
1414                 ret = i40e_add_del_fdir_filter(dev,
1415                         (struct rte_eth_fdir_filter *)arg,
1416                         TRUE);
1417                 break;
1418         case RTE_ETH_FILTER_DELETE:
1419                 ret = i40e_add_del_fdir_filter(dev,
1420                         (struct rte_eth_fdir_filter *)arg,
1421                         FALSE);
1422                 break;
1423         case RTE_ETH_FILTER_FLUSH:
1424                 ret = i40e_fdir_flush(dev);
1425                 break;
1426         case RTE_ETH_FILTER_INFO:
1427                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
1428                 break;
1429         case RTE_ETH_FILTER_SET:
1430                 ret = i40e_fdir_filter_set(dev,
1431                         (struct rte_eth_fdir_filter_info *)arg);
1432                 break;
1433         case RTE_ETH_FILTER_STATS:
1434                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
1435                 break;
1436         default:
1437                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
1438                 ret = -EINVAL;
1439                 break;
1440         }
1441         return ret;
1442 }