drivers/net/i40e/i40e_fdir.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2015 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_ether.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_log.h>
  16 #include <rte_memzone.h>
  17 #include <rte_malloc.h>
  18 #include <rte_arp.h>
  19 #include <rte_ip.h>
  20 #include <rte_udp.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_hash_crc.h>
  24
  25 #include "i40e_logs.h"
  26 #include "base/i40e_type.h"
  27 #include "base/i40e_prototype.h"
  28 #include "i40e_ethdev.h"
  29 #include "i40e_rxtx.h"
  30
  31 #define I40E_FDIR_MZ_NAME          "FDIR_MEMZONE"
  32 #ifndef IPV6_ADDR_LEN
  33 #define IPV6_ADDR_LEN              16
  34 #endif
  35
  36 #define I40E_FDIR_PKT_LEN                   512
  37 #define I40E_FDIR_IP_DEFAULT_LEN            420
  38 #define I40E_FDIR_IP_DEFAULT_TTL            0x40
  39 #define I40E_FDIR_IP_DEFAULT_VERSION_IHL    0x45
  40 #define I40E_FDIR_TCP_DEFAULT_DATAOFF       0x50
  41 #define I40E_FDIR_IPv6_DEFAULT_VTC_FLOW     0x60000000
  42
  43 #define I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS   0xFF
  44 #define I40E_FDIR_IPv6_PAYLOAD_LEN          380
  45 #define I40E_FDIR_UDP_DEFAULT_LEN           400
  46 #define I40E_FDIR_GTP_DEFAULT_LEN           384
  47 #define I40E_FDIR_INNER_IP_DEFAULT_LEN      384
  48 #define I40E_FDIR_INNER_IPV6_DEFAULT_LEN    344
  49
  50 #define I40E_FDIR_GTPC_DST_PORT             2123
  51 #define I40E_FDIR_GTPU_DST_PORT             2152
  52 #define I40E_FDIR_GTP_VER_FLAG_0X30         0x30
  53 #define I40E_FDIR_GTP_VER_FLAG_0X32         0x32
  54 #define I40E_FDIR_GTP_MSG_TYPE_0X01         0x01
  55 #define I40E_FDIR_GTP_MSG_TYPE_0XFF         0xFF
  56
  57 /* Wait time for fdir filter programming */
  58 #define I40E_FDIR_MAX_WAIT_US 10000
  59
  60 /* Wait count and interval for fdir filter flush */
  61 #define I40E_FDIR_FLUSH_RETRY       50
  62 #define I40E_FDIR_FLUSH_INTERVAL_MS 5
  63
  64 #define I40E_COUNTER_PF           2
  65 /* Statistic counter index for one pf */
  66 #define I40E_COUNTER_INDEX_FDIR(pf_id)   (0 + (pf_id) * I40E_COUNTER_PF)
  67
  68 #define I40E_FDIR_FLOWS ( \
  69         (1ULL << RTE_ETH_FLOW_FRAG_IPV4) | \
  70         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_UDP) | \
  71         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_TCP) | \
  72         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_SCTP) | \
  73         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV4_OTHER) | \
  74         (1ULL << RTE_ETH_FLOW_FRAG_IPV6) | \
  75         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_UDP) | \
  76         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_TCP) | \
  77         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_SCTP) | \
  78         (1ULL << RTE_ETH_FLOW_NONFRAG_IPV6_OTHER) | \
  79         (1ULL << RTE_ETH_FLOW_L2_PAYLOAD))
  80
  81 static int i40e_fdir_filter_programming(struct i40e_pf *pf,
  82                         enum i40e_filter_pctype pctype,
  83                         const struct rte_eth_fdir_filter *filter,
  84                         bool add);
  85 static int i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
  86                          struct i40e_fdir_filter *filter);
  87 static struct i40e_fdir_filter *
  88 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
  89                         const struct i40e_fdir_input *input);
  90 static int i40e_sw_fdir_filter_insert(struct i40e_pf *pf,
  91                                    struct i40e_fdir_filter *filter);
  92 static int
  93 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
  94                                   enum i40e_filter_pctype pctype,
  95                                   const struct i40e_fdir_filter_conf *filter,
  96                                   bool add);
  97
  98 static int
  99 i40e_fdir_rx_queue_init(struct i40e_rx_queue *rxq)
 100 {
 101         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
 102         struct i40e_hmc_obj_rxq rx_ctx;
 103         int err = I40E_SUCCESS;
 104
 105         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 106         /* Init the RX queue in hardware */
 107         rx_ctx.dbuff = I40E_RXBUF_SZ_1024 >> I40E_RXQ_CTX_DBUFF_SHIFT;
 108         rx_ctx.hbuff = 0;
 109         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 110         rx_ctx.qlen = rxq->nb_rx_desc;
 111 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 112         rx_ctx.dsize = 1;
 113 #endif
 114         rx_ctx.dtype = i40e_header_split_none;
 115         rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 116         rx_ctx.rxmax = ETHER_MAX_LEN;
 117         rx_ctx.tphrdesc_ena = 1;
 118         rx_ctx.tphwdesc_ena = 1;
 119         rx_ctx.tphdata_ena = 1;
 120         rx_ctx.tphhead_ena = 1;
 121         rx_ctx.lrxqthresh = 2;
 122         rx_ctx.crcstrip = 0;
 123         rx_ctx.l2tsel = 1;
 124         rx_ctx.showiv = 0;
 125         rx_ctx.prefena = 1;
 126
 127         err = i40e_clear_lan_rx_queue_context(hw, rxq->reg_idx);
 128         if (err != I40E_SUCCESS) {
 129                 PMD_DRV_LOG(ERR, "Failed to clear FDIR RX queue context.");
 130                 return err;
 131         }
 132         err = i40e_set_lan_rx_queue_context(hw, rxq->reg_idx, &rx_ctx);
 133         if (err != I40E_SUCCESS) {
 134                 PMD_DRV_LOG(ERR, "Failed to set FDIR RX queue context.");
 135                 return err;
 136         }
 137         rxq->qrx_tail = hw->hw_addr +
 138                 I40E_QRX_TAIL(rxq->vsi->base_queue);
 139
 140         rte_wmb();
 141         /* Init the RX tail regieter. */
 142         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 143
 144         return err;
 145 }
 146
 147 /*
 148  * i40e_fdir_setup - reserve and initialize the Flow Director resources
 149  * @pf: board private structure
 150  */
 151 int
 152 i40e_fdir_setup(struct i40e_pf *pf)
 153 {
 154         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 155         struct i40e_vsi *vsi;
 156         int err = I40E_SUCCESS;
 157         char z_name[RTE_MEMZONE_NAMESIZE];
 158         const struct rte_memzone *mz = NULL;
 159         struct rte_eth_dev *eth_dev = pf->adapter->eth_dev;
 160
 161         if ((pf->flags & I40E_FLAG_FDIR) == 0) {
 162                 PMD_INIT_LOG(ERR, "HW doesn't support FDIR");
 163                 return I40E_NOT_SUPPORTED;
 164         }
 165
 166         PMD_DRV_LOG(INFO, "FDIR HW Capabilities: num_filters_guaranteed = %u,"
 167                         " num_filters_best_effort = %u.",
 168                         hw->func_caps.fd_filters_guaranteed,
 169                         hw->func_caps.fd_filters_best_effort);
 170
 171         vsi = pf->fdir.fdir_vsi;
 172         if (vsi) {
 173                 PMD_DRV_LOG(INFO, "FDIR initialization has been done.");
 174                 return I40E_SUCCESS;
 175         }
 176         /* make new FDIR VSI */
 177         vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR, pf->main_vsi, 0);
 178         if (!vsi) {
 179                 PMD_DRV_LOG(ERR, "Couldn't create FDIR VSI.");
 180                 return I40E_ERR_NO_AVAILABLE_VSI;
 181         }
 182         pf->fdir.fdir_vsi = vsi;
 183
 184         /*Fdir tx queue setup*/
 185         err = i40e_fdir_setup_tx_resources(pf);
 186         if (err) {
 187                 PMD_DRV_LOG(ERR, "Failed to setup FDIR TX resources.");
 188                 goto fail_setup_tx;
 189         }
 190
 191         /*Fdir rx queue setup*/
 192         err = i40e_fdir_setup_rx_resources(pf);
 193         if (err) {
 194                 PMD_DRV_LOG(ERR, "Failed to setup FDIR RX resources.");
 195                 goto fail_setup_rx;
 196         }
 197
 198         err = i40e_tx_queue_init(pf->fdir.txq);
 199         if (err) {
 200                 PMD_DRV_LOG(ERR, "Failed to do FDIR TX initialization.");
 201                 goto fail_mem;
 202         }
 203
 204         /* need switch on before dev start*/
 205         err = i40e_switch_tx_queue(hw, vsi->base_queue, TRUE);
 206         if (err) {
 207                 PMD_DRV_LOG(ERR, "Failed to do fdir TX switch on.");
 208                 goto fail_mem;
 209         }
 210
 211         /* Init the rx queue in hardware */
 212         err = i40e_fdir_rx_queue_init(pf->fdir.rxq);
 213         if (err) {
 214                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX initialization.");
 215                 goto fail_mem;
 216         }
 217
 218         /* switch on rx queue */
 219         err = i40e_switch_rx_queue(hw, vsi->base_queue, TRUE);
 220         if (err) {
 221                 PMD_DRV_LOG(ERR, "Failed to do FDIR RX switch on.");
 222                 goto fail_mem;
 223         }
 224
 225         /* reserve memory for the fdir programming packet */
 226         snprintf(z_name, sizeof(z_name), "%s_%s_%d",
 227                         eth_dev->device->driver->name,
 228                         I40E_FDIR_MZ_NAME,
 229                         eth_dev->data->port_id);
 230         mz = i40e_memzone_reserve(z_name, I40E_FDIR_PKT_LEN, SOCKET_ID_ANY);
 231         if (!mz) {
 232                 PMD_DRV_LOG(ERR, "Cannot init memzone for "
 233                                  "flow director program packet.");
 234                 err = I40E_ERR_NO_MEMORY;
 235                 goto fail_mem;
 236         }
 237         pf->fdir.prg_pkt = mz->addr;
 238         pf->fdir.dma_addr = mz->iova;
 239
 240         pf->fdir.match_counter_index = I40E_COUNTER_INDEX_FDIR(hw->pf_id);
 241         PMD_DRV_LOG(INFO, "FDIR setup successfully, with programming queue %u.",
 242                     vsi->base_queue);
 243         return I40E_SUCCESS;
 244
 245 fail_mem:
 246         i40e_dev_rx_queue_release(pf->fdir.rxq);
 247         pf->fdir.rxq = NULL;
 248 fail_setup_rx:
 249         i40e_dev_tx_queue_release(pf->fdir.txq);
 250         pf->fdir.txq = NULL;
 251 fail_setup_tx:
 252         i40e_vsi_release(vsi);
 253         pf->fdir.fdir_vsi = NULL;
 254         return err;
 255 }
 256
 257 /*
 258  * i40e_fdir_teardown - release the Flow Director resources
 259  * @pf: board private structure
 260  */
 261 void
 262 i40e_fdir_teardown(struct i40e_pf *pf)
 263 {
 264         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 265         struct i40e_vsi *vsi;
 266
 267         vsi = pf->fdir.fdir_vsi;
 268         if (!vsi)
 269                 return;
 270         int err = i40e_switch_tx_queue(hw, vsi->base_queue, FALSE);
 271         if (err)
 272                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR TX switch off");
 273         err = i40e_switch_rx_queue(hw, vsi->base_queue, FALSE);
 274         if (err)
 275                 PMD_DRV_LOG(DEBUG, "Failed to do FDIR RX switch off");
 276         i40e_dev_rx_queue_release(pf->fdir.rxq);
 277         pf->fdir.rxq = NULL;
 278         i40e_dev_tx_queue_release(pf->fdir.txq);
 279         pf->fdir.txq = NULL;
 280         i40e_vsi_release(vsi);
 281         pf->fdir.fdir_vsi = NULL;
 282 }
 283
 284 /* check whether the flow director table in empty */
 285 static inline int
 286 i40e_fdir_empty(struct i40e_hw *hw)
 287 {
 288         uint32_t guarant_cnt, best_cnt;
 289
 290         guarant_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 291                                  I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
 292                                  I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
 293         best_cnt = (uint32_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
 294                               I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
 295                               I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
 296         if (best_cnt + guarant_cnt > 0)
 297                 return -1;
 298
 299         return 0;
 300 }
 301
 302 /*
 303  * Initialize the configuration about bytes stream extracted as flexible payload
 304  * and mask setting
 305  */
 306 static inline void
 307 i40e_init_flx_pld(struct i40e_pf *pf)
 308 {
 309         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 310         uint8_t pctype;
 311         int i, index;
 312         uint16_t flow_type;
 313
 314         /*
 315          * Define the bytes stream extracted as flexible payload in
 316          * field vector. By default, select 8 words from the beginning
 317          * of payload as flexible payload.
 318          */
 319         for (i = I40E_FLXPLD_L2_IDX; i < I40E_MAX_FLXPLD_LAYER; i++) {
 320                 index = i * I40E_MAX_FLXPLD_FIED;
 321                 pf->fdir.flex_set[index].src_offset = 0;
 322                 pf->fdir.flex_set[index].size = I40E_FDIR_MAX_FLEXWORD_NUM;
 323                 pf->fdir.flex_set[index].dst_offset = 0;
 324                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(index), 0x0000C900);
 325                 I40E_WRITE_REG(hw,
 326                         I40E_PRTQF_FLX_PIT(index + 1), 0x0000FC29);/*non-used*/
 327                 I40E_WRITE_REG(hw,
 328                         I40E_PRTQF_FLX_PIT(index + 2), 0x0000FC2A);/*non-used*/
 329         }
 330
 331         /* initialize the masks */
 332         for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
 333              pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++) {
 334                 flow_type = i40e_pctype_to_flowtype(pf->adapter, pctype);
 335
 336                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
 337                         continue;
 338                 pf->fdir.flex_mask[pctype].word_mask = 0;
 339                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), 0);
 340                 for (i = 0; i < I40E_FDIR_BITMASK_NUM_WORD; i++) {
 341                         pf->fdir.flex_mask[pctype].bitmask[i].offset = 0;
 342                         pf->fdir.flex_mask[pctype].bitmask[i].mask = 0;
 343                         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), 0);
 344                 }
 345         }
 346 }
 347
 348 #define I40E_VALIDATE_FLEX_PIT(flex_pit1, flex_pit2) do { \
 349         if ((flex_pit2).src_offset < \
 350                 (flex_pit1).src_offset + (flex_pit1).size) { \
 351                 PMD_DRV_LOG(ERR, "src_offset should be not" \
 352                         " less than than previous offset" \
 353                         " + previous FSIZE."); \
 354                 return -EINVAL; \
 355         } \
 356 } while (0)
 357
 358 /*
 359  * i40e_srcoff_to_flx_pit - transform the src_offset into flex_pit structure,
 360  * and the flex_pit will be sorted by it's src_offset value
 361  */
 362 static inline uint16_t
 363 i40e_srcoff_to_flx_pit(const uint16_t *src_offset,
 364                         struct i40e_fdir_flex_pit *flex_pit)
 365 {
 366         uint16_t src_tmp, size, num = 0;
 367         uint16_t i, k, j = 0;
 368
 369         while (j < I40E_FDIR_MAX_FLEX_LEN) {
 370                 size = 1;
 371                 for (; j < I40E_FDIR_MAX_FLEX_LEN - 1; j++) {
 372                         if (src_offset[j + 1] == src_offset[j] + 1)
 373                                 size++;
 374                         else
 375                                 break;
 376                 }
 377                 src_tmp = src_offset[j] + 1 - size;
 378                 /* the flex_pit need to be sort by src_offset */
 379                 for (i = 0; i < num; i++) {
 380                         if (src_tmp < flex_pit[i].src_offset)
 381                                 break;
 382                 }
 383                 /* if insert required, move backward */
 384                 for (k = num; k > i; k--)
 385                         flex_pit[k] = flex_pit[k - 1];
 386                 /* insert */
 387                 flex_pit[i].dst_offset = j + 1 - size;
 388                 flex_pit[i].src_offset = src_tmp;
 389                 flex_pit[i].size = size;
 390                 j++;
 391                 num++;
 392         }
 393         return num;
 394 }
 395
 396 /* i40e_check_fdir_flex_payload -check flex payload configuration arguments */
 397 static inline int
 398 i40e_check_fdir_flex_payload(const struct rte_eth_flex_payload_cfg *flex_cfg)
 399 {
 400         struct i40e_fdir_flex_pit flex_pit[I40E_FDIR_MAX_FLEX_LEN];
 401         uint16_t num, i;
 402
 403         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i++) {
 404                 if (flex_cfg->src_offset[i] >= I40E_MAX_FLX_SOURCE_OFF) {
 405                         PMD_DRV_LOG(ERR, "exceeds maxmial payload limit.");
 406                         return -EINVAL;
 407                 }
 408         }
 409
 410         memset(flex_pit, 0, sizeof(flex_pit));
 411         num = i40e_srcoff_to_flx_pit(flex_cfg->src_offset, flex_pit);
 412         if (num > I40E_MAX_FLXPLD_FIED) {
 413                 PMD_DRV_LOG(ERR, "exceeds maxmial number of flex fields.");
 414                 return -EINVAL;
 415         }
 416         for (i = 0; i < num; i++) {
 417                 if (flex_pit[i].size & 0x01 || flex_pit[i].dst_offset & 0x01 ||
 418                         flex_pit[i].src_offset & 0x01) {
 419                         PMD_DRV_LOG(ERR, "flexpayload should be measured"
 420                                 " in word");
 421                         return -EINVAL;
 422                 }
 423                 if (i != num - 1)
 424                         I40E_VALIDATE_FLEX_PIT(flex_pit[i], flex_pit[i + 1]);
 425         }
 426         return 0;
 427 }
 428
 429 /*
 430  * i40e_check_fdir_flex_conf -check if the flex payload and mask configuration
 431  * arguments are valid
 432  */
 433 static int
 434 i40e_check_fdir_flex_conf(const struct i40e_adapter *adapter,
 435                           const struct rte_eth_fdir_flex_conf *conf)
 436 {
 437         const struct rte_eth_flex_payload_cfg *flex_cfg;
 438         const struct rte_eth_fdir_flex_mask *flex_mask;
 439         uint16_t mask_tmp;
 440         uint8_t nb_bitmask;
 441         uint16_t i, j;
 442         int ret = 0;
 443         enum i40e_filter_pctype pctype;
 444
 445         if (conf == NULL) {
 446                 PMD_DRV_LOG(INFO, "NULL pointer.");
 447                 return -EINVAL;
 448         }
 449         /* check flexible payload setting configuration */
 450         if (conf->nb_payloads > RTE_ETH_L4_PAYLOAD) {
 451                 PMD_DRV_LOG(ERR, "invalid number of payload setting.");
 452                 return -EINVAL;
 453         }
 454         for (i = 0; i < conf->nb_payloads; i++) {
 455                 flex_cfg = &conf->flex_set[i];
 456                 if (flex_cfg->type > RTE_ETH_L4_PAYLOAD) {
 457                         PMD_DRV_LOG(ERR, "invalid payload type.");
 458                         return -EINVAL;
 459                 }
 460                 ret = i40e_check_fdir_flex_payload(flex_cfg);
 461                 if (ret < 0) {
 462                         PMD_DRV_LOG(ERR, "invalid flex payload arguments.");
 463                         return -EINVAL;
 464                 }
 465         }
 466
 467         /* check flex mask setting configuration */
 468         if (conf->nb_flexmasks >= RTE_ETH_FLOW_MAX) {
 469                 PMD_DRV_LOG(ERR, "invalid number of flex masks.");
 470                 return -EINVAL;
 471         }
 472         for (i = 0; i < conf->nb_flexmasks; i++) {
 473                 flex_mask = &conf->flex_mask[i];
 474                 pctype = i40e_flowtype_to_pctype(adapter, flex_mask->flow_type);
 475                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
 476                         PMD_DRV_LOG(WARNING, "invalid flow type.");
 477                         return -EINVAL;
 478                 }
 479                 nb_bitmask = 0;
 480                 for (j = 0; j < I40E_FDIR_MAX_FLEX_LEN; j += sizeof(uint16_t)) {
 481                         mask_tmp = I40E_WORD(flex_mask->mask[j],
 482                                              flex_mask->mask[j + 1]);
 483                         if (mask_tmp != 0x0 && mask_tmp != UINT16_MAX) {
 484                                 nb_bitmask++;
 485                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD) {
 486                                         PMD_DRV_LOG(ERR, " exceed maximal"
 487                                                 " number of bitmasks.");
 488                                         return -EINVAL;
 489                                 }
 490                         }
 491                 }
 492         }
 493         return 0;
 494 }
 495
 496 /*
 497  * i40e_set_flx_pld_cfg -configure the rule how bytes stream is extracted as flexible payload
 498  * @pf: board private structure
 499  * @cfg: the rule how bytes stream is extracted as flexible payload
 500  */
 501 static void
 502 i40e_set_flx_pld_cfg(struct i40e_pf *pf,
 503                          const struct rte_eth_flex_payload_cfg *cfg)
 504 {
 505         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 506         struct i40e_fdir_flex_pit flex_pit[I40E_MAX_FLXPLD_FIED];
 507         uint32_t flx_pit, flx_ort;
 508         uint16_t num, min_next_off;  /* in words */
 509         uint8_t field_idx = 0;
 510         uint8_t layer_idx = 0;
 511         uint16_t i;
 512
 513         if (cfg->type == RTE_ETH_L2_PAYLOAD)
 514                 layer_idx = I40E_FLXPLD_L2_IDX;
 515         else if (cfg->type == RTE_ETH_L3_PAYLOAD)
 516                 layer_idx = I40E_FLXPLD_L3_IDX;
 517         else if (cfg->type == RTE_ETH_L4_PAYLOAD)
 518                 layer_idx = I40E_FLXPLD_L4_IDX;
 519
 520         memset(flex_pit, 0, sizeof(flex_pit));
 521         num = RTE_MIN(i40e_srcoff_to_flx_pit(cfg->src_offset, flex_pit),
 522                       RTE_DIM(flex_pit));
 523
 524         if (num) {
 525                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
 526                           (num << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
 527                           (layer_idx * I40E_MAX_FLXPLD_FIED);
 528                 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
 529         }
 530
 531         for (i = 0; i < num; i++) {
 532                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
 533                 /* record the info in fdir structure */
 534                 pf->fdir.flex_set[field_idx].src_offset =
 535                         flex_pit[i].src_offset / sizeof(uint16_t);
 536                 pf->fdir.flex_set[field_idx].size =
 537                         flex_pit[i].size / sizeof(uint16_t);
 538                 pf->fdir.flex_set[field_idx].dst_offset =
 539                         flex_pit[i].dst_offset / sizeof(uint16_t);
 540                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
 541                                 pf->fdir.flex_set[field_idx].size,
 542                                 pf->fdir.flex_set[field_idx].dst_offset);
 543
 544                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
 545         }
 546         min_next_off = pf->fdir.flex_set[field_idx].src_offset +
 547                                 pf->fdir.flex_set[field_idx].size;
 548
 549         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
 550                 /* set the non-used register obeying register's constrain */
 551                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
 552                            NONUSE_FLX_PIT_DEST_OFF);
 553                 I40E_WRITE_REG(hw,
 554                         I40E_PRTQF_FLX_PIT(layer_idx * I40E_MAX_FLXPLD_FIED + i),
 555                         flx_pit);
 556                 min_next_off++;
 557         }
 558 }
 559
 560 /*
 561  * i40e_set_flex_mask_on_pctype - configure the mask on flexible payload
 562  * @pf: board private structure
 563  * @pctype: packet classify type
 564  * @flex_masks: mask for flexible payload
 565  */
 566 static void
 567 i40e_set_flex_mask_on_pctype(struct i40e_pf *pf,
 568                 enum i40e_filter_pctype pctype,
 569                 const struct rte_eth_fdir_flex_mask *mask_cfg)
 570 {
 571         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
 572         struct i40e_fdir_flex_mask *flex_mask;
 573         uint32_t flxinset, fd_mask;
 574         uint16_t mask_tmp;
 575         uint8_t i, nb_bitmask = 0;
 576
 577         flex_mask = &pf->fdir.flex_mask[pctype];
 578         memset(flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
 579         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
 580                 mask_tmp = I40E_WORD(mask_cfg->mask[i], mask_cfg->mask[i + 1]);
 581                 if (mask_tmp != 0x0) {
 582                         flex_mask->word_mask |=
 583                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
 584                         if (mask_tmp != UINT16_MAX) {
 585                                 /* set bit mask */
 586                                 flex_mask->bitmask[nb_bitmask].mask = ~mask_tmp;
 587                                 flex_mask->bitmask[nb_bitmask].offset =
 588                                         i / sizeof(uint16_t);
 589                                 nb_bitmask++;
 590                         }
 591                 }
 592         }
 593         /* write mask to hw */
 594         flxinset = (flex_mask->word_mask <<
 595                 I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
 596                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
 597         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
 598
 599         for (i = 0; i < nb_bitmask; i++) {
 600                 fd_mask = (flex_mask->bitmask[i].mask <<
 601                         I40E_PRTQF_FD_MSK_MASK_SHIFT) &
 602                         I40E_PRTQF_FD_MSK_MASK_MASK;
 603                 fd_mask |= ((flex_mask->bitmask[i].offset +
 604                         I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
 605                         I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
 606                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
 607                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
 608         }
 609 }
 610
 611 /*
 612  * Configure flow director related setting
 613  */
 614 int
 615 i40e_fdir_configure(struct rte_eth_dev *dev)
 616 {
 617         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 618         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 619         struct rte_eth_fdir_flex_conf *conf;
 620         enum i40e_filter_pctype pctype;
 621         uint32_t val;
 622         uint8_t i;
 623         int ret = 0;
 624
 625         /*
 626         * configuration need to be done before
 627         * flow director filters are added
 628         * If filters exist, flush them.
 629         */
 630         if (i40e_fdir_empty(hw) < 0) {
 631                 ret = i40e_fdir_flush(dev);
 632                 if (ret) {
 633                         PMD_DRV_LOG(ERR, "failed to flush fdir table.");
 634                         return ret;
 635                 }
 636         }
 637
 638         /* enable FDIR filter */
 639         val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
 640         val |= I40E_PFQF_CTL_0_FD_ENA_MASK;
 641         i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, val);
 642
 643         i40e_init_flx_pld(pf); /* set flex config to default value */
 644
 645         conf = &dev->data->dev_conf.fdir_conf.flex_conf;
 646         ret = i40e_check_fdir_flex_conf(pf->adapter, conf);
 647         if (ret < 0) {
 648                 PMD_DRV_LOG(ERR, " invalid configuration arguments.");
 649                 return -EINVAL;
 650         }
 651         /* configure flex payload */
 652         for (i = 0; i < conf->nb_payloads; i++)
 653                 i40e_set_flx_pld_cfg(pf, &conf->flex_set[i]);
 654         /* configure flex mask*/
 655         for (i = 0; i < conf->nb_flexmasks; i++) {
 656                 if (hw->mac.type == I40E_MAC_X722) {
 657                         /* get translated pctype value in fd pctype register */
 658                         pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
 659                                 hw, I40E_GLQF_FD_PCTYPES(
 660                                 (int)i40e_flowtype_to_pctype(pf->adapter,
 661                                 conf->flex_mask[i].flow_type)));
 662                 } else
 663                         pctype = i40e_flowtype_to_pctype(pf->adapter,
 664                                                 conf->flex_mask[i].flow_type);
 665
 666                 i40e_set_flex_mask_on_pctype(pf, pctype, &conf->flex_mask[i]);
 667         }
 668
 669         return ret;
 670 }
 671
 672 static inline int
 673 i40e_fdir_fill_eth_ip_head(const struct rte_eth_fdir_input *fdir_input,
 674                            unsigned char *raw_pkt,
 675                            bool vlan)
 676 {
 677         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 678         uint16_t *ether_type;
 679         uint8_t len = 2 * sizeof(struct ether_addr);
 680         struct ipv4_hdr *ip;
 681         struct ipv6_hdr *ip6;
 682         static const uint8_t next_proto[] = {
 683                 [RTE_ETH_FLOW_FRAG_IPV4] = IPPROTO_IP,
 684                 [RTE_ETH_FLOW_NONFRAG_IPV4_TCP] = IPPROTO_TCP,
 685                 [RTE_ETH_FLOW_NONFRAG_IPV4_UDP] = IPPROTO_UDP,
 686                 [RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] = IPPROTO_SCTP,
 687                 [RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] = IPPROTO_IP,
 688                 [RTE_ETH_FLOW_FRAG_IPV6] = IPPROTO_NONE,
 689                 [RTE_ETH_FLOW_NONFRAG_IPV6_TCP] = IPPROTO_TCP,
 690                 [RTE_ETH_FLOW_NONFRAG_IPV6_UDP] = IPPROTO_UDP,
 691                 [RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] = IPPROTO_SCTP,
 692                 [RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] = IPPROTO_NONE,
 693         };
 694
 695         raw_pkt += 2 * sizeof(struct ether_addr);
 696         if (vlan && fdir_input->flow_ext.vlan_tci) {
 697                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 698                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 699                            &fdir_input->flow_ext.vlan_tci,
 700                            sizeof(uint16_t));
 701                 raw_pkt += sizeof(vlan_frame);
 702                 len += sizeof(vlan_frame);
 703         }
 704         ether_type = (uint16_t *)raw_pkt;
 705         raw_pkt += sizeof(uint16_t);
 706         len += sizeof(uint16_t);
 707
 708         switch (fdir_input->flow_type) {
 709         case RTE_ETH_FLOW_L2_PAYLOAD:
 710                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 711                 break;
 712         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 713         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 714         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 715         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 716         case RTE_ETH_FLOW_FRAG_IPV4:
 717                 ip = (struct ipv4_hdr *)raw_pkt;
 718
 719                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
 720                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
 721                 /* set len to by default */
 722                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
 723                 ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
 724                                         fdir_input->flow.ip4_flow.proto :
 725                                         next_proto[fdir_input->flow_type];
 726                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
 727                                         fdir_input->flow.ip4_flow.ttl :
 728                                         I40E_FDIR_IP_DEFAULT_TTL;
 729                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
 730                 /*
 731                  * The source and destination fields in the transmitted packet
 732                  * need to be presented in a reversed order with respect
 733                  * to the expected received packets.
 734                  */
 735                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
 736                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
 737                 len += sizeof(struct ipv4_hdr);
 738                 break;
 739         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 740         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 741         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 742         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 743         case RTE_ETH_FLOW_FRAG_IPV6:
 744                 ip6 = (struct ipv6_hdr *)raw_pkt;
 745
 746                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
 747                 ip6->vtc_flow =
 748                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
 749                                          (fdir_input->flow.ipv6_flow.tc <<
 750                                           I40E_FDIR_IPv6_TC_OFFSET));
 751                 ip6->payload_len =
 752                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 753                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
 754                                         fdir_input->flow.ipv6_flow.proto :
 755                                         next_proto[fdir_input->flow_type];
 756                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
 757                                         fdir_input->flow.ipv6_flow.hop_limits :
 758                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
 759                 /*
 760                  * The source and destination fields in the transmitted packet
 761                  * need to be presented in a reversed order with respect
 762                  * to the expected received packets.
 763                  */
 764                 rte_memcpy(&(ip6->src_addr),
 765                            &(fdir_input->flow.ipv6_flow.dst_ip),
 766                            IPV6_ADDR_LEN);
 767                 rte_memcpy(&(ip6->dst_addr),
 768                            &(fdir_input->flow.ipv6_flow.src_ip),
 769                            IPV6_ADDR_LEN);
 770                 len += sizeof(struct ipv6_hdr);
 771                 break;
 772         default:
 773                 PMD_DRV_LOG(ERR, "unknown flow type %u.",
 774                             fdir_input->flow_type);
 775                 return -1;
 776         }
 777         return len;
 778 }
 779
 780
 781 /*
 782  * i40e_fdir_construct_pkt - construct packet based on fields in input
 783  * @pf: board private structure
 784  * @fdir_input: input set of the flow director entry
 785  * @raw_pkt: a packet to be constructed
 786  */
 787 static int
 788 i40e_fdir_construct_pkt(struct i40e_pf *pf,
 789                              const struct rte_eth_fdir_input *fdir_input,
 790                              unsigned char *raw_pkt)
 791 {
 792         unsigned char *payload, *ptr;
 793         struct udp_hdr *udp;
 794         struct tcp_hdr *tcp;
 795         struct sctp_hdr *sctp;
 796         uint8_t size, dst = 0;
 797         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
 798         int len;
 799
 800         /* fill the ethernet and IP head */
 801         len = i40e_fdir_fill_eth_ip_head(fdir_input, raw_pkt,
 802                                          !!fdir_input->flow_ext.vlan_tci);
 803         if (len < 0)
 804                 return -EINVAL;
 805
 806         /* fill the L4 head */
 807         switch (fdir_input->flow_type) {
 808         case RTE_ETH_FLOW_NONFRAG_IPV4_UDP:
 809                 udp = (struct udp_hdr *)(raw_pkt + len);
 810                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 811                 /*
 812                  * The source and destination fields in the transmitted packet
 813                  * need to be presented in a reversed order with respect
 814                  * to the expected received packets.
 815                  */
 816                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
 817                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
 818                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
 819                 break;
 820
 821         case RTE_ETH_FLOW_NONFRAG_IPV4_TCP:
 822                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 823                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 824                 /*
 825                  * The source and destination fields in the transmitted packet
 826                  * need to be presented in a reversed order with respect
 827                  * to the expected received packets.
 828                  */
 829                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
 830                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
 831                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 832                 break;
 833
 834         case RTE_ETH_FLOW_NONFRAG_IPV4_SCTP:
 835                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 836                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 837                 /*
 838                  * The source and destination fields in the transmitted packet
 839                  * need to be presented in a reversed order with respect
 840                  * to the expected received packets.
 841                  */
 842                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
 843                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
 844                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
 845                 break;
 846
 847         case RTE_ETH_FLOW_NONFRAG_IPV4_OTHER:
 848         case RTE_ETH_FLOW_FRAG_IPV4:
 849                 payload = raw_pkt + len;
 850                 set_idx = I40E_FLXPLD_L3_IDX;
 851                 break;
 852
 853         case RTE_ETH_FLOW_NONFRAG_IPV6_UDP:
 854                 udp = (struct udp_hdr *)(raw_pkt + len);
 855                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
 856                 /*
 857                  * The source and destination fields in the transmitted packet
 858                  * need to be presented in a reversed order with respect
 859                  * to the expected received packets.
 860                  */
 861                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
 862                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
 863                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
 864                 break;
 865
 866         case RTE_ETH_FLOW_NONFRAG_IPV6_TCP:
 867                 tcp = (struct tcp_hdr *)(raw_pkt + len);
 868                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
 869                 /*
 870                  * The source and destination fields in the transmitted packet
 871                  * need to be presented in a reversed order with respect
 872                  * to the expected received packets.
 873                  */
 874                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
 875                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
 876                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
 877                 break;
 878
 879         case RTE_ETH_FLOW_NONFRAG_IPV6_SCTP:
 880                 sctp = (struct sctp_hdr *)(raw_pkt + len);
 881                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
 882                 /*
 883                  * The source and destination fields in the transmitted packet
 884                  * need to be presented in a reversed order with respect
 885                  * to the expected received packets.
 886                  */
 887                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
 888                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
 889                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
 890                 break;
 891
 892         case RTE_ETH_FLOW_NONFRAG_IPV6_OTHER:
 893         case RTE_ETH_FLOW_FRAG_IPV6:
 894                 payload = raw_pkt + len;
 895                 set_idx = I40E_FLXPLD_L3_IDX;
 896                 break;
 897         case RTE_ETH_FLOW_L2_PAYLOAD:
 898                 payload = raw_pkt + len;
 899                 /*
 900                  * ARP packet is a special case on which the payload
 901                  * starts after the whole ARP header
 902                  */
 903                 if (fdir_input->flow.l2_flow.ether_type ==
 904                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
 905                         payload += sizeof(struct arp_hdr);
 906                 set_idx = I40E_FLXPLD_L2_IDX;
 907                 break;
 908         default:
 909                 PMD_DRV_LOG(ERR, "unknown flow type %u.", fdir_input->flow_type);
 910                 return -EINVAL;
 911         }
 912
 913         /* fill the flexbytes to payload */
 914         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
 915                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
 916                 size = pf->fdir.flex_set[pit_idx].size;
 917                 if (size == 0)
 918                         continue;
 919                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
 920                 ptr = payload +
 921                         pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
 922                 rte_memcpy(ptr,
 923                                  &fdir_input->flow_ext.flexbytes[dst],
 924                                  size * sizeof(uint16_t));
 925         }
 926
 927         return 0;
 928 }
 929
 930 static struct i40e_customized_pctype *
 931 i40e_flow_fdir_find_customized_pctype(struct i40e_pf *pf, uint8_t pctype)
 932 {
 933         struct i40e_customized_pctype *cus_pctype;
 934         enum i40e_new_pctype i = I40E_CUSTOMIZED_GTPC;
 935
 936         for (; i < I40E_CUSTOMIZED_MAX; i++) {
 937                 cus_pctype = &pf->customized_pctype[i];
 938                 if (pctype == cus_pctype->pctype)
 939                         return cus_pctype;
 940         }
 941         return NULL;
 942 }
 943
 944 static inline int
 945 i40e_flow_fdir_fill_eth_ip_head(struct i40e_pf *pf,
 946                                 const struct i40e_fdir_input *fdir_input,
 947                                 unsigned char *raw_pkt,
 948                                 bool vlan)
 949 {
 950         struct i40e_customized_pctype *cus_pctype = NULL;
 951         static uint8_t vlan_frame[] = {0x81, 0, 0, 0};
 952         uint16_t *ether_type;
 953         uint8_t len = 2 * sizeof(struct ether_addr);
 954         struct ipv4_hdr *ip;
 955         struct ipv6_hdr *ip6;
 956         uint8_t pctype = fdir_input->pctype;
 957         bool is_customized_pctype = fdir_input->flow_ext.customized_pctype;
 958         static const uint8_t next_proto[] = {
 959                 [I40E_FILTER_PCTYPE_FRAG_IPV4] = IPPROTO_IP,
 960                 [I40E_FILTER_PCTYPE_NONF_IPV4_TCP] = IPPROTO_TCP,
 961                 [I40E_FILTER_PCTYPE_NONF_IPV4_UDP] = IPPROTO_UDP,
 962                 [I40E_FILTER_PCTYPE_NONF_IPV4_SCTP] = IPPROTO_SCTP,
 963                 [I40E_FILTER_PCTYPE_NONF_IPV4_OTHER] = IPPROTO_IP,
 964                 [I40E_FILTER_PCTYPE_FRAG_IPV6] = IPPROTO_NONE,
 965                 [I40E_FILTER_PCTYPE_NONF_IPV6_TCP] = IPPROTO_TCP,
 966                 [I40E_FILTER_PCTYPE_NONF_IPV6_UDP] = IPPROTO_UDP,
 967                 [I40E_FILTER_PCTYPE_NONF_IPV6_SCTP] = IPPROTO_SCTP,
 968                 [I40E_FILTER_PCTYPE_NONF_IPV6_OTHER] = IPPROTO_NONE,
 969         };
 970
 971         raw_pkt += 2 * sizeof(struct ether_addr);
 972         if (vlan && fdir_input->flow_ext.vlan_tci) {
 973                 rte_memcpy(raw_pkt, vlan_frame, sizeof(vlan_frame));
 974                 rte_memcpy(raw_pkt + sizeof(uint16_t),
 975                            &fdir_input->flow_ext.vlan_tci,
 976                            sizeof(uint16_t));
 977                 raw_pkt += sizeof(vlan_frame);
 978                 len += sizeof(vlan_frame);
 979         }
 980         ether_type = (uint16_t *)raw_pkt;
 981         raw_pkt += sizeof(uint16_t);
 982         len += sizeof(uint16_t);
 983
 984         if (is_customized_pctype) {
 985                 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
 986                 if (!cus_pctype) {
 987                         PMD_DRV_LOG(ERR, "unknown pctype %u.",
 988                                     fdir_input->pctype);
 989                         return -1;
 990                 }
 991         }
 992
 993         if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD)
 994                 *ether_type = fdir_input->flow.l2_flow.ether_type;
 995         else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP ||
 996                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP ||
 997                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP ||
 998                  pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
 999                  pctype == I40E_FILTER_PCTYPE_FRAG_IPV4 ||
1000                  is_customized_pctype) {
1001                 ip = (struct ipv4_hdr *)raw_pkt;
1002
1003                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv4);
1004                 ip->version_ihl = I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1005                 /* set len to by default */
1006                 ip->total_length = rte_cpu_to_be_16(I40E_FDIR_IP_DEFAULT_LEN);
1007                 ip->time_to_live = fdir_input->flow.ip4_flow.ttl ?
1008                         fdir_input->flow.ip4_flow.ttl :
1009                         I40E_FDIR_IP_DEFAULT_TTL;
1010                 ip->type_of_service = fdir_input->flow.ip4_flow.tos;
1011                 /**
1012                  * The source and destination fields in the transmitted packet
1013                  * need to be presented in a reversed order with respect
1014                  * to the expected received packets.
1015                  */
1016                 ip->src_addr = fdir_input->flow.ip4_flow.dst_ip;
1017                 ip->dst_addr = fdir_input->flow.ip4_flow.src_ip;
1018
1019                 if (!is_customized_pctype)
1020                         ip->next_proto_id = fdir_input->flow.ip4_flow.proto ?
1021                                 fdir_input->flow.ip4_flow.proto :
1022                                 next_proto[fdir_input->pctype];
1023                 else if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1024                          cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1025                          cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1026                          cus_pctype->index == I40E_CUSTOMIZED_GTPU)
1027                         ip->next_proto_id = IPPROTO_UDP;
1028                 len += sizeof(struct ipv4_hdr);
1029         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP ||
1030                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP ||
1031                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP ||
1032                    pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1033                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1034                 ip6 = (struct ipv6_hdr *)raw_pkt;
1035
1036                 *ether_type = rte_cpu_to_be_16(ETHER_TYPE_IPv6);
1037                 ip6->vtc_flow =
1038                         rte_cpu_to_be_32(I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1039                                          (fdir_input->flow.ipv6_flow.tc <<
1040                                           I40E_FDIR_IPv6_TC_OFFSET));
1041                 ip6->payload_len =
1042                         rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1043                 ip6->proto = fdir_input->flow.ipv6_flow.proto ?
1044                         fdir_input->flow.ipv6_flow.proto :
1045                         next_proto[fdir_input->pctype];
1046                 ip6->hop_limits = fdir_input->flow.ipv6_flow.hop_limits ?
1047                         fdir_input->flow.ipv6_flow.hop_limits :
1048                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1049                 /**
1050                  * The source and destination fields in the transmitted packet
1051                  * need to be presented in a reversed order with respect
1052                  * to the expected received packets.
1053                  */
1054                 rte_memcpy(&ip6->src_addr,
1055                            &fdir_input->flow.ipv6_flow.dst_ip,
1056                            IPV6_ADDR_LEN);
1057                 rte_memcpy(&ip6->dst_addr,
1058                            &fdir_input->flow.ipv6_flow.src_ip,
1059                            IPV6_ADDR_LEN);
1060                 len += sizeof(struct ipv6_hdr);
1061         } else {
1062                 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1063                             fdir_input->pctype);
1064                 return -1;
1065         }
1066
1067         return len;
1068 }
1069
1070 /**
1071  * i40e_flow_fdir_construct_pkt - construct packet based on fields in input
1072  * @pf: board private structure
1073  * @fdir_input: input set of the flow director entry
1074  * @raw_pkt: a packet to be constructed
1075  */
1076 static int
1077 i40e_flow_fdir_construct_pkt(struct i40e_pf *pf,
1078                              const struct i40e_fdir_input *fdir_input,
1079                              unsigned char *raw_pkt)
1080 {
1081         unsigned char *payload = NULL;
1082         unsigned char *ptr;
1083         struct udp_hdr *udp;
1084         struct tcp_hdr *tcp;
1085         struct sctp_hdr *sctp;
1086         struct rte_flow_item_gtp *gtp;
1087         struct ipv4_hdr *gtp_ipv4;
1088         struct ipv6_hdr *gtp_ipv6;
1089         uint8_t size, dst = 0;
1090         uint8_t i, pit_idx, set_idx = I40E_FLXPLD_L4_IDX; /* use l4 by default*/
1091         int len;
1092         uint8_t pctype = fdir_input->pctype;
1093         struct i40e_customized_pctype *cus_pctype;
1094
1095         /* raw pcket template - just copy contents of the raw packet */
1096         if (fdir_input->flow_ext.pkt_template) {
1097                 memcpy(raw_pkt, fdir_input->flow.raw_flow.packet,
1098                        fdir_input->flow.raw_flow.length);
1099                 return 0;
1100         }
1101
1102         /* fill the ethernet and IP head */
1103         len = i40e_flow_fdir_fill_eth_ip_head(pf, fdir_input, raw_pkt,
1104                                               !!fdir_input->flow_ext.vlan_tci);
1105         if (len < 0)
1106                 return -EINVAL;
1107
1108         /* fill the L4 head */
1109         if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_UDP) {
1110                 udp = (struct udp_hdr *)(raw_pkt + len);
1111                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1112                 /**
1113                  * The source and destination fields in the transmitted packet
1114                  * need to be presented in a reversed order with respect
1115                  * to the expected received packets.
1116                  */
1117                 udp->src_port = fdir_input->flow.udp4_flow.dst_port;
1118                 udp->dst_port = fdir_input->flow.udp4_flow.src_port;
1119                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1120         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_TCP) {
1121                 tcp = (struct tcp_hdr *)(raw_pkt + len);
1122                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1123                 /**
1124                  * The source and destination fields in the transmitted packet
1125                  * need to be presented in a reversed order with respect
1126                  * to the expected received packets.
1127                  */
1128                 tcp->src_port = fdir_input->flow.tcp4_flow.dst_port;
1129                 tcp->dst_port = fdir_input->flow.tcp4_flow.src_port;
1130                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1131         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) {
1132                 sctp = (struct sctp_hdr *)(raw_pkt + len);
1133                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1134                 /**
1135                  * The source and destination fields in the transmitted packet
1136                  * need to be presented in a reversed order with respect
1137                  * to the expected received packets.
1138                  */
1139                 sctp->src_port = fdir_input->flow.sctp4_flow.dst_port;
1140                 sctp->dst_port = fdir_input->flow.sctp4_flow.src_port;
1141                 sctp->tag = fdir_input->flow.sctp4_flow.verify_tag;
1142         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV4_OTHER ||
1143                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV4) {
1144                 payload = raw_pkt + len;
1145                 set_idx = I40E_FLXPLD_L3_IDX;
1146         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_UDP) {
1147                 udp = (struct udp_hdr *)(raw_pkt + len);
1148                 payload = (unsigned char *)udp + sizeof(struct udp_hdr);
1149                 /**
1150                  * The source and destination fields in the transmitted packet
1151                  * need to be presented in a reversed order with respect
1152                  * to the expected received packets.
1153                  */
1154                 udp->src_port = fdir_input->flow.udp6_flow.dst_port;
1155                 udp->dst_port = fdir_input->flow.udp6_flow.src_port;
1156                 udp->dgram_len = rte_cpu_to_be_16(I40E_FDIR_IPv6_PAYLOAD_LEN);
1157         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_TCP) {
1158                 tcp = (struct tcp_hdr *)(raw_pkt + len);
1159                 payload = (unsigned char *)tcp + sizeof(struct tcp_hdr);
1160                 /**
1161                  * The source and destination fields in the transmitted packet
1162                  * need to be presented in a reversed order with respect
1163                  * to the expected received packets.
1164                  */
1165                 tcp->data_off = I40E_FDIR_TCP_DEFAULT_DATAOFF;
1166                 tcp->src_port = fdir_input->flow.udp6_flow.dst_port;
1167                 tcp->dst_port = fdir_input->flow.udp6_flow.src_port;
1168         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) {
1169                 sctp = (struct sctp_hdr *)(raw_pkt + len);
1170                 payload = (unsigned char *)sctp + sizeof(struct sctp_hdr);
1171                 /**
1172                  * The source and destination fields in the transmitted packet
1173                  * need to be presented in a reversed order with respect
1174                  * to the expected received packets.
1175                  */
1176                 sctp->src_port = fdir_input->flow.sctp6_flow.dst_port;
1177                 sctp->dst_port = fdir_input->flow.sctp6_flow.src_port;
1178                 sctp->tag = fdir_input->flow.sctp6_flow.verify_tag;
1179         } else if (pctype == I40E_FILTER_PCTYPE_NONF_IPV6_OTHER ||
1180                    pctype == I40E_FILTER_PCTYPE_FRAG_IPV6) {
1181                 payload = raw_pkt + len;
1182                 set_idx = I40E_FLXPLD_L3_IDX;
1183         } else if (pctype == I40E_FILTER_PCTYPE_L2_PAYLOAD) {
1184                 payload = raw_pkt + len;
1185                 /**
1186                  * ARP packet is a special case on which the payload
1187                  * starts after the whole ARP header
1188                  */
1189                 if (fdir_input->flow.l2_flow.ether_type ==
1190                                 rte_cpu_to_be_16(ETHER_TYPE_ARP))
1191                         payload += sizeof(struct arp_hdr);
1192                 set_idx = I40E_FLXPLD_L2_IDX;
1193         } else if (fdir_input->flow_ext.customized_pctype) {
1194                 /* If customized pctype is used */
1195                 cus_pctype = i40e_flow_fdir_find_customized_pctype(pf, pctype);
1196                 if (cus_pctype->index == I40E_CUSTOMIZED_GTPC ||
1197                     cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4 ||
1198                     cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV6 ||
1199                     cus_pctype->index == I40E_CUSTOMIZED_GTPU) {
1200                         udp = (struct udp_hdr *)(raw_pkt + len);
1201                         udp->dgram_len =
1202                                 rte_cpu_to_be_16(I40E_FDIR_UDP_DEFAULT_LEN);
1203
1204                         gtp = (struct rte_flow_item_gtp *)
1205                                 ((unsigned char *)udp + sizeof(struct udp_hdr));
1206                         gtp->msg_len =
1207                                 rte_cpu_to_be_16(I40E_FDIR_GTP_DEFAULT_LEN);
1208                         gtp->teid = fdir_input->flow.gtp_flow.teid;
1209                         gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0X01;
1210
1211                         /* GTP-C message type is not supported. */
1212                         if (cus_pctype->index == I40E_CUSTOMIZED_GTPC) {
1213                                 udp->dst_port =
1214                                       rte_cpu_to_be_16(I40E_FDIR_GTPC_DST_PORT);
1215                                 gtp->v_pt_rsv_flags =
1216                                         I40E_FDIR_GTP_VER_FLAG_0X32;
1217                         } else {
1218                                 udp->dst_port =
1219                                       rte_cpu_to_be_16(I40E_FDIR_GTPU_DST_PORT);
1220                                 gtp->v_pt_rsv_flags =
1221                                         I40E_FDIR_GTP_VER_FLAG_0X30;
1222                         }
1223
1224                         if (cus_pctype->index == I40E_CUSTOMIZED_GTPU_IPV4) {
1225                                 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1226                                 gtp_ipv4 = (struct ipv4_hdr *)
1227                                         ((unsigned char *)gtp +
1228                                          sizeof(struct rte_flow_item_gtp));
1229                                 gtp_ipv4->version_ihl =
1230                                         I40E_FDIR_IP_DEFAULT_VERSION_IHL;
1231                                 gtp_ipv4->next_proto_id = IPPROTO_IP;
1232                                 gtp_ipv4->total_length =
1233                                         rte_cpu_to_be_16(
1234                                                 I40E_FDIR_INNER_IP_DEFAULT_LEN);
1235                                 payload = (unsigned char *)gtp_ipv4 +
1236                                         sizeof(struct ipv4_hdr);
1237                         } else if (cus_pctype->index ==
1238                                    I40E_CUSTOMIZED_GTPU_IPV6) {
1239                                 gtp->msg_type = I40E_FDIR_GTP_MSG_TYPE_0XFF;
1240                                 gtp_ipv6 = (struct ipv6_hdr *)
1241                                         ((unsigned char *)gtp +
1242                                          sizeof(struct rte_flow_item_gtp));
1243                                 gtp_ipv6->vtc_flow =
1244                                         rte_cpu_to_be_32(
1245                                                I40E_FDIR_IPv6_DEFAULT_VTC_FLOW |
1246                                                (0 << I40E_FDIR_IPv6_TC_OFFSET));
1247                                 gtp_ipv6->proto = IPPROTO_NONE;
1248                                 gtp_ipv6->payload_len =
1249                                         rte_cpu_to_be_16(
1250                                               I40E_FDIR_INNER_IPV6_DEFAULT_LEN);
1251                                 gtp_ipv6->hop_limits =
1252                                         I40E_FDIR_IPv6_DEFAULT_HOP_LIMITS;
1253                                 payload = (unsigned char *)gtp_ipv6 +
1254                                         sizeof(struct ipv6_hdr);
1255                         } else
1256                                 payload = (unsigned char *)gtp +
1257                                         sizeof(struct rte_flow_item_gtp);
1258                 }
1259         } else {
1260                 PMD_DRV_LOG(ERR, "unknown pctype %u.",
1261                             fdir_input->pctype);
1262                 return -1;
1263         }
1264
1265         /* fill the flexbytes to payload */
1266         for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1267                 pit_idx = set_idx * I40E_MAX_FLXPLD_FIED + i;
1268                 size = pf->fdir.flex_set[pit_idx].size;
1269                 if (size == 0)
1270                         continue;
1271                 dst = pf->fdir.flex_set[pit_idx].dst_offset * sizeof(uint16_t);
1272                 ptr = payload +
1273                       pf->fdir.flex_set[pit_idx].src_offset * sizeof(uint16_t);
1274                 (void)rte_memcpy(ptr,
1275                                  &fdir_input->flow_ext.flexbytes[dst],
1276                                  size * sizeof(uint16_t));
1277         }
1278
1279         return 0;
1280 }
1281
1282 /* Construct the tx flags */
1283 static inline uint64_t
1284 i40e_build_ctob(uint32_t td_cmd,
1285                 uint32_t td_offset,
1286                 unsigned int size,
1287                 uint32_t td_tag)
1288 {
1289         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
1290                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
1291                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
1292                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
1293                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
1294 }
1295
1296 /*
1297  * check the programming status descriptor in rx queue.
1298  * done after Programming Flow Director is programmed on
1299  * tx queue
1300  */
1301 static inline int
1302 i40e_check_fdir_programming_status(struct i40e_rx_queue *rxq)
1303 {
1304         volatile union i40e_rx_desc *rxdp;
1305         uint64_t qword1;
1306         uint32_t rx_status;
1307         uint32_t len, id;
1308         uint32_t error;
1309         int ret = 0;
1310
1311         rxdp = &rxq->rx_ring[rxq->rx_tail];
1312         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1313         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1314                         >> I40E_RXD_QW1_STATUS_SHIFT;
1315
1316         if (rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1317                 len = qword1 >> I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT;
1318                 id = (qword1 & I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK) >>
1319                             I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT;
1320
1321                 if (len  == I40E_RX_PROG_STATUS_DESC_LENGTH &&
1322                     id == I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS) {
1323                         error = (qword1 &
1324                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK) >>
1325                                 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT;
1326                         if (error == (0x1 <<
1327                                 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT)) {
1328                                 PMD_DRV_LOG(ERR, "Failed to add FDIR filter"
1329                                             " (FD_ID %u): programming status"
1330                                             " reported.",
1331                                             rxdp->wb.qword0.hi_dword.fd_id);
1332                                 ret = -1;
1333                         } else if (error == (0x1 <<
1334                                 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT)) {
1335                                 PMD_DRV_LOG(ERR, "Failed to delete FDIR filter"
1336                                             " (FD_ID %u): programming status"
1337                                             " reported.",
1338                                             rxdp->wb.qword0.hi_dword.fd_id);
1339                                 ret = -1;
1340                         } else
1341                                 PMD_DRV_LOG(ERR, "invalid programming status"
1342                                             " reported, error = %u.", error);
1343                 } else
1344                         PMD_DRV_LOG(INFO, "unknown programming status"
1345                                     " reported, len = %d, id = %u.", len, id);
1346                 rxdp->wb.qword1.status_error_len = 0;
1347                 rxq->rx_tail++;
1348                 if (unlikely(rxq->rx_tail == rxq->nb_rx_desc))
1349                         rxq->rx_tail = 0;
1350                 if (rxq->rx_tail == 0)
1351                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1352                 else
1353                         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_tail - 1);
1354         }
1355
1356         return ret;
1357 }
1358
1359 static int
1360 i40e_fdir_filter_convert(const struct i40e_fdir_filter_conf *input,
1361                          struct i40e_fdir_filter *filter)
1362 {
1363         rte_memcpy(&filter->fdir, input, sizeof(struct i40e_fdir_filter_conf));
1364         if (input->input.flow_ext.pkt_template) {
1365                 filter->fdir.input.flow.raw_flow.packet = NULL;
1366                 filter->fdir.input.flow.raw_flow.length =
1367                         rte_hash_crc(input->input.flow.raw_flow.packet,
1368                                      input->input.flow.raw_flow.length,
1369                                      input->input.flow.raw_flow.pctype);
1370         }
1371         return 0;
1372 }
1373
1374 /* Check if there exists the flow director filter */
1375 static struct i40e_fdir_filter *
1376 i40e_sw_fdir_filter_lookup(struct i40e_fdir_info *fdir_info,
1377                         const struct i40e_fdir_input *input)
1378 {
1379         int ret;
1380
1381         if (input->flow_ext.pkt_template)
1382                 ret = rte_hash_lookup_with_hash(fdir_info->hash_table,
1383                                                 (const void *)input,
1384                                                 input->flow.raw_flow.length);
1385         else
1386                 ret = rte_hash_lookup(fdir_info->hash_table,
1387                                       (const void *)input);
1388         if (ret < 0)
1389                 return NULL;
1390
1391         return fdir_info->hash_map[ret];
1392 }
1393
1394 /* Add a flow director filter into the SW list */
1395 static int
1396 i40e_sw_fdir_filter_insert(struct i40e_pf *pf, struct i40e_fdir_filter *filter)
1397 {
1398         struct i40e_fdir_info *fdir_info = &pf->fdir;
1399         int ret;
1400
1401         if (filter->fdir.input.flow_ext.pkt_template)
1402                 ret = rte_hash_add_key_with_hash(fdir_info->hash_table,
1403                                  &filter->fdir.input,
1404                                  filter->fdir.input.flow.raw_flow.length);
1405         else
1406                 ret = rte_hash_add_key(fdir_info->hash_table,
1407                                        &filter->fdir.input);
1408         if (ret < 0) {
1409                 PMD_DRV_LOG(ERR,
1410                             "Failed to insert fdir filter to hash table %d!",
1411                             ret);
1412                 return ret;
1413         }
1414         fdir_info->hash_map[ret] = filter;
1415
1416         TAILQ_INSERT_TAIL(&fdir_info->fdir_list, filter, rules);
1417
1418         return 0;
1419 }
1420
1421 /* Delete a flow director filter from the SW list */
1422 int
1423 i40e_sw_fdir_filter_del(struct i40e_pf *pf, struct i40e_fdir_input *input)
1424 {
1425         struct i40e_fdir_info *fdir_info = &pf->fdir;
1426         struct i40e_fdir_filter *filter;
1427         int ret;
1428
1429         if (input->flow_ext.pkt_template)
1430                 ret = rte_hash_del_key_with_hash(fdir_info->hash_table,
1431                                                  input,
1432                                                  input->flow.raw_flow.length);
1433         else
1434                 ret = rte_hash_del_key(fdir_info->hash_table, input);
1435         if (ret < 0) {
1436                 PMD_DRV_LOG(ERR,
1437                             "Failed to delete fdir filter to hash table %d!",
1438                             ret);
1439                 return ret;
1440         }
1441         filter = fdir_info->hash_map[ret];
1442         fdir_info->hash_map[ret] = NULL;
1443
1444         TAILQ_REMOVE(&fdir_info->fdir_list, filter, rules);
1445         rte_free(filter);
1446
1447         return 0;
1448 }
1449
1450 /*
1451  * i40e_add_del_fdir_filter - add or remove a flow director filter.
1452  * @pf: board private structure
1453  * @filter: fdir filter entry
1454  * @add: 0 - delete, 1 - add
1455  */
1456 int
1457 i40e_add_del_fdir_filter(struct rte_eth_dev *dev,
1458                          const struct rte_eth_fdir_filter *filter,
1459                          bool add)
1460 {
1461         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1462         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1463         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1464         enum i40e_filter_pctype pctype;
1465         int ret = 0;
1466
1467         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1468                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please"
1469                         " check the mode in fdir_conf.");
1470                 return -ENOTSUP;
1471         }
1472
1473         pctype = i40e_flowtype_to_pctype(pf->adapter, filter->input.flow_type);
1474         if (pctype == I40E_FILTER_PCTYPE_INVALID) {
1475                 PMD_DRV_LOG(ERR, "invalid flow_type input.");
1476                 return -EINVAL;
1477         }
1478         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1479                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1480                 return -EINVAL;
1481         }
1482         if (filter->input.flow_ext.is_vf &&
1483                 filter->input.flow_ext.dst_id >= pf->vf_num) {
1484                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1485                 return -EINVAL;
1486         }
1487
1488         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1489
1490         ret = i40e_fdir_construct_pkt(pf, &filter->input, pkt);
1491         if (ret < 0) {
1492                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1493                 return ret;
1494         }
1495
1496         if (hw->mac.type == I40E_MAC_X722) {
1497                 /* get translated pctype value in fd pctype register */
1498                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1499                         hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1500         }
1501
1502         ret = i40e_fdir_filter_programming(pf, pctype, filter, add);
1503         if (ret < 0) {
1504                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1505                             pctype);
1506                 return ret;
1507         }
1508
1509         return ret;
1510 }
1511
1512 /**
1513  * i40e_flow_add_del_fdir_filter - add or remove a flow director filter.
1514  * @pf: board private structure
1515  * @filter: fdir filter entry
1516  * @add: 0 - delete, 1 - add
1517  */
1518 int
1519 i40e_flow_add_del_fdir_filter(struct rte_eth_dev *dev,
1520                               const struct i40e_fdir_filter_conf *filter,
1521                               bool add)
1522 {
1523         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1524         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1525         unsigned char *pkt = (unsigned char *)pf->fdir.prg_pkt;
1526         enum i40e_filter_pctype pctype;
1527         struct i40e_fdir_info *fdir_info = &pf->fdir;
1528         struct i40e_fdir_filter *fdir_filter, *node;
1529         struct i40e_fdir_filter check_filter; /* Check if the filter exists */
1530         int ret = 0;
1531
1532         if (dev->data->dev_conf.fdir_conf.mode != RTE_FDIR_MODE_PERFECT) {
1533                 PMD_DRV_LOG(ERR, "FDIR is not enabled, please check the mode in fdir_conf.");
1534                 return -ENOTSUP;
1535         }
1536
1537         if (filter->action.rx_queue >= pf->dev_data->nb_rx_queues) {
1538                 PMD_DRV_LOG(ERR, "Invalid queue ID");
1539                 return -EINVAL;
1540         }
1541         if (filter->input.flow_ext.is_vf &&
1542             filter->input.flow_ext.dst_id >= pf->vf_num) {
1543                 PMD_DRV_LOG(ERR, "Invalid VF ID");
1544                 return -EINVAL;
1545         }
1546         if (filter->input.flow_ext.pkt_template) {
1547                 if (filter->input.flow.raw_flow.length > I40E_FDIR_PKT_LEN ||
1548                     !filter->input.flow.raw_flow.packet) {
1549                         PMD_DRV_LOG(ERR, "Invalid raw packet template"
1550                                 " flow filter parameters!");
1551                         return -EINVAL;
1552                 }
1553                 pctype = filter->input.flow.raw_flow.pctype;
1554         } else {
1555                 pctype = filter->input.pctype;
1556         }
1557
1558         /* Check if there is the filter in SW list */
1559         memset(&check_filter, 0, sizeof(check_filter));
1560         i40e_fdir_filter_convert(filter, &check_filter);
1561         node = i40e_sw_fdir_filter_lookup(fdir_info, &check_filter.fdir.input);
1562         if (add && node) {
1563                 PMD_DRV_LOG(ERR,
1564                             "Conflict with existing flow director rules!");
1565                 return -EINVAL;
1566         }
1567
1568         if (!add && !node) {
1569                 PMD_DRV_LOG(ERR,
1570                             "There's no corresponding flow firector filter!");
1571                 return -EINVAL;
1572         }
1573
1574         memset(pkt, 0, I40E_FDIR_PKT_LEN);
1575
1576         ret = i40e_flow_fdir_construct_pkt(pf, &filter->input, pkt);
1577         if (ret < 0) {
1578                 PMD_DRV_LOG(ERR, "construct packet for fdir fails.");
1579                 return ret;
1580         }
1581
1582         if (hw->mac.type == I40E_MAC_X722) {
1583                 /* get translated pctype value in fd pctype register */
1584                 pctype = (enum i40e_filter_pctype)i40e_read_rx_ctl(
1585                         hw, I40E_GLQF_FD_PCTYPES((int)pctype));
1586         }
1587
1588         ret = i40e_flow_fdir_filter_programming(pf, pctype, filter, add);
1589         if (ret < 0) {
1590                 PMD_DRV_LOG(ERR, "fdir programming fails for PCTYPE(%u).",
1591                             pctype);
1592                 return ret;
1593         }
1594
1595         if (add) {
1596                 fdir_filter = rte_zmalloc("fdir_filter",
1597                                           sizeof(*fdir_filter), 0);
1598                 rte_memcpy(fdir_filter, &check_filter, sizeof(check_filter));
1599                 ret = i40e_sw_fdir_filter_insert(pf, fdir_filter);
1600         } else {
1601                 ret = i40e_sw_fdir_filter_del(pf, &node->fdir.input);
1602         }
1603
1604         return ret;
1605 }
1606
1607 /*
1608  * i40e_fdir_filter_programming - Program a flow director filter rule.
1609  * Is done by Flow Director Programming Descriptor followed by packet
1610  * structure that contains the filter fields need to match.
1611  * @pf: board private structure
1612  * @pctype: pctype
1613  * @filter: fdir filter entry
1614  * @add: 0 - delete, 1 - add
1615  */
1616 static int
1617 i40e_fdir_filter_programming(struct i40e_pf *pf,
1618                         enum i40e_filter_pctype pctype,
1619                         const struct rte_eth_fdir_filter *filter,
1620                         bool add)
1621 {
1622         struct i40e_tx_queue *txq = pf->fdir.txq;
1623         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1624         const struct rte_eth_fdir_action *fdir_action = &filter->action;
1625         volatile struct i40e_tx_desc *txdp;
1626         volatile struct i40e_filter_program_desc *fdirdp;
1627         uint32_t td_cmd;
1628         uint16_t vsi_id, i;
1629         uint8_t dest;
1630
1631         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1632         fdirdp = (volatile struct i40e_filter_program_desc *)
1633                         (&(txq->tx_ring[txq->tx_tail]));
1634
1635         fdirdp->qindex_flex_ptype_vsi =
1636                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1637                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1638                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1639
1640         fdirdp->qindex_flex_ptype_vsi |=
1641                         rte_cpu_to_le_32((fdir_action->flex_off <<
1642                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1643                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1644
1645         fdirdp->qindex_flex_ptype_vsi |=
1646                         rte_cpu_to_le_32((pctype <<
1647                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1648                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1649
1650         if (filter->input.flow_ext.is_vf)
1651                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1652         else
1653                 /* Use LAN VSI Id by default */
1654                 vsi_id = pf->main_vsi->vsi_id;
1655         fdirdp->qindex_flex_ptype_vsi |=
1656                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1657                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1658                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1659
1660         fdirdp->dtype_cmd_cntindex =
1661                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1662
1663         if (add)
1664                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1665                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1666                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1667         else
1668                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1669                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1670                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1671
1672         if (fdir_action->behavior == RTE_ETH_FDIR_REJECT)
1673                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1674         else if (fdir_action->behavior == RTE_ETH_FDIR_ACCEPT)
1675                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1676         else if (fdir_action->behavior == RTE_ETH_FDIR_PASSTHRU)
1677                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1678         else {
1679                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1680                             " unsupported fdir behavior.");
1681                 return -EINVAL;
1682         }
1683
1684         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1685                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1686                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1687
1688         fdirdp->dtype_cmd_cntindex |=
1689                 rte_cpu_to_le_32((fdir_action->report_status<<
1690                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1691                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1692
1693         fdirdp->dtype_cmd_cntindex |=
1694                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1695         fdirdp->dtype_cmd_cntindex |=
1696                         rte_cpu_to_le_32(
1697                         ((uint32_t)pf->fdir.match_counter_index <<
1698                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1699                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1700
1701         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1702
1703         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1704         txdp = &(txq->tx_ring[txq->tx_tail + 1]);
1705         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1706         td_cmd = I40E_TX_DESC_CMD_EOP |
1707                  I40E_TX_DESC_CMD_RS  |
1708                  I40E_TX_DESC_CMD_DUMMY;
1709
1710         txdp->cmd_type_offset_bsz =
1711                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1712
1713         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1714         if (txq->tx_tail >= txq->nb_tx_desc)
1715                 txq->tx_tail = 0;
1716         /* Update the tx tail register */
1717         rte_wmb();
1718         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1719         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1720                 if ((txdp->cmd_type_offset_bsz &
1721                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1722                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1723                         break;
1724                 rte_delay_us(1);
1725         }
1726         if (i >= I40E_FDIR_MAX_WAIT_US) {
1727                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter:"
1728                             " time out to get DD on tx queue.");
1729                 return -ETIMEDOUT;
1730         }
1731         /* totally delay 10 ms to check programming status*/
1732         for (; i < I40E_FDIR_MAX_WAIT_US; i++) {
1733                 if (i40e_check_fdir_programming_status(rxq) >= 0)
1734                         return 0;
1735                 rte_delay_us(1);
1736         }
1737         PMD_DRV_LOG(ERR,
1738                 "Failed to program FDIR filter: programming status reported.");
1739         return -ETIMEDOUT;
1740 }
1741
1742 /*
1743  * i40e_flow_fdir_filter_programming - Program a flow director filter rule.
1744  * Is done by Flow Director Programming Descriptor followed by packet
1745  * structure that contains the filter fields need to match.
1746  * @pf: board private structure
1747  * @pctype: pctype
1748  * @filter: fdir filter entry
1749  * @add: 0 - delete, 1 - add
1750  */
1751 static int
1752 i40e_flow_fdir_filter_programming(struct i40e_pf *pf,
1753                                   enum i40e_filter_pctype pctype,
1754                                   const struct i40e_fdir_filter_conf *filter,
1755                                   bool add)
1756 {
1757         struct i40e_tx_queue *txq = pf->fdir.txq;
1758         struct i40e_rx_queue *rxq = pf->fdir.rxq;
1759         const struct i40e_fdir_action *fdir_action = &filter->action;
1760         volatile struct i40e_tx_desc *txdp;
1761         volatile struct i40e_filter_program_desc *fdirdp;
1762         uint32_t td_cmd;
1763         uint16_t vsi_id, i;
1764         uint8_t dest;
1765
1766         PMD_DRV_LOG(INFO, "filling filter programming descriptor.");
1767         fdirdp = (volatile struct i40e_filter_program_desc *)
1768                                 (&txq->tx_ring[txq->tx_tail]);
1769
1770         fdirdp->qindex_flex_ptype_vsi =
1771                         rte_cpu_to_le_32((fdir_action->rx_queue <<
1772                                           I40E_TXD_FLTR_QW0_QINDEX_SHIFT) &
1773                                           I40E_TXD_FLTR_QW0_QINDEX_MASK);
1774
1775         fdirdp->qindex_flex_ptype_vsi |=
1776                         rte_cpu_to_le_32((fdir_action->flex_off <<
1777                                           I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT) &
1778                                           I40E_TXD_FLTR_QW0_FLEXOFF_MASK);
1779
1780         fdirdp->qindex_flex_ptype_vsi |=
1781                         rte_cpu_to_le_32((pctype <<
1782                                           I40E_TXD_FLTR_QW0_PCTYPE_SHIFT) &
1783                                           I40E_TXD_FLTR_QW0_PCTYPE_MASK);
1784
1785         if (filter->input.flow_ext.is_vf)
1786                 vsi_id = pf->vfs[filter->input.flow_ext.dst_id].vsi->vsi_id;
1787         else
1788                 /* Use LAN VSI Id by default */
1789                 vsi_id = pf->main_vsi->vsi_id;
1790         fdirdp->qindex_flex_ptype_vsi |=
1791                 rte_cpu_to_le_32(((uint32_t)vsi_id <<
1792                                   I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT) &
1793                                   I40E_TXD_FLTR_QW0_DEST_VSI_MASK);
1794
1795         fdirdp->dtype_cmd_cntindex =
1796                         rte_cpu_to_le_32(I40E_TX_DESC_DTYPE_FILTER_PROG);
1797
1798         if (add)
1799                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1800                                 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE <<
1801                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1802         else
1803                 fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32(
1804                                 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE <<
1805                                 I40E_TXD_FLTR_QW1_PCMD_SHIFT);
1806
1807         if (fdir_action->behavior == I40E_FDIR_REJECT)
1808                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET;
1809         else if (fdir_action->behavior == I40E_FDIR_ACCEPT)
1810                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX;
1811         else if (fdir_action->behavior == I40E_FDIR_PASSTHRU)
1812                 dest = I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER;
1813         else {
1814                 PMD_DRV_LOG(ERR, "Failed to program FDIR filter: unsupported fdir behavior.");
1815                 return -EINVAL;
1816         }
1817
1818         fdirdp->dtype_cmd_cntindex |= rte_cpu_to_le_32((dest <<
1819                                 I40E_TXD_FLTR_QW1_DEST_SHIFT) &
1820                                 I40E_TXD_FLTR_QW1_DEST_MASK);
1821
1822         fdirdp->dtype_cmd_cntindex |=
1823                 rte_cpu_to_le_32((fdir_action->report_status <<
1824                                 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT) &
1825                                 I40E_TXD_FLTR_QW1_FD_STATUS_MASK);
1826
1827         fdirdp->dtype_cmd_cntindex |=
1828                         rte_cpu_to_le_32(I40E_TXD_FLTR_QW1_CNT_ENA_MASK);
1829         fdirdp->dtype_cmd_cntindex |=
1830                         rte_cpu_to_le_32(
1831                         ((uint32_t)pf->fdir.match_counter_index <<
1832                         I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT) &
1833                         I40E_TXD_FLTR_QW1_CNTINDEX_MASK);
1834
1835         fdirdp->fd_id = rte_cpu_to_le_32(filter->soft_id);
1836
1837         PMD_DRV_LOG(INFO, "filling transmit descriptor.");
1838         txdp = &txq->tx_ring[txq->tx_tail + 1];
1839         txdp->buffer_addr = rte_cpu_to_le_64(pf->fdir.dma_addr);
1840         td_cmd = I40E_TX_DESC_CMD_EOP |
1841                  I40E_TX_DESC_CMD_RS  |
1842                  I40E_TX_DESC_CMD_DUMMY;
1843
1844         txdp->cmd_type_offset_bsz =
1845                 i40e_build_ctob(td_cmd, 0, I40E_FDIR_PKT_LEN, 0);
1846
1847         txq->tx_tail += 2; /* set 2 descriptors above, fdirdp and txdp */
1848         if (txq->tx_tail >= txq->nb_tx_desc)
1849                 txq->tx_tail = 0;
1850         /* Update the tx tail register */
1851         rte_wmb();
1852         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1853         for (i = 0; i < I40E_FDIR_MAX_WAIT_US; i++) {
1854                 if ((txdp->cmd_type_offset_bsz &
1855                                 rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) ==
1856                                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1857                         break;
1858                 rte_delay_us(1);
1859         }
1860         if (i >= I40E_FDIR_MAX_WAIT_US) {
1861                 PMD_DRV_LOG(ERR,
1862                     "Failed to program FDIR filter: time out to get DD on tx queue.");
1863                 return -ETIMEDOUT;
1864         }
1865         /* totally delay 10 ms to check programming status*/
1866         rte_delay_us(I40E_FDIR_MAX_WAIT_US);
1867         if (i40e_check_fdir_programming_status(rxq) < 0) {
1868                 PMD_DRV_LOG(ERR,
1869                     "Failed to program FDIR filter: programming status reported.");
1870                 return -ETIMEDOUT;
1871         }
1872
1873         return 0;
1874 }
1875
1876 /*
1877  * i40e_fdir_flush - clear all filters of Flow Director table
1878  * @pf: board private structure
1879  */
1880 int
1881 i40e_fdir_flush(struct rte_eth_dev *dev)
1882 {
1883         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1884         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1885         uint32_t reg;
1886         uint16_t guarant_cnt, best_cnt;
1887         uint16_t i;
1888
1889         I40E_WRITE_REG(hw, I40E_PFQF_CTL_1, I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
1890         I40E_WRITE_FLUSH(hw);
1891
1892         for (i = 0; i < I40E_FDIR_FLUSH_RETRY; i++) {
1893                 rte_delay_ms(I40E_FDIR_FLUSH_INTERVAL_MS);
1894                 reg = I40E_READ_REG(hw, I40E_PFQF_CTL_1);
1895                 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
1896                         break;
1897         }
1898         if (i >= I40E_FDIR_FLUSH_RETRY) {
1899                 PMD_DRV_LOG(ERR, "FD table did not flush, may need more time.");
1900                 return -ETIMEDOUT;
1901         }
1902         guarant_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1903                                 I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
1904                                 I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
1905         best_cnt = (uint16_t)((I40E_READ_REG(hw, I40E_PFQF_FDSTAT) &
1906                                 I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
1907                                 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
1908         if (guarant_cnt != 0 || best_cnt != 0) {
1909                 PMD_DRV_LOG(ERR, "Failed to flush FD table.");
1910                 return -ENOSYS;
1911         } else
1912                 PMD_DRV_LOG(INFO, "FD table Flush success.");
1913         return 0;
1914 }
1915
1916 static inline void
1917 i40e_fdir_info_get_flex_set(struct i40e_pf *pf,
1918                         struct rte_eth_flex_payload_cfg *flex_set,
1919                         uint16_t *num)
1920 {
1921         struct i40e_fdir_flex_pit *flex_pit;
1922         struct rte_eth_flex_payload_cfg *ptr = flex_set;
1923         uint16_t src, dst, size, j, k;
1924         uint8_t i, layer_idx;
1925
1926         for (layer_idx = I40E_FLXPLD_L2_IDX;
1927              layer_idx <= I40E_FLXPLD_L4_IDX;
1928              layer_idx++) {
1929                 if (layer_idx == I40E_FLXPLD_L2_IDX)
1930                         ptr->type = RTE_ETH_L2_PAYLOAD;
1931                 else if (layer_idx == I40E_FLXPLD_L3_IDX)
1932                         ptr->type = RTE_ETH_L3_PAYLOAD;
1933                 else if (layer_idx == I40E_FLXPLD_L4_IDX)
1934                         ptr->type = RTE_ETH_L4_PAYLOAD;
1935
1936                 for (i = 0; i < I40E_MAX_FLXPLD_FIED; i++) {
1937                         flex_pit = &pf->fdir.flex_set[layer_idx *
1938                                 I40E_MAX_FLXPLD_FIED + i];
1939                         if (flex_pit->size == 0)
1940                                 continue;
1941                         src = flex_pit->src_offset * sizeof(uint16_t);
1942                         dst = flex_pit->dst_offset * sizeof(uint16_t);
1943                         size = flex_pit->size * sizeof(uint16_t);
1944                         for (j = src, k = dst; j < src + size; j++, k++)
1945                                 ptr->src_offset[k] = j;
1946                 }
1947                 (*num)++;
1948                 ptr++;
1949         }
1950 }
1951
1952 static inline void
1953 i40e_fdir_info_get_flex_mask(struct i40e_pf *pf,
1954                         struct rte_eth_fdir_flex_mask *flex_mask,
1955                         uint16_t *num)
1956 {
1957         struct i40e_fdir_flex_mask *mask;
1958         struct rte_eth_fdir_flex_mask *ptr = flex_mask;
1959         uint16_t flow_type;
1960         uint8_t i, j;
1961         uint16_t off_bytes, mask_tmp;
1962
1963         for (i = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
1964              i <= I40E_FILTER_PCTYPE_L2_PAYLOAD;
1965              i++) {
1966                 mask =  &pf->fdir.flex_mask[i];
1967                 flow_type = i40e_pctype_to_flowtype(pf->adapter,
1968                                                     (enum i40e_filter_pctype)i);
1969                 if (flow_type == RTE_ETH_FLOW_UNKNOWN)
1970                         continue;
1971
1972                 for (j = 0; j < I40E_FDIR_MAX_FLEXWORD_NUM; j++) {
1973                         if (mask->word_mask & I40E_FLEX_WORD_MASK(j)) {
1974                                 ptr->mask[j * sizeof(uint16_t)] = UINT8_MAX;
1975                                 ptr->mask[j * sizeof(uint16_t) + 1] = UINT8_MAX;
1976                         } else {
1977                                 ptr->mask[j * sizeof(uint16_t)] = 0x0;
1978                                 ptr->mask[j * sizeof(uint16_t) + 1] = 0x0;
1979                         }
1980                 }
1981                 for (j = 0; j < I40E_FDIR_BITMASK_NUM_WORD; j++) {
1982                         off_bytes = mask->bitmask[j].offset * sizeof(uint16_t);
1983                         mask_tmp = ~mask->bitmask[j].mask;
1984                         ptr->mask[off_bytes] &= I40E_HI_BYTE(mask_tmp);
1985                         ptr->mask[off_bytes + 1] &= I40E_LO_BYTE(mask_tmp);
1986                 }
1987                 ptr->flow_type = flow_type;
1988                 ptr++;
1989                 (*num)++;
1990         }
1991 }
1992
1993 /*
1994  * i40e_fdir_info_get - get information of Flow Director
1995  * @pf: ethernet device to get info from
1996  * @fdir: a pointer to a structure of type *rte_eth_fdir_info* to be filled with
1997  *    the flow director information.
1998  */
1999 static void
2000 i40e_fdir_info_get(struct rte_eth_dev *dev, struct rte_eth_fdir_info *fdir)
2001 {
2002         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2003         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2004         uint16_t num_flex_set = 0;
2005         uint16_t num_flex_mask = 0;
2006         uint16_t i;
2007
2008         if (dev->data->dev_conf.fdir_conf.mode == RTE_FDIR_MODE_PERFECT)
2009                 fdir->mode = RTE_FDIR_MODE_PERFECT;
2010         else
2011                 fdir->mode = RTE_FDIR_MODE_NONE;
2012
2013         fdir->guarant_spc =
2014                 (uint32_t)hw->func_caps.fd_filters_guaranteed;
2015         fdir->best_spc =
2016                 (uint32_t)hw->func_caps.fd_filters_best_effort;
2017         fdir->max_flexpayload = I40E_FDIR_MAX_FLEX_LEN;
2018         fdir->flow_types_mask[0] = I40E_FDIR_FLOWS;
2019         for (i = 1; i < RTE_FLOW_MASK_ARRAY_SIZE; i++)
2020                 fdir->flow_types_mask[i] = 0ULL;
2021         fdir->flex_payload_unit = sizeof(uint16_t);
2022         fdir->flex_bitmask_unit = sizeof(uint16_t);
2023         fdir->max_flex_payload_segment_num = I40E_MAX_FLXPLD_FIED;
2024         fdir->flex_payload_limit = I40E_MAX_FLX_SOURCE_OFF;
2025         fdir->max_flex_bitmask_num = I40E_FDIR_BITMASK_NUM_WORD;
2026
2027         i40e_fdir_info_get_flex_set(pf,
2028                                 fdir->flex_conf.flex_set,
2029                                 &num_flex_set);
2030         i40e_fdir_info_get_flex_mask(pf,
2031                                 fdir->flex_conf.flex_mask,
2032                                 &num_flex_mask);
2033
2034         fdir->flex_conf.nb_payloads = num_flex_set;
2035         fdir->flex_conf.nb_flexmasks = num_flex_mask;
2036 }
2037
2038 /*
2039  * i40e_fdir_stat_get - get statistics of Flow Director
2040  * @pf: ethernet device to get info from
2041  * @stat: a pointer to a structure of type *rte_eth_fdir_stats* to be filled with
2042  *    the flow director statistics.
2043  */
2044 static void
2045 i40e_fdir_stats_get(struct rte_eth_dev *dev, struct rte_eth_fdir_stats *stat)
2046 {
2047         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2048         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2049         uint32_t fdstat;
2050
2051         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2052         stat->guarant_cnt =
2053                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2054                             I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2055         stat->best_cnt =
2056                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2057                             I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2058 }
2059
2060 static int
2061 i40e_fdir_filter_set(struct rte_eth_dev *dev,
2062                      struct rte_eth_fdir_filter_info *info)
2063 {
2064         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2065         int ret = 0;
2066
2067         if (!info) {
2068                 PMD_DRV_LOG(ERR, "Invalid pointer");
2069                 return -EFAULT;
2070         }
2071
2072         switch (info->info_type) {
2073         case RTE_ETH_FDIR_FILTER_INPUT_SET_SELECT:
2074                 ret = i40e_fdir_filter_inset_select(pf,
2075                                 &(info->info.input_set_conf));
2076                 break;
2077         default:
2078                 PMD_DRV_LOG(ERR, "FD filter info type (%d) not supported",
2079                             info->info_type);
2080                 return -EINVAL;
2081         }
2082
2083         return ret;
2084 }
2085
2086 /*
2087  * i40e_fdir_ctrl_func - deal with all operations on flow director.
2088  * @pf: board private structure
2089  * @filter_op:operation will be taken.
2090  * @arg: a pointer to specific structure corresponding to the filter_op
2091  */
2092 int
2093 i40e_fdir_ctrl_func(struct rte_eth_dev *dev,
2094                        enum rte_filter_op filter_op,
2095                        void *arg)
2096 {
2097         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2098         int ret = 0;
2099
2100         if ((pf->flags & I40E_FLAG_FDIR) == 0)
2101                 return -ENOTSUP;
2102
2103         if (filter_op == RTE_ETH_FILTER_NOP)
2104                 return 0;
2105
2106         if (arg == NULL && filter_op != RTE_ETH_FILTER_FLUSH)
2107                 return -EINVAL;
2108
2109         switch (filter_op) {
2110         case RTE_ETH_FILTER_ADD:
2111                 ret = i40e_add_del_fdir_filter(dev,
2112                         (struct rte_eth_fdir_filter *)arg,
2113                         TRUE);
2114                 break;
2115         case RTE_ETH_FILTER_DELETE:
2116                 ret = i40e_add_del_fdir_filter(dev,
2117                         (struct rte_eth_fdir_filter *)arg,
2118                         FALSE);
2119                 break;
2120         case RTE_ETH_FILTER_FLUSH:
2121                 ret = i40e_fdir_flush(dev);
2122                 break;
2123         case RTE_ETH_FILTER_INFO:
2124                 i40e_fdir_info_get(dev, (struct rte_eth_fdir_info *)arg);
2125                 break;
2126         case RTE_ETH_FILTER_SET:
2127                 ret = i40e_fdir_filter_set(dev,
2128                         (struct rte_eth_fdir_filter_info *)arg);
2129                 break;
2130         case RTE_ETH_FILTER_STATS:
2131                 i40e_fdir_stats_get(dev, (struct rte_eth_fdir_stats *)arg);
2132                 break;
2133         default:
2134                 PMD_DRV_LOG(ERR, "unknown operation %u.", filter_op);
2135                 ret = -EINVAL;
2136                 break;
2137         }
2138         return ret;
2139 }
2140
2141 /* Restore flow director filter */
2142 void
2143 i40e_fdir_filter_restore(struct i40e_pf *pf)
2144 {
2145         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(pf->main_vsi);
2146         struct i40e_fdir_filter_list *fdir_list = &pf->fdir.fdir_list;
2147         struct i40e_fdir_filter *f;
2148         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2149         uint32_t fdstat;
2150         uint32_t guarant_cnt;  /**< Number of filters in guaranteed spaces. */
2151         uint32_t best_cnt;     /**< Number of filters in best effort spaces. */
2152
2153         TAILQ_FOREACH(f, fdir_list, rules)
2154                 i40e_flow_add_del_fdir_filter(dev, &f->fdir, TRUE);
2155
2156         fdstat = I40E_READ_REG(hw, I40E_PFQF_FDSTAT);
2157         guarant_cnt =
2158                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) >>
2159                            I40E_PFQF_FDSTAT_GUARANT_CNT_SHIFT);
2160         best_cnt =
2161                 (uint32_t)((fdstat & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
2162                            I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
2163
2164         PMD_DRV_LOG(INFO, "FDIR: Guarant count: %d,  Best count: %d",
2165                     guarant_cnt, best_cnt);
2166 }