drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_ether.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_log.h>
  16 #include <rte_malloc.h>
  17 #include <rte_eth_ctrl.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_item *pattern,
  57                                         struct rte_flow_error *error,
  58                                         struct i40e_fdir_filter_conf *filter);
  59 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  60                                        const struct rte_flow_action *actions,
  61                                        struct rte_flow_error *error,
  62                                        struct i40e_fdir_filter_conf *filter);
  63 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  64                                  const struct rte_flow_action *actions,
  65                                  struct rte_flow_error *error,
  66                                  struct i40e_tunnel_filter_conf *filter);
  67 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  68                                 struct rte_flow_error *error);
  69 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  70                                     const struct rte_flow_attr *attr,
  71                                     const struct rte_flow_item pattern[],
  72                                     const struct rte_flow_action actions[],
  73                                     struct rte_flow_error *error,
  74                                     union i40e_filter_t *filter);
  75 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  76                                        const struct rte_flow_attr *attr,
  77                                        const struct rte_flow_item pattern[],
  78                                        const struct rte_flow_action actions[],
  79                                        struct rte_flow_error *error,
  80                                        union i40e_filter_t *filter);
  81 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  82                                         const struct rte_flow_attr *attr,
  83                                         const struct rte_flow_item pattern[],
  84                                         const struct rte_flow_action actions[],
  85                                         struct rte_flow_error *error,
  86                                         union i40e_filter_t *filter);
  87 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  88                                         const struct rte_flow_attr *attr,
  89                                         const struct rte_flow_item pattern[],
  90                                         const struct rte_flow_action actions[],
  91                                         struct rte_flow_error *error,
  92                                         union i40e_filter_t *filter);
  93 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  94                                        const struct rte_flow_attr *attr,
  95                                        const struct rte_flow_item pattern[],
  96                                        const struct rte_flow_action actions[],
  97                                        struct rte_flow_error *error,
  98                                        union i40e_filter_t *filter);
  99 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 100                                       const struct rte_flow_attr *attr,
 101                                       const struct rte_flow_item pattern[],
 102                                       const struct rte_flow_action actions[],
 103                                       struct rte_flow_error *error,
 104                                       union i40e_filter_t *filter);
 105 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 106                                       struct i40e_ethertype_filter *filter);
 107 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 108                                            struct i40e_tunnel_filter *filter);
 109 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 110 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 112 static int
 113 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 114 static int
 115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 116                               const struct rte_flow_attr *attr,
 117                               const struct rte_flow_item pattern[],
 118                               const struct rte_flow_action actions[],
 119                               struct rte_flow_error *error,
 120                               union i40e_filter_t *filter);
 121 static int
 122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 123                               const struct rte_flow_item *pattern,
 124                               struct rte_flow_error *error,
 125                               struct i40e_tunnel_filter_conf *filter);
 126
 127 const struct rte_flow_ops i40e_flow_ops = {
 128         .validate = i40e_flow_validate,
 129         .create = i40e_flow_create,
 130         .destroy = i40e_flow_destroy,
 131         .flush = i40e_flow_flush,
 132 };
 133
 134 union i40e_filter_t cons_filter;
 135 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 136
 137 /* Pattern matched ethertype filter */
 138 static enum rte_flow_item_type pattern_ethertype[] = {
 139         RTE_FLOW_ITEM_TYPE_ETH,
 140         RTE_FLOW_ITEM_TYPE_END,
 141 };
 142
 143 /* Pattern matched flow director filter */
 144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 145         RTE_FLOW_ITEM_TYPE_ETH,
 146         RTE_FLOW_ITEM_TYPE_IPV4,
 147         RTE_FLOW_ITEM_TYPE_END,
 148 };
 149
 150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 151         RTE_FLOW_ITEM_TYPE_ETH,
 152         RTE_FLOW_ITEM_TYPE_IPV4,
 153         RTE_FLOW_ITEM_TYPE_UDP,
 154         RTE_FLOW_ITEM_TYPE_END,
 155 };
 156
 157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 158         RTE_FLOW_ITEM_TYPE_ETH,
 159         RTE_FLOW_ITEM_TYPE_IPV4,
 160         RTE_FLOW_ITEM_TYPE_TCP,
 161         RTE_FLOW_ITEM_TYPE_END,
 162 };
 163
 164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 165         RTE_FLOW_ITEM_TYPE_ETH,
 166         RTE_FLOW_ITEM_TYPE_IPV4,
 167         RTE_FLOW_ITEM_TYPE_SCTP,
 168         RTE_FLOW_ITEM_TYPE_END,
 169 };
 170
 171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 172         RTE_FLOW_ITEM_TYPE_ETH,
 173         RTE_FLOW_ITEM_TYPE_IPV4,
 174         RTE_FLOW_ITEM_TYPE_UDP,
 175         RTE_FLOW_ITEM_TYPE_GTPC,
 176         RTE_FLOW_ITEM_TYPE_END,
 177 };
 178
 179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 180         RTE_FLOW_ITEM_TYPE_ETH,
 181         RTE_FLOW_ITEM_TYPE_IPV4,
 182         RTE_FLOW_ITEM_TYPE_UDP,
 183         RTE_FLOW_ITEM_TYPE_GTPU,
 184         RTE_FLOW_ITEM_TYPE_END,
 185 };
 186
 187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 188         RTE_FLOW_ITEM_TYPE_ETH,
 189         RTE_FLOW_ITEM_TYPE_IPV4,
 190         RTE_FLOW_ITEM_TYPE_UDP,
 191         RTE_FLOW_ITEM_TYPE_GTPU,
 192         RTE_FLOW_ITEM_TYPE_IPV4,
 193         RTE_FLOW_ITEM_TYPE_END,
 194 };
 195
 196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 197         RTE_FLOW_ITEM_TYPE_ETH,
 198         RTE_FLOW_ITEM_TYPE_IPV4,
 199         RTE_FLOW_ITEM_TYPE_UDP,
 200         RTE_FLOW_ITEM_TYPE_GTPU,
 201         RTE_FLOW_ITEM_TYPE_IPV6,
 202         RTE_FLOW_ITEM_TYPE_END,
 203 };
 204
 205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 206         RTE_FLOW_ITEM_TYPE_ETH,
 207         RTE_FLOW_ITEM_TYPE_IPV6,
 208         RTE_FLOW_ITEM_TYPE_END,
 209 };
 210
 211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 212         RTE_FLOW_ITEM_TYPE_ETH,
 213         RTE_FLOW_ITEM_TYPE_IPV6,
 214         RTE_FLOW_ITEM_TYPE_UDP,
 215         RTE_FLOW_ITEM_TYPE_END,
 216 };
 217
 218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 219         RTE_FLOW_ITEM_TYPE_ETH,
 220         RTE_FLOW_ITEM_TYPE_IPV6,
 221         RTE_FLOW_ITEM_TYPE_TCP,
 222         RTE_FLOW_ITEM_TYPE_END,
 223 };
 224
 225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 226         RTE_FLOW_ITEM_TYPE_ETH,
 227         RTE_FLOW_ITEM_TYPE_IPV6,
 228         RTE_FLOW_ITEM_TYPE_SCTP,
 229         RTE_FLOW_ITEM_TYPE_END,
 230 };
 231
 232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 233         RTE_FLOW_ITEM_TYPE_ETH,
 234         RTE_FLOW_ITEM_TYPE_IPV6,
 235         RTE_FLOW_ITEM_TYPE_UDP,
 236         RTE_FLOW_ITEM_TYPE_GTPC,
 237         RTE_FLOW_ITEM_TYPE_END,
 238 };
 239
 240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 241         RTE_FLOW_ITEM_TYPE_ETH,
 242         RTE_FLOW_ITEM_TYPE_IPV6,
 243         RTE_FLOW_ITEM_TYPE_UDP,
 244         RTE_FLOW_ITEM_TYPE_GTPU,
 245         RTE_FLOW_ITEM_TYPE_END,
 246 };
 247
 248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 249         RTE_FLOW_ITEM_TYPE_ETH,
 250         RTE_FLOW_ITEM_TYPE_IPV6,
 251         RTE_FLOW_ITEM_TYPE_UDP,
 252         RTE_FLOW_ITEM_TYPE_GTPU,
 253         RTE_FLOW_ITEM_TYPE_IPV4,
 254         RTE_FLOW_ITEM_TYPE_END,
 255 };
 256
 257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 258         RTE_FLOW_ITEM_TYPE_ETH,
 259         RTE_FLOW_ITEM_TYPE_IPV6,
 260         RTE_FLOW_ITEM_TYPE_UDP,
 261         RTE_FLOW_ITEM_TYPE_GTPU,
 262         RTE_FLOW_ITEM_TYPE_IPV6,
 263         RTE_FLOW_ITEM_TYPE_END,
 264 };
 265
 266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 267         RTE_FLOW_ITEM_TYPE_ETH,
 268         RTE_FLOW_ITEM_TYPE_RAW,
 269         RTE_FLOW_ITEM_TYPE_END,
 270 };
 271
 272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 273         RTE_FLOW_ITEM_TYPE_ETH,
 274         RTE_FLOW_ITEM_TYPE_RAW,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_END,
 277 };
 278
 279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 280         RTE_FLOW_ITEM_TYPE_ETH,
 281         RTE_FLOW_ITEM_TYPE_RAW,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_END,
 285 };
 286
 287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 288         RTE_FLOW_ITEM_TYPE_ETH,
 289         RTE_FLOW_ITEM_TYPE_IPV4,
 290         RTE_FLOW_ITEM_TYPE_RAW,
 291         RTE_FLOW_ITEM_TYPE_END,
 292 };
 293
 294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 295         RTE_FLOW_ITEM_TYPE_ETH,
 296         RTE_FLOW_ITEM_TYPE_IPV4,
 297         RTE_FLOW_ITEM_TYPE_RAW,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_END,
 300 };
 301
 302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 303         RTE_FLOW_ITEM_TYPE_ETH,
 304         RTE_FLOW_ITEM_TYPE_IPV4,
 305         RTE_FLOW_ITEM_TYPE_RAW,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_END,
 309 };
 310
 311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 312         RTE_FLOW_ITEM_TYPE_ETH,
 313         RTE_FLOW_ITEM_TYPE_IPV4,
 314         RTE_FLOW_ITEM_TYPE_UDP,
 315         RTE_FLOW_ITEM_TYPE_RAW,
 316         RTE_FLOW_ITEM_TYPE_END,
 317 };
 318
 319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 320         RTE_FLOW_ITEM_TYPE_ETH,
 321         RTE_FLOW_ITEM_TYPE_IPV4,
 322         RTE_FLOW_ITEM_TYPE_UDP,
 323         RTE_FLOW_ITEM_TYPE_RAW,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_END,
 326 };
 327
 328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 329         RTE_FLOW_ITEM_TYPE_ETH,
 330         RTE_FLOW_ITEM_TYPE_IPV4,
 331         RTE_FLOW_ITEM_TYPE_UDP,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_END,
 336 };
 337
 338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 339         RTE_FLOW_ITEM_TYPE_ETH,
 340         RTE_FLOW_ITEM_TYPE_IPV4,
 341         RTE_FLOW_ITEM_TYPE_TCP,
 342         RTE_FLOW_ITEM_TYPE_RAW,
 343         RTE_FLOW_ITEM_TYPE_END,
 344 };
 345
 346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 347         RTE_FLOW_ITEM_TYPE_ETH,
 348         RTE_FLOW_ITEM_TYPE_IPV4,
 349         RTE_FLOW_ITEM_TYPE_TCP,
 350         RTE_FLOW_ITEM_TYPE_RAW,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_END,
 353 };
 354
 355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 356         RTE_FLOW_ITEM_TYPE_ETH,
 357         RTE_FLOW_ITEM_TYPE_IPV4,
 358         RTE_FLOW_ITEM_TYPE_TCP,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_END,
 363 };
 364
 365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 366         RTE_FLOW_ITEM_TYPE_ETH,
 367         RTE_FLOW_ITEM_TYPE_IPV4,
 368         RTE_FLOW_ITEM_TYPE_SCTP,
 369         RTE_FLOW_ITEM_TYPE_RAW,
 370         RTE_FLOW_ITEM_TYPE_END,
 371 };
 372
 373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 374         RTE_FLOW_ITEM_TYPE_ETH,
 375         RTE_FLOW_ITEM_TYPE_IPV4,
 376         RTE_FLOW_ITEM_TYPE_SCTP,
 377         RTE_FLOW_ITEM_TYPE_RAW,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_END,
 380 };
 381
 382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 383         RTE_FLOW_ITEM_TYPE_ETH,
 384         RTE_FLOW_ITEM_TYPE_IPV4,
 385         RTE_FLOW_ITEM_TYPE_SCTP,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_END,
 390 };
 391
 392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 393         RTE_FLOW_ITEM_TYPE_ETH,
 394         RTE_FLOW_ITEM_TYPE_IPV6,
 395         RTE_FLOW_ITEM_TYPE_RAW,
 396         RTE_FLOW_ITEM_TYPE_END,
 397 };
 398
 399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 400         RTE_FLOW_ITEM_TYPE_ETH,
 401         RTE_FLOW_ITEM_TYPE_IPV6,
 402         RTE_FLOW_ITEM_TYPE_RAW,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_END,
 405 };
 406
 407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 408         RTE_FLOW_ITEM_TYPE_ETH,
 409         RTE_FLOW_ITEM_TYPE_IPV6,
 410         RTE_FLOW_ITEM_TYPE_RAW,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_END,
 414 };
 415
 416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 417         RTE_FLOW_ITEM_TYPE_ETH,
 418         RTE_FLOW_ITEM_TYPE_IPV6,
 419         RTE_FLOW_ITEM_TYPE_UDP,
 420         RTE_FLOW_ITEM_TYPE_RAW,
 421         RTE_FLOW_ITEM_TYPE_END,
 422 };
 423
 424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 425         RTE_FLOW_ITEM_TYPE_ETH,
 426         RTE_FLOW_ITEM_TYPE_IPV6,
 427         RTE_FLOW_ITEM_TYPE_UDP,
 428         RTE_FLOW_ITEM_TYPE_RAW,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_END,
 431 };
 432
 433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 434         RTE_FLOW_ITEM_TYPE_ETH,
 435         RTE_FLOW_ITEM_TYPE_IPV6,
 436         RTE_FLOW_ITEM_TYPE_UDP,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_END,
 441 };
 442
 443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 444         RTE_FLOW_ITEM_TYPE_ETH,
 445         RTE_FLOW_ITEM_TYPE_IPV6,
 446         RTE_FLOW_ITEM_TYPE_TCP,
 447         RTE_FLOW_ITEM_TYPE_RAW,
 448         RTE_FLOW_ITEM_TYPE_END,
 449 };
 450
 451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 452         RTE_FLOW_ITEM_TYPE_ETH,
 453         RTE_FLOW_ITEM_TYPE_IPV6,
 454         RTE_FLOW_ITEM_TYPE_TCP,
 455         RTE_FLOW_ITEM_TYPE_RAW,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_END,
 458 };
 459
 460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 461         RTE_FLOW_ITEM_TYPE_ETH,
 462         RTE_FLOW_ITEM_TYPE_IPV6,
 463         RTE_FLOW_ITEM_TYPE_TCP,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_END,
 468 };
 469
 470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 471         RTE_FLOW_ITEM_TYPE_ETH,
 472         RTE_FLOW_ITEM_TYPE_IPV6,
 473         RTE_FLOW_ITEM_TYPE_SCTP,
 474         RTE_FLOW_ITEM_TYPE_RAW,
 475         RTE_FLOW_ITEM_TYPE_END,
 476 };
 477
 478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 479         RTE_FLOW_ITEM_TYPE_ETH,
 480         RTE_FLOW_ITEM_TYPE_IPV6,
 481         RTE_FLOW_ITEM_TYPE_SCTP,
 482         RTE_FLOW_ITEM_TYPE_RAW,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_END,
 485 };
 486
 487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 488         RTE_FLOW_ITEM_TYPE_ETH,
 489         RTE_FLOW_ITEM_TYPE_IPV6,
 490         RTE_FLOW_ITEM_TYPE_SCTP,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_END,
 495 };
 496
 497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 498         RTE_FLOW_ITEM_TYPE_ETH,
 499         RTE_FLOW_ITEM_TYPE_VLAN,
 500         RTE_FLOW_ITEM_TYPE_END,
 501 };
 502
 503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 504         RTE_FLOW_ITEM_TYPE_ETH,
 505         RTE_FLOW_ITEM_TYPE_VLAN,
 506         RTE_FLOW_ITEM_TYPE_IPV4,
 507         RTE_FLOW_ITEM_TYPE_END,
 508 };
 509
 510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 511         RTE_FLOW_ITEM_TYPE_ETH,
 512         RTE_FLOW_ITEM_TYPE_VLAN,
 513         RTE_FLOW_ITEM_TYPE_IPV4,
 514         RTE_FLOW_ITEM_TYPE_UDP,
 515         RTE_FLOW_ITEM_TYPE_END,
 516 };
 517
 518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 519         RTE_FLOW_ITEM_TYPE_ETH,
 520         RTE_FLOW_ITEM_TYPE_VLAN,
 521         RTE_FLOW_ITEM_TYPE_IPV4,
 522         RTE_FLOW_ITEM_TYPE_TCP,
 523         RTE_FLOW_ITEM_TYPE_END,
 524 };
 525
 526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 527         RTE_FLOW_ITEM_TYPE_ETH,
 528         RTE_FLOW_ITEM_TYPE_VLAN,
 529         RTE_FLOW_ITEM_TYPE_IPV4,
 530         RTE_FLOW_ITEM_TYPE_SCTP,
 531         RTE_FLOW_ITEM_TYPE_END,
 532 };
 533
 534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 535         RTE_FLOW_ITEM_TYPE_ETH,
 536         RTE_FLOW_ITEM_TYPE_VLAN,
 537         RTE_FLOW_ITEM_TYPE_IPV6,
 538         RTE_FLOW_ITEM_TYPE_END,
 539 };
 540
 541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 542         RTE_FLOW_ITEM_TYPE_ETH,
 543         RTE_FLOW_ITEM_TYPE_VLAN,
 544         RTE_FLOW_ITEM_TYPE_IPV6,
 545         RTE_FLOW_ITEM_TYPE_UDP,
 546         RTE_FLOW_ITEM_TYPE_END,
 547 };
 548
 549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 550         RTE_FLOW_ITEM_TYPE_ETH,
 551         RTE_FLOW_ITEM_TYPE_VLAN,
 552         RTE_FLOW_ITEM_TYPE_IPV6,
 553         RTE_FLOW_ITEM_TYPE_TCP,
 554         RTE_FLOW_ITEM_TYPE_END,
 555 };
 556
 557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 558         RTE_FLOW_ITEM_TYPE_ETH,
 559         RTE_FLOW_ITEM_TYPE_VLAN,
 560         RTE_FLOW_ITEM_TYPE_IPV6,
 561         RTE_FLOW_ITEM_TYPE_SCTP,
 562         RTE_FLOW_ITEM_TYPE_END,
 563 };
 564
 565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 566         RTE_FLOW_ITEM_TYPE_ETH,
 567         RTE_FLOW_ITEM_TYPE_VLAN,
 568         RTE_FLOW_ITEM_TYPE_RAW,
 569         RTE_FLOW_ITEM_TYPE_END,
 570 };
 571
 572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 573         RTE_FLOW_ITEM_TYPE_ETH,
 574         RTE_FLOW_ITEM_TYPE_VLAN,
 575         RTE_FLOW_ITEM_TYPE_RAW,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_END,
 578 };
 579
 580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 581         RTE_FLOW_ITEM_TYPE_ETH,
 582         RTE_FLOW_ITEM_TYPE_VLAN,
 583         RTE_FLOW_ITEM_TYPE_RAW,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_END,
 587 };
 588
 589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 590         RTE_FLOW_ITEM_TYPE_ETH,
 591         RTE_FLOW_ITEM_TYPE_VLAN,
 592         RTE_FLOW_ITEM_TYPE_IPV4,
 593         RTE_FLOW_ITEM_TYPE_RAW,
 594         RTE_FLOW_ITEM_TYPE_END,
 595 };
 596
 597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 598         RTE_FLOW_ITEM_TYPE_ETH,
 599         RTE_FLOW_ITEM_TYPE_VLAN,
 600         RTE_FLOW_ITEM_TYPE_IPV4,
 601         RTE_FLOW_ITEM_TYPE_RAW,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_END,
 604 };
 605
 606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 607         RTE_FLOW_ITEM_TYPE_ETH,
 608         RTE_FLOW_ITEM_TYPE_VLAN,
 609         RTE_FLOW_ITEM_TYPE_IPV4,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_END,
 614 };
 615
 616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 617         RTE_FLOW_ITEM_TYPE_ETH,
 618         RTE_FLOW_ITEM_TYPE_VLAN,
 619         RTE_FLOW_ITEM_TYPE_IPV4,
 620         RTE_FLOW_ITEM_TYPE_UDP,
 621         RTE_FLOW_ITEM_TYPE_RAW,
 622         RTE_FLOW_ITEM_TYPE_END,
 623 };
 624
 625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 626         RTE_FLOW_ITEM_TYPE_ETH,
 627         RTE_FLOW_ITEM_TYPE_VLAN,
 628         RTE_FLOW_ITEM_TYPE_IPV4,
 629         RTE_FLOW_ITEM_TYPE_UDP,
 630         RTE_FLOW_ITEM_TYPE_RAW,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_END,
 633 };
 634
 635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 636         RTE_FLOW_ITEM_TYPE_ETH,
 637         RTE_FLOW_ITEM_TYPE_VLAN,
 638         RTE_FLOW_ITEM_TYPE_IPV4,
 639         RTE_FLOW_ITEM_TYPE_UDP,
 640         RTE_FLOW_ITEM_TYPE_RAW,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_END,
 644 };
 645
 646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 647         RTE_FLOW_ITEM_TYPE_ETH,
 648         RTE_FLOW_ITEM_TYPE_VLAN,
 649         RTE_FLOW_ITEM_TYPE_IPV4,
 650         RTE_FLOW_ITEM_TYPE_TCP,
 651         RTE_FLOW_ITEM_TYPE_RAW,
 652         RTE_FLOW_ITEM_TYPE_END,
 653 };
 654
 655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 656         RTE_FLOW_ITEM_TYPE_ETH,
 657         RTE_FLOW_ITEM_TYPE_VLAN,
 658         RTE_FLOW_ITEM_TYPE_IPV4,
 659         RTE_FLOW_ITEM_TYPE_TCP,
 660         RTE_FLOW_ITEM_TYPE_RAW,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_END,
 663 };
 664
 665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 666         RTE_FLOW_ITEM_TYPE_ETH,
 667         RTE_FLOW_ITEM_TYPE_VLAN,
 668         RTE_FLOW_ITEM_TYPE_IPV4,
 669         RTE_FLOW_ITEM_TYPE_TCP,
 670         RTE_FLOW_ITEM_TYPE_RAW,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_END,
 674 };
 675
 676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 677         RTE_FLOW_ITEM_TYPE_ETH,
 678         RTE_FLOW_ITEM_TYPE_VLAN,
 679         RTE_FLOW_ITEM_TYPE_IPV4,
 680         RTE_FLOW_ITEM_TYPE_SCTP,
 681         RTE_FLOW_ITEM_TYPE_RAW,
 682         RTE_FLOW_ITEM_TYPE_END,
 683 };
 684
 685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 686         RTE_FLOW_ITEM_TYPE_ETH,
 687         RTE_FLOW_ITEM_TYPE_VLAN,
 688         RTE_FLOW_ITEM_TYPE_IPV4,
 689         RTE_FLOW_ITEM_TYPE_SCTP,
 690         RTE_FLOW_ITEM_TYPE_RAW,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_END,
 693 };
 694
 695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 696         RTE_FLOW_ITEM_TYPE_ETH,
 697         RTE_FLOW_ITEM_TYPE_VLAN,
 698         RTE_FLOW_ITEM_TYPE_IPV4,
 699         RTE_FLOW_ITEM_TYPE_SCTP,
 700         RTE_FLOW_ITEM_TYPE_RAW,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_END,
 704 };
 705
 706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 707         RTE_FLOW_ITEM_TYPE_ETH,
 708         RTE_FLOW_ITEM_TYPE_VLAN,
 709         RTE_FLOW_ITEM_TYPE_IPV6,
 710         RTE_FLOW_ITEM_TYPE_RAW,
 711         RTE_FLOW_ITEM_TYPE_END,
 712 };
 713
 714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 715         RTE_FLOW_ITEM_TYPE_ETH,
 716         RTE_FLOW_ITEM_TYPE_VLAN,
 717         RTE_FLOW_ITEM_TYPE_IPV6,
 718         RTE_FLOW_ITEM_TYPE_RAW,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_END,
 721 };
 722
 723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 724         RTE_FLOW_ITEM_TYPE_ETH,
 725         RTE_FLOW_ITEM_TYPE_VLAN,
 726         RTE_FLOW_ITEM_TYPE_IPV6,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_END,
 731 };
 732
 733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 734         RTE_FLOW_ITEM_TYPE_ETH,
 735         RTE_FLOW_ITEM_TYPE_VLAN,
 736         RTE_FLOW_ITEM_TYPE_IPV6,
 737         RTE_FLOW_ITEM_TYPE_UDP,
 738         RTE_FLOW_ITEM_TYPE_RAW,
 739         RTE_FLOW_ITEM_TYPE_END,
 740 };
 741
 742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 743         RTE_FLOW_ITEM_TYPE_ETH,
 744         RTE_FLOW_ITEM_TYPE_VLAN,
 745         RTE_FLOW_ITEM_TYPE_IPV6,
 746         RTE_FLOW_ITEM_TYPE_UDP,
 747         RTE_FLOW_ITEM_TYPE_RAW,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_END,
 750 };
 751
 752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 753         RTE_FLOW_ITEM_TYPE_ETH,
 754         RTE_FLOW_ITEM_TYPE_VLAN,
 755         RTE_FLOW_ITEM_TYPE_IPV6,
 756         RTE_FLOW_ITEM_TYPE_UDP,
 757         RTE_FLOW_ITEM_TYPE_RAW,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_END,
 761 };
 762
 763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 764         RTE_FLOW_ITEM_TYPE_ETH,
 765         RTE_FLOW_ITEM_TYPE_VLAN,
 766         RTE_FLOW_ITEM_TYPE_IPV6,
 767         RTE_FLOW_ITEM_TYPE_TCP,
 768         RTE_FLOW_ITEM_TYPE_RAW,
 769         RTE_FLOW_ITEM_TYPE_END,
 770 };
 771
 772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 773         RTE_FLOW_ITEM_TYPE_ETH,
 774         RTE_FLOW_ITEM_TYPE_VLAN,
 775         RTE_FLOW_ITEM_TYPE_IPV6,
 776         RTE_FLOW_ITEM_TYPE_TCP,
 777         RTE_FLOW_ITEM_TYPE_RAW,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_END,
 780 };
 781
 782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 783         RTE_FLOW_ITEM_TYPE_ETH,
 784         RTE_FLOW_ITEM_TYPE_VLAN,
 785         RTE_FLOW_ITEM_TYPE_IPV6,
 786         RTE_FLOW_ITEM_TYPE_TCP,
 787         RTE_FLOW_ITEM_TYPE_RAW,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_END,
 791 };
 792
 793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 794         RTE_FLOW_ITEM_TYPE_ETH,
 795         RTE_FLOW_ITEM_TYPE_VLAN,
 796         RTE_FLOW_ITEM_TYPE_IPV6,
 797         RTE_FLOW_ITEM_TYPE_SCTP,
 798         RTE_FLOW_ITEM_TYPE_RAW,
 799         RTE_FLOW_ITEM_TYPE_END,
 800 };
 801
 802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 803         RTE_FLOW_ITEM_TYPE_ETH,
 804         RTE_FLOW_ITEM_TYPE_VLAN,
 805         RTE_FLOW_ITEM_TYPE_IPV6,
 806         RTE_FLOW_ITEM_TYPE_SCTP,
 807         RTE_FLOW_ITEM_TYPE_RAW,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_END,
 810 };
 811
 812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 813         RTE_FLOW_ITEM_TYPE_ETH,
 814         RTE_FLOW_ITEM_TYPE_VLAN,
 815         RTE_FLOW_ITEM_TYPE_IPV6,
 816         RTE_FLOW_ITEM_TYPE_SCTP,
 817         RTE_FLOW_ITEM_TYPE_RAW,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_END,
 821 };
 822
 823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 824         RTE_FLOW_ITEM_TYPE_ETH,
 825         RTE_FLOW_ITEM_TYPE_IPV4,
 826         RTE_FLOW_ITEM_TYPE_VF,
 827         RTE_FLOW_ITEM_TYPE_END,
 828 };
 829
 830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 831         RTE_FLOW_ITEM_TYPE_ETH,
 832         RTE_FLOW_ITEM_TYPE_IPV4,
 833         RTE_FLOW_ITEM_TYPE_UDP,
 834         RTE_FLOW_ITEM_TYPE_VF,
 835         RTE_FLOW_ITEM_TYPE_END,
 836 };
 837
 838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 839         RTE_FLOW_ITEM_TYPE_ETH,
 840         RTE_FLOW_ITEM_TYPE_IPV4,
 841         RTE_FLOW_ITEM_TYPE_TCP,
 842         RTE_FLOW_ITEM_TYPE_VF,
 843         RTE_FLOW_ITEM_TYPE_END,
 844 };
 845
 846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 847         RTE_FLOW_ITEM_TYPE_ETH,
 848         RTE_FLOW_ITEM_TYPE_IPV4,
 849         RTE_FLOW_ITEM_TYPE_SCTP,
 850         RTE_FLOW_ITEM_TYPE_VF,
 851         RTE_FLOW_ITEM_TYPE_END,
 852 };
 853
 854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 855         RTE_FLOW_ITEM_TYPE_ETH,
 856         RTE_FLOW_ITEM_TYPE_IPV6,
 857         RTE_FLOW_ITEM_TYPE_VF,
 858         RTE_FLOW_ITEM_TYPE_END,
 859 };
 860
 861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 862         RTE_FLOW_ITEM_TYPE_ETH,
 863         RTE_FLOW_ITEM_TYPE_IPV6,
 864         RTE_FLOW_ITEM_TYPE_UDP,
 865         RTE_FLOW_ITEM_TYPE_VF,
 866         RTE_FLOW_ITEM_TYPE_END,
 867 };
 868
 869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 870         RTE_FLOW_ITEM_TYPE_ETH,
 871         RTE_FLOW_ITEM_TYPE_IPV6,
 872         RTE_FLOW_ITEM_TYPE_TCP,
 873         RTE_FLOW_ITEM_TYPE_VF,
 874         RTE_FLOW_ITEM_TYPE_END,
 875 };
 876
 877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 878         RTE_FLOW_ITEM_TYPE_ETH,
 879         RTE_FLOW_ITEM_TYPE_IPV6,
 880         RTE_FLOW_ITEM_TYPE_SCTP,
 881         RTE_FLOW_ITEM_TYPE_VF,
 882         RTE_FLOW_ITEM_TYPE_END,
 883 };
 884
 885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 886         RTE_FLOW_ITEM_TYPE_ETH,
 887         RTE_FLOW_ITEM_TYPE_RAW,
 888         RTE_FLOW_ITEM_TYPE_VF,
 889         RTE_FLOW_ITEM_TYPE_END,
 890 };
 891
 892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 893         RTE_FLOW_ITEM_TYPE_ETH,
 894         RTE_FLOW_ITEM_TYPE_RAW,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_VF,
 897         RTE_FLOW_ITEM_TYPE_END,
 898 };
 899
 900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 901         RTE_FLOW_ITEM_TYPE_ETH,
 902         RTE_FLOW_ITEM_TYPE_RAW,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_VF,
 906         RTE_FLOW_ITEM_TYPE_END,
 907 };
 908
 909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 910         RTE_FLOW_ITEM_TYPE_ETH,
 911         RTE_FLOW_ITEM_TYPE_IPV4,
 912         RTE_FLOW_ITEM_TYPE_RAW,
 913         RTE_FLOW_ITEM_TYPE_VF,
 914         RTE_FLOW_ITEM_TYPE_END,
 915 };
 916
 917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 918         RTE_FLOW_ITEM_TYPE_ETH,
 919         RTE_FLOW_ITEM_TYPE_IPV4,
 920         RTE_FLOW_ITEM_TYPE_RAW,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_VF,
 923         RTE_FLOW_ITEM_TYPE_END,
 924 };
 925
 926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 927         RTE_FLOW_ITEM_TYPE_ETH,
 928         RTE_FLOW_ITEM_TYPE_IPV4,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_VF,
 933         RTE_FLOW_ITEM_TYPE_END,
 934 };
 935
 936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 937         RTE_FLOW_ITEM_TYPE_ETH,
 938         RTE_FLOW_ITEM_TYPE_IPV4,
 939         RTE_FLOW_ITEM_TYPE_UDP,
 940         RTE_FLOW_ITEM_TYPE_RAW,
 941         RTE_FLOW_ITEM_TYPE_VF,
 942         RTE_FLOW_ITEM_TYPE_END,
 943 };
 944
 945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 946         RTE_FLOW_ITEM_TYPE_ETH,
 947         RTE_FLOW_ITEM_TYPE_IPV4,
 948         RTE_FLOW_ITEM_TYPE_UDP,
 949         RTE_FLOW_ITEM_TYPE_RAW,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_VF,
 952         RTE_FLOW_ITEM_TYPE_END,
 953 };
 954
 955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 956         RTE_FLOW_ITEM_TYPE_ETH,
 957         RTE_FLOW_ITEM_TYPE_IPV4,
 958         RTE_FLOW_ITEM_TYPE_UDP,
 959         RTE_FLOW_ITEM_TYPE_RAW,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_VF,
 963         RTE_FLOW_ITEM_TYPE_END,
 964 };
 965
 966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 967         RTE_FLOW_ITEM_TYPE_ETH,
 968         RTE_FLOW_ITEM_TYPE_IPV4,
 969         RTE_FLOW_ITEM_TYPE_TCP,
 970         RTE_FLOW_ITEM_TYPE_RAW,
 971         RTE_FLOW_ITEM_TYPE_VF,
 972         RTE_FLOW_ITEM_TYPE_END,
 973 };
 974
 975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 976         RTE_FLOW_ITEM_TYPE_ETH,
 977         RTE_FLOW_ITEM_TYPE_IPV4,
 978         RTE_FLOW_ITEM_TYPE_TCP,
 979         RTE_FLOW_ITEM_TYPE_RAW,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_VF,
 982         RTE_FLOW_ITEM_TYPE_END,
 983 };
 984
 985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 986         RTE_FLOW_ITEM_TYPE_ETH,
 987         RTE_FLOW_ITEM_TYPE_IPV4,
 988         RTE_FLOW_ITEM_TYPE_TCP,
 989         RTE_FLOW_ITEM_TYPE_RAW,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_VF,
 993         RTE_FLOW_ITEM_TYPE_END,
 994 };
 995
 996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 997         RTE_FLOW_ITEM_TYPE_ETH,
 998         RTE_FLOW_ITEM_TYPE_IPV4,
 999         RTE_FLOW_ITEM_TYPE_SCTP,
1000         RTE_FLOW_ITEM_TYPE_RAW,
1001         RTE_FLOW_ITEM_TYPE_VF,
1002         RTE_FLOW_ITEM_TYPE_END,
1003 };
1004
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006         RTE_FLOW_ITEM_TYPE_ETH,
1007         RTE_FLOW_ITEM_TYPE_IPV4,
1008         RTE_FLOW_ITEM_TYPE_SCTP,
1009         RTE_FLOW_ITEM_TYPE_RAW,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_VF,
1012         RTE_FLOW_ITEM_TYPE_END,
1013 };
1014
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016         RTE_FLOW_ITEM_TYPE_ETH,
1017         RTE_FLOW_ITEM_TYPE_IPV4,
1018         RTE_FLOW_ITEM_TYPE_SCTP,
1019         RTE_FLOW_ITEM_TYPE_RAW,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_VF,
1023         RTE_FLOW_ITEM_TYPE_END,
1024 };
1025
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027         RTE_FLOW_ITEM_TYPE_ETH,
1028         RTE_FLOW_ITEM_TYPE_IPV6,
1029         RTE_FLOW_ITEM_TYPE_RAW,
1030         RTE_FLOW_ITEM_TYPE_VF,
1031         RTE_FLOW_ITEM_TYPE_END,
1032 };
1033
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035         RTE_FLOW_ITEM_TYPE_ETH,
1036         RTE_FLOW_ITEM_TYPE_IPV6,
1037         RTE_FLOW_ITEM_TYPE_RAW,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_VF,
1040         RTE_FLOW_ITEM_TYPE_END,
1041 };
1042
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044         RTE_FLOW_ITEM_TYPE_ETH,
1045         RTE_FLOW_ITEM_TYPE_IPV6,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_VF,
1050         RTE_FLOW_ITEM_TYPE_END,
1051 };
1052
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054         RTE_FLOW_ITEM_TYPE_ETH,
1055         RTE_FLOW_ITEM_TYPE_IPV6,
1056         RTE_FLOW_ITEM_TYPE_UDP,
1057         RTE_FLOW_ITEM_TYPE_RAW,
1058         RTE_FLOW_ITEM_TYPE_VF,
1059         RTE_FLOW_ITEM_TYPE_END,
1060 };
1061
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063         RTE_FLOW_ITEM_TYPE_ETH,
1064         RTE_FLOW_ITEM_TYPE_IPV6,
1065         RTE_FLOW_ITEM_TYPE_UDP,
1066         RTE_FLOW_ITEM_TYPE_RAW,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_VF,
1069         RTE_FLOW_ITEM_TYPE_END,
1070 };
1071
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073         RTE_FLOW_ITEM_TYPE_ETH,
1074         RTE_FLOW_ITEM_TYPE_IPV6,
1075         RTE_FLOW_ITEM_TYPE_UDP,
1076         RTE_FLOW_ITEM_TYPE_RAW,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_VF,
1080         RTE_FLOW_ITEM_TYPE_END,
1081 };
1082
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084         RTE_FLOW_ITEM_TYPE_ETH,
1085         RTE_FLOW_ITEM_TYPE_IPV6,
1086         RTE_FLOW_ITEM_TYPE_TCP,
1087         RTE_FLOW_ITEM_TYPE_RAW,
1088         RTE_FLOW_ITEM_TYPE_VF,
1089         RTE_FLOW_ITEM_TYPE_END,
1090 };
1091
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093         RTE_FLOW_ITEM_TYPE_ETH,
1094         RTE_FLOW_ITEM_TYPE_IPV6,
1095         RTE_FLOW_ITEM_TYPE_TCP,
1096         RTE_FLOW_ITEM_TYPE_RAW,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_VF,
1099         RTE_FLOW_ITEM_TYPE_END,
1100 };
1101
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103         RTE_FLOW_ITEM_TYPE_ETH,
1104         RTE_FLOW_ITEM_TYPE_IPV6,
1105         RTE_FLOW_ITEM_TYPE_TCP,
1106         RTE_FLOW_ITEM_TYPE_RAW,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_VF,
1110         RTE_FLOW_ITEM_TYPE_END,
1111 };
1112
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114         RTE_FLOW_ITEM_TYPE_ETH,
1115         RTE_FLOW_ITEM_TYPE_IPV6,
1116         RTE_FLOW_ITEM_TYPE_SCTP,
1117         RTE_FLOW_ITEM_TYPE_RAW,
1118         RTE_FLOW_ITEM_TYPE_VF,
1119         RTE_FLOW_ITEM_TYPE_END,
1120 };
1121
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123         RTE_FLOW_ITEM_TYPE_ETH,
1124         RTE_FLOW_ITEM_TYPE_IPV6,
1125         RTE_FLOW_ITEM_TYPE_SCTP,
1126         RTE_FLOW_ITEM_TYPE_RAW,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_VF,
1129         RTE_FLOW_ITEM_TYPE_END,
1130 };
1131
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133         RTE_FLOW_ITEM_TYPE_ETH,
1134         RTE_FLOW_ITEM_TYPE_IPV6,
1135         RTE_FLOW_ITEM_TYPE_SCTP,
1136         RTE_FLOW_ITEM_TYPE_RAW,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_VF,
1140         RTE_FLOW_ITEM_TYPE_END,
1141 };
1142
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144         RTE_FLOW_ITEM_TYPE_ETH,
1145         RTE_FLOW_ITEM_TYPE_VLAN,
1146         RTE_FLOW_ITEM_TYPE_VF,
1147         RTE_FLOW_ITEM_TYPE_END,
1148 };
1149
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151         RTE_FLOW_ITEM_TYPE_ETH,
1152         RTE_FLOW_ITEM_TYPE_VLAN,
1153         RTE_FLOW_ITEM_TYPE_IPV4,
1154         RTE_FLOW_ITEM_TYPE_VF,
1155         RTE_FLOW_ITEM_TYPE_END,
1156 };
1157
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159         RTE_FLOW_ITEM_TYPE_ETH,
1160         RTE_FLOW_ITEM_TYPE_VLAN,
1161         RTE_FLOW_ITEM_TYPE_IPV4,
1162         RTE_FLOW_ITEM_TYPE_UDP,
1163         RTE_FLOW_ITEM_TYPE_VF,
1164         RTE_FLOW_ITEM_TYPE_END,
1165 };
1166
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168         RTE_FLOW_ITEM_TYPE_ETH,
1169         RTE_FLOW_ITEM_TYPE_VLAN,
1170         RTE_FLOW_ITEM_TYPE_IPV4,
1171         RTE_FLOW_ITEM_TYPE_TCP,
1172         RTE_FLOW_ITEM_TYPE_VF,
1173         RTE_FLOW_ITEM_TYPE_END,
1174 };
1175
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177         RTE_FLOW_ITEM_TYPE_ETH,
1178         RTE_FLOW_ITEM_TYPE_VLAN,
1179         RTE_FLOW_ITEM_TYPE_IPV4,
1180         RTE_FLOW_ITEM_TYPE_SCTP,
1181         RTE_FLOW_ITEM_TYPE_VF,
1182         RTE_FLOW_ITEM_TYPE_END,
1183 };
1184
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186         RTE_FLOW_ITEM_TYPE_ETH,
1187         RTE_FLOW_ITEM_TYPE_VLAN,
1188         RTE_FLOW_ITEM_TYPE_IPV6,
1189         RTE_FLOW_ITEM_TYPE_VF,
1190         RTE_FLOW_ITEM_TYPE_END,
1191 };
1192
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194         RTE_FLOW_ITEM_TYPE_ETH,
1195         RTE_FLOW_ITEM_TYPE_VLAN,
1196         RTE_FLOW_ITEM_TYPE_IPV6,
1197         RTE_FLOW_ITEM_TYPE_UDP,
1198         RTE_FLOW_ITEM_TYPE_VF,
1199         RTE_FLOW_ITEM_TYPE_END,
1200 };
1201
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203         RTE_FLOW_ITEM_TYPE_ETH,
1204         RTE_FLOW_ITEM_TYPE_VLAN,
1205         RTE_FLOW_ITEM_TYPE_IPV6,
1206         RTE_FLOW_ITEM_TYPE_TCP,
1207         RTE_FLOW_ITEM_TYPE_VF,
1208         RTE_FLOW_ITEM_TYPE_END,
1209 };
1210
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212         RTE_FLOW_ITEM_TYPE_ETH,
1213         RTE_FLOW_ITEM_TYPE_VLAN,
1214         RTE_FLOW_ITEM_TYPE_IPV6,
1215         RTE_FLOW_ITEM_TYPE_SCTP,
1216         RTE_FLOW_ITEM_TYPE_VF,
1217         RTE_FLOW_ITEM_TYPE_END,
1218 };
1219
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221         RTE_FLOW_ITEM_TYPE_ETH,
1222         RTE_FLOW_ITEM_TYPE_VLAN,
1223         RTE_FLOW_ITEM_TYPE_RAW,
1224         RTE_FLOW_ITEM_TYPE_VF,
1225         RTE_FLOW_ITEM_TYPE_END,
1226 };
1227
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229         RTE_FLOW_ITEM_TYPE_ETH,
1230         RTE_FLOW_ITEM_TYPE_VLAN,
1231         RTE_FLOW_ITEM_TYPE_RAW,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_VF,
1234         RTE_FLOW_ITEM_TYPE_END,
1235 };
1236
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238         RTE_FLOW_ITEM_TYPE_ETH,
1239         RTE_FLOW_ITEM_TYPE_VLAN,
1240         RTE_FLOW_ITEM_TYPE_RAW,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_VF,
1244         RTE_FLOW_ITEM_TYPE_END,
1245 };
1246
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248         RTE_FLOW_ITEM_TYPE_ETH,
1249         RTE_FLOW_ITEM_TYPE_VLAN,
1250         RTE_FLOW_ITEM_TYPE_IPV4,
1251         RTE_FLOW_ITEM_TYPE_RAW,
1252         RTE_FLOW_ITEM_TYPE_VF,
1253         RTE_FLOW_ITEM_TYPE_END,
1254 };
1255
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257         RTE_FLOW_ITEM_TYPE_ETH,
1258         RTE_FLOW_ITEM_TYPE_VLAN,
1259         RTE_FLOW_ITEM_TYPE_IPV4,
1260         RTE_FLOW_ITEM_TYPE_RAW,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_VF,
1263         RTE_FLOW_ITEM_TYPE_END,
1264 };
1265
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267         RTE_FLOW_ITEM_TYPE_ETH,
1268         RTE_FLOW_ITEM_TYPE_VLAN,
1269         RTE_FLOW_ITEM_TYPE_IPV4,
1270         RTE_FLOW_ITEM_TYPE_RAW,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_VF,
1274         RTE_FLOW_ITEM_TYPE_END,
1275 };
1276
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278         RTE_FLOW_ITEM_TYPE_ETH,
1279         RTE_FLOW_ITEM_TYPE_VLAN,
1280         RTE_FLOW_ITEM_TYPE_IPV4,
1281         RTE_FLOW_ITEM_TYPE_UDP,
1282         RTE_FLOW_ITEM_TYPE_RAW,
1283         RTE_FLOW_ITEM_TYPE_VF,
1284         RTE_FLOW_ITEM_TYPE_END,
1285 };
1286
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288         RTE_FLOW_ITEM_TYPE_ETH,
1289         RTE_FLOW_ITEM_TYPE_VLAN,
1290         RTE_FLOW_ITEM_TYPE_IPV4,
1291         RTE_FLOW_ITEM_TYPE_UDP,
1292         RTE_FLOW_ITEM_TYPE_RAW,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_VF,
1295         RTE_FLOW_ITEM_TYPE_END,
1296 };
1297
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299         RTE_FLOW_ITEM_TYPE_ETH,
1300         RTE_FLOW_ITEM_TYPE_VLAN,
1301         RTE_FLOW_ITEM_TYPE_IPV4,
1302         RTE_FLOW_ITEM_TYPE_UDP,
1303         RTE_FLOW_ITEM_TYPE_RAW,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_VF,
1307         RTE_FLOW_ITEM_TYPE_END,
1308 };
1309
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311         RTE_FLOW_ITEM_TYPE_ETH,
1312         RTE_FLOW_ITEM_TYPE_VLAN,
1313         RTE_FLOW_ITEM_TYPE_IPV4,
1314         RTE_FLOW_ITEM_TYPE_TCP,
1315         RTE_FLOW_ITEM_TYPE_RAW,
1316         RTE_FLOW_ITEM_TYPE_VF,
1317         RTE_FLOW_ITEM_TYPE_END,
1318 };
1319
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321         RTE_FLOW_ITEM_TYPE_ETH,
1322         RTE_FLOW_ITEM_TYPE_VLAN,
1323         RTE_FLOW_ITEM_TYPE_IPV4,
1324         RTE_FLOW_ITEM_TYPE_TCP,
1325         RTE_FLOW_ITEM_TYPE_RAW,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_VF,
1328         RTE_FLOW_ITEM_TYPE_END,
1329 };
1330
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332         RTE_FLOW_ITEM_TYPE_ETH,
1333         RTE_FLOW_ITEM_TYPE_VLAN,
1334         RTE_FLOW_ITEM_TYPE_IPV4,
1335         RTE_FLOW_ITEM_TYPE_TCP,
1336         RTE_FLOW_ITEM_TYPE_RAW,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_VF,
1340         RTE_FLOW_ITEM_TYPE_END,
1341 };
1342
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344         RTE_FLOW_ITEM_TYPE_ETH,
1345         RTE_FLOW_ITEM_TYPE_VLAN,
1346         RTE_FLOW_ITEM_TYPE_IPV4,
1347         RTE_FLOW_ITEM_TYPE_SCTP,
1348         RTE_FLOW_ITEM_TYPE_RAW,
1349         RTE_FLOW_ITEM_TYPE_VF,
1350         RTE_FLOW_ITEM_TYPE_END,
1351 };
1352
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354         RTE_FLOW_ITEM_TYPE_ETH,
1355         RTE_FLOW_ITEM_TYPE_VLAN,
1356         RTE_FLOW_ITEM_TYPE_IPV4,
1357         RTE_FLOW_ITEM_TYPE_SCTP,
1358         RTE_FLOW_ITEM_TYPE_RAW,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_VF,
1361         RTE_FLOW_ITEM_TYPE_END,
1362 };
1363
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365         RTE_FLOW_ITEM_TYPE_ETH,
1366         RTE_FLOW_ITEM_TYPE_VLAN,
1367         RTE_FLOW_ITEM_TYPE_IPV4,
1368         RTE_FLOW_ITEM_TYPE_SCTP,
1369         RTE_FLOW_ITEM_TYPE_RAW,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_VF,
1373         RTE_FLOW_ITEM_TYPE_END,
1374 };
1375
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377         RTE_FLOW_ITEM_TYPE_ETH,
1378         RTE_FLOW_ITEM_TYPE_VLAN,
1379         RTE_FLOW_ITEM_TYPE_IPV6,
1380         RTE_FLOW_ITEM_TYPE_RAW,
1381         RTE_FLOW_ITEM_TYPE_VF,
1382         RTE_FLOW_ITEM_TYPE_END,
1383 };
1384
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386         RTE_FLOW_ITEM_TYPE_ETH,
1387         RTE_FLOW_ITEM_TYPE_VLAN,
1388         RTE_FLOW_ITEM_TYPE_IPV6,
1389         RTE_FLOW_ITEM_TYPE_RAW,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_VF,
1392         RTE_FLOW_ITEM_TYPE_END,
1393 };
1394
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396         RTE_FLOW_ITEM_TYPE_ETH,
1397         RTE_FLOW_ITEM_TYPE_VLAN,
1398         RTE_FLOW_ITEM_TYPE_IPV6,
1399         RTE_FLOW_ITEM_TYPE_RAW,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_VF,
1403         RTE_FLOW_ITEM_TYPE_END,
1404 };
1405
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407         RTE_FLOW_ITEM_TYPE_ETH,
1408         RTE_FLOW_ITEM_TYPE_VLAN,
1409         RTE_FLOW_ITEM_TYPE_IPV6,
1410         RTE_FLOW_ITEM_TYPE_UDP,
1411         RTE_FLOW_ITEM_TYPE_RAW,
1412         RTE_FLOW_ITEM_TYPE_VF,
1413         RTE_FLOW_ITEM_TYPE_END,
1414 };
1415
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417         RTE_FLOW_ITEM_TYPE_ETH,
1418         RTE_FLOW_ITEM_TYPE_VLAN,
1419         RTE_FLOW_ITEM_TYPE_IPV6,
1420         RTE_FLOW_ITEM_TYPE_UDP,
1421         RTE_FLOW_ITEM_TYPE_RAW,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_VF,
1424         RTE_FLOW_ITEM_TYPE_END,
1425 };
1426
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428         RTE_FLOW_ITEM_TYPE_ETH,
1429         RTE_FLOW_ITEM_TYPE_VLAN,
1430         RTE_FLOW_ITEM_TYPE_IPV6,
1431         RTE_FLOW_ITEM_TYPE_UDP,
1432         RTE_FLOW_ITEM_TYPE_RAW,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_VF,
1436         RTE_FLOW_ITEM_TYPE_END,
1437 };
1438
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440         RTE_FLOW_ITEM_TYPE_ETH,
1441         RTE_FLOW_ITEM_TYPE_VLAN,
1442         RTE_FLOW_ITEM_TYPE_IPV6,
1443         RTE_FLOW_ITEM_TYPE_TCP,
1444         RTE_FLOW_ITEM_TYPE_RAW,
1445         RTE_FLOW_ITEM_TYPE_VF,
1446         RTE_FLOW_ITEM_TYPE_END,
1447 };
1448
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450         RTE_FLOW_ITEM_TYPE_ETH,
1451         RTE_FLOW_ITEM_TYPE_VLAN,
1452         RTE_FLOW_ITEM_TYPE_IPV6,
1453         RTE_FLOW_ITEM_TYPE_TCP,
1454         RTE_FLOW_ITEM_TYPE_RAW,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_VF,
1457         RTE_FLOW_ITEM_TYPE_END,
1458 };
1459
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461         RTE_FLOW_ITEM_TYPE_ETH,
1462         RTE_FLOW_ITEM_TYPE_VLAN,
1463         RTE_FLOW_ITEM_TYPE_IPV6,
1464         RTE_FLOW_ITEM_TYPE_TCP,
1465         RTE_FLOW_ITEM_TYPE_RAW,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_VF,
1469         RTE_FLOW_ITEM_TYPE_END,
1470 };
1471
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473         RTE_FLOW_ITEM_TYPE_ETH,
1474         RTE_FLOW_ITEM_TYPE_VLAN,
1475         RTE_FLOW_ITEM_TYPE_IPV6,
1476         RTE_FLOW_ITEM_TYPE_SCTP,
1477         RTE_FLOW_ITEM_TYPE_RAW,
1478         RTE_FLOW_ITEM_TYPE_VF,
1479         RTE_FLOW_ITEM_TYPE_END,
1480 };
1481
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483         RTE_FLOW_ITEM_TYPE_ETH,
1484         RTE_FLOW_ITEM_TYPE_VLAN,
1485         RTE_FLOW_ITEM_TYPE_IPV6,
1486         RTE_FLOW_ITEM_TYPE_SCTP,
1487         RTE_FLOW_ITEM_TYPE_RAW,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_VF,
1490         RTE_FLOW_ITEM_TYPE_END,
1491 };
1492
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494         RTE_FLOW_ITEM_TYPE_ETH,
1495         RTE_FLOW_ITEM_TYPE_VLAN,
1496         RTE_FLOW_ITEM_TYPE_IPV6,
1497         RTE_FLOW_ITEM_TYPE_SCTP,
1498         RTE_FLOW_ITEM_TYPE_RAW,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_VF,
1502         RTE_FLOW_ITEM_TYPE_END,
1503 };
1504
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507         RTE_FLOW_ITEM_TYPE_ETH,
1508         RTE_FLOW_ITEM_TYPE_IPV4,
1509         RTE_FLOW_ITEM_TYPE_UDP,
1510         RTE_FLOW_ITEM_TYPE_VXLAN,
1511         RTE_FLOW_ITEM_TYPE_ETH,
1512         RTE_FLOW_ITEM_TYPE_END,
1513 };
1514
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516         RTE_FLOW_ITEM_TYPE_ETH,
1517         RTE_FLOW_ITEM_TYPE_IPV6,
1518         RTE_FLOW_ITEM_TYPE_UDP,
1519         RTE_FLOW_ITEM_TYPE_VXLAN,
1520         RTE_FLOW_ITEM_TYPE_ETH,
1521         RTE_FLOW_ITEM_TYPE_END,
1522 };
1523
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525         RTE_FLOW_ITEM_TYPE_ETH,
1526         RTE_FLOW_ITEM_TYPE_IPV4,
1527         RTE_FLOW_ITEM_TYPE_UDP,
1528         RTE_FLOW_ITEM_TYPE_VXLAN,
1529         RTE_FLOW_ITEM_TYPE_ETH,
1530         RTE_FLOW_ITEM_TYPE_VLAN,
1531         RTE_FLOW_ITEM_TYPE_END,
1532 };
1533
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535         RTE_FLOW_ITEM_TYPE_ETH,
1536         RTE_FLOW_ITEM_TYPE_IPV6,
1537         RTE_FLOW_ITEM_TYPE_UDP,
1538         RTE_FLOW_ITEM_TYPE_VXLAN,
1539         RTE_FLOW_ITEM_TYPE_ETH,
1540         RTE_FLOW_ITEM_TYPE_VLAN,
1541         RTE_FLOW_ITEM_TYPE_END,
1542 };
1543
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545         RTE_FLOW_ITEM_TYPE_ETH,
1546         RTE_FLOW_ITEM_TYPE_IPV4,
1547         RTE_FLOW_ITEM_TYPE_NVGRE,
1548         RTE_FLOW_ITEM_TYPE_ETH,
1549         RTE_FLOW_ITEM_TYPE_END,
1550 };
1551
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553         RTE_FLOW_ITEM_TYPE_ETH,
1554         RTE_FLOW_ITEM_TYPE_IPV6,
1555         RTE_FLOW_ITEM_TYPE_NVGRE,
1556         RTE_FLOW_ITEM_TYPE_ETH,
1557         RTE_FLOW_ITEM_TYPE_END,
1558 };
1559
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561         RTE_FLOW_ITEM_TYPE_ETH,
1562         RTE_FLOW_ITEM_TYPE_IPV4,
1563         RTE_FLOW_ITEM_TYPE_NVGRE,
1564         RTE_FLOW_ITEM_TYPE_ETH,
1565         RTE_FLOW_ITEM_TYPE_VLAN,
1566         RTE_FLOW_ITEM_TYPE_END,
1567 };
1568
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570         RTE_FLOW_ITEM_TYPE_ETH,
1571         RTE_FLOW_ITEM_TYPE_IPV6,
1572         RTE_FLOW_ITEM_TYPE_NVGRE,
1573         RTE_FLOW_ITEM_TYPE_ETH,
1574         RTE_FLOW_ITEM_TYPE_VLAN,
1575         RTE_FLOW_ITEM_TYPE_END,
1576 };
1577
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579         RTE_FLOW_ITEM_TYPE_ETH,
1580         RTE_FLOW_ITEM_TYPE_IPV4,
1581         RTE_FLOW_ITEM_TYPE_UDP,
1582         RTE_FLOW_ITEM_TYPE_MPLS,
1583         RTE_FLOW_ITEM_TYPE_END,
1584 };
1585
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587         RTE_FLOW_ITEM_TYPE_ETH,
1588         RTE_FLOW_ITEM_TYPE_IPV6,
1589         RTE_FLOW_ITEM_TYPE_UDP,
1590         RTE_FLOW_ITEM_TYPE_MPLS,
1591         RTE_FLOW_ITEM_TYPE_END,
1592 };
1593
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595         RTE_FLOW_ITEM_TYPE_ETH,
1596         RTE_FLOW_ITEM_TYPE_IPV4,
1597         RTE_FLOW_ITEM_TYPE_GRE,
1598         RTE_FLOW_ITEM_TYPE_MPLS,
1599         RTE_FLOW_ITEM_TYPE_END,
1600 };
1601
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603         RTE_FLOW_ITEM_TYPE_ETH,
1604         RTE_FLOW_ITEM_TYPE_IPV6,
1605         RTE_FLOW_ITEM_TYPE_GRE,
1606         RTE_FLOW_ITEM_TYPE_MPLS,
1607         RTE_FLOW_ITEM_TYPE_END,
1608 };
1609
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611         RTE_FLOW_ITEM_TYPE_ETH,
1612         RTE_FLOW_ITEM_TYPE_VLAN,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_END,
1615 };
1616
1617 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1618         /* Ethertype */
1619         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1620         /* FDIR - support default flow type without flexible payload*/
1621         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1622         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1638         /* FDIR - support default flow type with flexible payload */
1639         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1640         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1666         /* FDIR - support single vlan input set */
1667         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1668         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1703         /* FDIR - support VF item */
1704         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1775         /* VXLAN */
1776         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1777         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1778         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1780         /* NVGRE */
1781         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1782         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1783         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1785         /* MPLSoUDP & MPLSoGRE */
1786         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1787         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1788         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1790         /* GTP-C & GTP-U */
1791         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1792         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1793         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1795         /* QINQ */
1796         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1797 };
1798
1799 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1800         do {                                                            \
1801                 act = actions + index;                                  \
1802                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1803                         index++;                                        \
1804                         act = actions + index;                          \
1805                 }                                                       \
1806         } while (0)
1807
1808 /* Find the first VOID or non-VOID item pointer */
1809 static const struct rte_flow_item *
1810 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1811 {
1812         bool is_find;
1813
1814         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1815                 if (is_void)
1816                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1817                 else
1818                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1819                 if (is_find)
1820                         break;
1821                 item++;
1822         }
1823         return item;
1824 }
1825
1826 /* Skip all VOID items of the pattern */
1827 static void
1828 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1829                             const struct rte_flow_item *pattern)
1830 {
1831         uint32_t cpy_count = 0;
1832         const struct rte_flow_item *pb = pattern, *pe = pattern;
1833
1834         for (;;) {
1835                 /* Find a non-void item first */
1836                 pb = i40e_find_first_item(pb, false);
1837                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1838                         pe = pb;
1839                         break;
1840                 }
1841
1842                 /* Find a void item */
1843                 pe = i40e_find_first_item(pb + 1, true);
1844
1845                 cpy_count = pe - pb;
1846                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1847
1848                 items += cpy_count;
1849
1850                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1851                         pb = pe;
1852                         break;
1853                 }
1854
1855                 pb = pe + 1;
1856         }
1857         /* Copy the END item. */
1858         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1859 }
1860
1861 /* Check if the pattern matches a supported item type array */
1862 static bool
1863 i40e_match_pattern(enum rte_flow_item_type *item_array,
1864                    struct rte_flow_item *pattern)
1865 {
1866         struct rte_flow_item *item = pattern;
1867
1868         while ((*item_array == item->type) &&
1869                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1870                 item_array++;
1871                 item++;
1872         }
1873
1874         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1875                 item->type == RTE_FLOW_ITEM_TYPE_END);
1876 }
1877
1878 /* Find if there's parse filter function matched */
1879 static parse_filter_t
1880 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1881 {
1882         parse_filter_t parse_filter = NULL;
1883         uint8_t i = *idx;
1884
1885         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1886                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1887                                         pattern)) {
1888                         parse_filter = i40e_supported_patterns[i].parse_filter;
1889                         break;
1890                 }
1891         }
1892
1893         *idx = ++i;
1894
1895         return parse_filter;
1896 }
1897
1898 /* Parse attributes */
1899 static int
1900 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1901                      struct rte_flow_error *error)
1902 {
1903         /* Must be input direction */
1904         if (!attr->ingress) {
1905                 rte_flow_error_set(error, EINVAL,
1906                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1907                                    attr, "Only support ingress.");
1908                 return -rte_errno;
1909         }
1910
1911         /* Not supported */
1912         if (attr->egress) {
1913                 rte_flow_error_set(error, EINVAL,
1914                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1915                                    attr, "Not support egress.");
1916                 return -rte_errno;
1917         }
1918
1919         /* Not supported */
1920         if (attr->priority) {
1921                 rte_flow_error_set(error, EINVAL,
1922                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1923                                    attr, "Not support priority.");
1924                 return -rte_errno;
1925         }
1926
1927         /* Not supported */
1928         if (attr->group) {
1929                 rte_flow_error_set(error, EINVAL,
1930                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1931                                    attr, "Not support group.");
1932                 return -rte_errno;
1933         }
1934
1935         return 0;
1936 }
1937
1938 static uint16_t
1939 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1940 {
1941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1943         uint64_t reg_r = 0;
1944         uint16_t reg_id;
1945         uint16_t tpid;
1946
1947         if (qinq)
1948                 reg_id = 2;
1949         else
1950                 reg_id = 3;
1951
1952         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1953                                     &reg_r, NULL);
1954
1955         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1956
1957         return tpid;
1958 }
1959
1960 /* 1. Last in item should be NULL as range is not supported.
1961  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1962  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1963  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1964  *    FF:FF:FF:FF:FF:FF
1965  * 5. Ether_type mask should be 0xFFFF.
1966  */
1967 static int
1968 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1969                                   const struct rte_flow_item *pattern,
1970                                   struct rte_flow_error *error,
1971                                   struct rte_eth_ethertype_filter *filter)
1972 {
1973         const struct rte_flow_item *item = pattern;
1974         const struct rte_flow_item_eth *eth_spec;
1975         const struct rte_flow_item_eth *eth_mask;
1976         enum rte_flow_item_type item_type;
1977         uint16_t outer_tpid;
1978
1979         outer_tpid = i40e_get_outer_vlan(dev);
1980
1981         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1982                 if (item->last) {
1983                         rte_flow_error_set(error, EINVAL,
1984                                            RTE_FLOW_ERROR_TYPE_ITEM,
1985                                            item,
1986                                            "Not support range");
1987                         return -rte_errno;
1988                 }
1989                 item_type = item->type;
1990                 switch (item_type) {
1991                 case RTE_FLOW_ITEM_TYPE_ETH:
1992                         eth_spec = item->spec;
1993                         eth_mask = item->mask;
1994                         /* Get the MAC info. */
1995                         if (!eth_spec || !eth_mask) {
1996                                 rte_flow_error_set(error, EINVAL,
1997                                                    RTE_FLOW_ERROR_TYPE_ITEM,
1998                                                    item,
1999                                                    "NULL ETH spec/mask");
2000                                 return -rte_errno;
2001                         }
2002
2003                         /* Mask bits of source MAC address must be full of 0.
2004                          * Mask bits of destination MAC address must be full
2005                          * of 1 or full of 0.
2006                          */
2007                         if (!is_zero_ether_addr(&eth_mask->src) ||
2008                             (!is_zero_ether_addr(&eth_mask->dst) &&
2009                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2010                                 rte_flow_error_set(error, EINVAL,
2011                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2012                                                    item,
2013                                                    "Invalid MAC_addr mask");
2014                                 return -rte_errno;
2015                         }
2016
2017                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2018                                 rte_flow_error_set(error, EINVAL,
2019                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2020                                                    item,
2021                                                    "Invalid ethertype mask");
2022                                 return -rte_errno;
2023                         }
2024
2025                         /* If mask bits of destination MAC address
2026                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2027                          */
2028                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2029                                 filter->mac_addr = eth_spec->dst;
2030                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2031                         } else {
2032                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2033                         }
2034                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2035
2036                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2037                             filter->ether_type == ETHER_TYPE_IPv6 ||
2038                             filter->ether_type == ETHER_TYPE_LLDP ||
2039                             filter->ether_type == outer_tpid) {
2040                                 rte_flow_error_set(error, EINVAL,
2041                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2042                                                    item,
2043                                                    "Unsupported ether_type in"
2044                                                    " control packet filter.");
2045                                 return -rte_errno;
2046                         }
2047                         break;
2048                 default:
2049                         break;
2050                 }
2051         }
2052
2053         return 0;
2054 }
2055
2056 /* Ethertype action only supports QUEUE or DROP. */
2057 static int
2058 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2059                                  const struct rte_flow_action *actions,
2060                                  struct rte_flow_error *error,
2061                                  struct rte_eth_ethertype_filter *filter)
2062 {
2063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2064         const struct rte_flow_action *act;
2065         const struct rte_flow_action_queue *act_q;
2066         uint32_t index = 0;
2067
2068         /* Check if the first non-void action is QUEUE or DROP. */
2069         NEXT_ITEM_OF_ACTION(act, actions, index);
2070         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2071             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2072                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2073                                    act, "Not supported action.");
2074                 return -rte_errno;
2075         }
2076
2077         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2078                 act_q = act->conf;
2079                 filter->queue = act_q->index;
2080                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2081                         rte_flow_error_set(error, EINVAL,
2082                                            RTE_FLOW_ERROR_TYPE_ACTION,
2083                                            act, "Invalid queue ID for"
2084                                            " ethertype_filter.");
2085                         return -rte_errno;
2086                 }
2087         } else {
2088                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2089         }
2090
2091         /* Check if the next non-void item is END */
2092         index++;
2093         NEXT_ITEM_OF_ACTION(act, actions, index);
2094         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2095                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2096                                    act, "Not supported action.");
2097                 return -rte_errno;
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int
2104 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2105                                  const struct rte_flow_attr *attr,
2106                                  const struct rte_flow_item pattern[],
2107                                  const struct rte_flow_action actions[],
2108                                  struct rte_flow_error *error,
2109                                  union i40e_filter_t *filter)
2110 {
2111         struct rte_eth_ethertype_filter *ethertype_filter =
2112                 &filter->ethertype_filter;
2113         int ret;
2114
2115         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2116                                                 ethertype_filter);
2117         if (ret)
2118                 return ret;
2119
2120         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2121                                                ethertype_filter);
2122         if (ret)
2123                 return ret;
2124
2125         ret = i40e_flow_parse_attr(attr, error);
2126         if (ret)
2127                 return ret;
2128
2129         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2130
2131         return ret;
2132 }
2133
2134 static int
2135 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2136                          const struct rte_flow_item_raw *raw_spec,
2137                          struct rte_flow_error *error)
2138 {
2139         if (!raw_spec->relative) {
2140                 rte_flow_error_set(error, EINVAL,
2141                                    RTE_FLOW_ERROR_TYPE_ITEM,
2142                                    item,
2143                                    "Relative should be 1.");
2144                 return -rte_errno;
2145         }
2146
2147         if (raw_spec->offset % sizeof(uint16_t)) {
2148                 rte_flow_error_set(error, EINVAL,
2149                                    RTE_FLOW_ERROR_TYPE_ITEM,
2150                                    item,
2151                                    "Offset should be even.");
2152                 return -rte_errno;
2153         }
2154
2155         if (raw_spec->search || raw_spec->limit) {
2156                 rte_flow_error_set(error, EINVAL,
2157                                    RTE_FLOW_ERROR_TYPE_ITEM,
2158                                    item,
2159                                    "search or limit is not supported.");
2160                 return -rte_errno;
2161         }
2162
2163         if (raw_spec->offset < 0) {
2164                 rte_flow_error_set(error, EINVAL,
2165                                    RTE_FLOW_ERROR_TYPE_ITEM,
2166                                    item,
2167                                    "Offset should be non-negative.");
2168                 return -rte_errno;
2169         }
2170         return 0;
2171 }
2172
2173 static int
2174 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2175                          struct i40e_fdir_flex_pit *flex_pit,
2176                          enum i40e_flxpld_layer_idx layer_idx,
2177                          uint8_t raw_id)
2178 {
2179         uint8_t field_idx;
2180
2181         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2182         /* Check if the configuration is conflicted */
2183         if (pf->fdir.flex_pit_flag[layer_idx] &&
2184             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2185              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2186              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2187                 return -1;
2188
2189         /* Check if the configuration exists. */
2190         if (pf->fdir.flex_pit_flag[layer_idx] &&
2191             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2192              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2193              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2194                 return 1;
2195
2196         pf->fdir.flex_set[field_idx].src_offset =
2197                 flex_pit->src_offset;
2198         pf->fdir.flex_set[field_idx].size =
2199                 flex_pit->size;
2200         pf->fdir.flex_set[field_idx].dst_offset =
2201                 flex_pit->dst_offset;
2202
2203         return 0;
2204 }
2205
2206 static int
2207 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2208                           enum i40e_filter_pctype pctype,
2209                           uint8_t *mask)
2210 {
2211         struct i40e_fdir_flex_mask flex_mask;
2212         uint16_t mask_tmp;
2213         uint8_t i, nb_bitmask = 0;
2214
2215         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2216         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2217                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2218                 if (mask_tmp) {
2219                         flex_mask.word_mask |=
2220                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2221                         if (mask_tmp != UINT16_MAX) {
2222                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2223                                 flex_mask.bitmask[nb_bitmask].offset =
2224                                         i / sizeof(uint16_t);
2225                                 nb_bitmask++;
2226                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2227                                         return -1;
2228                         }
2229                 }
2230         }
2231         flex_mask.nb_bitmask = nb_bitmask;
2232
2233         if (pf->fdir.flex_mask_flag[pctype] &&
2234             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2235                     sizeof(struct i40e_fdir_flex_mask))))
2236                 return -2;
2237         else if (pf->fdir.flex_mask_flag[pctype] &&
2238                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2239                           sizeof(struct i40e_fdir_flex_mask))))
2240                 return 1;
2241
2242         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2243                sizeof(struct i40e_fdir_flex_mask));
2244         return 0;
2245 }
2246
2247 static void
2248 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2249                             enum i40e_flxpld_layer_idx layer_idx,
2250                             uint8_t raw_id)
2251 {
2252         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2253         uint32_t flx_pit, flx_ort;
2254         uint8_t field_idx;
2255         uint16_t min_next_off = 0;  /* in words */
2256         uint8_t i;
2257
2258         if (raw_id) {
2259                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2260                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2261                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2262                 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2263                 i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
2264         }
2265
2266         /* Set flex pit */
2267         for (i = 0; i < raw_id; i++) {
2268                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2269                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2270                                      pf->fdir.flex_set[field_idx].size,
2271                                      pf->fdir.flex_set[field_idx].dst_offset);
2272
2273                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2274                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2275                         pf->fdir.flex_set[field_idx].size;
2276         }
2277
2278         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2279                 /* set the non-used register obeying register's constrain */
2280                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2281                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2282                                      NONUSE_FLX_PIT_DEST_OFF);
2283                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2284                 min_next_off++;
2285         }
2286
2287         pf->fdir.flex_pit_flag[layer_idx] = 1;
2288 }
2289
2290 static void
2291 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2292                             enum i40e_filter_pctype pctype)
2293 {
2294         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2295         struct i40e_fdir_flex_mask *flex_mask;
2296         uint32_t flxinset, fd_mask;
2297         uint8_t i;
2298
2299         /* Set flex mask */
2300         flex_mask = &pf->fdir.flex_mask[pctype];
2301         flxinset = (flex_mask->word_mask <<
2302                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2303                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2304         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2305
2306         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2307                 fd_mask = (flex_mask->bitmask[i].mask <<
2308                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2309                         I40E_PRTQF_FD_MSK_MASK_MASK;
2310                 fd_mask |= ((flex_mask->bitmask[i].offset +
2311                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2312                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2313                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2314                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2315         }
2316
2317         pf->fdir.flex_mask_flag[pctype] = 1;
2318 }
2319
2320 static int
2321 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2322                          enum i40e_filter_pctype pctype,
2323                          uint64_t input_set)
2324 {
2325         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2326         uint64_t inset_reg = 0;
2327         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2328         int i, num;
2329
2330         /* Check if the input set is valid */
2331         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2332                                     input_set) != 0) {
2333                 PMD_DRV_LOG(ERR, "Invalid input set");
2334                 return -EINVAL;
2335         }
2336
2337         /* Check if the configuration is conflicted */
2338         if (pf->fdir.inset_flag[pctype] &&
2339             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2340                 return -1;
2341
2342         if (pf->fdir.inset_flag[pctype] &&
2343             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2344                 return 0;
2345
2346         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2347                                            I40E_INSET_MASK_NUM_REG);
2348         if (num < 0)
2349                 return -EINVAL;
2350
2351         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2352
2353         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2354                              (uint32_t)(inset_reg & UINT32_MAX));
2355         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2356                              (uint32_t)((inset_reg >>
2357                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2358
2359         for (i = 0; i < num; i++)
2360                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2361                                      mask_reg[i]);
2362
2363         /*clear unused mask registers of the pctype */
2364         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2365                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2366         I40E_WRITE_FLUSH(hw);
2367
2368         pf->fdir.input_set[pctype] = input_set;
2369         pf->fdir.inset_flag[pctype] = 1;
2370         return 0;
2371 }
2372
2373 static uint8_t
2374 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2375                                 enum rte_flow_item_type item_type,
2376                                 struct i40e_fdir_filter_conf *filter)
2377 {
2378         struct i40e_customized_pctype *cus_pctype = NULL;
2379
2380         switch (item_type) {
2381         case RTE_FLOW_ITEM_TYPE_GTPC:
2382                 cus_pctype = i40e_find_customized_pctype(pf,
2383                                                          I40E_CUSTOMIZED_GTPC);
2384                 break;
2385         case RTE_FLOW_ITEM_TYPE_GTPU:
2386                 if (!filter->input.flow_ext.inner_ip)
2387                         cus_pctype = i40e_find_customized_pctype(pf,
2388                                                          I40E_CUSTOMIZED_GTPU);
2389                 else if (filter->input.flow_ext.iip_type ==
2390                          I40E_FDIR_IPTYPE_IPV4)
2391                         cus_pctype = i40e_find_customized_pctype(pf,
2392                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2393                 else if (filter->input.flow_ext.iip_type ==
2394                          I40E_FDIR_IPTYPE_IPV6)
2395                         cus_pctype = i40e_find_customized_pctype(pf,
2396                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2397                 break;
2398         default:
2399                 PMD_DRV_LOG(ERR, "Unsupported item type");
2400                 break;
2401         }
2402
2403         if (cus_pctype)
2404                 return cus_pctype->pctype;
2405
2406         return I40E_FILTER_PCTYPE_INVALID;
2407 }
2408
2409 /* 1. Last in item should be NULL as range is not supported.
2410  * 2. Supported patterns: refer to array i40e_supported_patterns.
2411  * 3. Default supported flow type and input set: refer to array
2412  *    valid_fdir_inset_table in i40e_ethdev.c.
2413  * 4. Mask of fields which need to be matched should be
2414  *    filled with 1.
2415  * 5. Mask of fields which needn't to be matched should be
2416  *    filled with 0.
2417  * 6. GTP profile supports GTPv1 only.
2418  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2419  */
2420 static int
2421 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2422                              const struct rte_flow_item *pattern,
2423                              struct rte_flow_error *error,
2424                              struct i40e_fdir_filter_conf *filter)
2425 {
2426         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2427         const struct rte_flow_item *item = pattern;
2428         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2429         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2430         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2431         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2432         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2433         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2434         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2435         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2436         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2437         const struct rte_flow_item_vf *vf_spec;
2438
2439         uint8_t pctype = 0;
2440         uint64_t input_set = I40E_INSET_NONE;
2441         uint16_t frag_off;
2442         enum rte_flow_item_type item_type;
2443         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2444         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2445         uint32_t i, j;
2446         uint8_t  ipv6_addr_mask[16] = {
2447                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2448                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2449         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2450         uint8_t raw_id = 0;
2451         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2452         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2453         struct i40e_fdir_flex_pit flex_pit;
2454         uint8_t next_dst_off = 0;
2455         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2456         uint16_t flex_size;
2457         bool cfg_flex_pit = true;
2458         bool cfg_flex_msk = true;
2459         uint16_t outer_tpid;
2460         uint16_t ether_type;
2461         uint32_t vtc_flow_cpu;
2462         bool outer_ip = true;
2463         int ret;
2464
2465         memset(off_arr, 0, sizeof(off_arr));
2466         memset(len_arr, 0, sizeof(len_arr));
2467         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2468         outer_tpid = i40e_get_outer_vlan(dev);
2469         filter->input.flow_ext.customized_pctype = false;
2470         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2471                 if (item->last) {
2472                         rte_flow_error_set(error, EINVAL,
2473                                            RTE_FLOW_ERROR_TYPE_ITEM,
2474                                            item,
2475                                            "Not support range");
2476                         return -rte_errno;
2477                 }
2478                 item_type = item->type;
2479                 switch (item_type) {
2480                 case RTE_FLOW_ITEM_TYPE_ETH:
2481                         eth_spec = item->spec;
2482                         eth_mask = item->mask;
2483
2484                         if (eth_spec && eth_mask) {
2485                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2486                                     !is_zero_ether_addr(&eth_mask->dst)) {
2487                                         rte_flow_error_set(error, EINVAL,
2488                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2489                                                       item,
2490                                                       "Invalid MAC_addr mask.");
2491                                         return -rte_errno;
2492                                 }
2493
2494                                 if ((eth_mask->type & UINT16_MAX) ==
2495                                     UINT16_MAX) {
2496                                         input_set |= I40E_INSET_LAST_ETHER_TYPE;
2497                                         filter->input.flow.l2_flow.ether_type =
2498                                                 eth_spec->type;
2499                                 }
2500
2501                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2502                                 if (ether_type == ETHER_TYPE_IPv4 ||
2503                                     ether_type == ETHER_TYPE_IPv6 ||
2504                                     ether_type == ETHER_TYPE_ARP ||
2505                                     ether_type == outer_tpid) {
2506                                         rte_flow_error_set(error, EINVAL,
2507                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2508                                                      item,
2509                                                      "Unsupported ether_type.");
2510                                         return -rte_errno;
2511                                 }
2512                         }
2513
2514                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2515                         layer_idx = I40E_FLXPLD_L2_IDX;
2516
2517                         break;
2518                 case RTE_FLOW_ITEM_TYPE_VLAN:
2519                         vlan_spec = item->spec;
2520                         vlan_mask = item->mask;
2521                         if (vlan_spec && vlan_mask) {
2522                                 if (vlan_mask->tci ==
2523                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2524                                         input_set |= I40E_INSET_VLAN_INNER;
2525                                         filter->input.flow_ext.vlan_tci =
2526                                                 vlan_spec->tci;
2527                                 }
2528                         }
2529
2530                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2531                         layer_idx = I40E_FLXPLD_L2_IDX;
2532
2533                         break;
2534                 case RTE_FLOW_ITEM_TYPE_IPV4:
2535                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2536                         ipv4_spec = item->spec;
2537                         ipv4_mask = item->mask;
2538                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2539                         layer_idx = I40E_FLXPLD_L3_IDX;
2540
2541                         if (ipv4_spec && ipv4_mask && outer_ip) {
2542                                 /* Check IPv4 mask and update input set */
2543                                 if (ipv4_mask->hdr.version_ihl ||
2544                                     ipv4_mask->hdr.total_length ||
2545                                     ipv4_mask->hdr.packet_id ||
2546                                     ipv4_mask->hdr.fragment_offset ||
2547                                     ipv4_mask->hdr.hdr_checksum) {
2548                                         rte_flow_error_set(error, EINVAL,
2549                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2550                                                    item,
2551                                                    "Invalid IPv4 mask.");
2552                                         return -rte_errno;
2553                                 }
2554
2555                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2556                                         input_set |= I40E_INSET_IPV4_SRC;
2557                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2558                                         input_set |= I40E_INSET_IPV4_DST;
2559                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2560                                         input_set |= I40E_INSET_IPV4_TOS;
2561                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2562                                         input_set |= I40E_INSET_IPV4_TTL;
2563                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2564                                         input_set |= I40E_INSET_IPV4_PROTO;
2565
2566                                 /* Check if it is fragment. */
2567                                 frag_off = ipv4_spec->hdr.fragment_offset;
2568                                 frag_off = rte_be_to_cpu_16(frag_off);
2569                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2570                                     frag_off & IPV4_HDR_MF_FLAG)
2571                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2572
2573                                 /* Get the filter info */
2574                                 filter->input.flow.ip4_flow.proto =
2575                                         ipv4_spec->hdr.next_proto_id;
2576                                 filter->input.flow.ip4_flow.tos =
2577                                         ipv4_spec->hdr.type_of_service;
2578                                 filter->input.flow.ip4_flow.ttl =
2579                                         ipv4_spec->hdr.time_to_live;
2580                                 filter->input.flow.ip4_flow.src_ip =
2581                                         ipv4_spec->hdr.src_addr;
2582                                 filter->input.flow.ip4_flow.dst_ip =
2583                                         ipv4_spec->hdr.dst_addr;
2584                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2585                                 filter->input.flow_ext.inner_ip = true;
2586                                 filter->input.flow_ext.iip_type =
2587                                         I40E_FDIR_IPTYPE_IPV4;
2588                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2589                                 rte_flow_error_set(error, EINVAL,
2590                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2591                                                    item,
2592                                                    "Invalid inner IPv4 mask.");
2593                                 return -rte_errno;
2594                         }
2595
2596                         if (outer_ip)
2597                                 outer_ip = false;
2598
2599                         break;
2600                 case RTE_FLOW_ITEM_TYPE_IPV6:
2601                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2602                         ipv6_spec = item->spec;
2603                         ipv6_mask = item->mask;
2604                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2605                         layer_idx = I40E_FLXPLD_L3_IDX;
2606
2607                         if (ipv6_spec && ipv6_mask && outer_ip) {
2608                                 /* Check IPv6 mask and update input set */
2609                                 if (ipv6_mask->hdr.payload_len) {
2610                                         rte_flow_error_set(error, EINVAL,
2611                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2612                                                    item,
2613                                                    "Invalid IPv6 mask");
2614                                         return -rte_errno;
2615                                 }
2616
2617                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2618                                             ipv6_addr_mask,
2619                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2620                                         input_set |= I40E_INSET_IPV6_SRC;
2621                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2622                                             ipv6_addr_mask,
2623                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2624                                         input_set |= I40E_INSET_IPV6_DST;
2625
2626                                 if ((ipv6_mask->hdr.vtc_flow &
2627                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2628                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2629                                         input_set |= I40E_INSET_IPV6_TC;
2630                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2631                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2632                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2633                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2634
2635                                 /* Get filter info */
2636                                 vtc_flow_cpu =
2637                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2638                                 filter->input.flow.ipv6_flow.tc =
2639                                         (uint8_t)(vtc_flow_cpu >>
2640                                                   I40E_FDIR_IPv6_TC_OFFSET);
2641                                 filter->input.flow.ipv6_flow.proto =
2642                                         ipv6_spec->hdr.proto;
2643                                 filter->input.flow.ipv6_flow.hop_limits =
2644                                         ipv6_spec->hdr.hop_limits;
2645
2646                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2647                                            ipv6_spec->hdr.src_addr, 16);
2648                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2649                                            ipv6_spec->hdr.dst_addr, 16);
2650
2651                                 /* Check if it is fragment. */
2652                                 if (ipv6_spec->hdr.proto ==
2653                                     I40E_IPV6_FRAG_HEADER)
2654                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2655                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2656                                 filter->input.flow_ext.inner_ip = true;
2657                                 filter->input.flow_ext.iip_type =
2658                                         I40E_FDIR_IPTYPE_IPV6;
2659                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2660                                 rte_flow_error_set(error, EINVAL,
2661                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2662                                                    item,
2663                                                    "Invalid inner IPv6 mask");
2664                                 return -rte_errno;
2665                         }
2666
2667                         if (outer_ip)
2668                                 outer_ip = false;
2669                         break;
2670                 case RTE_FLOW_ITEM_TYPE_TCP:
2671                         tcp_spec = item->spec;
2672                         tcp_mask = item->mask;
2673
2674                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2675                                 pctype =
2676                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2677                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2678                                 pctype =
2679                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2680                         if (tcp_spec && tcp_mask) {
2681                                 /* Check TCP mask and update input set */
2682                                 if (tcp_mask->hdr.sent_seq ||
2683                                     tcp_mask->hdr.recv_ack ||
2684                                     tcp_mask->hdr.data_off ||
2685                                     tcp_mask->hdr.tcp_flags ||
2686                                     tcp_mask->hdr.rx_win ||
2687                                     tcp_mask->hdr.cksum ||
2688                                     tcp_mask->hdr.tcp_urp) {
2689                                         rte_flow_error_set(error, EINVAL,
2690                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2691                                                    item,
2692                                                    "Invalid TCP mask");
2693                                         return -rte_errno;
2694                                 }
2695
2696                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2697                                         input_set |= I40E_INSET_SRC_PORT;
2698                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2699                                         input_set |= I40E_INSET_DST_PORT;
2700
2701                                 /* Get filter info */
2702                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2703                                         filter->input.flow.tcp4_flow.src_port =
2704                                                 tcp_spec->hdr.src_port;
2705                                         filter->input.flow.tcp4_flow.dst_port =
2706                                                 tcp_spec->hdr.dst_port;
2707                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2708                                         filter->input.flow.tcp6_flow.src_port =
2709                                                 tcp_spec->hdr.src_port;
2710                                         filter->input.flow.tcp6_flow.dst_port =
2711                                                 tcp_spec->hdr.dst_port;
2712                                 }
2713                         }
2714
2715                         layer_idx = I40E_FLXPLD_L4_IDX;
2716
2717                         break;
2718                 case RTE_FLOW_ITEM_TYPE_UDP:
2719                         udp_spec = item->spec;
2720                         udp_mask = item->mask;
2721
2722                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2723                                 pctype =
2724                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2725                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2726                                 pctype =
2727                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2728
2729                         if (udp_spec && udp_mask) {
2730                                 /* Check UDP mask and update input set*/
2731                                 if (udp_mask->hdr.dgram_len ||
2732                                     udp_mask->hdr.dgram_cksum) {
2733                                         rte_flow_error_set(error, EINVAL,
2734                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2735                                                    item,
2736                                                    "Invalid UDP mask");
2737                                         return -rte_errno;
2738                                 }
2739
2740                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2741                                         input_set |= I40E_INSET_SRC_PORT;
2742                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2743                                         input_set |= I40E_INSET_DST_PORT;
2744
2745                                 /* Get filter info */
2746                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2747                                         filter->input.flow.udp4_flow.src_port =
2748                                                 udp_spec->hdr.src_port;
2749                                         filter->input.flow.udp4_flow.dst_port =
2750                                                 udp_spec->hdr.dst_port;
2751                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2752                                         filter->input.flow.udp6_flow.src_port =
2753                                                 udp_spec->hdr.src_port;
2754                                         filter->input.flow.udp6_flow.dst_port =
2755                                                 udp_spec->hdr.dst_port;
2756                                 }
2757                         }
2758
2759                         layer_idx = I40E_FLXPLD_L4_IDX;
2760
2761                         break;
2762                 case RTE_FLOW_ITEM_TYPE_GTPC:
2763                 case RTE_FLOW_ITEM_TYPE_GTPU:
2764                         if (!pf->gtp_support) {
2765                                 rte_flow_error_set(error, EINVAL,
2766                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2767                                                    item,
2768                                                    "Unsupported protocol");
2769                                 return -rte_errno;
2770                         }
2771
2772                         gtp_spec = item->spec;
2773                         gtp_mask = item->mask;
2774
2775                         if (gtp_spec && gtp_mask) {
2776                                 if (gtp_mask->v_pt_rsv_flags ||
2777                                     gtp_mask->msg_type ||
2778                                     gtp_mask->msg_len ||
2779                                     gtp_mask->teid != UINT32_MAX) {
2780                                         rte_flow_error_set(error, EINVAL,
2781                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2782                                                    item,
2783                                                    "Invalid GTP mask");
2784                                         return -rte_errno;
2785                                 }
2786
2787                                 filter->input.flow.gtp_flow.teid =
2788                                         gtp_spec->teid;
2789                                 filter->input.flow_ext.customized_pctype = true;
2790                                 cus_proto = item_type;
2791                         }
2792                         break;
2793                 case RTE_FLOW_ITEM_TYPE_SCTP:
2794                         sctp_spec = item->spec;
2795                         sctp_mask = item->mask;
2796
2797                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2798                                 pctype =
2799                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2800                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2801                                 pctype =
2802                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2803
2804                         if (sctp_spec && sctp_mask) {
2805                                 /* Check SCTP mask and update input set */
2806                                 if (sctp_mask->hdr.cksum) {
2807                                         rte_flow_error_set(error, EINVAL,
2808                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2809                                                    item,
2810                                                    "Invalid UDP mask");
2811                                         return -rte_errno;
2812                                 }
2813
2814                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2815                                         input_set |= I40E_INSET_SRC_PORT;
2816                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2817                                         input_set |= I40E_INSET_DST_PORT;
2818                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2819                                         input_set |= I40E_INSET_SCTP_VT;
2820
2821                                 /* Get filter info */
2822                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2823                                         filter->input.flow.sctp4_flow.src_port =
2824                                                 sctp_spec->hdr.src_port;
2825                                         filter->input.flow.sctp4_flow.dst_port =
2826                                                 sctp_spec->hdr.dst_port;
2827                                         filter->input.flow.sctp4_flow.verify_tag
2828                                                 = sctp_spec->hdr.tag;
2829                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2830                                         filter->input.flow.sctp6_flow.src_port =
2831                                                 sctp_spec->hdr.src_port;
2832                                         filter->input.flow.sctp6_flow.dst_port =
2833                                                 sctp_spec->hdr.dst_port;
2834                                         filter->input.flow.sctp6_flow.verify_tag
2835                                                 = sctp_spec->hdr.tag;
2836                                 }
2837                         }
2838
2839                         layer_idx = I40E_FLXPLD_L4_IDX;
2840
2841                         break;
2842                 case RTE_FLOW_ITEM_TYPE_RAW:
2843                         raw_spec = item->spec;
2844                         raw_mask = item->mask;
2845
2846                         if (!raw_spec || !raw_mask) {
2847                                 rte_flow_error_set(error, EINVAL,
2848                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2849                                                    item,
2850                                                    "NULL RAW spec/mask");
2851                                 return -rte_errno;
2852                         }
2853
2854                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2855                         if (ret < 0)
2856                                 return ret;
2857
2858                         off_arr[raw_id] = raw_spec->offset;
2859                         len_arr[raw_id] = raw_spec->length;
2860
2861                         flex_size = 0;
2862                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2863                         flex_pit.size =
2864                                 raw_spec->length / sizeof(uint16_t);
2865                         flex_pit.dst_offset =
2866                                 next_dst_off / sizeof(uint16_t);
2867
2868                         for (i = 0; i <= raw_id; i++) {
2869                                 if (i == raw_id)
2870                                         flex_pit.src_offset +=
2871                                                 raw_spec->offset /
2872                                                 sizeof(uint16_t);
2873                                 else
2874                                         flex_pit.src_offset +=
2875                                                 (off_arr[i] + len_arr[i]) /
2876                                                 sizeof(uint16_t);
2877                                 flex_size += len_arr[i];
2878                         }
2879                         if (((flex_pit.src_offset + flex_pit.size) >=
2880                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2881                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2882                                 rte_flow_error_set(error, EINVAL,
2883                                            RTE_FLOW_ERROR_TYPE_ITEM,
2884                                            item,
2885                                            "Exceeds maxmial payload limit.");
2886                                 return -rte_errno;
2887                         }
2888
2889                         /* Store flex pit to SW */
2890                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2891                                                        layer_idx, raw_id);
2892                         if (ret < 0) {
2893                                 rte_flow_error_set(error, EINVAL,
2894                                    RTE_FLOW_ERROR_TYPE_ITEM,
2895                                    item,
2896                                    "Conflict with the first flexible rule.");
2897                                 return -rte_errno;
2898                         } else if (ret > 0)
2899                                 cfg_flex_pit = false;
2900
2901                         for (i = 0; i < raw_spec->length; i++) {
2902                                 j = i + next_dst_off;
2903                                 filter->input.flow_ext.flexbytes[j] =
2904                                         raw_spec->pattern[i];
2905                                 flex_mask[j] = raw_mask->pattern[i];
2906                         }
2907
2908                         next_dst_off += raw_spec->length;
2909                         raw_id++;
2910                         break;
2911                 case RTE_FLOW_ITEM_TYPE_VF:
2912                         vf_spec = item->spec;
2913                         filter->input.flow_ext.is_vf = 1;
2914                         filter->input.flow_ext.dst_id = vf_spec->id;
2915                         if (filter->input.flow_ext.is_vf &&
2916                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2917                                 rte_flow_error_set(error, EINVAL,
2918                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2919                                                    item,
2920                                                    "Invalid VF ID for FDIR.");
2921                                 return -rte_errno;
2922                         }
2923                         break;
2924                 default:
2925                         break;
2926                 }
2927         }
2928
2929         /* Get customized pctype value */
2930         if (filter->input.flow_ext.customized_pctype) {
2931                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2932                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2933                         rte_flow_error_set(error, EINVAL,
2934                                            RTE_FLOW_ERROR_TYPE_ITEM,
2935                                            item,
2936                                            "Unsupported pctype");
2937                         return -rte_errno;
2938                 }
2939         }
2940
2941         /* If customized pctype is not used, set fdir configuration.*/
2942         if (!filter->input.flow_ext.customized_pctype) {
2943                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2944                 if (ret == -1) {
2945                         rte_flow_error_set(error, EINVAL,
2946                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2947                                            "Conflict with the first rule's input set.");
2948                         return -rte_errno;
2949                 } else if (ret == -EINVAL) {
2950                         rte_flow_error_set(error, EINVAL,
2951                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2952                                            "Invalid pattern mask.");
2953                         return -rte_errno;
2954                 }
2955
2956                 /* Store flex mask to SW */
2957                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2958                 if (ret == -1) {
2959                         rte_flow_error_set(error, EINVAL,
2960                                            RTE_FLOW_ERROR_TYPE_ITEM,
2961                                            item,
2962                                            "Exceed maximal number of bitmasks");
2963                         return -rte_errno;
2964                 } else if (ret == -2) {
2965                         rte_flow_error_set(error, EINVAL,
2966                                            RTE_FLOW_ERROR_TYPE_ITEM,
2967                                            item,
2968                                            "Conflict with the first flexible rule");
2969                         return -rte_errno;
2970                 } else if (ret > 0)
2971                         cfg_flex_msk = false;
2972
2973                 if (cfg_flex_pit)
2974                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
2975
2976                 if (cfg_flex_msk)
2977                         i40e_flow_set_fdir_flex_msk(pf, pctype);
2978         }
2979
2980         filter->input.pctype = pctype;
2981
2982         return 0;
2983 }
2984
2985 /* Parse to get the action info of a FDIR filter.
2986  * FDIR action supports QUEUE or (QUEUE + MARK).
2987  */
2988 static int
2989 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
2990                             const struct rte_flow_action *actions,
2991                             struct rte_flow_error *error,
2992                             struct i40e_fdir_filter_conf *filter)
2993 {
2994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2995         const struct rte_flow_action *act;
2996         const struct rte_flow_action_queue *act_q;
2997         const struct rte_flow_action_mark *mark_spec;
2998         uint32_t index = 0;
2999
3000         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3001         NEXT_ITEM_OF_ACTION(act, actions, index);
3002         switch (act->type) {
3003         case RTE_FLOW_ACTION_TYPE_QUEUE:
3004                 act_q = act->conf;
3005                 filter->action.rx_queue = act_q->index;
3006                 if ((!filter->input.flow_ext.is_vf &&
3007                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3008                     (filter->input.flow_ext.is_vf &&
3009                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3010                         rte_flow_error_set(error, EINVAL,
3011                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3012                                            "Invalid queue ID for FDIR.");
3013                         return -rte_errno;
3014                 }
3015                 filter->action.behavior = I40E_FDIR_ACCEPT;
3016                 break;
3017         case RTE_FLOW_ACTION_TYPE_DROP:
3018                 filter->action.behavior = I40E_FDIR_REJECT;
3019                 break;
3020         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3021                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3022                 break;
3023         default:
3024                 rte_flow_error_set(error, EINVAL,
3025                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3026                                    "Invalid action.");
3027                 return -rte_errno;
3028         }
3029
3030         /* Check if the next non-void item is MARK or FLAG or END. */
3031         index++;
3032         NEXT_ITEM_OF_ACTION(act, actions, index);
3033         switch (act->type) {
3034         case RTE_FLOW_ACTION_TYPE_MARK:
3035                 mark_spec = act->conf;
3036                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3037                 filter->soft_id = mark_spec->id;
3038                 break;
3039         case RTE_FLOW_ACTION_TYPE_FLAG:
3040                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3041                 break;
3042         case RTE_FLOW_ACTION_TYPE_END:
3043                 return 0;
3044         default:
3045                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3046                                    act, "Invalid action.");
3047                 return -rte_errno;
3048         }
3049
3050         /* Check if the next non-void item is END */
3051         index++;
3052         NEXT_ITEM_OF_ACTION(act, actions, index);
3053         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3054                 rte_flow_error_set(error, EINVAL,
3055                                    RTE_FLOW_ERROR_TYPE_ACTION,
3056                                    act, "Invalid action.");
3057                 return -rte_errno;
3058         }
3059
3060         return 0;
3061 }
3062
3063 static int
3064 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3065                             const struct rte_flow_attr *attr,
3066                             const struct rte_flow_item pattern[],
3067                             const struct rte_flow_action actions[],
3068                             struct rte_flow_error *error,
3069                             union i40e_filter_t *filter)
3070 {
3071         struct i40e_fdir_filter_conf *fdir_filter =
3072                 &filter->fdir_filter;
3073         int ret;
3074
3075         ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3076         if (ret)
3077                 return ret;
3078
3079         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3080         if (ret)
3081                 return ret;
3082
3083         ret = i40e_flow_parse_attr(attr, error);
3084         if (ret)
3085                 return ret;
3086
3087         cons_filter_type = RTE_ETH_FILTER_FDIR;
3088
3089         if (dev->data->dev_conf.fdir_conf.mode !=
3090             RTE_FDIR_MODE_PERFECT) {
3091                 rte_flow_error_set(error, ENOTSUP,
3092                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3093                                    NULL,
3094                                    "Check the mode in fdir_conf.");
3095                 return -rte_errno;
3096         }
3097
3098         return 0;
3099 }
3100
3101 /* Parse to get the action info of a tunnel filter
3102  * Tunnel action only supports PF, VF and QUEUE.
3103  */
3104 static int
3105 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3106                               const struct rte_flow_action *actions,
3107                               struct rte_flow_error *error,
3108                               struct i40e_tunnel_filter_conf *filter)
3109 {
3110         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3111         const struct rte_flow_action *act;
3112         const struct rte_flow_action_queue *act_q;
3113         const struct rte_flow_action_vf *act_vf;
3114         uint32_t index = 0;
3115
3116         /* Check if the first non-void action is PF or VF. */
3117         NEXT_ITEM_OF_ACTION(act, actions, index);
3118         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3119             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3120                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3121                                    act, "Not supported action.");
3122                 return -rte_errno;
3123         }
3124
3125         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3126                 act_vf = act->conf;
3127                 filter->vf_id = act_vf->id;
3128                 filter->is_to_vf = 1;
3129                 if (filter->vf_id >= pf->vf_num) {
3130                         rte_flow_error_set(error, EINVAL,
3131                                    RTE_FLOW_ERROR_TYPE_ACTION,
3132                                    act, "Invalid VF ID for tunnel filter");
3133                         return -rte_errno;
3134                 }
3135         }
3136
3137         /* Check if the next non-void item is QUEUE */
3138         index++;
3139         NEXT_ITEM_OF_ACTION(act, actions, index);
3140         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3141                 act_q = act->conf;
3142                 filter->queue_id = act_q->index;
3143                 if ((!filter->is_to_vf) &&
3144                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3145                         rte_flow_error_set(error, EINVAL,
3146                                    RTE_FLOW_ERROR_TYPE_ACTION,
3147                                    act, "Invalid queue ID for tunnel filter");
3148                         return -rte_errno;
3149                 } else if (filter->is_to_vf &&
3150                            (filter->queue_id >= pf->vf_nb_qps)) {
3151                         rte_flow_error_set(error, EINVAL,
3152                                    RTE_FLOW_ERROR_TYPE_ACTION,
3153                                    act, "Invalid queue ID for tunnel filter");
3154                         return -rte_errno;
3155                 }
3156         }
3157
3158         /* Check if the next non-void item is END */
3159         index++;
3160         NEXT_ITEM_OF_ACTION(act, actions, index);
3161         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3162                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3163                                    act, "Not supported action.");
3164                 return -rte_errno;
3165         }
3166
3167         return 0;
3168 }
3169
3170 static uint16_t i40e_supported_tunnel_filter_types[] = {
3171         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3172         ETH_TUNNEL_FILTER_IVLAN,
3173         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3174         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3175         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3176         ETH_TUNNEL_FILTER_IMAC,
3177         ETH_TUNNEL_FILTER_IMAC,
3178 };
3179
3180 static int
3181 i40e_check_tunnel_filter_type(uint8_t filter_type)
3182 {
3183         uint8_t i;
3184
3185         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3186                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3187                         return 0;
3188         }
3189
3190         return -1;
3191 }
3192
3193 /* 1. Last in item should be NULL as range is not supported.
3194  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3195  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3196  * 3. Mask of fields which need to be matched should be
3197  *    filled with 1.
3198  * 4. Mask of fields which needn't to be matched should be
3199  *    filled with 0.
3200  */
3201 static int
3202 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3203                               const struct rte_flow_item *pattern,
3204                               struct rte_flow_error *error,
3205                               struct i40e_tunnel_filter_conf *filter)
3206 {
3207         const struct rte_flow_item *item = pattern;
3208         const struct rte_flow_item_eth *eth_spec;
3209         const struct rte_flow_item_eth *eth_mask;
3210         const struct rte_flow_item_vxlan *vxlan_spec;
3211         const struct rte_flow_item_vxlan *vxlan_mask;
3212         const struct rte_flow_item_vlan *vlan_spec;
3213         const struct rte_flow_item_vlan *vlan_mask;
3214         uint8_t filter_type = 0;
3215         bool is_vni_masked = 0;
3216         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3217         enum rte_flow_item_type item_type;
3218         bool vxlan_flag = 0;
3219         uint32_t tenant_id_be = 0;
3220         int ret;
3221
3222         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3223                 if (item->last) {
3224                         rte_flow_error_set(error, EINVAL,
3225                                            RTE_FLOW_ERROR_TYPE_ITEM,
3226                                            item,
3227                                            "Not support range");
3228                         return -rte_errno;
3229                 }
3230                 item_type = item->type;
3231                 switch (item_type) {
3232                 case RTE_FLOW_ITEM_TYPE_ETH:
3233                         eth_spec = item->spec;
3234                         eth_mask = item->mask;
3235
3236                         /* Check if ETH item is used for place holder.
3237                          * If yes, both spec and mask should be NULL.
3238                          * If no, both spec and mask shouldn't be NULL.
3239                          */
3240                         if ((!eth_spec && eth_mask) ||
3241                             (eth_spec && !eth_mask)) {
3242                                 rte_flow_error_set(error, EINVAL,
3243                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3244                                                    item,
3245                                                    "Invalid ether spec/mask");
3246                                 return -rte_errno;
3247                         }
3248
3249                         if (eth_spec && eth_mask) {
3250                                 /* DST address of inner MAC shouldn't be masked.
3251                                  * SRC address of Inner MAC should be masked.
3252                                  */
3253                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3254                                     !is_zero_ether_addr(&eth_mask->src) ||
3255                                     eth_mask->type) {
3256                                         rte_flow_error_set(error, EINVAL,
3257                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3258                                                    item,
3259                                                    "Invalid ether spec/mask");
3260                                         return -rte_errno;
3261                                 }
3262
3263                                 if (!vxlan_flag) {
3264                                         rte_memcpy(&filter->outer_mac,
3265                                                    &eth_spec->dst,
3266                                                    ETHER_ADDR_LEN);
3267                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3268                                 } else {
3269                                         rte_memcpy(&filter->inner_mac,
3270                                                    &eth_spec->dst,
3271                                                    ETHER_ADDR_LEN);
3272                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3273                                 }
3274                         }
3275                         break;
3276                 case RTE_FLOW_ITEM_TYPE_VLAN:
3277                         vlan_spec = item->spec;
3278                         vlan_mask = item->mask;
3279                         if (!(vlan_spec && vlan_mask)) {
3280                                 rte_flow_error_set(error, EINVAL,
3281                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3282                                                    item,
3283                                                    "Invalid vlan item");
3284                                 return -rte_errno;
3285                         }
3286
3287                         if (vlan_spec && vlan_mask) {
3288                                 if (vlan_mask->tci ==
3289                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3290                                         filter->inner_vlan =
3291                                               rte_be_to_cpu_16(vlan_spec->tci) &
3292                                               I40E_TCI_MASK;
3293                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3294                         }
3295                         break;
3296                 case RTE_FLOW_ITEM_TYPE_IPV4:
3297                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3298                         /* IPv4 is used to describe protocol,
3299                          * spec and mask should be NULL.
3300                          */
3301                         if (item->spec || item->mask) {
3302                                 rte_flow_error_set(error, EINVAL,
3303                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3304                                                    item,
3305                                                    "Invalid IPv4 item");
3306                                 return -rte_errno;
3307                         }
3308                         break;
3309                 case RTE_FLOW_ITEM_TYPE_IPV6:
3310                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3311                         /* IPv6 is used to describe protocol,
3312                          * spec and mask should be NULL.
3313                          */
3314                         if (item->spec || item->mask) {
3315                                 rte_flow_error_set(error, EINVAL,
3316                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3317                                                    item,
3318                                                    "Invalid IPv6 item");
3319                                 return -rte_errno;
3320                         }
3321                         break;
3322                 case RTE_FLOW_ITEM_TYPE_UDP:
3323                         /* UDP is used to describe protocol,
3324                          * spec and mask should be NULL.
3325                          */
3326                         if (item->spec || item->mask) {
3327                                 rte_flow_error_set(error, EINVAL,
3328                                            RTE_FLOW_ERROR_TYPE_ITEM,
3329                                            item,
3330                                            "Invalid UDP item");
3331                                 return -rte_errno;
3332                         }
3333                         break;
3334                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3335                         vxlan_spec = item->spec;
3336                         vxlan_mask = item->mask;
3337                         /* Check if VXLAN item is used to describe protocol.
3338                          * If yes, both spec and mask should be NULL.
3339                          * If no, both spec and mask shouldn't be NULL.
3340                          */
3341                         if ((!vxlan_spec && vxlan_mask) ||
3342                             (vxlan_spec && !vxlan_mask)) {
3343                                 rte_flow_error_set(error, EINVAL,
3344                                            RTE_FLOW_ERROR_TYPE_ITEM,
3345                                            item,
3346                                            "Invalid VXLAN item");
3347                                 return -rte_errno;
3348                         }
3349
3350                         /* Check if VNI is masked. */
3351                         if (vxlan_spec && vxlan_mask) {
3352                                 is_vni_masked =
3353                                         !!memcmp(vxlan_mask->vni, vni_mask,
3354                                                  RTE_DIM(vni_mask));
3355                                 if (is_vni_masked) {
3356                                         rte_flow_error_set(error, EINVAL,
3357                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3358                                                    item,
3359                                                    "Invalid VNI mask");
3360                                         return -rte_errno;
3361                                 }
3362
3363                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3364                                            vxlan_spec->vni, 3);
3365                                 filter->tenant_id =
3366                                         rte_be_to_cpu_32(tenant_id_be);
3367                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3368                         }
3369
3370                         vxlan_flag = 1;
3371                         break;
3372                 default:
3373                         break;
3374                 }
3375         }
3376
3377         ret = i40e_check_tunnel_filter_type(filter_type);
3378         if (ret < 0) {
3379                 rte_flow_error_set(error, EINVAL,
3380                                    RTE_FLOW_ERROR_TYPE_ITEM,
3381                                    NULL,
3382                                    "Invalid filter type");
3383                 return -rte_errno;
3384         }
3385         filter->filter_type = filter_type;
3386
3387         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3388
3389         return 0;
3390 }
3391
3392 static int
3393 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3394                              const struct rte_flow_attr *attr,
3395                              const struct rte_flow_item pattern[],
3396                              const struct rte_flow_action actions[],
3397                              struct rte_flow_error *error,
3398                              union i40e_filter_t *filter)
3399 {
3400         struct i40e_tunnel_filter_conf *tunnel_filter =
3401                 &filter->consistent_tunnel_filter;
3402         int ret;
3403
3404         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3405                                             error, tunnel_filter);
3406         if (ret)
3407                 return ret;
3408
3409         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3410         if (ret)
3411                 return ret;
3412
3413         ret = i40e_flow_parse_attr(attr, error);
3414         if (ret)
3415                 return ret;
3416
3417         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3418
3419         return ret;
3420 }
3421
3422 /* 1. Last in item should be NULL as range is not supported.
3423  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3424  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3425  * 3. Mask of fields which need to be matched should be
3426  *    filled with 1.
3427  * 4. Mask of fields which needn't to be matched should be
3428  *    filled with 0.
3429  */
3430 static int
3431 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3432                               const struct rte_flow_item *pattern,
3433                               struct rte_flow_error *error,
3434                               struct i40e_tunnel_filter_conf *filter)
3435 {
3436         const struct rte_flow_item *item = pattern;
3437         const struct rte_flow_item_eth *eth_spec;
3438         const struct rte_flow_item_eth *eth_mask;
3439         const struct rte_flow_item_nvgre *nvgre_spec;
3440         const struct rte_flow_item_nvgre *nvgre_mask;
3441         const struct rte_flow_item_vlan *vlan_spec;
3442         const struct rte_flow_item_vlan *vlan_mask;
3443         enum rte_flow_item_type item_type;
3444         uint8_t filter_type = 0;
3445         bool is_tni_masked = 0;
3446         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3447         bool nvgre_flag = 0;
3448         uint32_t tenant_id_be = 0;
3449         int ret;
3450
3451         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3452                 if (item->last) {
3453                         rte_flow_error_set(error, EINVAL,
3454                                            RTE_FLOW_ERROR_TYPE_ITEM,
3455                                            item,
3456                                            "Not support range");
3457                         return -rte_errno;
3458                 }
3459                 item_type = item->type;
3460                 switch (item_type) {
3461                 case RTE_FLOW_ITEM_TYPE_ETH:
3462                         eth_spec = item->spec;
3463                         eth_mask = item->mask;
3464
3465                         /* Check if ETH item is used for place holder.
3466                          * If yes, both spec and mask should be NULL.
3467                          * If no, both spec and mask shouldn't be NULL.
3468                          */
3469                         if ((!eth_spec && eth_mask) ||
3470                             (eth_spec && !eth_mask)) {
3471                                 rte_flow_error_set(error, EINVAL,
3472                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3473                                                    item,
3474                                                    "Invalid ether spec/mask");
3475                                 return -rte_errno;
3476                         }
3477
3478                         if (eth_spec && eth_mask) {
3479                                 /* DST address of inner MAC shouldn't be masked.
3480                                  * SRC address of Inner MAC should be masked.
3481                                  */
3482                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3483                                     !is_zero_ether_addr(&eth_mask->src) ||
3484                                     eth_mask->type) {
3485                                         rte_flow_error_set(error, EINVAL,
3486                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3487                                                    item,
3488                                                    "Invalid ether spec/mask");
3489                                         return -rte_errno;
3490                                 }
3491
3492                                 if (!nvgre_flag) {
3493                                         rte_memcpy(&filter->outer_mac,
3494                                                    &eth_spec->dst,
3495                                                    ETHER_ADDR_LEN);
3496                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3497                                 } else {
3498                                         rte_memcpy(&filter->inner_mac,
3499                                                    &eth_spec->dst,
3500                                                    ETHER_ADDR_LEN);
3501                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3502                                 }
3503                         }
3504
3505                         break;
3506                 case RTE_FLOW_ITEM_TYPE_VLAN:
3507                         vlan_spec = item->spec;
3508                         vlan_mask = item->mask;
3509                         if (!(vlan_spec && vlan_mask)) {
3510                                 rte_flow_error_set(error, EINVAL,
3511                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3512                                                    item,
3513                                                    "Invalid vlan item");
3514                                 return -rte_errno;
3515                         }
3516
3517                         if (vlan_spec && vlan_mask) {
3518                                 if (vlan_mask->tci ==
3519                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3520                                         filter->inner_vlan =
3521                                               rte_be_to_cpu_16(vlan_spec->tci) &
3522                                               I40E_TCI_MASK;
3523                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3524                         }
3525                         break;
3526                 case RTE_FLOW_ITEM_TYPE_IPV4:
3527                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3528                         /* IPv4 is used to describe protocol,
3529                          * spec and mask should be NULL.
3530                          */
3531                         if (item->spec || item->mask) {
3532                                 rte_flow_error_set(error, EINVAL,
3533                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3534                                                    item,
3535                                                    "Invalid IPv4 item");
3536                                 return -rte_errno;
3537                         }
3538                         break;
3539                 case RTE_FLOW_ITEM_TYPE_IPV6:
3540                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3541                         /* IPv6 is used to describe protocol,
3542                          * spec and mask should be NULL.
3543                          */
3544                         if (item->spec || item->mask) {
3545                                 rte_flow_error_set(error, EINVAL,
3546                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3547                                                    item,
3548                                                    "Invalid IPv6 item");
3549                                 return -rte_errno;
3550                         }
3551                         break;
3552                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3553                         nvgre_spec = item->spec;
3554                         nvgre_mask = item->mask;
3555                         /* Check if NVGRE item is used to describe protocol.
3556                          * If yes, both spec and mask should be NULL.
3557                          * If no, both spec and mask shouldn't be NULL.
3558                          */
3559                         if ((!nvgre_spec && nvgre_mask) ||
3560                             (nvgre_spec && !nvgre_mask)) {
3561                                 rte_flow_error_set(error, EINVAL,
3562                                            RTE_FLOW_ERROR_TYPE_ITEM,
3563                                            item,
3564                                            "Invalid NVGRE item");
3565                                 return -rte_errno;
3566                         }
3567
3568                         if (nvgre_spec && nvgre_mask) {
3569                                 is_tni_masked =
3570                                         !!memcmp(nvgre_mask->tni, tni_mask,
3571                                                  RTE_DIM(tni_mask));
3572                                 if (is_tni_masked) {
3573                                         rte_flow_error_set(error, EINVAL,
3574                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3575                                                        item,
3576                                                        "Invalid TNI mask");
3577                                         return -rte_errno;
3578                                 }
3579                                 if (nvgre_mask->protocol &&
3580                                         nvgre_mask->protocol != 0xFFFF) {
3581                                         rte_flow_error_set(error, EINVAL,
3582                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3583                                                 item,
3584                                                 "Invalid NVGRE item");
3585                                         return -rte_errno;
3586                                 }
3587                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3588                                         nvgre_mask->c_k_s_rsvd0_ver !=
3589                                         rte_cpu_to_be_16(0xFFFF)) {
3590                                         rte_flow_error_set(error, EINVAL,
3591                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3592                                                    item,
3593                                                    "Invalid NVGRE item");
3594                                         return -rte_errno;
3595                                 }
3596                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3597                                         rte_cpu_to_be_16(0x2000) &&
3598                                         nvgre_mask->c_k_s_rsvd0_ver) {
3599                                         rte_flow_error_set(error, EINVAL,
3600                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3601                                                    item,
3602                                                    "Invalid NVGRE item");
3603                                         return -rte_errno;
3604                                 }
3605                                 if (nvgre_mask->protocol &&
3606                                         nvgre_spec->protocol !=
3607                                         rte_cpu_to_be_16(0x6558)) {
3608                                         rte_flow_error_set(error, EINVAL,
3609                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3610                                                    item,
3611                                                    "Invalid NVGRE item");
3612                                         return -rte_errno;
3613                                 }
3614                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3615                                            nvgre_spec->tni, 3);
3616                                 filter->tenant_id =
3617                                         rte_be_to_cpu_32(tenant_id_be);
3618                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3619                         }
3620
3621                         nvgre_flag = 1;
3622                         break;
3623                 default:
3624                         break;
3625                 }
3626         }
3627
3628         ret = i40e_check_tunnel_filter_type(filter_type);
3629         if (ret < 0) {
3630                 rte_flow_error_set(error, EINVAL,
3631                                    RTE_FLOW_ERROR_TYPE_ITEM,
3632                                    NULL,
3633                                    "Invalid filter type");
3634                 return -rte_errno;
3635         }
3636         filter->filter_type = filter_type;
3637
3638         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3639
3640         return 0;
3641 }
3642
3643 static int
3644 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3645                              const struct rte_flow_attr *attr,
3646                              const struct rte_flow_item pattern[],
3647                              const struct rte_flow_action actions[],
3648                              struct rte_flow_error *error,
3649                              union i40e_filter_t *filter)
3650 {
3651         struct i40e_tunnel_filter_conf *tunnel_filter =
3652                 &filter->consistent_tunnel_filter;
3653         int ret;
3654
3655         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3656                                             error, tunnel_filter);
3657         if (ret)
3658                 return ret;
3659
3660         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3661         if (ret)
3662                 return ret;
3663
3664         ret = i40e_flow_parse_attr(attr, error);
3665         if (ret)
3666                 return ret;
3667
3668         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3669
3670         return ret;
3671 }
3672
3673 /* 1. Last in item should be NULL as range is not supported.
3674  * 2. Supported filter types: MPLS label.
3675  * 3. Mask of fields which need to be matched should be
3676  *    filled with 1.
3677  * 4. Mask of fields which needn't to be matched should be
3678  *    filled with 0.
3679  */
3680 static int
3681 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3682                              const struct rte_flow_item *pattern,
3683                              struct rte_flow_error *error,
3684                              struct i40e_tunnel_filter_conf *filter)
3685 {
3686         const struct rte_flow_item *item = pattern;
3687         const struct rte_flow_item_mpls *mpls_spec;
3688         const struct rte_flow_item_mpls *mpls_mask;
3689         enum rte_flow_item_type item_type;
3690         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3691         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3692         uint32_t label_be = 0;
3693
3694         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3695                 if (item->last) {
3696                         rte_flow_error_set(error, EINVAL,
3697                                            RTE_FLOW_ERROR_TYPE_ITEM,
3698                                            item,
3699                                            "Not support range");
3700                         return -rte_errno;
3701                 }
3702                 item_type = item->type;
3703                 switch (item_type) {
3704                 case RTE_FLOW_ITEM_TYPE_ETH:
3705                         if (item->spec || item->mask) {
3706                                 rte_flow_error_set(error, EINVAL,
3707                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3708                                                    item,
3709                                                    "Invalid ETH item");
3710                                 return -rte_errno;
3711                         }
3712                         break;
3713                 case RTE_FLOW_ITEM_TYPE_IPV4:
3714                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3715                         /* IPv4 is used to describe protocol,
3716                          * spec and mask should be NULL.
3717                          */
3718                         if (item->spec || item->mask) {
3719                                 rte_flow_error_set(error, EINVAL,
3720                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3721                                                    item,
3722                                                    "Invalid IPv4 item");
3723                                 return -rte_errno;
3724                         }
3725                         break;
3726                 case RTE_FLOW_ITEM_TYPE_IPV6:
3727                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3728                         /* IPv6 is used to describe protocol,
3729                          * spec and mask should be NULL.
3730                          */
3731                         if (item->spec || item->mask) {
3732                                 rte_flow_error_set(error, EINVAL,
3733                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3734                                                    item,
3735                                                    "Invalid IPv6 item");
3736                                 return -rte_errno;
3737                         }
3738                         break;
3739                 case RTE_FLOW_ITEM_TYPE_UDP:
3740                         /* UDP is used to describe protocol,
3741                          * spec and mask should be NULL.
3742                          */
3743                         if (item->spec || item->mask) {
3744                                 rte_flow_error_set(error, EINVAL,
3745                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3746                                                    item,
3747                                                    "Invalid UDP item");
3748                                 return -rte_errno;
3749                         }
3750                         is_mplsoudp = 1;
3751                         break;
3752                 case RTE_FLOW_ITEM_TYPE_GRE:
3753                         /* GRE is used to describe protocol,
3754                          * spec and mask should be NULL.
3755                          */
3756                         if (item->spec || item->mask) {
3757                                 rte_flow_error_set(error, EINVAL,
3758                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3759                                                    item,
3760                                                    "Invalid GRE item");
3761                                 return -rte_errno;
3762                         }
3763                         break;
3764                 case RTE_FLOW_ITEM_TYPE_MPLS:
3765                         mpls_spec = item->spec;
3766                         mpls_mask = item->mask;
3767
3768                         if (!mpls_spec || !mpls_mask) {
3769                                 rte_flow_error_set(error, EINVAL,
3770                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3771                                                    item,
3772                                                    "Invalid MPLS item");
3773                                 return -rte_errno;
3774                         }
3775
3776                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3777                                 rte_flow_error_set(error, EINVAL,
3778                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3779                                                    item,
3780                                                    "Invalid MPLS label mask");
3781                                 return -rte_errno;
3782                         }
3783                         rte_memcpy(((uint8_t *)&label_be + 1),
3784                                    mpls_spec->label_tc_s, 3);
3785                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3786                         break;
3787                 default:
3788                         break;
3789                 }
3790         }
3791
3792         if (is_mplsoudp)
3793                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3794         else
3795                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3796
3797         return 0;
3798 }
3799
3800 static int
3801 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3802                             const struct rte_flow_attr *attr,
3803                             const struct rte_flow_item pattern[],
3804                             const struct rte_flow_action actions[],
3805                             struct rte_flow_error *error,
3806                             union i40e_filter_t *filter)
3807 {
3808         struct i40e_tunnel_filter_conf *tunnel_filter =
3809                 &filter->consistent_tunnel_filter;
3810         int ret;
3811
3812         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3813                                            error, tunnel_filter);
3814         if (ret)
3815                 return ret;
3816
3817         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3818         if (ret)
3819                 return ret;
3820
3821         ret = i40e_flow_parse_attr(attr, error);
3822         if (ret)
3823                 return ret;
3824
3825         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3826
3827         return ret;
3828 }
3829
3830 /* 1. Last in item should be NULL as range is not supported.
3831  * 2. Supported filter types: GTP TEID.
3832  * 3. Mask of fields which need to be matched should be
3833  *    filled with 1.
3834  * 4. Mask of fields which needn't to be matched should be
3835  *    filled with 0.
3836  * 5. GTP profile supports GTPv1 only.
3837  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3838  */
3839 static int
3840 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3841                             const struct rte_flow_item *pattern,
3842                             struct rte_flow_error *error,
3843                             struct i40e_tunnel_filter_conf *filter)
3844 {
3845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3846         const struct rte_flow_item *item = pattern;
3847         const struct rte_flow_item_gtp *gtp_spec;
3848         const struct rte_flow_item_gtp *gtp_mask;
3849         enum rte_flow_item_type item_type;
3850
3851         if (!pf->gtp_support) {
3852                 rte_flow_error_set(error, EINVAL,
3853                                    RTE_FLOW_ERROR_TYPE_ITEM,
3854                                    item,
3855                                    "GTP is not supported by default.");
3856                 return -rte_errno;
3857         }
3858
3859         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3860                 if (item->last) {
3861                         rte_flow_error_set(error, EINVAL,
3862                                            RTE_FLOW_ERROR_TYPE_ITEM,
3863                                            item,
3864                                            "Not support range");
3865                         return -rte_errno;
3866                 }
3867                 item_type = item->type;
3868                 switch (item_type) {
3869                 case RTE_FLOW_ITEM_TYPE_ETH:
3870                         if (item->spec || item->mask) {
3871                                 rte_flow_error_set(error, EINVAL,
3872                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3873                                                    item,
3874                                                    "Invalid ETH item");
3875                                 return -rte_errno;
3876                         }
3877                         break;
3878                 case RTE_FLOW_ITEM_TYPE_IPV4:
3879                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3880                         /* IPv4 is used to describe protocol,
3881                          * spec and mask should be NULL.
3882                          */
3883                         if (item->spec || item->mask) {
3884                                 rte_flow_error_set(error, EINVAL,
3885                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3886                                                    item,
3887                                                    "Invalid IPv4 item");
3888                                 return -rte_errno;
3889                         }
3890                         break;
3891                 case RTE_FLOW_ITEM_TYPE_UDP:
3892                         if (item->spec || item->mask) {
3893                                 rte_flow_error_set(error, EINVAL,
3894                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3895                                                    item,
3896                                                    "Invalid UDP item");
3897                                 return -rte_errno;
3898                         }
3899                         break;
3900                 case RTE_FLOW_ITEM_TYPE_GTPC:
3901                 case RTE_FLOW_ITEM_TYPE_GTPU:
3902                         gtp_spec = item->spec;
3903                         gtp_mask = item->mask;
3904
3905                         if (!gtp_spec || !gtp_mask) {
3906                                 rte_flow_error_set(error, EINVAL,
3907                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3908                                                    item,
3909                                                    "Invalid GTP item");
3910                                 return -rte_errno;
3911                         }
3912
3913                         if (gtp_mask->v_pt_rsv_flags ||
3914                             gtp_mask->msg_type ||
3915                             gtp_mask->msg_len ||
3916                             gtp_mask->teid != UINT32_MAX) {
3917                                 rte_flow_error_set(error, EINVAL,
3918                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3919                                                    item,
3920                                                    "Invalid GTP mask");
3921                                 return -rte_errno;
3922                         }
3923
3924                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3925                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3926                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3927                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3928
3929                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3930
3931                         break;
3932                 default:
3933                         break;
3934                 }
3935         }
3936
3937         return 0;
3938 }
3939
3940 static int
3941 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3942                            const struct rte_flow_attr *attr,
3943                            const struct rte_flow_item pattern[],
3944                            const struct rte_flow_action actions[],
3945                            struct rte_flow_error *error,
3946                            union i40e_filter_t *filter)
3947 {
3948         struct i40e_tunnel_filter_conf *tunnel_filter =
3949                 &filter->consistent_tunnel_filter;
3950         int ret;
3951
3952         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3953                                           error, tunnel_filter);
3954         if (ret)
3955                 return ret;
3956
3957         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3958         if (ret)
3959                 return ret;
3960
3961         ret = i40e_flow_parse_attr(attr, error);
3962         if (ret)
3963                 return ret;
3964
3965         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3966
3967         return ret;
3968 }
3969
3970 /* 1. Last in item should be NULL as range is not supported.
3971  * 2. Supported filter types: QINQ.
3972  * 3. Mask of fields which need to be matched should be
3973  *    filled with 1.
3974  * 4. Mask of fields which needn't to be matched should be
3975  *    filled with 0.
3976  */
3977 static int
3978 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3979                               const struct rte_flow_item *pattern,
3980                               struct rte_flow_error *error,
3981                               struct i40e_tunnel_filter_conf *filter)
3982 {
3983         const struct rte_flow_item *item = pattern;
3984         const struct rte_flow_item_vlan *vlan_spec = NULL;
3985         const struct rte_flow_item_vlan *vlan_mask = NULL;
3986         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3987         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3988         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3989         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3990
3991         enum rte_flow_item_type item_type;
3992         bool vlan_flag = 0;
3993
3994         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3995                 if (item->last) {
3996                         rte_flow_error_set(error, EINVAL,
3997                                            RTE_FLOW_ERROR_TYPE_ITEM,
3998                                            item,
3999                                            "Not support range");
4000                         return -rte_errno;
4001                 }
4002                 item_type = item->type;
4003                 switch (item_type) {
4004                 case RTE_FLOW_ITEM_TYPE_ETH:
4005                         if (item->spec || item->mask) {
4006                                 rte_flow_error_set(error, EINVAL,
4007                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4008                                                    item,
4009                                                    "Invalid ETH item");
4010                                 return -rte_errno;
4011                         }
4012                         break;
4013                 case RTE_FLOW_ITEM_TYPE_VLAN:
4014                         vlan_spec = item->spec;
4015                         vlan_mask = item->mask;
4016
4017                         if (!(vlan_spec && vlan_mask)) {
4018                                 rte_flow_error_set(error, EINVAL,
4019                                            RTE_FLOW_ERROR_TYPE_ITEM,
4020                                            item,
4021                                            "Invalid vlan item");
4022                                 return -rte_errno;
4023                         }
4024
4025                         if (!vlan_flag) {
4026                                 o_vlan_spec = vlan_spec;
4027                                 o_vlan_mask = vlan_mask;
4028                                 vlan_flag = 1;
4029                         } else {
4030                                 i_vlan_spec = vlan_spec;
4031                                 i_vlan_mask = vlan_mask;
4032                                 vlan_flag = 0;
4033                         }
4034                         break;
4035
4036                 default:
4037                         break;
4038                 }
4039         }
4040
4041         /* Get filter specification */
4042         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4043                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4044                         (i_vlan_mask != NULL) &&
4045                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4046                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4047                         & I40E_TCI_MASK;
4048                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4049                         & I40E_TCI_MASK;
4050         } else {
4051                         rte_flow_error_set(error, EINVAL,
4052                                            RTE_FLOW_ERROR_TYPE_ITEM,
4053                                            NULL,
4054                                            "Invalid filter type");
4055                         return -rte_errno;
4056         }
4057
4058         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4059         return 0;
4060 }
4061
4062 static int
4063 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4064                               const struct rte_flow_attr *attr,
4065                               const struct rte_flow_item pattern[],
4066                               const struct rte_flow_action actions[],
4067                               struct rte_flow_error *error,
4068                               union i40e_filter_t *filter)
4069 {
4070         struct i40e_tunnel_filter_conf *tunnel_filter =
4071                 &filter->consistent_tunnel_filter;
4072         int ret;
4073
4074         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4075                                              error, tunnel_filter);
4076         if (ret)
4077                 return ret;
4078
4079         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4080         if (ret)
4081                 return ret;
4082
4083         ret = i40e_flow_parse_attr(attr, error);
4084         if (ret)
4085                 return ret;
4086
4087         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4088
4089         return ret;
4090 }
4091
4092 /**
4093  * This function is used to do configuration i40e existing RSS with rte_flow.
4094  * It also enable queue region configuration using flow API for i40e.
4095  * pattern can be used indicate what parameters will be include in flow,
4096  * like user_priority or flowtype for queue region or HASH function for RSS.
4097  * Action is used to transmit parameter like queue index and HASH
4098  * function for RSS, or flowtype for queue region configuration.
4099  * For example:
4100  * pattern:
4101  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4102  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4103  * Case 3: none, indicate RSS related will be parsed in action.
4104  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4105  * So, pattern choice is depened on the purpose of configuration of
4106  * that flow.
4107  * action:
4108  * action RSS will be uaed to transmit valid parameter with
4109  * struct rte_flow_action_rss for all the 3 case.
4110  */
4111 static int
4112 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4113                              const struct rte_flow_item *pattern,
4114                              struct rte_flow_error *error,
4115                              uint8_t *action_flag,
4116                              struct i40e_queue_regions *info)
4117 {
4118         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4119         const struct rte_flow_item *item = pattern;
4120         enum rte_flow_item_type item_type;
4121
4122         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4123                 return 0;
4124
4125         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4126                 if (item->last) {
4127                         rte_flow_error_set(error, EINVAL,
4128                                            RTE_FLOW_ERROR_TYPE_ITEM,
4129                                            item,
4130                                            "Not support range");
4131                         return -rte_errno;
4132                 }
4133                 item_type = item->type;
4134                 switch (item_type) {
4135                 case RTE_FLOW_ITEM_TYPE_ETH:
4136                         *action_flag = 1;
4137                         break;
4138                 case RTE_FLOW_ITEM_TYPE_VLAN:
4139                         vlan_spec = item->spec;
4140                         vlan_mask = item->mask;
4141                         if (vlan_spec && vlan_mask) {
4142                                 if (vlan_mask->tci ==
4143                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4144                                         info->region[0].user_priority[0] =
4145                                                 (vlan_spec->tci >> 13) & 0x7;
4146                                         info->region[0].user_priority_num = 1;
4147                                         info->queue_region_number = 1;
4148                                         *action_flag = 0;
4149                                 }
4150                         }
4151                         break;
4152                 default:
4153                         rte_flow_error_set(error, EINVAL,
4154                                         RTE_FLOW_ERROR_TYPE_ITEM,
4155                                         item,
4156                                         "Not support range");
4157                         return -rte_errno;
4158                 }
4159         }
4160
4161         return 0;
4162 }
4163
4164 static int
4165 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4166                             const struct rte_flow_action *actions,
4167                             struct rte_flow_error *error,
4168                             uint8_t action_flag,
4169                             struct i40e_queue_regions *conf_info,
4170                             union i40e_filter_t *filter)
4171 {
4172         const struct rte_flow_action *act;
4173         const struct rte_flow_action_rss *rss;
4174         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4175         struct i40e_queue_regions *info = &pf->queue_region;
4176         struct i40e_rte_flow_rss_conf *rss_config =
4177                         &filter->rss_conf;
4178         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4179         uint16_t i, j, n, tmp;
4180         uint32_t index = 0;
4181         uint64_t hf_bit = 1;
4182
4183         NEXT_ITEM_OF_ACTION(act, actions, index);
4184         rss = act->conf;
4185
4186         /**
4187          * rss only supports forwarding,
4188          * check if the first not void action is RSS.
4189          */
4190         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4191                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4192                 rte_flow_error_set(error, EINVAL,
4193                         RTE_FLOW_ERROR_TYPE_ACTION,
4194                         act, "Not supported action.");
4195                 return -rte_errno;
4196         }
4197
4198         if (action_flag) {
4199                 for (n = 0; n < 64; n++) {
4200                         if (rss->rss_conf->rss_hf & (hf_bit << n)) {
4201                                 conf_info->region[0].hw_flowtype[0] = n;
4202                                 conf_info->region[0].flowtype_num = 1;
4203                                 conf_info->queue_region_number = 1;
4204                                 break;
4205                         }
4206                 }
4207         }
4208
4209         for (n = 0; n < conf_info->queue_region_number; n++) {
4210                 if (conf_info->region[n].user_priority_num ||
4211                                 conf_info->region[n].flowtype_num) {
4212                         if (!((rte_is_power_of_2(rss->num)) &&
4213                                         rss->num <= 64)) {
4214                                 PMD_DRV_LOG(ERR, "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4215                                 "total number of queues do not exceed the VSI allocation");
4216                                 return -rte_errno;
4217                         }
4218
4219                         if (conf_info->region[n].user_priority[n] >=
4220                                         I40E_MAX_USER_PRIORITY) {
4221                                 PMD_DRV_LOG(ERR, "the user priority max index is 7");
4222                                 return -rte_errno;
4223                         }
4224
4225                         if (conf_info->region[n].hw_flowtype[n] >=
4226                                         I40E_FILTER_PCTYPE_MAX) {
4227                                 PMD_DRV_LOG(ERR, "the hw_flowtype or PCTYPE max index is 63");
4228                                 return -rte_errno;
4229                         }
4230
4231                         if (rss_info->num < rss->num ||
4232                                 rss_info->queue[0] < rss->queue[0] ||
4233                                 (rss->queue[0] + rss->num >
4234                                         rss_info->num + rss_info->queue[0])) {
4235                                 rte_flow_error_set(error, EINVAL,
4236                                         RTE_FLOW_ERROR_TYPE_ACTION,
4237                                         act,
4238                                         "no valid queues");
4239                                 return -rte_errno;
4240                         }
4241
4242                         for (i = 0; i < info->queue_region_number; i++) {
4243                                 if (info->region[i].queue_num == rss->num &&
4244                                         info->region[i].queue_start_index ==
4245                                                 rss->queue[0])
4246                                         break;
4247                         }
4248
4249                         if (i == info->queue_region_number) {
4250                                 if (i > I40E_REGION_MAX_INDEX) {
4251                                         PMD_DRV_LOG(ERR, "the queue region max index is 7");
4252                                         return -rte_errno;
4253                                 }
4254
4255                                 info->region[i].queue_num =
4256                                         rss->num;
4257                                 info->region[i].queue_start_index =
4258                                         rss->queue[0];
4259                                 info->region[i].region_id =
4260                                         info->queue_region_number;
4261
4262                                 j = info->region[i].user_priority_num;
4263                                 tmp = conf_info->region[n].user_priority[0];
4264                                 if (conf_info->region[n].user_priority_num) {
4265                                         info->region[i].user_priority[j] = tmp;
4266                                         info->region[i].user_priority_num++;
4267                                 }
4268
4269                                 j = info->region[i].flowtype_num;
4270                                 tmp = conf_info->region[n].hw_flowtype[0];
4271                                 if (conf_info->region[n].flowtype_num) {
4272                                         info->region[i].hw_flowtype[j] = tmp;
4273                                         info->region[i].flowtype_num++;
4274                                 }
4275                                 info->queue_region_number++;
4276                         } else {
4277                                 j = info->region[i].user_priority_num;
4278                                 tmp = conf_info->region[n].user_priority[0];
4279                                 if (conf_info->region[n].user_priority_num) {
4280                                         info->region[i].user_priority[j] = tmp;
4281                                         info->region[i].user_priority_num++;
4282                                 }
4283
4284                                 j = info->region[i].flowtype_num;
4285                                 tmp = conf_info->region[n].hw_flowtype[0];
4286                                 if (conf_info->region[n].flowtype_num) {
4287                                         info->region[i].hw_flowtype[j] = tmp;
4288                                         info->region[i].flowtype_num++;
4289                                 }
4290                         }
4291                 }
4292
4293                 rss_config->queue_region_conf = TRUE;
4294         }
4295
4296         if (rss_config->queue_region_conf)
4297                 return 0;
4298
4299         if (!rss || !rss->num) {
4300                 rte_flow_error_set(error, EINVAL,
4301                                 RTE_FLOW_ERROR_TYPE_ACTION,
4302                                 act,
4303                                 "no valid queues");
4304                 return -rte_errno;
4305         }
4306
4307         for (n = 0; n < rss->num; n++) {
4308                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4309                         rte_flow_error_set(error, EINVAL,
4310                                    RTE_FLOW_ERROR_TYPE_ACTION,
4311                                    act,
4312                                    "queue id > max number of queues");
4313                         return -rte_errno;
4314                 }
4315         }
4316         if (rss->rss_conf)
4317                 rss_config->rss_conf = *rss->rss_conf;
4318         else
4319                 rss_config->rss_conf.rss_hf =
4320                         pf->adapter->flow_types_mask;
4321
4322         for (n = 0; n < rss->num; ++n)
4323                 rss_config->queue[n] = rss->queue[n];
4324         rss_config->num = rss->num;
4325         index++;
4326
4327         /* check if the next not void action is END */
4328         NEXT_ITEM_OF_ACTION(act, actions, index);
4329         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4330                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4331                 rte_flow_error_set(error, EINVAL,
4332                         RTE_FLOW_ERROR_TYPE_ACTION,
4333                         act, "Not supported action.");
4334                 return -rte_errno;
4335         }
4336         rss_config->queue_region_conf = FALSE;
4337
4338         return 0;
4339 }
4340
4341 static int
4342 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4343                         const struct rte_flow_attr *attr,
4344                         const struct rte_flow_item pattern[],
4345                         const struct rte_flow_action actions[],
4346                         union i40e_filter_t *filter,
4347                         struct rte_flow_error *error)
4348 {
4349         int ret;
4350         struct i40e_queue_regions info;
4351         uint8_t action_flag = 0;
4352
4353         memset(&info, 0, sizeof(struct i40e_queue_regions));
4354
4355         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4356                                         error, &action_flag, &info);
4357         if (ret)
4358                 return ret;
4359
4360         ret = i40e_flow_parse_rss_action(dev, actions, error,
4361                                         action_flag, &info, filter);
4362         if (ret)
4363                 return ret;
4364
4365         ret = i40e_flow_parse_attr(attr, error);
4366         if (ret)
4367                 return ret;
4368
4369         cons_filter_type = RTE_ETH_FILTER_HASH;
4370
4371         return 0;
4372 }
4373
4374 static int
4375 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4376                 struct i40e_rte_flow_rss_conf *conf)
4377 {
4378         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4379         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4380
4381         if (conf->queue_region_conf) {
4382                 i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4383                 conf->queue_region_conf = 0;
4384         } else {
4385                 i40e_config_rss_filter(pf, conf, 1);
4386         }
4387         return 0;
4388 }
4389
4390 static int
4391 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4392                 struct i40e_rte_flow_rss_conf *conf)
4393 {
4394         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4395         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4396
4397         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4398
4399         i40e_config_rss_filter(pf, conf, 0);
4400         return 0;
4401 }
4402
4403 static int
4404 i40e_flow_validate(struct rte_eth_dev *dev,
4405                    const struct rte_flow_attr *attr,
4406                    const struct rte_flow_item pattern[],
4407                    const struct rte_flow_action actions[],
4408                    struct rte_flow_error *error)
4409 {
4410         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4411         parse_filter_t parse_filter;
4412         uint32_t item_num = 0; /* non-void item number of pattern*/
4413         uint32_t i = 0;
4414         bool flag = false;
4415         int ret = I40E_NOT_SUPPORTED;
4416
4417         if (!pattern) {
4418                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4419                                    NULL, "NULL pattern.");
4420                 return -rte_errno;
4421         }
4422
4423         if (!actions) {
4424                 rte_flow_error_set(error, EINVAL,
4425                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4426                                    NULL, "NULL action.");
4427                 return -rte_errno;
4428         }
4429
4430         if (!attr) {
4431                 rte_flow_error_set(error, EINVAL,
4432                                    RTE_FLOW_ERROR_TYPE_ATTR,
4433                                    NULL, "NULL attribute.");
4434                 return -rte_errno;
4435         }
4436
4437         memset(&cons_filter, 0, sizeof(cons_filter));
4438
4439         /* Get the non-void item of action */
4440         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4441                 i++;
4442
4443         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4444                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4445                                         actions, &cons_filter, error);
4446                 return ret;
4447         }
4448
4449         i = 0;
4450         /* Get the non-void item number of pattern */
4451         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4452                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4453                         item_num++;
4454                 i++;
4455         }
4456         item_num++;
4457
4458         items = rte_zmalloc("i40e_pattern",
4459                             item_num * sizeof(struct rte_flow_item), 0);
4460         if (!items) {
4461                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4462                                    NULL, "No memory for PMD internal items.");
4463                 return -ENOMEM;
4464         }
4465
4466         i40e_pattern_skip_void_item(items, pattern);
4467
4468         i = 0;
4469         do {
4470                 parse_filter = i40e_find_parse_filter_func(items, &i);
4471                 if (!parse_filter && !flag) {
4472                         rte_flow_error_set(error, EINVAL,
4473                                            RTE_FLOW_ERROR_TYPE_ITEM,
4474                                            pattern, "Unsupported pattern");
4475                         rte_free(items);
4476                         return -rte_errno;
4477                 }
4478                 if (parse_filter)
4479                         ret = parse_filter(dev, attr, items, actions,
4480                                            error, &cons_filter);
4481                 flag = true;
4482         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4483
4484         rte_free(items);
4485
4486         return ret;
4487 }
4488
4489 static struct rte_flow *
4490 i40e_flow_create(struct rte_eth_dev *dev,
4491                  const struct rte_flow_attr *attr,
4492                  const struct rte_flow_item pattern[],
4493                  const struct rte_flow_action actions[],
4494                  struct rte_flow_error *error)
4495 {
4496         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4497         struct rte_flow *flow;
4498         int ret;
4499
4500         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4501         if (!flow) {
4502                 rte_flow_error_set(error, ENOMEM,
4503                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4504                                    "Failed to allocate memory");
4505                 return flow;
4506         }
4507
4508         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4509         if (ret < 0)
4510                 return NULL;
4511
4512         switch (cons_filter_type) {
4513         case RTE_ETH_FILTER_ETHERTYPE:
4514                 ret = i40e_ethertype_filter_set(pf,
4515                                         &cons_filter.ethertype_filter, 1);
4516                 if (ret)
4517                         goto free_flow;
4518                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4519                                         i40e_ethertype_filter_list);
4520                 break;
4521         case RTE_ETH_FILTER_FDIR:
4522                 ret = i40e_flow_add_del_fdir_filter(dev,
4523                                        &cons_filter.fdir_filter, 1);
4524                 if (ret)
4525                         goto free_flow;
4526                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4527                                         i40e_fdir_filter_list);
4528                 break;
4529         case RTE_ETH_FILTER_TUNNEL:
4530                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4531                             &cons_filter.consistent_tunnel_filter, 1);
4532                 if (ret)
4533                         goto free_flow;
4534                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4535                                         i40e_tunnel_filter_list);
4536                 break;
4537         case RTE_ETH_FILTER_HASH:
4538                 ret = i40e_config_rss_filter_set(dev,
4539                             &cons_filter.rss_conf);
4540                 flow->rule = &pf->rss_info;
4541                 break;
4542         default:
4543                 goto free_flow;
4544         }
4545
4546         flow->filter_type = cons_filter_type;
4547         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4548         return flow;
4549
4550 free_flow:
4551         rte_flow_error_set(error, -ret,
4552                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4553                            "Failed to create flow.");
4554         rte_free(flow);
4555         return NULL;
4556 }
4557
4558 static int
4559 i40e_flow_destroy(struct rte_eth_dev *dev,
4560                   struct rte_flow *flow,
4561                   struct rte_flow_error *error)
4562 {
4563         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4564         enum rte_filter_type filter_type = flow->filter_type;
4565         int ret = 0;
4566
4567         switch (filter_type) {
4568         case RTE_ETH_FILTER_ETHERTYPE:
4569                 ret = i40e_flow_destroy_ethertype_filter(pf,
4570                          (struct i40e_ethertype_filter *)flow->rule);
4571                 break;
4572         case RTE_ETH_FILTER_TUNNEL:
4573                 ret = i40e_flow_destroy_tunnel_filter(pf,
4574                               (struct i40e_tunnel_filter *)flow->rule);
4575                 break;
4576         case RTE_ETH_FILTER_FDIR:
4577                 ret = i40e_flow_add_del_fdir_filter(dev,
4578                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4579                 break;
4580         case RTE_ETH_FILTER_HASH:
4581                 ret = i40e_config_rss_filter_del(dev,
4582                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4583                 break;
4584         default:
4585                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4586                             filter_type);
4587                 ret = -EINVAL;
4588                 break;
4589         }
4590
4591         if (!ret) {
4592                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4593                 rte_free(flow);
4594         } else
4595                 rte_flow_error_set(error, -ret,
4596                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4597                                    "Failed to destroy flow.");
4598
4599         return ret;
4600 }
4601
4602 static int
4603 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4604                                    struct i40e_ethertype_filter *filter)
4605 {
4606         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4607         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4608         struct i40e_ethertype_filter *node;
4609         struct i40e_control_filter_stats stats;
4610         uint16_t flags = 0;
4611         int ret = 0;
4612
4613         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4614                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4615         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4616                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4617         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4618
4619         memset(&stats, 0, sizeof(stats));
4620         ret = i40e_aq_add_rem_control_packet_filter(hw,
4621                                     filter->input.mac_addr.addr_bytes,
4622                                     filter->input.ether_type,
4623                                     flags, pf->main_vsi->seid,
4624                                     filter->queue, 0, &stats, NULL);
4625         if (ret < 0)
4626                 return ret;
4627
4628         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4629         if (!node)
4630                 return -EINVAL;
4631
4632         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4633
4634         return ret;
4635 }
4636
4637 static int
4638 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4639                                 struct i40e_tunnel_filter *filter)
4640 {
4641         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4642         struct i40e_vsi *vsi;
4643         struct i40e_pf_vf *vf;
4644         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4645         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4646         struct i40e_tunnel_filter *node;
4647         bool big_buffer = 0;
4648         int ret = 0;
4649
4650         memset(&cld_filter, 0, sizeof(cld_filter));
4651         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4652                         (struct ether_addr *)&cld_filter.element.outer_mac);
4653         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4654                         (struct ether_addr *)&cld_filter.element.inner_mac);
4655         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4656         cld_filter.element.flags = filter->input.flags;
4657         cld_filter.element.tenant_id = filter->input.tenant_id;
4658         cld_filter.element.queue_number = filter->queue;
4659         rte_memcpy(cld_filter.general_fields,
4660                    filter->input.general_fields,
4661                    sizeof(cld_filter.general_fields));
4662
4663         if (!filter->is_to_vf)
4664                 vsi = pf->main_vsi;
4665         else {
4666                 vf = &pf->vfs[filter->vf_id];
4667                 vsi = vf->vsi;
4668         }
4669
4670         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4671             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4672             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4673             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4674             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4675             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4676                 big_buffer = 1;
4677
4678         if (big_buffer)
4679                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4680                                                               &cld_filter, 1);
4681         else
4682                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4683                                                    &cld_filter.element, 1);
4684         if (ret < 0)
4685                 return -ENOTSUP;
4686
4687         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4688         if (!node)
4689                 return -EINVAL;
4690
4691         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4692
4693         return ret;
4694 }
4695
4696 static int
4697 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4698 {
4699         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4700         int ret;
4701
4702         ret = i40e_flow_flush_fdir_filter(pf);
4703         if (ret) {
4704                 rte_flow_error_set(error, -ret,
4705                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4706                                    "Failed to flush FDIR flows.");
4707                 return -rte_errno;
4708         }
4709
4710         ret = i40e_flow_flush_ethertype_filter(pf);
4711         if (ret) {
4712                 rte_flow_error_set(error, -ret,
4713                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4714                                    "Failed to ethertype flush flows.");
4715                 return -rte_errno;
4716         }
4717
4718         ret = i40e_flow_flush_tunnel_filter(pf);
4719         if (ret) {
4720                 rte_flow_error_set(error, -ret,
4721                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4722                                    "Failed to flush tunnel flows.");
4723                 return -rte_errno;
4724         }
4725
4726         ret = i40e_flow_flush_rss_filter(dev);
4727         if (ret) {
4728                 rte_flow_error_set(error, -ret,
4729                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4730                                    "Failed to flush rss flows.");
4731                 return -rte_errno;
4732         }
4733
4734         return ret;
4735 }
4736
4737 static int
4738 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4739 {
4740         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4741         struct i40e_fdir_info *fdir_info = &pf->fdir;
4742         struct i40e_fdir_filter *fdir_filter;
4743         enum i40e_filter_pctype pctype;
4744         struct rte_flow *flow;
4745         void *temp;
4746         int ret;
4747
4748         ret = i40e_fdir_flush(dev);
4749         if (!ret) {
4750                 /* Delete FDIR filters in FDIR list. */
4751                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4752                         ret = i40e_sw_fdir_filter_del(pf,
4753                                                       &fdir_filter->fdir.input);
4754                         if (ret < 0)
4755                                 return ret;
4756                 }
4757
4758                 /* Delete FDIR flows in flow list. */
4759                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4760                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4761                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4762                                 rte_free(flow);
4763                         }
4764                 }
4765
4766                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4767                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4768                         pf->fdir.inset_flag[pctype] = 0;
4769         }
4770
4771         return ret;
4772 }
4773
4774 /* Flush all ethertype filters */
4775 static int
4776 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4777 {
4778         struct i40e_ethertype_filter_list
4779                 *ethertype_list = &pf->ethertype.ethertype_list;
4780         struct i40e_ethertype_filter *filter;
4781         struct rte_flow *flow;
4782         void *temp;
4783         int ret = 0;
4784
4785         while ((filter = TAILQ_FIRST(ethertype_list))) {
4786                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4787                 if (ret)
4788                         return ret;
4789         }
4790
4791         /* Delete ethertype flows in flow list. */
4792         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4793                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4794                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4795                         rte_free(flow);
4796                 }
4797         }
4798
4799         return ret;
4800 }
4801
4802 /* Flush all tunnel filters */
4803 static int
4804 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4805 {
4806         struct i40e_tunnel_filter_list
4807                 *tunnel_list = &pf->tunnel.tunnel_list;
4808         struct i40e_tunnel_filter *filter;
4809         struct rte_flow *flow;
4810         void *temp;
4811         int ret = 0;
4812
4813         while ((filter = TAILQ_FIRST(tunnel_list))) {
4814                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4815                 if (ret)
4816                         return ret;
4817         }
4818
4819         /* Delete tunnel flows in flow list. */
4820         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4821                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4822                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4823                         rte_free(flow);
4824                 }
4825         }
4826
4827         return ret;
4828 }
4829
4830 /* remove the rss filter */
4831 static int
4832 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4833 {
4834         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4835         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4836         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4837         int32_t ret = -EINVAL;
4838
4839         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4840
4841         if (rss_info->num)
4842                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
4843         return ret;
4844 }