drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_eth_ctrl.h>
  19 #include <rte_tailq.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "i40e_logs.h"
  23 #include "base/i40e_type.h"
  24 #include "base/i40e_prototype.h"
  25 #include "i40e_ethdev.h"
  26
  27 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  28 #define I40E_IPV6_FRAG_HEADER   44
  29 #define I40E_TENANT_ARRAY_NUM   3
  30 #define I40E_TCI_MASK           0xFFFF
  31
  32 static int i40e_flow_validate(struct rte_eth_dev *dev,
  33                               const struct rte_flow_attr *attr,
  34                               const struct rte_flow_item pattern[],
  35                               const struct rte_flow_action actions[],
  36                               struct rte_flow_error *error);
  37 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  38                                          const struct rte_flow_attr *attr,
  39                                          const struct rte_flow_item pattern[],
  40                                          const struct rte_flow_action actions[],
  41                                          struct rte_flow_error *error);
  42 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  43                              struct rte_flow *flow,
  44                              struct rte_flow_error *error);
  45 static int i40e_flow_flush(struct rte_eth_dev *dev,
  46                            struct rte_flow_error *error);
  47 static int
  48 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  49                                   const struct rte_flow_item *pattern,
  50                                   struct rte_flow_error *error,
  51                                   struct rte_eth_ethertype_filter *filter);
  52 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  53                                     const struct rte_flow_action *actions,
  54                                     struct rte_flow_error *error,
  55                                     struct rte_eth_ethertype_filter *filter);
  56 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  57                                         const struct rte_flow_attr *attr,
  58                                         const struct rte_flow_item *pattern,
  59                                         struct rte_flow_error *error,
  60                                         struct i40e_fdir_filter_conf *filter);
  61 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  62                                        const struct rte_flow_action *actions,
  63                                        struct rte_flow_error *error,
  64                                        struct i40e_fdir_filter_conf *filter);
  65 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  66                                  const struct rte_flow_action *actions,
  67                                  struct rte_flow_error *error,
  68                                  struct i40e_tunnel_filter_conf *filter);
  69 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  70                                 struct rte_flow_error *error);
  71 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  72                                     const struct rte_flow_attr *attr,
  73                                     const struct rte_flow_item pattern[],
  74                                     const struct rte_flow_action actions[],
  75                                     struct rte_flow_error *error,
  76                                     union i40e_filter_t *filter);
  77 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  78                                        const struct rte_flow_attr *attr,
  79                                        const struct rte_flow_item pattern[],
  80                                        const struct rte_flow_action actions[],
  81                                        struct rte_flow_error *error,
  82                                        union i40e_filter_t *filter);
  83 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  84                                         const struct rte_flow_attr *attr,
  85                                         const struct rte_flow_item pattern[],
  86                                         const struct rte_flow_action actions[],
  87                                         struct rte_flow_error *error,
  88                                         union i40e_filter_t *filter);
  89 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  90                                         const struct rte_flow_attr *attr,
  91                                         const struct rte_flow_item pattern[],
  92                                         const struct rte_flow_action actions[],
  93                                         struct rte_flow_error *error,
  94                                         union i40e_filter_t *filter);
  95 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  96                                        const struct rte_flow_attr *attr,
  97                                        const struct rte_flow_item pattern[],
  98                                        const struct rte_flow_action actions[],
  99                                        struct rte_flow_error *error,
 100                                        union i40e_filter_t *filter);
 101 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 102                                       const struct rte_flow_attr *attr,
 103                                       const struct rte_flow_item pattern[],
 104                                       const struct rte_flow_action actions[],
 105                                       struct rte_flow_error *error,
 106                                       union i40e_filter_t *filter);
 107 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 108                                       struct i40e_ethertype_filter *filter);
 109 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 110                                            struct i40e_tunnel_filter *filter);
 111 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 112 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 113 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 114 static int
 115 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 116 static int
 117 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 118                               const struct rte_flow_attr *attr,
 119                               const struct rte_flow_item pattern[],
 120                               const struct rte_flow_action actions[],
 121                               struct rte_flow_error *error,
 122                               union i40e_filter_t *filter);
 123 static int
 124 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 125                               const struct rte_flow_item *pattern,
 126                               struct rte_flow_error *error,
 127                               struct i40e_tunnel_filter_conf *filter);
 128
 129 const struct rte_flow_ops i40e_flow_ops = {
 130         .validate = i40e_flow_validate,
 131         .create = i40e_flow_create,
 132         .destroy = i40e_flow_destroy,
 133         .flush = i40e_flow_flush,
 134 };
 135
 136 union i40e_filter_t cons_filter;
 137 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 138
 139 /* Pattern matched ethertype filter */
 140 static enum rte_flow_item_type pattern_ethertype[] = {
 141         RTE_FLOW_ITEM_TYPE_ETH,
 142         RTE_FLOW_ITEM_TYPE_END,
 143 };
 144
 145 /* Pattern matched flow director filter */
 146 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 147         RTE_FLOW_ITEM_TYPE_ETH,
 148         RTE_FLOW_ITEM_TYPE_IPV4,
 149         RTE_FLOW_ITEM_TYPE_END,
 150 };
 151
 152 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 153         RTE_FLOW_ITEM_TYPE_ETH,
 154         RTE_FLOW_ITEM_TYPE_IPV4,
 155         RTE_FLOW_ITEM_TYPE_UDP,
 156         RTE_FLOW_ITEM_TYPE_END,
 157 };
 158
 159 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 160         RTE_FLOW_ITEM_TYPE_ETH,
 161         RTE_FLOW_ITEM_TYPE_IPV4,
 162         RTE_FLOW_ITEM_TYPE_TCP,
 163         RTE_FLOW_ITEM_TYPE_END,
 164 };
 165
 166 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 167         RTE_FLOW_ITEM_TYPE_ETH,
 168         RTE_FLOW_ITEM_TYPE_IPV4,
 169         RTE_FLOW_ITEM_TYPE_SCTP,
 170         RTE_FLOW_ITEM_TYPE_END,
 171 };
 172
 173 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 174         RTE_FLOW_ITEM_TYPE_ETH,
 175         RTE_FLOW_ITEM_TYPE_IPV4,
 176         RTE_FLOW_ITEM_TYPE_UDP,
 177         RTE_FLOW_ITEM_TYPE_GTPC,
 178         RTE_FLOW_ITEM_TYPE_END,
 179 };
 180
 181 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 182         RTE_FLOW_ITEM_TYPE_ETH,
 183         RTE_FLOW_ITEM_TYPE_IPV4,
 184         RTE_FLOW_ITEM_TYPE_UDP,
 185         RTE_FLOW_ITEM_TYPE_GTPU,
 186         RTE_FLOW_ITEM_TYPE_END,
 187 };
 188
 189 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 190         RTE_FLOW_ITEM_TYPE_ETH,
 191         RTE_FLOW_ITEM_TYPE_IPV4,
 192         RTE_FLOW_ITEM_TYPE_UDP,
 193         RTE_FLOW_ITEM_TYPE_GTPU,
 194         RTE_FLOW_ITEM_TYPE_IPV4,
 195         RTE_FLOW_ITEM_TYPE_END,
 196 };
 197
 198 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 199         RTE_FLOW_ITEM_TYPE_ETH,
 200         RTE_FLOW_ITEM_TYPE_IPV4,
 201         RTE_FLOW_ITEM_TYPE_UDP,
 202         RTE_FLOW_ITEM_TYPE_GTPU,
 203         RTE_FLOW_ITEM_TYPE_IPV6,
 204         RTE_FLOW_ITEM_TYPE_END,
 205 };
 206
 207 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 208         RTE_FLOW_ITEM_TYPE_ETH,
 209         RTE_FLOW_ITEM_TYPE_IPV6,
 210         RTE_FLOW_ITEM_TYPE_END,
 211 };
 212
 213 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 214         RTE_FLOW_ITEM_TYPE_ETH,
 215         RTE_FLOW_ITEM_TYPE_IPV6,
 216         RTE_FLOW_ITEM_TYPE_UDP,
 217         RTE_FLOW_ITEM_TYPE_END,
 218 };
 219
 220 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 221         RTE_FLOW_ITEM_TYPE_ETH,
 222         RTE_FLOW_ITEM_TYPE_IPV6,
 223         RTE_FLOW_ITEM_TYPE_TCP,
 224         RTE_FLOW_ITEM_TYPE_END,
 225 };
 226
 227 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 228         RTE_FLOW_ITEM_TYPE_ETH,
 229         RTE_FLOW_ITEM_TYPE_IPV6,
 230         RTE_FLOW_ITEM_TYPE_SCTP,
 231         RTE_FLOW_ITEM_TYPE_END,
 232 };
 233
 234 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 235         RTE_FLOW_ITEM_TYPE_ETH,
 236         RTE_FLOW_ITEM_TYPE_IPV6,
 237         RTE_FLOW_ITEM_TYPE_UDP,
 238         RTE_FLOW_ITEM_TYPE_GTPC,
 239         RTE_FLOW_ITEM_TYPE_END,
 240 };
 241
 242 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 243         RTE_FLOW_ITEM_TYPE_ETH,
 244         RTE_FLOW_ITEM_TYPE_IPV6,
 245         RTE_FLOW_ITEM_TYPE_UDP,
 246         RTE_FLOW_ITEM_TYPE_GTPU,
 247         RTE_FLOW_ITEM_TYPE_END,
 248 };
 249
 250 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 251         RTE_FLOW_ITEM_TYPE_ETH,
 252         RTE_FLOW_ITEM_TYPE_IPV6,
 253         RTE_FLOW_ITEM_TYPE_UDP,
 254         RTE_FLOW_ITEM_TYPE_GTPU,
 255         RTE_FLOW_ITEM_TYPE_IPV4,
 256         RTE_FLOW_ITEM_TYPE_END,
 257 };
 258
 259 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 260         RTE_FLOW_ITEM_TYPE_ETH,
 261         RTE_FLOW_ITEM_TYPE_IPV6,
 262         RTE_FLOW_ITEM_TYPE_UDP,
 263         RTE_FLOW_ITEM_TYPE_GTPU,
 264         RTE_FLOW_ITEM_TYPE_IPV6,
 265         RTE_FLOW_ITEM_TYPE_END,
 266 };
 267
 268 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 269         RTE_FLOW_ITEM_TYPE_ETH,
 270         RTE_FLOW_ITEM_TYPE_RAW,
 271         RTE_FLOW_ITEM_TYPE_END,
 272 };
 273
 274 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 275         RTE_FLOW_ITEM_TYPE_ETH,
 276         RTE_FLOW_ITEM_TYPE_RAW,
 277         RTE_FLOW_ITEM_TYPE_RAW,
 278         RTE_FLOW_ITEM_TYPE_END,
 279 };
 280
 281 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 282         RTE_FLOW_ITEM_TYPE_ETH,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_RAW,
 285         RTE_FLOW_ITEM_TYPE_RAW,
 286         RTE_FLOW_ITEM_TYPE_END,
 287 };
 288
 289 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 290         RTE_FLOW_ITEM_TYPE_ETH,
 291         RTE_FLOW_ITEM_TYPE_IPV4,
 292         RTE_FLOW_ITEM_TYPE_RAW,
 293         RTE_FLOW_ITEM_TYPE_END,
 294 };
 295
 296 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 297         RTE_FLOW_ITEM_TYPE_ETH,
 298         RTE_FLOW_ITEM_TYPE_IPV4,
 299         RTE_FLOW_ITEM_TYPE_RAW,
 300         RTE_FLOW_ITEM_TYPE_RAW,
 301         RTE_FLOW_ITEM_TYPE_END,
 302 };
 303
 304 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 305         RTE_FLOW_ITEM_TYPE_ETH,
 306         RTE_FLOW_ITEM_TYPE_IPV4,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_RAW,
 309         RTE_FLOW_ITEM_TYPE_RAW,
 310         RTE_FLOW_ITEM_TYPE_END,
 311 };
 312
 313 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 314         RTE_FLOW_ITEM_TYPE_ETH,
 315         RTE_FLOW_ITEM_TYPE_IPV4,
 316         RTE_FLOW_ITEM_TYPE_UDP,
 317         RTE_FLOW_ITEM_TYPE_RAW,
 318         RTE_FLOW_ITEM_TYPE_END,
 319 };
 320
 321 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 322         RTE_FLOW_ITEM_TYPE_ETH,
 323         RTE_FLOW_ITEM_TYPE_IPV4,
 324         RTE_FLOW_ITEM_TYPE_UDP,
 325         RTE_FLOW_ITEM_TYPE_RAW,
 326         RTE_FLOW_ITEM_TYPE_RAW,
 327         RTE_FLOW_ITEM_TYPE_END,
 328 };
 329
 330 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 331         RTE_FLOW_ITEM_TYPE_ETH,
 332         RTE_FLOW_ITEM_TYPE_IPV4,
 333         RTE_FLOW_ITEM_TYPE_UDP,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_RAW,
 336         RTE_FLOW_ITEM_TYPE_RAW,
 337         RTE_FLOW_ITEM_TYPE_END,
 338 };
 339
 340 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 341         RTE_FLOW_ITEM_TYPE_ETH,
 342         RTE_FLOW_ITEM_TYPE_IPV4,
 343         RTE_FLOW_ITEM_TYPE_TCP,
 344         RTE_FLOW_ITEM_TYPE_RAW,
 345         RTE_FLOW_ITEM_TYPE_END,
 346 };
 347
 348 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 349         RTE_FLOW_ITEM_TYPE_ETH,
 350         RTE_FLOW_ITEM_TYPE_IPV4,
 351         RTE_FLOW_ITEM_TYPE_TCP,
 352         RTE_FLOW_ITEM_TYPE_RAW,
 353         RTE_FLOW_ITEM_TYPE_RAW,
 354         RTE_FLOW_ITEM_TYPE_END,
 355 };
 356
 357 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 358         RTE_FLOW_ITEM_TYPE_ETH,
 359         RTE_FLOW_ITEM_TYPE_IPV4,
 360         RTE_FLOW_ITEM_TYPE_TCP,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_RAW,
 363         RTE_FLOW_ITEM_TYPE_RAW,
 364         RTE_FLOW_ITEM_TYPE_END,
 365 };
 366
 367 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 368         RTE_FLOW_ITEM_TYPE_ETH,
 369         RTE_FLOW_ITEM_TYPE_IPV4,
 370         RTE_FLOW_ITEM_TYPE_SCTP,
 371         RTE_FLOW_ITEM_TYPE_RAW,
 372         RTE_FLOW_ITEM_TYPE_END,
 373 };
 374
 375 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 376         RTE_FLOW_ITEM_TYPE_ETH,
 377         RTE_FLOW_ITEM_TYPE_IPV4,
 378         RTE_FLOW_ITEM_TYPE_SCTP,
 379         RTE_FLOW_ITEM_TYPE_RAW,
 380         RTE_FLOW_ITEM_TYPE_RAW,
 381         RTE_FLOW_ITEM_TYPE_END,
 382 };
 383
 384 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 385         RTE_FLOW_ITEM_TYPE_ETH,
 386         RTE_FLOW_ITEM_TYPE_IPV4,
 387         RTE_FLOW_ITEM_TYPE_SCTP,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_RAW,
 390         RTE_FLOW_ITEM_TYPE_RAW,
 391         RTE_FLOW_ITEM_TYPE_END,
 392 };
 393
 394 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 395         RTE_FLOW_ITEM_TYPE_ETH,
 396         RTE_FLOW_ITEM_TYPE_IPV6,
 397         RTE_FLOW_ITEM_TYPE_RAW,
 398         RTE_FLOW_ITEM_TYPE_END,
 399 };
 400
 401 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 402         RTE_FLOW_ITEM_TYPE_ETH,
 403         RTE_FLOW_ITEM_TYPE_IPV6,
 404         RTE_FLOW_ITEM_TYPE_RAW,
 405         RTE_FLOW_ITEM_TYPE_RAW,
 406         RTE_FLOW_ITEM_TYPE_END,
 407 };
 408
 409 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 410         RTE_FLOW_ITEM_TYPE_ETH,
 411         RTE_FLOW_ITEM_TYPE_IPV6,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_RAW,
 414         RTE_FLOW_ITEM_TYPE_RAW,
 415         RTE_FLOW_ITEM_TYPE_END,
 416 };
 417
 418 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 419         RTE_FLOW_ITEM_TYPE_ETH,
 420         RTE_FLOW_ITEM_TYPE_IPV6,
 421         RTE_FLOW_ITEM_TYPE_UDP,
 422         RTE_FLOW_ITEM_TYPE_RAW,
 423         RTE_FLOW_ITEM_TYPE_END,
 424 };
 425
 426 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 427         RTE_FLOW_ITEM_TYPE_ETH,
 428         RTE_FLOW_ITEM_TYPE_IPV6,
 429         RTE_FLOW_ITEM_TYPE_UDP,
 430         RTE_FLOW_ITEM_TYPE_RAW,
 431         RTE_FLOW_ITEM_TYPE_RAW,
 432         RTE_FLOW_ITEM_TYPE_END,
 433 };
 434
 435 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 436         RTE_FLOW_ITEM_TYPE_ETH,
 437         RTE_FLOW_ITEM_TYPE_IPV6,
 438         RTE_FLOW_ITEM_TYPE_UDP,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_RAW,
 441         RTE_FLOW_ITEM_TYPE_RAW,
 442         RTE_FLOW_ITEM_TYPE_END,
 443 };
 444
 445 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 446         RTE_FLOW_ITEM_TYPE_ETH,
 447         RTE_FLOW_ITEM_TYPE_IPV6,
 448         RTE_FLOW_ITEM_TYPE_TCP,
 449         RTE_FLOW_ITEM_TYPE_RAW,
 450         RTE_FLOW_ITEM_TYPE_END,
 451 };
 452
 453 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 454         RTE_FLOW_ITEM_TYPE_ETH,
 455         RTE_FLOW_ITEM_TYPE_IPV6,
 456         RTE_FLOW_ITEM_TYPE_TCP,
 457         RTE_FLOW_ITEM_TYPE_RAW,
 458         RTE_FLOW_ITEM_TYPE_RAW,
 459         RTE_FLOW_ITEM_TYPE_END,
 460 };
 461
 462 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 463         RTE_FLOW_ITEM_TYPE_ETH,
 464         RTE_FLOW_ITEM_TYPE_IPV6,
 465         RTE_FLOW_ITEM_TYPE_TCP,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_RAW,
 468         RTE_FLOW_ITEM_TYPE_RAW,
 469         RTE_FLOW_ITEM_TYPE_END,
 470 };
 471
 472 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 473         RTE_FLOW_ITEM_TYPE_ETH,
 474         RTE_FLOW_ITEM_TYPE_IPV6,
 475         RTE_FLOW_ITEM_TYPE_SCTP,
 476         RTE_FLOW_ITEM_TYPE_RAW,
 477         RTE_FLOW_ITEM_TYPE_END,
 478 };
 479
 480 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 481         RTE_FLOW_ITEM_TYPE_ETH,
 482         RTE_FLOW_ITEM_TYPE_IPV6,
 483         RTE_FLOW_ITEM_TYPE_SCTP,
 484         RTE_FLOW_ITEM_TYPE_RAW,
 485         RTE_FLOW_ITEM_TYPE_RAW,
 486         RTE_FLOW_ITEM_TYPE_END,
 487 };
 488
 489 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 490         RTE_FLOW_ITEM_TYPE_ETH,
 491         RTE_FLOW_ITEM_TYPE_IPV6,
 492         RTE_FLOW_ITEM_TYPE_SCTP,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_RAW,
 495         RTE_FLOW_ITEM_TYPE_RAW,
 496         RTE_FLOW_ITEM_TYPE_END,
 497 };
 498
 499 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 500         RTE_FLOW_ITEM_TYPE_ETH,
 501         RTE_FLOW_ITEM_TYPE_VLAN,
 502         RTE_FLOW_ITEM_TYPE_END,
 503 };
 504
 505 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 506         RTE_FLOW_ITEM_TYPE_ETH,
 507         RTE_FLOW_ITEM_TYPE_VLAN,
 508         RTE_FLOW_ITEM_TYPE_IPV4,
 509         RTE_FLOW_ITEM_TYPE_END,
 510 };
 511
 512 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 513         RTE_FLOW_ITEM_TYPE_ETH,
 514         RTE_FLOW_ITEM_TYPE_VLAN,
 515         RTE_FLOW_ITEM_TYPE_IPV4,
 516         RTE_FLOW_ITEM_TYPE_UDP,
 517         RTE_FLOW_ITEM_TYPE_END,
 518 };
 519
 520 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 521         RTE_FLOW_ITEM_TYPE_ETH,
 522         RTE_FLOW_ITEM_TYPE_VLAN,
 523         RTE_FLOW_ITEM_TYPE_IPV4,
 524         RTE_FLOW_ITEM_TYPE_TCP,
 525         RTE_FLOW_ITEM_TYPE_END,
 526 };
 527
 528 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 529         RTE_FLOW_ITEM_TYPE_ETH,
 530         RTE_FLOW_ITEM_TYPE_VLAN,
 531         RTE_FLOW_ITEM_TYPE_IPV4,
 532         RTE_FLOW_ITEM_TYPE_SCTP,
 533         RTE_FLOW_ITEM_TYPE_END,
 534 };
 535
 536 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 537         RTE_FLOW_ITEM_TYPE_ETH,
 538         RTE_FLOW_ITEM_TYPE_VLAN,
 539         RTE_FLOW_ITEM_TYPE_IPV6,
 540         RTE_FLOW_ITEM_TYPE_END,
 541 };
 542
 543 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 544         RTE_FLOW_ITEM_TYPE_ETH,
 545         RTE_FLOW_ITEM_TYPE_VLAN,
 546         RTE_FLOW_ITEM_TYPE_IPV6,
 547         RTE_FLOW_ITEM_TYPE_UDP,
 548         RTE_FLOW_ITEM_TYPE_END,
 549 };
 550
 551 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 552         RTE_FLOW_ITEM_TYPE_ETH,
 553         RTE_FLOW_ITEM_TYPE_VLAN,
 554         RTE_FLOW_ITEM_TYPE_IPV6,
 555         RTE_FLOW_ITEM_TYPE_TCP,
 556         RTE_FLOW_ITEM_TYPE_END,
 557 };
 558
 559 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 560         RTE_FLOW_ITEM_TYPE_ETH,
 561         RTE_FLOW_ITEM_TYPE_VLAN,
 562         RTE_FLOW_ITEM_TYPE_IPV6,
 563         RTE_FLOW_ITEM_TYPE_SCTP,
 564         RTE_FLOW_ITEM_TYPE_END,
 565 };
 566
 567 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 568         RTE_FLOW_ITEM_TYPE_ETH,
 569         RTE_FLOW_ITEM_TYPE_VLAN,
 570         RTE_FLOW_ITEM_TYPE_RAW,
 571         RTE_FLOW_ITEM_TYPE_END,
 572 };
 573
 574 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 575         RTE_FLOW_ITEM_TYPE_ETH,
 576         RTE_FLOW_ITEM_TYPE_VLAN,
 577         RTE_FLOW_ITEM_TYPE_RAW,
 578         RTE_FLOW_ITEM_TYPE_RAW,
 579         RTE_FLOW_ITEM_TYPE_END,
 580 };
 581
 582 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 583         RTE_FLOW_ITEM_TYPE_ETH,
 584         RTE_FLOW_ITEM_TYPE_VLAN,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_RAW,
 587         RTE_FLOW_ITEM_TYPE_RAW,
 588         RTE_FLOW_ITEM_TYPE_END,
 589 };
 590
 591 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 592         RTE_FLOW_ITEM_TYPE_ETH,
 593         RTE_FLOW_ITEM_TYPE_VLAN,
 594         RTE_FLOW_ITEM_TYPE_IPV4,
 595         RTE_FLOW_ITEM_TYPE_RAW,
 596         RTE_FLOW_ITEM_TYPE_END,
 597 };
 598
 599 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 600         RTE_FLOW_ITEM_TYPE_ETH,
 601         RTE_FLOW_ITEM_TYPE_VLAN,
 602         RTE_FLOW_ITEM_TYPE_IPV4,
 603         RTE_FLOW_ITEM_TYPE_RAW,
 604         RTE_FLOW_ITEM_TYPE_RAW,
 605         RTE_FLOW_ITEM_TYPE_END,
 606 };
 607
 608 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 609         RTE_FLOW_ITEM_TYPE_ETH,
 610         RTE_FLOW_ITEM_TYPE_VLAN,
 611         RTE_FLOW_ITEM_TYPE_IPV4,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_RAW,
 614         RTE_FLOW_ITEM_TYPE_RAW,
 615         RTE_FLOW_ITEM_TYPE_END,
 616 };
 617
 618 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 619         RTE_FLOW_ITEM_TYPE_ETH,
 620         RTE_FLOW_ITEM_TYPE_VLAN,
 621         RTE_FLOW_ITEM_TYPE_IPV4,
 622         RTE_FLOW_ITEM_TYPE_UDP,
 623         RTE_FLOW_ITEM_TYPE_RAW,
 624         RTE_FLOW_ITEM_TYPE_END,
 625 };
 626
 627 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 628         RTE_FLOW_ITEM_TYPE_ETH,
 629         RTE_FLOW_ITEM_TYPE_VLAN,
 630         RTE_FLOW_ITEM_TYPE_IPV4,
 631         RTE_FLOW_ITEM_TYPE_UDP,
 632         RTE_FLOW_ITEM_TYPE_RAW,
 633         RTE_FLOW_ITEM_TYPE_RAW,
 634         RTE_FLOW_ITEM_TYPE_END,
 635 };
 636
 637 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 638         RTE_FLOW_ITEM_TYPE_ETH,
 639         RTE_FLOW_ITEM_TYPE_VLAN,
 640         RTE_FLOW_ITEM_TYPE_IPV4,
 641         RTE_FLOW_ITEM_TYPE_UDP,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_RAW,
 644         RTE_FLOW_ITEM_TYPE_RAW,
 645         RTE_FLOW_ITEM_TYPE_END,
 646 };
 647
 648 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 649         RTE_FLOW_ITEM_TYPE_ETH,
 650         RTE_FLOW_ITEM_TYPE_VLAN,
 651         RTE_FLOW_ITEM_TYPE_IPV4,
 652         RTE_FLOW_ITEM_TYPE_TCP,
 653         RTE_FLOW_ITEM_TYPE_RAW,
 654         RTE_FLOW_ITEM_TYPE_END,
 655 };
 656
 657 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 658         RTE_FLOW_ITEM_TYPE_ETH,
 659         RTE_FLOW_ITEM_TYPE_VLAN,
 660         RTE_FLOW_ITEM_TYPE_IPV4,
 661         RTE_FLOW_ITEM_TYPE_TCP,
 662         RTE_FLOW_ITEM_TYPE_RAW,
 663         RTE_FLOW_ITEM_TYPE_RAW,
 664         RTE_FLOW_ITEM_TYPE_END,
 665 };
 666
 667 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 668         RTE_FLOW_ITEM_TYPE_ETH,
 669         RTE_FLOW_ITEM_TYPE_VLAN,
 670         RTE_FLOW_ITEM_TYPE_IPV4,
 671         RTE_FLOW_ITEM_TYPE_TCP,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_RAW,
 674         RTE_FLOW_ITEM_TYPE_RAW,
 675         RTE_FLOW_ITEM_TYPE_END,
 676 };
 677
 678 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 679         RTE_FLOW_ITEM_TYPE_ETH,
 680         RTE_FLOW_ITEM_TYPE_VLAN,
 681         RTE_FLOW_ITEM_TYPE_IPV4,
 682         RTE_FLOW_ITEM_TYPE_SCTP,
 683         RTE_FLOW_ITEM_TYPE_RAW,
 684         RTE_FLOW_ITEM_TYPE_END,
 685 };
 686
 687 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 688         RTE_FLOW_ITEM_TYPE_ETH,
 689         RTE_FLOW_ITEM_TYPE_VLAN,
 690         RTE_FLOW_ITEM_TYPE_IPV4,
 691         RTE_FLOW_ITEM_TYPE_SCTP,
 692         RTE_FLOW_ITEM_TYPE_RAW,
 693         RTE_FLOW_ITEM_TYPE_RAW,
 694         RTE_FLOW_ITEM_TYPE_END,
 695 };
 696
 697 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 698         RTE_FLOW_ITEM_TYPE_ETH,
 699         RTE_FLOW_ITEM_TYPE_VLAN,
 700         RTE_FLOW_ITEM_TYPE_IPV4,
 701         RTE_FLOW_ITEM_TYPE_SCTP,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_RAW,
 704         RTE_FLOW_ITEM_TYPE_RAW,
 705         RTE_FLOW_ITEM_TYPE_END,
 706 };
 707
 708 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 709         RTE_FLOW_ITEM_TYPE_ETH,
 710         RTE_FLOW_ITEM_TYPE_VLAN,
 711         RTE_FLOW_ITEM_TYPE_IPV6,
 712         RTE_FLOW_ITEM_TYPE_RAW,
 713         RTE_FLOW_ITEM_TYPE_END,
 714 };
 715
 716 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 717         RTE_FLOW_ITEM_TYPE_ETH,
 718         RTE_FLOW_ITEM_TYPE_VLAN,
 719         RTE_FLOW_ITEM_TYPE_IPV6,
 720         RTE_FLOW_ITEM_TYPE_RAW,
 721         RTE_FLOW_ITEM_TYPE_RAW,
 722         RTE_FLOW_ITEM_TYPE_END,
 723 };
 724
 725 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 726         RTE_FLOW_ITEM_TYPE_ETH,
 727         RTE_FLOW_ITEM_TYPE_VLAN,
 728         RTE_FLOW_ITEM_TYPE_IPV6,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_RAW,
 731         RTE_FLOW_ITEM_TYPE_RAW,
 732         RTE_FLOW_ITEM_TYPE_END,
 733 };
 734
 735 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 736         RTE_FLOW_ITEM_TYPE_ETH,
 737         RTE_FLOW_ITEM_TYPE_VLAN,
 738         RTE_FLOW_ITEM_TYPE_IPV6,
 739         RTE_FLOW_ITEM_TYPE_UDP,
 740         RTE_FLOW_ITEM_TYPE_RAW,
 741         RTE_FLOW_ITEM_TYPE_END,
 742 };
 743
 744 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 745         RTE_FLOW_ITEM_TYPE_ETH,
 746         RTE_FLOW_ITEM_TYPE_VLAN,
 747         RTE_FLOW_ITEM_TYPE_IPV6,
 748         RTE_FLOW_ITEM_TYPE_UDP,
 749         RTE_FLOW_ITEM_TYPE_RAW,
 750         RTE_FLOW_ITEM_TYPE_RAW,
 751         RTE_FLOW_ITEM_TYPE_END,
 752 };
 753
 754 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 755         RTE_FLOW_ITEM_TYPE_ETH,
 756         RTE_FLOW_ITEM_TYPE_VLAN,
 757         RTE_FLOW_ITEM_TYPE_IPV6,
 758         RTE_FLOW_ITEM_TYPE_UDP,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_RAW,
 761         RTE_FLOW_ITEM_TYPE_RAW,
 762         RTE_FLOW_ITEM_TYPE_END,
 763 };
 764
 765 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 766         RTE_FLOW_ITEM_TYPE_ETH,
 767         RTE_FLOW_ITEM_TYPE_VLAN,
 768         RTE_FLOW_ITEM_TYPE_IPV6,
 769         RTE_FLOW_ITEM_TYPE_TCP,
 770         RTE_FLOW_ITEM_TYPE_RAW,
 771         RTE_FLOW_ITEM_TYPE_END,
 772 };
 773
 774 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 775         RTE_FLOW_ITEM_TYPE_ETH,
 776         RTE_FLOW_ITEM_TYPE_VLAN,
 777         RTE_FLOW_ITEM_TYPE_IPV6,
 778         RTE_FLOW_ITEM_TYPE_TCP,
 779         RTE_FLOW_ITEM_TYPE_RAW,
 780         RTE_FLOW_ITEM_TYPE_RAW,
 781         RTE_FLOW_ITEM_TYPE_END,
 782 };
 783
 784 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 785         RTE_FLOW_ITEM_TYPE_ETH,
 786         RTE_FLOW_ITEM_TYPE_VLAN,
 787         RTE_FLOW_ITEM_TYPE_IPV6,
 788         RTE_FLOW_ITEM_TYPE_TCP,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_RAW,
 791         RTE_FLOW_ITEM_TYPE_RAW,
 792         RTE_FLOW_ITEM_TYPE_END,
 793 };
 794
 795 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 796         RTE_FLOW_ITEM_TYPE_ETH,
 797         RTE_FLOW_ITEM_TYPE_VLAN,
 798         RTE_FLOW_ITEM_TYPE_IPV6,
 799         RTE_FLOW_ITEM_TYPE_SCTP,
 800         RTE_FLOW_ITEM_TYPE_RAW,
 801         RTE_FLOW_ITEM_TYPE_END,
 802 };
 803
 804 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 805         RTE_FLOW_ITEM_TYPE_ETH,
 806         RTE_FLOW_ITEM_TYPE_VLAN,
 807         RTE_FLOW_ITEM_TYPE_IPV6,
 808         RTE_FLOW_ITEM_TYPE_SCTP,
 809         RTE_FLOW_ITEM_TYPE_RAW,
 810         RTE_FLOW_ITEM_TYPE_RAW,
 811         RTE_FLOW_ITEM_TYPE_END,
 812 };
 813
 814 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 815         RTE_FLOW_ITEM_TYPE_ETH,
 816         RTE_FLOW_ITEM_TYPE_VLAN,
 817         RTE_FLOW_ITEM_TYPE_IPV6,
 818         RTE_FLOW_ITEM_TYPE_SCTP,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_RAW,
 821         RTE_FLOW_ITEM_TYPE_RAW,
 822         RTE_FLOW_ITEM_TYPE_END,
 823 };
 824
 825 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 826         RTE_FLOW_ITEM_TYPE_ETH,
 827         RTE_FLOW_ITEM_TYPE_IPV4,
 828         RTE_FLOW_ITEM_TYPE_VF,
 829         RTE_FLOW_ITEM_TYPE_END,
 830 };
 831
 832 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 833         RTE_FLOW_ITEM_TYPE_ETH,
 834         RTE_FLOW_ITEM_TYPE_IPV4,
 835         RTE_FLOW_ITEM_TYPE_UDP,
 836         RTE_FLOW_ITEM_TYPE_VF,
 837         RTE_FLOW_ITEM_TYPE_END,
 838 };
 839
 840 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 841         RTE_FLOW_ITEM_TYPE_ETH,
 842         RTE_FLOW_ITEM_TYPE_IPV4,
 843         RTE_FLOW_ITEM_TYPE_TCP,
 844         RTE_FLOW_ITEM_TYPE_VF,
 845         RTE_FLOW_ITEM_TYPE_END,
 846 };
 847
 848 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 849         RTE_FLOW_ITEM_TYPE_ETH,
 850         RTE_FLOW_ITEM_TYPE_IPV4,
 851         RTE_FLOW_ITEM_TYPE_SCTP,
 852         RTE_FLOW_ITEM_TYPE_VF,
 853         RTE_FLOW_ITEM_TYPE_END,
 854 };
 855
 856 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 857         RTE_FLOW_ITEM_TYPE_ETH,
 858         RTE_FLOW_ITEM_TYPE_IPV6,
 859         RTE_FLOW_ITEM_TYPE_VF,
 860         RTE_FLOW_ITEM_TYPE_END,
 861 };
 862
 863 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 864         RTE_FLOW_ITEM_TYPE_ETH,
 865         RTE_FLOW_ITEM_TYPE_IPV6,
 866         RTE_FLOW_ITEM_TYPE_UDP,
 867         RTE_FLOW_ITEM_TYPE_VF,
 868         RTE_FLOW_ITEM_TYPE_END,
 869 };
 870
 871 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 872         RTE_FLOW_ITEM_TYPE_ETH,
 873         RTE_FLOW_ITEM_TYPE_IPV6,
 874         RTE_FLOW_ITEM_TYPE_TCP,
 875         RTE_FLOW_ITEM_TYPE_VF,
 876         RTE_FLOW_ITEM_TYPE_END,
 877 };
 878
 879 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 880         RTE_FLOW_ITEM_TYPE_ETH,
 881         RTE_FLOW_ITEM_TYPE_IPV6,
 882         RTE_FLOW_ITEM_TYPE_SCTP,
 883         RTE_FLOW_ITEM_TYPE_VF,
 884         RTE_FLOW_ITEM_TYPE_END,
 885 };
 886
 887 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 888         RTE_FLOW_ITEM_TYPE_ETH,
 889         RTE_FLOW_ITEM_TYPE_RAW,
 890         RTE_FLOW_ITEM_TYPE_VF,
 891         RTE_FLOW_ITEM_TYPE_END,
 892 };
 893
 894 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 895         RTE_FLOW_ITEM_TYPE_ETH,
 896         RTE_FLOW_ITEM_TYPE_RAW,
 897         RTE_FLOW_ITEM_TYPE_RAW,
 898         RTE_FLOW_ITEM_TYPE_VF,
 899         RTE_FLOW_ITEM_TYPE_END,
 900 };
 901
 902 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 903         RTE_FLOW_ITEM_TYPE_ETH,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_RAW,
 906         RTE_FLOW_ITEM_TYPE_RAW,
 907         RTE_FLOW_ITEM_TYPE_VF,
 908         RTE_FLOW_ITEM_TYPE_END,
 909 };
 910
 911 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 912         RTE_FLOW_ITEM_TYPE_ETH,
 913         RTE_FLOW_ITEM_TYPE_IPV4,
 914         RTE_FLOW_ITEM_TYPE_RAW,
 915         RTE_FLOW_ITEM_TYPE_VF,
 916         RTE_FLOW_ITEM_TYPE_END,
 917 };
 918
 919 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 920         RTE_FLOW_ITEM_TYPE_ETH,
 921         RTE_FLOW_ITEM_TYPE_IPV4,
 922         RTE_FLOW_ITEM_TYPE_RAW,
 923         RTE_FLOW_ITEM_TYPE_RAW,
 924         RTE_FLOW_ITEM_TYPE_VF,
 925         RTE_FLOW_ITEM_TYPE_END,
 926 };
 927
 928 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 929         RTE_FLOW_ITEM_TYPE_ETH,
 930         RTE_FLOW_ITEM_TYPE_IPV4,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_RAW,
 933         RTE_FLOW_ITEM_TYPE_RAW,
 934         RTE_FLOW_ITEM_TYPE_VF,
 935         RTE_FLOW_ITEM_TYPE_END,
 936 };
 937
 938 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 939         RTE_FLOW_ITEM_TYPE_ETH,
 940         RTE_FLOW_ITEM_TYPE_IPV4,
 941         RTE_FLOW_ITEM_TYPE_UDP,
 942         RTE_FLOW_ITEM_TYPE_RAW,
 943         RTE_FLOW_ITEM_TYPE_VF,
 944         RTE_FLOW_ITEM_TYPE_END,
 945 };
 946
 947 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 948         RTE_FLOW_ITEM_TYPE_ETH,
 949         RTE_FLOW_ITEM_TYPE_IPV4,
 950         RTE_FLOW_ITEM_TYPE_UDP,
 951         RTE_FLOW_ITEM_TYPE_RAW,
 952         RTE_FLOW_ITEM_TYPE_RAW,
 953         RTE_FLOW_ITEM_TYPE_VF,
 954         RTE_FLOW_ITEM_TYPE_END,
 955 };
 956
 957 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 958         RTE_FLOW_ITEM_TYPE_ETH,
 959         RTE_FLOW_ITEM_TYPE_IPV4,
 960         RTE_FLOW_ITEM_TYPE_UDP,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_RAW,
 963         RTE_FLOW_ITEM_TYPE_RAW,
 964         RTE_FLOW_ITEM_TYPE_VF,
 965         RTE_FLOW_ITEM_TYPE_END,
 966 };
 967
 968 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 969         RTE_FLOW_ITEM_TYPE_ETH,
 970         RTE_FLOW_ITEM_TYPE_IPV4,
 971         RTE_FLOW_ITEM_TYPE_TCP,
 972         RTE_FLOW_ITEM_TYPE_RAW,
 973         RTE_FLOW_ITEM_TYPE_VF,
 974         RTE_FLOW_ITEM_TYPE_END,
 975 };
 976
 977 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 978         RTE_FLOW_ITEM_TYPE_ETH,
 979         RTE_FLOW_ITEM_TYPE_IPV4,
 980         RTE_FLOW_ITEM_TYPE_TCP,
 981         RTE_FLOW_ITEM_TYPE_RAW,
 982         RTE_FLOW_ITEM_TYPE_RAW,
 983         RTE_FLOW_ITEM_TYPE_VF,
 984         RTE_FLOW_ITEM_TYPE_END,
 985 };
 986
 987 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 988         RTE_FLOW_ITEM_TYPE_ETH,
 989         RTE_FLOW_ITEM_TYPE_IPV4,
 990         RTE_FLOW_ITEM_TYPE_TCP,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_RAW,
 993         RTE_FLOW_ITEM_TYPE_RAW,
 994         RTE_FLOW_ITEM_TYPE_VF,
 995         RTE_FLOW_ITEM_TYPE_END,
 996 };
 997
 998 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 999         RTE_FLOW_ITEM_TYPE_ETH,
1000         RTE_FLOW_ITEM_TYPE_IPV4,
1001         RTE_FLOW_ITEM_TYPE_SCTP,
1002         RTE_FLOW_ITEM_TYPE_RAW,
1003         RTE_FLOW_ITEM_TYPE_VF,
1004         RTE_FLOW_ITEM_TYPE_END,
1005 };
1006
1007 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1008         RTE_FLOW_ITEM_TYPE_ETH,
1009         RTE_FLOW_ITEM_TYPE_IPV4,
1010         RTE_FLOW_ITEM_TYPE_SCTP,
1011         RTE_FLOW_ITEM_TYPE_RAW,
1012         RTE_FLOW_ITEM_TYPE_RAW,
1013         RTE_FLOW_ITEM_TYPE_VF,
1014         RTE_FLOW_ITEM_TYPE_END,
1015 };
1016
1017 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1018         RTE_FLOW_ITEM_TYPE_ETH,
1019         RTE_FLOW_ITEM_TYPE_IPV4,
1020         RTE_FLOW_ITEM_TYPE_SCTP,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_RAW,
1023         RTE_FLOW_ITEM_TYPE_RAW,
1024         RTE_FLOW_ITEM_TYPE_VF,
1025         RTE_FLOW_ITEM_TYPE_END,
1026 };
1027
1028 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1029         RTE_FLOW_ITEM_TYPE_ETH,
1030         RTE_FLOW_ITEM_TYPE_IPV6,
1031         RTE_FLOW_ITEM_TYPE_RAW,
1032         RTE_FLOW_ITEM_TYPE_VF,
1033         RTE_FLOW_ITEM_TYPE_END,
1034 };
1035
1036 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1037         RTE_FLOW_ITEM_TYPE_ETH,
1038         RTE_FLOW_ITEM_TYPE_IPV6,
1039         RTE_FLOW_ITEM_TYPE_RAW,
1040         RTE_FLOW_ITEM_TYPE_RAW,
1041         RTE_FLOW_ITEM_TYPE_VF,
1042         RTE_FLOW_ITEM_TYPE_END,
1043 };
1044
1045 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1046         RTE_FLOW_ITEM_TYPE_ETH,
1047         RTE_FLOW_ITEM_TYPE_IPV6,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_RAW,
1050         RTE_FLOW_ITEM_TYPE_RAW,
1051         RTE_FLOW_ITEM_TYPE_VF,
1052         RTE_FLOW_ITEM_TYPE_END,
1053 };
1054
1055 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1056         RTE_FLOW_ITEM_TYPE_ETH,
1057         RTE_FLOW_ITEM_TYPE_IPV6,
1058         RTE_FLOW_ITEM_TYPE_UDP,
1059         RTE_FLOW_ITEM_TYPE_RAW,
1060         RTE_FLOW_ITEM_TYPE_VF,
1061         RTE_FLOW_ITEM_TYPE_END,
1062 };
1063
1064 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1065         RTE_FLOW_ITEM_TYPE_ETH,
1066         RTE_FLOW_ITEM_TYPE_IPV6,
1067         RTE_FLOW_ITEM_TYPE_UDP,
1068         RTE_FLOW_ITEM_TYPE_RAW,
1069         RTE_FLOW_ITEM_TYPE_RAW,
1070         RTE_FLOW_ITEM_TYPE_VF,
1071         RTE_FLOW_ITEM_TYPE_END,
1072 };
1073
1074 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1075         RTE_FLOW_ITEM_TYPE_ETH,
1076         RTE_FLOW_ITEM_TYPE_IPV6,
1077         RTE_FLOW_ITEM_TYPE_UDP,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_RAW,
1080         RTE_FLOW_ITEM_TYPE_RAW,
1081         RTE_FLOW_ITEM_TYPE_VF,
1082         RTE_FLOW_ITEM_TYPE_END,
1083 };
1084
1085 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1086         RTE_FLOW_ITEM_TYPE_ETH,
1087         RTE_FLOW_ITEM_TYPE_IPV6,
1088         RTE_FLOW_ITEM_TYPE_TCP,
1089         RTE_FLOW_ITEM_TYPE_RAW,
1090         RTE_FLOW_ITEM_TYPE_VF,
1091         RTE_FLOW_ITEM_TYPE_END,
1092 };
1093
1094 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1095         RTE_FLOW_ITEM_TYPE_ETH,
1096         RTE_FLOW_ITEM_TYPE_IPV6,
1097         RTE_FLOW_ITEM_TYPE_TCP,
1098         RTE_FLOW_ITEM_TYPE_RAW,
1099         RTE_FLOW_ITEM_TYPE_RAW,
1100         RTE_FLOW_ITEM_TYPE_VF,
1101         RTE_FLOW_ITEM_TYPE_END,
1102 };
1103
1104 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1105         RTE_FLOW_ITEM_TYPE_ETH,
1106         RTE_FLOW_ITEM_TYPE_IPV6,
1107         RTE_FLOW_ITEM_TYPE_TCP,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_RAW,
1110         RTE_FLOW_ITEM_TYPE_RAW,
1111         RTE_FLOW_ITEM_TYPE_VF,
1112         RTE_FLOW_ITEM_TYPE_END,
1113 };
1114
1115 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1116         RTE_FLOW_ITEM_TYPE_ETH,
1117         RTE_FLOW_ITEM_TYPE_IPV6,
1118         RTE_FLOW_ITEM_TYPE_SCTP,
1119         RTE_FLOW_ITEM_TYPE_RAW,
1120         RTE_FLOW_ITEM_TYPE_VF,
1121         RTE_FLOW_ITEM_TYPE_END,
1122 };
1123
1124 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1125         RTE_FLOW_ITEM_TYPE_ETH,
1126         RTE_FLOW_ITEM_TYPE_IPV6,
1127         RTE_FLOW_ITEM_TYPE_SCTP,
1128         RTE_FLOW_ITEM_TYPE_RAW,
1129         RTE_FLOW_ITEM_TYPE_RAW,
1130         RTE_FLOW_ITEM_TYPE_VF,
1131         RTE_FLOW_ITEM_TYPE_END,
1132 };
1133
1134 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1135         RTE_FLOW_ITEM_TYPE_ETH,
1136         RTE_FLOW_ITEM_TYPE_IPV6,
1137         RTE_FLOW_ITEM_TYPE_SCTP,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_RAW,
1140         RTE_FLOW_ITEM_TYPE_RAW,
1141         RTE_FLOW_ITEM_TYPE_VF,
1142         RTE_FLOW_ITEM_TYPE_END,
1143 };
1144
1145 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1146         RTE_FLOW_ITEM_TYPE_ETH,
1147         RTE_FLOW_ITEM_TYPE_VLAN,
1148         RTE_FLOW_ITEM_TYPE_VF,
1149         RTE_FLOW_ITEM_TYPE_END,
1150 };
1151
1152 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1153         RTE_FLOW_ITEM_TYPE_ETH,
1154         RTE_FLOW_ITEM_TYPE_VLAN,
1155         RTE_FLOW_ITEM_TYPE_IPV4,
1156         RTE_FLOW_ITEM_TYPE_VF,
1157         RTE_FLOW_ITEM_TYPE_END,
1158 };
1159
1160 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1161         RTE_FLOW_ITEM_TYPE_ETH,
1162         RTE_FLOW_ITEM_TYPE_VLAN,
1163         RTE_FLOW_ITEM_TYPE_IPV4,
1164         RTE_FLOW_ITEM_TYPE_UDP,
1165         RTE_FLOW_ITEM_TYPE_VF,
1166         RTE_FLOW_ITEM_TYPE_END,
1167 };
1168
1169 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1170         RTE_FLOW_ITEM_TYPE_ETH,
1171         RTE_FLOW_ITEM_TYPE_VLAN,
1172         RTE_FLOW_ITEM_TYPE_IPV4,
1173         RTE_FLOW_ITEM_TYPE_TCP,
1174         RTE_FLOW_ITEM_TYPE_VF,
1175         RTE_FLOW_ITEM_TYPE_END,
1176 };
1177
1178 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1179         RTE_FLOW_ITEM_TYPE_ETH,
1180         RTE_FLOW_ITEM_TYPE_VLAN,
1181         RTE_FLOW_ITEM_TYPE_IPV4,
1182         RTE_FLOW_ITEM_TYPE_SCTP,
1183         RTE_FLOW_ITEM_TYPE_VF,
1184         RTE_FLOW_ITEM_TYPE_END,
1185 };
1186
1187 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1188         RTE_FLOW_ITEM_TYPE_ETH,
1189         RTE_FLOW_ITEM_TYPE_VLAN,
1190         RTE_FLOW_ITEM_TYPE_IPV6,
1191         RTE_FLOW_ITEM_TYPE_VF,
1192         RTE_FLOW_ITEM_TYPE_END,
1193 };
1194
1195 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1196         RTE_FLOW_ITEM_TYPE_ETH,
1197         RTE_FLOW_ITEM_TYPE_VLAN,
1198         RTE_FLOW_ITEM_TYPE_IPV6,
1199         RTE_FLOW_ITEM_TYPE_UDP,
1200         RTE_FLOW_ITEM_TYPE_VF,
1201         RTE_FLOW_ITEM_TYPE_END,
1202 };
1203
1204 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1205         RTE_FLOW_ITEM_TYPE_ETH,
1206         RTE_FLOW_ITEM_TYPE_VLAN,
1207         RTE_FLOW_ITEM_TYPE_IPV6,
1208         RTE_FLOW_ITEM_TYPE_TCP,
1209         RTE_FLOW_ITEM_TYPE_VF,
1210         RTE_FLOW_ITEM_TYPE_END,
1211 };
1212
1213 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1214         RTE_FLOW_ITEM_TYPE_ETH,
1215         RTE_FLOW_ITEM_TYPE_VLAN,
1216         RTE_FLOW_ITEM_TYPE_IPV6,
1217         RTE_FLOW_ITEM_TYPE_SCTP,
1218         RTE_FLOW_ITEM_TYPE_VF,
1219         RTE_FLOW_ITEM_TYPE_END,
1220 };
1221
1222 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1223         RTE_FLOW_ITEM_TYPE_ETH,
1224         RTE_FLOW_ITEM_TYPE_VLAN,
1225         RTE_FLOW_ITEM_TYPE_RAW,
1226         RTE_FLOW_ITEM_TYPE_VF,
1227         RTE_FLOW_ITEM_TYPE_END,
1228 };
1229
1230 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1231         RTE_FLOW_ITEM_TYPE_ETH,
1232         RTE_FLOW_ITEM_TYPE_VLAN,
1233         RTE_FLOW_ITEM_TYPE_RAW,
1234         RTE_FLOW_ITEM_TYPE_RAW,
1235         RTE_FLOW_ITEM_TYPE_VF,
1236         RTE_FLOW_ITEM_TYPE_END,
1237 };
1238
1239 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1240         RTE_FLOW_ITEM_TYPE_ETH,
1241         RTE_FLOW_ITEM_TYPE_VLAN,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_RAW,
1244         RTE_FLOW_ITEM_TYPE_RAW,
1245         RTE_FLOW_ITEM_TYPE_VF,
1246         RTE_FLOW_ITEM_TYPE_END,
1247 };
1248
1249 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1250         RTE_FLOW_ITEM_TYPE_ETH,
1251         RTE_FLOW_ITEM_TYPE_VLAN,
1252         RTE_FLOW_ITEM_TYPE_IPV4,
1253         RTE_FLOW_ITEM_TYPE_RAW,
1254         RTE_FLOW_ITEM_TYPE_VF,
1255         RTE_FLOW_ITEM_TYPE_END,
1256 };
1257
1258 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1259         RTE_FLOW_ITEM_TYPE_ETH,
1260         RTE_FLOW_ITEM_TYPE_VLAN,
1261         RTE_FLOW_ITEM_TYPE_IPV4,
1262         RTE_FLOW_ITEM_TYPE_RAW,
1263         RTE_FLOW_ITEM_TYPE_RAW,
1264         RTE_FLOW_ITEM_TYPE_VF,
1265         RTE_FLOW_ITEM_TYPE_END,
1266 };
1267
1268 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1269         RTE_FLOW_ITEM_TYPE_ETH,
1270         RTE_FLOW_ITEM_TYPE_VLAN,
1271         RTE_FLOW_ITEM_TYPE_IPV4,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_RAW,
1274         RTE_FLOW_ITEM_TYPE_RAW,
1275         RTE_FLOW_ITEM_TYPE_VF,
1276         RTE_FLOW_ITEM_TYPE_END,
1277 };
1278
1279 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1280         RTE_FLOW_ITEM_TYPE_ETH,
1281         RTE_FLOW_ITEM_TYPE_VLAN,
1282         RTE_FLOW_ITEM_TYPE_IPV4,
1283         RTE_FLOW_ITEM_TYPE_UDP,
1284         RTE_FLOW_ITEM_TYPE_RAW,
1285         RTE_FLOW_ITEM_TYPE_VF,
1286         RTE_FLOW_ITEM_TYPE_END,
1287 };
1288
1289 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1290         RTE_FLOW_ITEM_TYPE_ETH,
1291         RTE_FLOW_ITEM_TYPE_VLAN,
1292         RTE_FLOW_ITEM_TYPE_IPV4,
1293         RTE_FLOW_ITEM_TYPE_UDP,
1294         RTE_FLOW_ITEM_TYPE_RAW,
1295         RTE_FLOW_ITEM_TYPE_RAW,
1296         RTE_FLOW_ITEM_TYPE_VF,
1297         RTE_FLOW_ITEM_TYPE_END,
1298 };
1299
1300 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1301         RTE_FLOW_ITEM_TYPE_ETH,
1302         RTE_FLOW_ITEM_TYPE_VLAN,
1303         RTE_FLOW_ITEM_TYPE_IPV4,
1304         RTE_FLOW_ITEM_TYPE_UDP,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_RAW,
1307         RTE_FLOW_ITEM_TYPE_RAW,
1308         RTE_FLOW_ITEM_TYPE_VF,
1309         RTE_FLOW_ITEM_TYPE_END,
1310 };
1311
1312 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1313         RTE_FLOW_ITEM_TYPE_ETH,
1314         RTE_FLOW_ITEM_TYPE_VLAN,
1315         RTE_FLOW_ITEM_TYPE_IPV4,
1316         RTE_FLOW_ITEM_TYPE_TCP,
1317         RTE_FLOW_ITEM_TYPE_RAW,
1318         RTE_FLOW_ITEM_TYPE_VF,
1319         RTE_FLOW_ITEM_TYPE_END,
1320 };
1321
1322 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1323         RTE_FLOW_ITEM_TYPE_ETH,
1324         RTE_FLOW_ITEM_TYPE_VLAN,
1325         RTE_FLOW_ITEM_TYPE_IPV4,
1326         RTE_FLOW_ITEM_TYPE_TCP,
1327         RTE_FLOW_ITEM_TYPE_RAW,
1328         RTE_FLOW_ITEM_TYPE_RAW,
1329         RTE_FLOW_ITEM_TYPE_VF,
1330         RTE_FLOW_ITEM_TYPE_END,
1331 };
1332
1333 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1334         RTE_FLOW_ITEM_TYPE_ETH,
1335         RTE_FLOW_ITEM_TYPE_VLAN,
1336         RTE_FLOW_ITEM_TYPE_IPV4,
1337         RTE_FLOW_ITEM_TYPE_TCP,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_RAW,
1340         RTE_FLOW_ITEM_TYPE_RAW,
1341         RTE_FLOW_ITEM_TYPE_VF,
1342         RTE_FLOW_ITEM_TYPE_END,
1343 };
1344
1345 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1346         RTE_FLOW_ITEM_TYPE_ETH,
1347         RTE_FLOW_ITEM_TYPE_VLAN,
1348         RTE_FLOW_ITEM_TYPE_IPV4,
1349         RTE_FLOW_ITEM_TYPE_SCTP,
1350         RTE_FLOW_ITEM_TYPE_RAW,
1351         RTE_FLOW_ITEM_TYPE_VF,
1352         RTE_FLOW_ITEM_TYPE_END,
1353 };
1354
1355 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1356         RTE_FLOW_ITEM_TYPE_ETH,
1357         RTE_FLOW_ITEM_TYPE_VLAN,
1358         RTE_FLOW_ITEM_TYPE_IPV4,
1359         RTE_FLOW_ITEM_TYPE_SCTP,
1360         RTE_FLOW_ITEM_TYPE_RAW,
1361         RTE_FLOW_ITEM_TYPE_RAW,
1362         RTE_FLOW_ITEM_TYPE_VF,
1363         RTE_FLOW_ITEM_TYPE_END,
1364 };
1365
1366 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1367         RTE_FLOW_ITEM_TYPE_ETH,
1368         RTE_FLOW_ITEM_TYPE_VLAN,
1369         RTE_FLOW_ITEM_TYPE_IPV4,
1370         RTE_FLOW_ITEM_TYPE_SCTP,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_RAW,
1373         RTE_FLOW_ITEM_TYPE_RAW,
1374         RTE_FLOW_ITEM_TYPE_VF,
1375         RTE_FLOW_ITEM_TYPE_END,
1376 };
1377
1378 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1379         RTE_FLOW_ITEM_TYPE_ETH,
1380         RTE_FLOW_ITEM_TYPE_VLAN,
1381         RTE_FLOW_ITEM_TYPE_IPV6,
1382         RTE_FLOW_ITEM_TYPE_RAW,
1383         RTE_FLOW_ITEM_TYPE_VF,
1384         RTE_FLOW_ITEM_TYPE_END,
1385 };
1386
1387 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1388         RTE_FLOW_ITEM_TYPE_ETH,
1389         RTE_FLOW_ITEM_TYPE_VLAN,
1390         RTE_FLOW_ITEM_TYPE_IPV6,
1391         RTE_FLOW_ITEM_TYPE_RAW,
1392         RTE_FLOW_ITEM_TYPE_RAW,
1393         RTE_FLOW_ITEM_TYPE_VF,
1394         RTE_FLOW_ITEM_TYPE_END,
1395 };
1396
1397 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1398         RTE_FLOW_ITEM_TYPE_ETH,
1399         RTE_FLOW_ITEM_TYPE_VLAN,
1400         RTE_FLOW_ITEM_TYPE_IPV6,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_RAW,
1403         RTE_FLOW_ITEM_TYPE_RAW,
1404         RTE_FLOW_ITEM_TYPE_VF,
1405         RTE_FLOW_ITEM_TYPE_END,
1406 };
1407
1408 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1409         RTE_FLOW_ITEM_TYPE_ETH,
1410         RTE_FLOW_ITEM_TYPE_VLAN,
1411         RTE_FLOW_ITEM_TYPE_IPV6,
1412         RTE_FLOW_ITEM_TYPE_UDP,
1413         RTE_FLOW_ITEM_TYPE_RAW,
1414         RTE_FLOW_ITEM_TYPE_VF,
1415         RTE_FLOW_ITEM_TYPE_END,
1416 };
1417
1418 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1419         RTE_FLOW_ITEM_TYPE_ETH,
1420         RTE_FLOW_ITEM_TYPE_VLAN,
1421         RTE_FLOW_ITEM_TYPE_IPV6,
1422         RTE_FLOW_ITEM_TYPE_UDP,
1423         RTE_FLOW_ITEM_TYPE_RAW,
1424         RTE_FLOW_ITEM_TYPE_RAW,
1425         RTE_FLOW_ITEM_TYPE_VF,
1426         RTE_FLOW_ITEM_TYPE_END,
1427 };
1428
1429 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1430         RTE_FLOW_ITEM_TYPE_ETH,
1431         RTE_FLOW_ITEM_TYPE_VLAN,
1432         RTE_FLOW_ITEM_TYPE_IPV6,
1433         RTE_FLOW_ITEM_TYPE_UDP,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_RAW,
1436         RTE_FLOW_ITEM_TYPE_RAW,
1437         RTE_FLOW_ITEM_TYPE_VF,
1438         RTE_FLOW_ITEM_TYPE_END,
1439 };
1440
1441 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1442         RTE_FLOW_ITEM_TYPE_ETH,
1443         RTE_FLOW_ITEM_TYPE_VLAN,
1444         RTE_FLOW_ITEM_TYPE_IPV6,
1445         RTE_FLOW_ITEM_TYPE_TCP,
1446         RTE_FLOW_ITEM_TYPE_RAW,
1447         RTE_FLOW_ITEM_TYPE_VF,
1448         RTE_FLOW_ITEM_TYPE_END,
1449 };
1450
1451 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1452         RTE_FLOW_ITEM_TYPE_ETH,
1453         RTE_FLOW_ITEM_TYPE_VLAN,
1454         RTE_FLOW_ITEM_TYPE_IPV6,
1455         RTE_FLOW_ITEM_TYPE_TCP,
1456         RTE_FLOW_ITEM_TYPE_RAW,
1457         RTE_FLOW_ITEM_TYPE_RAW,
1458         RTE_FLOW_ITEM_TYPE_VF,
1459         RTE_FLOW_ITEM_TYPE_END,
1460 };
1461
1462 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1463         RTE_FLOW_ITEM_TYPE_ETH,
1464         RTE_FLOW_ITEM_TYPE_VLAN,
1465         RTE_FLOW_ITEM_TYPE_IPV6,
1466         RTE_FLOW_ITEM_TYPE_TCP,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_RAW,
1469         RTE_FLOW_ITEM_TYPE_RAW,
1470         RTE_FLOW_ITEM_TYPE_VF,
1471         RTE_FLOW_ITEM_TYPE_END,
1472 };
1473
1474 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1475         RTE_FLOW_ITEM_TYPE_ETH,
1476         RTE_FLOW_ITEM_TYPE_VLAN,
1477         RTE_FLOW_ITEM_TYPE_IPV6,
1478         RTE_FLOW_ITEM_TYPE_SCTP,
1479         RTE_FLOW_ITEM_TYPE_RAW,
1480         RTE_FLOW_ITEM_TYPE_VF,
1481         RTE_FLOW_ITEM_TYPE_END,
1482 };
1483
1484 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1485         RTE_FLOW_ITEM_TYPE_ETH,
1486         RTE_FLOW_ITEM_TYPE_VLAN,
1487         RTE_FLOW_ITEM_TYPE_IPV6,
1488         RTE_FLOW_ITEM_TYPE_SCTP,
1489         RTE_FLOW_ITEM_TYPE_RAW,
1490         RTE_FLOW_ITEM_TYPE_RAW,
1491         RTE_FLOW_ITEM_TYPE_VF,
1492         RTE_FLOW_ITEM_TYPE_END,
1493 };
1494
1495 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1496         RTE_FLOW_ITEM_TYPE_ETH,
1497         RTE_FLOW_ITEM_TYPE_VLAN,
1498         RTE_FLOW_ITEM_TYPE_IPV6,
1499         RTE_FLOW_ITEM_TYPE_SCTP,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_RAW,
1502         RTE_FLOW_ITEM_TYPE_RAW,
1503         RTE_FLOW_ITEM_TYPE_VF,
1504         RTE_FLOW_ITEM_TYPE_END,
1505 };
1506
1507 /* Pattern matched tunnel filter */
1508 static enum rte_flow_item_type pattern_vxlan_1[] = {
1509         RTE_FLOW_ITEM_TYPE_ETH,
1510         RTE_FLOW_ITEM_TYPE_IPV4,
1511         RTE_FLOW_ITEM_TYPE_UDP,
1512         RTE_FLOW_ITEM_TYPE_VXLAN,
1513         RTE_FLOW_ITEM_TYPE_ETH,
1514         RTE_FLOW_ITEM_TYPE_END,
1515 };
1516
1517 static enum rte_flow_item_type pattern_vxlan_2[] = {
1518         RTE_FLOW_ITEM_TYPE_ETH,
1519         RTE_FLOW_ITEM_TYPE_IPV6,
1520         RTE_FLOW_ITEM_TYPE_UDP,
1521         RTE_FLOW_ITEM_TYPE_VXLAN,
1522         RTE_FLOW_ITEM_TYPE_ETH,
1523         RTE_FLOW_ITEM_TYPE_END,
1524 };
1525
1526 static enum rte_flow_item_type pattern_vxlan_3[] = {
1527         RTE_FLOW_ITEM_TYPE_ETH,
1528         RTE_FLOW_ITEM_TYPE_IPV4,
1529         RTE_FLOW_ITEM_TYPE_UDP,
1530         RTE_FLOW_ITEM_TYPE_VXLAN,
1531         RTE_FLOW_ITEM_TYPE_ETH,
1532         RTE_FLOW_ITEM_TYPE_VLAN,
1533         RTE_FLOW_ITEM_TYPE_END,
1534 };
1535
1536 static enum rte_flow_item_type pattern_vxlan_4[] = {
1537         RTE_FLOW_ITEM_TYPE_ETH,
1538         RTE_FLOW_ITEM_TYPE_IPV6,
1539         RTE_FLOW_ITEM_TYPE_UDP,
1540         RTE_FLOW_ITEM_TYPE_VXLAN,
1541         RTE_FLOW_ITEM_TYPE_ETH,
1542         RTE_FLOW_ITEM_TYPE_VLAN,
1543         RTE_FLOW_ITEM_TYPE_END,
1544 };
1545
1546 static enum rte_flow_item_type pattern_nvgre_1[] = {
1547         RTE_FLOW_ITEM_TYPE_ETH,
1548         RTE_FLOW_ITEM_TYPE_IPV4,
1549         RTE_FLOW_ITEM_TYPE_NVGRE,
1550         RTE_FLOW_ITEM_TYPE_ETH,
1551         RTE_FLOW_ITEM_TYPE_END,
1552 };
1553
1554 static enum rte_flow_item_type pattern_nvgre_2[] = {
1555         RTE_FLOW_ITEM_TYPE_ETH,
1556         RTE_FLOW_ITEM_TYPE_IPV6,
1557         RTE_FLOW_ITEM_TYPE_NVGRE,
1558         RTE_FLOW_ITEM_TYPE_ETH,
1559         RTE_FLOW_ITEM_TYPE_END,
1560 };
1561
1562 static enum rte_flow_item_type pattern_nvgre_3[] = {
1563         RTE_FLOW_ITEM_TYPE_ETH,
1564         RTE_FLOW_ITEM_TYPE_IPV4,
1565         RTE_FLOW_ITEM_TYPE_NVGRE,
1566         RTE_FLOW_ITEM_TYPE_ETH,
1567         RTE_FLOW_ITEM_TYPE_VLAN,
1568         RTE_FLOW_ITEM_TYPE_END,
1569 };
1570
1571 static enum rte_flow_item_type pattern_nvgre_4[] = {
1572         RTE_FLOW_ITEM_TYPE_ETH,
1573         RTE_FLOW_ITEM_TYPE_IPV6,
1574         RTE_FLOW_ITEM_TYPE_NVGRE,
1575         RTE_FLOW_ITEM_TYPE_ETH,
1576         RTE_FLOW_ITEM_TYPE_VLAN,
1577         RTE_FLOW_ITEM_TYPE_END,
1578 };
1579
1580 static enum rte_flow_item_type pattern_mpls_1[] = {
1581         RTE_FLOW_ITEM_TYPE_ETH,
1582         RTE_FLOW_ITEM_TYPE_IPV4,
1583         RTE_FLOW_ITEM_TYPE_UDP,
1584         RTE_FLOW_ITEM_TYPE_MPLS,
1585         RTE_FLOW_ITEM_TYPE_END,
1586 };
1587
1588 static enum rte_flow_item_type pattern_mpls_2[] = {
1589         RTE_FLOW_ITEM_TYPE_ETH,
1590         RTE_FLOW_ITEM_TYPE_IPV6,
1591         RTE_FLOW_ITEM_TYPE_UDP,
1592         RTE_FLOW_ITEM_TYPE_MPLS,
1593         RTE_FLOW_ITEM_TYPE_END,
1594 };
1595
1596 static enum rte_flow_item_type pattern_mpls_3[] = {
1597         RTE_FLOW_ITEM_TYPE_ETH,
1598         RTE_FLOW_ITEM_TYPE_IPV4,
1599         RTE_FLOW_ITEM_TYPE_GRE,
1600         RTE_FLOW_ITEM_TYPE_MPLS,
1601         RTE_FLOW_ITEM_TYPE_END,
1602 };
1603
1604 static enum rte_flow_item_type pattern_mpls_4[] = {
1605         RTE_FLOW_ITEM_TYPE_ETH,
1606         RTE_FLOW_ITEM_TYPE_IPV6,
1607         RTE_FLOW_ITEM_TYPE_GRE,
1608         RTE_FLOW_ITEM_TYPE_MPLS,
1609         RTE_FLOW_ITEM_TYPE_END,
1610 };
1611
1612 static enum rte_flow_item_type pattern_qinq_1[] = {
1613         RTE_FLOW_ITEM_TYPE_ETH,
1614         RTE_FLOW_ITEM_TYPE_VLAN,
1615         RTE_FLOW_ITEM_TYPE_VLAN,
1616         RTE_FLOW_ITEM_TYPE_END,
1617 };
1618
1619 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1620         /* Ethertype */
1621         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1622         /* FDIR - support default flow type without flexible payload*/
1623         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1638         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1639         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1640         /* FDIR - support default flow type with flexible payload */
1641         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1667         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1668         /* FDIR - support single vlan input set */
1669         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1704         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1705         /* FDIR - support VF item */
1706         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1776         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1777         /* VXLAN */
1778         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1780         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1781         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1782         /* NVGRE */
1783         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1785         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1786         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1787         /* MPLSoUDP & MPLSoGRE */
1788         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1790         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1791         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1792         /* GTP-C & GTP-U */
1793         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1795         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1796         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1797         /* QINQ */
1798         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1799 };
1800
1801 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1802         do {                                                            \
1803                 act = actions + index;                                  \
1804                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1805                         index++;                                        \
1806                         act = actions + index;                          \
1807                 }                                                       \
1808         } while (0)
1809
1810 /* Find the first VOID or non-VOID item pointer */
1811 static const struct rte_flow_item *
1812 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1813 {
1814         bool is_find;
1815
1816         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1817                 if (is_void)
1818                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1819                 else
1820                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1821                 if (is_find)
1822                         break;
1823                 item++;
1824         }
1825         return item;
1826 }
1827
1828 /* Skip all VOID items of the pattern */
1829 static void
1830 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1831                             const struct rte_flow_item *pattern)
1832 {
1833         uint32_t cpy_count = 0;
1834         const struct rte_flow_item *pb = pattern, *pe = pattern;
1835
1836         for (;;) {
1837                 /* Find a non-void item first */
1838                 pb = i40e_find_first_item(pb, false);
1839                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1840                         pe = pb;
1841                         break;
1842                 }
1843
1844                 /* Find a void item */
1845                 pe = i40e_find_first_item(pb + 1, true);
1846
1847                 cpy_count = pe - pb;
1848                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1849
1850                 items += cpy_count;
1851
1852                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1853                         pb = pe;
1854                         break;
1855                 }
1856
1857                 pb = pe + 1;
1858         }
1859         /* Copy the END item. */
1860         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1861 }
1862
1863 /* Check if the pattern matches a supported item type array */
1864 static bool
1865 i40e_match_pattern(enum rte_flow_item_type *item_array,
1866                    struct rte_flow_item *pattern)
1867 {
1868         struct rte_flow_item *item = pattern;
1869
1870         while ((*item_array == item->type) &&
1871                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1872                 item_array++;
1873                 item++;
1874         }
1875
1876         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1877                 item->type == RTE_FLOW_ITEM_TYPE_END);
1878 }
1879
1880 /* Find if there's parse filter function matched */
1881 static parse_filter_t
1882 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1883 {
1884         parse_filter_t parse_filter = NULL;
1885         uint8_t i = *idx;
1886
1887         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1888                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1889                                         pattern)) {
1890                         parse_filter = i40e_supported_patterns[i].parse_filter;
1891                         break;
1892                 }
1893         }
1894
1895         *idx = ++i;
1896
1897         return parse_filter;
1898 }
1899
1900 /* Parse attributes */
1901 static int
1902 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1903                      struct rte_flow_error *error)
1904 {
1905         /* Must be input direction */
1906         if (!attr->ingress) {
1907                 rte_flow_error_set(error, EINVAL,
1908                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1909                                    attr, "Only support ingress.");
1910                 return -rte_errno;
1911         }
1912
1913         /* Not supported */
1914         if (attr->egress) {
1915                 rte_flow_error_set(error, EINVAL,
1916                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1917                                    attr, "Not support egress.");
1918                 return -rte_errno;
1919         }
1920
1921         /* Not supported */
1922         if (attr->priority) {
1923                 rte_flow_error_set(error, EINVAL,
1924                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1925                                    attr, "Not support priority.");
1926                 return -rte_errno;
1927         }
1928
1929         /* Not supported */
1930         if (attr->group) {
1931                 rte_flow_error_set(error, EINVAL,
1932                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1933                                    attr, "Not support group.");
1934                 return -rte_errno;
1935         }
1936
1937         return 0;
1938 }
1939
1940 static uint16_t
1941 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1942 {
1943         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1944         int qinq = dev->data->dev_conf.rxmode.offloads &
1945                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1946         uint64_t reg_r = 0;
1947         uint16_t reg_id;
1948         uint16_t tpid;
1949
1950         if (qinq)
1951                 reg_id = 2;
1952         else
1953                 reg_id = 3;
1954
1955         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1956                                     &reg_r, NULL);
1957
1958         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1959
1960         return tpid;
1961 }
1962
1963 /* 1. Last in item should be NULL as range is not supported.
1964  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1965  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1966  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1967  *    FF:FF:FF:FF:FF:FF
1968  * 5. Ether_type mask should be 0xFFFF.
1969  */
1970 static int
1971 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1972                                   const struct rte_flow_item *pattern,
1973                                   struct rte_flow_error *error,
1974                                   struct rte_eth_ethertype_filter *filter)
1975 {
1976         const struct rte_flow_item *item = pattern;
1977         const struct rte_flow_item_eth *eth_spec;
1978         const struct rte_flow_item_eth *eth_mask;
1979         enum rte_flow_item_type item_type;
1980         uint16_t outer_tpid;
1981
1982         outer_tpid = i40e_get_outer_vlan(dev);
1983
1984         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1985                 if (item->last) {
1986                         rte_flow_error_set(error, EINVAL,
1987                                            RTE_FLOW_ERROR_TYPE_ITEM,
1988                                            item,
1989                                            "Not support range");
1990                         return -rte_errno;
1991                 }
1992                 item_type = item->type;
1993                 switch (item_type) {
1994                 case RTE_FLOW_ITEM_TYPE_ETH:
1995                         eth_spec = item->spec;
1996                         eth_mask = item->mask;
1997                         /* Get the MAC info. */
1998                         if (!eth_spec || !eth_mask) {
1999                                 rte_flow_error_set(error, EINVAL,
2000                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2001                                                    item,
2002                                                    "NULL ETH spec/mask");
2003                                 return -rte_errno;
2004                         }
2005
2006                         /* Mask bits of source MAC address must be full of 0.
2007                          * Mask bits of destination MAC address must be full
2008                          * of 1 or full of 0.
2009                          */
2010                         if (!is_zero_ether_addr(&eth_mask->src) ||
2011                             (!is_zero_ether_addr(&eth_mask->dst) &&
2012                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2013                                 rte_flow_error_set(error, EINVAL,
2014                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2015                                                    item,
2016                                                    "Invalid MAC_addr mask");
2017                                 return -rte_errno;
2018                         }
2019
2020                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2021                                 rte_flow_error_set(error, EINVAL,
2022                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2023                                                    item,
2024                                                    "Invalid ethertype mask");
2025                                 return -rte_errno;
2026                         }
2027
2028                         /* If mask bits of destination MAC address
2029                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2030                          */
2031                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2032                                 filter->mac_addr = eth_spec->dst;
2033                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2034                         } else {
2035                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2036                         }
2037                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2038
2039                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2040                             filter->ether_type == ETHER_TYPE_IPv6 ||
2041                             filter->ether_type == ETHER_TYPE_LLDP ||
2042                             filter->ether_type == outer_tpid) {
2043                                 rte_flow_error_set(error, EINVAL,
2044                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2045                                                    item,
2046                                                    "Unsupported ether_type in"
2047                                                    " control packet filter.");
2048                                 return -rte_errno;
2049                         }
2050                         break;
2051                 default:
2052                         break;
2053                 }
2054         }
2055
2056         return 0;
2057 }
2058
2059 /* Ethertype action only supports QUEUE or DROP. */
2060 static int
2061 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2062                                  const struct rte_flow_action *actions,
2063                                  struct rte_flow_error *error,
2064                                  struct rte_eth_ethertype_filter *filter)
2065 {
2066         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2067         const struct rte_flow_action *act;
2068         const struct rte_flow_action_queue *act_q;
2069         uint32_t index = 0;
2070
2071         /* Check if the first non-void action is QUEUE or DROP. */
2072         NEXT_ITEM_OF_ACTION(act, actions, index);
2073         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2074             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2075                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2076                                    act, "Not supported action.");
2077                 return -rte_errno;
2078         }
2079
2080         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2081                 act_q = act->conf;
2082                 filter->queue = act_q->index;
2083                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2084                         rte_flow_error_set(error, EINVAL,
2085                                            RTE_FLOW_ERROR_TYPE_ACTION,
2086                                            act, "Invalid queue ID for"
2087                                            " ethertype_filter.");
2088                         return -rte_errno;
2089                 }
2090         } else {
2091                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2092         }
2093
2094         /* Check if the next non-void item is END */
2095         index++;
2096         NEXT_ITEM_OF_ACTION(act, actions, index);
2097         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2098                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2099                                    act, "Not supported action.");
2100                 return -rte_errno;
2101         }
2102
2103         return 0;
2104 }
2105
2106 static int
2107 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2108                                  const struct rte_flow_attr *attr,
2109                                  const struct rte_flow_item pattern[],
2110                                  const struct rte_flow_action actions[],
2111                                  struct rte_flow_error *error,
2112                                  union i40e_filter_t *filter)
2113 {
2114         struct rte_eth_ethertype_filter *ethertype_filter =
2115                 &filter->ethertype_filter;
2116         int ret;
2117
2118         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2119                                                 ethertype_filter);
2120         if (ret)
2121                 return ret;
2122
2123         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2124                                                ethertype_filter);
2125         if (ret)
2126                 return ret;
2127
2128         ret = i40e_flow_parse_attr(attr, error);
2129         if (ret)
2130                 return ret;
2131
2132         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2133
2134         return ret;
2135 }
2136
2137 static int
2138 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2139                          const struct rte_flow_item_raw *raw_spec,
2140                          struct rte_flow_error *error)
2141 {
2142         if (!raw_spec->relative) {
2143                 rte_flow_error_set(error, EINVAL,
2144                                    RTE_FLOW_ERROR_TYPE_ITEM,
2145                                    item,
2146                                    "Relative should be 1.");
2147                 return -rte_errno;
2148         }
2149
2150         if (raw_spec->offset % sizeof(uint16_t)) {
2151                 rte_flow_error_set(error, EINVAL,
2152                                    RTE_FLOW_ERROR_TYPE_ITEM,
2153                                    item,
2154                                    "Offset should be even.");
2155                 return -rte_errno;
2156         }
2157
2158         if (raw_spec->search || raw_spec->limit) {
2159                 rte_flow_error_set(error, EINVAL,
2160                                    RTE_FLOW_ERROR_TYPE_ITEM,
2161                                    item,
2162                                    "search or limit is not supported.");
2163                 return -rte_errno;
2164         }
2165
2166         if (raw_spec->offset < 0) {
2167                 rte_flow_error_set(error, EINVAL,
2168                                    RTE_FLOW_ERROR_TYPE_ITEM,
2169                                    item,
2170                                    "Offset should be non-negative.");
2171                 return -rte_errno;
2172         }
2173         return 0;
2174 }
2175
2176 static int
2177 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2178                          struct i40e_fdir_flex_pit *flex_pit,
2179                          enum i40e_flxpld_layer_idx layer_idx,
2180                          uint8_t raw_id)
2181 {
2182         uint8_t field_idx;
2183
2184         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2185         /* Check if the configuration is conflicted */
2186         if (pf->fdir.flex_pit_flag[layer_idx] &&
2187             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2188              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2189              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2190                 return -1;
2191
2192         /* Check if the configuration exists. */
2193         if (pf->fdir.flex_pit_flag[layer_idx] &&
2194             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2195              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2196              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2197                 return 1;
2198
2199         pf->fdir.flex_set[field_idx].src_offset =
2200                 flex_pit->src_offset;
2201         pf->fdir.flex_set[field_idx].size =
2202                 flex_pit->size;
2203         pf->fdir.flex_set[field_idx].dst_offset =
2204                 flex_pit->dst_offset;
2205
2206         return 0;
2207 }
2208
2209 static int
2210 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2211                           enum i40e_filter_pctype pctype,
2212                           uint8_t *mask)
2213 {
2214         struct i40e_fdir_flex_mask flex_mask;
2215         uint16_t mask_tmp;
2216         uint8_t i, nb_bitmask = 0;
2217
2218         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2219         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2220                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2221                 if (mask_tmp) {
2222                         flex_mask.word_mask |=
2223                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2224                         if (mask_tmp != UINT16_MAX) {
2225                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2226                                 flex_mask.bitmask[nb_bitmask].offset =
2227                                         i / sizeof(uint16_t);
2228                                 nb_bitmask++;
2229                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2230                                         return -1;
2231                         }
2232                 }
2233         }
2234         flex_mask.nb_bitmask = nb_bitmask;
2235
2236         if (pf->fdir.flex_mask_flag[pctype] &&
2237             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2238                     sizeof(struct i40e_fdir_flex_mask))))
2239                 return -2;
2240         else if (pf->fdir.flex_mask_flag[pctype] &&
2241                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2242                           sizeof(struct i40e_fdir_flex_mask))))
2243                 return 1;
2244
2245         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2246                sizeof(struct i40e_fdir_flex_mask));
2247         return 0;
2248 }
2249
2250 static void
2251 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2252                             enum i40e_flxpld_layer_idx layer_idx,
2253                             uint8_t raw_id)
2254 {
2255         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2256         uint32_t flx_pit, flx_ort;
2257         uint8_t field_idx;
2258         uint16_t min_next_off = 0;  /* in words */
2259         uint8_t i;
2260
2261         if (raw_id) {
2262                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2263                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2264                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2265                 I40E_WRITE_GLB_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2266                 i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
2267         }
2268
2269         /* Set flex pit */
2270         for (i = 0; i < raw_id; i++) {
2271                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2272                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2273                                      pf->fdir.flex_set[field_idx].size,
2274                                      pf->fdir.flex_set[field_idx].dst_offset);
2275
2276                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2277                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2278                         pf->fdir.flex_set[field_idx].size;
2279         }
2280
2281         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2282                 /* set the non-used register obeying register's constrain */
2283                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2284                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2285                                      NONUSE_FLX_PIT_DEST_OFF);
2286                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2287                 min_next_off++;
2288         }
2289
2290         pf->fdir.flex_pit_flag[layer_idx] = 1;
2291 }
2292
2293 static void
2294 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2295                             enum i40e_filter_pctype pctype)
2296 {
2297         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2298         struct i40e_fdir_flex_mask *flex_mask;
2299         uint32_t flxinset, fd_mask;
2300         uint8_t i;
2301
2302         /* Set flex mask */
2303         flex_mask = &pf->fdir.flex_mask[pctype];
2304         flxinset = (flex_mask->word_mask <<
2305                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2306                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2307         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2308
2309         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2310                 fd_mask = (flex_mask->bitmask[i].mask <<
2311                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2312                         I40E_PRTQF_FD_MSK_MASK_MASK;
2313                 fd_mask |= ((flex_mask->bitmask[i].offset +
2314                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2315                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2316                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2317                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2318         }
2319
2320         pf->fdir.flex_mask_flag[pctype] = 1;
2321 }
2322
2323 static int
2324 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2325                          enum i40e_filter_pctype pctype,
2326                          uint64_t input_set)
2327 {
2328         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2329         uint64_t inset_reg = 0;
2330         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2331         int i, num;
2332
2333         /* Check if the input set is valid */
2334         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2335                                     input_set) != 0) {
2336                 PMD_DRV_LOG(ERR, "Invalid input set");
2337                 return -EINVAL;
2338         }
2339
2340         /* Check if the configuration is conflicted */
2341         if (pf->fdir.inset_flag[pctype] &&
2342             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2343                 return -1;
2344
2345         if (pf->fdir.inset_flag[pctype] &&
2346             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2347                 return 0;
2348
2349         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2350                                            I40E_INSET_MASK_NUM_REG);
2351         if (num < 0)
2352                 return -EINVAL;
2353
2354         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2355
2356         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2357                              (uint32_t)(inset_reg & UINT32_MAX));
2358         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2359                              (uint32_t)((inset_reg >>
2360                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2361
2362         for (i = 0; i < num; i++)
2363                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2364                                      mask_reg[i]);
2365
2366         /*clear unused mask registers of the pctype */
2367         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2368                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2369         I40E_WRITE_FLUSH(hw);
2370
2371         pf->fdir.input_set[pctype] = input_set;
2372         pf->fdir.inset_flag[pctype] = 1;
2373         return 0;
2374 }
2375
2376 static uint8_t
2377 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2378                                 enum rte_flow_item_type item_type,
2379                                 struct i40e_fdir_filter_conf *filter)
2380 {
2381         struct i40e_customized_pctype *cus_pctype = NULL;
2382
2383         switch (item_type) {
2384         case RTE_FLOW_ITEM_TYPE_GTPC:
2385                 cus_pctype = i40e_find_customized_pctype(pf,
2386                                                          I40E_CUSTOMIZED_GTPC);
2387                 break;
2388         case RTE_FLOW_ITEM_TYPE_GTPU:
2389                 if (!filter->input.flow_ext.inner_ip)
2390                         cus_pctype = i40e_find_customized_pctype(pf,
2391                                                          I40E_CUSTOMIZED_GTPU);
2392                 else if (filter->input.flow_ext.iip_type ==
2393                          I40E_FDIR_IPTYPE_IPV4)
2394                         cus_pctype = i40e_find_customized_pctype(pf,
2395                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2396                 else if (filter->input.flow_ext.iip_type ==
2397                          I40E_FDIR_IPTYPE_IPV6)
2398                         cus_pctype = i40e_find_customized_pctype(pf,
2399                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2400                 break;
2401         default:
2402                 PMD_DRV_LOG(ERR, "Unsupported item type");
2403                 break;
2404         }
2405
2406         if (cus_pctype && cus_pctype->valid)
2407                 return cus_pctype->pctype;
2408
2409         return I40E_FILTER_PCTYPE_INVALID;
2410 }
2411
2412 /* 1. Last in item should be NULL as range is not supported.
2413  * 2. Supported patterns: refer to array i40e_supported_patterns.
2414  * 3. Default supported flow type and input set: refer to array
2415  *    valid_fdir_inset_table in i40e_ethdev.c.
2416  * 4. Mask of fields which need to be matched should be
2417  *    filled with 1.
2418  * 5. Mask of fields which needn't to be matched should be
2419  *    filled with 0.
2420  * 6. GTP profile supports GTPv1 only.
2421  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2422  */
2423 static int
2424 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2425                              const struct rte_flow_attr *attr,
2426                              const struct rte_flow_item *pattern,
2427                              struct rte_flow_error *error,
2428                              struct i40e_fdir_filter_conf *filter)
2429 {
2430         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2431         const struct rte_flow_item *item = pattern;
2432         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2433         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2434         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2435         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2436         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2437         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2438         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2439         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2440         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2441         const struct rte_flow_item_vf *vf_spec;
2442
2443         uint8_t pctype = 0;
2444         uint64_t input_set = I40E_INSET_NONE;
2445         uint16_t frag_off;
2446         enum rte_flow_item_type item_type;
2447         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2448         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2449         uint32_t i, j;
2450         uint8_t  ipv6_addr_mask[16] = {
2451                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2452                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2453         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2454         uint8_t raw_id = 0;
2455         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2456         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2457         struct i40e_fdir_flex_pit flex_pit;
2458         uint8_t next_dst_off = 0;
2459         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2460         uint16_t flex_size;
2461         bool cfg_flex_pit = true;
2462         bool cfg_flex_msk = true;
2463         uint16_t outer_tpid;
2464         uint16_t ether_type;
2465         uint32_t vtc_flow_cpu;
2466         bool outer_ip = true;
2467         int ret;
2468
2469         memset(off_arr, 0, sizeof(off_arr));
2470         memset(len_arr, 0, sizeof(len_arr));
2471         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2472         outer_tpid = i40e_get_outer_vlan(dev);
2473         filter->input.flow_ext.customized_pctype = false;
2474         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2475                 if (item->last) {
2476                         rte_flow_error_set(error, EINVAL,
2477                                            RTE_FLOW_ERROR_TYPE_ITEM,
2478                                            item,
2479                                            "Not support range");
2480                         return -rte_errno;
2481                 }
2482                 item_type = item->type;
2483                 switch (item_type) {
2484                 case RTE_FLOW_ITEM_TYPE_ETH:
2485                         eth_spec = item->spec;
2486                         eth_mask = item->mask;
2487
2488                         if (eth_spec && eth_mask) {
2489                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2490                                     !is_zero_ether_addr(&eth_mask->dst)) {
2491                                         rte_flow_error_set(error, EINVAL,
2492                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2493                                                       item,
2494                                                       "Invalid MAC_addr mask.");
2495                                         return -rte_errno;
2496                                 }
2497                         }
2498                         if (eth_spec && eth_mask && eth_mask->type) {
2499                                 enum rte_flow_item_type next = (item + 1)->type;
2500
2501                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2502                                         rte_flow_error_set(error, EINVAL,
2503                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2504                                                       item,
2505                                                       "Invalid type mask.");
2506                                         return -rte_errno;
2507                                 }
2508
2509                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2510
2511                                 if (next == RTE_FLOW_ITEM_TYPE_VLAN ||
2512                                     ether_type == ETHER_TYPE_IPv4 ||
2513                                     ether_type == ETHER_TYPE_IPv6 ||
2514                                     ether_type == ETHER_TYPE_ARP ||
2515                                     ether_type == outer_tpid) {
2516                                         rte_flow_error_set(error, EINVAL,
2517                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2518                                                      item,
2519                                                      "Unsupported ether_type.");
2520                                         return -rte_errno;
2521                                 }
2522                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2523                                 filter->input.flow.l2_flow.ether_type =
2524                                         eth_spec->type;
2525                         }
2526
2527                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2528                         layer_idx = I40E_FLXPLD_L2_IDX;
2529
2530                         break;
2531                 case RTE_FLOW_ITEM_TYPE_VLAN:
2532                         vlan_spec = item->spec;
2533                         vlan_mask = item->mask;
2534
2535                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2536                         if (vlan_spec && vlan_mask) {
2537                                 if (vlan_mask->tci ==
2538                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2539                                         input_set |= I40E_INSET_VLAN_INNER;
2540                                         filter->input.flow_ext.vlan_tci =
2541                                                 vlan_spec->tci;
2542                                 }
2543                         }
2544                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2545                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2546                                         rte_flow_error_set(error, EINVAL,
2547                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2548                                                       item,
2549                                                       "Invalid inner_type"
2550                                                       " mask.");
2551                                         return -rte_errno;
2552                                 }
2553
2554                                 ether_type =
2555                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2556
2557                                 if (ether_type == ETHER_TYPE_IPv4 ||
2558                                     ether_type == ETHER_TYPE_IPv6 ||
2559                                     ether_type == ETHER_TYPE_ARP ||
2560                                     ether_type == outer_tpid) {
2561                                         rte_flow_error_set(error, EINVAL,
2562                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2563                                                      item,
2564                                                      "Unsupported inner_type.");
2565                                         return -rte_errno;
2566                                 }
2567                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2568                                 filter->input.flow.l2_flow.ether_type =
2569                                         vlan_spec->inner_type;
2570                         }
2571
2572                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2573                         layer_idx = I40E_FLXPLD_L2_IDX;
2574
2575                         break;
2576                 case RTE_FLOW_ITEM_TYPE_IPV4:
2577                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2578                         ipv4_spec = item->spec;
2579                         ipv4_mask = item->mask;
2580                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2581                         layer_idx = I40E_FLXPLD_L3_IDX;
2582
2583                         if (ipv4_spec && ipv4_mask && outer_ip) {
2584                                 /* Check IPv4 mask and update input set */
2585                                 if (ipv4_mask->hdr.version_ihl ||
2586                                     ipv4_mask->hdr.total_length ||
2587                                     ipv4_mask->hdr.packet_id ||
2588                                     ipv4_mask->hdr.fragment_offset ||
2589                                     ipv4_mask->hdr.hdr_checksum) {
2590                                         rte_flow_error_set(error, EINVAL,
2591                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2592                                                    item,
2593                                                    "Invalid IPv4 mask.");
2594                                         return -rte_errno;
2595                                 }
2596
2597                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2598                                         input_set |= I40E_INSET_IPV4_SRC;
2599                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2600                                         input_set |= I40E_INSET_IPV4_DST;
2601                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2602                                         input_set |= I40E_INSET_IPV4_TOS;
2603                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2604                                         input_set |= I40E_INSET_IPV4_TTL;
2605                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2606                                         input_set |= I40E_INSET_IPV4_PROTO;
2607
2608                                 /* Check if it is fragment. */
2609                                 frag_off = ipv4_spec->hdr.fragment_offset;
2610                                 frag_off = rte_be_to_cpu_16(frag_off);
2611                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2612                                     frag_off & IPV4_HDR_MF_FLAG)
2613                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2614
2615                                 /* Get the filter info */
2616                                 filter->input.flow.ip4_flow.proto =
2617                                         ipv4_spec->hdr.next_proto_id;
2618                                 filter->input.flow.ip4_flow.tos =
2619                                         ipv4_spec->hdr.type_of_service;
2620                                 filter->input.flow.ip4_flow.ttl =
2621                                         ipv4_spec->hdr.time_to_live;
2622                                 filter->input.flow.ip4_flow.src_ip =
2623                                         ipv4_spec->hdr.src_addr;
2624                                 filter->input.flow.ip4_flow.dst_ip =
2625                                         ipv4_spec->hdr.dst_addr;
2626                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2627                                 filter->input.flow_ext.inner_ip = true;
2628                                 filter->input.flow_ext.iip_type =
2629                                         I40E_FDIR_IPTYPE_IPV4;
2630                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2631                                 rte_flow_error_set(error, EINVAL,
2632                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2633                                                    item,
2634                                                    "Invalid inner IPv4 mask.");
2635                                 return -rte_errno;
2636                         }
2637
2638                         if (outer_ip)
2639                                 outer_ip = false;
2640
2641                         break;
2642                 case RTE_FLOW_ITEM_TYPE_IPV6:
2643                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2644                         ipv6_spec = item->spec;
2645                         ipv6_mask = item->mask;
2646                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2647                         layer_idx = I40E_FLXPLD_L3_IDX;
2648
2649                         if (ipv6_spec && ipv6_mask && outer_ip) {
2650                                 /* Check IPv6 mask and update input set */
2651                                 if (ipv6_mask->hdr.payload_len) {
2652                                         rte_flow_error_set(error, EINVAL,
2653                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2654                                                    item,
2655                                                    "Invalid IPv6 mask");
2656                                         return -rte_errno;
2657                                 }
2658
2659                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2660                                             ipv6_addr_mask,
2661                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2662                                         input_set |= I40E_INSET_IPV6_SRC;
2663                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2664                                             ipv6_addr_mask,
2665                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2666                                         input_set |= I40E_INSET_IPV6_DST;
2667
2668                                 if ((ipv6_mask->hdr.vtc_flow &
2669                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2670                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2671                                         input_set |= I40E_INSET_IPV6_TC;
2672                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2673                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2674                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2675                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2676
2677                                 /* Get filter info */
2678                                 vtc_flow_cpu =
2679                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2680                                 filter->input.flow.ipv6_flow.tc =
2681                                         (uint8_t)(vtc_flow_cpu >>
2682                                                   I40E_FDIR_IPv6_TC_OFFSET);
2683                                 filter->input.flow.ipv6_flow.proto =
2684                                         ipv6_spec->hdr.proto;
2685                                 filter->input.flow.ipv6_flow.hop_limits =
2686                                         ipv6_spec->hdr.hop_limits;
2687
2688                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2689                                            ipv6_spec->hdr.src_addr, 16);
2690                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2691                                            ipv6_spec->hdr.dst_addr, 16);
2692
2693                                 /* Check if it is fragment. */
2694                                 if (ipv6_spec->hdr.proto ==
2695                                     I40E_IPV6_FRAG_HEADER)
2696                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2697                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2698                                 filter->input.flow_ext.inner_ip = true;
2699                                 filter->input.flow_ext.iip_type =
2700                                         I40E_FDIR_IPTYPE_IPV6;
2701                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2702                                 rte_flow_error_set(error, EINVAL,
2703                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2704                                                    item,
2705                                                    "Invalid inner IPv6 mask");
2706                                 return -rte_errno;
2707                         }
2708
2709                         if (outer_ip)
2710                                 outer_ip = false;
2711                         break;
2712                 case RTE_FLOW_ITEM_TYPE_TCP:
2713                         tcp_spec = item->spec;
2714                         tcp_mask = item->mask;
2715
2716                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2717                                 pctype =
2718                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2719                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2720                                 pctype =
2721                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2722                         if (tcp_spec && tcp_mask) {
2723                                 /* Check TCP mask and update input set */
2724                                 if (tcp_mask->hdr.sent_seq ||
2725                                     tcp_mask->hdr.recv_ack ||
2726                                     tcp_mask->hdr.data_off ||
2727                                     tcp_mask->hdr.tcp_flags ||
2728                                     tcp_mask->hdr.rx_win ||
2729                                     tcp_mask->hdr.cksum ||
2730                                     tcp_mask->hdr.tcp_urp) {
2731                                         rte_flow_error_set(error, EINVAL,
2732                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2733                                                    item,
2734                                                    "Invalid TCP mask");
2735                                         return -rte_errno;
2736                                 }
2737
2738                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2739                                         input_set |= I40E_INSET_SRC_PORT;
2740                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2741                                         input_set |= I40E_INSET_DST_PORT;
2742
2743                                 /* Get filter info */
2744                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2745                                         filter->input.flow.tcp4_flow.src_port =
2746                                                 tcp_spec->hdr.src_port;
2747                                         filter->input.flow.tcp4_flow.dst_port =
2748                                                 tcp_spec->hdr.dst_port;
2749                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2750                                         filter->input.flow.tcp6_flow.src_port =
2751                                                 tcp_spec->hdr.src_port;
2752                                         filter->input.flow.tcp6_flow.dst_port =
2753                                                 tcp_spec->hdr.dst_port;
2754                                 }
2755                         }
2756
2757                         layer_idx = I40E_FLXPLD_L4_IDX;
2758
2759                         break;
2760                 case RTE_FLOW_ITEM_TYPE_UDP:
2761                         udp_spec = item->spec;
2762                         udp_mask = item->mask;
2763
2764                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2765                                 pctype =
2766                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2767                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2768                                 pctype =
2769                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2770
2771                         if (udp_spec && udp_mask) {
2772                                 /* Check UDP mask and update input set*/
2773                                 if (udp_mask->hdr.dgram_len ||
2774                                     udp_mask->hdr.dgram_cksum) {
2775                                         rte_flow_error_set(error, EINVAL,
2776                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2777                                                    item,
2778                                                    "Invalid UDP mask");
2779                                         return -rte_errno;
2780                                 }
2781
2782                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2783                                         input_set |= I40E_INSET_SRC_PORT;
2784                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2785                                         input_set |= I40E_INSET_DST_PORT;
2786
2787                                 /* Get filter info */
2788                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2789                                         filter->input.flow.udp4_flow.src_port =
2790                                                 udp_spec->hdr.src_port;
2791                                         filter->input.flow.udp4_flow.dst_port =
2792                                                 udp_spec->hdr.dst_port;
2793                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2794                                         filter->input.flow.udp6_flow.src_port =
2795                                                 udp_spec->hdr.src_port;
2796                                         filter->input.flow.udp6_flow.dst_port =
2797                                                 udp_spec->hdr.dst_port;
2798                                 }
2799                         }
2800
2801                         layer_idx = I40E_FLXPLD_L4_IDX;
2802
2803                         break;
2804                 case RTE_FLOW_ITEM_TYPE_GTPC:
2805                 case RTE_FLOW_ITEM_TYPE_GTPU:
2806                         if (!pf->gtp_support) {
2807                                 rte_flow_error_set(error, EINVAL,
2808                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2809                                                    item,
2810                                                    "Unsupported protocol");
2811                                 return -rte_errno;
2812                         }
2813
2814                         gtp_spec = item->spec;
2815                         gtp_mask = item->mask;
2816
2817                         if (gtp_spec && gtp_mask) {
2818                                 if (gtp_mask->v_pt_rsv_flags ||
2819                                     gtp_mask->msg_type ||
2820                                     gtp_mask->msg_len ||
2821                                     gtp_mask->teid != UINT32_MAX) {
2822                                         rte_flow_error_set(error, EINVAL,
2823                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2824                                                    item,
2825                                                    "Invalid GTP mask");
2826                                         return -rte_errno;
2827                                 }
2828
2829                                 filter->input.flow.gtp_flow.teid =
2830                                         gtp_spec->teid;
2831                                 filter->input.flow_ext.customized_pctype = true;
2832                                 cus_proto = item_type;
2833                         }
2834                         break;
2835                 case RTE_FLOW_ITEM_TYPE_SCTP:
2836                         sctp_spec = item->spec;
2837                         sctp_mask = item->mask;
2838
2839                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2840                                 pctype =
2841                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2842                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2843                                 pctype =
2844                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2845
2846                         if (sctp_spec && sctp_mask) {
2847                                 /* Check SCTP mask and update input set */
2848                                 if (sctp_mask->hdr.cksum) {
2849                                         rte_flow_error_set(error, EINVAL,
2850                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2851                                                    item,
2852                                                    "Invalid UDP mask");
2853                                         return -rte_errno;
2854                                 }
2855
2856                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2857                                         input_set |= I40E_INSET_SRC_PORT;
2858                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2859                                         input_set |= I40E_INSET_DST_PORT;
2860                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2861                                         input_set |= I40E_INSET_SCTP_VT;
2862
2863                                 /* Get filter info */
2864                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2865                                         filter->input.flow.sctp4_flow.src_port =
2866                                                 sctp_spec->hdr.src_port;
2867                                         filter->input.flow.sctp4_flow.dst_port =
2868                                                 sctp_spec->hdr.dst_port;
2869                                         filter->input.flow.sctp4_flow.verify_tag
2870                                                 = sctp_spec->hdr.tag;
2871                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2872                                         filter->input.flow.sctp6_flow.src_port =
2873                                                 sctp_spec->hdr.src_port;
2874                                         filter->input.flow.sctp6_flow.dst_port =
2875                                                 sctp_spec->hdr.dst_port;
2876                                         filter->input.flow.sctp6_flow.verify_tag
2877                                                 = sctp_spec->hdr.tag;
2878                                 }
2879                         }
2880
2881                         layer_idx = I40E_FLXPLD_L4_IDX;
2882
2883                         break;
2884                 case RTE_FLOW_ITEM_TYPE_RAW:
2885                         raw_spec = item->spec;
2886                         raw_mask = item->mask;
2887
2888                         if (!raw_spec || !raw_mask) {
2889                                 rte_flow_error_set(error, EINVAL,
2890                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2891                                                    item,
2892                                                    "NULL RAW spec/mask");
2893                                 return -rte_errno;
2894                         }
2895
2896                         if (pf->support_multi_driver) {
2897                                 rte_flow_error_set(error, ENOTSUP,
2898                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2899                                                    item,
2900                                                    "Unsupported flexible payload.");
2901                                 return -rte_errno;
2902                         }
2903
2904                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2905                         if (ret < 0)
2906                                 return ret;
2907
2908                         off_arr[raw_id] = raw_spec->offset;
2909                         len_arr[raw_id] = raw_spec->length;
2910
2911                         flex_size = 0;
2912                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2913                         flex_pit.size =
2914                                 raw_spec->length / sizeof(uint16_t);
2915                         flex_pit.dst_offset =
2916                                 next_dst_off / sizeof(uint16_t);
2917
2918                         for (i = 0; i <= raw_id; i++) {
2919                                 if (i == raw_id)
2920                                         flex_pit.src_offset +=
2921                                                 raw_spec->offset /
2922                                                 sizeof(uint16_t);
2923                                 else
2924                                         flex_pit.src_offset +=
2925                                                 (off_arr[i] + len_arr[i]) /
2926                                                 sizeof(uint16_t);
2927                                 flex_size += len_arr[i];
2928                         }
2929                         if (((flex_pit.src_offset + flex_pit.size) >=
2930                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2931                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2932                                 rte_flow_error_set(error, EINVAL,
2933                                            RTE_FLOW_ERROR_TYPE_ITEM,
2934                                            item,
2935                                            "Exceeds maxmial payload limit.");
2936                                 return -rte_errno;
2937                         }
2938
2939                         /* Store flex pit to SW */
2940                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2941                                                        layer_idx, raw_id);
2942                         if (ret < 0) {
2943                                 rte_flow_error_set(error, EINVAL,
2944                                    RTE_FLOW_ERROR_TYPE_ITEM,
2945                                    item,
2946                                    "Conflict with the first flexible rule.");
2947                                 return -rte_errno;
2948                         } else if (ret > 0)
2949                                 cfg_flex_pit = false;
2950
2951                         for (i = 0; i < raw_spec->length; i++) {
2952                                 j = i + next_dst_off;
2953                                 filter->input.flow_ext.flexbytes[j] =
2954                                         raw_spec->pattern[i];
2955                                 flex_mask[j] = raw_mask->pattern[i];
2956                         }
2957
2958                         next_dst_off += raw_spec->length;
2959                         raw_id++;
2960                         break;
2961                 case RTE_FLOW_ITEM_TYPE_VF:
2962                         vf_spec = item->spec;
2963                         if (!attr->transfer) {
2964                                 rte_flow_error_set(error, ENOTSUP,
2965                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2966                                                    item,
2967                                                    "Matching VF traffic"
2968                                                    " without affecting it"
2969                                                    " (transfer attribute)"
2970                                                    " is unsupported");
2971                                 return -rte_errno;
2972                         }
2973                         filter->input.flow_ext.is_vf = 1;
2974                         filter->input.flow_ext.dst_id = vf_spec->id;
2975                         if (filter->input.flow_ext.is_vf &&
2976                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2977                                 rte_flow_error_set(error, EINVAL,
2978                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2979                                                    item,
2980                                                    "Invalid VF ID for FDIR.");
2981                                 return -rte_errno;
2982                         }
2983                         break;
2984                 default:
2985                         break;
2986                 }
2987         }
2988
2989         /* Get customized pctype value */
2990         if (filter->input.flow_ext.customized_pctype) {
2991                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2992                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2993                         rte_flow_error_set(error, EINVAL,
2994                                            RTE_FLOW_ERROR_TYPE_ITEM,
2995                                            item,
2996                                            "Unsupported pctype");
2997                         return -rte_errno;
2998                 }
2999         }
3000
3001         /* If customized pctype is not used, set fdir configuration.*/
3002         if (!filter->input.flow_ext.customized_pctype) {
3003                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
3004                 if (ret == -1) {
3005                         rte_flow_error_set(error, EINVAL,
3006                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3007                                            "Conflict with the first rule's input set.");
3008                         return -rte_errno;
3009                 } else if (ret == -EINVAL) {
3010                         rte_flow_error_set(error, EINVAL,
3011                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3012                                            "Invalid pattern mask.");
3013                         return -rte_errno;
3014                 }
3015
3016                 /* Store flex mask to SW */
3017                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3018                 if (ret == -1) {
3019                         rte_flow_error_set(error, EINVAL,
3020                                            RTE_FLOW_ERROR_TYPE_ITEM,
3021                                            item,
3022                                            "Exceed maximal number of bitmasks");
3023                         return -rte_errno;
3024                 } else if (ret == -2) {
3025                         rte_flow_error_set(error, EINVAL,
3026                                            RTE_FLOW_ERROR_TYPE_ITEM,
3027                                            item,
3028                                            "Conflict with the first flexible rule");
3029                         return -rte_errno;
3030                 } else if (ret > 0)
3031                         cfg_flex_msk = false;
3032
3033                 if (cfg_flex_pit)
3034                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3035
3036                 if (cfg_flex_msk)
3037                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3038         }
3039
3040         filter->input.pctype = pctype;
3041
3042         return 0;
3043 }
3044
3045 /* Parse to get the action info of a FDIR filter.
3046  * FDIR action supports QUEUE or (QUEUE + MARK).
3047  */
3048 static int
3049 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3050                             const struct rte_flow_action *actions,
3051                             struct rte_flow_error *error,
3052                             struct i40e_fdir_filter_conf *filter)
3053 {
3054         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3055         const struct rte_flow_action *act;
3056         const struct rte_flow_action_queue *act_q;
3057         const struct rte_flow_action_mark *mark_spec;
3058         uint32_t index = 0;
3059
3060         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3061         NEXT_ITEM_OF_ACTION(act, actions, index);
3062         switch (act->type) {
3063         case RTE_FLOW_ACTION_TYPE_QUEUE:
3064                 act_q = act->conf;
3065                 filter->action.rx_queue = act_q->index;
3066                 if ((!filter->input.flow_ext.is_vf &&
3067                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3068                     (filter->input.flow_ext.is_vf &&
3069                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3070                         rte_flow_error_set(error, EINVAL,
3071                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3072                                            "Invalid queue ID for FDIR.");
3073                         return -rte_errno;
3074                 }
3075                 filter->action.behavior = I40E_FDIR_ACCEPT;
3076                 break;
3077         case RTE_FLOW_ACTION_TYPE_DROP:
3078                 filter->action.behavior = I40E_FDIR_REJECT;
3079                 break;
3080         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3081                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3082                 break;
3083         default:
3084                 rte_flow_error_set(error, EINVAL,
3085                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3086                                    "Invalid action.");
3087                 return -rte_errno;
3088         }
3089
3090         /* Check if the next non-void item is MARK or FLAG or END. */
3091         index++;
3092         NEXT_ITEM_OF_ACTION(act, actions, index);
3093         switch (act->type) {
3094         case RTE_FLOW_ACTION_TYPE_MARK:
3095                 mark_spec = act->conf;
3096                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3097                 filter->soft_id = mark_spec->id;
3098                 break;
3099         case RTE_FLOW_ACTION_TYPE_FLAG:
3100                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3101                 break;
3102         case RTE_FLOW_ACTION_TYPE_END:
3103                 return 0;
3104         default:
3105                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3106                                    act, "Invalid action.");
3107                 return -rte_errno;
3108         }
3109
3110         /* Check if the next non-void item is END */
3111         index++;
3112         NEXT_ITEM_OF_ACTION(act, actions, index);
3113         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3114                 rte_flow_error_set(error, EINVAL,
3115                                    RTE_FLOW_ERROR_TYPE_ACTION,
3116                                    act, "Invalid action.");
3117                 return -rte_errno;
3118         }
3119
3120         return 0;
3121 }
3122
3123 static int
3124 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3125                             const struct rte_flow_attr *attr,
3126                             const struct rte_flow_item pattern[],
3127                             const struct rte_flow_action actions[],
3128                             struct rte_flow_error *error,
3129                             union i40e_filter_t *filter)
3130 {
3131         struct i40e_fdir_filter_conf *fdir_filter =
3132                 &filter->fdir_filter;
3133         int ret;
3134
3135         ret = i40e_flow_parse_fdir_pattern(dev, attr, pattern, error,
3136                                            fdir_filter);
3137         if (ret)
3138                 return ret;
3139
3140         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3141         if (ret)
3142                 return ret;
3143
3144         ret = i40e_flow_parse_attr(attr, error);
3145         if (ret)
3146                 return ret;
3147
3148         cons_filter_type = RTE_ETH_FILTER_FDIR;
3149
3150         if (dev->data->dev_conf.fdir_conf.mode !=
3151             RTE_FDIR_MODE_PERFECT) {
3152                 rte_flow_error_set(error, ENOTSUP,
3153                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3154                                    NULL,
3155                                    "Check the mode in fdir_conf.");
3156                 return -rte_errno;
3157         }
3158
3159         return 0;
3160 }
3161
3162 /* Parse to get the action info of a tunnel filter
3163  * Tunnel action only supports PF, VF and QUEUE.
3164  */
3165 static int
3166 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3167                               const struct rte_flow_action *actions,
3168                               struct rte_flow_error *error,
3169                               struct i40e_tunnel_filter_conf *filter)
3170 {
3171         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3172         const struct rte_flow_action *act;
3173         const struct rte_flow_action_queue *act_q;
3174         const struct rte_flow_action_vf *act_vf;
3175         uint32_t index = 0;
3176
3177         /* Check if the first non-void action is PF or VF. */
3178         NEXT_ITEM_OF_ACTION(act, actions, index);
3179         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3180             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3181                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3182                                    act, "Not supported action.");
3183                 return -rte_errno;
3184         }
3185
3186         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3187                 act_vf = act->conf;
3188                 filter->vf_id = act_vf->id;
3189                 filter->is_to_vf = 1;
3190                 if (filter->vf_id >= pf->vf_num) {
3191                         rte_flow_error_set(error, EINVAL,
3192                                    RTE_FLOW_ERROR_TYPE_ACTION,
3193                                    act, "Invalid VF ID for tunnel filter");
3194                         return -rte_errno;
3195                 }
3196         }
3197
3198         /* Check if the next non-void item is QUEUE */
3199         index++;
3200         NEXT_ITEM_OF_ACTION(act, actions, index);
3201         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3202                 act_q = act->conf;
3203                 filter->queue_id = act_q->index;
3204                 if ((!filter->is_to_vf) &&
3205                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3206                         rte_flow_error_set(error, EINVAL,
3207                                    RTE_FLOW_ERROR_TYPE_ACTION,
3208                                    act, "Invalid queue ID for tunnel filter");
3209                         return -rte_errno;
3210                 } else if (filter->is_to_vf &&
3211                            (filter->queue_id >= pf->vf_nb_qps)) {
3212                         rte_flow_error_set(error, EINVAL,
3213                                    RTE_FLOW_ERROR_TYPE_ACTION,
3214                                    act, "Invalid queue ID for tunnel filter");
3215                         return -rte_errno;
3216                 }
3217         }
3218
3219         /* Check if the next non-void item is END */
3220         index++;
3221         NEXT_ITEM_OF_ACTION(act, actions, index);
3222         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3223                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3224                                    act, "Not supported action.");
3225                 return -rte_errno;
3226         }
3227
3228         return 0;
3229 }
3230
3231 static uint16_t i40e_supported_tunnel_filter_types[] = {
3232         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3233         ETH_TUNNEL_FILTER_IVLAN,
3234         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3235         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3236         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3237         ETH_TUNNEL_FILTER_IMAC,
3238         ETH_TUNNEL_FILTER_IMAC,
3239 };
3240
3241 static int
3242 i40e_check_tunnel_filter_type(uint8_t filter_type)
3243 {
3244         uint8_t i;
3245
3246         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3247                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3248                         return 0;
3249         }
3250
3251         return -1;
3252 }
3253
3254 /* 1. Last in item should be NULL as range is not supported.
3255  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3256  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3257  * 3. Mask of fields which need to be matched should be
3258  *    filled with 1.
3259  * 4. Mask of fields which needn't to be matched should be
3260  *    filled with 0.
3261  */
3262 static int
3263 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3264                               const struct rte_flow_item *pattern,
3265                               struct rte_flow_error *error,
3266                               struct i40e_tunnel_filter_conf *filter)
3267 {
3268         const struct rte_flow_item *item = pattern;
3269         const struct rte_flow_item_eth *eth_spec;
3270         const struct rte_flow_item_eth *eth_mask;
3271         const struct rte_flow_item_vxlan *vxlan_spec;
3272         const struct rte_flow_item_vxlan *vxlan_mask;
3273         const struct rte_flow_item_vlan *vlan_spec;
3274         const struct rte_flow_item_vlan *vlan_mask;
3275         uint8_t filter_type = 0;
3276         bool is_vni_masked = 0;
3277         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3278         enum rte_flow_item_type item_type;
3279         bool vxlan_flag = 0;
3280         uint32_t tenant_id_be = 0;
3281         int ret;
3282
3283         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3284                 if (item->last) {
3285                         rte_flow_error_set(error, EINVAL,
3286                                            RTE_FLOW_ERROR_TYPE_ITEM,
3287                                            item,
3288                                            "Not support range");
3289                         return -rte_errno;
3290                 }
3291                 item_type = item->type;
3292                 switch (item_type) {
3293                 case RTE_FLOW_ITEM_TYPE_ETH:
3294                         eth_spec = item->spec;
3295                         eth_mask = item->mask;
3296
3297                         /* Check if ETH item is used for place holder.
3298                          * If yes, both spec and mask should be NULL.
3299                          * If no, both spec and mask shouldn't be NULL.
3300                          */
3301                         if ((!eth_spec && eth_mask) ||
3302                             (eth_spec && !eth_mask)) {
3303                                 rte_flow_error_set(error, EINVAL,
3304                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3305                                                    item,
3306                                                    "Invalid ether spec/mask");
3307                                 return -rte_errno;
3308                         }
3309
3310                         if (eth_spec && eth_mask) {
3311                                 /* DST address of inner MAC shouldn't be masked.
3312                                  * SRC address of Inner MAC should be masked.
3313                                  */
3314                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3315                                     !is_zero_ether_addr(&eth_mask->src) ||
3316                                     eth_mask->type) {
3317                                         rte_flow_error_set(error, EINVAL,
3318                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3319                                                    item,
3320                                                    "Invalid ether spec/mask");
3321                                         return -rte_errno;
3322                                 }
3323
3324                                 if (!vxlan_flag) {
3325                                         rte_memcpy(&filter->outer_mac,
3326                                                    &eth_spec->dst,
3327                                                    ETHER_ADDR_LEN);
3328                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3329                                 } else {
3330                                         rte_memcpy(&filter->inner_mac,
3331                                                    &eth_spec->dst,
3332                                                    ETHER_ADDR_LEN);
3333                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3334                                 }
3335                         }
3336                         break;
3337                 case RTE_FLOW_ITEM_TYPE_VLAN:
3338                         vlan_spec = item->spec;
3339                         vlan_mask = item->mask;
3340                         if (!(vlan_spec && vlan_mask) ||
3341                             vlan_mask->inner_type) {
3342                                 rte_flow_error_set(error, EINVAL,
3343                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3344                                                    item,
3345                                                    "Invalid vlan item");
3346                                 return -rte_errno;
3347                         }
3348
3349                         if (vlan_spec && vlan_mask) {
3350                                 if (vlan_mask->tci ==
3351                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3352                                         filter->inner_vlan =
3353                                               rte_be_to_cpu_16(vlan_spec->tci) &
3354                                               I40E_TCI_MASK;
3355                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3356                         }
3357                         break;
3358                 case RTE_FLOW_ITEM_TYPE_IPV4:
3359                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3360                         /* IPv4 is used to describe protocol,
3361                          * spec and mask should be NULL.
3362                          */
3363                         if (item->spec || item->mask) {
3364                                 rte_flow_error_set(error, EINVAL,
3365                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3366                                                    item,
3367                                                    "Invalid IPv4 item");
3368                                 return -rte_errno;
3369                         }
3370                         break;
3371                 case RTE_FLOW_ITEM_TYPE_IPV6:
3372                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3373                         /* IPv6 is used to describe protocol,
3374                          * spec and mask should be NULL.
3375                          */
3376                         if (item->spec || item->mask) {
3377                                 rte_flow_error_set(error, EINVAL,
3378                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3379                                                    item,
3380                                                    "Invalid IPv6 item");
3381                                 return -rte_errno;
3382                         }
3383                         break;
3384                 case RTE_FLOW_ITEM_TYPE_UDP:
3385                         /* UDP is used to describe protocol,
3386                          * spec and mask should be NULL.
3387                          */
3388                         if (item->spec || item->mask) {
3389                                 rte_flow_error_set(error, EINVAL,
3390                                            RTE_FLOW_ERROR_TYPE_ITEM,
3391                                            item,
3392                                            "Invalid UDP item");
3393                                 return -rte_errno;
3394                         }
3395                         break;
3396                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3397                         vxlan_spec = item->spec;
3398                         vxlan_mask = item->mask;
3399                         /* Check if VXLAN item is used to describe protocol.
3400                          * If yes, both spec and mask should be NULL.
3401                          * If no, both spec and mask shouldn't be NULL.
3402                          */
3403                         if ((!vxlan_spec && vxlan_mask) ||
3404                             (vxlan_spec && !vxlan_mask)) {
3405                                 rte_flow_error_set(error, EINVAL,
3406                                            RTE_FLOW_ERROR_TYPE_ITEM,
3407                                            item,
3408                                            "Invalid VXLAN item");
3409                                 return -rte_errno;
3410                         }
3411
3412                         /* Check if VNI is masked. */
3413                         if (vxlan_spec && vxlan_mask) {
3414                                 is_vni_masked =
3415                                         !!memcmp(vxlan_mask->vni, vni_mask,
3416                                                  RTE_DIM(vni_mask));
3417                                 if (is_vni_masked) {
3418                                         rte_flow_error_set(error, EINVAL,
3419                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3420                                                    item,
3421                                                    "Invalid VNI mask");
3422                                         return -rte_errno;
3423                                 }
3424
3425                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3426                                            vxlan_spec->vni, 3);
3427                                 filter->tenant_id =
3428                                         rte_be_to_cpu_32(tenant_id_be);
3429                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3430                         }
3431
3432                         vxlan_flag = 1;
3433                         break;
3434                 default:
3435                         break;
3436                 }
3437         }
3438
3439         ret = i40e_check_tunnel_filter_type(filter_type);
3440         if (ret < 0) {
3441                 rte_flow_error_set(error, EINVAL,
3442                                    RTE_FLOW_ERROR_TYPE_ITEM,
3443                                    NULL,
3444                                    "Invalid filter type");
3445                 return -rte_errno;
3446         }
3447         filter->filter_type = filter_type;
3448
3449         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3450
3451         return 0;
3452 }
3453
3454 static int
3455 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3456                              const struct rte_flow_attr *attr,
3457                              const struct rte_flow_item pattern[],
3458                              const struct rte_flow_action actions[],
3459                              struct rte_flow_error *error,
3460                              union i40e_filter_t *filter)
3461 {
3462         struct i40e_tunnel_filter_conf *tunnel_filter =
3463                 &filter->consistent_tunnel_filter;
3464         int ret;
3465
3466         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3467                                             error, tunnel_filter);
3468         if (ret)
3469                 return ret;
3470
3471         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3472         if (ret)
3473                 return ret;
3474
3475         ret = i40e_flow_parse_attr(attr, error);
3476         if (ret)
3477                 return ret;
3478
3479         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3480
3481         return ret;
3482 }
3483
3484 /* 1. Last in item should be NULL as range is not supported.
3485  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3486  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3487  * 3. Mask of fields which need to be matched should be
3488  *    filled with 1.
3489  * 4. Mask of fields which needn't to be matched should be
3490  *    filled with 0.
3491  */
3492 static int
3493 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3494                               const struct rte_flow_item *pattern,
3495                               struct rte_flow_error *error,
3496                               struct i40e_tunnel_filter_conf *filter)
3497 {
3498         const struct rte_flow_item *item = pattern;
3499         const struct rte_flow_item_eth *eth_spec;
3500         const struct rte_flow_item_eth *eth_mask;
3501         const struct rte_flow_item_nvgre *nvgre_spec;
3502         const struct rte_flow_item_nvgre *nvgre_mask;
3503         const struct rte_flow_item_vlan *vlan_spec;
3504         const struct rte_flow_item_vlan *vlan_mask;
3505         enum rte_flow_item_type item_type;
3506         uint8_t filter_type = 0;
3507         bool is_tni_masked = 0;
3508         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3509         bool nvgre_flag = 0;
3510         uint32_t tenant_id_be = 0;
3511         int ret;
3512
3513         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3514                 if (item->last) {
3515                         rte_flow_error_set(error, EINVAL,
3516                                            RTE_FLOW_ERROR_TYPE_ITEM,
3517                                            item,
3518                                            "Not support range");
3519                         return -rte_errno;
3520                 }
3521                 item_type = item->type;
3522                 switch (item_type) {
3523                 case RTE_FLOW_ITEM_TYPE_ETH:
3524                         eth_spec = item->spec;
3525                         eth_mask = item->mask;
3526
3527                         /* Check if ETH item is used for place holder.
3528                          * If yes, both spec and mask should be NULL.
3529                          * If no, both spec and mask shouldn't be NULL.
3530                          */
3531                         if ((!eth_spec && eth_mask) ||
3532                             (eth_spec && !eth_mask)) {
3533                                 rte_flow_error_set(error, EINVAL,
3534                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3535                                                    item,
3536                                                    "Invalid ether spec/mask");
3537                                 return -rte_errno;
3538                         }
3539
3540                         if (eth_spec && eth_mask) {
3541                                 /* DST address of inner MAC shouldn't be masked.
3542                                  * SRC address of Inner MAC should be masked.
3543                                  */
3544                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3545                                     !is_zero_ether_addr(&eth_mask->src) ||
3546                                     eth_mask->type) {
3547                                         rte_flow_error_set(error, EINVAL,
3548                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3549                                                    item,
3550                                                    "Invalid ether spec/mask");
3551                                         return -rte_errno;
3552                                 }
3553
3554                                 if (!nvgre_flag) {
3555                                         rte_memcpy(&filter->outer_mac,
3556                                                    &eth_spec->dst,
3557                                                    ETHER_ADDR_LEN);
3558                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3559                                 } else {
3560                                         rte_memcpy(&filter->inner_mac,
3561                                                    &eth_spec->dst,
3562                                                    ETHER_ADDR_LEN);
3563                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3564                                 }
3565                         }
3566
3567                         break;
3568                 case RTE_FLOW_ITEM_TYPE_VLAN:
3569                         vlan_spec = item->spec;
3570                         vlan_mask = item->mask;
3571                         if (!(vlan_spec && vlan_mask) ||
3572                             vlan_mask->inner_type) {
3573                                 rte_flow_error_set(error, EINVAL,
3574                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3575                                                    item,
3576                                                    "Invalid vlan item");
3577                                 return -rte_errno;
3578                         }
3579
3580                         if (vlan_spec && vlan_mask) {
3581                                 if (vlan_mask->tci ==
3582                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3583                                         filter->inner_vlan =
3584                                               rte_be_to_cpu_16(vlan_spec->tci) &
3585                                               I40E_TCI_MASK;
3586                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3587                         }
3588                         break;
3589                 case RTE_FLOW_ITEM_TYPE_IPV4:
3590                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3591                         /* IPv4 is used to describe protocol,
3592                          * spec and mask should be NULL.
3593                          */
3594                         if (item->spec || item->mask) {
3595                                 rte_flow_error_set(error, EINVAL,
3596                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3597                                                    item,
3598                                                    "Invalid IPv4 item");
3599                                 return -rte_errno;
3600                         }
3601                         break;
3602                 case RTE_FLOW_ITEM_TYPE_IPV6:
3603                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3604                         /* IPv6 is used to describe protocol,
3605                          * spec and mask should be NULL.
3606                          */
3607                         if (item->spec || item->mask) {
3608                                 rte_flow_error_set(error, EINVAL,
3609                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3610                                                    item,
3611                                                    "Invalid IPv6 item");
3612                                 return -rte_errno;
3613                         }
3614                         break;
3615                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3616                         nvgre_spec = item->spec;
3617                         nvgre_mask = item->mask;
3618                         /* Check if NVGRE item is used to describe protocol.
3619                          * If yes, both spec and mask should be NULL.
3620                          * If no, both spec and mask shouldn't be NULL.
3621                          */
3622                         if ((!nvgre_spec && nvgre_mask) ||
3623                             (nvgre_spec && !nvgre_mask)) {
3624                                 rte_flow_error_set(error, EINVAL,
3625                                            RTE_FLOW_ERROR_TYPE_ITEM,
3626                                            item,
3627                                            "Invalid NVGRE item");
3628                                 return -rte_errno;
3629                         }
3630
3631                         if (nvgre_spec && nvgre_mask) {
3632                                 is_tni_masked =
3633                                         !!memcmp(nvgre_mask->tni, tni_mask,
3634                                                  RTE_DIM(tni_mask));
3635                                 if (is_tni_masked) {
3636                                         rte_flow_error_set(error, EINVAL,
3637                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3638                                                        item,
3639                                                        "Invalid TNI mask");
3640                                         return -rte_errno;
3641                                 }
3642                                 if (nvgre_mask->protocol &&
3643                                         nvgre_mask->protocol != 0xFFFF) {
3644                                         rte_flow_error_set(error, EINVAL,
3645                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3646                                                 item,
3647                                                 "Invalid NVGRE item");
3648                                         return -rte_errno;
3649                                 }
3650                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3651                                         nvgre_mask->c_k_s_rsvd0_ver !=
3652                                         rte_cpu_to_be_16(0xFFFF)) {
3653                                         rte_flow_error_set(error, EINVAL,
3654                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3655                                                    item,
3656                                                    "Invalid NVGRE item");
3657                                         return -rte_errno;
3658                                 }
3659                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3660                                         rte_cpu_to_be_16(0x2000) &&
3661                                         nvgre_mask->c_k_s_rsvd0_ver) {
3662                                         rte_flow_error_set(error, EINVAL,
3663                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3664                                                    item,
3665                                                    "Invalid NVGRE item");
3666                                         return -rte_errno;
3667                                 }
3668                                 if (nvgre_mask->protocol &&
3669                                         nvgre_spec->protocol !=
3670                                         rte_cpu_to_be_16(0x6558)) {
3671                                         rte_flow_error_set(error, EINVAL,
3672                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3673                                                    item,
3674                                                    "Invalid NVGRE item");
3675                                         return -rte_errno;
3676                                 }
3677                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3678                                            nvgre_spec->tni, 3);
3679                                 filter->tenant_id =
3680                                         rte_be_to_cpu_32(tenant_id_be);
3681                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3682                         }
3683
3684                         nvgre_flag = 1;
3685                         break;
3686                 default:
3687                         break;
3688                 }
3689         }
3690
3691         ret = i40e_check_tunnel_filter_type(filter_type);
3692         if (ret < 0) {
3693                 rte_flow_error_set(error, EINVAL,
3694                                    RTE_FLOW_ERROR_TYPE_ITEM,
3695                                    NULL,
3696                                    "Invalid filter type");
3697                 return -rte_errno;
3698         }
3699         filter->filter_type = filter_type;
3700
3701         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3702
3703         return 0;
3704 }
3705
3706 static int
3707 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3708                              const struct rte_flow_attr *attr,
3709                              const struct rte_flow_item pattern[],
3710                              const struct rte_flow_action actions[],
3711                              struct rte_flow_error *error,
3712                              union i40e_filter_t *filter)
3713 {
3714         struct i40e_tunnel_filter_conf *tunnel_filter =
3715                 &filter->consistent_tunnel_filter;
3716         int ret;
3717
3718         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3719                                             error, tunnel_filter);
3720         if (ret)
3721                 return ret;
3722
3723         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3724         if (ret)
3725                 return ret;
3726
3727         ret = i40e_flow_parse_attr(attr, error);
3728         if (ret)
3729                 return ret;
3730
3731         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3732
3733         return ret;
3734 }
3735
3736 /* 1. Last in item should be NULL as range is not supported.
3737  * 2. Supported filter types: MPLS label.
3738  * 3. Mask of fields which need to be matched should be
3739  *    filled with 1.
3740  * 4. Mask of fields which needn't to be matched should be
3741  *    filled with 0.
3742  */
3743 static int
3744 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3745                              const struct rte_flow_item *pattern,
3746                              struct rte_flow_error *error,
3747                              struct i40e_tunnel_filter_conf *filter)
3748 {
3749         const struct rte_flow_item *item = pattern;
3750         const struct rte_flow_item_mpls *mpls_spec;
3751         const struct rte_flow_item_mpls *mpls_mask;
3752         enum rte_flow_item_type item_type;
3753         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3754         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3755         uint32_t label_be = 0;
3756
3757         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3758                 if (item->last) {
3759                         rte_flow_error_set(error, EINVAL,
3760                                            RTE_FLOW_ERROR_TYPE_ITEM,
3761                                            item,
3762                                            "Not support range");
3763                         return -rte_errno;
3764                 }
3765                 item_type = item->type;
3766                 switch (item_type) {
3767                 case RTE_FLOW_ITEM_TYPE_ETH:
3768                         if (item->spec || item->mask) {
3769                                 rte_flow_error_set(error, EINVAL,
3770                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3771                                                    item,
3772                                                    "Invalid ETH item");
3773                                 return -rte_errno;
3774                         }
3775                         break;
3776                 case RTE_FLOW_ITEM_TYPE_IPV4:
3777                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3778                         /* IPv4 is used to describe protocol,
3779                          * spec and mask should be NULL.
3780                          */
3781                         if (item->spec || item->mask) {
3782                                 rte_flow_error_set(error, EINVAL,
3783                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3784                                                    item,
3785                                                    "Invalid IPv4 item");
3786                                 return -rte_errno;
3787                         }
3788                         break;
3789                 case RTE_FLOW_ITEM_TYPE_IPV6:
3790                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3791                         /* IPv6 is used to describe protocol,
3792                          * spec and mask should be NULL.
3793                          */
3794                         if (item->spec || item->mask) {
3795                                 rte_flow_error_set(error, EINVAL,
3796                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3797                                                    item,
3798                                                    "Invalid IPv6 item");
3799                                 return -rte_errno;
3800                         }
3801                         break;
3802                 case RTE_FLOW_ITEM_TYPE_UDP:
3803                         /* UDP is used to describe protocol,
3804                          * spec and mask should be NULL.
3805                          */
3806                         if (item->spec || item->mask) {
3807                                 rte_flow_error_set(error, EINVAL,
3808                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3809                                                    item,
3810                                                    "Invalid UDP item");
3811                                 return -rte_errno;
3812                         }
3813                         is_mplsoudp = 1;
3814                         break;
3815                 case RTE_FLOW_ITEM_TYPE_GRE:
3816                         /* GRE is used to describe protocol,
3817                          * spec and mask should be NULL.
3818                          */
3819                         if (item->spec || item->mask) {
3820                                 rte_flow_error_set(error, EINVAL,
3821                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3822                                                    item,
3823                                                    "Invalid GRE item");
3824                                 return -rte_errno;
3825                         }
3826                         break;
3827                 case RTE_FLOW_ITEM_TYPE_MPLS:
3828                         mpls_spec = item->spec;
3829                         mpls_mask = item->mask;
3830
3831                         if (!mpls_spec || !mpls_mask) {
3832                                 rte_flow_error_set(error, EINVAL,
3833                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3834                                                    item,
3835                                                    "Invalid MPLS item");
3836                                 return -rte_errno;
3837                         }
3838
3839                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3840                                 rte_flow_error_set(error, EINVAL,
3841                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3842                                                    item,
3843                                                    "Invalid MPLS label mask");
3844                                 return -rte_errno;
3845                         }
3846                         rte_memcpy(((uint8_t *)&label_be + 1),
3847                                    mpls_spec->label_tc_s, 3);
3848                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3849                         break;
3850                 default:
3851                         break;
3852                 }
3853         }
3854
3855         if (is_mplsoudp)
3856                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3857         else
3858                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3859
3860         return 0;
3861 }
3862
3863 static int
3864 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3865                             const struct rte_flow_attr *attr,
3866                             const struct rte_flow_item pattern[],
3867                             const struct rte_flow_action actions[],
3868                             struct rte_flow_error *error,
3869                             union i40e_filter_t *filter)
3870 {
3871         struct i40e_tunnel_filter_conf *tunnel_filter =
3872                 &filter->consistent_tunnel_filter;
3873         int ret;
3874
3875         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3876                                            error, tunnel_filter);
3877         if (ret)
3878                 return ret;
3879
3880         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3881         if (ret)
3882                 return ret;
3883
3884         ret = i40e_flow_parse_attr(attr, error);
3885         if (ret)
3886                 return ret;
3887
3888         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3889
3890         return ret;
3891 }
3892
3893 /* 1. Last in item should be NULL as range is not supported.
3894  * 2. Supported filter types: GTP TEID.
3895  * 3. Mask of fields which need to be matched should be
3896  *    filled with 1.
3897  * 4. Mask of fields which needn't to be matched should be
3898  *    filled with 0.
3899  * 5. GTP profile supports GTPv1 only.
3900  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3901  */
3902 static int
3903 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3904                             const struct rte_flow_item *pattern,
3905                             struct rte_flow_error *error,
3906                             struct i40e_tunnel_filter_conf *filter)
3907 {
3908         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3909         const struct rte_flow_item *item = pattern;
3910         const struct rte_flow_item_gtp *gtp_spec;
3911         const struct rte_flow_item_gtp *gtp_mask;
3912         enum rte_flow_item_type item_type;
3913
3914         if (!pf->gtp_support) {
3915                 rte_flow_error_set(error, EINVAL,
3916                                    RTE_FLOW_ERROR_TYPE_ITEM,
3917                                    item,
3918                                    "GTP is not supported by default.");
3919                 return -rte_errno;
3920         }
3921
3922         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3923                 if (item->last) {
3924                         rte_flow_error_set(error, EINVAL,
3925                                            RTE_FLOW_ERROR_TYPE_ITEM,
3926                                            item,
3927                                            "Not support range");
3928                         return -rte_errno;
3929                 }
3930                 item_type = item->type;
3931                 switch (item_type) {
3932                 case RTE_FLOW_ITEM_TYPE_ETH:
3933                         if (item->spec || item->mask) {
3934                                 rte_flow_error_set(error, EINVAL,
3935                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3936                                                    item,
3937                                                    "Invalid ETH item");
3938                                 return -rte_errno;
3939                         }
3940                         break;
3941                 case RTE_FLOW_ITEM_TYPE_IPV4:
3942                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3943                         /* IPv4 is used to describe protocol,
3944                          * spec and mask should be NULL.
3945                          */
3946                         if (item->spec || item->mask) {
3947                                 rte_flow_error_set(error, EINVAL,
3948                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3949                                                    item,
3950                                                    "Invalid IPv4 item");
3951                                 return -rte_errno;
3952                         }
3953                         break;
3954                 case RTE_FLOW_ITEM_TYPE_UDP:
3955                         if (item->spec || item->mask) {
3956                                 rte_flow_error_set(error, EINVAL,
3957                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3958                                                    item,
3959                                                    "Invalid UDP item");
3960                                 return -rte_errno;
3961                         }
3962                         break;
3963                 case RTE_FLOW_ITEM_TYPE_GTPC:
3964                 case RTE_FLOW_ITEM_TYPE_GTPU:
3965                         gtp_spec = item->spec;
3966                         gtp_mask = item->mask;
3967
3968                         if (!gtp_spec || !gtp_mask) {
3969                                 rte_flow_error_set(error, EINVAL,
3970                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3971                                                    item,
3972                                                    "Invalid GTP item");
3973                                 return -rte_errno;
3974                         }
3975
3976                         if (gtp_mask->v_pt_rsv_flags ||
3977                             gtp_mask->msg_type ||
3978                             gtp_mask->msg_len ||
3979                             gtp_mask->teid != UINT32_MAX) {
3980                                 rte_flow_error_set(error, EINVAL,
3981                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3982                                                    item,
3983                                                    "Invalid GTP mask");
3984                                 return -rte_errno;
3985                         }
3986
3987                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3988                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3989                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3990                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3991
3992                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3993
3994                         break;
3995                 default:
3996                         break;
3997                 }
3998         }
3999
4000         return 0;
4001 }
4002
4003 static int
4004 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
4005                            const struct rte_flow_attr *attr,
4006                            const struct rte_flow_item pattern[],
4007                            const struct rte_flow_action actions[],
4008                            struct rte_flow_error *error,
4009                            union i40e_filter_t *filter)
4010 {
4011         struct i40e_tunnel_filter_conf *tunnel_filter =
4012                 &filter->consistent_tunnel_filter;
4013         int ret;
4014
4015         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4016                                           error, tunnel_filter);
4017         if (ret)
4018                 return ret;
4019
4020         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4021         if (ret)
4022                 return ret;
4023
4024         ret = i40e_flow_parse_attr(attr, error);
4025         if (ret)
4026                 return ret;
4027
4028         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4029
4030         return ret;
4031 }
4032
4033 /* 1. Last in item should be NULL as range is not supported.
4034  * 2. Supported filter types: QINQ.
4035  * 3. Mask of fields which need to be matched should be
4036  *    filled with 1.
4037  * 4. Mask of fields which needn't to be matched should be
4038  *    filled with 0.
4039  */
4040 static int
4041 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4042                               const struct rte_flow_item *pattern,
4043                               struct rte_flow_error *error,
4044                               struct i40e_tunnel_filter_conf *filter)
4045 {
4046         const struct rte_flow_item *item = pattern;
4047         const struct rte_flow_item_vlan *vlan_spec = NULL;
4048         const struct rte_flow_item_vlan *vlan_mask = NULL;
4049         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4050         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4051         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4052         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4053
4054         enum rte_flow_item_type item_type;
4055         bool vlan_flag = 0;
4056
4057         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4058                 if (item->last) {
4059                         rte_flow_error_set(error, EINVAL,
4060                                            RTE_FLOW_ERROR_TYPE_ITEM,
4061                                            item,
4062                                            "Not support range");
4063                         return -rte_errno;
4064                 }
4065                 item_type = item->type;
4066                 switch (item_type) {
4067                 case RTE_FLOW_ITEM_TYPE_ETH:
4068                         if (item->spec || item->mask) {
4069                                 rte_flow_error_set(error, EINVAL,
4070                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4071                                                    item,
4072                                                    "Invalid ETH item");
4073                                 return -rte_errno;
4074                         }
4075                         break;
4076                 case RTE_FLOW_ITEM_TYPE_VLAN:
4077                         vlan_spec = item->spec;
4078                         vlan_mask = item->mask;
4079
4080                         if (!(vlan_spec && vlan_mask) ||
4081                             vlan_mask->inner_type) {
4082                                 rte_flow_error_set(error, EINVAL,
4083                                            RTE_FLOW_ERROR_TYPE_ITEM,
4084                                            item,
4085                                            "Invalid vlan item");
4086                                 return -rte_errno;
4087                         }
4088
4089                         if (!vlan_flag) {
4090                                 o_vlan_spec = vlan_spec;
4091                                 o_vlan_mask = vlan_mask;
4092                                 vlan_flag = 1;
4093                         } else {
4094                                 i_vlan_spec = vlan_spec;
4095                                 i_vlan_mask = vlan_mask;
4096                                 vlan_flag = 0;
4097                         }
4098                         break;
4099
4100                 default:
4101                         break;
4102                 }
4103         }
4104
4105         /* Get filter specification */
4106         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4107                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4108                         (i_vlan_mask != NULL) &&
4109                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4110                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4111                         & I40E_TCI_MASK;
4112                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4113                         & I40E_TCI_MASK;
4114         } else {
4115                         rte_flow_error_set(error, EINVAL,
4116                                            RTE_FLOW_ERROR_TYPE_ITEM,
4117                                            NULL,
4118                                            "Invalid filter type");
4119                         return -rte_errno;
4120         }
4121
4122         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4123         return 0;
4124 }
4125
4126 static int
4127 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4128                               const struct rte_flow_attr *attr,
4129                               const struct rte_flow_item pattern[],
4130                               const struct rte_flow_action actions[],
4131                               struct rte_flow_error *error,
4132                               union i40e_filter_t *filter)
4133 {
4134         struct i40e_tunnel_filter_conf *tunnel_filter =
4135                 &filter->consistent_tunnel_filter;
4136         int ret;
4137
4138         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4139                                              error, tunnel_filter);
4140         if (ret)
4141                 return ret;
4142
4143         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4144         if (ret)
4145                 return ret;
4146
4147         ret = i40e_flow_parse_attr(attr, error);
4148         if (ret)
4149                 return ret;
4150
4151         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4152
4153         return ret;
4154 }
4155
4156 /**
4157  * This function is used to do configuration i40e existing RSS with rte_flow.
4158  * It also enable queue region configuration using flow API for i40e.
4159  * pattern can be used indicate what parameters will be include in flow,
4160  * like user_priority or flowtype for queue region or HASH function for RSS.
4161  * Action is used to transmit parameter like queue index and HASH
4162  * function for RSS, or flowtype for queue region configuration.
4163  * For example:
4164  * pattern:
4165  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4166  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4167  * Case 3: none, indicate RSS related will be parsed in action.
4168  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4169  * So, pattern choice is depened on the purpose of configuration of
4170  * that flow.
4171  * action:
4172  * action RSS will be uaed to transmit valid parameter with
4173  * struct rte_flow_action_rss for all the 3 case.
4174  */
4175 static int
4176 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4177                              const struct rte_flow_item *pattern,
4178                              struct rte_flow_error *error,
4179                              uint8_t *action_flag,
4180                              struct i40e_queue_regions *info)
4181 {
4182         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4183         const struct rte_flow_item *item = pattern;
4184         enum rte_flow_item_type item_type;
4185
4186         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4187                 return 0;
4188
4189         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4190                 if (item->last) {
4191                         rte_flow_error_set(error, EINVAL,
4192                                            RTE_FLOW_ERROR_TYPE_ITEM,
4193                                            item,
4194                                            "Not support range");
4195                         return -rte_errno;
4196                 }
4197                 item_type = item->type;
4198                 switch (item_type) {
4199                 case RTE_FLOW_ITEM_TYPE_ETH:
4200                         *action_flag = 1;
4201                         break;
4202                 case RTE_FLOW_ITEM_TYPE_VLAN:
4203                         vlan_spec = item->spec;
4204                         vlan_mask = item->mask;
4205                         if (vlan_spec && vlan_mask) {
4206                                 if (vlan_mask->tci ==
4207                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4208                                         info->region[0].user_priority[0] =
4209                                                 (rte_be_to_cpu_16(
4210                                                 vlan_spec->tci) >> 13) & 0x7;
4211                                         info->region[0].user_priority_num = 1;
4212                                         info->queue_region_number = 1;
4213                                         *action_flag = 0;
4214                                 }
4215                         }
4216                         break;
4217                 default:
4218                         rte_flow_error_set(error, EINVAL,
4219                                         RTE_FLOW_ERROR_TYPE_ITEM,
4220                                         item,
4221                                         "Not support range");
4222                         return -rte_errno;
4223                 }
4224         }
4225
4226         return 0;
4227 }
4228
4229 /**
4230  * This function is used to parse rss queue index, total queue number and
4231  * hash functions, If the purpose of this configuration is for queue region
4232  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4233  * In queue region configuration, it also need to parse hardware flowtype
4234  * and user_priority from configuration, it will also cheeck the validity
4235  * of these parameters. For example, The queue region sizes should
4236  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4237  * hw_flowtype or PCTYPE max index should be 63, the user priority
4238  * max index should be 7, and so on. And also, queue index should be
4239  * continuous sequence and queue region index should be part of rss
4240  * queue index for this port.
4241  */
4242 static int
4243 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4244                             const struct rte_flow_action *actions,
4245                             struct rte_flow_error *error,
4246                             uint8_t action_flag,
4247                             struct i40e_queue_regions *conf_info,
4248                             union i40e_filter_t *filter)
4249 {
4250         const struct rte_flow_action *act;
4251         const struct rte_flow_action_rss *rss;
4252         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4253         struct i40e_queue_regions *info = &pf->queue_region;
4254         struct i40e_rte_flow_rss_conf *rss_config =
4255                         &filter->rss_conf;
4256         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4257         uint16_t i, j, n, tmp;
4258         uint32_t index = 0;
4259         uint64_t hf_bit = 1;
4260
4261         NEXT_ITEM_OF_ACTION(act, actions, index);
4262         rss = act->conf;
4263
4264         /**
4265          * rss only supports forwarding,
4266          * check if the first not void action is RSS.
4267          */
4268         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4269                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4270                 rte_flow_error_set(error, EINVAL,
4271                         RTE_FLOW_ERROR_TYPE_ACTION,
4272                         act, "Not supported action.");
4273                 return -rte_errno;
4274         }
4275
4276         if (action_flag) {
4277                 for (n = 0; n < 64; n++) {
4278                         if (rss->types & (hf_bit << n)) {
4279                                 conf_info->region[0].hw_flowtype[0] = n;
4280                                 conf_info->region[0].flowtype_num = 1;
4281                                 conf_info->queue_region_number = 1;
4282                                 break;
4283                         }
4284                 }
4285         }
4286
4287         /**
4288          * Do some queue region related parameters check
4289          * in order to keep queue index for queue region to be
4290          * continuous sequence and also to be part of RSS
4291          * queue index for this port.
4292          */
4293         if (conf_info->queue_region_number) {
4294                 for (i = 0; i < rss->queue_num; i++) {
4295                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4296                                 if (rss->queue[i] == rss_info->conf.queue[j])
4297                                         break;
4298                         }
4299                         if (j == rss_info->conf.queue_num) {
4300                                 rte_flow_error_set(error, EINVAL,
4301                                         RTE_FLOW_ERROR_TYPE_ACTION,
4302                                         act,
4303                                         "no valid queues");
4304                                 return -rte_errno;
4305                         }
4306                 }
4307
4308                 for (i = 0; i < rss->queue_num - 1; i++) {
4309                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4310                                 rte_flow_error_set(error, EINVAL,
4311                                         RTE_FLOW_ERROR_TYPE_ACTION,
4312                                         act,
4313                                         "no valid queues");
4314                                 return -rte_errno;
4315                         }
4316                 }
4317         }
4318
4319         /* Parse queue region related parameters from configuration */
4320         for (n = 0; n < conf_info->queue_region_number; n++) {
4321                 if (conf_info->region[n].user_priority_num ||
4322                                 conf_info->region[n].flowtype_num) {
4323                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4324                                         rss->queue_num <= 64)) {
4325                                 rte_flow_error_set(error, EINVAL,
4326                                         RTE_FLOW_ERROR_TYPE_ACTION,
4327                                         act,
4328                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4329                                         "total number of queues do not exceed the VSI allocation");
4330                                 return -rte_errno;
4331                         }
4332
4333                         if (conf_info->region[n].user_priority[n] >=
4334                                         I40E_MAX_USER_PRIORITY) {
4335                                 rte_flow_error_set(error, EINVAL,
4336                                         RTE_FLOW_ERROR_TYPE_ACTION,
4337                                         act,
4338                                         "the user priority max index is 7");
4339                                 return -rte_errno;
4340                         }
4341
4342                         if (conf_info->region[n].hw_flowtype[n] >=
4343                                         I40E_FILTER_PCTYPE_MAX) {
4344                                 rte_flow_error_set(error, EINVAL,
4345                                         RTE_FLOW_ERROR_TYPE_ACTION,
4346                                         act,
4347                                         "the hw_flowtype or PCTYPE max index is 63");
4348                                 return -rte_errno;
4349                         }
4350
4351                         for (i = 0; i < info->queue_region_number; i++) {
4352                                 if (info->region[i].queue_num ==
4353                                     rss->queue_num &&
4354                                         info->region[i].queue_start_index ==
4355                                                 rss->queue[0])
4356                                         break;
4357                         }
4358
4359                         if (i == info->queue_region_number) {
4360                                 if (i > I40E_REGION_MAX_INDEX) {
4361                                         rte_flow_error_set(error, EINVAL,
4362                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4363                                                 act,
4364                                                 "the queue region max index is 7");
4365                                         return -rte_errno;
4366                                 }
4367
4368                                 info->region[i].queue_num =
4369                                         rss->queue_num;
4370                                 info->region[i].queue_start_index =
4371                                         rss->queue[0];
4372                                 info->region[i].region_id =
4373                                         info->queue_region_number;
4374
4375                                 j = info->region[i].user_priority_num;
4376                                 tmp = conf_info->region[n].user_priority[0];
4377                                 if (conf_info->region[n].user_priority_num) {
4378                                         info->region[i].user_priority[j] = tmp;
4379                                         info->region[i].user_priority_num++;
4380                                 }
4381
4382                                 j = info->region[i].flowtype_num;
4383                                 tmp = conf_info->region[n].hw_flowtype[0];
4384                                 if (conf_info->region[n].flowtype_num) {
4385                                         info->region[i].hw_flowtype[j] = tmp;
4386                                         info->region[i].flowtype_num++;
4387                                 }
4388                                 info->queue_region_number++;
4389                         } else {
4390                                 j = info->region[i].user_priority_num;
4391                                 tmp = conf_info->region[n].user_priority[0];
4392                                 if (conf_info->region[n].user_priority_num) {
4393                                         info->region[i].user_priority[j] = tmp;
4394                                         info->region[i].user_priority_num++;
4395                                 }
4396
4397                                 j = info->region[i].flowtype_num;
4398                                 tmp = conf_info->region[n].hw_flowtype[0];
4399                                 if (conf_info->region[n].flowtype_num) {
4400                                         info->region[i].hw_flowtype[j] = tmp;
4401                                         info->region[i].flowtype_num++;
4402                                 }
4403                         }
4404                 }
4405
4406                 rss_config->queue_region_conf = TRUE;
4407         }
4408
4409         /**
4410          * Return function if this flow is used for queue region configuration
4411          */
4412         if (rss_config->queue_region_conf)
4413                 return 0;
4414
4415         if (!rss || !rss->queue_num) {
4416                 rte_flow_error_set(error, EINVAL,
4417                                 RTE_FLOW_ERROR_TYPE_ACTION,
4418                                 act,
4419                                 "no valid queues");
4420                 return -rte_errno;
4421         }
4422
4423         for (n = 0; n < rss->queue_num; n++) {
4424                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4425                         rte_flow_error_set(error, EINVAL,
4426                                    RTE_FLOW_ERROR_TYPE_ACTION,
4427                                    act,
4428                                    "queue id > max number of queues");
4429                         return -rte_errno;
4430                 }
4431         }
4432
4433         /* Parse RSS related parameters from configuration */
4434         if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4435                 return rte_flow_error_set
4436                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4437                          "non-default RSS hash functions are not supported");
4438         if (rss->level)
4439                 return rte_flow_error_set
4440                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4441                          "a nonzero RSS encapsulation level is not supported");
4442         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4443                 return rte_flow_error_set
4444                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4445                          "RSS hash key too large");
4446         if (rss->queue_num > RTE_DIM(rss_config->queue))
4447                 return rte_flow_error_set
4448                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4449                          "too many queues for RSS context");
4450         if (i40e_rss_conf_init(rss_config, rss))
4451                 return rte_flow_error_set
4452                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4453                          "RSS context initialization failure");
4454
4455         index++;
4456
4457         /* check if the next not void action is END */
4458         NEXT_ITEM_OF_ACTION(act, actions, index);
4459         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4460                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4461                 rte_flow_error_set(error, EINVAL,
4462                         RTE_FLOW_ERROR_TYPE_ACTION,
4463                         act, "Not supported action.");
4464                 return -rte_errno;
4465         }
4466         rss_config->queue_region_conf = FALSE;
4467
4468         return 0;
4469 }
4470
4471 static int
4472 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4473                         const struct rte_flow_attr *attr,
4474                         const struct rte_flow_item pattern[],
4475                         const struct rte_flow_action actions[],
4476                         union i40e_filter_t *filter,
4477                         struct rte_flow_error *error)
4478 {
4479         int ret;
4480         struct i40e_queue_regions info;
4481         uint8_t action_flag = 0;
4482
4483         memset(&info, 0, sizeof(struct i40e_queue_regions));
4484
4485         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4486                                         error, &action_flag, &info);
4487         if (ret)
4488                 return ret;
4489
4490         ret = i40e_flow_parse_rss_action(dev, actions, error,
4491                                         action_flag, &info, filter);
4492         if (ret)
4493                 return ret;
4494
4495         ret = i40e_flow_parse_attr(attr, error);
4496         if (ret)
4497                 return ret;
4498
4499         cons_filter_type = RTE_ETH_FILTER_HASH;
4500
4501         return 0;
4502 }
4503
4504 static int
4505 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4506                 struct i40e_rte_flow_rss_conf *conf)
4507 {
4508         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4509         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4510         int ret;
4511
4512         if (conf->queue_region_conf) {
4513                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4514                 conf->queue_region_conf = 0;
4515         } else {
4516                 ret = i40e_config_rss_filter(pf, conf, 1);
4517         }
4518         return ret;
4519 }
4520
4521 static int
4522 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4523                 struct i40e_rte_flow_rss_conf *conf)
4524 {
4525         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4526         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4527
4528         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4529
4530         i40e_config_rss_filter(pf, conf, 0);
4531         return 0;
4532 }
4533
4534 static int
4535 i40e_flow_validate(struct rte_eth_dev *dev,
4536                    const struct rte_flow_attr *attr,
4537                    const struct rte_flow_item pattern[],
4538                    const struct rte_flow_action actions[],
4539                    struct rte_flow_error *error)
4540 {
4541         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4542         parse_filter_t parse_filter;
4543         uint32_t item_num = 0; /* non-void item number of pattern*/
4544         uint32_t i = 0;
4545         bool flag = false;
4546         int ret = I40E_NOT_SUPPORTED;
4547
4548         if (!pattern) {
4549                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4550                                    NULL, "NULL pattern.");
4551                 return -rte_errno;
4552         }
4553
4554         if (!actions) {
4555                 rte_flow_error_set(error, EINVAL,
4556                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4557                                    NULL, "NULL action.");
4558                 return -rte_errno;
4559         }
4560
4561         if (!attr) {
4562                 rte_flow_error_set(error, EINVAL,
4563                                    RTE_FLOW_ERROR_TYPE_ATTR,
4564                                    NULL, "NULL attribute.");
4565                 return -rte_errno;
4566         }
4567
4568         memset(&cons_filter, 0, sizeof(cons_filter));
4569
4570         /* Get the non-void item of action */
4571         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4572                 i++;
4573
4574         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4575                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4576                                         actions, &cons_filter, error);
4577                 return ret;
4578         }
4579
4580         i = 0;
4581         /* Get the non-void item number of pattern */
4582         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4583                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4584                         item_num++;
4585                 i++;
4586         }
4587         item_num++;
4588
4589         items = rte_zmalloc("i40e_pattern",
4590                             item_num * sizeof(struct rte_flow_item), 0);
4591         if (!items) {
4592                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4593                                    NULL, "No memory for PMD internal items.");
4594                 return -ENOMEM;
4595         }
4596
4597         i40e_pattern_skip_void_item(items, pattern);
4598
4599         i = 0;
4600         do {
4601                 parse_filter = i40e_find_parse_filter_func(items, &i);
4602                 if (!parse_filter && !flag) {
4603                         rte_flow_error_set(error, EINVAL,
4604                                            RTE_FLOW_ERROR_TYPE_ITEM,
4605                                            pattern, "Unsupported pattern");
4606                         rte_free(items);
4607                         return -rte_errno;
4608                 }
4609                 if (parse_filter)
4610                         ret = parse_filter(dev, attr, items, actions,
4611                                            error, &cons_filter);
4612                 flag = true;
4613         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4614
4615         rte_free(items);
4616
4617         return ret;
4618 }
4619
4620 static struct rte_flow *
4621 i40e_flow_create(struct rte_eth_dev *dev,
4622                  const struct rte_flow_attr *attr,
4623                  const struct rte_flow_item pattern[],
4624                  const struct rte_flow_action actions[],
4625                  struct rte_flow_error *error)
4626 {
4627         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4628         struct rte_flow *flow;
4629         int ret;
4630
4631         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4632         if (!flow) {
4633                 rte_flow_error_set(error, ENOMEM,
4634                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4635                                    "Failed to allocate memory");
4636                 return flow;
4637         }
4638
4639         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4640         if (ret < 0)
4641                 return NULL;
4642
4643         switch (cons_filter_type) {
4644         case RTE_ETH_FILTER_ETHERTYPE:
4645                 ret = i40e_ethertype_filter_set(pf,
4646                                         &cons_filter.ethertype_filter, 1);
4647                 if (ret)
4648                         goto free_flow;
4649                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4650                                         i40e_ethertype_filter_list);
4651                 break;
4652         case RTE_ETH_FILTER_FDIR:
4653                 ret = i40e_flow_add_del_fdir_filter(dev,
4654                                        &cons_filter.fdir_filter, 1);
4655                 if (ret)
4656                         goto free_flow;
4657                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4658                                         i40e_fdir_filter_list);
4659                 break;
4660         case RTE_ETH_FILTER_TUNNEL:
4661                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4662                             &cons_filter.consistent_tunnel_filter, 1);
4663                 if (ret)
4664                         goto free_flow;
4665                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4666                                         i40e_tunnel_filter_list);
4667                 break;
4668         case RTE_ETH_FILTER_HASH:
4669                 ret = i40e_config_rss_filter_set(dev,
4670                             &cons_filter.rss_conf);
4671                 if (ret)
4672                         goto free_flow;
4673                 flow->rule = &pf->rss_info;
4674                 break;
4675         default:
4676                 goto free_flow;
4677         }
4678
4679         flow->filter_type = cons_filter_type;
4680         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4681         return flow;
4682
4683 free_flow:
4684         rte_flow_error_set(error, -ret,
4685                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4686                            "Failed to create flow.");
4687         rte_free(flow);
4688         return NULL;
4689 }
4690
4691 static int
4692 i40e_flow_destroy(struct rte_eth_dev *dev,
4693                   struct rte_flow *flow,
4694                   struct rte_flow_error *error)
4695 {
4696         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4697         enum rte_filter_type filter_type = flow->filter_type;
4698         int ret = 0;
4699
4700         switch (filter_type) {
4701         case RTE_ETH_FILTER_ETHERTYPE:
4702                 ret = i40e_flow_destroy_ethertype_filter(pf,
4703                          (struct i40e_ethertype_filter *)flow->rule);
4704                 break;
4705         case RTE_ETH_FILTER_TUNNEL:
4706                 ret = i40e_flow_destroy_tunnel_filter(pf,
4707                               (struct i40e_tunnel_filter *)flow->rule);
4708                 break;
4709         case RTE_ETH_FILTER_FDIR:
4710                 ret = i40e_flow_add_del_fdir_filter(dev,
4711                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4712                 break;
4713         case RTE_ETH_FILTER_HASH:
4714                 ret = i40e_config_rss_filter_del(dev,
4715                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4716                 break;
4717         default:
4718                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4719                             filter_type);
4720                 ret = -EINVAL;
4721                 break;
4722         }
4723
4724         if (!ret) {
4725                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4726                 rte_free(flow);
4727         } else
4728                 rte_flow_error_set(error, -ret,
4729                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4730                                    "Failed to destroy flow.");
4731
4732         return ret;
4733 }
4734
4735 static int
4736 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4737                                    struct i40e_ethertype_filter *filter)
4738 {
4739         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4740         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4741         struct i40e_ethertype_filter *node;
4742         struct i40e_control_filter_stats stats;
4743         uint16_t flags = 0;
4744         int ret = 0;
4745
4746         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4747                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4748         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4749                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4750         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4751
4752         memset(&stats, 0, sizeof(stats));
4753         ret = i40e_aq_add_rem_control_packet_filter(hw,
4754                                     filter->input.mac_addr.addr_bytes,
4755                                     filter->input.ether_type,
4756                                     flags, pf->main_vsi->seid,
4757                                     filter->queue, 0, &stats, NULL);
4758         if (ret < 0)
4759                 return ret;
4760
4761         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4762         if (!node)
4763                 return -EINVAL;
4764
4765         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4766
4767         return ret;
4768 }
4769
4770 static int
4771 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4772                                 struct i40e_tunnel_filter *filter)
4773 {
4774         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4775         struct i40e_vsi *vsi;
4776         struct i40e_pf_vf *vf;
4777         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4778         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4779         struct i40e_tunnel_filter *node;
4780         bool big_buffer = 0;
4781         int ret = 0;
4782
4783         memset(&cld_filter, 0, sizeof(cld_filter));
4784         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4785                         (struct ether_addr *)&cld_filter.element.outer_mac);
4786         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4787                         (struct ether_addr *)&cld_filter.element.inner_mac);
4788         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4789         cld_filter.element.flags = filter->input.flags;
4790         cld_filter.element.tenant_id = filter->input.tenant_id;
4791         cld_filter.element.queue_number = filter->queue;
4792         rte_memcpy(cld_filter.general_fields,
4793                    filter->input.general_fields,
4794                    sizeof(cld_filter.general_fields));
4795
4796         if (!filter->is_to_vf)
4797                 vsi = pf->main_vsi;
4798         else {
4799                 vf = &pf->vfs[filter->vf_id];
4800                 vsi = vf->vsi;
4801         }
4802
4803         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4804             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4805             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4806             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4807             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4808             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4809                 big_buffer = 1;
4810
4811         if (big_buffer)
4812                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4813                                                               &cld_filter, 1);
4814         else
4815                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4816                                                    &cld_filter.element, 1);
4817         if (ret < 0)
4818                 return -ENOTSUP;
4819
4820         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4821         if (!node)
4822                 return -EINVAL;
4823
4824         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4825
4826         return ret;
4827 }
4828
4829 static int
4830 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4831 {
4832         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4833         int ret;
4834
4835         ret = i40e_flow_flush_fdir_filter(pf);
4836         if (ret) {
4837                 rte_flow_error_set(error, -ret,
4838                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4839                                    "Failed to flush FDIR flows.");
4840                 return -rte_errno;
4841         }
4842
4843         ret = i40e_flow_flush_ethertype_filter(pf);
4844         if (ret) {
4845                 rte_flow_error_set(error, -ret,
4846                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4847                                    "Failed to ethertype flush flows.");
4848                 return -rte_errno;
4849         }
4850
4851         ret = i40e_flow_flush_tunnel_filter(pf);
4852         if (ret) {
4853                 rte_flow_error_set(error, -ret,
4854                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4855                                    "Failed to flush tunnel flows.");
4856                 return -rte_errno;
4857         }
4858
4859         ret = i40e_flow_flush_rss_filter(dev);
4860         if (ret) {
4861                 rte_flow_error_set(error, -ret,
4862                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4863                                    "Failed to flush rss flows.");
4864                 return -rte_errno;
4865         }
4866
4867         return ret;
4868 }
4869
4870 static int
4871 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4872 {
4873         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4874         struct i40e_fdir_info *fdir_info = &pf->fdir;
4875         struct i40e_fdir_filter *fdir_filter;
4876         enum i40e_filter_pctype pctype;
4877         struct rte_flow *flow;
4878         void *temp;
4879         int ret;
4880
4881         ret = i40e_fdir_flush(dev);
4882         if (!ret) {
4883                 /* Delete FDIR filters in FDIR list. */
4884                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4885                         ret = i40e_sw_fdir_filter_del(pf,
4886                                                       &fdir_filter->fdir.input);
4887                         if (ret < 0)
4888                                 return ret;
4889                 }
4890
4891                 /* Delete FDIR flows in flow list. */
4892                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4893                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4894                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4895                                 rte_free(flow);
4896                         }
4897                 }
4898
4899                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4900                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4901                         pf->fdir.inset_flag[pctype] = 0;
4902         }
4903
4904         return ret;
4905 }
4906
4907 /* Flush all ethertype filters */
4908 static int
4909 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4910 {
4911         struct i40e_ethertype_filter_list
4912                 *ethertype_list = &pf->ethertype.ethertype_list;
4913         struct i40e_ethertype_filter *filter;
4914         struct rte_flow *flow;
4915         void *temp;
4916         int ret = 0;
4917
4918         while ((filter = TAILQ_FIRST(ethertype_list))) {
4919                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4920                 if (ret)
4921                         return ret;
4922         }
4923
4924         /* Delete ethertype flows in flow list. */
4925         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4926                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4927                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4928                         rte_free(flow);
4929                 }
4930         }
4931
4932         return ret;
4933 }
4934
4935 /* Flush all tunnel filters */
4936 static int
4937 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4938 {
4939         struct i40e_tunnel_filter_list
4940                 *tunnel_list = &pf->tunnel.tunnel_list;
4941         struct i40e_tunnel_filter *filter;
4942         struct rte_flow *flow;
4943         void *temp;
4944         int ret = 0;
4945
4946         while ((filter = TAILQ_FIRST(tunnel_list))) {
4947                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4948                 if (ret)
4949                         return ret;
4950         }
4951
4952         /* Delete tunnel flows in flow list. */
4953         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4954                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4955                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4956                         rte_free(flow);
4957                 }
4958         }
4959
4960         return ret;
4961 }
4962
4963 /* remove the rss filter */
4964 static int
4965 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4966 {
4967         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4968         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4970         int32_t ret = -EINVAL;
4971
4972         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4973
4974         if (rss_info->conf.queue_num)
4975                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
4976         return ret;
4977 }