drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_ether.h>
  14 #include <rte_ethdev_driver.h>
  15 #include <rte_log.h>
  16 #include <rte_malloc.h>
  17 #include <rte_eth_ctrl.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_item *pattern,
  57                                         struct rte_flow_error *error,
  58                                         struct i40e_fdir_filter_conf *filter);
  59 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  60                                        const struct rte_flow_action *actions,
  61                                        struct rte_flow_error *error,
  62                                        struct i40e_fdir_filter_conf *filter);
  63 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  64                                  const struct rte_flow_action *actions,
  65                                  struct rte_flow_error *error,
  66                                  struct i40e_tunnel_filter_conf *filter);
  67 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  68                                 struct rte_flow_error *error);
  69 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  70                                     const struct rte_flow_attr *attr,
  71                                     const struct rte_flow_item pattern[],
  72                                     const struct rte_flow_action actions[],
  73                                     struct rte_flow_error *error,
  74                                     union i40e_filter_t *filter);
  75 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  76                                        const struct rte_flow_attr *attr,
  77                                        const struct rte_flow_item pattern[],
  78                                        const struct rte_flow_action actions[],
  79                                        struct rte_flow_error *error,
  80                                        union i40e_filter_t *filter);
  81 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  82                                         const struct rte_flow_attr *attr,
  83                                         const struct rte_flow_item pattern[],
  84                                         const struct rte_flow_action actions[],
  85                                         struct rte_flow_error *error,
  86                                         union i40e_filter_t *filter);
  87 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  88                                         const struct rte_flow_attr *attr,
  89                                         const struct rte_flow_item pattern[],
  90                                         const struct rte_flow_action actions[],
  91                                         struct rte_flow_error *error,
  92                                         union i40e_filter_t *filter);
  93 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  94                                        const struct rte_flow_attr *attr,
  95                                        const struct rte_flow_item pattern[],
  96                                        const struct rte_flow_action actions[],
  97                                        struct rte_flow_error *error,
  98                                        union i40e_filter_t *filter);
  99 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 100                                       const struct rte_flow_attr *attr,
 101                                       const struct rte_flow_item pattern[],
 102                                       const struct rte_flow_action actions[],
 103                                       struct rte_flow_error *error,
 104                                       union i40e_filter_t *filter);
 105 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 106                                       struct i40e_ethertype_filter *filter);
 107 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 108                                            struct i40e_tunnel_filter *filter);
 109 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 110 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 112 static int
 113 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 114 static int
 115 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 116                               const struct rte_flow_attr *attr,
 117                               const struct rte_flow_item pattern[],
 118                               const struct rte_flow_action actions[],
 119                               struct rte_flow_error *error,
 120                               union i40e_filter_t *filter);
 121 static int
 122 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 123                               const struct rte_flow_item *pattern,
 124                               struct rte_flow_error *error,
 125                               struct i40e_tunnel_filter_conf *filter);
 126
 127 const struct rte_flow_ops i40e_flow_ops = {
 128         .validate = i40e_flow_validate,
 129         .create = i40e_flow_create,
 130         .destroy = i40e_flow_destroy,
 131         .flush = i40e_flow_flush,
 132 };
 133
 134 union i40e_filter_t cons_filter;
 135 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 136
 137 /* Pattern matched ethertype filter */
 138 static enum rte_flow_item_type pattern_ethertype[] = {
 139         RTE_FLOW_ITEM_TYPE_ETH,
 140         RTE_FLOW_ITEM_TYPE_END,
 141 };
 142
 143 /* Pattern matched flow director filter */
 144 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 145         RTE_FLOW_ITEM_TYPE_ETH,
 146         RTE_FLOW_ITEM_TYPE_IPV4,
 147         RTE_FLOW_ITEM_TYPE_END,
 148 };
 149
 150 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 151         RTE_FLOW_ITEM_TYPE_ETH,
 152         RTE_FLOW_ITEM_TYPE_IPV4,
 153         RTE_FLOW_ITEM_TYPE_UDP,
 154         RTE_FLOW_ITEM_TYPE_END,
 155 };
 156
 157 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 158         RTE_FLOW_ITEM_TYPE_ETH,
 159         RTE_FLOW_ITEM_TYPE_IPV4,
 160         RTE_FLOW_ITEM_TYPE_TCP,
 161         RTE_FLOW_ITEM_TYPE_END,
 162 };
 163
 164 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 165         RTE_FLOW_ITEM_TYPE_ETH,
 166         RTE_FLOW_ITEM_TYPE_IPV4,
 167         RTE_FLOW_ITEM_TYPE_SCTP,
 168         RTE_FLOW_ITEM_TYPE_END,
 169 };
 170
 171 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 172         RTE_FLOW_ITEM_TYPE_ETH,
 173         RTE_FLOW_ITEM_TYPE_IPV4,
 174         RTE_FLOW_ITEM_TYPE_UDP,
 175         RTE_FLOW_ITEM_TYPE_GTPC,
 176         RTE_FLOW_ITEM_TYPE_END,
 177 };
 178
 179 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 180         RTE_FLOW_ITEM_TYPE_ETH,
 181         RTE_FLOW_ITEM_TYPE_IPV4,
 182         RTE_FLOW_ITEM_TYPE_UDP,
 183         RTE_FLOW_ITEM_TYPE_GTPU,
 184         RTE_FLOW_ITEM_TYPE_END,
 185 };
 186
 187 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 188         RTE_FLOW_ITEM_TYPE_ETH,
 189         RTE_FLOW_ITEM_TYPE_IPV4,
 190         RTE_FLOW_ITEM_TYPE_UDP,
 191         RTE_FLOW_ITEM_TYPE_GTPU,
 192         RTE_FLOW_ITEM_TYPE_IPV4,
 193         RTE_FLOW_ITEM_TYPE_END,
 194 };
 195
 196 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 197         RTE_FLOW_ITEM_TYPE_ETH,
 198         RTE_FLOW_ITEM_TYPE_IPV4,
 199         RTE_FLOW_ITEM_TYPE_UDP,
 200         RTE_FLOW_ITEM_TYPE_GTPU,
 201         RTE_FLOW_ITEM_TYPE_IPV6,
 202         RTE_FLOW_ITEM_TYPE_END,
 203 };
 204
 205 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 206         RTE_FLOW_ITEM_TYPE_ETH,
 207         RTE_FLOW_ITEM_TYPE_IPV6,
 208         RTE_FLOW_ITEM_TYPE_END,
 209 };
 210
 211 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 212         RTE_FLOW_ITEM_TYPE_ETH,
 213         RTE_FLOW_ITEM_TYPE_IPV6,
 214         RTE_FLOW_ITEM_TYPE_UDP,
 215         RTE_FLOW_ITEM_TYPE_END,
 216 };
 217
 218 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 219         RTE_FLOW_ITEM_TYPE_ETH,
 220         RTE_FLOW_ITEM_TYPE_IPV6,
 221         RTE_FLOW_ITEM_TYPE_TCP,
 222         RTE_FLOW_ITEM_TYPE_END,
 223 };
 224
 225 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 226         RTE_FLOW_ITEM_TYPE_ETH,
 227         RTE_FLOW_ITEM_TYPE_IPV6,
 228         RTE_FLOW_ITEM_TYPE_SCTP,
 229         RTE_FLOW_ITEM_TYPE_END,
 230 };
 231
 232 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 233         RTE_FLOW_ITEM_TYPE_ETH,
 234         RTE_FLOW_ITEM_TYPE_IPV6,
 235         RTE_FLOW_ITEM_TYPE_UDP,
 236         RTE_FLOW_ITEM_TYPE_GTPC,
 237         RTE_FLOW_ITEM_TYPE_END,
 238 };
 239
 240 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 241         RTE_FLOW_ITEM_TYPE_ETH,
 242         RTE_FLOW_ITEM_TYPE_IPV6,
 243         RTE_FLOW_ITEM_TYPE_UDP,
 244         RTE_FLOW_ITEM_TYPE_GTPU,
 245         RTE_FLOW_ITEM_TYPE_END,
 246 };
 247
 248 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 249         RTE_FLOW_ITEM_TYPE_ETH,
 250         RTE_FLOW_ITEM_TYPE_IPV6,
 251         RTE_FLOW_ITEM_TYPE_UDP,
 252         RTE_FLOW_ITEM_TYPE_GTPU,
 253         RTE_FLOW_ITEM_TYPE_IPV4,
 254         RTE_FLOW_ITEM_TYPE_END,
 255 };
 256
 257 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 258         RTE_FLOW_ITEM_TYPE_ETH,
 259         RTE_FLOW_ITEM_TYPE_IPV6,
 260         RTE_FLOW_ITEM_TYPE_UDP,
 261         RTE_FLOW_ITEM_TYPE_GTPU,
 262         RTE_FLOW_ITEM_TYPE_IPV6,
 263         RTE_FLOW_ITEM_TYPE_END,
 264 };
 265
 266 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 267         RTE_FLOW_ITEM_TYPE_ETH,
 268         RTE_FLOW_ITEM_TYPE_RAW,
 269         RTE_FLOW_ITEM_TYPE_END,
 270 };
 271
 272 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 273         RTE_FLOW_ITEM_TYPE_ETH,
 274         RTE_FLOW_ITEM_TYPE_RAW,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_END,
 277 };
 278
 279 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 280         RTE_FLOW_ITEM_TYPE_ETH,
 281         RTE_FLOW_ITEM_TYPE_RAW,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_END,
 285 };
 286
 287 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 288         RTE_FLOW_ITEM_TYPE_ETH,
 289         RTE_FLOW_ITEM_TYPE_IPV4,
 290         RTE_FLOW_ITEM_TYPE_RAW,
 291         RTE_FLOW_ITEM_TYPE_END,
 292 };
 293
 294 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 295         RTE_FLOW_ITEM_TYPE_ETH,
 296         RTE_FLOW_ITEM_TYPE_IPV4,
 297         RTE_FLOW_ITEM_TYPE_RAW,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_END,
 300 };
 301
 302 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 303         RTE_FLOW_ITEM_TYPE_ETH,
 304         RTE_FLOW_ITEM_TYPE_IPV4,
 305         RTE_FLOW_ITEM_TYPE_RAW,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_END,
 309 };
 310
 311 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 312         RTE_FLOW_ITEM_TYPE_ETH,
 313         RTE_FLOW_ITEM_TYPE_IPV4,
 314         RTE_FLOW_ITEM_TYPE_UDP,
 315         RTE_FLOW_ITEM_TYPE_RAW,
 316         RTE_FLOW_ITEM_TYPE_END,
 317 };
 318
 319 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 320         RTE_FLOW_ITEM_TYPE_ETH,
 321         RTE_FLOW_ITEM_TYPE_IPV4,
 322         RTE_FLOW_ITEM_TYPE_UDP,
 323         RTE_FLOW_ITEM_TYPE_RAW,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_END,
 326 };
 327
 328 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 329         RTE_FLOW_ITEM_TYPE_ETH,
 330         RTE_FLOW_ITEM_TYPE_IPV4,
 331         RTE_FLOW_ITEM_TYPE_UDP,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_END,
 336 };
 337
 338 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 339         RTE_FLOW_ITEM_TYPE_ETH,
 340         RTE_FLOW_ITEM_TYPE_IPV4,
 341         RTE_FLOW_ITEM_TYPE_TCP,
 342         RTE_FLOW_ITEM_TYPE_RAW,
 343         RTE_FLOW_ITEM_TYPE_END,
 344 };
 345
 346 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 347         RTE_FLOW_ITEM_TYPE_ETH,
 348         RTE_FLOW_ITEM_TYPE_IPV4,
 349         RTE_FLOW_ITEM_TYPE_TCP,
 350         RTE_FLOW_ITEM_TYPE_RAW,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_END,
 353 };
 354
 355 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 356         RTE_FLOW_ITEM_TYPE_ETH,
 357         RTE_FLOW_ITEM_TYPE_IPV4,
 358         RTE_FLOW_ITEM_TYPE_TCP,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_END,
 363 };
 364
 365 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 366         RTE_FLOW_ITEM_TYPE_ETH,
 367         RTE_FLOW_ITEM_TYPE_IPV4,
 368         RTE_FLOW_ITEM_TYPE_SCTP,
 369         RTE_FLOW_ITEM_TYPE_RAW,
 370         RTE_FLOW_ITEM_TYPE_END,
 371 };
 372
 373 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 374         RTE_FLOW_ITEM_TYPE_ETH,
 375         RTE_FLOW_ITEM_TYPE_IPV4,
 376         RTE_FLOW_ITEM_TYPE_SCTP,
 377         RTE_FLOW_ITEM_TYPE_RAW,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_END,
 380 };
 381
 382 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 383         RTE_FLOW_ITEM_TYPE_ETH,
 384         RTE_FLOW_ITEM_TYPE_IPV4,
 385         RTE_FLOW_ITEM_TYPE_SCTP,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_END,
 390 };
 391
 392 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 393         RTE_FLOW_ITEM_TYPE_ETH,
 394         RTE_FLOW_ITEM_TYPE_IPV6,
 395         RTE_FLOW_ITEM_TYPE_RAW,
 396         RTE_FLOW_ITEM_TYPE_END,
 397 };
 398
 399 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 400         RTE_FLOW_ITEM_TYPE_ETH,
 401         RTE_FLOW_ITEM_TYPE_IPV6,
 402         RTE_FLOW_ITEM_TYPE_RAW,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_END,
 405 };
 406
 407 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 408         RTE_FLOW_ITEM_TYPE_ETH,
 409         RTE_FLOW_ITEM_TYPE_IPV6,
 410         RTE_FLOW_ITEM_TYPE_RAW,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_END,
 414 };
 415
 416 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 417         RTE_FLOW_ITEM_TYPE_ETH,
 418         RTE_FLOW_ITEM_TYPE_IPV6,
 419         RTE_FLOW_ITEM_TYPE_UDP,
 420         RTE_FLOW_ITEM_TYPE_RAW,
 421         RTE_FLOW_ITEM_TYPE_END,
 422 };
 423
 424 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 425         RTE_FLOW_ITEM_TYPE_ETH,
 426         RTE_FLOW_ITEM_TYPE_IPV6,
 427         RTE_FLOW_ITEM_TYPE_UDP,
 428         RTE_FLOW_ITEM_TYPE_RAW,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_END,
 431 };
 432
 433 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 434         RTE_FLOW_ITEM_TYPE_ETH,
 435         RTE_FLOW_ITEM_TYPE_IPV6,
 436         RTE_FLOW_ITEM_TYPE_UDP,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_END,
 441 };
 442
 443 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 444         RTE_FLOW_ITEM_TYPE_ETH,
 445         RTE_FLOW_ITEM_TYPE_IPV6,
 446         RTE_FLOW_ITEM_TYPE_TCP,
 447         RTE_FLOW_ITEM_TYPE_RAW,
 448         RTE_FLOW_ITEM_TYPE_END,
 449 };
 450
 451 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 452         RTE_FLOW_ITEM_TYPE_ETH,
 453         RTE_FLOW_ITEM_TYPE_IPV6,
 454         RTE_FLOW_ITEM_TYPE_TCP,
 455         RTE_FLOW_ITEM_TYPE_RAW,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_END,
 458 };
 459
 460 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 461         RTE_FLOW_ITEM_TYPE_ETH,
 462         RTE_FLOW_ITEM_TYPE_IPV6,
 463         RTE_FLOW_ITEM_TYPE_TCP,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_END,
 468 };
 469
 470 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 471         RTE_FLOW_ITEM_TYPE_ETH,
 472         RTE_FLOW_ITEM_TYPE_IPV6,
 473         RTE_FLOW_ITEM_TYPE_SCTP,
 474         RTE_FLOW_ITEM_TYPE_RAW,
 475         RTE_FLOW_ITEM_TYPE_END,
 476 };
 477
 478 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 479         RTE_FLOW_ITEM_TYPE_ETH,
 480         RTE_FLOW_ITEM_TYPE_IPV6,
 481         RTE_FLOW_ITEM_TYPE_SCTP,
 482         RTE_FLOW_ITEM_TYPE_RAW,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_END,
 485 };
 486
 487 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 488         RTE_FLOW_ITEM_TYPE_ETH,
 489         RTE_FLOW_ITEM_TYPE_IPV6,
 490         RTE_FLOW_ITEM_TYPE_SCTP,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_END,
 495 };
 496
 497 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 498         RTE_FLOW_ITEM_TYPE_ETH,
 499         RTE_FLOW_ITEM_TYPE_VLAN,
 500         RTE_FLOW_ITEM_TYPE_END,
 501 };
 502
 503 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 504         RTE_FLOW_ITEM_TYPE_ETH,
 505         RTE_FLOW_ITEM_TYPE_VLAN,
 506         RTE_FLOW_ITEM_TYPE_IPV4,
 507         RTE_FLOW_ITEM_TYPE_END,
 508 };
 509
 510 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 511         RTE_FLOW_ITEM_TYPE_ETH,
 512         RTE_FLOW_ITEM_TYPE_VLAN,
 513         RTE_FLOW_ITEM_TYPE_IPV4,
 514         RTE_FLOW_ITEM_TYPE_UDP,
 515         RTE_FLOW_ITEM_TYPE_END,
 516 };
 517
 518 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 519         RTE_FLOW_ITEM_TYPE_ETH,
 520         RTE_FLOW_ITEM_TYPE_VLAN,
 521         RTE_FLOW_ITEM_TYPE_IPV4,
 522         RTE_FLOW_ITEM_TYPE_TCP,
 523         RTE_FLOW_ITEM_TYPE_END,
 524 };
 525
 526 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 527         RTE_FLOW_ITEM_TYPE_ETH,
 528         RTE_FLOW_ITEM_TYPE_VLAN,
 529         RTE_FLOW_ITEM_TYPE_IPV4,
 530         RTE_FLOW_ITEM_TYPE_SCTP,
 531         RTE_FLOW_ITEM_TYPE_END,
 532 };
 533
 534 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 535         RTE_FLOW_ITEM_TYPE_ETH,
 536         RTE_FLOW_ITEM_TYPE_VLAN,
 537         RTE_FLOW_ITEM_TYPE_IPV6,
 538         RTE_FLOW_ITEM_TYPE_END,
 539 };
 540
 541 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 542         RTE_FLOW_ITEM_TYPE_ETH,
 543         RTE_FLOW_ITEM_TYPE_VLAN,
 544         RTE_FLOW_ITEM_TYPE_IPV6,
 545         RTE_FLOW_ITEM_TYPE_UDP,
 546         RTE_FLOW_ITEM_TYPE_END,
 547 };
 548
 549 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 550         RTE_FLOW_ITEM_TYPE_ETH,
 551         RTE_FLOW_ITEM_TYPE_VLAN,
 552         RTE_FLOW_ITEM_TYPE_IPV6,
 553         RTE_FLOW_ITEM_TYPE_TCP,
 554         RTE_FLOW_ITEM_TYPE_END,
 555 };
 556
 557 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 558         RTE_FLOW_ITEM_TYPE_ETH,
 559         RTE_FLOW_ITEM_TYPE_VLAN,
 560         RTE_FLOW_ITEM_TYPE_IPV6,
 561         RTE_FLOW_ITEM_TYPE_SCTP,
 562         RTE_FLOW_ITEM_TYPE_END,
 563 };
 564
 565 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 566         RTE_FLOW_ITEM_TYPE_ETH,
 567         RTE_FLOW_ITEM_TYPE_VLAN,
 568         RTE_FLOW_ITEM_TYPE_RAW,
 569         RTE_FLOW_ITEM_TYPE_END,
 570 };
 571
 572 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 573         RTE_FLOW_ITEM_TYPE_ETH,
 574         RTE_FLOW_ITEM_TYPE_VLAN,
 575         RTE_FLOW_ITEM_TYPE_RAW,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_END,
 578 };
 579
 580 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 581         RTE_FLOW_ITEM_TYPE_ETH,
 582         RTE_FLOW_ITEM_TYPE_VLAN,
 583         RTE_FLOW_ITEM_TYPE_RAW,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_END,
 587 };
 588
 589 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 590         RTE_FLOW_ITEM_TYPE_ETH,
 591         RTE_FLOW_ITEM_TYPE_VLAN,
 592         RTE_FLOW_ITEM_TYPE_IPV4,
 593         RTE_FLOW_ITEM_TYPE_RAW,
 594         RTE_FLOW_ITEM_TYPE_END,
 595 };
 596
 597 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 598         RTE_FLOW_ITEM_TYPE_ETH,
 599         RTE_FLOW_ITEM_TYPE_VLAN,
 600         RTE_FLOW_ITEM_TYPE_IPV4,
 601         RTE_FLOW_ITEM_TYPE_RAW,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_END,
 604 };
 605
 606 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 607         RTE_FLOW_ITEM_TYPE_ETH,
 608         RTE_FLOW_ITEM_TYPE_VLAN,
 609         RTE_FLOW_ITEM_TYPE_IPV4,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_END,
 614 };
 615
 616 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 617         RTE_FLOW_ITEM_TYPE_ETH,
 618         RTE_FLOW_ITEM_TYPE_VLAN,
 619         RTE_FLOW_ITEM_TYPE_IPV4,
 620         RTE_FLOW_ITEM_TYPE_UDP,
 621         RTE_FLOW_ITEM_TYPE_RAW,
 622         RTE_FLOW_ITEM_TYPE_END,
 623 };
 624
 625 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 626         RTE_FLOW_ITEM_TYPE_ETH,
 627         RTE_FLOW_ITEM_TYPE_VLAN,
 628         RTE_FLOW_ITEM_TYPE_IPV4,
 629         RTE_FLOW_ITEM_TYPE_UDP,
 630         RTE_FLOW_ITEM_TYPE_RAW,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_END,
 633 };
 634
 635 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 636         RTE_FLOW_ITEM_TYPE_ETH,
 637         RTE_FLOW_ITEM_TYPE_VLAN,
 638         RTE_FLOW_ITEM_TYPE_IPV4,
 639         RTE_FLOW_ITEM_TYPE_UDP,
 640         RTE_FLOW_ITEM_TYPE_RAW,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_END,
 644 };
 645
 646 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 647         RTE_FLOW_ITEM_TYPE_ETH,
 648         RTE_FLOW_ITEM_TYPE_VLAN,
 649         RTE_FLOW_ITEM_TYPE_IPV4,
 650         RTE_FLOW_ITEM_TYPE_TCP,
 651         RTE_FLOW_ITEM_TYPE_RAW,
 652         RTE_FLOW_ITEM_TYPE_END,
 653 };
 654
 655 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 656         RTE_FLOW_ITEM_TYPE_ETH,
 657         RTE_FLOW_ITEM_TYPE_VLAN,
 658         RTE_FLOW_ITEM_TYPE_IPV4,
 659         RTE_FLOW_ITEM_TYPE_TCP,
 660         RTE_FLOW_ITEM_TYPE_RAW,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_END,
 663 };
 664
 665 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 666         RTE_FLOW_ITEM_TYPE_ETH,
 667         RTE_FLOW_ITEM_TYPE_VLAN,
 668         RTE_FLOW_ITEM_TYPE_IPV4,
 669         RTE_FLOW_ITEM_TYPE_TCP,
 670         RTE_FLOW_ITEM_TYPE_RAW,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_END,
 674 };
 675
 676 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 677         RTE_FLOW_ITEM_TYPE_ETH,
 678         RTE_FLOW_ITEM_TYPE_VLAN,
 679         RTE_FLOW_ITEM_TYPE_IPV4,
 680         RTE_FLOW_ITEM_TYPE_SCTP,
 681         RTE_FLOW_ITEM_TYPE_RAW,
 682         RTE_FLOW_ITEM_TYPE_END,
 683 };
 684
 685 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 686         RTE_FLOW_ITEM_TYPE_ETH,
 687         RTE_FLOW_ITEM_TYPE_VLAN,
 688         RTE_FLOW_ITEM_TYPE_IPV4,
 689         RTE_FLOW_ITEM_TYPE_SCTP,
 690         RTE_FLOW_ITEM_TYPE_RAW,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_END,
 693 };
 694
 695 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 696         RTE_FLOW_ITEM_TYPE_ETH,
 697         RTE_FLOW_ITEM_TYPE_VLAN,
 698         RTE_FLOW_ITEM_TYPE_IPV4,
 699         RTE_FLOW_ITEM_TYPE_SCTP,
 700         RTE_FLOW_ITEM_TYPE_RAW,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_END,
 704 };
 705
 706 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 707         RTE_FLOW_ITEM_TYPE_ETH,
 708         RTE_FLOW_ITEM_TYPE_VLAN,
 709         RTE_FLOW_ITEM_TYPE_IPV6,
 710         RTE_FLOW_ITEM_TYPE_RAW,
 711         RTE_FLOW_ITEM_TYPE_END,
 712 };
 713
 714 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 715         RTE_FLOW_ITEM_TYPE_ETH,
 716         RTE_FLOW_ITEM_TYPE_VLAN,
 717         RTE_FLOW_ITEM_TYPE_IPV6,
 718         RTE_FLOW_ITEM_TYPE_RAW,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_END,
 721 };
 722
 723 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 724         RTE_FLOW_ITEM_TYPE_ETH,
 725         RTE_FLOW_ITEM_TYPE_VLAN,
 726         RTE_FLOW_ITEM_TYPE_IPV6,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_END,
 731 };
 732
 733 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 734         RTE_FLOW_ITEM_TYPE_ETH,
 735         RTE_FLOW_ITEM_TYPE_VLAN,
 736         RTE_FLOW_ITEM_TYPE_IPV6,
 737         RTE_FLOW_ITEM_TYPE_UDP,
 738         RTE_FLOW_ITEM_TYPE_RAW,
 739         RTE_FLOW_ITEM_TYPE_END,
 740 };
 741
 742 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 743         RTE_FLOW_ITEM_TYPE_ETH,
 744         RTE_FLOW_ITEM_TYPE_VLAN,
 745         RTE_FLOW_ITEM_TYPE_IPV6,
 746         RTE_FLOW_ITEM_TYPE_UDP,
 747         RTE_FLOW_ITEM_TYPE_RAW,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_END,
 750 };
 751
 752 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 753         RTE_FLOW_ITEM_TYPE_ETH,
 754         RTE_FLOW_ITEM_TYPE_VLAN,
 755         RTE_FLOW_ITEM_TYPE_IPV6,
 756         RTE_FLOW_ITEM_TYPE_UDP,
 757         RTE_FLOW_ITEM_TYPE_RAW,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_END,
 761 };
 762
 763 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 764         RTE_FLOW_ITEM_TYPE_ETH,
 765         RTE_FLOW_ITEM_TYPE_VLAN,
 766         RTE_FLOW_ITEM_TYPE_IPV6,
 767         RTE_FLOW_ITEM_TYPE_TCP,
 768         RTE_FLOW_ITEM_TYPE_RAW,
 769         RTE_FLOW_ITEM_TYPE_END,
 770 };
 771
 772 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 773         RTE_FLOW_ITEM_TYPE_ETH,
 774         RTE_FLOW_ITEM_TYPE_VLAN,
 775         RTE_FLOW_ITEM_TYPE_IPV6,
 776         RTE_FLOW_ITEM_TYPE_TCP,
 777         RTE_FLOW_ITEM_TYPE_RAW,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_END,
 780 };
 781
 782 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 783         RTE_FLOW_ITEM_TYPE_ETH,
 784         RTE_FLOW_ITEM_TYPE_VLAN,
 785         RTE_FLOW_ITEM_TYPE_IPV6,
 786         RTE_FLOW_ITEM_TYPE_TCP,
 787         RTE_FLOW_ITEM_TYPE_RAW,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_END,
 791 };
 792
 793 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 794         RTE_FLOW_ITEM_TYPE_ETH,
 795         RTE_FLOW_ITEM_TYPE_VLAN,
 796         RTE_FLOW_ITEM_TYPE_IPV6,
 797         RTE_FLOW_ITEM_TYPE_SCTP,
 798         RTE_FLOW_ITEM_TYPE_RAW,
 799         RTE_FLOW_ITEM_TYPE_END,
 800 };
 801
 802 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 803         RTE_FLOW_ITEM_TYPE_ETH,
 804         RTE_FLOW_ITEM_TYPE_VLAN,
 805         RTE_FLOW_ITEM_TYPE_IPV6,
 806         RTE_FLOW_ITEM_TYPE_SCTP,
 807         RTE_FLOW_ITEM_TYPE_RAW,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_END,
 810 };
 811
 812 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 813         RTE_FLOW_ITEM_TYPE_ETH,
 814         RTE_FLOW_ITEM_TYPE_VLAN,
 815         RTE_FLOW_ITEM_TYPE_IPV6,
 816         RTE_FLOW_ITEM_TYPE_SCTP,
 817         RTE_FLOW_ITEM_TYPE_RAW,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_END,
 821 };
 822
 823 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 824         RTE_FLOW_ITEM_TYPE_ETH,
 825         RTE_FLOW_ITEM_TYPE_IPV4,
 826         RTE_FLOW_ITEM_TYPE_VF,
 827         RTE_FLOW_ITEM_TYPE_END,
 828 };
 829
 830 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 831         RTE_FLOW_ITEM_TYPE_ETH,
 832         RTE_FLOW_ITEM_TYPE_IPV4,
 833         RTE_FLOW_ITEM_TYPE_UDP,
 834         RTE_FLOW_ITEM_TYPE_VF,
 835         RTE_FLOW_ITEM_TYPE_END,
 836 };
 837
 838 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 839         RTE_FLOW_ITEM_TYPE_ETH,
 840         RTE_FLOW_ITEM_TYPE_IPV4,
 841         RTE_FLOW_ITEM_TYPE_TCP,
 842         RTE_FLOW_ITEM_TYPE_VF,
 843         RTE_FLOW_ITEM_TYPE_END,
 844 };
 845
 846 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 847         RTE_FLOW_ITEM_TYPE_ETH,
 848         RTE_FLOW_ITEM_TYPE_IPV4,
 849         RTE_FLOW_ITEM_TYPE_SCTP,
 850         RTE_FLOW_ITEM_TYPE_VF,
 851         RTE_FLOW_ITEM_TYPE_END,
 852 };
 853
 854 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 855         RTE_FLOW_ITEM_TYPE_ETH,
 856         RTE_FLOW_ITEM_TYPE_IPV6,
 857         RTE_FLOW_ITEM_TYPE_VF,
 858         RTE_FLOW_ITEM_TYPE_END,
 859 };
 860
 861 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 862         RTE_FLOW_ITEM_TYPE_ETH,
 863         RTE_FLOW_ITEM_TYPE_IPV6,
 864         RTE_FLOW_ITEM_TYPE_UDP,
 865         RTE_FLOW_ITEM_TYPE_VF,
 866         RTE_FLOW_ITEM_TYPE_END,
 867 };
 868
 869 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 870         RTE_FLOW_ITEM_TYPE_ETH,
 871         RTE_FLOW_ITEM_TYPE_IPV6,
 872         RTE_FLOW_ITEM_TYPE_TCP,
 873         RTE_FLOW_ITEM_TYPE_VF,
 874         RTE_FLOW_ITEM_TYPE_END,
 875 };
 876
 877 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 878         RTE_FLOW_ITEM_TYPE_ETH,
 879         RTE_FLOW_ITEM_TYPE_IPV6,
 880         RTE_FLOW_ITEM_TYPE_SCTP,
 881         RTE_FLOW_ITEM_TYPE_VF,
 882         RTE_FLOW_ITEM_TYPE_END,
 883 };
 884
 885 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 886         RTE_FLOW_ITEM_TYPE_ETH,
 887         RTE_FLOW_ITEM_TYPE_RAW,
 888         RTE_FLOW_ITEM_TYPE_VF,
 889         RTE_FLOW_ITEM_TYPE_END,
 890 };
 891
 892 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 893         RTE_FLOW_ITEM_TYPE_ETH,
 894         RTE_FLOW_ITEM_TYPE_RAW,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_VF,
 897         RTE_FLOW_ITEM_TYPE_END,
 898 };
 899
 900 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 901         RTE_FLOW_ITEM_TYPE_ETH,
 902         RTE_FLOW_ITEM_TYPE_RAW,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_VF,
 906         RTE_FLOW_ITEM_TYPE_END,
 907 };
 908
 909 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 910         RTE_FLOW_ITEM_TYPE_ETH,
 911         RTE_FLOW_ITEM_TYPE_IPV4,
 912         RTE_FLOW_ITEM_TYPE_RAW,
 913         RTE_FLOW_ITEM_TYPE_VF,
 914         RTE_FLOW_ITEM_TYPE_END,
 915 };
 916
 917 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 918         RTE_FLOW_ITEM_TYPE_ETH,
 919         RTE_FLOW_ITEM_TYPE_IPV4,
 920         RTE_FLOW_ITEM_TYPE_RAW,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_VF,
 923         RTE_FLOW_ITEM_TYPE_END,
 924 };
 925
 926 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 927         RTE_FLOW_ITEM_TYPE_ETH,
 928         RTE_FLOW_ITEM_TYPE_IPV4,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_VF,
 933         RTE_FLOW_ITEM_TYPE_END,
 934 };
 935
 936 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 937         RTE_FLOW_ITEM_TYPE_ETH,
 938         RTE_FLOW_ITEM_TYPE_IPV4,
 939         RTE_FLOW_ITEM_TYPE_UDP,
 940         RTE_FLOW_ITEM_TYPE_RAW,
 941         RTE_FLOW_ITEM_TYPE_VF,
 942         RTE_FLOW_ITEM_TYPE_END,
 943 };
 944
 945 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 946         RTE_FLOW_ITEM_TYPE_ETH,
 947         RTE_FLOW_ITEM_TYPE_IPV4,
 948         RTE_FLOW_ITEM_TYPE_UDP,
 949         RTE_FLOW_ITEM_TYPE_RAW,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_VF,
 952         RTE_FLOW_ITEM_TYPE_END,
 953 };
 954
 955 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 956         RTE_FLOW_ITEM_TYPE_ETH,
 957         RTE_FLOW_ITEM_TYPE_IPV4,
 958         RTE_FLOW_ITEM_TYPE_UDP,
 959         RTE_FLOW_ITEM_TYPE_RAW,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_VF,
 963         RTE_FLOW_ITEM_TYPE_END,
 964 };
 965
 966 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 967         RTE_FLOW_ITEM_TYPE_ETH,
 968         RTE_FLOW_ITEM_TYPE_IPV4,
 969         RTE_FLOW_ITEM_TYPE_TCP,
 970         RTE_FLOW_ITEM_TYPE_RAW,
 971         RTE_FLOW_ITEM_TYPE_VF,
 972         RTE_FLOW_ITEM_TYPE_END,
 973 };
 974
 975 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 976         RTE_FLOW_ITEM_TYPE_ETH,
 977         RTE_FLOW_ITEM_TYPE_IPV4,
 978         RTE_FLOW_ITEM_TYPE_TCP,
 979         RTE_FLOW_ITEM_TYPE_RAW,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_VF,
 982         RTE_FLOW_ITEM_TYPE_END,
 983 };
 984
 985 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 986         RTE_FLOW_ITEM_TYPE_ETH,
 987         RTE_FLOW_ITEM_TYPE_IPV4,
 988         RTE_FLOW_ITEM_TYPE_TCP,
 989         RTE_FLOW_ITEM_TYPE_RAW,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_VF,
 993         RTE_FLOW_ITEM_TYPE_END,
 994 };
 995
 996 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 997         RTE_FLOW_ITEM_TYPE_ETH,
 998         RTE_FLOW_ITEM_TYPE_IPV4,
 999         RTE_FLOW_ITEM_TYPE_SCTP,
1000         RTE_FLOW_ITEM_TYPE_RAW,
1001         RTE_FLOW_ITEM_TYPE_VF,
1002         RTE_FLOW_ITEM_TYPE_END,
1003 };
1004
1005 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1006         RTE_FLOW_ITEM_TYPE_ETH,
1007         RTE_FLOW_ITEM_TYPE_IPV4,
1008         RTE_FLOW_ITEM_TYPE_SCTP,
1009         RTE_FLOW_ITEM_TYPE_RAW,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_VF,
1012         RTE_FLOW_ITEM_TYPE_END,
1013 };
1014
1015 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1016         RTE_FLOW_ITEM_TYPE_ETH,
1017         RTE_FLOW_ITEM_TYPE_IPV4,
1018         RTE_FLOW_ITEM_TYPE_SCTP,
1019         RTE_FLOW_ITEM_TYPE_RAW,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_VF,
1023         RTE_FLOW_ITEM_TYPE_END,
1024 };
1025
1026 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1027         RTE_FLOW_ITEM_TYPE_ETH,
1028         RTE_FLOW_ITEM_TYPE_IPV6,
1029         RTE_FLOW_ITEM_TYPE_RAW,
1030         RTE_FLOW_ITEM_TYPE_VF,
1031         RTE_FLOW_ITEM_TYPE_END,
1032 };
1033
1034 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1035         RTE_FLOW_ITEM_TYPE_ETH,
1036         RTE_FLOW_ITEM_TYPE_IPV6,
1037         RTE_FLOW_ITEM_TYPE_RAW,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_VF,
1040         RTE_FLOW_ITEM_TYPE_END,
1041 };
1042
1043 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1044         RTE_FLOW_ITEM_TYPE_ETH,
1045         RTE_FLOW_ITEM_TYPE_IPV6,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_VF,
1050         RTE_FLOW_ITEM_TYPE_END,
1051 };
1052
1053 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1054         RTE_FLOW_ITEM_TYPE_ETH,
1055         RTE_FLOW_ITEM_TYPE_IPV6,
1056         RTE_FLOW_ITEM_TYPE_UDP,
1057         RTE_FLOW_ITEM_TYPE_RAW,
1058         RTE_FLOW_ITEM_TYPE_VF,
1059         RTE_FLOW_ITEM_TYPE_END,
1060 };
1061
1062 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1063         RTE_FLOW_ITEM_TYPE_ETH,
1064         RTE_FLOW_ITEM_TYPE_IPV6,
1065         RTE_FLOW_ITEM_TYPE_UDP,
1066         RTE_FLOW_ITEM_TYPE_RAW,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_VF,
1069         RTE_FLOW_ITEM_TYPE_END,
1070 };
1071
1072 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1073         RTE_FLOW_ITEM_TYPE_ETH,
1074         RTE_FLOW_ITEM_TYPE_IPV6,
1075         RTE_FLOW_ITEM_TYPE_UDP,
1076         RTE_FLOW_ITEM_TYPE_RAW,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_VF,
1080         RTE_FLOW_ITEM_TYPE_END,
1081 };
1082
1083 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1084         RTE_FLOW_ITEM_TYPE_ETH,
1085         RTE_FLOW_ITEM_TYPE_IPV6,
1086         RTE_FLOW_ITEM_TYPE_TCP,
1087         RTE_FLOW_ITEM_TYPE_RAW,
1088         RTE_FLOW_ITEM_TYPE_VF,
1089         RTE_FLOW_ITEM_TYPE_END,
1090 };
1091
1092 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1093         RTE_FLOW_ITEM_TYPE_ETH,
1094         RTE_FLOW_ITEM_TYPE_IPV6,
1095         RTE_FLOW_ITEM_TYPE_TCP,
1096         RTE_FLOW_ITEM_TYPE_RAW,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_VF,
1099         RTE_FLOW_ITEM_TYPE_END,
1100 };
1101
1102 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1103         RTE_FLOW_ITEM_TYPE_ETH,
1104         RTE_FLOW_ITEM_TYPE_IPV6,
1105         RTE_FLOW_ITEM_TYPE_TCP,
1106         RTE_FLOW_ITEM_TYPE_RAW,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_VF,
1110         RTE_FLOW_ITEM_TYPE_END,
1111 };
1112
1113 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1114         RTE_FLOW_ITEM_TYPE_ETH,
1115         RTE_FLOW_ITEM_TYPE_IPV6,
1116         RTE_FLOW_ITEM_TYPE_SCTP,
1117         RTE_FLOW_ITEM_TYPE_RAW,
1118         RTE_FLOW_ITEM_TYPE_VF,
1119         RTE_FLOW_ITEM_TYPE_END,
1120 };
1121
1122 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1123         RTE_FLOW_ITEM_TYPE_ETH,
1124         RTE_FLOW_ITEM_TYPE_IPV6,
1125         RTE_FLOW_ITEM_TYPE_SCTP,
1126         RTE_FLOW_ITEM_TYPE_RAW,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_VF,
1129         RTE_FLOW_ITEM_TYPE_END,
1130 };
1131
1132 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1133         RTE_FLOW_ITEM_TYPE_ETH,
1134         RTE_FLOW_ITEM_TYPE_IPV6,
1135         RTE_FLOW_ITEM_TYPE_SCTP,
1136         RTE_FLOW_ITEM_TYPE_RAW,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_VF,
1140         RTE_FLOW_ITEM_TYPE_END,
1141 };
1142
1143 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1144         RTE_FLOW_ITEM_TYPE_ETH,
1145         RTE_FLOW_ITEM_TYPE_VLAN,
1146         RTE_FLOW_ITEM_TYPE_VF,
1147         RTE_FLOW_ITEM_TYPE_END,
1148 };
1149
1150 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1151         RTE_FLOW_ITEM_TYPE_ETH,
1152         RTE_FLOW_ITEM_TYPE_VLAN,
1153         RTE_FLOW_ITEM_TYPE_IPV4,
1154         RTE_FLOW_ITEM_TYPE_VF,
1155         RTE_FLOW_ITEM_TYPE_END,
1156 };
1157
1158 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1159         RTE_FLOW_ITEM_TYPE_ETH,
1160         RTE_FLOW_ITEM_TYPE_VLAN,
1161         RTE_FLOW_ITEM_TYPE_IPV4,
1162         RTE_FLOW_ITEM_TYPE_UDP,
1163         RTE_FLOW_ITEM_TYPE_VF,
1164         RTE_FLOW_ITEM_TYPE_END,
1165 };
1166
1167 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1168         RTE_FLOW_ITEM_TYPE_ETH,
1169         RTE_FLOW_ITEM_TYPE_VLAN,
1170         RTE_FLOW_ITEM_TYPE_IPV4,
1171         RTE_FLOW_ITEM_TYPE_TCP,
1172         RTE_FLOW_ITEM_TYPE_VF,
1173         RTE_FLOW_ITEM_TYPE_END,
1174 };
1175
1176 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1177         RTE_FLOW_ITEM_TYPE_ETH,
1178         RTE_FLOW_ITEM_TYPE_VLAN,
1179         RTE_FLOW_ITEM_TYPE_IPV4,
1180         RTE_FLOW_ITEM_TYPE_SCTP,
1181         RTE_FLOW_ITEM_TYPE_VF,
1182         RTE_FLOW_ITEM_TYPE_END,
1183 };
1184
1185 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1186         RTE_FLOW_ITEM_TYPE_ETH,
1187         RTE_FLOW_ITEM_TYPE_VLAN,
1188         RTE_FLOW_ITEM_TYPE_IPV6,
1189         RTE_FLOW_ITEM_TYPE_VF,
1190         RTE_FLOW_ITEM_TYPE_END,
1191 };
1192
1193 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1194         RTE_FLOW_ITEM_TYPE_ETH,
1195         RTE_FLOW_ITEM_TYPE_VLAN,
1196         RTE_FLOW_ITEM_TYPE_IPV6,
1197         RTE_FLOW_ITEM_TYPE_UDP,
1198         RTE_FLOW_ITEM_TYPE_VF,
1199         RTE_FLOW_ITEM_TYPE_END,
1200 };
1201
1202 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1203         RTE_FLOW_ITEM_TYPE_ETH,
1204         RTE_FLOW_ITEM_TYPE_VLAN,
1205         RTE_FLOW_ITEM_TYPE_IPV6,
1206         RTE_FLOW_ITEM_TYPE_TCP,
1207         RTE_FLOW_ITEM_TYPE_VF,
1208         RTE_FLOW_ITEM_TYPE_END,
1209 };
1210
1211 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1212         RTE_FLOW_ITEM_TYPE_ETH,
1213         RTE_FLOW_ITEM_TYPE_VLAN,
1214         RTE_FLOW_ITEM_TYPE_IPV6,
1215         RTE_FLOW_ITEM_TYPE_SCTP,
1216         RTE_FLOW_ITEM_TYPE_VF,
1217         RTE_FLOW_ITEM_TYPE_END,
1218 };
1219
1220 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1221         RTE_FLOW_ITEM_TYPE_ETH,
1222         RTE_FLOW_ITEM_TYPE_VLAN,
1223         RTE_FLOW_ITEM_TYPE_RAW,
1224         RTE_FLOW_ITEM_TYPE_VF,
1225         RTE_FLOW_ITEM_TYPE_END,
1226 };
1227
1228 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1229         RTE_FLOW_ITEM_TYPE_ETH,
1230         RTE_FLOW_ITEM_TYPE_VLAN,
1231         RTE_FLOW_ITEM_TYPE_RAW,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_VF,
1234         RTE_FLOW_ITEM_TYPE_END,
1235 };
1236
1237 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1238         RTE_FLOW_ITEM_TYPE_ETH,
1239         RTE_FLOW_ITEM_TYPE_VLAN,
1240         RTE_FLOW_ITEM_TYPE_RAW,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_VF,
1244         RTE_FLOW_ITEM_TYPE_END,
1245 };
1246
1247 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1248         RTE_FLOW_ITEM_TYPE_ETH,
1249         RTE_FLOW_ITEM_TYPE_VLAN,
1250         RTE_FLOW_ITEM_TYPE_IPV4,
1251         RTE_FLOW_ITEM_TYPE_RAW,
1252         RTE_FLOW_ITEM_TYPE_VF,
1253         RTE_FLOW_ITEM_TYPE_END,
1254 };
1255
1256 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1257         RTE_FLOW_ITEM_TYPE_ETH,
1258         RTE_FLOW_ITEM_TYPE_VLAN,
1259         RTE_FLOW_ITEM_TYPE_IPV4,
1260         RTE_FLOW_ITEM_TYPE_RAW,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_VF,
1263         RTE_FLOW_ITEM_TYPE_END,
1264 };
1265
1266 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1267         RTE_FLOW_ITEM_TYPE_ETH,
1268         RTE_FLOW_ITEM_TYPE_VLAN,
1269         RTE_FLOW_ITEM_TYPE_IPV4,
1270         RTE_FLOW_ITEM_TYPE_RAW,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_VF,
1274         RTE_FLOW_ITEM_TYPE_END,
1275 };
1276
1277 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1278         RTE_FLOW_ITEM_TYPE_ETH,
1279         RTE_FLOW_ITEM_TYPE_VLAN,
1280         RTE_FLOW_ITEM_TYPE_IPV4,
1281         RTE_FLOW_ITEM_TYPE_UDP,
1282         RTE_FLOW_ITEM_TYPE_RAW,
1283         RTE_FLOW_ITEM_TYPE_VF,
1284         RTE_FLOW_ITEM_TYPE_END,
1285 };
1286
1287 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1288         RTE_FLOW_ITEM_TYPE_ETH,
1289         RTE_FLOW_ITEM_TYPE_VLAN,
1290         RTE_FLOW_ITEM_TYPE_IPV4,
1291         RTE_FLOW_ITEM_TYPE_UDP,
1292         RTE_FLOW_ITEM_TYPE_RAW,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_VF,
1295         RTE_FLOW_ITEM_TYPE_END,
1296 };
1297
1298 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1299         RTE_FLOW_ITEM_TYPE_ETH,
1300         RTE_FLOW_ITEM_TYPE_VLAN,
1301         RTE_FLOW_ITEM_TYPE_IPV4,
1302         RTE_FLOW_ITEM_TYPE_UDP,
1303         RTE_FLOW_ITEM_TYPE_RAW,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_VF,
1307         RTE_FLOW_ITEM_TYPE_END,
1308 };
1309
1310 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1311         RTE_FLOW_ITEM_TYPE_ETH,
1312         RTE_FLOW_ITEM_TYPE_VLAN,
1313         RTE_FLOW_ITEM_TYPE_IPV4,
1314         RTE_FLOW_ITEM_TYPE_TCP,
1315         RTE_FLOW_ITEM_TYPE_RAW,
1316         RTE_FLOW_ITEM_TYPE_VF,
1317         RTE_FLOW_ITEM_TYPE_END,
1318 };
1319
1320 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1321         RTE_FLOW_ITEM_TYPE_ETH,
1322         RTE_FLOW_ITEM_TYPE_VLAN,
1323         RTE_FLOW_ITEM_TYPE_IPV4,
1324         RTE_FLOW_ITEM_TYPE_TCP,
1325         RTE_FLOW_ITEM_TYPE_RAW,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_VF,
1328         RTE_FLOW_ITEM_TYPE_END,
1329 };
1330
1331 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1332         RTE_FLOW_ITEM_TYPE_ETH,
1333         RTE_FLOW_ITEM_TYPE_VLAN,
1334         RTE_FLOW_ITEM_TYPE_IPV4,
1335         RTE_FLOW_ITEM_TYPE_TCP,
1336         RTE_FLOW_ITEM_TYPE_RAW,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_VF,
1340         RTE_FLOW_ITEM_TYPE_END,
1341 };
1342
1343 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1344         RTE_FLOW_ITEM_TYPE_ETH,
1345         RTE_FLOW_ITEM_TYPE_VLAN,
1346         RTE_FLOW_ITEM_TYPE_IPV4,
1347         RTE_FLOW_ITEM_TYPE_SCTP,
1348         RTE_FLOW_ITEM_TYPE_RAW,
1349         RTE_FLOW_ITEM_TYPE_VF,
1350         RTE_FLOW_ITEM_TYPE_END,
1351 };
1352
1353 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1354         RTE_FLOW_ITEM_TYPE_ETH,
1355         RTE_FLOW_ITEM_TYPE_VLAN,
1356         RTE_FLOW_ITEM_TYPE_IPV4,
1357         RTE_FLOW_ITEM_TYPE_SCTP,
1358         RTE_FLOW_ITEM_TYPE_RAW,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_VF,
1361         RTE_FLOW_ITEM_TYPE_END,
1362 };
1363
1364 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1365         RTE_FLOW_ITEM_TYPE_ETH,
1366         RTE_FLOW_ITEM_TYPE_VLAN,
1367         RTE_FLOW_ITEM_TYPE_IPV4,
1368         RTE_FLOW_ITEM_TYPE_SCTP,
1369         RTE_FLOW_ITEM_TYPE_RAW,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_VF,
1373         RTE_FLOW_ITEM_TYPE_END,
1374 };
1375
1376 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1377         RTE_FLOW_ITEM_TYPE_ETH,
1378         RTE_FLOW_ITEM_TYPE_VLAN,
1379         RTE_FLOW_ITEM_TYPE_IPV6,
1380         RTE_FLOW_ITEM_TYPE_RAW,
1381         RTE_FLOW_ITEM_TYPE_VF,
1382         RTE_FLOW_ITEM_TYPE_END,
1383 };
1384
1385 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1386         RTE_FLOW_ITEM_TYPE_ETH,
1387         RTE_FLOW_ITEM_TYPE_VLAN,
1388         RTE_FLOW_ITEM_TYPE_IPV6,
1389         RTE_FLOW_ITEM_TYPE_RAW,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_VF,
1392         RTE_FLOW_ITEM_TYPE_END,
1393 };
1394
1395 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1396         RTE_FLOW_ITEM_TYPE_ETH,
1397         RTE_FLOW_ITEM_TYPE_VLAN,
1398         RTE_FLOW_ITEM_TYPE_IPV6,
1399         RTE_FLOW_ITEM_TYPE_RAW,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_VF,
1403         RTE_FLOW_ITEM_TYPE_END,
1404 };
1405
1406 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1407         RTE_FLOW_ITEM_TYPE_ETH,
1408         RTE_FLOW_ITEM_TYPE_VLAN,
1409         RTE_FLOW_ITEM_TYPE_IPV6,
1410         RTE_FLOW_ITEM_TYPE_UDP,
1411         RTE_FLOW_ITEM_TYPE_RAW,
1412         RTE_FLOW_ITEM_TYPE_VF,
1413         RTE_FLOW_ITEM_TYPE_END,
1414 };
1415
1416 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1417         RTE_FLOW_ITEM_TYPE_ETH,
1418         RTE_FLOW_ITEM_TYPE_VLAN,
1419         RTE_FLOW_ITEM_TYPE_IPV6,
1420         RTE_FLOW_ITEM_TYPE_UDP,
1421         RTE_FLOW_ITEM_TYPE_RAW,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_VF,
1424         RTE_FLOW_ITEM_TYPE_END,
1425 };
1426
1427 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1428         RTE_FLOW_ITEM_TYPE_ETH,
1429         RTE_FLOW_ITEM_TYPE_VLAN,
1430         RTE_FLOW_ITEM_TYPE_IPV6,
1431         RTE_FLOW_ITEM_TYPE_UDP,
1432         RTE_FLOW_ITEM_TYPE_RAW,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_VF,
1436         RTE_FLOW_ITEM_TYPE_END,
1437 };
1438
1439 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1440         RTE_FLOW_ITEM_TYPE_ETH,
1441         RTE_FLOW_ITEM_TYPE_VLAN,
1442         RTE_FLOW_ITEM_TYPE_IPV6,
1443         RTE_FLOW_ITEM_TYPE_TCP,
1444         RTE_FLOW_ITEM_TYPE_RAW,
1445         RTE_FLOW_ITEM_TYPE_VF,
1446         RTE_FLOW_ITEM_TYPE_END,
1447 };
1448
1449 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1450         RTE_FLOW_ITEM_TYPE_ETH,
1451         RTE_FLOW_ITEM_TYPE_VLAN,
1452         RTE_FLOW_ITEM_TYPE_IPV6,
1453         RTE_FLOW_ITEM_TYPE_TCP,
1454         RTE_FLOW_ITEM_TYPE_RAW,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_VF,
1457         RTE_FLOW_ITEM_TYPE_END,
1458 };
1459
1460 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1461         RTE_FLOW_ITEM_TYPE_ETH,
1462         RTE_FLOW_ITEM_TYPE_VLAN,
1463         RTE_FLOW_ITEM_TYPE_IPV6,
1464         RTE_FLOW_ITEM_TYPE_TCP,
1465         RTE_FLOW_ITEM_TYPE_RAW,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_VF,
1469         RTE_FLOW_ITEM_TYPE_END,
1470 };
1471
1472 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1473         RTE_FLOW_ITEM_TYPE_ETH,
1474         RTE_FLOW_ITEM_TYPE_VLAN,
1475         RTE_FLOW_ITEM_TYPE_IPV6,
1476         RTE_FLOW_ITEM_TYPE_SCTP,
1477         RTE_FLOW_ITEM_TYPE_RAW,
1478         RTE_FLOW_ITEM_TYPE_VF,
1479         RTE_FLOW_ITEM_TYPE_END,
1480 };
1481
1482 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1483         RTE_FLOW_ITEM_TYPE_ETH,
1484         RTE_FLOW_ITEM_TYPE_VLAN,
1485         RTE_FLOW_ITEM_TYPE_IPV6,
1486         RTE_FLOW_ITEM_TYPE_SCTP,
1487         RTE_FLOW_ITEM_TYPE_RAW,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_VF,
1490         RTE_FLOW_ITEM_TYPE_END,
1491 };
1492
1493 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1494         RTE_FLOW_ITEM_TYPE_ETH,
1495         RTE_FLOW_ITEM_TYPE_VLAN,
1496         RTE_FLOW_ITEM_TYPE_IPV6,
1497         RTE_FLOW_ITEM_TYPE_SCTP,
1498         RTE_FLOW_ITEM_TYPE_RAW,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_VF,
1502         RTE_FLOW_ITEM_TYPE_END,
1503 };
1504
1505 /* Pattern matched tunnel filter */
1506 static enum rte_flow_item_type pattern_vxlan_1[] = {
1507         RTE_FLOW_ITEM_TYPE_ETH,
1508         RTE_FLOW_ITEM_TYPE_IPV4,
1509         RTE_FLOW_ITEM_TYPE_UDP,
1510         RTE_FLOW_ITEM_TYPE_VXLAN,
1511         RTE_FLOW_ITEM_TYPE_ETH,
1512         RTE_FLOW_ITEM_TYPE_END,
1513 };
1514
1515 static enum rte_flow_item_type pattern_vxlan_2[] = {
1516         RTE_FLOW_ITEM_TYPE_ETH,
1517         RTE_FLOW_ITEM_TYPE_IPV6,
1518         RTE_FLOW_ITEM_TYPE_UDP,
1519         RTE_FLOW_ITEM_TYPE_VXLAN,
1520         RTE_FLOW_ITEM_TYPE_ETH,
1521         RTE_FLOW_ITEM_TYPE_END,
1522 };
1523
1524 static enum rte_flow_item_type pattern_vxlan_3[] = {
1525         RTE_FLOW_ITEM_TYPE_ETH,
1526         RTE_FLOW_ITEM_TYPE_IPV4,
1527         RTE_FLOW_ITEM_TYPE_UDP,
1528         RTE_FLOW_ITEM_TYPE_VXLAN,
1529         RTE_FLOW_ITEM_TYPE_ETH,
1530         RTE_FLOW_ITEM_TYPE_VLAN,
1531         RTE_FLOW_ITEM_TYPE_END,
1532 };
1533
1534 static enum rte_flow_item_type pattern_vxlan_4[] = {
1535         RTE_FLOW_ITEM_TYPE_ETH,
1536         RTE_FLOW_ITEM_TYPE_IPV6,
1537         RTE_FLOW_ITEM_TYPE_UDP,
1538         RTE_FLOW_ITEM_TYPE_VXLAN,
1539         RTE_FLOW_ITEM_TYPE_ETH,
1540         RTE_FLOW_ITEM_TYPE_VLAN,
1541         RTE_FLOW_ITEM_TYPE_END,
1542 };
1543
1544 static enum rte_flow_item_type pattern_nvgre_1[] = {
1545         RTE_FLOW_ITEM_TYPE_ETH,
1546         RTE_FLOW_ITEM_TYPE_IPV4,
1547         RTE_FLOW_ITEM_TYPE_NVGRE,
1548         RTE_FLOW_ITEM_TYPE_ETH,
1549         RTE_FLOW_ITEM_TYPE_END,
1550 };
1551
1552 static enum rte_flow_item_type pattern_nvgre_2[] = {
1553         RTE_FLOW_ITEM_TYPE_ETH,
1554         RTE_FLOW_ITEM_TYPE_IPV6,
1555         RTE_FLOW_ITEM_TYPE_NVGRE,
1556         RTE_FLOW_ITEM_TYPE_ETH,
1557         RTE_FLOW_ITEM_TYPE_END,
1558 };
1559
1560 static enum rte_flow_item_type pattern_nvgre_3[] = {
1561         RTE_FLOW_ITEM_TYPE_ETH,
1562         RTE_FLOW_ITEM_TYPE_IPV4,
1563         RTE_FLOW_ITEM_TYPE_NVGRE,
1564         RTE_FLOW_ITEM_TYPE_ETH,
1565         RTE_FLOW_ITEM_TYPE_VLAN,
1566         RTE_FLOW_ITEM_TYPE_END,
1567 };
1568
1569 static enum rte_flow_item_type pattern_nvgre_4[] = {
1570         RTE_FLOW_ITEM_TYPE_ETH,
1571         RTE_FLOW_ITEM_TYPE_IPV6,
1572         RTE_FLOW_ITEM_TYPE_NVGRE,
1573         RTE_FLOW_ITEM_TYPE_ETH,
1574         RTE_FLOW_ITEM_TYPE_VLAN,
1575         RTE_FLOW_ITEM_TYPE_END,
1576 };
1577
1578 static enum rte_flow_item_type pattern_mpls_1[] = {
1579         RTE_FLOW_ITEM_TYPE_ETH,
1580         RTE_FLOW_ITEM_TYPE_IPV4,
1581         RTE_FLOW_ITEM_TYPE_UDP,
1582         RTE_FLOW_ITEM_TYPE_MPLS,
1583         RTE_FLOW_ITEM_TYPE_END,
1584 };
1585
1586 static enum rte_flow_item_type pattern_mpls_2[] = {
1587         RTE_FLOW_ITEM_TYPE_ETH,
1588         RTE_FLOW_ITEM_TYPE_IPV6,
1589         RTE_FLOW_ITEM_TYPE_UDP,
1590         RTE_FLOW_ITEM_TYPE_MPLS,
1591         RTE_FLOW_ITEM_TYPE_END,
1592 };
1593
1594 static enum rte_flow_item_type pattern_mpls_3[] = {
1595         RTE_FLOW_ITEM_TYPE_ETH,
1596         RTE_FLOW_ITEM_TYPE_IPV4,
1597         RTE_FLOW_ITEM_TYPE_GRE,
1598         RTE_FLOW_ITEM_TYPE_MPLS,
1599         RTE_FLOW_ITEM_TYPE_END,
1600 };
1601
1602 static enum rte_flow_item_type pattern_mpls_4[] = {
1603         RTE_FLOW_ITEM_TYPE_ETH,
1604         RTE_FLOW_ITEM_TYPE_IPV6,
1605         RTE_FLOW_ITEM_TYPE_GRE,
1606         RTE_FLOW_ITEM_TYPE_MPLS,
1607         RTE_FLOW_ITEM_TYPE_END,
1608 };
1609
1610 static enum rte_flow_item_type pattern_qinq_1[] = {
1611         RTE_FLOW_ITEM_TYPE_ETH,
1612         RTE_FLOW_ITEM_TYPE_VLAN,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_END,
1615 };
1616
1617 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1618         /* Ethertype */
1619         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1620         /* FDIR - support default flow type without flexible payload*/
1621         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1622         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1638         /* FDIR - support default flow type with flexible payload */
1639         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1640         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1666         /* FDIR - support single vlan input set */
1667         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1668         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1703         /* FDIR - support VF item */
1704         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1775         /* VXLAN */
1776         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1777         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1778         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1780         /* NVGRE */
1781         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1782         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1783         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1785         /* MPLSoUDP & MPLSoGRE */
1786         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1787         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1788         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1790         /* GTP-C & GTP-U */
1791         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1792         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1793         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1795         /* QINQ */
1796         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1797 };
1798
1799 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1800         do {                                                            \
1801                 act = actions + index;                                  \
1802                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1803                         index++;                                        \
1804                         act = actions + index;                          \
1805                 }                                                       \
1806         } while (0)
1807
1808 /* Find the first VOID or non-VOID item pointer */
1809 static const struct rte_flow_item *
1810 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1811 {
1812         bool is_find;
1813
1814         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1815                 if (is_void)
1816                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1817                 else
1818                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1819                 if (is_find)
1820                         break;
1821                 item++;
1822         }
1823         return item;
1824 }
1825
1826 /* Skip all VOID items of the pattern */
1827 static void
1828 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1829                             const struct rte_flow_item *pattern)
1830 {
1831         uint32_t cpy_count = 0;
1832         const struct rte_flow_item *pb = pattern, *pe = pattern;
1833
1834         for (;;) {
1835                 /* Find a non-void item first */
1836                 pb = i40e_find_first_item(pb, false);
1837                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1838                         pe = pb;
1839                         break;
1840                 }
1841
1842                 /* Find a void item */
1843                 pe = i40e_find_first_item(pb + 1, true);
1844
1845                 cpy_count = pe - pb;
1846                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1847
1848                 items += cpy_count;
1849
1850                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1851                         pb = pe;
1852                         break;
1853                 }
1854
1855                 pb = pe + 1;
1856         }
1857         /* Copy the END item. */
1858         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1859 }
1860
1861 /* Check if the pattern matches a supported item type array */
1862 static bool
1863 i40e_match_pattern(enum rte_flow_item_type *item_array,
1864                    struct rte_flow_item *pattern)
1865 {
1866         struct rte_flow_item *item = pattern;
1867
1868         while ((*item_array == item->type) &&
1869                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1870                 item_array++;
1871                 item++;
1872         }
1873
1874         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1875                 item->type == RTE_FLOW_ITEM_TYPE_END);
1876 }
1877
1878 /* Find if there's parse filter function matched */
1879 static parse_filter_t
1880 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1881 {
1882         parse_filter_t parse_filter = NULL;
1883         uint8_t i = *idx;
1884
1885         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1886                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1887                                         pattern)) {
1888                         parse_filter = i40e_supported_patterns[i].parse_filter;
1889                         break;
1890                 }
1891         }
1892
1893         *idx = ++i;
1894
1895         return parse_filter;
1896 }
1897
1898 /* Parse attributes */
1899 static int
1900 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1901                      struct rte_flow_error *error)
1902 {
1903         /* Must be input direction */
1904         if (!attr->ingress) {
1905                 rte_flow_error_set(error, EINVAL,
1906                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1907                                    attr, "Only support ingress.");
1908                 return -rte_errno;
1909         }
1910
1911         /* Not supported */
1912         if (attr->egress) {
1913                 rte_flow_error_set(error, EINVAL,
1914                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1915                                    attr, "Not support egress.");
1916                 return -rte_errno;
1917         }
1918
1919         /* Not supported */
1920         if (attr->priority) {
1921                 rte_flow_error_set(error, EINVAL,
1922                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1923                                    attr, "Not support priority.");
1924                 return -rte_errno;
1925         }
1926
1927         /* Not supported */
1928         if (attr->group) {
1929                 rte_flow_error_set(error, EINVAL,
1930                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1931                                    attr, "Not support group.");
1932                 return -rte_errno;
1933         }
1934
1935         return 0;
1936 }
1937
1938 static uint16_t
1939 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1940 {
1941         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1942         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1943         uint64_t reg_r = 0;
1944         uint16_t reg_id;
1945         uint16_t tpid;
1946
1947         if (qinq)
1948                 reg_id = 2;
1949         else
1950                 reg_id = 3;
1951
1952         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1953                                     &reg_r, NULL);
1954
1955         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1956
1957         return tpid;
1958 }
1959
1960 /* 1. Last in item should be NULL as range is not supported.
1961  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1962  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1963  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1964  *    FF:FF:FF:FF:FF:FF
1965  * 5. Ether_type mask should be 0xFFFF.
1966  */
1967 static int
1968 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1969                                   const struct rte_flow_item *pattern,
1970                                   struct rte_flow_error *error,
1971                                   struct rte_eth_ethertype_filter *filter)
1972 {
1973         const struct rte_flow_item *item = pattern;
1974         const struct rte_flow_item_eth *eth_spec;
1975         const struct rte_flow_item_eth *eth_mask;
1976         enum rte_flow_item_type item_type;
1977         uint16_t outer_tpid;
1978
1979         outer_tpid = i40e_get_outer_vlan(dev);
1980
1981         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1982                 if (item->last) {
1983                         rte_flow_error_set(error, EINVAL,
1984                                            RTE_FLOW_ERROR_TYPE_ITEM,
1985                                            item,
1986                                            "Not support range");
1987                         return -rte_errno;
1988                 }
1989                 item_type = item->type;
1990                 switch (item_type) {
1991                 case RTE_FLOW_ITEM_TYPE_ETH:
1992                         eth_spec = item->spec;
1993                         eth_mask = item->mask;
1994                         /* Get the MAC info. */
1995                         if (!eth_spec || !eth_mask) {
1996                                 rte_flow_error_set(error, EINVAL,
1997                                                    RTE_FLOW_ERROR_TYPE_ITEM,
1998                                                    item,
1999                                                    "NULL ETH spec/mask");
2000                                 return -rte_errno;
2001                         }
2002
2003                         /* Mask bits of source MAC address must be full of 0.
2004                          * Mask bits of destination MAC address must be full
2005                          * of 1 or full of 0.
2006                          */
2007                         if (!is_zero_ether_addr(&eth_mask->src) ||
2008                             (!is_zero_ether_addr(&eth_mask->dst) &&
2009                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2010                                 rte_flow_error_set(error, EINVAL,
2011                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2012                                                    item,
2013                                                    "Invalid MAC_addr mask");
2014                                 return -rte_errno;
2015                         }
2016
2017                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2018                                 rte_flow_error_set(error, EINVAL,
2019                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2020                                                    item,
2021                                                    "Invalid ethertype mask");
2022                                 return -rte_errno;
2023                         }
2024
2025                         /* If mask bits of destination MAC address
2026                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2027                          */
2028                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2029                                 filter->mac_addr = eth_spec->dst;
2030                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2031                         } else {
2032                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2033                         }
2034                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2035
2036                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2037                             filter->ether_type == ETHER_TYPE_IPv6 ||
2038                             filter->ether_type == ETHER_TYPE_LLDP ||
2039                             filter->ether_type == outer_tpid) {
2040                                 rte_flow_error_set(error, EINVAL,
2041                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2042                                                    item,
2043                                                    "Unsupported ether_type in"
2044                                                    " control packet filter.");
2045                                 return -rte_errno;
2046                         }
2047                         break;
2048                 default:
2049                         break;
2050                 }
2051         }
2052
2053         return 0;
2054 }
2055
2056 /* Ethertype action only supports QUEUE or DROP. */
2057 static int
2058 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2059                                  const struct rte_flow_action *actions,
2060                                  struct rte_flow_error *error,
2061                                  struct rte_eth_ethertype_filter *filter)
2062 {
2063         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2064         const struct rte_flow_action *act;
2065         const struct rte_flow_action_queue *act_q;
2066         uint32_t index = 0;
2067
2068         /* Check if the first non-void action is QUEUE or DROP. */
2069         NEXT_ITEM_OF_ACTION(act, actions, index);
2070         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2071             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2072                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2073                                    act, "Not supported action.");
2074                 return -rte_errno;
2075         }
2076
2077         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2078                 act_q = act->conf;
2079                 filter->queue = act_q->index;
2080                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2081                         rte_flow_error_set(error, EINVAL,
2082                                            RTE_FLOW_ERROR_TYPE_ACTION,
2083                                            act, "Invalid queue ID for"
2084                                            " ethertype_filter.");
2085                         return -rte_errno;
2086                 }
2087         } else {
2088                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2089         }
2090
2091         /* Check if the next non-void item is END */
2092         index++;
2093         NEXT_ITEM_OF_ACTION(act, actions, index);
2094         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2095                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2096                                    act, "Not supported action.");
2097                 return -rte_errno;
2098         }
2099
2100         return 0;
2101 }
2102
2103 static int
2104 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2105                                  const struct rte_flow_attr *attr,
2106                                  const struct rte_flow_item pattern[],
2107                                  const struct rte_flow_action actions[],
2108                                  struct rte_flow_error *error,
2109                                  union i40e_filter_t *filter)
2110 {
2111         struct rte_eth_ethertype_filter *ethertype_filter =
2112                 &filter->ethertype_filter;
2113         int ret;
2114
2115         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2116                                                 ethertype_filter);
2117         if (ret)
2118                 return ret;
2119
2120         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2121                                                ethertype_filter);
2122         if (ret)
2123                 return ret;
2124
2125         ret = i40e_flow_parse_attr(attr, error);
2126         if (ret)
2127                 return ret;
2128
2129         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2130
2131         return ret;
2132 }
2133
2134 static int
2135 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2136                          const struct rte_flow_item_raw *raw_spec,
2137                          struct rte_flow_error *error)
2138 {
2139         if (!raw_spec->relative) {
2140                 rte_flow_error_set(error, EINVAL,
2141                                    RTE_FLOW_ERROR_TYPE_ITEM,
2142                                    item,
2143                                    "Relative should be 1.");
2144                 return -rte_errno;
2145         }
2146
2147         if (raw_spec->offset % sizeof(uint16_t)) {
2148                 rte_flow_error_set(error, EINVAL,
2149                                    RTE_FLOW_ERROR_TYPE_ITEM,
2150                                    item,
2151                                    "Offset should be even.");
2152                 return -rte_errno;
2153         }
2154
2155         if (raw_spec->search || raw_spec->limit) {
2156                 rte_flow_error_set(error, EINVAL,
2157                                    RTE_FLOW_ERROR_TYPE_ITEM,
2158                                    item,
2159                                    "search or limit is not supported.");
2160                 return -rte_errno;
2161         }
2162
2163         if (raw_spec->offset < 0) {
2164                 rte_flow_error_set(error, EINVAL,
2165                                    RTE_FLOW_ERROR_TYPE_ITEM,
2166                                    item,
2167                                    "Offset should be non-negative.");
2168                 return -rte_errno;
2169         }
2170         return 0;
2171 }
2172
2173 static int
2174 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2175                          struct i40e_fdir_flex_pit *flex_pit,
2176                          enum i40e_flxpld_layer_idx layer_idx,
2177                          uint8_t raw_id)
2178 {
2179         uint8_t field_idx;
2180
2181         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2182         /* Check if the configuration is conflicted */
2183         if (pf->fdir.flex_pit_flag[layer_idx] &&
2184             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2185              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2186              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2187                 return -1;
2188
2189         /* Check if the configuration exists. */
2190         if (pf->fdir.flex_pit_flag[layer_idx] &&
2191             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2192              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2193              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2194                 return 1;
2195
2196         pf->fdir.flex_set[field_idx].src_offset =
2197                 flex_pit->src_offset;
2198         pf->fdir.flex_set[field_idx].size =
2199                 flex_pit->size;
2200         pf->fdir.flex_set[field_idx].dst_offset =
2201                 flex_pit->dst_offset;
2202
2203         return 0;
2204 }
2205
2206 static int
2207 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2208                           enum i40e_filter_pctype pctype,
2209                           uint8_t *mask)
2210 {
2211         struct i40e_fdir_flex_mask flex_mask;
2212         uint16_t mask_tmp;
2213         uint8_t i, nb_bitmask = 0;
2214
2215         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2216         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2217                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2218                 if (mask_tmp) {
2219                         flex_mask.word_mask |=
2220                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2221                         if (mask_tmp != UINT16_MAX) {
2222                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2223                                 flex_mask.bitmask[nb_bitmask].offset =
2224                                         i / sizeof(uint16_t);
2225                                 nb_bitmask++;
2226                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2227                                         return -1;
2228                         }
2229                 }
2230         }
2231         flex_mask.nb_bitmask = nb_bitmask;
2232
2233         if (pf->fdir.flex_mask_flag[pctype] &&
2234             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2235                     sizeof(struct i40e_fdir_flex_mask))))
2236                 return -2;
2237         else if (pf->fdir.flex_mask_flag[pctype] &&
2238                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2239                           sizeof(struct i40e_fdir_flex_mask))))
2240                 return 1;
2241
2242         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2243                sizeof(struct i40e_fdir_flex_mask));
2244         return 0;
2245 }
2246
2247 static void
2248 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2249                             enum i40e_flxpld_layer_idx layer_idx,
2250                             uint8_t raw_id)
2251 {
2252         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2253         uint32_t flx_pit, flx_ort;
2254         uint8_t field_idx;
2255         uint16_t min_next_off = 0;  /* in words */
2256         uint8_t i;
2257
2258         if (raw_id) {
2259                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2260                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2261                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2262                 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2263         }
2264
2265         /* Set flex pit */
2266         for (i = 0; i < raw_id; i++) {
2267                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2268                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2269                                      pf->fdir.flex_set[field_idx].size,
2270                                      pf->fdir.flex_set[field_idx].dst_offset);
2271
2272                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2273                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2274                         pf->fdir.flex_set[field_idx].size;
2275         }
2276
2277         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2278                 /* set the non-used register obeying register's constrain */
2279                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2280                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2281                                      NONUSE_FLX_PIT_DEST_OFF);
2282                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2283                 min_next_off++;
2284         }
2285
2286         pf->fdir.flex_pit_flag[layer_idx] = 1;
2287 }
2288
2289 static void
2290 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2291                             enum i40e_filter_pctype pctype)
2292 {
2293         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2294         struct i40e_fdir_flex_mask *flex_mask;
2295         uint32_t flxinset, fd_mask;
2296         uint8_t i;
2297
2298         /* Set flex mask */
2299         flex_mask = &pf->fdir.flex_mask[pctype];
2300         flxinset = (flex_mask->word_mask <<
2301                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2302                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2303         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2304
2305         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2306                 fd_mask = (flex_mask->bitmask[i].mask <<
2307                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2308                         I40E_PRTQF_FD_MSK_MASK_MASK;
2309                 fd_mask |= ((flex_mask->bitmask[i].offset +
2310                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2311                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2312                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2313                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2314         }
2315
2316         pf->fdir.flex_mask_flag[pctype] = 1;
2317 }
2318
2319 static int
2320 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2321                          enum i40e_filter_pctype pctype,
2322                          uint64_t input_set)
2323 {
2324         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2325         uint64_t inset_reg = 0;
2326         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2327         int i, num;
2328
2329         /* Check if the input set is valid */
2330         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2331                                     input_set) != 0) {
2332                 PMD_DRV_LOG(ERR, "Invalid input set");
2333                 return -EINVAL;
2334         }
2335
2336         /* Check if the configuration is conflicted */
2337         if (pf->fdir.inset_flag[pctype] &&
2338             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2339                 return -1;
2340
2341         if (pf->fdir.inset_flag[pctype] &&
2342             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2343                 return 0;
2344
2345         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2346                                            I40E_INSET_MASK_NUM_REG);
2347         if (num < 0)
2348                 return -EINVAL;
2349
2350         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2351
2352         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2353                              (uint32_t)(inset_reg & UINT32_MAX));
2354         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2355                              (uint32_t)((inset_reg >>
2356                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2357
2358         for (i = 0; i < num; i++)
2359                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2360                                      mask_reg[i]);
2361
2362         /*clear unused mask registers of the pctype */
2363         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2364                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2365         I40E_WRITE_FLUSH(hw);
2366
2367         pf->fdir.input_set[pctype] = input_set;
2368         pf->fdir.inset_flag[pctype] = 1;
2369         return 0;
2370 }
2371
2372 static uint8_t
2373 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2374                                 enum rte_flow_item_type item_type,
2375                                 struct i40e_fdir_filter_conf *filter)
2376 {
2377         struct i40e_customized_pctype *cus_pctype = NULL;
2378
2379         switch (item_type) {
2380         case RTE_FLOW_ITEM_TYPE_GTPC:
2381                 cus_pctype = i40e_find_customized_pctype(pf,
2382                                                          I40E_CUSTOMIZED_GTPC);
2383                 break;
2384         case RTE_FLOW_ITEM_TYPE_GTPU:
2385                 if (!filter->input.flow_ext.inner_ip)
2386                         cus_pctype = i40e_find_customized_pctype(pf,
2387                                                          I40E_CUSTOMIZED_GTPU);
2388                 else if (filter->input.flow_ext.iip_type ==
2389                          I40E_FDIR_IPTYPE_IPV4)
2390                         cus_pctype = i40e_find_customized_pctype(pf,
2391                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2392                 else if (filter->input.flow_ext.iip_type ==
2393                          I40E_FDIR_IPTYPE_IPV6)
2394                         cus_pctype = i40e_find_customized_pctype(pf,
2395                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2396                 break;
2397         default:
2398                 PMD_DRV_LOG(ERR, "Unsupported item type");
2399                 break;
2400         }
2401
2402         if (cus_pctype)
2403                 return cus_pctype->pctype;
2404
2405         return I40E_FILTER_PCTYPE_INVALID;
2406 }
2407
2408 /* 1. Last in item should be NULL as range is not supported.
2409  * 2. Supported patterns: refer to array i40e_supported_patterns.
2410  * 3. Default supported flow type and input set: refer to array
2411  *    valid_fdir_inset_table in i40e_ethdev.c.
2412  * 4. Mask of fields which need to be matched should be
2413  *    filled with 1.
2414  * 5. Mask of fields which needn't to be matched should be
2415  *    filled with 0.
2416  * 6. GTP profile supports GTPv1 only.
2417  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2418  */
2419 static int
2420 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2421                              const struct rte_flow_item *pattern,
2422                              struct rte_flow_error *error,
2423                              struct i40e_fdir_filter_conf *filter)
2424 {
2425         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2426         const struct rte_flow_item *item = pattern;
2427         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2428         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2429         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2430         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2431         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2432         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2433         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2434         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2435         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2436         const struct rte_flow_item_vf *vf_spec;
2437
2438         uint8_t pctype = 0;
2439         uint64_t input_set = I40E_INSET_NONE;
2440         uint16_t frag_off;
2441         enum rte_flow_item_type item_type;
2442         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2443         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2444         uint32_t i, j;
2445         uint8_t  ipv6_addr_mask[16] = {
2446                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2447                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2448         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2449         uint8_t raw_id = 0;
2450         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2451         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2452         struct i40e_fdir_flex_pit flex_pit;
2453         uint8_t next_dst_off = 0;
2454         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2455         uint16_t flex_size;
2456         bool cfg_flex_pit = true;
2457         bool cfg_flex_msk = true;
2458         uint16_t outer_tpid;
2459         uint16_t ether_type;
2460         uint32_t vtc_flow_cpu;
2461         bool outer_ip = true;
2462         int ret;
2463
2464         memset(off_arr, 0, sizeof(off_arr));
2465         memset(len_arr, 0, sizeof(len_arr));
2466         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2467         outer_tpid = i40e_get_outer_vlan(dev);
2468         filter->input.flow_ext.customized_pctype = false;
2469         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2470                 if (item->last) {
2471                         rte_flow_error_set(error, EINVAL,
2472                                            RTE_FLOW_ERROR_TYPE_ITEM,
2473                                            item,
2474                                            "Not support range");
2475                         return -rte_errno;
2476                 }
2477                 item_type = item->type;
2478                 switch (item_type) {
2479                 case RTE_FLOW_ITEM_TYPE_ETH:
2480                         eth_spec = item->spec;
2481                         eth_mask = item->mask;
2482
2483                         if (eth_spec && eth_mask) {
2484                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2485                                     !is_zero_ether_addr(&eth_mask->dst)) {
2486                                         rte_flow_error_set(error, EINVAL,
2487                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2488                                                       item,
2489                                                       "Invalid MAC_addr mask.");
2490                                         return -rte_errno;
2491                                 }
2492
2493                                 if ((eth_mask->type & UINT16_MAX) ==
2494                                     UINT16_MAX) {
2495                                         input_set |= I40E_INSET_LAST_ETHER_TYPE;
2496                                         filter->input.flow.l2_flow.ether_type =
2497                                                 eth_spec->type;
2498                                 }
2499
2500                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2501                                 if (ether_type == ETHER_TYPE_IPv4 ||
2502                                     ether_type == ETHER_TYPE_IPv6 ||
2503                                     ether_type == ETHER_TYPE_ARP ||
2504                                     ether_type == outer_tpid) {
2505                                         rte_flow_error_set(error, EINVAL,
2506                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2507                                                      item,
2508                                                      "Unsupported ether_type.");
2509                                         return -rte_errno;
2510                                 }
2511                         }
2512
2513                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2514                         layer_idx = I40E_FLXPLD_L2_IDX;
2515
2516                         break;
2517                 case RTE_FLOW_ITEM_TYPE_VLAN:
2518                         vlan_spec = item->spec;
2519                         vlan_mask = item->mask;
2520                         if (vlan_spec && vlan_mask) {
2521                                 if (vlan_mask->tci ==
2522                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2523                                         input_set |= I40E_INSET_VLAN_INNER;
2524                                         filter->input.flow_ext.vlan_tci =
2525                                                 vlan_spec->tci;
2526                                 }
2527                         }
2528
2529                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2530                         layer_idx = I40E_FLXPLD_L2_IDX;
2531
2532                         break;
2533                 case RTE_FLOW_ITEM_TYPE_IPV4:
2534                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2535                         ipv4_spec = item->spec;
2536                         ipv4_mask = item->mask;
2537                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2538                         layer_idx = I40E_FLXPLD_L3_IDX;
2539
2540                         if (ipv4_spec && ipv4_mask && outer_ip) {
2541                                 /* Check IPv4 mask and update input set */
2542                                 if (ipv4_mask->hdr.version_ihl ||
2543                                     ipv4_mask->hdr.total_length ||
2544                                     ipv4_mask->hdr.packet_id ||
2545                                     ipv4_mask->hdr.fragment_offset ||
2546                                     ipv4_mask->hdr.hdr_checksum) {
2547                                         rte_flow_error_set(error, EINVAL,
2548                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2549                                                    item,
2550                                                    "Invalid IPv4 mask.");
2551                                         return -rte_errno;
2552                                 }
2553
2554                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2555                                         input_set |= I40E_INSET_IPV4_SRC;
2556                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2557                                         input_set |= I40E_INSET_IPV4_DST;
2558                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2559                                         input_set |= I40E_INSET_IPV4_TOS;
2560                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2561                                         input_set |= I40E_INSET_IPV4_TTL;
2562                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2563                                         input_set |= I40E_INSET_IPV4_PROTO;
2564
2565                                 /* Check if it is fragment. */
2566                                 frag_off = ipv4_spec->hdr.fragment_offset;
2567                                 frag_off = rte_be_to_cpu_16(frag_off);
2568                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2569                                     frag_off & IPV4_HDR_MF_FLAG)
2570                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2571
2572                                 /* Get the filter info */
2573                                 filter->input.flow.ip4_flow.proto =
2574                                         ipv4_spec->hdr.next_proto_id;
2575                                 filter->input.flow.ip4_flow.tos =
2576                                         ipv4_spec->hdr.type_of_service;
2577                                 filter->input.flow.ip4_flow.ttl =
2578                                         ipv4_spec->hdr.time_to_live;
2579                                 filter->input.flow.ip4_flow.src_ip =
2580                                         ipv4_spec->hdr.src_addr;
2581                                 filter->input.flow.ip4_flow.dst_ip =
2582                                         ipv4_spec->hdr.dst_addr;
2583                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2584                                 filter->input.flow_ext.inner_ip = true;
2585                                 filter->input.flow_ext.iip_type =
2586                                         I40E_FDIR_IPTYPE_IPV4;
2587                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2588                                 rte_flow_error_set(error, EINVAL,
2589                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2590                                                    item,
2591                                                    "Invalid inner IPv4 mask.");
2592                                 return -rte_errno;
2593                         }
2594
2595                         if (outer_ip)
2596                                 outer_ip = false;
2597
2598                         break;
2599                 case RTE_FLOW_ITEM_TYPE_IPV6:
2600                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2601                         ipv6_spec = item->spec;
2602                         ipv6_mask = item->mask;
2603                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2604                         layer_idx = I40E_FLXPLD_L3_IDX;
2605
2606                         if (ipv6_spec && ipv6_mask && outer_ip) {
2607                                 /* Check IPv6 mask and update input set */
2608                                 if (ipv6_mask->hdr.payload_len) {
2609                                         rte_flow_error_set(error, EINVAL,
2610                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2611                                                    item,
2612                                                    "Invalid IPv6 mask");
2613                                         return -rte_errno;
2614                                 }
2615
2616                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2617                                             ipv6_addr_mask,
2618                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2619                                         input_set |= I40E_INSET_IPV6_SRC;
2620                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2621                                             ipv6_addr_mask,
2622                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2623                                         input_set |= I40E_INSET_IPV6_DST;
2624
2625                                 if ((ipv6_mask->hdr.vtc_flow &
2626                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2627                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2628                                         input_set |= I40E_INSET_IPV6_TC;
2629                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2630                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2631                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2632                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2633
2634                                 /* Get filter info */
2635                                 vtc_flow_cpu =
2636                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2637                                 filter->input.flow.ipv6_flow.tc =
2638                                         (uint8_t)(vtc_flow_cpu >>
2639                                                   I40E_FDIR_IPv6_TC_OFFSET);
2640                                 filter->input.flow.ipv6_flow.proto =
2641                                         ipv6_spec->hdr.proto;
2642                                 filter->input.flow.ipv6_flow.hop_limits =
2643                                         ipv6_spec->hdr.hop_limits;
2644
2645                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2646                                            ipv6_spec->hdr.src_addr, 16);
2647                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2648                                            ipv6_spec->hdr.dst_addr, 16);
2649
2650                                 /* Check if it is fragment. */
2651                                 if (ipv6_spec->hdr.proto ==
2652                                     I40E_IPV6_FRAG_HEADER)
2653                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2654                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2655                                 filter->input.flow_ext.inner_ip = true;
2656                                 filter->input.flow_ext.iip_type =
2657                                         I40E_FDIR_IPTYPE_IPV6;
2658                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2659                                 rte_flow_error_set(error, EINVAL,
2660                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2661                                                    item,
2662                                                    "Invalid inner IPv6 mask");
2663                                 return -rte_errno;
2664                         }
2665
2666                         if (outer_ip)
2667                                 outer_ip = false;
2668                         break;
2669                 case RTE_FLOW_ITEM_TYPE_TCP:
2670                         tcp_spec = item->spec;
2671                         tcp_mask = item->mask;
2672
2673                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2674                                 pctype =
2675                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2676                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2677                                 pctype =
2678                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2679                         if (tcp_spec && tcp_mask) {
2680                                 /* Check TCP mask and update input set */
2681                                 if (tcp_mask->hdr.sent_seq ||
2682                                     tcp_mask->hdr.recv_ack ||
2683                                     tcp_mask->hdr.data_off ||
2684                                     tcp_mask->hdr.tcp_flags ||
2685                                     tcp_mask->hdr.rx_win ||
2686                                     tcp_mask->hdr.cksum ||
2687                                     tcp_mask->hdr.tcp_urp) {
2688                                         rte_flow_error_set(error, EINVAL,
2689                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2690                                                    item,
2691                                                    "Invalid TCP mask");
2692                                         return -rte_errno;
2693                                 }
2694
2695                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2696                                         input_set |= I40E_INSET_SRC_PORT;
2697                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2698                                         input_set |= I40E_INSET_DST_PORT;
2699
2700                                 /* Get filter info */
2701                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2702                                         filter->input.flow.tcp4_flow.src_port =
2703                                                 tcp_spec->hdr.src_port;
2704                                         filter->input.flow.tcp4_flow.dst_port =
2705                                                 tcp_spec->hdr.dst_port;
2706                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2707                                         filter->input.flow.tcp6_flow.src_port =
2708                                                 tcp_spec->hdr.src_port;
2709                                         filter->input.flow.tcp6_flow.dst_port =
2710                                                 tcp_spec->hdr.dst_port;
2711                                 }
2712                         }
2713
2714                         layer_idx = I40E_FLXPLD_L4_IDX;
2715
2716                         break;
2717                 case RTE_FLOW_ITEM_TYPE_UDP:
2718                         udp_spec = item->spec;
2719                         udp_mask = item->mask;
2720
2721                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2722                                 pctype =
2723                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2724                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2725                                 pctype =
2726                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2727
2728                         if (udp_spec && udp_mask) {
2729                                 /* Check UDP mask and update input set*/
2730                                 if (udp_mask->hdr.dgram_len ||
2731                                     udp_mask->hdr.dgram_cksum) {
2732                                         rte_flow_error_set(error, EINVAL,
2733                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2734                                                    item,
2735                                                    "Invalid UDP mask");
2736                                         return -rte_errno;
2737                                 }
2738
2739                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2740                                         input_set |= I40E_INSET_SRC_PORT;
2741                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2742                                         input_set |= I40E_INSET_DST_PORT;
2743
2744                                 /* Get filter info */
2745                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2746                                         filter->input.flow.udp4_flow.src_port =
2747                                                 udp_spec->hdr.src_port;
2748                                         filter->input.flow.udp4_flow.dst_port =
2749                                                 udp_spec->hdr.dst_port;
2750                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2751                                         filter->input.flow.udp6_flow.src_port =
2752                                                 udp_spec->hdr.src_port;
2753                                         filter->input.flow.udp6_flow.dst_port =
2754                                                 udp_spec->hdr.dst_port;
2755                                 }
2756                         }
2757
2758                         layer_idx = I40E_FLXPLD_L4_IDX;
2759
2760                         break;
2761                 case RTE_FLOW_ITEM_TYPE_GTPC:
2762                 case RTE_FLOW_ITEM_TYPE_GTPU:
2763                         if (!pf->gtp_support) {
2764                                 rte_flow_error_set(error, EINVAL,
2765                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2766                                                    item,
2767                                                    "Unsupported protocol");
2768                                 return -rte_errno;
2769                         }
2770
2771                         gtp_spec = item->spec;
2772                         gtp_mask = item->mask;
2773
2774                         if (gtp_spec && gtp_mask) {
2775                                 if (gtp_mask->v_pt_rsv_flags ||
2776                                     gtp_mask->msg_type ||
2777                                     gtp_mask->msg_len ||
2778                                     gtp_mask->teid != UINT32_MAX) {
2779                                         rte_flow_error_set(error, EINVAL,
2780                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2781                                                    item,
2782                                                    "Invalid GTP mask");
2783                                         return -rte_errno;
2784                                 }
2785
2786                                 filter->input.flow.gtp_flow.teid =
2787                                         gtp_spec->teid;
2788                                 filter->input.flow_ext.customized_pctype = true;
2789                                 cus_proto = item_type;
2790                         }
2791                         break;
2792                 case RTE_FLOW_ITEM_TYPE_SCTP:
2793                         sctp_spec = item->spec;
2794                         sctp_mask = item->mask;
2795
2796                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2797                                 pctype =
2798                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2799                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2800                                 pctype =
2801                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2802
2803                         if (sctp_spec && sctp_mask) {
2804                                 /* Check SCTP mask and update input set */
2805                                 if (sctp_mask->hdr.cksum) {
2806                                         rte_flow_error_set(error, EINVAL,
2807                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2808                                                    item,
2809                                                    "Invalid UDP mask");
2810                                         return -rte_errno;
2811                                 }
2812
2813                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2814                                         input_set |= I40E_INSET_SRC_PORT;
2815                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2816                                         input_set |= I40E_INSET_DST_PORT;
2817                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2818                                         input_set |= I40E_INSET_SCTP_VT;
2819
2820                                 /* Get filter info */
2821                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2822                                         filter->input.flow.sctp4_flow.src_port =
2823                                                 sctp_spec->hdr.src_port;
2824                                         filter->input.flow.sctp4_flow.dst_port =
2825                                                 sctp_spec->hdr.dst_port;
2826                                         filter->input.flow.sctp4_flow.verify_tag
2827                                                 = sctp_spec->hdr.tag;
2828                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2829                                         filter->input.flow.sctp6_flow.src_port =
2830                                                 sctp_spec->hdr.src_port;
2831                                         filter->input.flow.sctp6_flow.dst_port =
2832                                                 sctp_spec->hdr.dst_port;
2833                                         filter->input.flow.sctp6_flow.verify_tag
2834                                                 = sctp_spec->hdr.tag;
2835                                 }
2836                         }
2837
2838                         layer_idx = I40E_FLXPLD_L4_IDX;
2839
2840                         break;
2841                 case RTE_FLOW_ITEM_TYPE_RAW:
2842                         raw_spec = item->spec;
2843                         raw_mask = item->mask;
2844
2845                         if (!raw_spec || !raw_mask) {
2846                                 rte_flow_error_set(error, EINVAL,
2847                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2848                                                    item,
2849                                                    "NULL RAW spec/mask");
2850                                 return -rte_errno;
2851                         }
2852
2853                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2854                         if (ret < 0)
2855                                 return ret;
2856
2857                         off_arr[raw_id] = raw_spec->offset;
2858                         len_arr[raw_id] = raw_spec->length;
2859
2860                         flex_size = 0;
2861                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2862                         flex_pit.size =
2863                                 raw_spec->length / sizeof(uint16_t);
2864                         flex_pit.dst_offset =
2865                                 next_dst_off / sizeof(uint16_t);
2866
2867                         for (i = 0; i <= raw_id; i++) {
2868                                 if (i == raw_id)
2869                                         flex_pit.src_offset +=
2870                                                 raw_spec->offset /
2871                                                 sizeof(uint16_t);
2872                                 else
2873                                         flex_pit.src_offset +=
2874                                                 (off_arr[i] + len_arr[i]) /
2875                                                 sizeof(uint16_t);
2876                                 flex_size += len_arr[i];
2877                         }
2878                         if (((flex_pit.src_offset + flex_pit.size) >=
2879                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2880                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2881                                 rte_flow_error_set(error, EINVAL,
2882                                            RTE_FLOW_ERROR_TYPE_ITEM,
2883                                            item,
2884                                            "Exceeds maxmial payload limit.");
2885                                 return -rte_errno;
2886                         }
2887
2888                         /* Store flex pit to SW */
2889                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2890                                                        layer_idx, raw_id);
2891                         if (ret < 0) {
2892                                 rte_flow_error_set(error, EINVAL,
2893                                    RTE_FLOW_ERROR_TYPE_ITEM,
2894                                    item,
2895                                    "Conflict with the first flexible rule.");
2896                                 return -rte_errno;
2897                         } else if (ret > 0)
2898                                 cfg_flex_pit = false;
2899
2900                         for (i = 0; i < raw_spec->length; i++) {
2901                                 j = i + next_dst_off;
2902                                 filter->input.flow_ext.flexbytes[j] =
2903                                         raw_spec->pattern[i];
2904                                 flex_mask[j] = raw_mask->pattern[i];
2905                         }
2906
2907                         next_dst_off += raw_spec->length;
2908                         raw_id++;
2909                         break;
2910                 case RTE_FLOW_ITEM_TYPE_VF:
2911                         vf_spec = item->spec;
2912                         filter->input.flow_ext.is_vf = 1;
2913                         filter->input.flow_ext.dst_id = vf_spec->id;
2914                         if (filter->input.flow_ext.is_vf &&
2915                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2916                                 rte_flow_error_set(error, EINVAL,
2917                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2918                                                    item,
2919                                                    "Invalid VF ID for FDIR.");
2920                                 return -rte_errno;
2921                         }
2922                         break;
2923                 default:
2924                         break;
2925                 }
2926         }
2927
2928         /* Get customized pctype value */
2929         if (filter->input.flow_ext.customized_pctype) {
2930                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2931                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2932                         rte_flow_error_set(error, EINVAL,
2933                                            RTE_FLOW_ERROR_TYPE_ITEM,
2934                                            item,
2935                                            "Unsupported pctype");
2936                         return -rte_errno;
2937                 }
2938         }
2939
2940         /* If customized pctype is not used, set fdir configuration.*/
2941         if (!filter->input.flow_ext.customized_pctype) {
2942                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2943                 if (ret == -1) {
2944                         rte_flow_error_set(error, EINVAL,
2945                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2946                                            "Conflict with the first rule's input set.");
2947                         return -rte_errno;
2948                 } else if (ret == -EINVAL) {
2949                         rte_flow_error_set(error, EINVAL,
2950                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2951                                            "Invalid pattern mask.");
2952                         return -rte_errno;
2953                 }
2954
2955                 /* Store flex mask to SW */
2956                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2957                 if (ret == -1) {
2958                         rte_flow_error_set(error, EINVAL,
2959                                            RTE_FLOW_ERROR_TYPE_ITEM,
2960                                            item,
2961                                            "Exceed maximal number of bitmasks");
2962                         return -rte_errno;
2963                 } else if (ret == -2) {
2964                         rte_flow_error_set(error, EINVAL,
2965                                            RTE_FLOW_ERROR_TYPE_ITEM,
2966                                            item,
2967                                            "Conflict with the first flexible rule");
2968                         return -rte_errno;
2969                 } else if (ret > 0)
2970                         cfg_flex_msk = false;
2971
2972                 if (cfg_flex_pit)
2973                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
2974
2975                 if (cfg_flex_msk)
2976                         i40e_flow_set_fdir_flex_msk(pf, pctype);
2977         }
2978
2979         filter->input.pctype = pctype;
2980
2981         return 0;
2982 }
2983
2984 /* Parse to get the action info of a FDIR filter.
2985  * FDIR action supports QUEUE or (QUEUE + MARK).
2986  */
2987 static int
2988 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
2989                             const struct rte_flow_action *actions,
2990                             struct rte_flow_error *error,
2991                             struct i40e_fdir_filter_conf *filter)
2992 {
2993         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2994         const struct rte_flow_action *act;
2995         const struct rte_flow_action_queue *act_q;
2996         const struct rte_flow_action_mark *mark_spec;
2997         uint32_t index = 0;
2998
2999         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3000         NEXT_ITEM_OF_ACTION(act, actions, index);
3001         switch (act->type) {
3002         case RTE_FLOW_ACTION_TYPE_QUEUE:
3003                 act_q = act->conf;
3004                 filter->action.rx_queue = act_q->index;
3005                 if ((!filter->input.flow_ext.is_vf &&
3006                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3007                     (filter->input.flow_ext.is_vf &&
3008                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3009                         rte_flow_error_set(error, EINVAL,
3010                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3011                                            "Invalid queue ID for FDIR.");
3012                         return -rte_errno;
3013                 }
3014                 filter->action.behavior = I40E_FDIR_ACCEPT;
3015                 break;
3016         case RTE_FLOW_ACTION_TYPE_DROP:
3017                 filter->action.behavior = I40E_FDIR_REJECT;
3018                 break;
3019         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3020                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3021                 break;
3022         default:
3023                 rte_flow_error_set(error, EINVAL,
3024                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3025                                    "Invalid action.");
3026                 return -rte_errno;
3027         }
3028
3029         /* Check if the next non-void item is MARK or FLAG or END. */
3030         index++;
3031         NEXT_ITEM_OF_ACTION(act, actions, index);
3032         switch (act->type) {
3033         case RTE_FLOW_ACTION_TYPE_MARK:
3034                 mark_spec = act->conf;
3035                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3036                 filter->soft_id = mark_spec->id;
3037                 break;
3038         case RTE_FLOW_ACTION_TYPE_FLAG:
3039                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3040                 break;
3041         case RTE_FLOW_ACTION_TYPE_END:
3042                 return 0;
3043         default:
3044                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3045                                    act, "Invalid action.");
3046                 return -rte_errno;
3047         }
3048
3049         /* Check if the next non-void item is END */
3050         index++;
3051         NEXT_ITEM_OF_ACTION(act, actions, index);
3052         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3053                 rte_flow_error_set(error, EINVAL,
3054                                    RTE_FLOW_ERROR_TYPE_ACTION,
3055                                    act, "Invalid action.");
3056                 return -rte_errno;
3057         }
3058
3059         return 0;
3060 }
3061
3062 static int
3063 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3064                             const struct rte_flow_attr *attr,
3065                             const struct rte_flow_item pattern[],
3066                             const struct rte_flow_action actions[],
3067                             struct rte_flow_error *error,
3068                             union i40e_filter_t *filter)
3069 {
3070         struct i40e_fdir_filter_conf *fdir_filter =
3071                 &filter->fdir_filter;
3072         int ret;
3073
3074         ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3075         if (ret)
3076                 return ret;
3077
3078         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3079         if (ret)
3080                 return ret;
3081
3082         ret = i40e_flow_parse_attr(attr, error);
3083         if (ret)
3084                 return ret;
3085
3086         cons_filter_type = RTE_ETH_FILTER_FDIR;
3087
3088         if (dev->data->dev_conf.fdir_conf.mode !=
3089             RTE_FDIR_MODE_PERFECT) {
3090                 rte_flow_error_set(error, ENOTSUP,
3091                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3092                                    NULL,
3093                                    "Check the mode in fdir_conf.");
3094                 return -rte_errno;
3095         }
3096
3097         return 0;
3098 }
3099
3100 /* Parse to get the action info of a tunnel filter
3101  * Tunnel action only supports PF, VF and QUEUE.
3102  */
3103 static int
3104 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3105                               const struct rte_flow_action *actions,
3106                               struct rte_flow_error *error,
3107                               struct i40e_tunnel_filter_conf *filter)
3108 {
3109         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3110         const struct rte_flow_action *act;
3111         const struct rte_flow_action_queue *act_q;
3112         const struct rte_flow_action_vf *act_vf;
3113         uint32_t index = 0;
3114
3115         /* Check if the first non-void action is PF or VF. */
3116         NEXT_ITEM_OF_ACTION(act, actions, index);
3117         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3118             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3119                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3120                                    act, "Not supported action.");
3121                 return -rte_errno;
3122         }
3123
3124         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3125                 act_vf = act->conf;
3126                 filter->vf_id = act_vf->id;
3127                 filter->is_to_vf = 1;
3128                 if (filter->vf_id >= pf->vf_num) {
3129                         rte_flow_error_set(error, EINVAL,
3130                                    RTE_FLOW_ERROR_TYPE_ACTION,
3131                                    act, "Invalid VF ID for tunnel filter");
3132                         return -rte_errno;
3133                 }
3134         }
3135
3136         /* Check if the next non-void item is QUEUE */
3137         index++;
3138         NEXT_ITEM_OF_ACTION(act, actions, index);
3139         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3140                 act_q = act->conf;
3141                 filter->queue_id = act_q->index;
3142                 if ((!filter->is_to_vf) &&
3143                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3144                         rte_flow_error_set(error, EINVAL,
3145                                    RTE_FLOW_ERROR_TYPE_ACTION,
3146                                    act, "Invalid queue ID for tunnel filter");
3147                         return -rte_errno;
3148                 } else if (filter->is_to_vf &&
3149                            (filter->queue_id >= pf->vf_nb_qps)) {
3150                         rte_flow_error_set(error, EINVAL,
3151                                    RTE_FLOW_ERROR_TYPE_ACTION,
3152                                    act, "Invalid queue ID for tunnel filter");
3153                         return -rte_errno;
3154                 }
3155         }
3156
3157         /* Check if the next non-void item is END */
3158         index++;
3159         NEXT_ITEM_OF_ACTION(act, actions, index);
3160         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3161                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3162                                    act, "Not supported action.");
3163                 return -rte_errno;
3164         }
3165
3166         return 0;
3167 }
3168
3169 static uint16_t i40e_supported_tunnel_filter_types[] = {
3170         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3171         ETH_TUNNEL_FILTER_IVLAN,
3172         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3173         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3174         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3175         ETH_TUNNEL_FILTER_IMAC,
3176         ETH_TUNNEL_FILTER_IMAC,
3177 };
3178
3179 static int
3180 i40e_check_tunnel_filter_type(uint8_t filter_type)
3181 {
3182         uint8_t i;
3183
3184         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3185                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3186                         return 0;
3187         }
3188
3189         return -1;
3190 }
3191
3192 /* 1. Last in item should be NULL as range is not supported.
3193  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3194  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3195  * 3. Mask of fields which need to be matched should be
3196  *    filled with 1.
3197  * 4. Mask of fields which needn't to be matched should be
3198  *    filled with 0.
3199  */
3200 static int
3201 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3202                               const struct rte_flow_item *pattern,
3203                               struct rte_flow_error *error,
3204                               struct i40e_tunnel_filter_conf *filter)
3205 {
3206         const struct rte_flow_item *item = pattern;
3207         const struct rte_flow_item_eth *eth_spec;
3208         const struct rte_flow_item_eth *eth_mask;
3209         const struct rte_flow_item_vxlan *vxlan_spec;
3210         const struct rte_flow_item_vxlan *vxlan_mask;
3211         const struct rte_flow_item_vlan *vlan_spec;
3212         const struct rte_flow_item_vlan *vlan_mask;
3213         uint8_t filter_type = 0;
3214         bool is_vni_masked = 0;
3215         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3216         enum rte_flow_item_type item_type;
3217         bool vxlan_flag = 0;
3218         uint32_t tenant_id_be = 0;
3219         int ret;
3220
3221         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3222                 if (item->last) {
3223                         rte_flow_error_set(error, EINVAL,
3224                                            RTE_FLOW_ERROR_TYPE_ITEM,
3225                                            item,
3226                                            "Not support range");
3227                         return -rte_errno;
3228                 }
3229                 item_type = item->type;
3230                 switch (item_type) {
3231                 case RTE_FLOW_ITEM_TYPE_ETH:
3232                         eth_spec = item->spec;
3233                         eth_mask = item->mask;
3234
3235                         /* Check if ETH item is used for place holder.
3236                          * If yes, both spec and mask should be NULL.
3237                          * If no, both spec and mask shouldn't be NULL.
3238                          */
3239                         if ((!eth_spec && eth_mask) ||
3240                             (eth_spec && !eth_mask)) {
3241                                 rte_flow_error_set(error, EINVAL,
3242                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3243                                                    item,
3244                                                    "Invalid ether spec/mask");
3245                                 return -rte_errno;
3246                         }
3247
3248                         if (eth_spec && eth_mask) {
3249                                 /* DST address of inner MAC shouldn't be masked.
3250                                  * SRC address of Inner MAC should be masked.
3251                                  */
3252                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3253                                     !is_zero_ether_addr(&eth_mask->src) ||
3254                                     eth_mask->type) {
3255                                         rte_flow_error_set(error, EINVAL,
3256                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3257                                                    item,
3258                                                    "Invalid ether spec/mask");
3259                                         return -rte_errno;
3260                                 }
3261
3262                                 if (!vxlan_flag) {
3263                                         rte_memcpy(&filter->outer_mac,
3264                                                    &eth_spec->dst,
3265                                                    ETHER_ADDR_LEN);
3266                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3267                                 } else {
3268                                         rte_memcpy(&filter->inner_mac,
3269                                                    &eth_spec->dst,
3270                                                    ETHER_ADDR_LEN);
3271                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3272                                 }
3273                         }
3274                         break;
3275                 case RTE_FLOW_ITEM_TYPE_VLAN:
3276                         vlan_spec = item->spec;
3277                         vlan_mask = item->mask;
3278                         if (!(vlan_spec && vlan_mask)) {
3279                                 rte_flow_error_set(error, EINVAL,
3280                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3281                                                    item,
3282                                                    "Invalid vlan item");
3283                                 return -rte_errno;
3284                         }
3285
3286                         if (vlan_spec && vlan_mask) {
3287                                 if (vlan_mask->tci ==
3288                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3289                                         filter->inner_vlan =
3290                                               rte_be_to_cpu_16(vlan_spec->tci) &
3291                                               I40E_TCI_MASK;
3292                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3293                         }
3294                         break;
3295                 case RTE_FLOW_ITEM_TYPE_IPV4:
3296                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3297                         /* IPv4 is used to describe protocol,
3298                          * spec and mask should be NULL.
3299                          */
3300                         if (item->spec || item->mask) {
3301                                 rte_flow_error_set(error, EINVAL,
3302                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3303                                                    item,
3304                                                    "Invalid IPv4 item");
3305                                 return -rte_errno;
3306                         }
3307                         break;
3308                 case RTE_FLOW_ITEM_TYPE_IPV6:
3309                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3310                         /* IPv6 is used to describe protocol,
3311                          * spec and mask should be NULL.
3312                          */
3313                         if (item->spec || item->mask) {
3314                                 rte_flow_error_set(error, EINVAL,
3315                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3316                                                    item,
3317                                                    "Invalid IPv6 item");
3318                                 return -rte_errno;
3319                         }
3320                         break;
3321                 case RTE_FLOW_ITEM_TYPE_UDP:
3322                         /* UDP is used to describe protocol,
3323                          * spec and mask should be NULL.
3324                          */
3325                         if (item->spec || item->mask) {
3326                                 rte_flow_error_set(error, EINVAL,
3327                                            RTE_FLOW_ERROR_TYPE_ITEM,
3328                                            item,
3329                                            "Invalid UDP item");
3330                                 return -rte_errno;
3331                         }
3332                         break;
3333                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3334                         vxlan_spec = item->spec;
3335                         vxlan_mask = item->mask;
3336                         /* Check if VXLAN item is used to describe protocol.
3337                          * If yes, both spec and mask should be NULL.
3338                          * If no, both spec and mask shouldn't be NULL.
3339                          */
3340                         if ((!vxlan_spec && vxlan_mask) ||
3341                             (vxlan_spec && !vxlan_mask)) {
3342                                 rte_flow_error_set(error, EINVAL,
3343                                            RTE_FLOW_ERROR_TYPE_ITEM,
3344                                            item,
3345                                            "Invalid VXLAN item");
3346                                 return -rte_errno;
3347                         }
3348
3349                         /* Check if VNI is masked. */
3350                         if (vxlan_spec && vxlan_mask) {
3351                                 is_vni_masked =
3352                                         !!memcmp(vxlan_mask->vni, vni_mask,
3353                                                  RTE_DIM(vni_mask));
3354                                 if (is_vni_masked) {
3355                                         rte_flow_error_set(error, EINVAL,
3356                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3357                                                    item,
3358                                                    "Invalid VNI mask");
3359                                         return -rte_errno;
3360                                 }
3361
3362                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3363                                            vxlan_spec->vni, 3);
3364                                 filter->tenant_id =
3365                                         rte_be_to_cpu_32(tenant_id_be);
3366                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3367                         }
3368
3369                         vxlan_flag = 1;
3370                         break;
3371                 default:
3372                         break;
3373                 }
3374         }
3375
3376         ret = i40e_check_tunnel_filter_type(filter_type);
3377         if (ret < 0) {
3378                 rte_flow_error_set(error, EINVAL,
3379                                    RTE_FLOW_ERROR_TYPE_ITEM,
3380                                    NULL,
3381                                    "Invalid filter type");
3382                 return -rte_errno;
3383         }
3384         filter->filter_type = filter_type;
3385
3386         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3387
3388         return 0;
3389 }
3390
3391 static int
3392 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3393                              const struct rte_flow_attr *attr,
3394                              const struct rte_flow_item pattern[],
3395                              const struct rte_flow_action actions[],
3396                              struct rte_flow_error *error,
3397                              union i40e_filter_t *filter)
3398 {
3399         struct i40e_tunnel_filter_conf *tunnel_filter =
3400                 &filter->consistent_tunnel_filter;
3401         int ret;
3402
3403         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3404                                             error, tunnel_filter);
3405         if (ret)
3406                 return ret;
3407
3408         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3409         if (ret)
3410                 return ret;
3411
3412         ret = i40e_flow_parse_attr(attr, error);
3413         if (ret)
3414                 return ret;
3415
3416         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3417
3418         return ret;
3419 }
3420
3421 /* 1. Last in item should be NULL as range is not supported.
3422  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3423  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3424  * 3. Mask of fields which need to be matched should be
3425  *    filled with 1.
3426  * 4. Mask of fields which needn't to be matched should be
3427  *    filled with 0.
3428  */
3429 static int
3430 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3431                               const struct rte_flow_item *pattern,
3432                               struct rte_flow_error *error,
3433                               struct i40e_tunnel_filter_conf *filter)
3434 {
3435         const struct rte_flow_item *item = pattern;
3436         const struct rte_flow_item_eth *eth_spec;
3437         const struct rte_flow_item_eth *eth_mask;
3438         const struct rte_flow_item_nvgre *nvgre_spec;
3439         const struct rte_flow_item_nvgre *nvgre_mask;
3440         const struct rte_flow_item_vlan *vlan_spec;
3441         const struct rte_flow_item_vlan *vlan_mask;
3442         enum rte_flow_item_type item_type;
3443         uint8_t filter_type = 0;
3444         bool is_tni_masked = 0;
3445         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3446         bool nvgre_flag = 0;
3447         uint32_t tenant_id_be = 0;
3448         int ret;
3449
3450         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3451                 if (item->last) {
3452                         rte_flow_error_set(error, EINVAL,
3453                                            RTE_FLOW_ERROR_TYPE_ITEM,
3454                                            item,
3455                                            "Not support range");
3456                         return -rte_errno;
3457                 }
3458                 item_type = item->type;
3459                 switch (item_type) {
3460                 case RTE_FLOW_ITEM_TYPE_ETH:
3461                         eth_spec = item->spec;
3462                         eth_mask = item->mask;
3463
3464                         /* Check if ETH item is used for place holder.
3465                          * If yes, both spec and mask should be NULL.
3466                          * If no, both spec and mask shouldn't be NULL.
3467                          */
3468                         if ((!eth_spec && eth_mask) ||
3469                             (eth_spec && !eth_mask)) {
3470                                 rte_flow_error_set(error, EINVAL,
3471                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3472                                                    item,
3473                                                    "Invalid ether spec/mask");
3474                                 return -rte_errno;
3475                         }
3476
3477                         if (eth_spec && eth_mask) {
3478                                 /* DST address of inner MAC shouldn't be masked.
3479                                  * SRC address of Inner MAC should be masked.
3480                                  */
3481                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3482                                     !is_zero_ether_addr(&eth_mask->src) ||
3483                                     eth_mask->type) {
3484                                         rte_flow_error_set(error, EINVAL,
3485                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3486                                                    item,
3487                                                    "Invalid ether spec/mask");
3488                                         return -rte_errno;
3489                                 }
3490
3491                                 if (!nvgre_flag) {
3492                                         rte_memcpy(&filter->outer_mac,
3493                                                    &eth_spec->dst,
3494                                                    ETHER_ADDR_LEN);
3495                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3496                                 } else {
3497                                         rte_memcpy(&filter->inner_mac,
3498                                                    &eth_spec->dst,
3499                                                    ETHER_ADDR_LEN);
3500                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3501                                 }
3502                         }
3503
3504                         break;
3505                 case RTE_FLOW_ITEM_TYPE_VLAN:
3506                         vlan_spec = item->spec;
3507                         vlan_mask = item->mask;
3508                         if (!(vlan_spec && vlan_mask)) {
3509                                 rte_flow_error_set(error, EINVAL,
3510                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3511                                                    item,
3512                                                    "Invalid vlan item");
3513                                 return -rte_errno;
3514                         }
3515
3516                         if (vlan_spec && vlan_mask) {
3517                                 if (vlan_mask->tci ==
3518                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3519                                         filter->inner_vlan =
3520                                               rte_be_to_cpu_16(vlan_spec->tci) &
3521                                               I40E_TCI_MASK;
3522                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3523                         }
3524                         break;
3525                 case RTE_FLOW_ITEM_TYPE_IPV4:
3526                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3527                         /* IPv4 is used to describe protocol,
3528                          * spec and mask should be NULL.
3529                          */
3530                         if (item->spec || item->mask) {
3531                                 rte_flow_error_set(error, EINVAL,
3532                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3533                                                    item,
3534                                                    "Invalid IPv4 item");
3535                                 return -rte_errno;
3536                         }
3537                         break;
3538                 case RTE_FLOW_ITEM_TYPE_IPV6:
3539                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3540                         /* IPv6 is used to describe protocol,
3541                          * spec and mask should be NULL.
3542                          */
3543                         if (item->spec || item->mask) {
3544                                 rte_flow_error_set(error, EINVAL,
3545                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3546                                                    item,
3547                                                    "Invalid IPv6 item");
3548                                 return -rte_errno;
3549                         }
3550                         break;
3551                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3552                         nvgre_spec = item->spec;
3553                         nvgre_mask = item->mask;
3554                         /* Check if NVGRE item is used to describe protocol.
3555                          * If yes, both spec and mask should be NULL.
3556                          * If no, both spec and mask shouldn't be NULL.
3557                          */
3558                         if ((!nvgre_spec && nvgre_mask) ||
3559                             (nvgre_spec && !nvgre_mask)) {
3560                                 rte_flow_error_set(error, EINVAL,
3561                                            RTE_FLOW_ERROR_TYPE_ITEM,
3562                                            item,
3563                                            "Invalid NVGRE item");
3564                                 return -rte_errno;
3565                         }
3566
3567                         if (nvgre_spec && nvgre_mask) {
3568                                 is_tni_masked =
3569                                         !!memcmp(nvgre_mask->tni, tni_mask,
3570                                                  RTE_DIM(tni_mask));
3571                                 if (is_tni_masked) {
3572                                         rte_flow_error_set(error, EINVAL,
3573                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3574                                                        item,
3575                                                        "Invalid TNI mask");
3576                                         return -rte_errno;
3577                                 }
3578                                 if (nvgre_mask->protocol &&
3579                                         nvgre_mask->protocol != 0xFFFF) {
3580                                         rte_flow_error_set(error, EINVAL,
3581                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3582                                                 item,
3583                                                 "Invalid NVGRE item");
3584                                         return -rte_errno;
3585                                 }
3586                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3587                                         nvgre_mask->c_k_s_rsvd0_ver !=
3588                                         rte_cpu_to_be_16(0xFFFF)) {
3589                                         rte_flow_error_set(error, EINVAL,
3590                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3591                                                    item,
3592                                                    "Invalid NVGRE item");
3593                                         return -rte_errno;
3594                                 }
3595                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3596                                         rte_cpu_to_be_16(0x2000) &&
3597                                         nvgre_mask->c_k_s_rsvd0_ver) {
3598                                         rte_flow_error_set(error, EINVAL,
3599                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3600                                                    item,
3601                                                    "Invalid NVGRE item");
3602                                         return -rte_errno;
3603                                 }
3604                                 if (nvgre_mask->protocol &&
3605                                         nvgre_spec->protocol !=
3606                                         rte_cpu_to_be_16(0x6558)) {
3607                                         rte_flow_error_set(error, EINVAL,
3608                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3609                                                    item,
3610                                                    "Invalid NVGRE item");
3611                                         return -rte_errno;
3612                                 }
3613                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3614                                            nvgre_spec->tni, 3);
3615                                 filter->tenant_id =
3616                                         rte_be_to_cpu_32(tenant_id_be);
3617                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3618                         }
3619
3620                         nvgre_flag = 1;
3621                         break;
3622                 default:
3623                         break;
3624                 }
3625         }
3626
3627         ret = i40e_check_tunnel_filter_type(filter_type);
3628         if (ret < 0) {
3629                 rte_flow_error_set(error, EINVAL,
3630                                    RTE_FLOW_ERROR_TYPE_ITEM,
3631                                    NULL,
3632                                    "Invalid filter type");
3633                 return -rte_errno;
3634         }
3635         filter->filter_type = filter_type;
3636
3637         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3638
3639         return 0;
3640 }
3641
3642 static int
3643 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3644                              const struct rte_flow_attr *attr,
3645                              const struct rte_flow_item pattern[],
3646                              const struct rte_flow_action actions[],
3647                              struct rte_flow_error *error,
3648                              union i40e_filter_t *filter)
3649 {
3650         struct i40e_tunnel_filter_conf *tunnel_filter =
3651                 &filter->consistent_tunnel_filter;
3652         int ret;
3653
3654         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3655                                             error, tunnel_filter);
3656         if (ret)
3657                 return ret;
3658
3659         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3660         if (ret)
3661                 return ret;
3662
3663         ret = i40e_flow_parse_attr(attr, error);
3664         if (ret)
3665                 return ret;
3666
3667         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3668
3669         return ret;
3670 }
3671
3672 /* 1. Last in item should be NULL as range is not supported.
3673  * 2. Supported filter types: MPLS label.
3674  * 3. Mask of fields which need to be matched should be
3675  *    filled with 1.
3676  * 4. Mask of fields which needn't to be matched should be
3677  *    filled with 0.
3678  */
3679 static int
3680 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3681                              const struct rte_flow_item *pattern,
3682                              struct rte_flow_error *error,
3683                              struct i40e_tunnel_filter_conf *filter)
3684 {
3685         const struct rte_flow_item *item = pattern;
3686         const struct rte_flow_item_mpls *mpls_spec;
3687         const struct rte_flow_item_mpls *mpls_mask;
3688         enum rte_flow_item_type item_type;
3689         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3690         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3691         uint32_t label_be = 0;
3692
3693         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3694                 if (item->last) {
3695                         rte_flow_error_set(error, EINVAL,
3696                                            RTE_FLOW_ERROR_TYPE_ITEM,
3697                                            item,
3698                                            "Not support range");
3699                         return -rte_errno;
3700                 }
3701                 item_type = item->type;
3702                 switch (item_type) {
3703                 case RTE_FLOW_ITEM_TYPE_ETH:
3704                         if (item->spec || item->mask) {
3705                                 rte_flow_error_set(error, EINVAL,
3706                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3707                                                    item,
3708                                                    "Invalid ETH item");
3709                                 return -rte_errno;
3710                         }
3711                         break;
3712                 case RTE_FLOW_ITEM_TYPE_IPV4:
3713                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3714                         /* IPv4 is used to describe protocol,
3715                          * spec and mask should be NULL.
3716                          */
3717                         if (item->spec || item->mask) {
3718                                 rte_flow_error_set(error, EINVAL,
3719                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3720                                                    item,
3721                                                    "Invalid IPv4 item");
3722                                 return -rte_errno;
3723                         }
3724                         break;
3725                 case RTE_FLOW_ITEM_TYPE_IPV6:
3726                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3727                         /* IPv6 is used to describe protocol,
3728                          * spec and mask should be NULL.
3729                          */
3730                         if (item->spec || item->mask) {
3731                                 rte_flow_error_set(error, EINVAL,
3732                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3733                                                    item,
3734                                                    "Invalid IPv6 item");
3735                                 return -rte_errno;
3736                         }
3737                         break;
3738                 case RTE_FLOW_ITEM_TYPE_UDP:
3739                         /* UDP is used to describe protocol,
3740                          * spec and mask should be NULL.
3741                          */
3742                         if (item->spec || item->mask) {
3743                                 rte_flow_error_set(error, EINVAL,
3744                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3745                                                    item,
3746                                                    "Invalid UDP item");
3747                                 return -rte_errno;
3748                         }
3749                         is_mplsoudp = 1;
3750                         break;
3751                 case RTE_FLOW_ITEM_TYPE_GRE:
3752                         /* GRE is used to describe protocol,
3753                          * spec and mask should be NULL.
3754                          */
3755                         if (item->spec || item->mask) {
3756                                 rte_flow_error_set(error, EINVAL,
3757                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3758                                                    item,
3759                                                    "Invalid GRE item");
3760                                 return -rte_errno;
3761                         }
3762                         break;
3763                 case RTE_FLOW_ITEM_TYPE_MPLS:
3764                         mpls_spec = item->spec;
3765                         mpls_mask = item->mask;
3766
3767                         if (!mpls_spec || !mpls_mask) {
3768                                 rte_flow_error_set(error, EINVAL,
3769                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3770                                                    item,
3771                                                    "Invalid MPLS item");
3772                                 return -rte_errno;
3773                         }
3774
3775                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3776                                 rte_flow_error_set(error, EINVAL,
3777                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3778                                                    item,
3779                                                    "Invalid MPLS label mask");
3780                                 return -rte_errno;
3781                         }
3782                         rte_memcpy(((uint8_t *)&label_be + 1),
3783                                    mpls_spec->label_tc_s, 3);
3784                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3785                         break;
3786                 default:
3787                         break;
3788                 }
3789         }
3790
3791         if (is_mplsoudp)
3792                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3793         else
3794                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3795
3796         return 0;
3797 }
3798
3799 static int
3800 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3801                             const struct rte_flow_attr *attr,
3802                             const struct rte_flow_item pattern[],
3803                             const struct rte_flow_action actions[],
3804                             struct rte_flow_error *error,
3805                             union i40e_filter_t *filter)
3806 {
3807         struct i40e_tunnel_filter_conf *tunnel_filter =
3808                 &filter->consistent_tunnel_filter;
3809         int ret;
3810
3811         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3812                                            error, tunnel_filter);
3813         if (ret)
3814                 return ret;
3815
3816         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3817         if (ret)
3818                 return ret;
3819
3820         ret = i40e_flow_parse_attr(attr, error);
3821         if (ret)
3822                 return ret;
3823
3824         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3825
3826         return ret;
3827 }
3828
3829 /* 1. Last in item should be NULL as range is not supported.
3830  * 2. Supported filter types: GTP TEID.
3831  * 3. Mask of fields which need to be matched should be
3832  *    filled with 1.
3833  * 4. Mask of fields which needn't to be matched should be
3834  *    filled with 0.
3835  * 5. GTP profile supports GTPv1 only.
3836  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3837  */
3838 static int
3839 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3840                             const struct rte_flow_item *pattern,
3841                             struct rte_flow_error *error,
3842                             struct i40e_tunnel_filter_conf *filter)
3843 {
3844         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3845         const struct rte_flow_item *item = pattern;
3846         const struct rte_flow_item_gtp *gtp_spec;
3847         const struct rte_flow_item_gtp *gtp_mask;
3848         enum rte_flow_item_type item_type;
3849
3850         if (!pf->gtp_support) {
3851                 rte_flow_error_set(error, EINVAL,
3852                                    RTE_FLOW_ERROR_TYPE_ITEM,
3853                                    item,
3854                                    "GTP is not supported by default.");
3855                 return -rte_errno;
3856         }
3857
3858         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3859                 if (item->last) {
3860                         rte_flow_error_set(error, EINVAL,
3861                                            RTE_FLOW_ERROR_TYPE_ITEM,
3862                                            item,
3863                                            "Not support range");
3864                         return -rte_errno;
3865                 }
3866                 item_type = item->type;
3867                 switch (item_type) {
3868                 case RTE_FLOW_ITEM_TYPE_ETH:
3869                         if (item->spec || item->mask) {
3870                                 rte_flow_error_set(error, EINVAL,
3871                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3872                                                    item,
3873                                                    "Invalid ETH item");
3874                                 return -rte_errno;
3875                         }
3876                         break;
3877                 case RTE_FLOW_ITEM_TYPE_IPV4:
3878                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3879                         /* IPv4 is used to describe protocol,
3880                          * spec and mask should be NULL.
3881                          */
3882                         if (item->spec || item->mask) {
3883                                 rte_flow_error_set(error, EINVAL,
3884                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3885                                                    item,
3886                                                    "Invalid IPv4 item");
3887                                 return -rte_errno;
3888                         }
3889                         break;
3890                 case RTE_FLOW_ITEM_TYPE_UDP:
3891                         if (item->spec || item->mask) {
3892                                 rte_flow_error_set(error, EINVAL,
3893                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3894                                                    item,
3895                                                    "Invalid UDP item");
3896                                 return -rte_errno;
3897                         }
3898                         break;
3899                 case RTE_FLOW_ITEM_TYPE_GTPC:
3900                 case RTE_FLOW_ITEM_TYPE_GTPU:
3901                         gtp_spec = item->spec;
3902                         gtp_mask = item->mask;
3903
3904                         if (!gtp_spec || !gtp_mask) {
3905                                 rte_flow_error_set(error, EINVAL,
3906                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3907                                                    item,
3908                                                    "Invalid GTP item");
3909                                 return -rte_errno;
3910                         }
3911
3912                         if (gtp_mask->v_pt_rsv_flags ||
3913                             gtp_mask->msg_type ||
3914                             gtp_mask->msg_len ||
3915                             gtp_mask->teid != UINT32_MAX) {
3916                                 rte_flow_error_set(error, EINVAL,
3917                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3918                                                    item,
3919                                                    "Invalid GTP mask");
3920                                 return -rte_errno;
3921                         }
3922
3923                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3924                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3925                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3926                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3927
3928                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3929
3930                         break;
3931                 default:
3932                         break;
3933                 }
3934         }
3935
3936         return 0;
3937 }
3938
3939 static int
3940 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3941                            const struct rte_flow_attr *attr,
3942                            const struct rte_flow_item pattern[],
3943                            const struct rte_flow_action actions[],
3944                            struct rte_flow_error *error,
3945                            union i40e_filter_t *filter)
3946 {
3947         struct i40e_tunnel_filter_conf *tunnel_filter =
3948                 &filter->consistent_tunnel_filter;
3949         int ret;
3950
3951         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3952                                           error, tunnel_filter);
3953         if (ret)
3954                 return ret;
3955
3956         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3957         if (ret)
3958                 return ret;
3959
3960         ret = i40e_flow_parse_attr(attr, error);
3961         if (ret)
3962                 return ret;
3963
3964         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3965
3966         return ret;
3967 }
3968
3969 /* 1. Last in item should be NULL as range is not supported.
3970  * 2. Supported filter types: QINQ.
3971  * 3. Mask of fields which need to be matched should be
3972  *    filled with 1.
3973  * 4. Mask of fields which needn't to be matched should be
3974  *    filled with 0.
3975  */
3976 static int
3977 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3978                               const struct rte_flow_item *pattern,
3979                               struct rte_flow_error *error,
3980                               struct i40e_tunnel_filter_conf *filter)
3981 {
3982         const struct rte_flow_item *item = pattern;
3983         const struct rte_flow_item_vlan *vlan_spec = NULL;
3984         const struct rte_flow_item_vlan *vlan_mask = NULL;
3985         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3986         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3987         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3988         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3989
3990         enum rte_flow_item_type item_type;
3991         bool vlan_flag = 0;
3992
3993         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3994                 if (item->last) {
3995                         rte_flow_error_set(error, EINVAL,
3996                                            RTE_FLOW_ERROR_TYPE_ITEM,
3997                                            item,
3998                                            "Not support range");
3999                         return -rte_errno;
4000                 }
4001                 item_type = item->type;
4002                 switch (item_type) {
4003                 case RTE_FLOW_ITEM_TYPE_ETH:
4004                         if (item->spec || item->mask) {
4005                                 rte_flow_error_set(error, EINVAL,
4006                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4007                                                    item,
4008                                                    "Invalid ETH item");
4009                                 return -rte_errno;
4010                         }
4011                         break;
4012                 case RTE_FLOW_ITEM_TYPE_VLAN:
4013                         vlan_spec = item->spec;
4014                         vlan_mask = item->mask;
4015
4016                         if (!(vlan_spec && vlan_mask)) {
4017                                 rte_flow_error_set(error, EINVAL,
4018                                            RTE_FLOW_ERROR_TYPE_ITEM,
4019                                            item,
4020                                            "Invalid vlan item");
4021                                 return -rte_errno;
4022                         }
4023
4024                         if (!vlan_flag) {
4025                                 o_vlan_spec = vlan_spec;
4026                                 o_vlan_mask = vlan_mask;
4027                                 vlan_flag = 1;
4028                         } else {
4029                                 i_vlan_spec = vlan_spec;
4030                                 i_vlan_mask = vlan_mask;
4031                                 vlan_flag = 0;
4032                         }
4033                         break;
4034
4035                 default:
4036                         break;
4037                 }
4038         }
4039
4040         /* Get filter specification */
4041         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4042                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4043                         (i_vlan_mask != NULL) &&
4044                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4045                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4046                         & I40E_TCI_MASK;
4047                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4048                         & I40E_TCI_MASK;
4049         } else {
4050                         rte_flow_error_set(error, EINVAL,
4051                                            RTE_FLOW_ERROR_TYPE_ITEM,
4052                                            NULL,
4053                                            "Invalid filter type");
4054                         return -rte_errno;
4055         }
4056
4057         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4058         return 0;
4059 }
4060
4061 static int
4062 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4063                               const struct rte_flow_attr *attr,
4064                               const struct rte_flow_item pattern[],
4065                               const struct rte_flow_action actions[],
4066                               struct rte_flow_error *error,
4067                               union i40e_filter_t *filter)
4068 {
4069         struct i40e_tunnel_filter_conf *tunnel_filter =
4070                 &filter->consistent_tunnel_filter;
4071         int ret;
4072
4073         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4074                                              error, tunnel_filter);
4075         if (ret)
4076                 return ret;
4077
4078         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4079         if (ret)
4080                 return ret;
4081
4082         ret = i40e_flow_parse_attr(attr, error);
4083         if (ret)
4084                 return ret;
4085
4086         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4087
4088         return ret;
4089 }
4090
4091 /**
4092  * This function is used to do configuration i40e existing RSS with rte_flow.
4093  * It also enable queue region configuration using flow API for i40e.
4094  * pattern can be used indicate what parameters will be include in flow,
4095  * like user_priority or flowtype for queue region or HASH function for RSS.
4096  * Action is used to transmit parameter like queue index and HASH
4097  * function for RSS, or flowtype for queue region configuration.
4098  * For example:
4099  * pattern:
4100  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4101  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4102  * Case 3: none, indicate RSS related will be parsed in action.
4103  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4104  * So, pattern choice is depened on the purpose of configuration of
4105  * that flow.
4106  * action:
4107  * action RSS will be uaed to transmit valid parameter with
4108  * struct rte_flow_action_rss for all the 3 case.
4109  */
4110 static int
4111 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4112                              const struct rte_flow_item *pattern,
4113                              struct rte_flow_error *error,
4114                              uint8_t *action_flag,
4115                              struct i40e_queue_regions *info)
4116 {
4117         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4118         const struct rte_flow_item *item = pattern;
4119         enum rte_flow_item_type item_type;
4120
4121         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4122                 return 0;
4123
4124         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4125                 if (item->last) {
4126                         rte_flow_error_set(error, EINVAL,
4127                                            RTE_FLOW_ERROR_TYPE_ITEM,
4128                                            item,
4129                                            "Not support range");
4130                         return -rte_errno;
4131                 }
4132                 item_type = item->type;
4133                 switch (item_type) {
4134                 case RTE_FLOW_ITEM_TYPE_ETH:
4135                         *action_flag = 1;
4136                         break;
4137                 case RTE_FLOW_ITEM_TYPE_VLAN:
4138                         vlan_spec = item->spec;
4139                         vlan_mask = item->mask;
4140                         if (vlan_spec && vlan_mask) {
4141                                 if (vlan_mask->tci ==
4142                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4143                                         info->region[0].user_priority[0] =
4144                                                 (vlan_spec->tci >> 13) & 0x7;
4145                                         info->region[0].user_priority_num = 1;
4146                                         info->queue_region_number = 1;
4147                                         *action_flag = 0;
4148                                 }
4149                         }
4150                         break;
4151                 default:
4152                         rte_flow_error_set(error, EINVAL,
4153                                         RTE_FLOW_ERROR_TYPE_ITEM,
4154                                         item,
4155                                         "Not support range");
4156                         return -rte_errno;
4157                 }
4158         }
4159
4160         return 0;
4161 }
4162
4163 static int
4164 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4165                             const struct rte_flow_action *actions,
4166                             struct rte_flow_error *error,
4167                             uint8_t action_flag,
4168                             struct i40e_queue_regions *conf_info,
4169                             union i40e_filter_t *filter)
4170 {
4171         const struct rte_flow_action *act;
4172         const struct rte_flow_action_rss *rss;
4173         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4174         struct i40e_queue_regions *info = &pf->queue_region;
4175         struct i40e_rte_flow_rss_conf *rss_config =
4176                         &filter->rss_conf;
4177         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4178         uint16_t i, j, n, tmp;
4179         uint32_t index = 0;
4180         uint64_t hf_bit = 1;
4181
4182         NEXT_ITEM_OF_ACTION(act, actions, index);
4183         rss = act->conf;
4184
4185         /**
4186          * rss only supports forwarding,
4187          * check if the first not void action is RSS.
4188          */
4189         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4190                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4191                 rte_flow_error_set(error, EINVAL,
4192                         RTE_FLOW_ERROR_TYPE_ACTION,
4193                         act, "Not supported action.");
4194                 return -rte_errno;
4195         }
4196
4197         if (action_flag) {
4198                 for (n = 0; n < 64; n++) {
4199                         if (rss->rss_conf->rss_hf & (hf_bit << n)) {
4200                                 conf_info->region[0].hw_flowtype[0] = n;
4201                                 conf_info->region[0].flowtype_num = 1;
4202                                 conf_info->queue_region_number = 1;
4203                                 break;
4204                         }
4205                 }
4206         }
4207
4208         for (n = 0; n < conf_info->queue_region_number; n++) {
4209                 if (conf_info->region[n].user_priority_num ||
4210                                 conf_info->region[n].flowtype_num) {
4211                         if (!((rte_is_power_of_2(rss->num)) &&
4212                                         rss->num <= 64)) {
4213                                 PMD_DRV_LOG(ERR, "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4214                                 "total number of queues do not exceed the VSI allocation");
4215                                 return -rte_errno;
4216                         }
4217
4218                         if (conf_info->region[n].user_priority[n] >=
4219                                         I40E_MAX_USER_PRIORITY) {
4220                                 PMD_DRV_LOG(ERR, "the user priority max index is 7");
4221                                 return -rte_errno;
4222                         }
4223
4224                         if (conf_info->region[n].hw_flowtype[n] >=
4225                                         I40E_FILTER_PCTYPE_MAX) {
4226                                 PMD_DRV_LOG(ERR, "the hw_flowtype or PCTYPE max index is 63");
4227                                 return -rte_errno;
4228                         }
4229
4230                         if (rss_info->num < rss->num ||
4231                                 rss_info->queue[0] < rss->queue[0] ||
4232                                 (rss->queue[0] + rss->num >
4233                                         rss_info->num + rss_info->queue[0])) {
4234                                 rte_flow_error_set(error, EINVAL,
4235                                         RTE_FLOW_ERROR_TYPE_ACTION,
4236                                         act,
4237                                         "no valid queues");
4238                                 return -rte_errno;
4239                         }
4240
4241                         for (i = 0; i < info->queue_region_number; i++) {
4242                                 if (info->region[i].queue_num == rss->num &&
4243                                         info->region[i].queue_start_index ==
4244                                                 rss->queue[0])
4245                                         break;
4246                         }
4247
4248                         if (i == info->queue_region_number) {
4249                                 if (i > I40E_REGION_MAX_INDEX) {
4250                                         PMD_DRV_LOG(ERR, "the queue region max index is 7");
4251                                         return -rte_errno;
4252                                 }
4253
4254                                 info->region[i].queue_num =
4255                                         rss->num;
4256                                 info->region[i].queue_start_index =
4257                                         rss->queue[0];
4258                                 info->region[i].region_id =
4259                                         info->queue_region_number;
4260
4261                                 j = info->region[i].user_priority_num;
4262                                 tmp = conf_info->region[n].user_priority[0];
4263                                 if (conf_info->region[n].user_priority_num) {
4264                                         info->region[i].user_priority[j] = tmp;
4265                                         info->region[i].user_priority_num++;
4266                                 }
4267
4268                                 j = info->region[i].flowtype_num;
4269                                 tmp = conf_info->region[n].hw_flowtype[0];
4270                                 if (conf_info->region[n].flowtype_num) {
4271                                         info->region[i].hw_flowtype[j] = tmp;
4272                                         info->region[i].flowtype_num++;
4273                                 }
4274                                 info->queue_region_number++;
4275                         } else {
4276                                 j = info->region[i].user_priority_num;
4277                                 tmp = conf_info->region[n].user_priority[0];
4278                                 if (conf_info->region[n].user_priority_num) {
4279                                         info->region[i].user_priority[j] = tmp;
4280                                         info->region[i].user_priority_num++;
4281                                 }
4282
4283                                 j = info->region[i].flowtype_num;
4284                                 tmp = conf_info->region[n].hw_flowtype[0];
4285                                 if (conf_info->region[n].flowtype_num) {
4286                                         info->region[i].hw_flowtype[j] = tmp;
4287                                         info->region[i].flowtype_num++;
4288                                 }
4289                         }
4290                 }
4291
4292                 rss_config->queue_region_conf = TRUE;
4293         }
4294
4295         if (rss_config->queue_region_conf)
4296                 return 0;
4297
4298         if (!rss || !rss->num) {
4299                 rte_flow_error_set(error, EINVAL,
4300                                 RTE_FLOW_ERROR_TYPE_ACTION,
4301                                 act,
4302                                 "no valid queues");
4303                 return -rte_errno;
4304         }
4305
4306         for (n = 0; n < rss->num; n++) {
4307                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4308                         rte_flow_error_set(error, EINVAL,
4309                                    RTE_FLOW_ERROR_TYPE_ACTION,
4310                                    act,
4311                                    "queue id > max number of queues");
4312                         return -rte_errno;
4313                 }
4314         }
4315         if (rss->rss_conf)
4316                 rss_config->rss_conf = *rss->rss_conf;
4317         else
4318                 rss_config->rss_conf.rss_hf =
4319                         pf->adapter->flow_types_mask;
4320
4321         for (n = 0; n < rss->num; ++n)
4322                 rss_config->queue[n] = rss->queue[n];
4323         rss_config->num = rss->num;
4324         index++;
4325
4326         /* check if the next not void action is END */
4327         NEXT_ITEM_OF_ACTION(act, actions, index);
4328         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4329                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4330                 rte_flow_error_set(error, EINVAL,
4331                         RTE_FLOW_ERROR_TYPE_ACTION,
4332                         act, "Not supported action.");
4333                 return -rte_errno;
4334         }
4335         rss_config->queue_region_conf = FALSE;
4336
4337         return 0;
4338 }
4339
4340 static int
4341 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4342                         const struct rte_flow_attr *attr,
4343                         const struct rte_flow_item pattern[],
4344                         const struct rte_flow_action actions[],
4345                         union i40e_filter_t *filter,
4346                         struct rte_flow_error *error)
4347 {
4348         int ret;
4349         struct i40e_queue_regions info;
4350         uint8_t action_flag = 0;
4351
4352         memset(&info, 0, sizeof(struct i40e_queue_regions));
4353
4354         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4355                                         error, &action_flag, &info);
4356         if (ret)
4357                 return ret;
4358
4359         ret = i40e_flow_parse_rss_action(dev, actions, error,
4360                                         action_flag, &info, filter);
4361         if (ret)
4362                 return ret;
4363
4364         ret = i40e_flow_parse_attr(attr, error);
4365         if (ret)
4366                 return ret;
4367
4368         cons_filter_type = RTE_ETH_FILTER_HASH;
4369
4370         return 0;
4371 }
4372
4373 static int
4374 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4375                 struct i40e_rte_flow_rss_conf *conf)
4376 {
4377         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4378         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4379
4380         if (conf->queue_region_conf) {
4381                 i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4382                 conf->queue_region_conf = 0;
4383         } else {
4384                 i40e_config_rss_filter(pf, conf, 1);
4385         }
4386         return 0;
4387 }
4388
4389 static int
4390 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4391                 struct i40e_rte_flow_rss_conf *conf)
4392 {
4393         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4394         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4395
4396         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4397
4398         i40e_config_rss_filter(pf, conf, 0);
4399         return 0;
4400 }
4401
4402 static int
4403 i40e_flow_validate(struct rte_eth_dev *dev,
4404                    const struct rte_flow_attr *attr,
4405                    const struct rte_flow_item pattern[],
4406                    const struct rte_flow_action actions[],
4407                    struct rte_flow_error *error)
4408 {
4409         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4410         parse_filter_t parse_filter;
4411         uint32_t item_num = 0; /* non-void item number of pattern*/
4412         uint32_t i = 0;
4413         bool flag = false;
4414         int ret = I40E_NOT_SUPPORTED;
4415
4416         if (!pattern) {
4417                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4418                                    NULL, "NULL pattern.");
4419                 return -rte_errno;
4420         }
4421
4422         if (!actions) {
4423                 rte_flow_error_set(error, EINVAL,
4424                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4425                                    NULL, "NULL action.");
4426                 return -rte_errno;
4427         }
4428
4429         if (!attr) {
4430                 rte_flow_error_set(error, EINVAL,
4431                                    RTE_FLOW_ERROR_TYPE_ATTR,
4432                                    NULL, "NULL attribute.");
4433                 return -rte_errno;
4434         }
4435
4436         memset(&cons_filter, 0, sizeof(cons_filter));
4437
4438         /* Get the non-void item of action */
4439         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4440                 i++;
4441
4442         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4443                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4444                                         actions, &cons_filter, error);
4445                 return ret;
4446         }
4447
4448         i = 0;
4449         /* Get the non-void item number of pattern */
4450         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4451                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4452                         item_num++;
4453                 i++;
4454         }
4455         item_num++;
4456
4457         items = rte_zmalloc("i40e_pattern",
4458                             item_num * sizeof(struct rte_flow_item), 0);
4459         if (!items) {
4460                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4461                                    NULL, "No memory for PMD internal items.");
4462                 return -ENOMEM;
4463         }
4464
4465         i40e_pattern_skip_void_item(items, pattern);
4466
4467         i = 0;
4468         do {
4469                 parse_filter = i40e_find_parse_filter_func(items, &i);
4470                 if (!parse_filter && !flag) {
4471                         rte_flow_error_set(error, EINVAL,
4472                                            RTE_FLOW_ERROR_TYPE_ITEM,
4473                                            pattern, "Unsupported pattern");
4474                         rte_free(items);
4475                         return -rte_errno;
4476                 }
4477                 if (parse_filter)
4478                         ret = parse_filter(dev, attr, items, actions,
4479                                            error, &cons_filter);
4480                 flag = true;
4481         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4482
4483         rte_free(items);
4484
4485         return ret;
4486 }
4487
4488 static struct rte_flow *
4489 i40e_flow_create(struct rte_eth_dev *dev,
4490                  const struct rte_flow_attr *attr,
4491                  const struct rte_flow_item pattern[],
4492                  const struct rte_flow_action actions[],
4493                  struct rte_flow_error *error)
4494 {
4495         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4496         struct rte_flow *flow;
4497         int ret;
4498
4499         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4500         if (!flow) {
4501                 rte_flow_error_set(error, ENOMEM,
4502                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4503                                    "Failed to allocate memory");
4504                 return flow;
4505         }
4506
4507         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4508         if (ret < 0)
4509                 return NULL;
4510
4511         switch (cons_filter_type) {
4512         case RTE_ETH_FILTER_ETHERTYPE:
4513                 ret = i40e_ethertype_filter_set(pf,
4514                                         &cons_filter.ethertype_filter, 1);
4515                 if (ret)
4516                         goto free_flow;
4517                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4518                                         i40e_ethertype_filter_list);
4519                 break;
4520         case RTE_ETH_FILTER_FDIR:
4521                 ret = i40e_flow_add_del_fdir_filter(dev,
4522                                        &cons_filter.fdir_filter, 1);
4523                 if (ret)
4524                         goto free_flow;
4525                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4526                                         i40e_fdir_filter_list);
4527                 break;
4528         case RTE_ETH_FILTER_TUNNEL:
4529                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4530                             &cons_filter.consistent_tunnel_filter, 1);
4531                 if (ret)
4532                         goto free_flow;
4533                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4534                                         i40e_tunnel_filter_list);
4535                 break;
4536         case RTE_ETH_FILTER_HASH:
4537                 ret = i40e_config_rss_filter_set(dev,
4538                             &cons_filter.rss_conf);
4539                 flow->rule = &pf->rss_info;
4540                 break;
4541         default:
4542                 goto free_flow;
4543         }
4544
4545         flow->filter_type = cons_filter_type;
4546         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4547         return flow;
4548
4549 free_flow:
4550         rte_flow_error_set(error, -ret,
4551                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4552                            "Failed to create flow.");
4553         rte_free(flow);
4554         return NULL;
4555 }
4556
4557 static int
4558 i40e_flow_destroy(struct rte_eth_dev *dev,
4559                   struct rte_flow *flow,
4560                   struct rte_flow_error *error)
4561 {
4562         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4563         enum rte_filter_type filter_type = flow->filter_type;
4564         int ret = 0;
4565
4566         switch (filter_type) {
4567         case RTE_ETH_FILTER_ETHERTYPE:
4568                 ret = i40e_flow_destroy_ethertype_filter(pf,
4569                          (struct i40e_ethertype_filter *)flow->rule);
4570                 break;
4571         case RTE_ETH_FILTER_TUNNEL:
4572                 ret = i40e_flow_destroy_tunnel_filter(pf,
4573                               (struct i40e_tunnel_filter *)flow->rule);
4574                 break;
4575         case RTE_ETH_FILTER_FDIR:
4576                 ret = i40e_flow_add_del_fdir_filter(dev,
4577                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4578                 break;
4579         case RTE_ETH_FILTER_HASH:
4580                 ret = i40e_config_rss_filter_del(dev,
4581                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4582                 break;
4583         default:
4584                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4585                             filter_type);
4586                 ret = -EINVAL;
4587                 break;
4588         }
4589
4590         if (!ret) {
4591                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4592                 rte_free(flow);
4593         } else
4594                 rte_flow_error_set(error, -ret,
4595                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4596                                    "Failed to destroy flow.");
4597
4598         return ret;
4599 }
4600
4601 static int
4602 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4603                                    struct i40e_ethertype_filter *filter)
4604 {
4605         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4606         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4607         struct i40e_ethertype_filter *node;
4608         struct i40e_control_filter_stats stats;
4609         uint16_t flags = 0;
4610         int ret = 0;
4611
4612         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4613                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4614         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4615                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4616         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4617
4618         memset(&stats, 0, sizeof(stats));
4619         ret = i40e_aq_add_rem_control_packet_filter(hw,
4620                                     filter->input.mac_addr.addr_bytes,
4621                                     filter->input.ether_type,
4622                                     flags, pf->main_vsi->seid,
4623                                     filter->queue, 0, &stats, NULL);
4624         if (ret < 0)
4625                 return ret;
4626
4627         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4628         if (!node)
4629                 return -EINVAL;
4630
4631         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4632
4633         return ret;
4634 }
4635
4636 static int
4637 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4638                                 struct i40e_tunnel_filter *filter)
4639 {
4640         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4641         struct i40e_vsi *vsi;
4642         struct i40e_pf_vf *vf;
4643         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4644         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4645         struct i40e_tunnel_filter *node;
4646         bool big_buffer = 0;
4647         int ret = 0;
4648
4649         memset(&cld_filter, 0, sizeof(cld_filter));
4650         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4651                         (struct ether_addr *)&cld_filter.element.outer_mac);
4652         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4653                         (struct ether_addr *)&cld_filter.element.inner_mac);
4654         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4655         cld_filter.element.flags = filter->input.flags;
4656         cld_filter.element.tenant_id = filter->input.tenant_id;
4657         cld_filter.element.queue_number = filter->queue;
4658         rte_memcpy(cld_filter.general_fields,
4659                    filter->input.general_fields,
4660                    sizeof(cld_filter.general_fields));
4661
4662         if (!filter->is_to_vf)
4663                 vsi = pf->main_vsi;
4664         else {
4665                 vf = &pf->vfs[filter->vf_id];
4666                 vsi = vf->vsi;
4667         }
4668
4669         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4670             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4671             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4672             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4673             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4674             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4675                 big_buffer = 1;
4676
4677         if (big_buffer)
4678                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4679                                                               &cld_filter, 1);
4680         else
4681                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4682                                                    &cld_filter.element, 1);
4683         if (ret < 0)
4684                 return -ENOTSUP;
4685
4686         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4687         if (!node)
4688                 return -EINVAL;
4689
4690         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4691
4692         return ret;
4693 }
4694
4695 static int
4696 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4697 {
4698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4699         int ret;
4700
4701         ret = i40e_flow_flush_fdir_filter(pf);
4702         if (ret) {
4703                 rte_flow_error_set(error, -ret,
4704                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4705                                    "Failed to flush FDIR flows.");
4706                 return -rte_errno;
4707         }
4708
4709         ret = i40e_flow_flush_ethertype_filter(pf);
4710         if (ret) {
4711                 rte_flow_error_set(error, -ret,
4712                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4713                                    "Failed to ethertype flush flows.");
4714                 return -rte_errno;
4715         }
4716
4717         ret = i40e_flow_flush_tunnel_filter(pf);
4718         if (ret) {
4719                 rte_flow_error_set(error, -ret,
4720                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4721                                    "Failed to flush tunnel flows.");
4722                 return -rte_errno;
4723         }
4724
4725         ret = i40e_flow_flush_rss_filter(dev);
4726         if (ret) {
4727                 rte_flow_error_set(error, -ret,
4728                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4729                                    "Failed to flush rss flows.");
4730                 return -rte_errno;
4731         }
4732
4733         return ret;
4734 }
4735
4736 static int
4737 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4738 {
4739         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4740         struct i40e_fdir_info *fdir_info = &pf->fdir;
4741         struct i40e_fdir_filter *fdir_filter;
4742         enum i40e_filter_pctype pctype;
4743         struct rte_flow *flow;
4744         void *temp;
4745         int ret;
4746
4747         ret = i40e_fdir_flush(dev);
4748         if (!ret) {
4749                 /* Delete FDIR filters in FDIR list. */
4750                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4751                         ret = i40e_sw_fdir_filter_del(pf,
4752                                                       &fdir_filter->fdir.input);
4753                         if (ret < 0)
4754                                 return ret;
4755                 }
4756
4757                 /* Delete FDIR flows in flow list. */
4758                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4759                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4760                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4761                                 rte_free(flow);
4762                         }
4763                 }
4764
4765                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4766                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4767                         pf->fdir.inset_flag[pctype] = 0;
4768         }
4769
4770         return ret;
4771 }
4772
4773 /* Flush all ethertype filters */
4774 static int
4775 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4776 {
4777         struct i40e_ethertype_filter_list
4778                 *ethertype_list = &pf->ethertype.ethertype_list;
4779         struct i40e_ethertype_filter *filter;
4780         struct rte_flow *flow;
4781         void *temp;
4782         int ret = 0;
4783
4784         while ((filter = TAILQ_FIRST(ethertype_list))) {
4785                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4786                 if (ret)
4787                         return ret;
4788         }
4789
4790         /* Delete ethertype flows in flow list. */
4791         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4792                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4793                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4794                         rte_free(flow);
4795                 }
4796         }
4797
4798         return ret;
4799 }
4800
4801 /* Flush all tunnel filters */
4802 static int
4803 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4804 {
4805         struct i40e_tunnel_filter_list
4806                 *tunnel_list = &pf->tunnel.tunnel_list;
4807         struct i40e_tunnel_filter *filter;
4808         struct rte_flow *flow;
4809         void *temp;
4810         int ret = 0;
4811
4812         while ((filter = TAILQ_FIRST(tunnel_list))) {
4813                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4814                 if (ret)
4815                         return ret;
4816         }
4817
4818         /* Delete tunnel flows in flow list. */
4819         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4820                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4821                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4822                         rte_free(flow);
4823                 }
4824         }
4825
4826         return ret;
4827 }
4828
4829 /* remove the rss filter */
4830 static int
4831 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4832 {
4833         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4834         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4835         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4836         int32_t ret = -EINVAL;
4837
4838         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4839
4840         if (rss_info->num)
4841                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
4842         return ret;
4843 }