drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_debug.h>
  14 #include <rte_ether.h>
  15 #include <rte_ethdev_driver.h>
  16 #include <rte_log.h>
  17 #include <rte_malloc.h>
  18 #include <rte_eth_ctrl.h>
  19 #include <rte_tailq.h>
  20 #include <rte_flow_driver.h>
  21
  22 #include "i40e_logs.h"
  23 #include "base/i40e_type.h"
  24 #include "base/i40e_prototype.h"
  25 #include "i40e_ethdev.h"
  26
  27 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  28 #define I40E_IPV6_FRAG_HEADER   44
  29 #define I40E_TENANT_ARRAY_NUM   3
  30 #define I40E_TCI_MASK           0xFFFF
  31
  32 static int i40e_flow_validate(struct rte_eth_dev *dev,
  33                               const struct rte_flow_attr *attr,
  34                               const struct rte_flow_item pattern[],
  35                               const struct rte_flow_action actions[],
  36                               struct rte_flow_error *error);
  37 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  38                                          const struct rte_flow_attr *attr,
  39                                          const struct rte_flow_item pattern[],
  40                                          const struct rte_flow_action actions[],
  41                                          struct rte_flow_error *error);
  42 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  43                              struct rte_flow *flow,
  44                              struct rte_flow_error *error);
  45 static int i40e_flow_flush(struct rte_eth_dev *dev,
  46                            struct rte_flow_error *error);
  47 static int
  48 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  49                                   const struct rte_flow_item *pattern,
  50                                   struct rte_flow_error *error,
  51                                   struct rte_eth_ethertype_filter *filter);
  52 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  53                                     const struct rte_flow_action *actions,
  54                                     struct rte_flow_error *error,
  55                                     struct rte_eth_ethertype_filter *filter);
  56 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  57                                         const struct rte_flow_item *pattern,
  58                                         struct rte_flow_error *error,
  59                                         struct i40e_fdir_filter_conf *filter);
  60 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  61                                        const struct rte_flow_action *actions,
  62                                        struct rte_flow_error *error,
  63                                        struct i40e_fdir_filter_conf *filter);
  64 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  65                                  const struct rte_flow_action *actions,
  66                                  struct rte_flow_error *error,
  67                                  struct i40e_tunnel_filter_conf *filter);
  68 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  69                                 struct rte_flow_error *error);
  70 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  71                                     const struct rte_flow_attr *attr,
  72                                     const struct rte_flow_item pattern[],
  73                                     const struct rte_flow_action actions[],
  74                                     struct rte_flow_error *error,
  75                                     union i40e_filter_t *filter);
  76 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  77                                        const struct rte_flow_attr *attr,
  78                                        const struct rte_flow_item pattern[],
  79                                        const struct rte_flow_action actions[],
  80                                        struct rte_flow_error *error,
  81                                        union i40e_filter_t *filter);
  82 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  83                                         const struct rte_flow_attr *attr,
  84                                         const struct rte_flow_item pattern[],
  85                                         const struct rte_flow_action actions[],
  86                                         struct rte_flow_error *error,
  87                                         union i40e_filter_t *filter);
  88 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  89                                         const struct rte_flow_attr *attr,
  90                                         const struct rte_flow_item pattern[],
  91                                         const struct rte_flow_action actions[],
  92                                         struct rte_flow_error *error,
  93                                         union i40e_filter_t *filter);
  94 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  95                                        const struct rte_flow_attr *attr,
  96                                        const struct rte_flow_item pattern[],
  97                                        const struct rte_flow_action actions[],
  98                                        struct rte_flow_error *error,
  99                                        union i40e_filter_t *filter);
 100 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 101                                       const struct rte_flow_attr *attr,
 102                                       const struct rte_flow_item pattern[],
 103                                       const struct rte_flow_action actions[],
 104                                       struct rte_flow_error *error,
 105                                       union i40e_filter_t *filter);
 106 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 107                                       struct i40e_ethertype_filter *filter);
 108 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 109                                            struct i40e_tunnel_filter *filter);
 110 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 112 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 113 static int
 114 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev);
 115 static int
 116 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 117                               const struct rte_flow_attr *attr,
 118                               const struct rte_flow_item pattern[],
 119                               const struct rte_flow_action actions[],
 120                               struct rte_flow_error *error,
 121                               union i40e_filter_t *filter);
 122 static int
 123 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 124                               const struct rte_flow_item *pattern,
 125                               struct rte_flow_error *error,
 126                               struct i40e_tunnel_filter_conf *filter);
 127
 128 const struct rte_flow_ops i40e_flow_ops = {
 129         .validate = i40e_flow_validate,
 130         .create = i40e_flow_create,
 131         .destroy = i40e_flow_destroy,
 132         .flush = i40e_flow_flush,
 133 };
 134
 135 union i40e_filter_t cons_filter;
 136 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 137
 138 /* Pattern matched ethertype filter */
 139 static enum rte_flow_item_type pattern_ethertype[] = {
 140         RTE_FLOW_ITEM_TYPE_ETH,
 141         RTE_FLOW_ITEM_TYPE_END,
 142 };
 143
 144 /* Pattern matched flow director filter */
 145 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 146         RTE_FLOW_ITEM_TYPE_ETH,
 147         RTE_FLOW_ITEM_TYPE_IPV4,
 148         RTE_FLOW_ITEM_TYPE_END,
 149 };
 150
 151 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 152         RTE_FLOW_ITEM_TYPE_ETH,
 153         RTE_FLOW_ITEM_TYPE_IPV4,
 154         RTE_FLOW_ITEM_TYPE_UDP,
 155         RTE_FLOW_ITEM_TYPE_END,
 156 };
 157
 158 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 159         RTE_FLOW_ITEM_TYPE_ETH,
 160         RTE_FLOW_ITEM_TYPE_IPV4,
 161         RTE_FLOW_ITEM_TYPE_TCP,
 162         RTE_FLOW_ITEM_TYPE_END,
 163 };
 164
 165 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 166         RTE_FLOW_ITEM_TYPE_ETH,
 167         RTE_FLOW_ITEM_TYPE_IPV4,
 168         RTE_FLOW_ITEM_TYPE_SCTP,
 169         RTE_FLOW_ITEM_TYPE_END,
 170 };
 171
 172 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 173         RTE_FLOW_ITEM_TYPE_ETH,
 174         RTE_FLOW_ITEM_TYPE_IPV4,
 175         RTE_FLOW_ITEM_TYPE_UDP,
 176         RTE_FLOW_ITEM_TYPE_GTPC,
 177         RTE_FLOW_ITEM_TYPE_END,
 178 };
 179
 180 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 181         RTE_FLOW_ITEM_TYPE_ETH,
 182         RTE_FLOW_ITEM_TYPE_IPV4,
 183         RTE_FLOW_ITEM_TYPE_UDP,
 184         RTE_FLOW_ITEM_TYPE_GTPU,
 185         RTE_FLOW_ITEM_TYPE_END,
 186 };
 187
 188 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 189         RTE_FLOW_ITEM_TYPE_ETH,
 190         RTE_FLOW_ITEM_TYPE_IPV4,
 191         RTE_FLOW_ITEM_TYPE_UDP,
 192         RTE_FLOW_ITEM_TYPE_GTPU,
 193         RTE_FLOW_ITEM_TYPE_IPV4,
 194         RTE_FLOW_ITEM_TYPE_END,
 195 };
 196
 197 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 198         RTE_FLOW_ITEM_TYPE_ETH,
 199         RTE_FLOW_ITEM_TYPE_IPV4,
 200         RTE_FLOW_ITEM_TYPE_UDP,
 201         RTE_FLOW_ITEM_TYPE_GTPU,
 202         RTE_FLOW_ITEM_TYPE_IPV6,
 203         RTE_FLOW_ITEM_TYPE_END,
 204 };
 205
 206 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 207         RTE_FLOW_ITEM_TYPE_ETH,
 208         RTE_FLOW_ITEM_TYPE_IPV6,
 209         RTE_FLOW_ITEM_TYPE_END,
 210 };
 211
 212 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 213         RTE_FLOW_ITEM_TYPE_ETH,
 214         RTE_FLOW_ITEM_TYPE_IPV6,
 215         RTE_FLOW_ITEM_TYPE_UDP,
 216         RTE_FLOW_ITEM_TYPE_END,
 217 };
 218
 219 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 220         RTE_FLOW_ITEM_TYPE_ETH,
 221         RTE_FLOW_ITEM_TYPE_IPV6,
 222         RTE_FLOW_ITEM_TYPE_TCP,
 223         RTE_FLOW_ITEM_TYPE_END,
 224 };
 225
 226 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 227         RTE_FLOW_ITEM_TYPE_ETH,
 228         RTE_FLOW_ITEM_TYPE_IPV6,
 229         RTE_FLOW_ITEM_TYPE_SCTP,
 230         RTE_FLOW_ITEM_TYPE_END,
 231 };
 232
 233 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 234         RTE_FLOW_ITEM_TYPE_ETH,
 235         RTE_FLOW_ITEM_TYPE_IPV6,
 236         RTE_FLOW_ITEM_TYPE_UDP,
 237         RTE_FLOW_ITEM_TYPE_GTPC,
 238         RTE_FLOW_ITEM_TYPE_END,
 239 };
 240
 241 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 242         RTE_FLOW_ITEM_TYPE_ETH,
 243         RTE_FLOW_ITEM_TYPE_IPV6,
 244         RTE_FLOW_ITEM_TYPE_UDP,
 245         RTE_FLOW_ITEM_TYPE_GTPU,
 246         RTE_FLOW_ITEM_TYPE_END,
 247 };
 248
 249 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 250         RTE_FLOW_ITEM_TYPE_ETH,
 251         RTE_FLOW_ITEM_TYPE_IPV6,
 252         RTE_FLOW_ITEM_TYPE_UDP,
 253         RTE_FLOW_ITEM_TYPE_GTPU,
 254         RTE_FLOW_ITEM_TYPE_IPV4,
 255         RTE_FLOW_ITEM_TYPE_END,
 256 };
 257
 258 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 259         RTE_FLOW_ITEM_TYPE_ETH,
 260         RTE_FLOW_ITEM_TYPE_IPV6,
 261         RTE_FLOW_ITEM_TYPE_UDP,
 262         RTE_FLOW_ITEM_TYPE_GTPU,
 263         RTE_FLOW_ITEM_TYPE_IPV6,
 264         RTE_FLOW_ITEM_TYPE_END,
 265 };
 266
 267 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 268         RTE_FLOW_ITEM_TYPE_ETH,
 269         RTE_FLOW_ITEM_TYPE_RAW,
 270         RTE_FLOW_ITEM_TYPE_END,
 271 };
 272
 273 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 274         RTE_FLOW_ITEM_TYPE_ETH,
 275         RTE_FLOW_ITEM_TYPE_RAW,
 276         RTE_FLOW_ITEM_TYPE_RAW,
 277         RTE_FLOW_ITEM_TYPE_END,
 278 };
 279
 280 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 281         RTE_FLOW_ITEM_TYPE_ETH,
 282         RTE_FLOW_ITEM_TYPE_RAW,
 283         RTE_FLOW_ITEM_TYPE_RAW,
 284         RTE_FLOW_ITEM_TYPE_RAW,
 285         RTE_FLOW_ITEM_TYPE_END,
 286 };
 287
 288 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 289         RTE_FLOW_ITEM_TYPE_ETH,
 290         RTE_FLOW_ITEM_TYPE_IPV4,
 291         RTE_FLOW_ITEM_TYPE_RAW,
 292         RTE_FLOW_ITEM_TYPE_END,
 293 };
 294
 295 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 296         RTE_FLOW_ITEM_TYPE_ETH,
 297         RTE_FLOW_ITEM_TYPE_IPV4,
 298         RTE_FLOW_ITEM_TYPE_RAW,
 299         RTE_FLOW_ITEM_TYPE_RAW,
 300         RTE_FLOW_ITEM_TYPE_END,
 301 };
 302
 303 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 304         RTE_FLOW_ITEM_TYPE_ETH,
 305         RTE_FLOW_ITEM_TYPE_IPV4,
 306         RTE_FLOW_ITEM_TYPE_RAW,
 307         RTE_FLOW_ITEM_TYPE_RAW,
 308         RTE_FLOW_ITEM_TYPE_RAW,
 309         RTE_FLOW_ITEM_TYPE_END,
 310 };
 311
 312 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 313         RTE_FLOW_ITEM_TYPE_ETH,
 314         RTE_FLOW_ITEM_TYPE_IPV4,
 315         RTE_FLOW_ITEM_TYPE_UDP,
 316         RTE_FLOW_ITEM_TYPE_RAW,
 317         RTE_FLOW_ITEM_TYPE_END,
 318 };
 319
 320 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 321         RTE_FLOW_ITEM_TYPE_ETH,
 322         RTE_FLOW_ITEM_TYPE_IPV4,
 323         RTE_FLOW_ITEM_TYPE_UDP,
 324         RTE_FLOW_ITEM_TYPE_RAW,
 325         RTE_FLOW_ITEM_TYPE_RAW,
 326         RTE_FLOW_ITEM_TYPE_END,
 327 };
 328
 329 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 330         RTE_FLOW_ITEM_TYPE_ETH,
 331         RTE_FLOW_ITEM_TYPE_IPV4,
 332         RTE_FLOW_ITEM_TYPE_UDP,
 333         RTE_FLOW_ITEM_TYPE_RAW,
 334         RTE_FLOW_ITEM_TYPE_RAW,
 335         RTE_FLOW_ITEM_TYPE_RAW,
 336         RTE_FLOW_ITEM_TYPE_END,
 337 };
 338
 339 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 340         RTE_FLOW_ITEM_TYPE_ETH,
 341         RTE_FLOW_ITEM_TYPE_IPV4,
 342         RTE_FLOW_ITEM_TYPE_TCP,
 343         RTE_FLOW_ITEM_TYPE_RAW,
 344         RTE_FLOW_ITEM_TYPE_END,
 345 };
 346
 347 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 348         RTE_FLOW_ITEM_TYPE_ETH,
 349         RTE_FLOW_ITEM_TYPE_IPV4,
 350         RTE_FLOW_ITEM_TYPE_TCP,
 351         RTE_FLOW_ITEM_TYPE_RAW,
 352         RTE_FLOW_ITEM_TYPE_RAW,
 353         RTE_FLOW_ITEM_TYPE_END,
 354 };
 355
 356 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 357         RTE_FLOW_ITEM_TYPE_ETH,
 358         RTE_FLOW_ITEM_TYPE_IPV4,
 359         RTE_FLOW_ITEM_TYPE_TCP,
 360         RTE_FLOW_ITEM_TYPE_RAW,
 361         RTE_FLOW_ITEM_TYPE_RAW,
 362         RTE_FLOW_ITEM_TYPE_RAW,
 363         RTE_FLOW_ITEM_TYPE_END,
 364 };
 365
 366 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 367         RTE_FLOW_ITEM_TYPE_ETH,
 368         RTE_FLOW_ITEM_TYPE_IPV4,
 369         RTE_FLOW_ITEM_TYPE_SCTP,
 370         RTE_FLOW_ITEM_TYPE_RAW,
 371         RTE_FLOW_ITEM_TYPE_END,
 372 };
 373
 374 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 375         RTE_FLOW_ITEM_TYPE_ETH,
 376         RTE_FLOW_ITEM_TYPE_IPV4,
 377         RTE_FLOW_ITEM_TYPE_SCTP,
 378         RTE_FLOW_ITEM_TYPE_RAW,
 379         RTE_FLOW_ITEM_TYPE_RAW,
 380         RTE_FLOW_ITEM_TYPE_END,
 381 };
 382
 383 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 384         RTE_FLOW_ITEM_TYPE_ETH,
 385         RTE_FLOW_ITEM_TYPE_IPV4,
 386         RTE_FLOW_ITEM_TYPE_SCTP,
 387         RTE_FLOW_ITEM_TYPE_RAW,
 388         RTE_FLOW_ITEM_TYPE_RAW,
 389         RTE_FLOW_ITEM_TYPE_RAW,
 390         RTE_FLOW_ITEM_TYPE_END,
 391 };
 392
 393 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 394         RTE_FLOW_ITEM_TYPE_ETH,
 395         RTE_FLOW_ITEM_TYPE_IPV6,
 396         RTE_FLOW_ITEM_TYPE_RAW,
 397         RTE_FLOW_ITEM_TYPE_END,
 398 };
 399
 400 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 401         RTE_FLOW_ITEM_TYPE_ETH,
 402         RTE_FLOW_ITEM_TYPE_IPV6,
 403         RTE_FLOW_ITEM_TYPE_RAW,
 404         RTE_FLOW_ITEM_TYPE_RAW,
 405         RTE_FLOW_ITEM_TYPE_END,
 406 };
 407
 408 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 409         RTE_FLOW_ITEM_TYPE_ETH,
 410         RTE_FLOW_ITEM_TYPE_IPV6,
 411         RTE_FLOW_ITEM_TYPE_RAW,
 412         RTE_FLOW_ITEM_TYPE_RAW,
 413         RTE_FLOW_ITEM_TYPE_RAW,
 414         RTE_FLOW_ITEM_TYPE_END,
 415 };
 416
 417 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 418         RTE_FLOW_ITEM_TYPE_ETH,
 419         RTE_FLOW_ITEM_TYPE_IPV6,
 420         RTE_FLOW_ITEM_TYPE_UDP,
 421         RTE_FLOW_ITEM_TYPE_RAW,
 422         RTE_FLOW_ITEM_TYPE_END,
 423 };
 424
 425 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 426         RTE_FLOW_ITEM_TYPE_ETH,
 427         RTE_FLOW_ITEM_TYPE_IPV6,
 428         RTE_FLOW_ITEM_TYPE_UDP,
 429         RTE_FLOW_ITEM_TYPE_RAW,
 430         RTE_FLOW_ITEM_TYPE_RAW,
 431         RTE_FLOW_ITEM_TYPE_END,
 432 };
 433
 434 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 435         RTE_FLOW_ITEM_TYPE_ETH,
 436         RTE_FLOW_ITEM_TYPE_IPV6,
 437         RTE_FLOW_ITEM_TYPE_UDP,
 438         RTE_FLOW_ITEM_TYPE_RAW,
 439         RTE_FLOW_ITEM_TYPE_RAW,
 440         RTE_FLOW_ITEM_TYPE_RAW,
 441         RTE_FLOW_ITEM_TYPE_END,
 442 };
 443
 444 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 445         RTE_FLOW_ITEM_TYPE_ETH,
 446         RTE_FLOW_ITEM_TYPE_IPV6,
 447         RTE_FLOW_ITEM_TYPE_TCP,
 448         RTE_FLOW_ITEM_TYPE_RAW,
 449         RTE_FLOW_ITEM_TYPE_END,
 450 };
 451
 452 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 453         RTE_FLOW_ITEM_TYPE_ETH,
 454         RTE_FLOW_ITEM_TYPE_IPV6,
 455         RTE_FLOW_ITEM_TYPE_TCP,
 456         RTE_FLOW_ITEM_TYPE_RAW,
 457         RTE_FLOW_ITEM_TYPE_RAW,
 458         RTE_FLOW_ITEM_TYPE_END,
 459 };
 460
 461 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 462         RTE_FLOW_ITEM_TYPE_ETH,
 463         RTE_FLOW_ITEM_TYPE_IPV6,
 464         RTE_FLOW_ITEM_TYPE_TCP,
 465         RTE_FLOW_ITEM_TYPE_RAW,
 466         RTE_FLOW_ITEM_TYPE_RAW,
 467         RTE_FLOW_ITEM_TYPE_RAW,
 468         RTE_FLOW_ITEM_TYPE_END,
 469 };
 470
 471 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 472         RTE_FLOW_ITEM_TYPE_ETH,
 473         RTE_FLOW_ITEM_TYPE_IPV6,
 474         RTE_FLOW_ITEM_TYPE_SCTP,
 475         RTE_FLOW_ITEM_TYPE_RAW,
 476         RTE_FLOW_ITEM_TYPE_END,
 477 };
 478
 479 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 480         RTE_FLOW_ITEM_TYPE_ETH,
 481         RTE_FLOW_ITEM_TYPE_IPV6,
 482         RTE_FLOW_ITEM_TYPE_SCTP,
 483         RTE_FLOW_ITEM_TYPE_RAW,
 484         RTE_FLOW_ITEM_TYPE_RAW,
 485         RTE_FLOW_ITEM_TYPE_END,
 486 };
 487
 488 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 489         RTE_FLOW_ITEM_TYPE_ETH,
 490         RTE_FLOW_ITEM_TYPE_IPV6,
 491         RTE_FLOW_ITEM_TYPE_SCTP,
 492         RTE_FLOW_ITEM_TYPE_RAW,
 493         RTE_FLOW_ITEM_TYPE_RAW,
 494         RTE_FLOW_ITEM_TYPE_RAW,
 495         RTE_FLOW_ITEM_TYPE_END,
 496 };
 497
 498 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 499         RTE_FLOW_ITEM_TYPE_ETH,
 500         RTE_FLOW_ITEM_TYPE_VLAN,
 501         RTE_FLOW_ITEM_TYPE_END,
 502 };
 503
 504 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 505         RTE_FLOW_ITEM_TYPE_ETH,
 506         RTE_FLOW_ITEM_TYPE_VLAN,
 507         RTE_FLOW_ITEM_TYPE_IPV4,
 508         RTE_FLOW_ITEM_TYPE_END,
 509 };
 510
 511 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 512         RTE_FLOW_ITEM_TYPE_ETH,
 513         RTE_FLOW_ITEM_TYPE_VLAN,
 514         RTE_FLOW_ITEM_TYPE_IPV4,
 515         RTE_FLOW_ITEM_TYPE_UDP,
 516         RTE_FLOW_ITEM_TYPE_END,
 517 };
 518
 519 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 520         RTE_FLOW_ITEM_TYPE_ETH,
 521         RTE_FLOW_ITEM_TYPE_VLAN,
 522         RTE_FLOW_ITEM_TYPE_IPV4,
 523         RTE_FLOW_ITEM_TYPE_TCP,
 524         RTE_FLOW_ITEM_TYPE_END,
 525 };
 526
 527 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 528         RTE_FLOW_ITEM_TYPE_ETH,
 529         RTE_FLOW_ITEM_TYPE_VLAN,
 530         RTE_FLOW_ITEM_TYPE_IPV4,
 531         RTE_FLOW_ITEM_TYPE_SCTP,
 532         RTE_FLOW_ITEM_TYPE_END,
 533 };
 534
 535 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 536         RTE_FLOW_ITEM_TYPE_ETH,
 537         RTE_FLOW_ITEM_TYPE_VLAN,
 538         RTE_FLOW_ITEM_TYPE_IPV6,
 539         RTE_FLOW_ITEM_TYPE_END,
 540 };
 541
 542 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 543         RTE_FLOW_ITEM_TYPE_ETH,
 544         RTE_FLOW_ITEM_TYPE_VLAN,
 545         RTE_FLOW_ITEM_TYPE_IPV6,
 546         RTE_FLOW_ITEM_TYPE_UDP,
 547         RTE_FLOW_ITEM_TYPE_END,
 548 };
 549
 550 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 551         RTE_FLOW_ITEM_TYPE_ETH,
 552         RTE_FLOW_ITEM_TYPE_VLAN,
 553         RTE_FLOW_ITEM_TYPE_IPV6,
 554         RTE_FLOW_ITEM_TYPE_TCP,
 555         RTE_FLOW_ITEM_TYPE_END,
 556 };
 557
 558 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 559         RTE_FLOW_ITEM_TYPE_ETH,
 560         RTE_FLOW_ITEM_TYPE_VLAN,
 561         RTE_FLOW_ITEM_TYPE_IPV6,
 562         RTE_FLOW_ITEM_TYPE_SCTP,
 563         RTE_FLOW_ITEM_TYPE_END,
 564 };
 565
 566 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 567         RTE_FLOW_ITEM_TYPE_ETH,
 568         RTE_FLOW_ITEM_TYPE_VLAN,
 569         RTE_FLOW_ITEM_TYPE_RAW,
 570         RTE_FLOW_ITEM_TYPE_END,
 571 };
 572
 573 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 574         RTE_FLOW_ITEM_TYPE_ETH,
 575         RTE_FLOW_ITEM_TYPE_VLAN,
 576         RTE_FLOW_ITEM_TYPE_RAW,
 577         RTE_FLOW_ITEM_TYPE_RAW,
 578         RTE_FLOW_ITEM_TYPE_END,
 579 };
 580
 581 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 582         RTE_FLOW_ITEM_TYPE_ETH,
 583         RTE_FLOW_ITEM_TYPE_VLAN,
 584         RTE_FLOW_ITEM_TYPE_RAW,
 585         RTE_FLOW_ITEM_TYPE_RAW,
 586         RTE_FLOW_ITEM_TYPE_RAW,
 587         RTE_FLOW_ITEM_TYPE_END,
 588 };
 589
 590 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 591         RTE_FLOW_ITEM_TYPE_ETH,
 592         RTE_FLOW_ITEM_TYPE_VLAN,
 593         RTE_FLOW_ITEM_TYPE_IPV4,
 594         RTE_FLOW_ITEM_TYPE_RAW,
 595         RTE_FLOW_ITEM_TYPE_END,
 596 };
 597
 598 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 599         RTE_FLOW_ITEM_TYPE_ETH,
 600         RTE_FLOW_ITEM_TYPE_VLAN,
 601         RTE_FLOW_ITEM_TYPE_IPV4,
 602         RTE_FLOW_ITEM_TYPE_RAW,
 603         RTE_FLOW_ITEM_TYPE_RAW,
 604         RTE_FLOW_ITEM_TYPE_END,
 605 };
 606
 607 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 608         RTE_FLOW_ITEM_TYPE_ETH,
 609         RTE_FLOW_ITEM_TYPE_VLAN,
 610         RTE_FLOW_ITEM_TYPE_IPV4,
 611         RTE_FLOW_ITEM_TYPE_RAW,
 612         RTE_FLOW_ITEM_TYPE_RAW,
 613         RTE_FLOW_ITEM_TYPE_RAW,
 614         RTE_FLOW_ITEM_TYPE_END,
 615 };
 616
 617 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 618         RTE_FLOW_ITEM_TYPE_ETH,
 619         RTE_FLOW_ITEM_TYPE_VLAN,
 620         RTE_FLOW_ITEM_TYPE_IPV4,
 621         RTE_FLOW_ITEM_TYPE_UDP,
 622         RTE_FLOW_ITEM_TYPE_RAW,
 623         RTE_FLOW_ITEM_TYPE_END,
 624 };
 625
 626 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 627         RTE_FLOW_ITEM_TYPE_ETH,
 628         RTE_FLOW_ITEM_TYPE_VLAN,
 629         RTE_FLOW_ITEM_TYPE_IPV4,
 630         RTE_FLOW_ITEM_TYPE_UDP,
 631         RTE_FLOW_ITEM_TYPE_RAW,
 632         RTE_FLOW_ITEM_TYPE_RAW,
 633         RTE_FLOW_ITEM_TYPE_END,
 634 };
 635
 636 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 637         RTE_FLOW_ITEM_TYPE_ETH,
 638         RTE_FLOW_ITEM_TYPE_VLAN,
 639         RTE_FLOW_ITEM_TYPE_IPV4,
 640         RTE_FLOW_ITEM_TYPE_UDP,
 641         RTE_FLOW_ITEM_TYPE_RAW,
 642         RTE_FLOW_ITEM_TYPE_RAW,
 643         RTE_FLOW_ITEM_TYPE_RAW,
 644         RTE_FLOW_ITEM_TYPE_END,
 645 };
 646
 647 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 648         RTE_FLOW_ITEM_TYPE_ETH,
 649         RTE_FLOW_ITEM_TYPE_VLAN,
 650         RTE_FLOW_ITEM_TYPE_IPV4,
 651         RTE_FLOW_ITEM_TYPE_TCP,
 652         RTE_FLOW_ITEM_TYPE_RAW,
 653         RTE_FLOW_ITEM_TYPE_END,
 654 };
 655
 656 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 657         RTE_FLOW_ITEM_TYPE_ETH,
 658         RTE_FLOW_ITEM_TYPE_VLAN,
 659         RTE_FLOW_ITEM_TYPE_IPV4,
 660         RTE_FLOW_ITEM_TYPE_TCP,
 661         RTE_FLOW_ITEM_TYPE_RAW,
 662         RTE_FLOW_ITEM_TYPE_RAW,
 663         RTE_FLOW_ITEM_TYPE_END,
 664 };
 665
 666 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 667         RTE_FLOW_ITEM_TYPE_ETH,
 668         RTE_FLOW_ITEM_TYPE_VLAN,
 669         RTE_FLOW_ITEM_TYPE_IPV4,
 670         RTE_FLOW_ITEM_TYPE_TCP,
 671         RTE_FLOW_ITEM_TYPE_RAW,
 672         RTE_FLOW_ITEM_TYPE_RAW,
 673         RTE_FLOW_ITEM_TYPE_RAW,
 674         RTE_FLOW_ITEM_TYPE_END,
 675 };
 676
 677 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 678         RTE_FLOW_ITEM_TYPE_ETH,
 679         RTE_FLOW_ITEM_TYPE_VLAN,
 680         RTE_FLOW_ITEM_TYPE_IPV4,
 681         RTE_FLOW_ITEM_TYPE_SCTP,
 682         RTE_FLOW_ITEM_TYPE_RAW,
 683         RTE_FLOW_ITEM_TYPE_END,
 684 };
 685
 686 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 687         RTE_FLOW_ITEM_TYPE_ETH,
 688         RTE_FLOW_ITEM_TYPE_VLAN,
 689         RTE_FLOW_ITEM_TYPE_IPV4,
 690         RTE_FLOW_ITEM_TYPE_SCTP,
 691         RTE_FLOW_ITEM_TYPE_RAW,
 692         RTE_FLOW_ITEM_TYPE_RAW,
 693         RTE_FLOW_ITEM_TYPE_END,
 694 };
 695
 696 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 697         RTE_FLOW_ITEM_TYPE_ETH,
 698         RTE_FLOW_ITEM_TYPE_VLAN,
 699         RTE_FLOW_ITEM_TYPE_IPV4,
 700         RTE_FLOW_ITEM_TYPE_SCTP,
 701         RTE_FLOW_ITEM_TYPE_RAW,
 702         RTE_FLOW_ITEM_TYPE_RAW,
 703         RTE_FLOW_ITEM_TYPE_RAW,
 704         RTE_FLOW_ITEM_TYPE_END,
 705 };
 706
 707 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 708         RTE_FLOW_ITEM_TYPE_ETH,
 709         RTE_FLOW_ITEM_TYPE_VLAN,
 710         RTE_FLOW_ITEM_TYPE_IPV6,
 711         RTE_FLOW_ITEM_TYPE_RAW,
 712         RTE_FLOW_ITEM_TYPE_END,
 713 };
 714
 715 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 716         RTE_FLOW_ITEM_TYPE_ETH,
 717         RTE_FLOW_ITEM_TYPE_VLAN,
 718         RTE_FLOW_ITEM_TYPE_IPV6,
 719         RTE_FLOW_ITEM_TYPE_RAW,
 720         RTE_FLOW_ITEM_TYPE_RAW,
 721         RTE_FLOW_ITEM_TYPE_END,
 722 };
 723
 724 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 725         RTE_FLOW_ITEM_TYPE_ETH,
 726         RTE_FLOW_ITEM_TYPE_VLAN,
 727         RTE_FLOW_ITEM_TYPE_IPV6,
 728         RTE_FLOW_ITEM_TYPE_RAW,
 729         RTE_FLOW_ITEM_TYPE_RAW,
 730         RTE_FLOW_ITEM_TYPE_RAW,
 731         RTE_FLOW_ITEM_TYPE_END,
 732 };
 733
 734 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 735         RTE_FLOW_ITEM_TYPE_ETH,
 736         RTE_FLOW_ITEM_TYPE_VLAN,
 737         RTE_FLOW_ITEM_TYPE_IPV6,
 738         RTE_FLOW_ITEM_TYPE_UDP,
 739         RTE_FLOW_ITEM_TYPE_RAW,
 740         RTE_FLOW_ITEM_TYPE_END,
 741 };
 742
 743 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 744         RTE_FLOW_ITEM_TYPE_ETH,
 745         RTE_FLOW_ITEM_TYPE_VLAN,
 746         RTE_FLOW_ITEM_TYPE_IPV6,
 747         RTE_FLOW_ITEM_TYPE_UDP,
 748         RTE_FLOW_ITEM_TYPE_RAW,
 749         RTE_FLOW_ITEM_TYPE_RAW,
 750         RTE_FLOW_ITEM_TYPE_END,
 751 };
 752
 753 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 754         RTE_FLOW_ITEM_TYPE_ETH,
 755         RTE_FLOW_ITEM_TYPE_VLAN,
 756         RTE_FLOW_ITEM_TYPE_IPV6,
 757         RTE_FLOW_ITEM_TYPE_UDP,
 758         RTE_FLOW_ITEM_TYPE_RAW,
 759         RTE_FLOW_ITEM_TYPE_RAW,
 760         RTE_FLOW_ITEM_TYPE_RAW,
 761         RTE_FLOW_ITEM_TYPE_END,
 762 };
 763
 764 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 765         RTE_FLOW_ITEM_TYPE_ETH,
 766         RTE_FLOW_ITEM_TYPE_VLAN,
 767         RTE_FLOW_ITEM_TYPE_IPV6,
 768         RTE_FLOW_ITEM_TYPE_TCP,
 769         RTE_FLOW_ITEM_TYPE_RAW,
 770         RTE_FLOW_ITEM_TYPE_END,
 771 };
 772
 773 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 774         RTE_FLOW_ITEM_TYPE_ETH,
 775         RTE_FLOW_ITEM_TYPE_VLAN,
 776         RTE_FLOW_ITEM_TYPE_IPV6,
 777         RTE_FLOW_ITEM_TYPE_TCP,
 778         RTE_FLOW_ITEM_TYPE_RAW,
 779         RTE_FLOW_ITEM_TYPE_RAW,
 780         RTE_FLOW_ITEM_TYPE_END,
 781 };
 782
 783 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 784         RTE_FLOW_ITEM_TYPE_ETH,
 785         RTE_FLOW_ITEM_TYPE_VLAN,
 786         RTE_FLOW_ITEM_TYPE_IPV6,
 787         RTE_FLOW_ITEM_TYPE_TCP,
 788         RTE_FLOW_ITEM_TYPE_RAW,
 789         RTE_FLOW_ITEM_TYPE_RAW,
 790         RTE_FLOW_ITEM_TYPE_RAW,
 791         RTE_FLOW_ITEM_TYPE_END,
 792 };
 793
 794 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 795         RTE_FLOW_ITEM_TYPE_ETH,
 796         RTE_FLOW_ITEM_TYPE_VLAN,
 797         RTE_FLOW_ITEM_TYPE_IPV6,
 798         RTE_FLOW_ITEM_TYPE_SCTP,
 799         RTE_FLOW_ITEM_TYPE_RAW,
 800         RTE_FLOW_ITEM_TYPE_END,
 801 };
 802
 803 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 804         RTE_FLOW_ITEM_TYPE_ETH,
 805         RTE_FLOW_ITEM_TYPE_VLAN,
 806         RTE_FLOW_ITEM_TYPE_IPV6,
 807         RTE_FLOW_ITEM_TYPE_SCTP,
 808         RTE_FLOW_ITEM_TYPE_RAW,
 809         RTE_FLOW_ITEM_TYPE_RAW,
 810         RTE_FLOW_ITEM_TYPE_END,
 811 };
 812
 813 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 814         RTE_FLOW_ITEM_TYPE_ETH,
 815         RTE_FLOW_ITEM_TYPE_VLAN,
 816         RTE_FLOW_ITEM_TYPE_IPV6,
 817         RTE_FLOW_ITEM_TYPE_SCTP,
 818         RTE_FLOW_ITEM_TYPE_RAW,
 819         RTE_FLOW_ITEM_TYPE_RAW,
 820         RTE_FLOW_ITEM_TYPE_RAW,
 821         RTE_FLOW_ITEM_TYPE_END,
 822 };
 823
 824 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 825         RTE_FLOW_ITEM_TYPE_ETH,
 826         RTE_FLOW_ITEM_TYPE_IPV4,
 827         RTE_FLOW_ITEM_TYPE_VF,
 828         RTE_FLOW_ITEM_TYPE_END,
 829 };
 830
 831 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 832         RTE_FLOW_ITEM_TYPE_ETH,
 833         RTE_FLOW_ITEM_TYPE_IPV4,
 834         RTE_FLOW_ITEM_TYPE_UDP,
 835         RTE_FLOW_ITEM_TYPE_VF,
 836         RTE_FLOW_ITEM_TYPE_END,
 837 };
 838
 839 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 840         RTE_FLOW_ITEM_TYPE_ETH,
 841         RTE_FLOW_ITEM_TYPE_IPV4,
 842         RTE_FLOW_ITEM_TYPE_TCP,
 843         RTE_FLOW_ITEM_TYPE_VF,
 844         RTE_FLOW_ITEM_TYPE_END,
 845 };
 846
 847 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 848         RTE_FLOW_ITEM_TYPE_ETH,
 849         RTE_FLOW_ITEM_TYPE_IPV4,
 850         RTE_FLOW_ITEM_TYPE_SCTP,
 851         RTE_FLOW_ITEM_TYPE_VF,
 852         RTE_FLOW_ITEM_TYPE_END,
 853 };
 854
 855 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 856         RTE_FLOW_ITEM_TYPE_ETH,
 857         RTE_FLOW_ITEM_TYPE_IPV6,
 858         RTE_FLOW_ITEM_TYPE_VF,
 859         RTE_FLOW_ITEM_TYPE_END,
 860 };
 861
 862 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 863         RTE_FLOW_ITEM_TYPE_ETH,
 864         RTE_FLOW_ITEM_TYPE_IPV6,
 865         RTE_FLOW_ITEM_TYPE_UDP,
 866         RTE_FLOW_ITEM_TYPE_VF,
 867         RTE_FLOW_ITEM_TYPE_END,
 868 };
 869
 870 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 871         RTE_FLOW_ITEM_TYPE_ETH,
 872         RTE_FLOW_ITEM_TYPE_IPV6,
 873         RTE_FLOW_ITEM_TYPE_TCP,
 874         RTE_FLOW_ITEM_TYPE_VF,
 875         RTE_FLOW_ITEM_TYPE_END,
 876 };
 877
 878 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 879         RTE_FLOW_ITEM_TYPE_ETH,
 880         RTE_FLOW_ITEM_TYPE_IPV6,
 881         RTE_FLOW_ITEM_TYPE_SCTP,
 882         RTE_FLOW_ITEM_TYPE_VF,
 883         RTE_FLOW_ITEM_TYPE_END,
 884 };
 885
 886 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 887         RTE_FLOW_ITEM_TYPE_ETH,
 888         RTE_FLOW_ITEM_TYPE_RAW,
 889         RTE_FLOW_ITEM_TYPE_VF,
 890         RTE_FLOW_ITEM_TYPE_END,
 891 };
 892
 893 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 894         RTE_FLOW_ITEM_TYPE_ETH,
 895         RTE_FLOW_ITEM_TYPE_RAW,
 896         RTE_FLOW_ITEM_TYPE_RAW,
 897         RTE_FLOW_ITEM_TYPE_VF,
 898         RTE_FLOW_ITEM_TYPE_END,
 899 };
 900
 901 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 902         RTE_FLOW_ITEM_TYPE_ETH,
 903         RTE_FLOW_ITEM_TYPE_RAW,
 904         RTE_FLOW_ITEM_TYPE_RAW,
 905         RTE_FLOW_ITEM_TYPE_RAW,
 906         RTE_FLOW_ITEM_TYPE_VF,
 907         RTE_FLOW_ITEM_TYPE_END,
 908 };
 909
 910 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 911         RTE_FLOW_ITEM_TYPE_ETH,
 912         RTE_FLOW_ITEM_TYPE_IPV4,
 913         RTE_FLOW_ITEM_TYPE_RAW,
 914         RTE_FLOW_ITEM_TYPE_VF,
 915         RTE_FLOW_ITEM_TYPE_END,
 916 };
 917
 918 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 919         RTE_FLOW_ITEM_TYPE_ETH,
 920         RTE_FLOW_ITEM_TYPE_IPV4,
 921         RTE_FLOW_ITEM_TYPE_RAW,
 922         RTE_FLOW_ITEM_TYPE_RAW,
 923         RTE_FLOW_ITEM_TYPE_VF,
 924         RTE_FLOW_ITEM_TYPE_END,
 925 };
 926
 927 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 928         RTE_FLOW_ITEM_TYPE_ETH,
 929         RTE_FLOW_ITEM_TYPE_IPV4,
 930         RTE_FLOW_ITEM_TYPE_RAW,
 931         RTE_FLOW_ITEM_TYPE_RAW,
 932         RTE_FLOW_ITEM_TYPE_RAW,
 933         RTE_FLOW_ITEM_TYPE_VF,
 934         RTE_FLOW_ITEM_TYPE_END,
 935 };
 936
 937 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 938         RTE_FLOW_ITEM_TYPE_ETH,
 939         RTE_FLOW_ITEM_TYPE_IPV4,
 940         RTE_FLOW_ITEM_TYPE_UDP,
 941         RTE_FLOW_ITEM_TYPE_RAW,
 942         RTE_FLOW_ITEM_TYPE_VF,
 943         RTE_FLOW_ITEM_TYPE_END,
 944 };
 945
 946 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 947         RTE_FLOW_ITEM_TYPE_ETH,
 948         RTE_FLOW_ITEM_TYPE_IPV4,
 949         RTE_FLOW_ITEM_TYPE_UDP,
 950         RTE_FLOW_ITEM_TYPE_RAW,
 951         RTE_FLOW_ITEM_TYPE_RAW,
 952         RTE_FLOW_ITEM_TYPE_VF,
 953         RTE_FLOW_ITEM_TYPE_END,
 954 };
 955
 956 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 957         RTE_FLOW_ITEM_TYPE_ETH,
 958         RTE_FLOW_ITEM_TYPE_IPV4,
 959         RTE_FLOW_ITEM_TYPE_UDP,
 960         RTE_FLOW_ITEM_TYPE_RAW,
 961         RTE_FLOW_ITEM_TYPE_RAW,
 962         RTE_FLOW_ITEM_TYPE_RAW,
 963         RTE_FLOW_ITEM_TYPE_VF,
 964         RTE_FLOW_ITEM_TYPE_END,
 965 };
 966
 967 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 968         RTE_FLOW_ITEM_TYPE_ETH,
 969         RTE_FLOW_ITEM_TYPE_IPV4,
 970         RTE_FLOW_ITEM_TYPE_TCP,
 971         RTE_FLOW_ITEM_TYPE_RAW,
 972         RTE_FLOW_ITEM_TYPE_VF,
 973         RTE_FLOW_ITEM_TYPE_END,
 974 };
 975
 976 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 977         RTE_FLOW_ITEM_TYPE_ETH,
 978         RTE_FLOW_ITEM_TYPE_IPV4,
 979         RTE_FLOW_ITEM_TYPE_TCP,
 980         RTE_FLOW_ITEM_TYPE_RAW,
 981         RTE_FLOW_ITEM_TYPE_RAW,
 982         RTE_FLOW_ITEM_TYPE_VF,
 983         RTE_FLOW_ITEM_TYPE_END,
 984 };
 985
 986 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 987         RTE_FLOW_ITEM_TYPE_ETH,
 988         RTE_FLOW_ITEM_TYPE_IPV4,
 989         RTE_FLOW_ITEM_TYPE_TCP,
 990         RTE_FLOW_ITEM_TYPE_RAW,
 991         RTE_FLOW_ITEM_TYPE_RAW,
 992         RTE_FLOW_ITEM_TYPE_RAW,
 993         RTE_FLOW_ITEM_TYPE_VF,
 994         RTE_FLOW_ITEM_TYPE_END,
 995 };
 996
 997 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 998         RTE_FLOW_ITEM_TYPE_ETH,
 999         RTE_FLOW_ITEM_TYPE_IPV4,
1000         RTE_FLOW_ITEM_TYPE_SCTP,
1001         RTE_FLOW_ITEM_TYPE_RAW,
1002         RTE_FLOW_ITEM_TYPE_VF,
1003         RTE_FLOW_ITEM_TYPE_END,
1004 };
1005
1006 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1007         RTE_FLOW_ITEM_TYPE_ETH,
1008         RTE_FLOW_ITEM_TYPE_IPV4,
1009         RTE_FLOW_ITEM_TYPE_SCTP,
1010         RTE_FLOW_ITEM_TYPE_RAW,
1011         RTE_FLOW_ITEM_TYPE_RAW,
1012         RTE_FLOW_ITEM_TYPE_VF,
1013         RTE_FLOW_ITEM_TYPE_END,
1014 };
1015
1016 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1017         RTE_FLOW_ITEM_TYPE_ETH,
1018         RTE_FLOW_ITEM_TYPE_IPV4,
1019         RTE_FLOW_ITEM_TYPE_SCTP,
1020         RTE_FLOW_ITEM_TYPE_RAW,
1021         RTE_FLOW_ITEM_TYPE_RAW,
1022         RTE_FLOW_ITEM_TYPE_RAW,
1023         RTE_FLOW_ITEM_TYPE_VF,
1024         RTE_FLOW_ITEM_TYPE_END,
1025 };
1026
1027 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1028         RTE_FLOW_ITEM_TYPE_ETH,
1029         RTE_FLOW_ITEM_TYPE_IPV6,
1030         RTE_FLOW_ITEM_TYPE_RAW,
1031         RTE_FLOW_ITEM_TYPE_VF,
1032         RTE_FLOW_ITEM_TYPE_END,
1033 };
1034
1035 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1036         RTE_FLOW_ITEM_TYPE_ETH,
1037         RTE_FLOW_ITEM_TYPE_IPV6,
1038         RTE_FLOW_ITEM_TYPE_RAW,
1039         RTE_FLOW_ITEM_TYPE_RAW,
1040         RTE_FLOW_ITEM_TYPE_VF,
1041         RTE_FLOW_ITEM_TYPE_END,
1042 };
1043
1044 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1045         RTE_FLOW_ITEM_TYPE_ETH,
1046         RTE_FLOW_ITEM_TYPE_IPV6,
1047         RTE_FLOW_ITEM_TYPE_RAW,
1048         RTE_FLOW_ITEM_TYPE_RAW,
1049         RTE_FLOW_ITEM_TYPE_RAW,
1050         RTE_FLOW_ITEM_TYPE_VF,
1051         RTE_FLOW_ITEM_TYPE_END,
1052 };
1053
1054 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1055         RTE_FLOW_ITEM_TYPE_ETH,
1056         RTE_FLOW_ITEM_TYPE_IPV6,
1057         RTE_FLOW_ITEM_TYPE_UDP,
1058         RTE_FLOW_ITEM_TYPE_RAW,
1059         RTE_FLOW_ITEM_TYPE_VF,
1060         RTE_FLOW_ITEM_TYPE_END,
1061 };
1062
1063 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1064         RTE_FLOW_ITEM_TYPE_ETH,
1065         RTE_FLOW_ITEM_TYPE_IPV6,
1066         RTE_FLOW_ITEM_TYPE_UDP,
1067         RTE_FLOW_ITEM_TYPE_RAW,
1068         RTE_FLOW_ITEM_TYPE_RAW,
1069         RTE_FLOW_ITEM_TYPE_VF,
1070         RTE_FLOW_ITEM_TYPE_END,
1071 };
1072
1073 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1074         RTE_FLOW_ITEM_TYPE_ETH,
1075         RTE_FLOW_ITEM_TYPE_IPV6,
1076         RTE_FLOW_ITEM_TYPE_UDP,
1077         RTE_FLOW_ITEM_TYPE_RAW,
1078         RTE_FLOW_ITEM_TYPE_RAW,
1079         RTE_FLOW_ITEM_TYPE_RAW,
1080         RTE_FLOW_ITEM_TYPE_VF,
1081         RTE_FLOW_ITEM_TYPE_END,
1082 };
1083
1084 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1085         RTE_FLOW_ITEM_TYPE_ETH,
1086         RTE_FLOW_ITEM_TYPE_IPV6,
1087         RTE_FLOW_ITEM_TYPE_TCP,
1088         RTE_FLOW_ITEM_TYPE_RAW,
1089         RTE_FLOW_ITEM_TYPE_VF,
1090         RTE_FLOW_ITEM_TYPE_END,
1091 };
1092
1093 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1094         RTE_FLOW_ITEM_TYPE_ETH,
1095         RTE_FLOW_ITEM_TYPE_IPV6,
1096         RTE_FLOW_ITEM_TYPE_TCP,
1097         RTE_FLOW_ITEM_TYPE_RAW,
1098         RTE_FLOW_ITEM_TYPE_RAW,
1099         RTE_FLOW_ITEM_TYPE_VF,
1100         RTE_FLOW_ITEM_TYPE_END,
1101 };
1102
1103 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1104         RTE_FLOW_ITEM_TYPE_ETH,
1105         RTE_FLOW_ITEM_TYPE_IPV6,
1106         RTE_FLOW_ITEM_TYPE_TCP,
1107         RTE_FLOW_ITEM_TYPE_RAW,
1108         RTE_FLOW_ITEM_TYPE_RAW,
1109         RTE_FLOW_ITEM_TYPE_RAW,
1110         RTE_FLOW_ITEM_TYPE_VF,
1111         RTE_FLOW_ITEM_TYPE_END,
1112 };
1113
1114 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1115         RTE_FLOW_ITEM_TYPE_ETH,
1116         RTE_FLOW_ITEM_TYPE_IPV6,
1117         RTE_FLOW_ITEM_TYPE_SCTP,
1118         RTE_FLOW_ITEM_TYPE_RAW,
1119         RTE_FLOW_ITEM_TYPE_VF,
1120         RTE_FLOW_ITEM_TYPE_END,
1121 };
1122
1123 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1124         RTE_FLOW_ITEM_TYPE_ETH,
1125         RTE_FLOW_ITEM_TYPE_IPV6,
1126         RTE_FLOW_ITEM_TYPE_SCTP,
1127         RTE_FLOW_ITEM_TYPE_RAW,
1128         RTE_FLOW_ITEM_TYPE_RAW,
1129         RTE_FLOW_ITEM_TYPE_VF,
1130         RTE_FLOW_ITEM_TYPE_END,
1131 };
1132
1133 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1134         RTE_FLOW_ITEM_TYPE_ETH,
1135         RTE_FLOW_ITEM_TYPE_IPV6,
1136         RTE_FLOW_ITEM_TYPE_SCTP,
1137         RTE_FLOW_ITEM_TYPE_RAW,
1138         RTE_FLOW_ITEM_TYPE_RAW,
1139         RTE_FLOW_ITEM_TYPE_RAW,
1140         RTE_FLOW_ITEM_TYPE_VF,
1141         RTE_FLOW_ITEM_TYPE_END,
1142 };
1143
1144 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1145         RTE_FLOW_ITEM_TYPE_ETH,
1146         RTE_FLOW_ITEM_TYPE_VLAN,
1147         RTE_FLOW_ITEM_TYPE_VF,
1148         RTE_FLOW_ITEM_TYPE_END,
1149 };
1150
1151 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1152         RTE_FLOW_ITEM_TYPE_ETH,
1153         RTE_FLOW_ITEM_TYPE_VLAN,
1154         RTE_FLOW_ITEM_TYPE_IPV4,
1155         RTE_FLOW_ITEM_TYPE_VF,
1156         RTE_FLOW_ITEM_TYPE_END,
1157 };
1158
1159 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1160         RTE_FLOW_ITEM_TYPE_ETH,
1161         RTE_FLOW_ITEM_TYPE_VLAN,
1162         RTE_FLOW_ITEM_TYPE_IPV4,
1163         RTE_FLOW_ITEM_TYPE_UDP,
1164         RTE_FLOW_ITEM_TYPE_VF,
1165         RTE_FLOW_ITEM_TYPE_END,
1166 };
1167
1168 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1169         RTE_FLOW_ITEM_TYPE_ETH,
1170         RTE_FLOW_ITEM_TYPE_VLAN,
1171         RTE_FLOW_ITEM_TYPE_IPV4,
1172         RTE_FLOW_ITEM_TYPE_TCP,
1173         RTE_FLOW_ITEM_TYPE_VF,
1174         RTE_FLOW_ITEM_TYPE_END,
1175 };
1176
1177 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1178         RTE_FLOW_ITEM_TYPE_ETH,
1179         RTE_FLOW_ITEM_TYPE_VLAN,
1180         RTE_FLOW_ITEM_TYPE_IPV4,
1181         RTE_FLOW_ITEM_TYPE_SCTP,
1182         RTE_FLOW_ITEM_TYPE_VF,
1183         RTE_FLOW_ITEM_TYPE_END,
1184 };
1185
1186 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1187         RTE_FLOW_ITEM_TYPE_ETH,
1188         RTE_FLOW_ITEM_TYPE_VLAN,
1189         RTE_FLOW_ITEM_TYPE_IPV6,
1190         RTE_FLOW_ITEM_TYPE_VF,
1191         RTE_FLOW_ITEM_TYPE_END,
1192 };
1193
1194 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1195         RTE_FLOW_ITEM_TYPE_ETH,
1196         RTE_FLOW_ITEM_TYPE_VLAN,
1197         RTE_FLOW_ITEM_TYPE_IPV6,
1198         RTE_FLOW_ITEM_TYPE_UDP,
1199         RTE_FLOW_ITEM_TYPE_VF,
1200         RTE_FLOW_ITEM_TYPE_END,
1201 };
1202
1203 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1204         RTE_FLOW_ITEM_TYPE_ETH,
1205         RTE_FLOW_ITEM_TYPE_VLAN,
1206         RTE_FLOW_ITEM_TYPE_IPV6,
1207         RTE_FLOW_ITEM_TYPE_TCP,
1208         RTE_FLOW_ITEM_TYPE_VF,
1209         RTE_FLOW_ITEM_TYPE_END,
1210 };
1211
1212 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1213         RTE_FLOW_ITEM_TYPE_ETH,
1214         RTE_FLOW_ITEM_TYPE_VLAN,
1215         RTE_FLOW_ITEM_TYPE_IPV6,
1216         RTE_FLOW_ITEM_TYPE_SCTP,
1217         RTE_FLOW_ITEM_TYPE_VF,
1218         RTE_FLOW_ITEM_TYPE_END,
1219 };
1220
1221 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1222         RTE_FLOW_ITEM_TYPE_ETH,
1223         RTE_FLOW_ITEM_TYPE_VLAN,
1224         RTE_FLOW_ITEM_TYPE_RAW,
1225         RTE_FLOW_ITEM_TYPE_VF,
1226         RTE_FLOW_ITEM_TYPE_END,
1227 };
1228
1229 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1230         RTE_FLOW_ITEM_TYPE_ETH,
1231         RTE_FLOW_ITEM_TYPE_VLAN,
1232         RTE_FLOW_ITEM_TYPE_RAW,
1233         RTE_FLOW_ITEM_TYPE_RAW,
1234         RTE_FLOW_ITEM_TYPE_VF,
1235         RTE_FLOW_ITEM_TYPE_END,
1236 };
1237
1238 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1239         RTE_FLOW_ITEM_TYPE_ETH,
1240         RTE_FLOW_ITEM_TYPE_VLAN,
1241         RTE_FLOW_ITEM_TYPE_RAW,
1242         RTE_FLOW_ITEM_TYPE_RAW,
1243         RTE_FLOW_ITEM_TYPE_RAW,
1244         RTE_FLOW_ITEM_TYPE_VF,
1245         RTE_FLOW_ITEM_TYPE_END,
1246 };
1247
1248 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1249         RTE_FLOW_ITEM_TYPE_ETH,
1250         RTE_FLOW_ITEM_TYPE_VLAN,
1251         RTE_FLOW_ITEM_TYPE_IPV4,
1252         RTE_FLOW_ITEM_TYPE_RAW,
1253         RTE_FLOW_ITEM_TYPE_VF,
1254         RTE_FLOW_ITEM_TYPE_END,
1255 };
1256
1257 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1258         RTE_FLOW_ITEM_TYPE_ETH,
1259         RTE_FLOW_ITEM_TYPE_VLAN,
1260         RTE_FLOW_ITEM_TYPE_IPV4,
1261         RTE_FLOW_ITEM_TYPE_RAW,
1262         RTE_FLOW_ITEM_TYPE_RAW,
1263         RTE_FLOW_ITEM_TYPE_VF,
1264         RTE_FLOW_ITEM_TYPE_END,
1265 };
1266
1267 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1268         RTE_FLOW_ITEM_TYPE_ETH,
1269         RTE_FLOW_ITEM_TYPE_VLAN,
1270         RTE_FLOW_ITEM_TYPE_IPV4,
1271         RTE_FLOW_ITEM_TYPE_RAW,
1272         RTE_FLOW_ITEM_TYPE_RAW,
1273         RTE_FLOW_ITEM_TYPE_RAW,
1274         RTE_FLOW_ITEM_TYPE_VF,
1275         RTE_FLOW_ITEM_TYPE_END,
1276 };
1277
1278 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1279         RTE_FLOW_ITEM_TYPE_ETH,
1280         RTE_FLOW_ITEM_TYPE_VLAN,
1281         RTE_FLOW_ITEM_TYPE_IPV4,
1282         RTE_FLOW_ITEM_TYPE_UDP,
1283         RTE_FLOW_ITEM_TYPE_RAW,
1284         RTE_FLOW_ITEM_TYPE_VF,
1285         RTE_FLOW_ITEM_TYPE_END,
1286 };
1287
1288 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1289         RTE_FLOW_ITEM_TYPE_ETH,
1290         RTE_FLOW_ITEM_TYPE_VLAN,
1291         RTE_FLOW_ITEM_TYPE_IPV4,
1292         RTE_FLOW_ITEM_TYPE_UDP,
1293         RTE_FLOW_ITEM_TYPE_RAW,
1294         RTE_FLOW_ITEM_TYPE_RAW,
1295         RTE_FLOW_ITEM_TYPE_VF,
1296         RTE_FLOW_ITEM_TYPE_END,
1297 };
1298
1299 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1300         RTE_FLOW_ITEM_TYPE_ETH,
1301         RTE_FLOW_ITEM_TYPE_VLAN,
1302         RTE_FLOW_ITEM_TYPE_IPV4,
1303         RTE_FLOW_ITEM_TYPE_UDP,
1304         RTE_FLOW_ITEM_TYPE_RAW,
1305         RTE_FLOW_ITEM_TYPE_RAW,
1306         RTE_FLOW_ITEM_TYPE_RAW,
1307         RTE_FLOW_ITEM_TYPE_VF,
1308         RTE_FLOW_ITEM_TYPE_END,
1309 };
1310
1311 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1312         RTE_FLOW_ITEM_TYPE_ETH,
1313         RTE_FLOW_ITEM_TYPE_VLAN,
1314         RTE_FLOW_ITEM_TYPE_IPV4,
1315         RTE_FLOW_ITEM_TYPE_TCP,
1316         RTE_FLOW_ITEM_TYPE_RAW,
1317         RTE_FLOW_ITEM_TYPE_VF,
1318         RTE_FLOW_ITEM_TYPE_END,
1319 };
1320
1321 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1322         RTE_FLOW_ITEM_TYPE_ETH,
1323         RTE_FLOW_ITEM_TYPE_VLAN,
1324         RTE_FLOW_ITEM_TYPE_IPV4,
1325         RTE_FLOW_ITEM_TYPE_TCP,
1326         RTE_FLOW_ITEM_TYPE_RAW,
1327         RTE_FLOW_ITEM_TYPE_RAW,
1328         RTE_FLOW_ITEM_TYPE_VF,
1329         RTE_FLOW_ITEM_TYPE_END,
1330 };
1331
1332 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1333         RTE_FLOW_ITEM_TYPE_ETH,
1334         RTE_FLOW_ITEM_TYPE_VLAN,
1335         RTE_FLOW_ITEM_TYPE_IPV4,
1336         RTE_FLOW_ITEM_TYPE_TCP,
1337         RTE_FLOW_ITEM_TYPE_RAW,
1338         RTE_FLOW_ITEM_TYPE_RAW,
1339         RTE_FLOW_ITEM_TYPE_RAW,
1340         RTE_FLOW_ITEM_TYPE_VF,
1341         RTE_FLOW_ITEM_TYPE_END,
1342 };
1343
1344 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1345         RTE_FLOW_ITEM_TYPE_ETH,
1346         RTE_FLOW_ITEM_TYPE_VLAN,
1347         RTE_FLOW_ITEM_TYPE_IPV4,
1348         RTE_FLOW_ITEM_TYPE_SCTP,
1349         RTE_FLOW_ITEM_TYPE_RAW,
1350         RTE_FLOW_ITEM_TYPE_VF,
1351         RTE_FLOW_ITEM_TYPE_END,
1352 };
1353
1354 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1355         RTE_FLOW_ITEM_TYPE_ETH,
1356         RTE_FLOW_ITEM_TYPE_VLAN,
1357         RTE_FLOW_ITEM_TYPE_IPV4,
1358         RTE_FLOW_ITEM_TYPE_SCTP,
1359         RTE_FLOW_ITEM_TYPE_RAW,
1360         RTE_FLOW_ITEM_TYPE_RAW,
1361         RTE_FLOW_ITEM_TYPE_VF,
1362         RTE_FLOW_ITEM_TYPE_END,
1363 };
1364
1365 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1366         RTE_FLOW_ITEM_TYPE_ETH,
1367         RTE_FLOW_ITEM_TYPE_VLAN,
1368         RTE_FLOW_ITEM_TYPE_IPV4,
1369         RTE_FLOW_ITEM_TYPE_SCTP,
1370         RTE_FLOW_ITEM_TYPE_RAW,
1371         RTE_FLOW_ITEM_TYPE_RAW,
1372         RTE_FLOW_ITEM_TYPE_RAW,
1373         RTE_FLOW_ITEM_TYPE_VF,
1374         RTE_FLOW_ITEM_TYPE_END,
1375 };
1376
1377 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1378         RTE_FLOW_ITEM_TYPE_ETH,
1379         RTE_FLOW_ITEM_TYPE_VLAN,
1380         RTE_FLOW_ITEM_TYPE_IPV6,
1381         RTE_FLOW_ITEM_TYPE_RAW,
1382         RTE_FLOW_ITEM_TYPE_VF,
1383         RTE_FLOW_ITEM_TYPE_END,
1384 };
1385
1386 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1387         RTE_FLOW_ITEM_TYPE_ETH,
1388         RTE_FLOW_ITEM_TYPE_VLAN,
1389         RTE_FLOW_ITEM_TYPE_IPV6,
1390         RTE_FLOW_ITEM_TYPE_RAW,
1391         RTE_FLOW_ITEM_TYPE_RAW,
1392         RTE_FLOW_ITEM_TYPE_VF,
1393         RTE_FLOW_ITEM_TYPE_END,
1394 };
1395
1396 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1397         RTE_FLOW_ITEM_TYPE_ETH,
1398         RTE_FLOW_ITEM_TYPE_VLAN,
1399         RTE_FLOW_ITEM_TYPE_IPV6,
1400         RTE_FLOW_ITEM_TYPE_RAW,
1401         RTE_FLOW_ITEM_TYPE_RAW,
1402         RTE_FLOW_ITEM_TYPE_RAW,
1403         RTE_FLOW_ITEM_TYPE_VF,
1404         RTE_FLOW_ITEM_TYPE_END,
1405 };
1406
1407 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1408         RTE_FLOW_ITEM_TYPE_ETH,
1409         RTE_FLOW_ITEM_TYPE_VLAN,
1410         RTE_FLOW_ITEM_TYPE_IPV6,
1411         RTE_FLOW_ITEM_TYPE_UDP,
1412         RTE_FLOW_ITEM_TYPE_RAW,
1413         RTE_FLOW_ITEM_TYPE_VF,
1414         RTE_FLOW_ITEM_TYPE_END,
1415 };
1416
1417 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1418         RTE_FLOW_ITEM_TYPE_ETH,
1419         RTE_FLOW_ITEM_TYPE_VLAN,
1420         RTE_FLOW_ITEM_TYPE_IPV6,
1421         RTE_FLOW_ITEM_TYPE_UDP,
1422         RTE_FLOW_ITEM_TYPE_RAW,
1423         RTE_FLOW_ITEM_TYPE_RAW,
1424         RTE_FLOW_ITEM_TYPE_VF,
1425         RTE_FLOW_ITEM_TYPE_END,
1426 };
1427
1428 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1429         RTE_FLOW_ITEM_TYPE_ETH,
1430         RTE_FLOW_ITEM_TYPE_VLAN,
1431         RTE_FLOW_ITEM_TYPE_IPV6,
1432         RTE_FLOW_ITEM_TYPE_UDP,
1433         RTE_FLOW_ITEM_TYPE_RAW,
1434         RTE_FLOW_ITEM_TYPE_RAW,
1435         RTE_FLOW_ITEM_TYPE_RAW,
1436         RTE_FLOW_ITEM_TYPE_VF,
1437         RTE_FLOW_ITEM_TYPE_END,
1438 };
1439
1440 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1441         RTE_FLOW_ITEM_TYPE_ETH,
1442         RTE_FLOW_ITEM_TYPE_VLAN,
1443         RTE_FLOW_ITEM_TYPE_IPV6,
1444         RTE_FLOW_ITEM_TYPE_TCP,
1445         RTE_FLOW_ITEM_TYPE_RAW,
1446         RTE_FLOW_ITEM_TYPE_VF,
1447         RTE_FLOW_ITEM_TYPE_END,
1448 };
1449
1450 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1451         RTE_FLOW_ITEM_TYPE_ETH,
1452         RTE_FLOW_ITEM_TYPE_VLAN,
1453         RTE_FLOW_ITEM_TYPE_IPV6,
1454         RTE_FLOW_ITEM_TYPE_TCP,
1455         RTE_FLOW_ITEM_TYPE_RAW,
1456         RTE_FLOW_ITEM_TYPE_RAW,
1457         RTE_FLOW_ITEM_TYPE_VF,
1458         RTE_FLOW_ITEM_TYPE_END,
1459 };
1460
1461 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1462         RTE_FLOW_ITEM_TYPE_ETH,
1463         RTE_FLOW_ITEM_TYPE_VLAN,
1464         RTE_FLOW_ITEM_TYPE_IPV6,
1465         RTE_FLOW_ITEM_TYPE_TCP,
1466         RTE_FLOW_ITEM_TYPE_RAW,
1467         RTE_FLOW_ITEM_TYPE_RAW,
1468         RTE_FLOW_ITEM_TYPE_RAW,
1469         RTE_FLOW_ITEM_TYPE_VF,
1470         RTE_FLOW_ITEM_TYPE_END,
1471 };
1472
1473 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1474         RTE_FLOW_ITEM_TYPE_ETH,
1475         RTE_FLOW_ITEM_TYPE_VLAN,
1476         RTE_FLOW_ITEM_TYPE_IPV6,
1477         RTE_FLOW_ITEM_TYPE_SCTP,
1478         RTE_FLOW_ITEM_TYPE_RAW,
1479         RTE_FLOW_ITEM_TYPE_VF,
1480         RTE_FLOW_ITEM_TYPE_END,
1481 };
1482
1483 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1484         RTE_FLOW_ITEM_TYPE_ETH,
1485         RTE_FLOW_ITEM_TYPE_VLAN,
1486         RTE_FLOW_ITEM_TYPE_IPV6,
1487         RTE_FLOW_ITEM_TYPE_SCTP,
1488         RTE_FLOW_ITEM_TYPE_RAW,
1489         RTE_FLOW_ITEM_TYPE_RAW,
1490         RTE_FLOW_ITEM_TYPE_VF,
1491         RTE_FLOW_ITEM_TYPE_END,
1492 };
1493
1494 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1495         RTE_FLOW_ITEM_TYPE_ETH,
1496         RTE_FLOW_ITEM_TYPE_VLAN,
1497         RTE_FLOW_ITEM_TYPE_IPV6,
1498         RTE_FLOW_ITEM_TYPE_SCTP,
1499         RTE_FLOW_ITEM_TYPE_RAW,
1500         RTE_FLOW_ITEM_TYPE_RAW,
1501         RTE_FLOW_ITEM_TYPE_RAW,
1502         RTE_FLOW_ITEM_TYPE_VF,
1503         RTE_FLOW_ITEM_TYPE_END,
1504 };
1505
1506 /* Pattern matched tunnel filter */
1507 static enum rte_flow_item_type pattern_vxlan_1[] = {
1508         RTE_FLOW_ITEM_TYPE_ETH,
1509         RTE_FLOW_ITEM_TYPE_IPV4,
1510         RTE_FLOW_ITEM_TYPE_UDP,
1511         RTE_FLOW_ITEM_TYPE_VXLAN,
1512         RTE_FLOW_ITEM_TYPE_ETH,
1513         RTE_FLOW_ITEM_TYPE_END,
1514 };
1515
1516 static enum rte_flow_item_type pattern_vxlan_2[] = {
1517         RTE_FLOW_ITEM_TYPE_ETH,
1518         RTE_FLOW_ITEM_TYPE_IPV6,
1519         RTE_FLOW_ITEM_TYPE_UDP,
1520         RTE_FLOW_ITEM_TYPE_VXLAN,
1521         RTE_FLOW_ITEM_TYPE_ETH,
1522         RTE_FLOW_ITEM_TYPE_END,
1523 };
1524
1525 static enum rte_flow_item_type pattern_vxlan_3[] = {
1526         RTE_FLOW_ITEM_TYPE_ETH,
1527         RTE_FLOW_ITEM_TYPE_IPV4,
1528         RTE_FLOW_ITEM_TYPE_UDP,
1529         RTE_FLOW_ITEM_TYPE_VXLAN,
1530         RTE_FLOW_ITEM_TYPE_ETH,
1531         RTE_FLOW_ITEM_TYPE_VLAN,
1532         RTE_FLOW_ITEM_TYPE_END,
1533 };
1534
1535 static enum rte_flow_item_type pattern_vxlan_4[] = {
1536         RTE_FLOW_ITEM_TYPE_ETH,
1537         RTE_FLOW_ITEM_TYPE_IPV6,
1538         RTE_FLOW_ITEM_TYPE_UDP,
1539         RTE_FLOW_ITEM_TYPE_VXLAN,
1540         RTE_FLOW_ITEM_TYPE_ETH,
1541         RTE_FLOW_ITEM_TYPE_VLAN,
1542         RTE_FLOW_ITEM_TYPE_END,
1543 };
1544
1545 static enum rte_flow_item_type pattern_nvgre_1[] = {
1546         RTE_FLOW_ITEM_TYPE_ETH,
1547         RTE_FLOW_ITEM_TYPE_IPV4,
1548         RTE_FLOW_ITEM_TYPE_NVGRE,
1549         RTE_FLOW_ITEM_TYPE_ETH,
1550         RTE_FLOW_ITEM_TYPE_END,
1551 };
1552
1553 static enum rte_flow_item_type pattern_nvgre_2[] = {
1554         RTE_FLOW_ITEM_TYPE_ETH,
1555         RTE_FLOW_ITEM_TYPE_IPV6,
1556         RTE_FLOW_ITEM_TYPE_NVGRE,
1557         RTE_FLOW_ITEM_TYPE_ETH,
1558         RTE_FLOW_ITEM_TYPE_END,
1559 };
1560
1561 static enum rte_flow_item_type pattern_nvgre_3[] = {
1562         RTE_FLOW_ITEM_TYPE_ETH,
1563         RTE_FLOW_ITEM_TYPE_IPV4,
1564         RTE_FLOW_ITEM_TYPE_NVGRE,
1565         RTE_FLOW_ITEM_TYPE_ETH,
1566         RTE_FLOW_ITEM_TYPE_VLAN,
1567         RTE_FLOW_ITEM_TYPE_END,
1568 };
1569
1570 static enum rte_flow_item_type pattern_nvgre_4[] = {
1571         RTE_FLOW_ITEM_TYPE_ETH,
1572         RTE_FLOW_ITEM_TYPE_IPV6,
1573         RTE_FLOW_ITEM_TYPE_NVGRE,
1574         RTE_FLOW_ITEM_TYPE_ETH,
1575         RTE_FLOW_ITEM_TYPE_VLAN,
1576         RTE_FLOW_ITEM_TYPE_END,
1577 };
1578
1579 static enum rte_flow_item_type pattern_mpls_1[] = {
1580         RTE_FLOW_ITEM_TYPE_ETH,
1581         RTE_FLOW_ITEM_TYPE_IPV4,
1582         RTE_FLOW_ITEM_TYPE_UDP,
1583         RTE_FLOW_ITEM_TYPE_MPLS,
1584         RTE_FLOW_ITEM_TYPE_END,
1585 };
1586
1587 static enum rte_flow_item_type pattern_mpls_2[] = {
1588         RTE_FLOW_ITEM_TYPE_ETH,
1589         RTE_FLOW_ITEM_TYPE_IPV6,
1590         RTE_FLOW_ITEM_TYPE_UDP,
1591         RTE_FLOW_ITEM_TYPE_MPLS,
1592         RTE_FLOW_ITEM_TYPE_END,
1593 };
1594
1595 static enum rte_flow_item_type pattern_mpls_3[] = {
1596         RTE_FLOW_ITEM_TYPE_ETH,
1597         RTE_FLOW_ITEM_TYPE_IPV4,
1598         RTE_FLOW_ITEM_TYPE_GRE,
1599         RTE_FLOW_ITEM_TYPE_MPLS,
1600         RTE_FLOW_ITEM_TYPE_END,
1601 };
1602
1603 static enum rte_flow_item_type pattern_mpls_4[] = {
1604         RTE_FLOW_ITEM_TYPE_ETH,
1605         RTE_FLOW_ITEM_TYPE_IPV6,
1606         RTE_FLOW_ITEM_TYPE_GRE,
1607         RTE_FLOW_ITEM_TYPE_MPLS,
1608         RTE_FLOW_ITEM_TYPE_END,
1609 };
1610
1611 static enum rte_flow_item_type pattern_qinq_1[] = {
1612         RTE_FLOW_ITEM_TYPE_ETH,
1613         RTE_FLOW_ITEM_TYPE_VLAN,
1614         RTE_FLOW_ITEM_TYPE_VLAN,
1615         RTE_FLOW_ITEM_TYPE_END,
1616 };
1617
1618 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1619         /* Ethertype */
1620         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1621         /* FDIR - support default flow type without flexible payload*/
1622         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1636         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1637         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1638         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1639         /* FDIR - support default flow type with flexible payload */
1640         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1664         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1665         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1667         /* FDIR - support single vlan input set */
1668         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1701         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1702         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1704         /* FDIR - support VF item */
1705         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1773         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1774         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1775         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1776         /* VXLAN */
1777         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1778         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1779         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1780         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1781         /* NVGRE */
1782         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1783         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1784         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1785         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1786         /* MPLSoUDP & MPLSoGRE */
1787         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1788         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1789         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1790         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1791         /* GTP-C & GTP-U */
1792         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1793         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1794         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1795         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1796         /* QINQ */
1797         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1798 };
1799
1800 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1801         do {                                                            \
1802                 act = actions + index;                                  \
1803                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1804                         index++;                                        \
1805                         act = actions + index;                          \
1806                 }                                                       \
1807         } while (0)
1808
1809 /* Find the first VOID or non-VOID item pointer */
1810 static const struct rte_flow_item *
1811 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1812 {
1813         bool is_find;
1814
1815         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1816                 if (is_void)
1817                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1818                 else
1819                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1820                 if (is_find)
1821                         break;
1822                 item++;
1823         }
1824         return item;
1825 }
1826
1827 /* Skip all VOID items of the pattern */
1828 static void
1829 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1830                             const struct rte_flow_item *pattern)
1831 {
1832         uint32_t cpy_count = 0;
1833         const struct rte_flow_item *pb = pattern, *pe = pattern;
1834
1835         for (;;) {
1836                 /* Find a non-void item first */
1837                 pb = i40e_find_first_item(pb, false);
1838                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1839                         pe = pb;
1840                         break;
1841                 }
1842
1843                 /* Find a void item */
1844                 pe = i40e_find_first_item(pb + 1, true);
1845
1846                 cpy_count = pe - pb;
1847                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1848
1849                 items += cpy_count;
1850
1851                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1852                         pb = pe;
1853                         break;
1854                 }
1855
1856                 pb = pe + 1;
1857         }
1858         /* Copy the END item. */
1859         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1860 }
1861
1862 /* Check if the pattern matches a supported item type array */
1863 static bool
1864 i40e_match_pattern(enum rte_flow_item_type *item_array,
1865                    struct rte_flow_item *pattern)
1866 {
1867         struct rte_flow_item *item = pattern;
1868
1869         while ((*item_array == item->type) &&
1870                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1871                 item_array++;
1872                 item++;
1873         }
1874
1875         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1876                 item->type == RTE_FLOW_ITEM_TYPE_END);
1877 }
1878
1879 /* Find if there's parse filter function matched */
1880 static parse_filter_t
1881 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1882 {
1883         parse_filter_t parse_filter = NULL;
1884         uint8_t i = *idx;
1885
1886         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1887                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1888                                         pattern)) {
1889                         parse_filter = i40e_supported_patterns[i].parse_filter;
1890                         break;
1891                 }
1892         }
1893
1894         *idx = ++i;
1895
1896         return parse_filter;
1897 }
1898
1899 /* Parse attributes */
1900 static int
1901 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1902                      struct rte_flow_error *error)
1903 {
1904         /* Must be input direction */
1905         if (!attr->ingress) {
1906                 rte_flow_error_set(error, EINVAL,
1907                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1908                                    attr, "Only support ingress.");
1909                 return -rte_errno;
1910         }
1911
1912         /* Not supported */
1913         if (attr->egress) {
1914                 rte_flow_error_set(error, EINVAL,
1915                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1916                                    attr, "Not support egress.");
1917                 return -rte_errno;
1918         }
1919
1920         /* Not supported */
1921         if (attr->priority) {
1922                 rte_flow_error_set(error, EINVAL,
1923                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1924                                    attr, "Not support priority.");
1925                 return -rte_errno;
1926         }
1927
1928         /* Not supported */
1929         if (attr->group) {
1930                 rte_flow_error_set(error, EINVAL,
1931                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1932                                    attr, "Not support group.");
1933                 return -rte_errno;
1934         }
1935
1936         return 0;
1937 }
1938
1939 static uint16_t
1940 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1941 {
1942         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1943         int qinq = dev->data->dev_conf.rxmode.offloads &
1944                 DEV_RX_OFFLOAD_VLAN_EXTEND;
1945         uint64_t reg_r = 0;
1946         uint16_t reg_id;
1947         uint16_t tpid;
1948
1949         if (qinq)
1950                 reg_id = 2;
1951         else
1952                 reg_id = 3;
1953
1954         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1955                                     &reg_r, NULL);
1956
1957         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1958
1959         return tpid;
1960 }
1961
1962 /* 1. Last in item should be NULL as range is not supported.
1963  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1964  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1965  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1966  *    FF:FF:FF:FF:FF:FF
1967  * 5. Ether_type mask should be 0xFFFF.
1968  */
1969 static int
1970 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1971                                   const struct rte_flow_item *pattern,
1972                                   struct rte_flow_error *error,
1973                                   struct rte_eth_ethertype_filter *filter)
1974 {
1975         const struct rte_flow_item *item = pattern;
1976         const struct rte_flow_item_eth *eth_spec;
1977         const struct rte_flow_item_eth *eth_mask;
1978         enum rte_flow_item_type item_type;
1979         uint16_t outer_tpid;
1980
1981         outer_tpid = i40e_get_outer_vlan(dev);
1982
1983         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1984                 if (item->last) {
1985                         rte_flow_error_set(error, EINVAL,
1986                                            RTE_FLOW_ERROR_TYPE_ITEM,
1987                                            item,
1988                                            "Not support range");
1989                         return -rte_errno;
1990                 }
1991                 item_type = item->type;
1992                 switch (item_type) {
1993                 case RTE_FLOW_ITEM_TYPE_ETH:
1994                         eth_spec = item->spec;
1995                         eth_mask = item->mask;
1996                         /* Get the MAC info. */
1997                         if (!eth_spec || !eth_mask) {
1998                                 rte_flow_error_set(error, EINVAL,
1999                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2000                                                    item,
2001                                                    "NULL ETH spec/mask");
2002                                 return -rte_errno;
2003                         }
2004
2005                         /* Mask bits of source MAC address must be full of 0.
2006                          * Mask bits of destination MAC address must be full
2007                          * of 1 or full of 0.
2008                          */
2009                         if (!is_zero_ether_addr(&eth_mask->src) ||
2010                             (!is_zero_ether_addr(&eth_mask->dst) &&
2011                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2012                                 rte_flow_error_set(error, EINVAL,
2013                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2014                                                    item,
2015                                                    "Invalid MAC_addr mask");
2016                                 return -rte_errno;
2017                         }
2018
2019                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2020                                 rte_flow_error_set(error, EINVAL,
2021                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2022                                                    item,
2023                                                    "Invalid ethertype mask");
2024                                 return -rte_errno;
2025                         }
2026
2027                         /* If mask bits of destination MAC address
2028                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2029                          */
2030                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2031                                 filter->mac_addr = eth_spec->dst;
2032                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2033                         } else {
2034                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2035                         }
2036                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2037
2038                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2039                             filter->ether_type == ETHER_TYPE_IPv6 ||
2040                             filter->ether_type == ETHER_TYPE_LLDP ||
2041                             filter->ether_type == outer_tpid) {
2042                                 rte_flow_error_set(error, EINVAL,
2043                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2044                                                    item,
2045                                                    "Unsupported ether_type in"
2046                                                    " control packet filter.");
2047                                 return -rte_errno;
2048                         }
2049                         break;
2050                 default:
2051                         break;
2052                 }
2053         }
2054
2055         return 0;
2056 }
2057
2058 /* Ethertype action only supports QUEUE or DROP. */
2059 static int
2060 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2061                                  const struct rte_flow_action *actions,
2062                                  struct rte_flow_error *error,
2063                                  struct rte_eth_ethertype_filter *filter)
2064 {
2065         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2066         const struct rte_flow_action *act;
2067         const struct rte_flow_action_queue *act_q;
2068         uint32_t index = 0;
2069
2070         /* Check if the first non-void action is QUEUE or DROP. */
2071         NEXT_ITEM_OF_ACTION(act, actions, index);
2072         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2073             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2074                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2075                                    act, "Not supported action.");
2076                 return -rte_errno;
2077         }
2078
2079         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2080                 act_q = act->conf;
2081                 filter->queue = act_q->index;
2082                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2083                         rte_flow_error_set(error, EINVAL,
2084                                            RTE_FLOW_ERROR_TYPE_ACTION,
2085                                            act, "Invalid queue ID for"
2086                                            " ethertype_filter.");
2087                         return -rte_errno;
2088                 }
2089         } else {
2090                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2091         }
2092
2093         /* Check if the next non-void item is END */
2094         index++;
2095         NEXT_ITEM_OF_ACTION(act, actions, index);
2096         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2097                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2098                                    act, "Not supported action.");
2099                 return -rte_errno;
2100         }
2101
2102         return 0;
2103 }
2104
2105 static int
2106 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2107                                  const struct rte_flow_attr *attr,
2108                                  const struct rte_flow_item pattern[],
2109                                  const struct rte_flow_action actions[],
2110                                  struct rte_flow_error *error,
2111                                  union i40e_filter_t *filter)
2112 {
2113         struct rte_eth_ethertype_filter *ethertype_filter =
2114                 &filter->ethertype_filter;
2115         int ret;
2116
2117         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2118                                                 ethertype_filter);
2119         if (ret)
2120                 return ret;
2121
2122         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2123                                                ethertype_filter);
2124         if (ret)
2125                 return ret;
2126
2127         ret = i40e_flow_parse_attr(attr, error);
2128         if (ret)
2129                 return ret;
2130
2131         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2132
2133         return ret;
2134 }
2135
2136 static int
2137 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2138                          const struct rte_flow_item_raw *raw_spec,
2139                          struct rte_flow_error *error)
2140 {
2141         if (!raw_spec->relative) {
2142                 rte_flow_error_set(error, EINVAL,
2143                                    RTE_FLOW_ERROR_TYPE_ITEM,
2144                                    item,
2145                                    "Relative should be 1.");
2146                 return -rte_errno;
2147         }
2148
2149         if (raw_spec->offset % sizeof(uint16_t)) {
2150                 rte_flow_error_set(error, EINVAL,
2151                                    RTE_FLOW_ERROR_TYPE_ITEM,
2152                                    item,
2153                                    "Offset should be even.");
2154                 return -rte_errno;
2155         }
2156
2157         if (raw_spec->search || raw_spec->limit) {
2158                 rte_flow_error_set(error, EINVAL,
2159                                    RTE_FLOW_ERROR_TYPE_ITEM,
2160                                    item,
2161                                    "search or limit is not supported.");
2162                 return -rte_errno;
2163         }
2164
2165         if (raw_spec->offset < 0) {
2166                 rte_flow_error_set(error, EINVAL,
2167                                    RTE_FLOW_ERROR_TYPE_ITEM,
2168                                    item,
2169                                    "Offset should be non-negative.");
2170                 return -rte_errno;
2171         }
2172         return 0;
2173 }
2174
2175 static int
2176 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2177                          struct i40e_fdir_flex_pit *flex_pit,
2178                          enum i40e_flxpld_layer_idx layer_idx,
2179                          uint8_t raw_id)
2180 {
2181         uint8_t field_idx;
2182
2183         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2184         /* Check if the configuration is conflicted */
2185         if (pf->fdir.flex_pit_flag[layer_idx] &&
2186             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2187              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2188              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2189                 return -1;
2190
2191         /* Check if the configuration exists. */
2192         if (pf->fdir.flex_pit_flag[layer_idx] &&
2193             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2194              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2195              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2196                 return 1;
2197
2198         pf->fdir.flex_set[field_idx].src_offset =
2199                 flex_pit->src_offset;
2200         pf->fdir.flex_set[field_idx].size =
2201                 flex_pit->size;
2202         pf->fdir.flex_set[field_idx].dst_offset =
2203                 flex_pit->dst_offset;
2204
2205         return 0;
2206 }
2207
2208 static int
2209 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2210                           enum i40e_filter_pctype pctype,
2211                           uint8_t *mask)
2212 {
2213         struct i40e_fdir_flex_mask flex_mask;
2214         uint16_t mask_tmp;
2215         uint8_t i, nb_bitmask = 0;
2216
2217         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2218         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2219                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2220                 if (mask_tmp) {
2221                         flex_mask.word_mask |=
2222                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2223                         if (mask_tmp != UINT16_MAX) {
2224                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2225                                 flex_mask.bitmask[nb_bitmask].offset =
2226                                         i / sizeof(uint16_t);
2227                                 nb_bitmask++;
2228                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2229                                         return -1;
2230                         }
2231                 }
2232         }
2233         flex_mask.nb_bitmask = nb_bitmask;
2234
2235         if (pf->fdir.flex_mask_flag[pctype] &&
2236             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2237                     sizeof(struct i40e_fdir_flex_mask))))
2238                 return -2;
2239         else if (pf->fdir.flex_mask_flag[pctype] &&
2240                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2241                           sizeof(struct i40e_fdir_flex_mask))))
2242                 return 1;
2243
2244         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2245                sizeof(struct i40e_fdir_flex_mask));
2246         return 0;
2247 }
2248
2249 static void
2250 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2251                             enum i40e_flxpld_layer_idx layer_idx,
2252                             uint8_t raw_id)
2253 {
2254         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2255         uint32_t flx_pit, flx_ort;
2256         uint8_t field_idx;
2257         uint16_t min_next_off = 0;  /* in words */
2258         uint8_t i;
2259
2260         if (raw_id) {
2261                 flx_ort = (1 << I40E_GLQF_ORT_FLX_PAYLOAD_SHIFT) |
2262                           (raw_id << I40E_GLQF_ORT_FIELD_CNT_SHIFT) |
2263                           (layer_idx * I40E_MAX_FLXPLD_FIED);
2264                 I40E_WRITE_REG(hw, I40E_GLQF_ORT(33 + layer_idx), flx_ort);
2265                 i40e_global_cfg_warning(I40E_WARNING_ENA_FLX_PLD);
2266         }
2267
2268         /* Set flex pit */
2269         for (i = 0; i < raw_id; i++) {
2270                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2271                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2272                                      pf->fdir.flex_set[field_idx].size,
2273                                      pf->fdir.flex_set[field_idx].dst_offset);
2274
2275                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2276                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2277                         pf->fdir.flex_set[field_idx].size;
2278         }
2279
2280         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2281                 /* set the non-used register obeying register's constrain */
2282                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2283                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2284                                      NONUSE_FLX_PIT_DEST_OFF);
2285                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2286                 min_next_off++;
2287         }
2288
2289         pf->fdir.flex_pit_flag[layer_idx] = 1;
2290 }
2291
2292 static void
2293 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2294                             enum i40e_filter_pctype pctype)
2295 {
2296         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2297         struct i40e_fdir_flex_mask *flex_mask;
2298         uint32_t flxinset, fd_mask;
2299         uint8_t i;
2300
2301         /* Set flex mask */
2302         flex_mask = &pf->fdir.flex_mask[pctype];
2303         flxinset = (flex_mask->word_mask <<
2304                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2305                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2306         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2307
2308         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2309                 fd_mask = (flex_mask->bitmask[i].mask <<
2310                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2311                         I40E_PRTQF_FD_MSK_MASK_MASK;
2312                 fd_mask |= ((flex_mask->bitmask[i].offset +
2313                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2314                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2315                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2316                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2317         }
2318
2319         pf->fdir.flex_mask_flag[pctype] = 1;
2320 }
2321
2322 static int
2323 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2324                          enum i40e_filter_pctype pctype,
2325                          uint64_t input_set)
2326 {
2327         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2328         uint64_t inset_reg = 0;
2329         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2330         int i, num;
2331
2332         /* Check if the input set is valid */
2333         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2334                                     input_set) != 0) {
2335                 PMD_DRV_LOG(ERR, "Invalid input set");
2336                 return -EINVAL;
2337         }
2338
2339         /* Check if the configuration is conflicted */
2340         if (pf->fdir.inset_flag[pctype] &&
2341             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2342                 return -1;
2343
2344         if (pf->fdir.inset_flag[pctype] &&
2345             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2346                 return 0;
2347
2348         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2349                                            I40E_INSET_MASK_NUM_REG);
2350         if (num < 0)
2351                 return -EINVAL;
2352
2353         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2354
2355         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2356                              (uint32_t)(inset_reg & UINT32_MAX));
2357         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2358                              (uint32_t)((inset_reg >>
2359                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2360
2361         for (i = 0; i < num; i++)
2362                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2363                                      mask_reg[i]);
2364
2365         /*clear unused mask registers of the pctype */
2366         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2367                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2368         I40E_WRITE_FLUSH(hw);
2369
2370         pf->fdir.input_set[pctype] = input_set;
2371         pf->fdir.inset_flag[pctype] = 1;
2372         return 0;
2373 }
2374
2375 static uint8_t
2376 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2377                                 enum rte_flow_item_type item_type,
2378                                 struct i40e_fdir_filter_conf *filter)
2379 {
2380         struct i40e_customized_pctype *cus_pctype = NULL;
2381
2382         switch (item_type) {
2383         case RTE_FLOW_ITEM_TYPE_GTPC:
2384                 cus_pctype = i40e_find_customized_pctype(pf,
2385                                                          I40E_CUSTOMIZED_GTPC);
2386                 break;
2387         case RTE_FLOW_ITEM_TYPE_GTPU:
2388                 if (!filter->input.flow_ext.inner_ip)
2389                         cus_pctype = i40e_find_customized_pctype(pf,
2390                                                          I40E_CUSTOMIZED_GTPU);
2391                 else if (filter->input.flow_ext.iip_type ==
2392                          I40E_FDIR_IPTYPE_IPV4)
2393                         cus_pctype = i40e_find_customized_pctype(pf,
2394                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2395                 else if (filter->input.flow_ext.iip_type ==
2396                          I40E_FDIR_IPTYPE_IPV6)
2397                         cus_pctype = i40e_find_customized_pctype(pf,
2398                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2399                 break;
2400         default:
2401                 PMD_DRV_LOG(ERR, "Unsupported item type");
2402                 break;
2403         }
2404
2405         if (cus_pctype && cus_pctype->valid)
2406                 return cus_pctype->pctype;
2407
2408         return I40E_FILTER_PCTYPE_INVALID;
2409 }
2410
2411 /* 1. Last in item should be NULL as range is not supported.
2412  * 2. Supported patterns: refer to array i40e_supported_patterns.
2413  * 3. Default supported flow type and input set: refer to array
2414  *    valid_fdir_inset_table in i40e_ethdev.c.
2415  * 4. Mask of fields which need to be matched should be
2416  *    filled with 1.
2417  * 5. Mask of fields which needn't to be matched should be
2418  *    filled with 0.
2419  * 6. GTP profile supports GTPv1 only.
2420  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2421  */
2422 static int
2423 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2424                              const struct rte_flow_item *pattern,
2425                              struct rte_flow_error *error,
2426                              struct i40e_fdir_filter_conf *filter)
2427 {
2428         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2429         const struct rte_flow_item *item = pattern;
2430         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2431         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2432         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2433         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2434         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2435         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2436         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2437         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2438         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2439         const struct rte_flow_item_vf *vf_spec;
2440
2441         uint8_t pctype = 0;
2442         uint64_t input_set = I40E_INSET_NONE;
2443         uint16_t frag_off;
2444         enum rte_flow_item_type item_type;
2445         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2446         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2447         uint32_t i, j;
2448         uint8_t  ipv6_addr_mask[16] = {
2449                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2450                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2451         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2452         uint8_t raw_id = 0;
2453         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2454         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2455         struct i40e_fdir_flex_pit flex_pit;
2456         uint8_t next_dst_off = 0;
2457         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2458         uint16_t flex_size;
2459         bool cfg_flex_pit = true;
2460         bool cfg_flex_msk = true;
2461         uint16_t outer_tpid;
2462         uint16_t ether_type;
2463         uint32_t vtc_flow_cpu;
2464         bool outer_ip = true;
2465         int ret;
2466
2467         memset(off_arr, 0, sizeof(off_arr));
2468         memset(len_arr, 0, sizeof(len_arr));
2469         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2470         outer_tpid = i40e_get_outer_vlan(dev);
2471         filter->input.flow_ext.customized_pctype = false;
2472         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2473                 if (item->last) {
2474                         rte_flow_error_set(error, EINVAL,
2475                                            RTE_FLOW_ERROR_TYPE_ITEM,
2476                                            item,
2477                                            "Not support range");
2478                         return -rte_errno;
2479                 }
2480                 item_type = item->type;
2481                 switch (item_type) {
2482                 case RTE_FLOW_ITEM_TYPE_ETH:
2483                         eth_spec = item->spec;
2484                         eth_mask = item->mask;
2485
2486                         if (eth_spec && eth_mask) {
2487                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2488                                     !is_zero_ether_addr(&eth_mask->dst)) {
2489                                         rte_flow_error_set(error, EINVAL,
2490                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2491                                                       item,
2492                                                       "Invalid MAC_addr mask.");
2493                                         return -rte_errno;
2494                                 }
2495                         }
2496                         if (eth_spec && eth_mask && eth_mask->type) {
2497                                 enum rte_flow_item_type next = (item + 1)->type;
2498
2499                                 if (eth_mask->type != RTE_BE16(0xffff)) {
2500                                         rte_flow_error_set(error, EINVAL,
2501                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2502                                                       item,
2503                                                       "Invalid type mask.");
2504                                         return -rte_errno;
2505                                 }
2506
2507                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2508
2509                                 if (next == RTE_FLOW_ITEM_TYPE_VLAN ||
2510                                     ether_type == ETHER_TYPE_IPv4 ||
2511                                     ether_type == ETHER_TYPE_IPv6 ||
2512                                     ether_type == ETHER_TYPE_ARP ||
2513                                     ether_type == outer_tpid) {
2514                                         rte_flow_error_set(error, EINVAL,
2515                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2516                                                      item,
2517                                                      "Unsupported ether_type.");
2518                                         return -rte_errno;
2519                                 }
2520                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2521                                 filter->input.flow.l2_flow.ether_type =
2522                                         eth_spec->type;
2523                         }
2524
2525                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2526                         layer_idx = I40E_FLXPLD_L2_IDX;
2527
2528                         break;
2529                 case RTE_FLOW_ITEM_TYPE_VLAN:
2530                         vlan_spec = item->spec;
2531                         vlan_mask = item->mask;
2532
2533                         RTE_ASSERT(!(input_set & I40E_INSET_LAST_ETHER_TYPE));
2534                         if (vlan_spec && vlan_mask) {
2535                                 if (vlan_mask->tci ==
2536                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2537                                         input_set |= I40E_INSET_VLAN_INNER;
2538                                         filter->input.flow_ext.vlan_tci =
2539                                                 vlan_spec->tci;
2540                                 }
2541                         }
2542                         if (vlan_spec && vlan_mask && vlan_mask->inner_type) {
2543                                 if (vlan_mask->inner_type != RTE_BE16(0xffff)) {
2544                                         rte_flow_error_set(error, EINVAL,
2545                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2546                                                       item,
2547                                                       "Invalid inner_type"
2548                                                       " mask.");
2549                                         return -rte_errno;
2550                                 }
2551
2552                                 ether_type =
2553                                         rte_be_to_cpu_16(vlan_spec->inner_type);
2554
2555                                 if (ether_type == ETHER_TYPE_IPv4 ||
2556                                     ether_type == ETHER_TYPE_IPv6 ||
2557                                     ether_type == ETHER_TYPE_ARP ||
2558                                     ether_type == outer_tpid) {
2559                                         rte_flow_error_set(error, EINVAL,
2560                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2561                                                      item,
2562                                                      "Unsupported inner_type.");
2563                                         return -rte_errno;
2564                                 }
2565                                 input_set |= I40E_INSET_LAST_ETHER_TYPE;
2566                                 filter->input.flow.l2_flow.ether_type =
2567                                         vlan_spec->inner_type;
2568                         }
2569
2570                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2571                         layer_idx = I40E_FLXPLD_L2_IDX;
2572
2573                         break;
2574                 case RTE_FLOW_ITEM_TYPE_IPV4:
2575                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2576                         ipv4_spec = item->spec;
2577                         ipv4_mask = item->mask;
2578                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2579                         layer_idx = I40E_FLXPLD_L3_IDX;
2580
2581                         if (ipv4_spec && ipv4_mask && outer_ip) {
2582                                 /* Check IPv4 mask and update input set */
2583                                 if (ipv4_mask->hdr.version_ihl ||
2584                                     ipv4_mask->hdr.total_length ||
2585                                     ipv4_mask->hdr.packet_id ||
2586                                     ipv4_mask->hdr.fragment_offset ||
2587                                     ipv4_mask->hdr.hdr_checksum) {
2588                                         rte_flow_error_set(error, EINVAL,
2589                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2590                                                    item,
2591                                                    "Invalid IPv4 mask.");
2592                                         return -rte_errno;
2593                                 }
2594
2595                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2596                                         input_set |= I40E_INSET_IPV4_SRC;
2597                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2598                                         input_set |= I40E_INSET_IPV4_DST;
2599                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2600                                         input_set |= I40E_INSET_IPV4_TOS;
2601                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2602                                         input_set |= I40E_INSET_IPV4_TTL;
2603                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2604                                         input_set |= I40E_INSET_IPV4_PROTO;
2605
2606                                 /* Check if it is fragment. */
2607                                 frag_off = ipv4_spec->hdr.fragment_offset;
2608                                 frag_off = rte_be_to_cpu_16(frag_off);
2609                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2610                                     frag_off & IPV4_HDR_MF_FLAG)
2611                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2612
2613                                 /* Get the filter info */
2614                                 filter->input.flow.ip4_flow.proto =
2615                                         ipv4_spec->hdr.next_proto_id;
2616                                 filter->input.flow.ip4_flow.tos =
2617                                         ipv4_spec->hdr.type_of_service;
2618                                 filter->input.flow.ip4_flow.ttl =
2619                                         ipv4_spec->hdr.time_to_live;
2620                                 filter->input.flow.ip4_flow.src_ip =
2621                                         ipv4_spec->hdr.src_addr;
2622                                 filter->input.flow.ip4_flow.dst_ip =
2623                                         ipv4_spec->hdr.dst_addr;
2624                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2625                                 filter->input.flow_ext.inner_ip = true;
2626                                 filter->input.flow_ext.iip_type =
2627                                         I40E_FDIR_IPTYPE_IPV4;
2628                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2629                                 rte_flow_error_set(error, EINVAL,
2630                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2631                                                    item,
2632                                                    "Invalid inner IPv4 mask.");
2633                                 return -rte_errno;
2634                         }
2635
2636                         if (outer_ip)
2637                                 outer_ip = false;
2638
2639                         break;
2640                 case RTE_FLOW_ITEM_TYPE_IPV6:
2641                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2642                         ipv6_spec = item->spec;
2643                         ipv6_mask = item->mask;
2644                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2645                         layer_idx = I40E_FLXPLD_L3_IDX;
2646
2647                         if (ipv6_spec && ipv6_mask && outer_ip) {
2648                                 /* Check IPv6 mask and update input set */
2649                                 if (ipv6_mask->hdr.payload_len) {
2650                                         rte_flow_error_set(error, EINVAL,
2651                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2652                                                    item,
2653                                                    "Invalid IPv6 mask");
2654                                         return -rte_errno;
2655                                 }
2656
2657                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2658                                             ipv6_addr_mask,
2659                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2660                                         input_set |= I40E_INSET_IPV6_SRC;
2661                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2662                                             ipv6_addr_mask,
2663                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2664                                         input_set |= I40E_INSET_IPV6_DST;
2665
2666                                 if ((ipv6_mask->hdr.vtc_flow &
2667                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2668                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2669                                         input_set |= I40E_INSET_IPV6_TC;
2670                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2671                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2672                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2673                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2674
2675                                 /* Get filter info */
2676                                 vtc_flow_cpu =
2677                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2678                                 filter->input.flow.ipv6_flow.tc =
2679                                         (uint8_t)(vtc_flow_cpu >>
2680                                                   I40E_FDIR_IPv6_TC_OFFSET);
2681                                 filter->input.flow.ipv6_flow.proto =
2682                                         ipv6_spec->hdr.proto;
2683                                 filter->input.flow.ipv6_flow.hop_limits =
2684                                         ipv6_spec->hdr.hop_limits;
2685
2686                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2687                                            ipv6_spec->hdr.src_addr, 16);
2688                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2689                                            ipv6_spec->hdr.dst_addr, 16);
2690
2691                                 /* Check if it is fragment. */
2692                                 if (ipv6_spec->hdr.proto ==
2693                                     I40E_IPV6_FRAG_HEADER)
2694                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2695                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2696                                 filter->input.flow_ext.inner_ip = true;
2697                                 filter->input.flow_ext.iip_type =
2698                                         I40E_FDIR_IPTYPE_IPV6;
2699                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2700                                 rte_flow_error_set(error, EINVAL,
2701                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2702                                                    item,
2703                                                    "Invalid inner IPv6 mask");
2704                                 return -rte_errno;
2705                         }
2706
2707                         if (outer_ip)
2708                                 outer_ip = false;
2709                         break;
2710                 case RTE_FLOW_ITEM_TYPE_TCP:
2711                         tcp_spec = item->spec;
2712                         tcp_mask = item->mask;
2713
2714                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2715                                 pctype =
2716                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2717                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2718                                 pctype =
2719                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2720                         if (tcp_spec && tcp_mask) {
2721                                 /* Check TCP mask and update input set */
2722                                 if (tcp_mask->hdr.sent_seq ||
2723                                     tcp_mask->hdr.recv_ack ||
2724                                     tcp_mask->hdr.data_off ||
2725                                     tcp_mask->hdr.tcp_flags ||
2726                                     tcp_mask->hdr.rx_win ||
2727                                     tcp_mask->hdr.cksum ||
2728                                     tcp_mask->hdr.tcp_urp) {
2729                                         rte_flow_error_set(error, EINVAL,
2730                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2731                                                    item,
2732                                                    "Invalid TCP mask");
2733                                         return -rte_errno;
2734                                 }
2735
2736                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2737                                         input_set |= I40E_INSET_SRC_PORT;
2738                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2739                                         input_set |= I40E_INSET_DST_PORT;
2740
2741                                 /* Get filter info */
2742                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2743                                         filter->input.flow.tcp4_flow.src_port =
2744                                                 tcp_spec->hdr.src_port;
2745                                         filter->input.flow.tcp4_flow.dst_port =
2746                                                 tcp_spec->hdr.dst_port;
2747                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2748                                         filter->input.flow.tcp6_flow.src_port =
2749                                                 tcp_spec->hdr.src_port;
2750                                         filter->input.flow.tcp6_flow.dst_port =
2751                                                 tcp_spec->hdr.dst_port;
2752                                 }
2753                         }
2754
2755                         layer_idx = I40E_FLXPLD_L4_IDX;
2756
2757                         break;
2758                 case RTE_FLOW_ITEM_TYPE_UDP:
2759                         udp_spec = item->spec;
2760                         udp_mask = item->mask;
2761
2762                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2763                                 pctype =
2764                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2765                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2766                                 pctype =
2767                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2768
2769                         if (udp_spec && udp_mask) {
2770                                 /* Check UDP mask and update input set*/
2771                                 if (udp_mask->hdr.dgram_len ||
2772                                     udp_mask->hdr.dgram_cksum) {
2773                                         rte_flow_error_set(error, EINVAL,
2774                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2775                                                    item,
2776                                                    "Invalid UDP mask");
2777                                         return -rte_errno;
2778                                 }
2779
2780                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2781                                         input_set |= I40E_INSET_SRC_PORT;
2782                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2783                                         input_set |= I40E_INSET_DST_PORT;
2784
2785                                 /* Get filter info */
2786                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2787                                         filter->input.flow.udp4_flow.src_port =
2788                                                 udp_spec->hdr.src_port;
2789                                         filter->input.flow.udp4_flow.dst_port =
2790                                                 udp_spec->hdr.dst_port;
2791                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2792                                         filter->input.flow.udp6_flow.src_port =
2793                                                 udp_spec->hdr.src_port;
2794                                         filter->input.flow.udp6_flow.dst_port =
2795                                                 udp_spec->hdr.dst_port;
2796                                 }
2797                         }
2798
2799                         layer_idx = I40E_FLXPLD_L4_IDX;
2800
2801                         break;
2802                 case RTE_FLOW_ITEM_TYPE_GTPC:
2803                 case RTE_FLOW_ITEM_TYPE_GTPU:
2804                         if (!pf->gtp_support) {
2805                                 rte_flow_error_set(error, EINVAL,
2806                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2807                                                    item,
2808                                                    "Unsupported protocol");
2809                                 return -rte_errno;
2810                         }
2811
2812                         gtp_spec = item->spec;
2813                         gtp_mask = item->mask;
2814
2815                         if (gtp_spec && gtp_mask) {
2816                                 if (gtp_mask->v_pt_rsv_flags ||
2817                                     gtp_mask->msg_type ||
2818                                     gtp_mask->msg_len ||
2819                                     gtp_mask->teid != UINT32_MAX) {
2820                                         rte_flow_error_set(error, EINVAL,
2821                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2822                                                    item,
2823                                                    "Invalid GTP mask");
2824                                         return -rte_errno;
2825                                 }
2826
2827                                 filter->input.flow.gtp_flow.teid =
2828                                         gtp_spec->teid;
2829                                 filter->input.flow_ext.customized_pctype = true;
2830                                 cus_proto = item_type;
2831                         }
2832                         break;
2833                 case RTE_FLOW_ITEM_TYPE_SCTP:
2834                         sctp_spec = item->spec;
2835                         sctp_mask = item->mask;
2836
2837                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2838                                 pctype =
2839                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2840                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2841                                 pctype =
2842                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2843
2844                         if (sctp_spec && sctp_mask) {
2845                                 /* Check SCTP mask and update input set */
2846                                 if (sctp_mask->hdr.cksum) {
2847                                         rte_flow_error_set(error, EINVAL,
2848                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2849                                                    item,
2850                                                    "Invalid UDP mask");
2851                                         return -rte_errno;
2852                                 }
2853
2854                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2855                                         input_set |= I40E_INSET_SRC_PORT;
2856                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2857                                         input_set |= I40E_INSET_DST_PORT;
2858                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2859                                         input_set |= I40E_INSET_SCTP_VT;
2860
2861                                 /* Get filter info */
2862                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2863                                         filter->input.flow.sctp4_flow.src_port =
2864                                                 sctp_spec->hdr.src_port;
2865                                         filter->input.flow.sctp4_flow.dst_port =
2866                                                 sctp_spec->hdr.dst_port;
2867                                         filter->input.flow.sctp4_flow.verify_tag
2868                                                 = sctp_spec->hdr.tag;
2869                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2870                                         filter->input.flow.sctp6_flow.src_port =
2871                                                 sctp_spec->hdr.src_port;
2872                                         filter->input.flow.sctp6_flow.dst_port =
2873                                                 sctp_spec->hdr.dst_port;
2874                                         filter->input.flow.sctp6_flow.verify_tag
2875                                                 = sctp_spec->hdr.tag;
2876                                 }
2877                         }
2878
2879                         layer_idx = I40E_FLXPLD_L4_IDX;
2880
2881                         break;
2882                 case RTE_FLOW_ITEM_TYPE_RAW:
2883                         raw_spec = item->spec;
2884                         raw_mask = item->mask;
2885
2886                         if (!raw_spec || !raw_mask) {
2887                                 rte_flow_error_set(error, EINVAL,
2888                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2889                                                    item,
2890                                                    "NULL RAW spec/mask");
2891                                 return -rte_errno;
2892                         }
2893
2894                         if (pf->support_multi_driver) {
2895                                 rte_flow_error_set(error, ENOTSUP,
2896                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2897                                                    item,
2898                                                    "Unsupported flexible payload.");
2899                                 return -rte_errno;
2900                         }
2901
2902                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2903                         if (ret < 0)
2904                                 return ret;
2905
2906                         off_arr[raw_id] = raw_spec->offset;
2907                         len_arr[raw_id] = raw_spec->length;
2908
2909                         flex_size = 0;
2910                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2911                         flex_pit.size =
2912                                 raw_spec->length / sizeof(uint16_t);
2913                         flex_pit.dst_offset =
2914                                 next_dst_off / sizeof(uint16_t);
2915
2916                         for (i = 0; i <= raw_id; i++) {
2917                                 if (i == raw_id)
2918                                         flex_pit.src_offset +=
2919                                                 raw_spec->offset /
2920                                                 sizeof(uint16_t);
2921                                 else
2922                                         flex_pit.src_offset +=
2923                                                 (off_arr[i] + len_arr[i]) /
2924                                                 sizeof(uint16_t);
2925                                 flex_size += len_arr[i];
2926                         }
2927                         if (((flex_pit.src_offset + flex_pit.size) >=
2928                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2929                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2930                                 rte_flow_error_set(error, EINVAL,
2931                                            RTE_FLOW_ERROR_TYPE_ITEM,
2932                                            item,
2933                                            "Exceeds maxmial payload limit.");
2934                                 return -rte_errno;
2935                         }
2936
2937                         /* Store flex pit to SW */
2938                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2939                                                        layer_idx, raw_id);
2940                         if (ret < 0) {
2941                                 rte_flow_error_set(error, EINVAL,
2942                                    RTE_FLOW_ERROR_TYPE_ITEM,
2943                                    item,
2944                                    "Conflict with the first flexible rule.");
2945                                 return -rte_errno;
2946                         } else if (ret > 0)
2947                                 cfg_flex_pit = false;
2948
2949                         for (i = 0; i < raw_spec->length; i++) {
2950                                 j = i + next_dst_off;
2951                                 filter->input.flow_ext.flexbytes[j] =
2952                                         raw_spec->pattern[i];
2953                                 flex_mask[j] = raw_mask->pattern[i];
2954                         }
2955
2956                         next_dst_off += raw_spec->length;
2957                         raw_id++;
2958                         break;
2959                 case RTE_FLOW_ITEM_TYPE_VF:
2960                         vf_spec = item->spec;
2961                         filter->input.flow_ext.is_vf = 1;
2962                         filter->input.flow_ext.dst_id = vf_spec->id;
2963                         if (filter->input.flow_ext.is_vf &&
2964                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2965                                 rte_flow_error_set(error, EINVAL,
2966                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2967                                                    item,
2968                                                    "Invalid VF ID for FDIR.");
2969                                 return -rte_errno;
2970                         }
2971                         break;
2972                 default:
2973                         break;
2974                 }
2975         }
2976
2977         /* Get customized pctype value */
2978         if (filter->input.flow_ext.customized_pctype) {
2979                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2980                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2981                         rte_flow_error_set(error, EINVAL,
2982                                            RTE_FLOW_ERROR_TYPE_ITEM,
2983                                            item,
2984                                            "Unsupported pctype");
2985                         return -rte_errno;
2986                 }
2987         }
2988
2989         /* If customized pctype is not used, set fdir configuration.*/
2990         if (!filter->input.flow_ext.customized_pctype) {
2991                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2992                 if (ret == -1) {
2993                         rte_flow_error_set(error, EINVAL,
2994                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2995                                            "Conflict with the first rule's input set.");
2996                         return -rte_errno;
2997                 } else if (ret == -EINVAL) {
2998                         rte_flow_error_set(error, EINVAL,
2999                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
3000                                            "Invalid pattern mask.");
3001                         return -rte_errno;
3002                 }
3003
3004                 /* Store flex mask to SW */
3005                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
3006                 if (ret == -1) {
3007                         rte_flow_error_set(error, EINVAL,
3008                                            RTE_FLOW_ERROR_TYPE_ITEM,
3009                                            item,
3010                                            "Exceed maximal number of bitmasks");
3011                         return -rte_errno;
3012                 } else if (ret == -2) {
3013                         rte_flow_error_set(error, EINVAL,
3014                                            RTE_FLOW_ERROR_TYPE_ITEM,
3015                                            item,
3016                                            "Conflict with the first flexible rule");
3017                         return -rte_errno;
3018                 } else if (ret > 0)
3019                         cfg_flex_msk = false;
3020
3021                 if (cfg_flex_pit)
3022                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
3023
3024                 if (cfg_flex_msk)
3025                         i40e_flow_set_fdir_flex_msk(pf, pctype);
3026         }
3027
3028         filter->input.pctype = pctype;
3029
3030         return 0;
3031 }
3032
3033 /* Parse to get the action info of a FDIR filter.
3034  * FDIR action supports QUEUE or (QUEUE + MARK).
3035  */
3036 static int
3037 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
3038                             const struct rte_flow_action *actions,
3039                             struct rte_flow_error *error,
3040                             struct i40e_fdir_filter_conf *filter)
3041 {
3042         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3043         const struct rte_flow_action *act;
3044         const struct rte_flow_action_queue *act_q;
3045         const struct rte_flow_action_mark *mark_spec;
3046         uint32_t index = 0;
3047
3048         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
3049         NEXT_ITEM_OF_ACTION(act, actions, index);
3050         switch (act->type) {
3051         case RTE_FLOW_ACTION_TYPE_QUEUE:
3052                 act_q = act->conf;
3053                 filter->action.rx_queue = act_q->index;
3054                 if ((!filter->input.flow_ext.is_vf &&
3055                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3056                     (filter->input.flow_ext.is_vf &&
3057                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3058                         rte_flow_error_set(error, EINVAL,
3059                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3060                                            "Invalid queue ID for FDIR.");
3061                         return -rte_errno;
3062                 }
3063                 filter->action.behavior = I40E_FDIR_ACCEPT;
3064                 break;
3065         case RTE_FLOW_ACTION_TYPE_DROP:
3066                 filter->action.behavior = I40E_FDIR_REJECT;
3067                 break;
3068         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3069                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3070                 break;
3071         default:
3072                 rte_flow_error_set(error, EINVAL,
3073                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3074                                    "Invalid action.");
3075                 return -rte_errno;
3076         }
3077
3078         /* Check if the next non-void item is MARK or FLAG or END. */
3079         index++;
3080         NEXT_ITEM_OF_ACTION(act, actions, index);
3081         switch (act->type) {
3082         case RTE_FLOW_ACTION_TYPE_MARK:
3083                 mark_spec = act->conf;
3084                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3085                 filter->soft_id = mark_spec->id;
3086                 break;
3087         case RTE_FLOW_ACTION_TYPE_FLAG:
3088                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3089                 break;
3090         case RTE_FLOW_ACTION_TYPE_END:
3091                 return 0;
3092         default:
3093                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3094                                    act, "Invalid action.");
3095                 return -rte_errno;
3096         }
3097
3098         /* Check if the next non-void item is END */
3099         index++;
3100         NEXT_ITEM_OF_ACTION(act, actions, index);
3101         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3102                 rte_flow_error_set(error, EINVAL,
3103                                    RTE_FLOW_ERROR_TYPE_ACTION,
3104                                    act, "Invalid action.");
3105                 return -rte_errno;
3106         }
3107
3108         return 0;
3109 }
3110
3111 static int
3112 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3113                             const struct rte_flow_attr *attr,
3114                             const struct rte_flow_item pattern[],
3115                             const struct rte_flow_action actions[],
3116                             struct rte_flow_error *error,
3117                             union i40e_filter_t *filter)
3118 {
3119         struct i40e_fdir_filter_conf *fdir_filter =
3120                 &filter->fdir_filter;
3121         int ret;
3122
3123         ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3124         if (ret)
3125                 return ret;
3126
3127         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3128         if (ret)
3129                 return ret;
3130
3131         ret = i40e_flow_parse_attr(attr, error);
3132         if (ret)
3133                 return ret;
3134
3135         cons_filter_type = RTE_ETH_FILTER_FDIR;
3136
3137         if (dev->data->dev_conf.fdir_conf.mode !=
3138             RTE_FDIR_MODE_PERFECT) {
3139                 rte_flow_error_set(error, ENOTSUP,
3140                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3141                                    NULL,
3142                                    "Check the mode in fdir_conf.");
3143                 return -rte_errno;
3144         }
3145
3146         return 0;
3147 }
3148
3149 /* Parse to get the action info of a tunnel filter
3150  * Tunnel action only supports PF, VF and QUEUE.
3151  */
3152 static int
3153 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3154                               const struct rte_flow_action *actions,
3155                               struct rte_flow_error *error,
3156                               struct i40e_tunnel_filter_conf *filter)
3157 {
3158         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3159         const struct rte_flow_action *act;
3160         const struct rte_flow_action_queue *act_q;
3161         const struct rte_flow_action_vf *act_vf;
3162         uint32_t index = 0;
3163
3164         /* Check if the first non-void action is PF or VF. */
3165         NEXT_ITEM_OF_ACTION(act, actions, index);
3166         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3167             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3168                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3169                                    act, "Not supported action.");
3170                 return -rte_errno;
3171         }
3172
3173         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3174                 act_vf = act->conf;
3175                 filter->vf_id = act_vf->id;
3176                 filter->is_to_vf = 1;
3177                 if (filter->vf_id >= pf->vf_num) {
3178                         rte_flow_error_set(error, EINVAL,
3179                                    RTE_FLOW_ERROR_TYPE_ACTION,
3180                                    act, "Invalid VF ID for tunnel filter");
3181                         return -rte_errno;
3182                 }
3183         }
3184
3185         /* Check if the next non-void item is QUEUE */
3186         index++;
3187         NEXT_ITEM_OF_ACTION(act, actions, index);
3188         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3189                 act_q = act->conf;
3190                 filter->queue_id = act_q->index;
3191                 if ((!filter->is_to_vf) &&
3192                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3193                         rte_flow_error_set(error, EINVAL,
3194                                    RTE_FLOW_ERROR_TYPE_ACTION,
3195                                    act, "Invalid queue ID for tunnel filter");
3196                         return -rte_errno;
3197                 } else if (filter->is_to_vf &&
3198                            (filter->queue_id >= pf->vf_nb_qps)) {
3199                         rte_flow_error_set(error, EINVAL,
3200                                    RTE_FLOW_ERROR_TYPE_ACTION,
3201                                    act, "Invalid queue ID for tunnel filter");
3202                         return -rte_errno;
3203                 }
3204         }
3205
3206         /* Check if the next non-void item is END */
3207         index++;
3208         NEXT_ITEM_OF_ACTION(act, actions, index);
3209         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3210                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3211                                    act, "Not supported action.");
3212                 return -rte_errno;
3213         }
3214
3215         return 0;
3216 }
3217
3218 static uint16_t i40e_supported_tunnel_filter_types[] = {
3219         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3220         ETH_TUNNEL_FILTER_IVLAN,
3221         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3222         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3223         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3224         ETH_TUNNEL_FILTER_IMAC,
3225         ETH_TUNNEL_FILTER_IMAC,
3226 };
3227
3228 static int
3229 i40e_check_tunnel_filter_type(uint8_t filter_type)
3230 {
3231         uint8_t i;
3232
3233         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3234                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3235                         return 0;
3236         }
3237
3238         return -1;
3239 }
3240
3241 /* 1. Last in item should be NULL as range is not supported.
3242  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3243  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3244  * 3. Mask of fields which need to be matched should be
3245  *    filled with 1.
3246  * 4. Mask of fields which needn't to be matched should be
3247  *    filled with 0.
3248  */
3249 static int
3250 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3251                               const struct rte_flow_item *pattern,
3252                               struct rte_flow_error *error,
3253                               struct i40e_tunnel_filter_conf *filter)
3254 {
3255         const struct rte_flow_item *item = pattern;
3256         const struct rte_flow_item_eth *eth_spec;
3257         const struct rte_flow_item_eth *eth_mask;
3258         const struct rte_flow_item_vxlan *vxlan_spec;
3259         const struct rte_flow_item_vxlan *vxlan_mask;
3260         const struct rte_flow_item_vlan *vlan_spec;
3261         const struct rte_flow_item_vlan *vlan_mask;
3262         uint8_t filter_type = 0;
3263         bool is_vni_masked = 0;
3264         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3265         enum rte_flow_item_type item_type;
3266         bool vxlan_flag = 0;
3267         uint32_t tenant_id_be = 0;
3268         int ret;
3269
3270         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3271                 if (item->last) {
3272                         rte_flow_error_set(error, EINVAL,
3273                                            RTE_FLOW_ERROR_TYPE_ITEM,
3274                                            item,
3275                                            "Not support range");
3276                         return -rte_errno;
3277                 }
3278                 item_type = item->type;
3279                 switch (item_type) {
3280                 case RTE_FLOW_ITEM_TYPE_ETH:
3281                         eth_spec = item->spec;
3282                         eth_mask = item->mask;
3283
3284                         /* Check if ETH item is used for place holder.
3285                          * If yes, both spec and mask should be NULL.
3286                          * If no, both spec and mask shouldn't be NULL.
3287                          */
3288                         if ((!eth_spec && eth_mask) ||
3289                             (eth_spec && !eth_mask)) {
3290                                 rte_flow_error_set(error, EINVAL,
3291                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3292                                                    item,
3293                                                    "Invalid ether spec/mask");
3294                                 return -rte_errno;
3295                         }
3296
3297                         if (eth_spec && eth_mask) {
3298                                 /* DST address of inner MAC shouldn't be masked.
3299                                  * SRC address of Inner MAC should be masked.
3300                                  */
3301                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3302                                     !is_zero_ether_addr(&eth_mask->src) ||
3303                                     eth_mask->type) {
3304                                         rte_flow_error_set(error, EINVAL,
3305                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3306                                                    item,
3307                                                    "Invalid ether spec/mask");
3308                                         return -rte_errno;
3309                                 }
3310
3311                                 if (!vxlan_flag) {
3312                                         rte_memcpy(&filter->outer_mac,
3313                                                    &eth_spec->dst,
3314                                                    ETHER_ADDR_LEN);
3315                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3316                                 } else {
3317                                         rte_memcpy(&filter->inner_mac,
3318                                                    &eth_spec->dst,
3319                                                    ETHER_ADDR_LEN);
3320                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3321                                 }
3322                         }
3323                         break;
3324                 case RTE_FLOW_ITEM_TYPE_VLAN:
3325                         vlan_spec = item->spec;
3326                         vlan_mask = item->mask;
3327                         if (!(vlan_spec && vlan_mask) ||
3328                             vlan_mask->inner_type) {
3329                                 rte_flow_error_set(error, EINVAL,
3330                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3331                                                    item,
3332                                                    "Invalid vlan item");
3333                                 return -rte_errno;
3334                         }
3335
3336                         if (vlan_spec && vlan_mask) {
3337                                 if (vlan_mask->tci ==
3338                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3339                                         filter->inner_vlan =
3340                                               rte_be_to_cpu_16(vlan_spec->tci) &
3341                                               I40E_TCI_MASK;
3342                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3343                         }
3344                         break;
3345                 case RTE_FLOW_ITEM_TYPE_IPV4:
3346                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3347                         /* IPv4 is used to describe protocol,
3348                          * spec and mask should be NULL.
3349                          */
3350                         if (item->spec || item->mask) {
3351                                 rte_flow_error_set(error, EINVAL,
3352                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3353                                                    item,
3354                                                    "Invalid IPv4 item");
3355                                 return -rte_errno;
3356                         }
3357                         break;
3358                 case RTE_FLOW_ITEM_TYPE_IPV6:
3359                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3360                         /* IPv6 is used to describe protocol,
3361                          * spec and mask should be NULL.
3362                          */
3363                         if (item->spec || item->mask) {
3364                                 rte_flow_error_set(error, EINVAL,
3365                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3366                                                    item,
3367                                                    "Invalid IPv6 item");
3368                                 return -rte_errno;
3369                         }
3370                         break;
3371                 case RTE_FLOW_ITEM_TYPE_UDP:
3372                         /* UDP is used to describe protocol,
3373                          * spec and mask should be NULL.
3374                          */
3375                         if (item->spec || item->mask) {
3376                                 rte_flow_error_set(error, EINVAL,
3377                                            RTE_FLOW_ERROR_TYPE_ITEM,
3378                                            item,
3379                                            "Invalid UDP item");
3380                                 return -rte_errno;
3381                         }
3382                         break;
3383                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3384                         vxlan_spec = item->spec;
3385                         vxlan_mask = item->mask;
3386                         /* Check if VXLAN item is used to describe protocol.
3387                          * If yes, both spec and mask should be NULL.
3388                          * If no, both spec and mask shouldn't be NULL.
3389                          */
3390                         if ((!vxlan_spec && vxlan_mask) ||
3391                             (vxlan_spec && !vxlan_mask)) {
3392                                 rte_flow_error_set(error, EINVAL,
3393                                            RTE_FLOW_ERROR_TYPE_ITEM,
3394                                            item,
3395                                            "Invalid VXLAN item");
3396                                 return -rte_errno;
3397                         }
3398
3399                         /* Check if VNI is masked. */
3400                         if (vxlan_spec && vxlan_mask) {
3401                                 is_vni_masked =
3402                                         !!memcmp(vxlan_mask->vni, vni_mask,
3403                                                  RTE_DIM(vni_mask));
3404                                 if (is_vni_masked) {
3405                                         rte_flow_error_set(error, EINVAL,
3406                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3407                                                    item,
3408                                                    "Invalid VNI mask");
3409                                         return -rte_errno;
3410                                 }
3411
3412                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3413                                            vxlan_spec->vni, 3);
3414                                 filter->tenant_id =
3415                                         rte_be_to_cpu_32(tenant_id_be);
3416                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3417                         }
3418
3419                         vxlan_flag = 1;
3420                         break;
3421                 default:
3422                         break;
3423                 }
3424         }
3425
3426         ret = i40e_check_tunnel_filter_type(filter_type);
3427         if (ret < 0) {
3428                 rte_flow_error_set(error, EINVAL,
3429                                    RTE_FLOW_ERROR_TYPE_ITEM,
3430                                    NULL,
3431                                    "Invalid filter type");
3432                 return -rte_errno;
3433         }
3434         filter->filter_type = filter_type;
3435
3436         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3437
3438         return 0;
3439 }
3440
3441 static int
3442 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3443                              const struct rte_flow_attr *attr,
3444                              const struct rte_flow_item pattern[],
3445                              const struct rte_flow_action actions[],
3446                              struct rte_flow_error *error,
3447                              union i40e_filter_t *filter)
3448 {
3449         struct i40e_tunnel_filter_conf *tunnel_filter =
3450                 &filter->consistent_tunnel_filter;
3451         int ret;
3452
3453         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3454                                             error, tunnel_filter);
3455         if (ret)
3456                 return ret;
3457
3458         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3459         if (ret)
3460                 return ret;
3461
3462         ret = i40e_flow_parse_attr(attr, error);
3463         if (ret)
3464                 return ret;
3465
3466         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3467
3468         return ret;
3469 }
3470
3471 /* 1. Last in item should be NULL as range is not supported.
3472  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3473  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3474  * 3. Mask of fields which need to be matched should be
3475  *    filled with 1.
3476  * 4. Mask of fields which needn't to be matched should be
3477  *    filled with 0.
3478  */
3479 static int
3480 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3481                               const struct rte_flow_item *pattern,
3482                               struct rte_flow_error *error,
3483                               struct i40e_tunnel_filter_conf *filter)
3484 {
3485         const struct rte_flow_item *item = pattern;
3486         const struct rte_flow_item_eth *eth_spec;
3487         const struct rte_flow_item_eth *eth_mask;
3488         const struct rte_flow_item_nvgre *nvgre_spec;
3489         const struct rte_flow_item_nvgre *nvgre_mask;
3490         const struct rte_flow_item_vlan *vlan_spec;
3491         const struct rte_flow_item_vlan *vlan_mask;
3492         enum rte_flow_item_type item_type;
3493         uint8_t filter_type = 0;
3494         bool is_tni_masked = 0;
3495         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3496         bool nvgre_flag = 0;
3497         uint32_t tenant_id_be = 0;
3498         int ret;
3499
3500         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3501                 if (item->last) {
3502                         rte_flow_error_set(error, EINVAL,
3503                                            RTE_FLOW_ERROR_TYPE_ITEM,
3504                                            item,
3505                                            "Not support range");
3506                         return -rte_errno;
3507                 }
3508                 item_type = item->type;
3509                 switch (item_type) {
3510                 case RTE_FLOW_ITEM_TYPE_ETH:
3511                         eth_spec = item->spec;
3512                         eth_mask = item->mask;
3513
3514                         /* Check if ETH item is used for place holder.
3515                          * If yes, both spec and mask should be NULL.
3516                          * If no, both spec and mask shouldn't be NULL.
3517                          */
3518                         if ((!eth_spec && eth_mask) ||
3519                             (eth_spec && !eth_mask)) {
3520                                 rte_flow_error_set(error, EINVAL,
3521                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3522                                                    item,
3523                                                    "Invalid ether spec/mask");
3524                                 return -rte_errno;
3525                         }
3526
3527                         if (eth_spec && eth_mask) {
3528                                 /* DST address of inner MAC shouldn't be masked.
3529                                  * SRC address of Inner MAC should be masked.
3530                                  */
3531                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3532                                     !is_zero_ether_addr(&eth_mask->src) ||
3533                                     eth_mask->type) {
3534                                         rte_flow_error_set(error, EINVAL,
3535                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3536                                                    item,
3537                                                    "Invalid ether spec/mask");
3538                                         return -rte_errno;
3539                                 }
3540
3541                                 if (!nvgre_flag) {
3542                                         rte_memcpy(&filter->outer_mac,
3543                                                    &eth_spec->dst,
3544                                                    ETHER_ADDR_LEN);
3545                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3546                                 } else {
3547                                         rte_memcpy(&filter->inner_mac,
3548                                                    &eth_spec->dst,
3549                                                    ETHER_ADDR_LEN);
3550                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3551                                 }
3552                         }
3553
3554                         break;
3555                 case RTE_FLOW_ITEM_TYPE_VLAN:
3556                         vlan_spec = item->spec;
3557                         vlan_mask = item->mask;
3558                         if (!(vlan_spec && vlan_mask) ||
3559                             vlan_mask->inner_type) {
3560                                 rte_flow_error_set(error, EINVAL,
3561                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3562                                                    item,
3563                                                    "Invalid vlan item");
3564                                 return -rte_errno;
3565                         }
3566
3567                         if (vlan_spec && vlan_mask) {
3568                                 if (vlan_mask->tci ==
3569                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3570                                         filter->inner_vlan =
3571                                               rte_be_to_cpu_16(vlan_spec->tci) &
3572                                               I40E_TCI_MASK;
3573                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3574                         }
3575                         break;
3576                 case RTE_FLOW_ITEM_TYPE_IPV4:
3577                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3578                         /* IPv4 is used to describe protocol,
3579                          * spec and mask should be NULL.
3580                          */
3581                         if (item->spec || item->mask) {
3582                                 rte_flow_error_set(error, EINVAL,
3583                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3584                                                    item,
3585                                                    "Invalid IPv4 item");
3586                                 return -rte_errno;
3587                         }
3588                         break;
3589                 case RTE_FLOW_ITEM_TYPE_IPV6:
3590                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3591                         /* IPv6 is used to describe protocol,
3592                          * spec and mask should be NULL.
3593                          */
3594                         if (item->spec || item->mask) {
3595                                 rte_flow_error_set(error, EINVAL,
3596                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3597                                                    item,
3598                                                    "Invalid IPv6 item");
3599                                 return -rte_errno;
3600                         }
3601                         break;
3602                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3603                         nvgre_spec = item->spec;
3604                         nvgre_mask = item->mask;
3605                         /* Check if NVGRE item is used to describe protocol.
3606                          * If yes, both spec and mask should be NULL.
3607                          * If no, both spec and mask shouldn't be NULL.
3608                          */
3609                         if ((!nvgre_spec && nvgre_mask) ||
3610                             (nvgre_spec && !nvgre_mask)) {
3611                                 rte_flow_error_set(error, EINVAL,
3612                                            RTE_FLOW_ERROR_TYPE_ITEM,
3613                                            item,
3614                                            "Invalid NVGRE item");
3615                                 return -rte_errno;
3616                         }
3617
3618                         if (nvgre_spec && nvgre_mask) {
3619                                 is_tni_masked =
3620                                         !!memcmp(nvgre_mask->tni, tni_mask,
3621                                                  RTE_DIM(tni_mask));
3622                                 if (is_tni_masked) {
3623                                         rte_flow_error_set(error, EINVAL,
3624                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3625                                                        item,
3626                                                        "Invalid TNI mask");
3627                                         return -rte_errno;
3628                                 }
3629                                 if (nvgre_mask->protocol &&
3630                                         nvgre_mask->protocol != 0xFFFF) {
3631                                         rte_flow_error_set(error, EINVAL,
3632                                                 RTE_FLOW_ERROR_TYPE_ITEM,
3633                                                 item,
3634                                                 "Invalid NVGRE item");
3635                                         return -rte_errno;
3636                                 }
3637                                 if (nvgre_mask->c_k_s_rsvd0_ver &&
3638                                         nvgre_mask->c_k_s_rsvd0_ver !=
3639                                         rte_cpu_to_be_16(0xFFFF)) {
3640                                         rte_flow_error_set(error, EINVAL,
3641                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3642                                                    item,
3643                                                    "Invalid NVGRE item");
3644                                         return -rte_errno;
3645                                 }
3646                                 if (nvgre_spec->c_k_s_rsvd0_ver !=
3647                                         rte_cpu_to_be_16(0x2000) &&
3648                                         nvgre_mask->c_k_s_rsvd0_ver) {
3649                                         rte_flow_error_set(error, EINVAL,
3650                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3651                                                    item,
3652                                                    "Invalid NVGRE item");
3653                                         return -rte_errno;
3654                                 }
3655                                 if (nvgre_mask->protocol &&
3656                                         nvgre_spec->protocol !=
3657                                         rte_cpu_to_be_16(0x6558)) {
3658                                         rte_flow_error_set(error, EINVAL,
3659                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3660                                                    item,
3661                                                    "Invalid NVGRE item");
3662                                         return -rte_errno;
3663                                 }
3664                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3665                                            nvgre_spec->tni, 3);
3666                                 filter->tenant_id =
3667                                         rte_be_to_cpu_32(tenant_id_be);
3668                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3669                         }
3670
3671                         nvgre_flag = 1;
3672                         break;
3673                 default:
3674                         break;
3675                 }
3676         }
3677
3678         ret = i40e_check_tunnel_filter_type(filter_type);
3679         if (ret < 0) {
3680                 rte_flow_error_set(error, EINVAL,
3681                                    RTE_FLOW_ERROR_TYPE_ITEM,
3682                                    NULL,
3683                                    "Invalid filter type");
3684                 return -rte_errno;
3685         }
3686         filter->filter_type = filter_type;
3687
3688         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3689
3690         return 0;
3691 }
3692
3693 static int
3694 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3695                              const struct rte_flow_attr *attr,
3696                              const struct rte_flow_item pattern[],
3697                              const struct rte_flow_action actions[],
3698                              struct rte_flow_error *error,
3699                              union i40e_filter_t *filter)
3700 {
3701         struct i40e_tunnel_filter_conf *tunnel_filter =
3702                 &filter->consistent_tunnel_filter;
3703         int ret;
3704
3705         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3706                                             error, tunnel_filter);
3707         if (ret)
3708                 return ret;
3709
3710         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3711         if (ret)
3712                 return ret;
3713
3714         ret = i40e_flow_parse_attr(attr, error);
3715         if (ret)
3716                 return ret;
3717
3718         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3719
3720         return ret;
3721 }
3722
3723 /* 1. Last in item should be NULL as range is not supported.
3724  * 2. Supported filter types: MPLS label.
3725  * 3. Mask of fields which need to be matched should be
3726  *    filled with 1.
3727  * 4. Mask of fields which needn't to be matched should be
3728  *    filled with 0.
3729  */
3730 static int
3731 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3732                              const struct rte_flow_item *pattern,
3733                              struct rte_flow_error *error,
3734                              struct i40e_tunnel_filter_conf *filter)
3735 {
3736         const struct rte_flow_item *item = pattern;
3737         const struct rte_flow_item_mpls *mpls_spec;
3738         const struct rte_flow_item_mpls *mpls_mask;
3739         enum rte_flow_item_type item_type;
3740         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3741         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3742         uint32_t label_be = 0;
3743
3744         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3745                 if (item->last) {
3746                         rte_flow_error_set(error, EINVAL,
3747                                            RTE_FLOW_ERROR_TYPE_ITEM,
3748                                            item,
3749                                            "Not support range");
3750                         return -rte_errno;
3751                 }
3752                 item_type = item->type;
3753                 switch (item_type) {
3754                 case RTE_FLOW_ITEM_TYPE_ETH:
3755                         if (item->spec || item->mask) {
3756                                 rte_flow_error_set(error, EINVAL,
3757                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3758                                                    item,
3759                                                    "Invalid ETH item");
3760                                 return -rte_errno;
3761                         }
3762                         break;
3763                 case RTE_FLOW_ITEM_TYPE_IPV4:
3764                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3765                         /* IPv4 is used to describe protocol,
3766                          * spec and mask should be NULL.
3767                          */
3768                         if (item->spec || item->mask) {
3769                                 rte_flow_error_set(error, EINVAL,
3770                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3771                                                    item,
3772                                                    "Invalid IPv4 item");
3773                                 return -rte_errno;
3774                         }
3775                         break;
3776                 case RTE_FLOW_ITEM_TYPE_IPV6:
3777                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3778                         /* IPv6 is used to describe protocol,
3779                          * spec and mask should be NULL.
3780                          */
3781                         if (item->spec || item->mask) {
3782                                 rte_flow_error_set(error, EINVAL,
3783                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3784                                                    item,
3785                                                    "Invalid IPv6 item");
3786                                 return -rte_errno;
3787                         }
3788                         break;
3789                 case RTE_FLOW_ITEM_TYPE_UDP:
3790                         /* UDP is used to describe protocol,
3791                          * spec and mask should be NULL.
3792                          */
3793                         if (item->spec || item->mask) {
3794                                 rte_flow_error_set(error, EINVAL,
3795                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3796                                                    item,
3797                                                    "Invalid UDP item");
3798                                 return -rte_errno;
3799                         }
3800                         is_mplsoudp = 1;
3801                         break;
3802                 case RTE_FLOW_ITEM_TYPE_GRE:
3803                         /* GRE is used to describe protocol,
3804                          * spec and mask should be NULL.
3805                          */
3806                         if (item->spec || item->mask) {
3807                                 rte_flow_error_set(error, EINVAL,
3808                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3809                                                    item,
3810                                                    "Invalid GRE item");
3811                                 return -rte_errno;
3812                         }
3813                         break;
3814                 case RTE_FLOW_ITEM_TYPE_MPLS:
3815                         mpls_spec = item->spec;
3816                         mpls_mask = item->mask;
3817
3818                         if (!mpls_spec || !mpls_mask) {
3819                                 rte_flow_error_set(error, EINVAL,
3820                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3821                                                    item,
3822                                                    "Invalid MPLS item");
3823                                 return -rte_errno;
3824                         }
3825
3826                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3827                                 rte_flow_error_set(error, EINVAL,
3828                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3829                                                    item,
3830                                                    "Invalid MPLS label mask");
3831                                 return -rte_errno;
3832                         }
3833                         rte_memcpy(((uint8_t *)&label_be + 1),
3834                                    mpls_spec->label_tc_s, 3);
3835                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3836                         break;
3837                 default:
3838                         break;
3839                 }
3840         }
3841
3842         if (is_mplsoudp)
3843                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3844         else
3845                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3846
3847         return 0;
3848 }
3849
3850 static int
3851 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3852                             const struct rte_flow_attr *attr,
3853                             const struct rte_flow_item pattern[],
3854                             const struct rte_flow_action actions[],
3855                             struct rte_flow_error *error,
3856                             union i40e_filter_t *filter)
3857 {
3858         struct i40e_tunnel_filter_conf *tunnel_filter =
3859                 &filter->consistent_tunnel_filter;
3860         int ret;
3861
3862         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3863                                            error, tunnel_filter);
3864         if (ret)
3865                 return ret;
3866
3867         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3868         if (ret)
3869                 return ret;
3870
3871         ret = i40e_flow_parse_attr(attr, error);
3872         if (ret)
3873                 return ret;
3874
3875         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3876
3877         return ret;
3878 }
3879
3880 /* 1. Last in item should be NULL as range is not supported.
3881  * 2. Supported filter types: GTP TEID.
3882  * 3. Mask of fields which need to be matched should be
3883  *    filled with 1.
3884  * 4. Mask of fields which needn't to be matched should be
3885  *    filled with 0.
3886  * 5. GTP profile supports GTPv1 only.
3887  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3888  */
3889 static int
3890 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3891                             const struct rte_flow_item *pattern,
3892                             struct rte_flow_error *error,
3893                             struct i40e_tunnel_filter_conf *filter)
3894 {
3895         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3896         const struct rte_flow_item *item = pattern;
3897         const struct rte_flow_item_gtp *gtp_spec;
3898         const struct rte_flow_item_gtp *gtp_mask;
3899         enum rte_flow_item_type item_type;
3900
3901         if (!pf->gtp_support) {
3902                 rte_flow_error_set(error, EINVAL,
3903                                    RTE_FLOW_ERROR_TYPE_ITEM,
3904                                    item,
3905                                    "GTP is not supported by default.");
3906                 return -rte_errno;
3907         }
3908
3909         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3910                 if (item->last) {
3911                         rte_flow_error_set(error, EINVAL,
3912                                            RTE_FLOW_ERROR_TYPE_ITEM,
3913                                            item,
3914                                            "Not support range");
3915                         return -rte_errno;
3916                 }
3917                 item_type = item->type;
3918                 switch (item_type) {
3919                 case RTE_FLOW_ITEM_TYPE_ETH:
3920                         if (item->spec || item->mask) {
3921                                 rte_flow_error_set(error, EINVAL,
3922                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3923                                                    item,
3924                                                    "Invalid ETH item");
3925                                 return -rte_errno;
3926                         }
3927                         break;
3928                 case RTE_FLOW_ITEM_TYPE_IPV4:
3929                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3930                         /* IPv4 is used to describe protocol,
3931                          * spec and mask should be NULL.
3932                          */
3933                         if (item->spec || item->mask) {
3934                                 rte_flow_error_set(error, EINVAL,
3935                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3936                                                    item,
3937                                                    "Invalid IPv4 item");
3938                                 return -rte_errno;
3939                         }
3940                         break;
3941                 case RTE_FLOW_ITEM_TYPE_UDP:
3942                         if (item->spec || item->mask) {
3943                                 rte_flow_error_set(error, EINVAL,
3944                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3945                                                    item,
3946                                                    "Invalid UDP item");
3947                                 return -rte_errno;
3948                         }
3949                         break;
3950                 case RTE_FLOW_ITEM_TYPE_GTPC:
3951                 case RTE_FLOW_ITEM_TYPE_GTPU:
3952                         gtp_spec = item->spec;
3953                         gtp_mask = item->mask;
3954
3955                         if (!gtp_spec || !gtp_mask) {
3956                                 rte_flow_error_set(error, EINVAL,
3957                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3958                                                    item,
3959                                                    "Invalid GTP item");
3960                                 return -rte_errno;
3961                         }
3962
3963                         if (gtp_mask->v_pt_rsv_flags ||
3964                             gtp_mask->msg_type ||
3965                             gtp_mask->msg_len ||
3966                             gtp_mask->teid != UINT32_MAX) {
3967                                 rte_flow_error_set(error, EINVAL,
3968                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3969                                                    item,
3970                                                    "Invalid GTP mask");
3971                                 return -rte_errno;
3972                         }
3973
3974                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3975                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3976                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3977                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3978
3979                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3980
3981                         break;
3982                 default:
3983                         break;
3984                 }
3985         }
3986
3987         return 0;
3988 }
3989
3990 static int
3991 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3992                            const struct rte_flow_attr *attr,
3993                            const struct rte_flow_item pattern[],
3994                            const struct rte_flow_action actions[],
3995                            struct rte_flow_error *error,
3996                            union i40e_filter_t *filter)
3997 {
3998         struct i40e_tunnel_filter_conf *tunnel_filter =
3999                 &filter->consistent_tunnel_filter;
4000         int ret;
4001
4002         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
4003                                           error, tunnel_filter);
4004         if (ret)
4005                 return ret;
4006
4007         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4008         if (ret)
4009                 return ret;
4010
4011         ret = i40e_flow_parse_attr(attr, error);
4012         if (ret)
4013                 return ret;
4014
4015         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4016
4017         return ret;
4018 }
4019
4020 /* 1. Last in item should be NULL as range is not supported.
4021  * 2. Supported filter types: QINQ.
4022  * 3. Mask of fields which need to be matched should be
4023  *    filled with 1.
4024  * 4. Mask of fields which needn't to be matched should be
4025  *    filled with 0.
4026  */
4027 static int
4028 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
4029                               const struct rte_flow_item *pattern,
4030                               struct rte_flow_error *error,
4031                               struct i40e_tunnel_filter_conf *filter)
4032 {
4033         const struct rte_flow_item *item = pattern;
4034         const struct rte_flow_item_vlan *vlan_spec = NULL;
4035         const struct rte_flow_item_vlan *vlan_mask = NULL;
4036         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
4037         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
4038         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
4039         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
4040
4041         enum rte_flow_item_type item_type;
4042         bool vlan_flag = 0;
4043
4044         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4045                 if (item->last) {
4046                         rte_flow_error_set(error, EINVAL,
4047                                            RTE_FLOW_ERROR_TYPE_ITEM,
4048                                            item,
4049                                            "Not support range");
4050                         return -rte_errno;
4051                 }
4052                 item_type = item->type;
4053                 switch (item_type) {
4054                 case RTE_FLOW_ITEM_TYPE_ETH:
4055                         if (item->spec || item->mask) {
4056                                 rte_flow_error_set(error, EINVAL,
4057                                                    RTE_FLOW_ERROR_TYPE_ITEM,
4058                                                    item,
4059                                                    "Invalid ETH item");
4060                                 return -rte_errno;
4061                         }
4062                         break;
4063                 case RTE_FLOW_ITEM_TYPE_VLAN:
4064                         vlan_spec = item->spec;
4065                         vlan_mask = item->mask;
4066
4067                         if (!(vlan_spec && vlan_mask) ||
4068                             vlan_mask->inner_type) {
4069                                 rte_flow_error_set(error, EINVAL,
4070                                            RTE_FLOW_ERROR_TYPE_ITEM,
4071                                            item,
4072                                            "Invalid vlan item");
4073                                 return -rte_errno;
4074                         }
4075
4076                         if (!vlan_flag) {
4077                                 o_vlan_spec = vlan_spec;
4078                                 o_vlan_mask = vlan_mask;
4079                                 vlan_flag = 1;
4080                         } else {
4081                                 i_vlan_spec = vlan_spec;
4082                                 i_vlan_mask = vlan_mask;
4083                                 vlan_flag = 0;
4084                         }
4085                         break;
4086
4087                 default:
4088                         break;
4089                 }
4090         }
4091
4092         /* Get filter specification */
4093         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4094                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4095                         (i_vlan_mask != NULL) &&
4096                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4097                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4098                         & I40E_TCI_MASK;
4099                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4100                         & I40E_TCI_MASK;
4101         } else {
4102                         rte_flow_error_set(error, EINVAL,
4103                                            RTE_FLOW_ERROR_TYPE_ITEM,
4104                                            NULL,
4105                                            "Invalid filter type");
4106                         return -rte_errno;
4107         }
4108
4109         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4110         return 0;
4111 }
4112
4113 static int
4114 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4115                               const struct rte_flow_attr *attr,
4116                               const struct rte_flow_item pattern[],
4117                               const struct rte_flow_action actions[],
4118                               struct rte_flow_error *error,
4119                               union i40e_filter_t *filter)
4120 {
4121         struct i40e_tunnel_filter_conf *tunnel_filter =
4122                 &filter->consistent_tunnel_filter;
4123         int ret;
4124
4125         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4126                                              error, tunnel_filter);
4127         if (ret)
4128                 return ret;
4129
4130         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4131         if (ret)
4132                 return ret;
4133
4134         ret = i40e_flow_parse_attr(attr, error);
4135         if (ret)
4136                 return ret;
4137
4138         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4139
4140         return ret;
4141 }
4142
4143 /**
4144  * This function is used to do configuration i40e existing RSS with rte_flow.
4145  * It also enable queue region configuration using flow API for i40e.
4146  * pattern can be used indicate what parameters will be include in flow,
4147  * like user_priority or flowtype for queue region or HASH function for RSS.
4148  * Action is used to transmit parameter like queue index and HASH
4149  * function for RSS, or flowtype for queue region configuration.
4150  * For example:
4151  * pattern:
4152  * Case 1: only ETH, indicate  flowtype for queue region will be parsed.
4153  * Case 2: only VLAN, indicate user_priority for queue region will be parsed.
4154  * Case 3: none, indicate RSS related will be parsed in action.
4155  * Any pattern other the ETH or VLAN will be treated as invalid except END.
4156  * So, pattern choice is depened on the purpose of configuration of
4157  * that flow.
4158  * action:
4159  * action RSS will be uaed to transmit valid parameter with
4160  * struct rte_flow_action_rss for all the 3 case.
4161  */
4162 static int
4163 i40e_flow_parse_rss_pattern(__rte_unused struct rte_eth_dev *dev,
4164                              const struct rte_flow_item *pattern,
4165                              struct rte_flow_error *error,
4166                              uint8_t *action_flag,
4167                              struct i40e_queue_regions *info)
4168 {
4169         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
4170         const struct rte_flow_item *item = pattern;
4171         enum rte_flow_item_type item_type;
4172
4173         if (item->type == RTE_FLOW_ITEM_TYPE_END)
4174                 return 0;
4175
4176         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
4177                 if (item->last) {
4178                         rte_flow_error_set(error, EINVAL,
4179                                            RTE_FLOW_ERROR_TYPE_ITEM,
4180                                            item,
4181                                            "Not support range");
4182                         return -rte_errno;
4183                 }
4184                 item_type = item->type;
4185                 switch (item_type) {
4186                 case RTE_FLOW_ITEM_TYPE_ETH:
4187                         *action_flag = 1;
4188                         break;
4189                 case RTE_FLOW_ITEM_TYPE_VLAN:
4190                         vlan_spec = item->spec;
4191                         vlan_mask = item->mask;
4192                         if (vlan_spec && vlan_mask) {
4193                                 if (vlan_mask->tci ==
4194                                         rte_cpu_to_be_16(I40E_TCI_MASK)) {
4195                                         info->region[0].user_priority[0] =
4196                                                 (rte_be_to_cpu_16(
4197                                                 vlan_spec->tci) >> 13) & 0x7;
4198                                         info->region[0].user_priority_num = 1;
4199                                         info->queue_region_number = 1;
4200                                         *action_flag = 0;
4201                                 }
4202                         }
4203                         break;
4204                 default:
4205                         rte_flow_error_set(error, EINVAL,
4206                                         RTE_FLOW_ERROR_TYPE_ITEM,
4207                                         item,
4208                                         "Not support range");
4209                         return -rte_errno;
4210                 }
4211         }
4212
4213         return 0;
4214 }
4215
4216 /**
4217  * This function is used to parse rss queue index, total queue number and
4218  * hash functions, If the purpose of this configuration is for queue region
4219  * configuration, it will set queue_region_conf flag to TRUE, else to FALSE.
4220  * In queue region configuration, it also need to parse hardware flowtype
4221  * and user_priority from configuration, it will also cheeck the validity
4222  * of these parameters. For example, The queue region sizes should
4223  * be any of the following values: 1, 2, 4, 8, 16, 32, 64, the
4224  * hw_flowtype or PCTYPE max index should be 63, the user priority
4225  * max index should be 7, and so on. And also, queue index should be
4226  * continuous sequence and queue region index should be part of rss
4227  * queue index for this port.
4228  */
4229 static int
4230 i40e_flow_parse_rss_action(struct rte_eth_dev *dev,
4231                             const struct rte_flow_action *actions,
4232                             struct rte_flow_error *error,
4233                             uint8_t action_flag,
4234                             struct i40e_queue_regions *conf_info,
4235                             union i40e_filter_t *filter)
4236 {
4237         const struct rte_flow_action *act;
4238         const struct rte_flow_action_rss *rss;
4239         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4240         struct i40e_queue_regions *info = &pf->queue_region;
4241         struct i40e_rte_flow_rss_conf *rss_config =
4242                         &filter->rss_conf;
4243         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4244         uint16_t i, j, n, tmp;
4245         uint32_t index = 0;
4246         uint64_t hf_bit = 1;
4247
4248         NEXT_ITEM_OF_ACTION(act, actions, index);
4249         rss = act->conf;
4250
4251         /**
4252          * rss only supports forwarding,
4253          * check if the first not void action is RSS.
4254          */
4255         if (act->type != RTE_FLOW_ACTION_TYPE_RSS) {
4256                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4257                 rte_flow_error_set(error, EINVAL,
4258                         RTE_FLOW_ERROR_TYPE_ACTION,
4259                         act, "Not supported action.");
4260                 return -rte_errno;
4261         }
4262
4263         if (action_flag) {
4264                 for (n = 0; n < 64; n++) {
4265                         if (rss->types & (hf_bit << n)) {
4266                                 conf_info->region[0].hw_flowtype[0] = n;
4267                                 conf_info->region[0].flowtype_num = 1;
4268                                 conf_info->queue_region_number = 1;
4269                                 break;
4270                         }
4271                 }
4272         }
4273
4274         /**
4275          * Do some queue region related parameters check
4276          * in order to keep queue index for queue region to be
4277          * continuous sequence and also to be part of RSS
4278          * queue index for this port.
4279          */
4280         if (conf_info->queue_region_number) {
4281                 for (i = 0; i < rss->queue_num; i++) {
4282                         for (j = 0; j < rss_info->conf.queue_num; j++) {
4283                                 if (rss->queue[i] == rss_info->conf.queue[j])
4284                                         break;
4285                         }
4286                         if (j == rss_info->conf.queue_num) {
4287                                 rte_flow_error_set(error, EINVAL,
4288                                         RTE_FLOW_ERROR_TYPE_ACTION,
4289                                         act,
4290                                         "no valid queues");
4291                                 return -rte_errno;
4292                         }
4293                 }
4294
4295                 for (i = 0; i < rss->queue_num - 1; i++) {
4296                         if (rss->queue[i + 1] != rss->queue[i] + 1) {
4297                                 rte_flow_error_set(error, EINVAL,
4298                                         RTE_FLOW_ERROR_TYPE_ACTION,
4299                                         act,
4300                                         "no valid queues");
4301                                 return -rte_errno;
4302                         }
4303                 }
4304         }
4305
4306         /* Parse queue region related parameters from configuration */
4307         for (n = 0; n < conf_info->queue_region_number; n++) {
4308                 if (conf_info->region[n].user_priority_num ||
4309                                 conf_info->region[n].flowtype_num) {
4310                         if (!((rte_is_power_of_2(rss->queue_num)) &&
4311                                         rss->queue_num <= 64)) {
4312                                 rte_flow_error_set(error, EINVAL,
4313                                         RTE_FLOW_ERROR_TYPE_ACTION,
4314                                         act,
4315                                         "The region sizes should be any of the following values: 1, 2, 4, 8, 16, 32, 64 as long as the "
4316                                         "total number of queues do not exceed the VSI allocation");
4317                                 return -rte_errno;
4318                         }
4319
4320                         if (conf_info->region[n].user_priority[n] >=
4321                                         I40E_MAX_USER_PRIORITY) {
4322                                 rte_flow_error_set(error, EINVAL,
4323                                         RTE_FLOW_ERROR_TYPE_ACTION,
4324                                         act,
4325                                         "the user priority max index is 7");
4326                                 return -rte_errno;
4327                         }
4328
4329                         if (conf_info->region[n].hw_flowtype[n] >=
4330                                         I40E_FILTER_PCTYPE_MAX) {
4331                                 rte_flow_error_set(error, EINVAL,
4332                                         RTE_FLOW_ERROR_TYPE_ACTION,
4333                                         act,
4334                                         "the hw_flowtype or PCTYPE max index is 63");
4335                                 return -rte_errno;
4336                         }
4337
4338                         for (i = 0; i < info->queue_region_number; i++) {
4339                                 if (info->region[i].queue_num ==
4340                                     rss->queue_num &&
4341                                         info->region[i].queue_start_index ==
4342                                                 rss->queue[0])
4343                                         break;
4344                         }
4345
4346                         if (i == info->queue_region_number) {
4347                                 if (i > I40E_REGION_MAX_INDEX) {
4348                                         rte_flow_error_set(error, EINVAL,
4349                                                 RTE_FLOW_ERROR_TYPE_ACTION,
4350                                                 act,
4351                                                 "the queue region max index is 7");
4352                                         return -rte_errno;
4353                                 }
4354
4355                                 info->region[i].queue_num =
4356                                         rss->queue_num;
4357                                 info->region[i].queue_start_index =
4358                                         rss->queue[0];
4359                                 info->region[i].region_id =
4360                                         info->queue_region_number;
4361
4362                                 j = info->region[i].user_priority_num;
4363                                 tmp = conf_info->region[n].user_priority[0];
4364                                 if (conf_info->region[n].user_priority_num) {
4365                                         info->region[i].user_priority[j] = tmp;
4366                                         info->region[i].user_priority_num++;
4367                                 }
4368
4369                                 j = info->region[i].flowtype_num;
4370                                 tmp = conf_info->region[n].hw_flowtype[0];
4371                                 if (conf_info->region[n].flowtype_num) {
4372                                         info->region[i].hw_flowtype[j] = tmp;
4373                                         info->region[i].flowtype_num++;
4374                                 }
4375                                 info->queue_region_number++;
4376                         } else {
4377                                 j = info->region[i].user_priority_num;
4378                                 tmp = conf_info->region[n].user_priority[0];
4379                                 if (conf_info->region[n].user_priority_num) {
4380                                         info->region[i].user_priority[j] = tmp;
4381                                         info->region[i].user_priority_num++;
4382                                 }
4383
4384                                 j = info->region[i].flowtype_num;
4385                                 tmp = conf_info->region[n].hw_flowtype[0];
4386                                 if (conf_info->region[n].flowtype_num) {
4387                                         info->region[i].hw_flowtype[j] = tmp;
4388                                         info->region[i].flowtype_num++;
4389                                 }
4390                         }
4391                 }
4392
4393                 rss_config->queue_region_conf = TRUE;
4394         }
4395
4396         /**
4397          * Return function if this flow is used for queue region configuration
4398          */
4399         if (rss_config->queue_region_conf)
4400                 return 0;
4401
4402         if (!rss || !rss->queue_num) {
4403                 rte_flow_error_set(error, EINVAL,
4404                                 RTE_FLOW_ERROR_TYPE_ACTION,
4405                                 act,
4406                                 "no valid queues");
4407                 return -rte_errno;
4408         }
4409
4410         for (n = 0; n < rss->queue_num; n++) {
4411                 if (rss->queue[n] >= dev->data->nb_rx_queues) {
4412                         rte_flow_error_set(error, EINVAL,
4413                                    RTE_FLOW_ERROR_TYPE_ACTION,
4414                                    act,
4415                                    "queue id > max number of queues");
4416                         return -rte_errno;
4417                 }
4418         }
4419
4420         /* Parse RSS related parameters from configuration */
4421         if (rss->func != RTE_ETH_HASH_FUNCTION_DEFAULT)
4422                 return rte_flow_error_set
4423                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4424                          "non-default RSS hash functions are not supported");
4425         if (rss->level)
4426                 return rte_flow_error_set
4427                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4428                          "a nonzero RSS encapsulation level is not supported");
4429         if (rss->key_len && rss->key_len > RTE_DIM(rss_config->key))
4430                 return rte_flow_error_set
4431                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4432                          "RSS hash key too large");
4433         if (rss->queue_num > RTE_DIM(rss_config->queue))
4434                 return rte_flow_error_set
4435                         (error, ENOTSUP, RTE_FLOW_ERROR_TYPE_ACTION, act,
4436                          "too many queues for RSS context");
4437         if (i40e_rss_conf_init(rss_config, rss))
4438                 return rte_flow_error_set
4439                         (error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION, act,
4440                          "RSS context initialization failure");
4441
4442         index++;
4443
4444         /* check if the next not void action is END */
4445         NEXT_ITEM_OF_ACTION(act, actions, index);
4446         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
4447                 memset(rss_config, 0, sizeof(struct i40e_rte_flow_rss_conf));
4448                 rte_flow_error_set(error, EINVAL,
4449                         RTE_FLOW_ERROR_TYPE_ACTION,
4450                         act, "Not supported action.");
4451                 return -rte_errno;
4452         }
4453         rss_config->queue_region_conf = FALSE;
4454
4455         return 0;
4456 }
4457
4458 static int
4459 i40e_parse_rss_filter(struct rte_eth_dev *dev,
4460                         const struct rte_flow_attr *attr,
4461                         const struct rte_flow_item pattern[],
4462                         const struct rte_flow_action actions[],
4463                         union i40e_filter_t *filter,
4464                         struct rte_flow_error *error)
4465 {
4466         int ret;
4467         struct i40e_queue_regions info;
4468         uint8_t action_flag = 0;
4469
4470         memset(&info, 0, sizeof(struct i40e_queue_regions));
4471
4472         ret = i40e_flow_parse_rss_pattern(dev, pattern,
4473                                         error, &action_flag, &info);
4474         if (ret)
4475                 return ret;
4476
4477         ret = i40e_flow_parse_rss_action(dev, actions, error,
4478                                         action_flag, &info, filter);
4479         if (ret)
4480                 return ret;
4481
4482         ret = i40e_flow_parse_attr(attr, error);
4483         if (ret)
4484                 return ret;
4485
4486         cons_filter_type = RTE_ETH_FILTER_HASH;
4487
4488         return 0;
4489 }
4490
4491 static int
4492 i40e_config_rss_filter_set(struct rte_eth_dev *dev,
4493                 struct i40e_rte_flow_rss_conf *conf)
4494 {
4495         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4496         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4497         int ret;
4498
4499         if (conf->queue_region_conf) {
4500                 ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 1);
4501                 conf->queue_region_conf = 0;
4502         } else {
4503                 ret = i40e_config_rss_filter(pf, conf, 1);
4504         }
4505         return ret;
4506 }
4507
4508 static int
4509 i40e_config_rss_filter_del(struct rte_eth_dev *dev,
4510                 struct i40e_rte_flow_rss_conf *conf)
4511 {
4512         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4513         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4514
4515         i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4516
4517         i40e_config_rss_filter(pf, conf, 0);
4518         return 0;
4519 }
4520
4521 static int
4522 i40e_flow_validate(struct rte_eth_dev *dev,
4523                    const struct rte_flow_attr *attr,
4524                    const struct rte_flow_item pattern[],
4525                    const struct rte_flow_action actions[],
4526                    struct rte_flow_error *error)
4527 {
4528         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4529         parse_filter_t parse_filter;
4530         uint32_t item_num = 0; /* non-void item number of pattern*/
4531         uint32_t i = 0;
4532         bool flag = false;
4533         int ret = I40E_NOT_SUPPORTED;
4534
4535         if (!pattern) {
4536                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4537                                    NULL, "NULL pattern.");
4538                 return -rte_errno;
4539         }
4540
4541         if (!actions) {
4542                 rte_flow_error_set(error, EINVAL,
4543                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4544                                    NULL, "NULL action.");
4545                 return -rte_errno;
4546         }
4547
4548         if (!attr) {
4549                 rte_flow_error_set(error, EINVAL,
4550                                    RTE_FLOW_ERROR_TYPE_ATTR,
4551                                    NULL, "NULL attribute.");
4552                 return -rte_errno;
4553         }
4554
4555         memset(&cons_filter, 0, sizeof(cons_filter));
4556
4557         /* Get the non-void item of action */
4558         while ((actions + i)->type == RTE_FLOW_ACTION_TYPE_VOID)
4559                 i++;
4560
4561         if ((actions + i)->type == RTE_FLOW_ACTION_TYPE_RSS) {
4562                 ret = i40e_parse_rss_filter(dev, attr, pattern,
4563                                         actions, &cons_filter, error);
4564                 return ret;
4565         }
4566
4567         i = 0;
4568         /* Get the non-void item number of pattern */
4569         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4570                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4571                         item_num++;
4572                 i++;
4573         }
4574         item_num++;
4575
4576         items = rte_zmalloc("i40e_pattern",
4577                             item_num * sizeof(struct rte_flow_item), 0);
4578         if (!items) {
4579                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4580                                    NULL, "No memory for PMD internal items.");
4581                 return -ENOMEM;
4582         }
4583
4584         i40e_pattern_skip_void_item(items, pattern);
4585
4586         i = 0;
4587         do {
4588                 parse_filter = i40e_find_parse_filter_func(items, &i);
4589                 if (!parse_filter && !flag) {
4590                         rte_flow_error_set(error, EINVAL,
4591                                            RTE_FLOW_ERROR_TYPE_ITEM,
4592                                            pattern, "Unsupported pattern");
4593                         rte_free(items);
4594                         return -rte_errno;
4595                 }
4596                 if (parse_filter)
4597                         ret = parse_filter(dev, attr, items, actions,
4598                                            error, &cons_filter);
4599                 flag = true;
4600         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4601
4602         rte_free(items);
4603
4604         return ret;
4605 }
4606
4607 static struct rte_flow *
4608 i40e_flow_create(struct rte_eth_dev *dev,
4609                  const struct rte_flow_attr *attr,
4610                  const struct rte_flow_item pattern[],
4611                  const struct rte_flow_action actions[],
4612                  struct rte_flow_error *error)
4613 {
4614         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4615         struct rte_flow *flow;
4616         int ret;
4617
4618         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4619         if (!flow) {
4620                 rte_flow_error_set(error, ENOMEM,
4621                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4622                                    "Failed to allocate memory");
4623                 return flow;
4624         }
4625
4626         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4627         if (ret < 0)
4628                 return NULL;
4629
4630         switch (cons_filter_type) {
4631         case RTE_ETH_FILTER_ETHERTYPE:
4632                 ret = i40e_ethertype_filter_set(pf,
4633                                         &cons_filter.ethertype_filter, 1);
4634                 if (ret)
4635                         goto free_flow;
4636                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4637                                         i40e_ethertype_filter_list);
4638                 break;
4639         case RTE_ETH_FILTER_FDIR:
4640                 ret = i40e_flow_add_del_fdir_filter(dev,
4641                                        &cons_filter.fdir_filter, 1);
4642                 if (ret)
4643                         goto free_flow;
4644                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4645                                         i40e_fdir_filter_list);
4646                 break;
4647         case RTE_ETH_FILTER_TUNNEL:
4648                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4649                             &cons_filter.consistent_tunnel_filter, 1);
4650                 if (ret)
4651                         goto free_flow;
4652                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4653                                         i40e_tunnel_filter_list);
4654                 break;
4655         case RTE_ETH_FILTER_HASH:
4656                 ret = i40e_config_rss_filter_set(dev,
4657                             &cons_filter.rss_conf);
4658                 if (ret)
4659                         goto free_flow;
4660                 flow->rule = &pf->rss_info;
4661                 break;
4662         default:
4663                 goto free_flow;
4664         }
4665
4666         flow->filter_type = cons_filter_type;
4667         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4668         return flow;
4669
4670 free_flow:
4671         rte_flow_error_set(error, -ret,
4672                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4673                            "Failed to create flow.");
4674         rte_free(flow);
4675         return NULL;
4676 }
4677
4678 static int
4679 i40e_flow_destroy(struct rte_eth_dev *dev,
4680                   struct rte_flow *flow,
4681                   struct rte_flow_error *error)
4682 {
4683         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4684         enum rte_filter_type filter_type = flow->filter_type;
4685         int ret = 0;
4686
4687         switch (filter_type) {
4688         case RTE_ETH_FILTER_ETHERTYPE:
4689                 ret = i40e_flow_destroy_ethertype_filter(pf,
4690                          (struct i40e_ethertype_filter *)flow->rule);
4691                 break;
4692         case RTE_ETH_FILTER_TUNNEL:
4693                 ret = i40e_flow_destroy_tunnel_filter(pf,
4694                               (struct i40e_tunnel_filter *)flow->rule);
4695                 break;
4696         case RTE_ETH_FILTER_FDIR:
4697                 ret = i40e_flow_add_del_fdir_filter(dev,
4698                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4699                 break;
4700         case RTE_ETH_FILTER_HASH:
4701                 ret = i40e_config_rss_filter_del(dev,
4702                            (struct i40e_rte_flow_rss_conf *)flow->rule);
4703                 break;
4704         default:
4705                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4706                             filter_type);
4707                 ret = -EINVAL;
4708                 break;
4709         }
4710
4711         if (!ret) {
4712                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4713                 rte_free(flow);
4714         } else
4715                 rte_flow_error_set(error, -ret,
4716                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4717                                    "Failed to destroy flow.");
4718
4719         return ret;
4720 }
4721
4722 static int
4723 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4724                                    struct i40e_ethertype_filter *filter)
4725 {
4726         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4727         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4728         struct i40e_ethertype_filter *node;
4729         struct i40e_control_filter_stats stats;
4730         uint16_t flags = 0;
4731         int ret = 0;
4732
4733         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4734                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4735         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4736                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4737         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4738
4739         memset(&stats, 0, sizeof(stats));
4740         ret = i40e_aq_add_rem_control_packet_filter(hw,
4741                                     filter->input.mac_addr.addr_bytes,
4742                                     filter->input.ether_type,
4743                                     flags, pf->main_vsi->seid,
4744                                     filter->queue, 0, &stats, NULL);
4745         if (ret < 0)
4746                 return ret;
4747
4748         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4749         if (!node)
4750                 return -EINVAL;
4751
4752         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4753
4754         return ret;
4755 }
4756
4757 static int
4758 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4759                                 struct i40e_tunnel_filter *filter)
4760 {
4761         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4762         struct i40e_vsi *vsi;
4763         struct i40e_pf_vf *vf;
4764         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4765         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4766         struct i40e_tunnel_filter *node;
4767         bool big_buffer = 0;
4768         int ret = 0;
4769
4770         memset(&cld_filter, 0, sizeof(cld_filter));
4771         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4772                         (struct ether_addr *)&cld_filter.element.outer_mac);
4773         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4774                         (struct ether_addr *)&cld_filter.element.inner_mac);
4775         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4776         cld_filter.element.flags = filter->input.flags;
4777         cld_filter.element.tenant_id = filter->input.tenant_id;
4778         cld_filter.element.queue_number = filter->queue;
4779         rte_memcpy(cld_filter.general_fields,
4780                    filter->input.general_fields,
4781                    sizeof(cld_filter.general_fields));
4782
4783         if (!filter->is_to_vf)
4784                 vsi = pf->main_vsi;
4785         else {
4786                 vf = &pf->vfs[filter->vf_id];
4787                 vsi = vf->vsi;
4788         }
4789
4790         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4791             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4792             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4793             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4794             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4795             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4796                 big_buffer = 1;
4797
4798         if (big_buffer)
4799                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4800                                                               &cld_filter, 1);
4801         else
4802                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4803                                                    &cld_filter.element, 1);
4804         if (ret < 0)
4805                 return -ENOTSUP;
4806
4807         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4808         if (!node)
4809                 return -EINVAL;
4810
4811         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4812
4813         return ret;
4814 }
4815
4816 static int
4817 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4818 {
4819         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4820         int ret;
4821
4822         ret = i40e_flow_flush_fdir_filter(pf);
4823         if (ret) {
4824                 rte_flow_error_set(error, -ret,
4825                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4826                                    "Failed to flush FDIR flows.");
4827                 return -rte_errno;
4828         }
4829
4830         ret = i40e_flow_flush_ethertype_filter(pf);
4831         if (ret) {
4832                 rte_flow_error_set(error, -ret,
4833                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4834                                    "Failed to ethertype flush flows.");
4835                 return -rte_errno;
4836         }
4837
4838         ret = i40e_flow_flush_tunnel_filter(pf);
4839         if (ret) {
4840                 rte_flow_error_set(error, -ret,
4841                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4842                                    "Failed to flush tunnel flows.");
4843                 return -rte_errno;
4844         }
4845
4846         ret = i40e_flow_flush_rss_filter(dev);
4847         if (ret) {
4848                 rte_flow_error_set(error, -ret,
4849                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4850                                    "Failed to flush rss flows.");
4851                 return -rte_errno;
4852         }
4853
4854         return ret;
4855 }
4856
4857 static int
4858 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4859 {
4860         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4861         struct i40e_fdir_info *fdir_info = &pf->fdir;
4862         struct i40e_fdir_filter *fdir_filter;
4863         enum i40e_filter_pctype pctype;
4864         struct rte_flow *flow;
4865         void *temp;
4866         int ret;
4867
4868         ret = i40e_fdir_flush(dev);
4869         if (!ret) {
4870                 /* Delete FDIR filters in FDIR list. */
4871                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4872                         ret = i40e_sw_fdir_filter_del(pf,
4873                                                       &fdir_filter->fdir.input);
4874                         if (ret < 0)
4875                                 return ret;
4876                 }
4877
4878                 /* Delete FDIR flows in flow list. */
4879                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4880                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4881                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4882                                 rte_free(flow);
4883                         }
4884                 }
4885
4886                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4887                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4888                         pf->fdir.inset_flag[pctype] = 0;
4889         }
4890
4891         return ret;
4892 }
4893
4894 /* Flush all ethertype filters */
4895 static int
4896 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4897 {
4898         struct i40e_ethertype_filter_list
4899                 *ethertype_list = &pf->ethertype.ethertype_list;
4900         struct i40e_ethertype_filter *filter;
4901         struct rte_flow *flow;
4902         void *temp;
4903         int ret = 0;
4904
4905         while ((filter = TAILQ_FIRST(ethertype_list))) {
4906                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4907                 if (ret)
4908                         return ret;
4909         }
4910
4911         /* Delete ethertype flows in flow list. */
4912         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4913                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4914                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4915                         rte_free(flow);
4916                 }
4917         }
4918
4919         return ret;
4920 }
4921
4922 /* Flush all tunnel filters */
4923 static int
4924 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4925 {
4926         struct i40e_tunnel_filter_list
4927                 *tunnel_list = &pf->tunnel.tunnel_list;
4928         struct i40e_tunnel_filter *filter;
4929         struct rte_flow *flow;
4930         void *temp;
4931         int ret = 0;
4932
4933         while ((filter = TAILQ_FIRST(tunnel_list))) {
4934                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4935                 if (ret)
4936                         return ret;
4937         }
4938
4939         /* Delete tunnel flows in flow list. */
4940         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4941                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4942                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4943                         rte_free(flow);
4944                 }
4945         }
4946
4947         return ret;
4948 }
4949
4950 /* remove the rss filter */
4951 static int
4952 i40e_flow_flush_rss_filter(struct rte_eth_dev *dev)
4953 {
4954         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4955         struct i40e_rte_flow_rss_conf *rss_info = &pf->rss_info;
4956         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4957         int32_t ret = -EINVAL;
4958
4959         ret = i40e_flush_queue_region_all_conf(dev, hw, pf, 0);
4960
4961         if (rss_info->conf.queue_num)
4962                 ret = i40e_config_rss_filter(pf, rss_info, FALSE);
4963         return ret;
4964 }