drivers/net/i40e/i40e_flow.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2016-2017 Intel Corporation
   3  */
   4
   5 #include <sys/queue.h>
   6 #include <stdio.h>
   7 #include <errno.h>
   8 #include <stdint.h>
   9 #include <string.h>
  10 #include <unistd.h>
  11 #include <stdarg.h>
  12
  13 #include <rte_ether.h>
  14 #include <rte_ethdev.h>
  15 #include <rte_log.h>
  16 #include <rte_malloc.h>
  17 #include <rte_eth_ctrl.h>
  18 #include <rte_tailq.h>
  19 #include <rte_flow_driver.h>
  20
  21 #include "i40e_logs.h"
  22 #include "base/i40e_type.h"
  23 #include "base/i40e_prototype.h"
  24 #include "i40e_ethdev.h"
  25
  26 #define I40E_IPV6_TC_MASK       (0xFF << I40E_FDIR_IPv6_TC_OFFSET)
  27 #define I40E_IPV6_FRAG_HEADER   44
  28 #define I40E_TENANT_ARRAY_NUM   3
  29 #define I40E_TCI_MASK           0xFFFF
  30
  31 static int i40e_flow_validate(struct rte_eth_dev *dev,
  32                               const struct rte_flow_attr *attr,
  33                               const struct rte_flow_item pattern[],
  34                               const struct rte_flow_action actions[],
  35                               struct rte_flow_error *error);
  36 static struct rte_flow *i40e_flow_create(struct rte_eth_dev *dev,
  37                                          const struct rte_flow_attr *attr,
  38                                          const struct rte_flow_item pattern[],
  39                                          const struct rte_flow_action actions[],
  40                                          struct rte_flow_error *error);
  41 static int i40e_flow_destroy(struct rte_eth_dev *dev,
  42                              struct rte_flow *flow,
  43                              struct rte_flow_error *error);
  44 static int i40e_flow_flush(struct rte_eth_dev *dev,
  45                            struct rte_flow_error *error);
  46 static int
  47 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
  48                                   const struct rte_flow_item *pattern,
  49                                   struct rte_flow_error *error,
  50                                   struct rte_eth_ethertype_filter *filter);
  51 static int i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
  52                                     const struct rte_flow_action *actions,
  53                                     struct rte_flow_error *error,
  54                                     struct rte_eth_ethertype_filter *filter);
  55 static int i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
  56                                         const struct rte_flow_item *pattern,
  57                                         struct rte_flow_error *error,
  58                                         struct i40e_fdir_filter_conf *filter);
  59 static int i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
  60                                        const struct rte_flow_action *actions,
  61                                        struct rte_flow_error *error,
  62                                        struct i40e_fdir_filter_conf *filter);
  63 static int i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
  64                                  const struct rte_flow_action *actions,
  65                                  struct rte_flow_error *error,
  66                                  struct i40e_tunnel_filter_conf *filter);
  67 static int i40e_flow_parse_attr(const struct rte_flow_attr *attr,
  68                                 struct rte_flow_error *error);
  69 static int i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
  70                                     const struct rte_flow_attr *attr,
  71                                     const struct rte_flow_item pattern[],
  72                                     const struct rte_flow_action actions[],
  73                                     struct rte_flow_error *error,
  74                                     union i40e_filter_t *filter);
  75 static int i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
  76                                        const struct rte_flow_attr *attr,
  77                                        const struct rte_flow_item pattern[],
  78                                        const struct rte_flow_action actions[],
  79                                        struct rte_flow_error *error,
  80                                        union i40e_filter_t *filter);
  81 static int i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
  82                                         const struct rte_flow_attr *attr,
  83                                         const struct rte_flow_item pattern[],
  84                                         const struct rte_flow_action actions[],
  85                                         struct rte_flow_error *error,
  86                                         union i40e_filter_t *filter);
  87 static int i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
  88                                         const struct rte_flow_attr *attr,
  89                                         const struct rte_flow_item pattern[],
  90                                         const struct rte_flow_action actions[],
  91                                         struct rte_flow_error *error,
  92                                         union i40e_filter_t *filter);
  93 static int i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
  94                                        const struct rte_flow_attr *attr,
  95                                        const struct rte_flow_item pattern[],
  96                                        const struct rte_flow_action actions[],
  97                                        struct rte_flow_error *error,
  98                                        union i40e_filter_t *filter);
  99 static int i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
 100                                       const struct rte_flow_attr *attr,
 101                                       const struct rte_flow_item pattern[],
 102                                       const struct rte_flow_action actions[],
 103                                       struct rte_flow_error *error,
 104                                       union i40e_filter_t *filter);
 105 static int i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
 106                                       struct i40e_ethertype_filter *filter);
 107 static int i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
 108                                            struct i40e_tunnel_filter *filter);
 109 static int i40e_flow_flush_fdir_filter(struct i40e_pf *pf);
 110 static int i40e_flow_flush_ethertype_filter(struct i40e_pf *pf);
 111 static int i40e_flow_flush_tunnel_filter(struct i40e_pf *pf);
 112 static int
 113 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
 114                               const struct rte_flow_attr *attr,
 115                               const struct rte_flow_item pattern[],
 116                               const struct rte_flow_action actions[],
 117                               struct rte_flow_error *error,
 118                               union i40e_filter_t *filter);
 119 static int
 120 i40e_flow_parse_qinq_pattern(struct rte_eth_dev *dev,
 121                               const struct rte_flow_item *pattern,
 122                               struct rte_flow_error *error,
 123                               struct i40e_tunnel_filter_conf *filter);
 124
 125 const struct rte_flow_ops i40e_flow_ops = {
 126         .validate = i40e_flow_validate,
 127         .create = i40e_flow_create,
 128         .destroy = i40e_flow_destroy,
 129         .flush = i40e_flow_flush,
 130 };
 131
 132 union i40e_filter_t cons_filter;
 133 enum rte_filter_type cons_filter_type = RTE_ETH_FILTER_NONE;
 134
 135 /* Pattern matched ethertype filter */
 136 static enum rte_flow_item_type pattern_ethertype[] = {
 137         RTE_FLOW_ITEM_TYPE_ETH,
 138         RTE_FLOW_ITEM_TYPE_END,
 139 };
 140
 141 /* Pattern matched flow director filter */
 142 static enum rte_flow_item_type pattern_fdir_ipv4[] = {
 143         RTE_FLOW_ITEM_TYPE_ETH,
 144         RTE_FLOW_ITEM_TYPE_IPV4,
 145         RTE_FLOW_ITEM_TYPE_END,
 146 };
 147
 148 static enum rte_flow_item_type pattern_fdir_ipv4_udp[] = {
 149         RTE_FLOW_ITEM_TYPE_ETH,
 150         RTE_FLOW_ITEM_TYPE_IPV4,
 151         RTE_FLOW_ITEM_TYPE_UDP,
 152         RTE_FLOW_ITEM_TYPE_END,
 153 };
 154
 155 static enum rte_flow_item_type pattern_fdir_ipv4_tcp[] = {
 156         RTE_FLOW_ITEM_TYPE_ETH,
 157         RTE_FLOW_ITEM_TYPE_IPV4,
 158         RTE_FLOW_ITEM_TYPE_TCP,
 159         RTE_FLOW_ITEM_TYPE_END,
 160 };
 161
 162 static enum rte_flow_item_type pattern_fdir_ipv4_sctp[] = {
 163         RTE_FLOW_ITEM_TYPE_ETH,
 164         RTE_FLOW_ITEM_TYPE_IPV4,
 165         RTE_FLOW_ITEM_TYPE_SCTP,
 166         RTE_FLOW_ITEM_TYPE_END,
 167 };
 168
 169 static enum rte_flow_item_type pattern_fdir_ipv4_gtpc[] = {
 170         RTE_FLOW_ITEM_TYPE_ETH,
 171         RTE_FLOW_ITEM_TYPE_IPV4,
 172         RTE_FLOW_ITEM_TYPE_UDP,
 173         RTE_FLOW_ITEM_TYPE_GTPC,
 174         RTE_FLOW_ITEM_TYPE_END,
 175 };
 176
 177 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu[] = {
 178         RTE_FLOW_ITEM_TYPE_ETH,
 179         RTE_FLOW_ITEM_TYPE_IPV4,
 180         RTE_FLOW_ITEM_TYPE_UDP,
 181         RTE_FLOW_ITEM_TYPE_GTPU,
 182         RTE_FLOW_ITEM_TYPE_END,
 183 };
 184
 185 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv4[] = {
 186         RTE_FLOW_ITEM_TYPE_ETH,
 187         RTE_FLOW_ITEM_TYPE_IPV4,
 188         RTE_FLOW_ITEM_TYPE_UDP,
 189         RTE_FLOW_ITEM_TYPE_GTPU,
 190         RTE_FLOW_ITEM_TYPE_IPV4,
 191         RTE_FLOW_ITEM_TYPE_END,
 192 };
 193
 194 static enum rte_flow_item_type pattern_fdir_ipv4_gtpu_ipv6[] = {
 195         RTE_FLOW_ITEM_TYPE_ETH,
 196         RTE_FLOW_ITEM_TYPE_IPV4,
 197         RTE_FLOW_ITEM_TYPE_UDP,
 198         RTE_FLOW_ITEM_TYPE_GTPU,
 199         RTE_FLOW_ITEM_TYPE_IPV6,
 200         RTE_FLOW_ITEM_TYPE_END,
 201 };
 202
 203 static enum rte_flow_item_type pattern_fdir_ipv6[] = {
 204         RTE_FLOW_ITEM_TYPE_ETH,
 205         RTE_FLOW_ITEM_TYPE_IPV6,
 206         RTE_FLOW_ITEM_TYPE_END,
 207 };
 208
 209 static enum rte_flow_item_type pattern_fdir_ipv6_udp[] = {
 210         RTE_FLOW_ITEM_TYPE_ETH,
 211         RTE_FLOW_ITEM_TYPE_IPV6,
 212         RTE_FLOW_ITEM_TYPE_UDP,
 213         RTE_FLOW_ITEM_TYPE_END,
 214 };
 215
 216 static enum rte_flow_item_type pattern_fdir_ipv6_tcp[] = {
 217         RTE_FLOW_ITEM_TYPE_ETH,
 218         RTE_FLOW_ITEM_TYPE_IPV6,
 219         RTE_FLOW_ITEM_TYPE_TCP,
 220         RTE_FLOW_ITEM_TYPE_END,
 221 };
 222
 223 static enum rte_flow_item_type pattern_fdir_ipv6_sctp[] = {
 224         RTE_FLOW_ITEM_TYPE_ETH,
 225         RTE_FLOW_ITEM_TYPE_IPV6,
 226         RTE_FLOW_ITEM_TYPE_SCTP,
 227         RTE_FLOW_ITEM_TYPE_END,
 228 };
 229
 230 static enum rte_flow_item_type pattern_fdir_ipv6_gtpc[] = {
 231         RTE_FLOW_ITEM_TYPE_ETH,
 232         RTE_FLOW_ITEM_TYPE_IPV6,
 233         RTE_FLOW_ITEM_TYPE_UDP,
 234         RTE_FLOW_ITEM_TYPE_GTPC,
 235         RTE_FLOW_ITEM_TYPE_END,
 236 };
 237
 238 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu[] = {
 239         RTE_FLOW_ITEM_TYPE_ETH,
 240         RTE_FLOW_ITEM_TYPE_IPV6,
 241         RTE_FLOW_ITEM_TYPE_UDP,
 242         RTE_FLOW_ITEM_TYPE_GTPU,
 243         RTE_FLOW_ITEM_TYPE_END,
 244 };
 245
 246 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv4[] = {
 247         RTE_FLOW_ITEM_TYPE_ETH,
 248         RTE_FLOW_ITEM_TYPE_IPV6,
 249         RTE_FLOW_ITEM_TYPE_UDP,
 250         RTE_FLOW_ITEM_TYPE_GTPU,
 251         RTE_FLOW_ITEM_TYPE_IPV4,
 252         RTE_FLOW_ITEM_TYPE_END,
 253 };
 254
 255 static enum rte_flow_item_type pattern_fdir_ipv6_gtpu_ipv6[] = {
 256         RTE_FLOW_ITEM_TYPE_ETH,
 257         RTE_FLOW_ITEM_TYPE_IPV6,
 258         RTE_FLOW_ITEM_TYPE_UDP,
 259         RTE_FLOW_ITEM_TYPE_GTPU,
 260         RTE_FLOW_ITEM_TYPE_IPV6,
 261         RTE_FLOW_ITEM_TYPE_END,
 262 };
 263
 264 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1[] = {
 265         RTE_FLOW_ITEM_TYPE_ETH,
 266         RTE_FLOW_ITEM_TYPE_RAW,
 267         RTE_FLOW_ITEM_TYPE_END,
 268 };
 269
 270 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2[] = {
 271         RTE_FLOW_ITEM_TYPE_ETH,
 272         RTE_FLOW_ITEM_TYPE_RAW,
 273         RTE_FLOW_ITEM_TYPE_RAW,
 274         RTE_FLOW_ITEM_TYPE_END,
 275 };
 276
 277 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3[] = {
 278         RTE_FLOW_ITEM_TYPE_ETH,
 279         RTE_FLOW_ITEM_TYPE_RAW,
 280         RTE_FLOW_ITEM_TYPE_RAW,
 281         RTE_FLOW_ITEM_TYPE_RAW,
 282         RTE_FLOW_ITEM_TYPE_END,
 283 };
 284
 285 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1[] = {
 286         RTE_FLOW_ITEM_TYPE_ETH,
 287         RTE_FLOW_ITEM_TYPE_IPV4,
 288         RTE_FLOW_ITEM_TYPE_RAW,
 289         RTE_FLOW_ITEM_TYPE_END,
 290 };
 291
 292 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2[] = {
 293         RTE_FLOW_ITEM_TYPE_ETH,
 294         RTE_FLOW_ITEM_TYPE_IPV4,
 295         RTE_FLOW_ITEM_TYPE_RAW,
 296         RTE_FLOW_ITEM_TYPE_RAW,
 297         RTE_FLOW_ITEM_TYPE_END,
 298 };
 299
 300 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3[] = {
 301         RTE_FLOW_ITEM_TYPE_ETH,
 302         RTE_FLOW_ITEM_TYPE_IPV4,
 303         RTE_FLOW_ITEM_TYPE_RAW,
 304         RTE_FLOW_ITEM_TYPE_RAW,
 305         RTE_FLOW_ITEM_TYPE_RAW,
 306         RTE_FLOW_ITEM_TYPE_END,
 307 };
 308
 309 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1[] = {
 310         RTE_FLOW_ITEM_TYPE_ETH,
 311         RTE_FLOW_ITEM_TYPE_IPV4,
 312         RTE_FLOW_ITEM_TYPE_UDP,
 313         RTE_FLOW_ITEM_TYPE_RAW,
 314         RTE_FLOW_ITEM_TYPE_END,
 315 };
 316
 317 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2[] = {
 318         RTE_FLOW_ITEM_TYPE_ETH,
 319         RTE_FLOW_ITEM_TYPE_IPV4,
 320         RTE_FLOW_ITEM_TYPE_UDP,
 321         RTE_FLOW_ITEM_TYPE_RAW,
 322         RTE_FLOW_ITEM_TYPE_RAW,
 323         RTE_FLOW_ITEM_TYPE_END,
 324 };
 325
 326 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3[] = {
 327         RTE_FLOW_ITEM_TYPE_ETH,
 328         RTE_FLOW_ITEM_TYPE_IPV4,
 329         RTE_FLOW_ITEM_TYPE_UDP,
 330         RTE_FLOW_ITEM_TYPE_RAW,
 331         RTE_FLOW_ITEM_TYPE_RAW,
 332         RTE_FLOW_ITEM_TYPE_RAW,
 333         RTE_FLOW_ITEM_TYPE_END,
 334 };
 335
 336 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1[] = {
 337         RTE_FLOW_ITEM_TYPE_ETH,
 338         RTE_FLOW_ITEM_TYPE_IPV4,
 339         RTE_FLOW_ITEM_TYPE_TCP,
 340         RTE_FLOW_ITEM_TYPE_RAW,
 341         RTE_FLOW_ITEM_TYPE_END,
 342 };
 343
 344 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2[] = {
 345         RTE_FLOW_ITEM_TYPE_ETH,
 346         RTE_FLOW_ITEM_TYPE_IPV4,
 347         RTE_FLOW_ITEM_TYPE_TCP,
 348         RTE_FLOW_ITEM_TYPE_RAW,
 349         RTE_FLOW_ITEM_TYPE_RAW,
 350         RTE_FLOW_ITEM_TYPE_END,
 351 };
 352
 353 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3[] = {
 354         RTE_FLOW_ITEM_TYPE_ETH,
 355         RTE_FLOW_ITEM_TYPE_IPV4,
 356         RTE_FLOW_ITEM_TYPE_TCP,
 357         RTE_FLOW_ITEM_TYPE_RAW,
 358         RTE_FLOW_ITEM_TYPE_RAW,
 359         RTE_FLOW_ITEM_TYPE_RAW,
 360         RTE_FLOW_ITEM_TYPE_END,
 361 };
 362
 363 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1[] = {
 364         RTE_FLOW_ITEM_TYPE_ETH,
 365         RTE_FLOW_ITEM_TYPE_IPV4,
 366         RTE_FLOW_ITEM_TYPE_SCTP,
 367         RTE_FLOW_ITEM_TYPE_RAW,
 368         RTE_FLOW_ITEM_TYPE_END,
 369 };
 370
 371 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2[] = {
 372         RTE_FLOW_ITEM_TYPE_ETH,
 373         RTE_FLOW_ITEM_TYPE_IPV4,
 374         RTE_FLOW_ITEM_TYPE_SCTP,
 375         RTE_FLOW_ITEM_TYPE_RAW,
 376         RTE_FLOW_ITEM_TYPE_RAW,
 377         RTE_FLOW_ITEM_TYPE_END,
 378 };
 379
 380 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3[] = {
 381         RTE_FLOW_ITEM_TYPE_ETH,
 382         RTE_FLOW_ITEM_TYPE_IPV4,
 383         RTE_FLOW_ITEM_TYPE_SCTP,
 384         RTE_FLOW_ITEM_TYPE_RAW,
 385         RTE_FLOW_ITEM_TYPE_RAW,
 386         RTE_FLOW_ITEM_TYPE_RAW,
 387         RTE_FLOW_ITEM_TYPE_END,
 388 };
 389
 390 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1[] = {
 391         RTE_FLOW_ITEM_TYPE_ETH,
 392         RTE_FLOW_ITEM_TYPE_IPV6,
 393         RTE_FLOW_ITEM_TYPE_RAW,
 394         RTE_FLOW_ITEM_TYPE_END,
 395 };
 396
 397 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2[] = {
 398         RTE_FLOW_ITEM_TYPE_ETH,
 399         RTE_FLOW_ITEM_TYPE_IPV6,
 400         RTE_FLOW_ITEM_TYPE_RAW,
 401         RTE_FLOW_ITEM_TYPE_RAW,
 402         RTE_FLOW_ITEM_TYPE_END,
 403 };
 404
 405 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3[] = {
 406         RTE_FLOW_ITEM_TYPE_ETH,
 407         RTE_FLOW_ITEM_TYPE_IPV6,
 408         RTE_FLOW_ITEM_TYPE_RAW,
 409         RTE_FLOW_ITEM_TYPE_RAW,
 410         RTE_FLOW_ITEM_TYPE_RAW,
 411         RTE_FLOW_ITEM_TYPE_END,
 412 };
 413
 414 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1[] = {
 415         RTE_FLOW_ITEM_TYPE_ETH,
 416         RTE_FLOW_ITEM_TYPE_IPV6,
 417         RTE_FLOW_ITEM_TYPE_UDP,
 418         RTE_FLOW_ITEM_TYPE_RAW,
 419         RTE_FLOW_ITEM_TYPE_END,
 420 };
 421
 422 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2[] = {
 423         RTE_FLOW_ITEM_TYPE_ETH,
 424         RTE_FLOW_ITEM_TYPE_IPV6,
 425         RTE_FLOW_ITEM_TYPE_UDP,
 426         RTE_FLOW_ITEM_TYPE_RAW,
 427         RTE_FLOW_ITEM_TYPE_RAW,
 428         RTE_FLOW_ITEM_TYPE_END,
 429 };
 430
 431 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3[] = {
 432         RTE_FLOW_ITEM_TYPE_ETH,
 433         RTE_FLOW_ITEM_TYPE_IPV6,
 434         RTE_FLOW_ITEM_TYPE_UDP,
 435         RTE_FLOW_ITEM_TYPE_RAW,
 436         RTE_FLOW_ITEM_TYPE_RAW,
 437         RTE_FLOW_ITEM_TYPE_RAW,
 438         RTE_FLOW_ITEM_TYPE_END,
 439 };
 440
 441 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1[] = {
 442         RTE_FLOW_ITEM_TYPE_ETH,
 443         RTE_FLOW_ITEM_TYPE_IPV6,
 444         RTE_FLOW_ITEM_TYPE_TCP,
 445         RTE_FLOW_ITEM_TYPE_RAW,
 446         RTE_FLOW_ITEM_TYPE_END,
 447 };
 448
 449 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2[] = {
 450         RTE_FLOW_ITEM_TYPE_ETH,
 451         RTE_FLOW_ITEM_TYPE_IPV6,
 452         RTE_FLOW_ITEM_TYPE_TCP,
 453         RTE_FLOW_ITEM_TYPE_RAW,
 454         RTE_FLOW_ITEM_TYPE_RAW,
 455         RTE_FLOW_ITEM_TYPE_END,
 456 };
 457
 458 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3[] = {
 459         RTE_FLOW_ITEM_TYPE_ETH,
 460         RTE_FLOW_ITEM_TYPE_IPV6,
 461         RTE_FLOW_ITEM_TYPE_TCP,
 462         RTE_FLOW_ITEM_TYPE_RAW,
 463         RTE_FLOW_ITEM_TYPE_RAW,
 464         RTE_FLOW_ITEM_TYPE_RAW,
 465         RTE_FLOW_ITEM_TYPE_END,
 466 };
 467
 468 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1[] = {
 469         RTE_FLOW_ITEM_TYPE_ETH,
 470         RTE_FLOW_ITEM_TYPE_IPV6,
 471         RTE_FLOW_ITEM_TYPE_SCTP,
 472         RTE_FLOW_ITEM_TYPE_RAW,
 473         RTE_FLOW_ITEM_TYPE_END,
 474 };
 475
 476 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2[] = {
 477         RTE_FLOW_ITEM_TYPE_ETH,
 478         RTE_FLOW_ITEM_TYPE_IPV6,
 479         RTE_FLOW_ITEM_TYPE_SCTP,
 480         RTE_FLOW_ITEM_TYPE_RAW,
 481         RTE_FLOW_ITEM_TYPE_RAW,
 482         RTE_FLOW_ITEM_TYPE_END,
 483 };
 484
 485 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3[] = {
 486         RTE_FLOW_ITEM_TYPE_ETH,
 487         RTE_FLOW_ITEM_TYPE_IPV6,
 488         RTE_FLOW_ITEM_TYPE_SCTP,
 489         RTE_FLOW_ITEM_TYPE_RAW,
 490         RTE_FLOW_ITEM_TYPE_RAW,
 491         RTE_FLOW_ITEM_TYPE_RAW,
 492         RTE_FLOW_ITEM_TYPE_END,
 493 };
 494
 495 static enum rte_flow_item_type pattern_fdir_ethertype_vlan[] = {
 496         RTE_FLOW_ITEM_TYPE_ETH,
 497         RTE_FLOW_ITEM_TYPE_VLAN,
 498         RTE_FLOW_ITEM_TYPE_END,
 499 };
 500
 501 static enum rte_flow_item_type pattern_fdir_vlan_ipv4[] = {
 502         RTE_FLOW_ITEM_TYPE_ETH,
 503         RTE_FLOW_ITEM_TYPE_VLAN,
 504         RTE_FLOW_ITEM_TYPE_IPV4,
 505         RTE_FLOW_ITEM_TYPE_END,
 506 };
 507
 508 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp[] = {
 509         RTE_FLOW_ITEM_TYPE_ETH,
 510         RTE_FLOW_ITEM_TYPE_VLAN,
 511         RTE_FLOW_ITEM_TYPE_IPV4,
 512         RTE_FLOW_ITEM_TYPE_UDP,
 513         RTE_FLOW_ITEM_TYPE_END,
 514 };
 515
 516 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp[] = {
 517         RTE_FLOW_ITEM_TYPE_ETH,
 518         RTE_FLOW_ITEM_TYPE_VLAN,
 519         RTE_FLOW_ITEM_TYPE_IPV4,
 520         RTE_FLOW_ITEM_TYPE_TCP,
 521         RTE_FLOW_ITEM_TYPE_END,
 522 };
 523
 524 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp[] = {
 525         RTE_FLOW_ITEM_TYPE_ETH,
 526         RTE_FLOW_ITEM_TYPE_VLAN,
 527         RTE_FLOW_ITEM_TYPE_IPV4,
 528         RTE_FLOW_ITEM_TYPE_SCTP,
 529         RTE_FLOW_ITEM_TYPE_END,
 530 };
 531
 532 static enum rte_flow_item_type pattern_fdir_vlan_ipv6[] = {
 533         RTE_FLOW_ITEM_TYPE_ETH,
 534         RTE_FLOW_ITEM_TYPE_VLAN,
 535         RTE_FLOW_ITEM_TYPE_IPV6,
 536         RTE_FLOW_ITEM_TYPE_END,
 537 };
 538
 539 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp[] = {
 540         RTE_FLOW_ITEM_TYPE_ETH,
 541         RTE_FLOW_ITEM_TYPE_VLAN,
 542         RTE_FLOW_ITEM_TYPE_IPV6,
 543         RTE_FLOW_ITEM_TYPE_UDP,
 544         RTE_FLOW_ITEM_TYPE_END,
 545 };
 546
 547 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp[] = {
 548         RTE_FLOW_ITEM_TYPE_ETH,
 549         RTE_FLOW_ITEM_TYPE_VLAN,
 550         RTE_FLOW_ITEM_TYPE_IPV6,
 551         RTE_FLOW_ITEM_TYPE_TCP,
 552         RTE_FLOW_ITEM_TYPE_END,
 553 };
 554
 555 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp[] = {
 556         RTE_FLOW_ITEM_TYPE_ETH,
 557         RTE_FLOW_ITEM_TYPE_VLAN,
 558         RTE_FLOW_ITEM_TYPE_IPV6,
 559         RTE_FLOW_ITEM_TYPE_SCTP,
 560         RTE_FLOW_ITEM_TYPE_END,
 561 };
 562
 563 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1[] = {
 564         RTE_FLOW_ITEM_TYPE_ETH,
 565         RTE_FLOW_ITEM_TYPE_VLAN,
 566         RTE_FLOW_ITEM_TYPE_RAW,
 567         RTE_FLOW_ITEM_TYPE_END,
 568 };
 569
 570 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2[] = {
 571         RTE_FLOW_ITEM_TYPE_ETH,
 572         RTE_FLOW_ITEM_TYPE_VLAN,
 573         RTE_FLOW_ITEM_TYPE_RAW,
 574         RTE_FLOW_ITEM_TYPE_RAW,
 575         RTE_FLOW_ITEM_TYPE_END,
 576 };
 577
 578 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3[] = {
 579         RTE_FLOW_ITEM_TYPE_ETH,
 580         RTE_FLOW_ITEM_TYPE_VLAN,
 581         RTE_FLOW_ITEM_TYPE_RAW,
 582         RTE_FLOW_ITEM_TYPE_RAW,
 583         RTE_FLOW_ITEM_TYPE_RAW,
 584         RTE_FLOW_ITEM_TYPE_END,
 585 };
 586
 587 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1[] = {
 588         RTE_FLOW_ITEM_TYPE_ETH,
 589         RTE_FLOW_ITEM_TYPE_VLAN,
 590         RTE_FLOW_ITEM_TYPE_IPV4,
 591         RTE_FLOW_ITEM_TYPE_RAW,
 592         RTE_FLOW_ITEM_TYPE_END,
 593 };
 594
 595 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2[] = {
 596         RTE_FLOW_ITEM_TYPE_ETH,
 597         RTE_FLOW_ITEM_TYPE_VLAN,
 598         RTE_FLOW_ITEM_TYPE_IPV4,
 599         RTE_FLOW_ITEM_TYPE_RAW,
 600         RTE_FLOW_ITEM_TYPE_RAW,
 601         RTE_FLOW_ITEM_TYPE_END,
 602 };
 603
 604 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3[] = {
 605         RTE_FLOW_ITEM_TYPE_ETH,
 606         RTE_FLOW_ITEM_TYPE_VLAN,
 607         RTE_FLOW_ITEM_TYPE_IPV4,
 608         RTE_FLOW_ITEM_TYPE_RAW,
 609         RTE_FLOW_ITEM_TYPE_RAW,
 610         RTE_FLOW_ITEM_TYPE_RAW,
 611         RTE_FLOW_ITEM_TYPE_END,
 612 };
 613
 614 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1[] = {
 615         RTE_FLOW_ITEM_TYPE_ETH,
 616         RTE_FLOW_ITEM_TYPE_VLAN,
 617         RTE_FLOW_ITEM_TYPE_IPV4,
 618         RTE_FLOW_ITEM_TYPE_UDP,
 619         RTE_FLOW_ITEM_TYPE_RAW,
 620         RTE_FLOW_ITEM_TYPE_END,
 621 };
 622
 623 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2[] = {
 624         RTE_FLOW_ITEM_TYPE_ETH,
 625         RTE_FLOW_ITEM_TYPE_VLAN,
 626         RTE_FLOW_ITEM_TYPE_IPV4,
 627         RTE_FLOW_ITEM_TYPE_UDP,
 628         RTE_FLOW_ITEM_TYPE_RAW,
 629         RTE_FLOW_ITEM_TYPE_RAW,
 630         RTE_FLOW_ITEM_TYPE_END,
 631 };
 632
 633 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3[] = {
 634         RTE_FLOW_ITEM_TYPE_ETH,
 635         RTE_FLOW_ITEM_TYPE_VLAN,
 636         RTE_FLOW_ITEM_TYPE_IPV4,
 637         RTE_FLOW_ITEM_TYPE_UDP,
 638         RTE_FLOW_ITEM_TYPE_RAW,
 639         RTE_FLOW_ITEM_TYPE_RAW,
 640         RTE_FLOW_ITEM_TYPE_RAW,
 641         RTE_FLOW_ITEM_TYPE_END,
 642 };
 643
 644 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1[] = {
 645         RTE_FLOW_ITEM_TYPE_ETH,
 646         RTE_FLOW_ITEM_TYPE_VLAN,
 647         RTE_FLOW_ITEM_TYPE_IPV4,
 648         RTE_FLOW_ITEM_TYPE_TCP,
 649         RTE_FLOW_ITEM_TYPE_RAW,
 650         RTE_FLOW_ITEM_TYPE_END,
 651 };
 652
 653 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2[] = {
 654         RTE_FLOW_ITEM_TYPE_ETH,
 655         RTE_FLOW_ITEM_TYPE_VLAN,
 656         RTE_FLOW_ITEM_TYPE_IPV4,
 657         RTE_FLOW_ITEM_TYPE_TCP,
 658         RTE_FLOW_ITEM_TYPE_RAW,
 659         RTE_FLOW_ITEM_TYPE_RAW,
 660         RTE_FLOW_ITEM_TYPE_END,
 661 };
 662
 663 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3[] = {
 664         RTE_FLOW_ITEM_TYPE_ETH,
 665         RTE_FLOW_ITEM_TYPE_VLAN,
 666         RTE_FLOW_ITEM_TYPE_IPV4,
 667         RTE_FLOW_ITEM_TYPE_TCP,
 668         RTE_FLOW_ITEM_TYPE_RAW,
 669         RTE_FLOW_ITEM_TYPE_RAW,
 670         RTE_FLOW_ITEM_TYPE_RAW,
 671         RTE_FLOW_ITEM_TYPE_END,
 672 };
 673
 674 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1[] = {
 675         RTE_FLOW_ITEM_TYPE_ETH,
 676         RTE_FLOW_ITEM_TYPE_VLAN,
 677         RTE_FLOW_ITEM_TYPE_IPV4,
 678         RTE_FLOW_ITEM_TYPE_SCTP,
 679         RTE_FLOW_ITEM_TYPE_RAW,
 680         RTE_FLOW_ITEM_TYPE_END,
 681 };
 682
 683 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2[] = {
 684         RTE_FLOW_ITEM_TYPE_ETH,
 685         RTE_FLOW_ITEM_TYPE_VLAN,
 686         RTE_FLOW_ITEM_TYPE_IPV4,
 687         RTE_FLOW_ITEM_TYPE_SCTP,
 688         RTE_FLOW_ITEM_TYPE_RAW,
 689         RTE_FLOW_ITEM_TYPE_RAW,
 690         RTE_FLOW_ITEM_TYPE_END,
 691 };
 692
 693 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3[] = {
 694         RTE_FLOW_ITEM_TYPE_ETH,
 695         RTE_FLOW_ITEM_TYPE_VLAN,
 696         RTE_FLOW_ITEM_TYPE_IPV4,
 697         RTE_FLOW_ITEM_TYPE_SCTP,
 698         RTE_FLOW_ITEM_TYPE_RAW,
 699         RTE_FLOW_ITEM_TYPE_RAW,
 700         RTE_FLOW_ITEM_TYPE_RAW,
 701         RTE_FLOW_ITEM_TYPE_END,
 702 };
 703
 704 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1[] = {
 705         RTE_FLOW_ITEM_TYPE_ETH,
 706         RTE_FLOW_ITEM_TYPE_VLAN,
 707         RTE_FLOW_ITEM_TYPE_IPV6,
 708         RTE_FLOW_ITEM_TYPE_RAW,
 709         RTE_FLOW_ITEM_TYPE_END,
 710 };
 711
 712 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2[] = {
 713         RTE_FLOW_ITEM_TYPE_ETH,
 714         RTE_FLOW_ITEM_TYPE_VLAN,
 715         RTE_FLOW_ITEM_TYPE_IPV6,
 716         RTE_FLOW_ITEM_TYPE_RAW,
 717         RTE_FLOW_ITEM_TYPE_RAW,
 718         RTE_FLOW_ITEM_TYPE_END,
 719 };
 720
 721 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3[] = {
 722         RTE_FLOW_ITEM_TYPE_ETH,
 723         RTE_FLOW_ITEM_TYPE_VLAN,
 724         RTE_FLOW_ITEM_TYPE_IPV6,
 725         RTE_FLOW_ITEM_TYPE_RAW,
 726         RTE_FLOW_ITEM_TYPE_RAW,
 727         RTE_FLOW_ITEM_TYPE_RAW,
 728         RTE_FLOW_ITEM_TYPE_END,
 729 };
 730
 731 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1[] = {
 732         RTE_FLOW_ITEM_TYPE_ETH,
 733         RTE_FLOW_ITEM_TYPE_VLAN,
 734         RTE_FLOW_ITEM_TYPE_IPV6,
 735         RTE_FLOW_ITEM_TYPE_UDP,
 736         RTE_FLOW_ITEM_TYPE_RAW,
 737         RTE_FLOW_ITEM_TYPE_END,
 738 };
 739
 740 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2[] = {
 741         RTE_FLOW_ITEM_TYPE_ETH,
 742         RTE_FLOW_ITEM_TYPE_VLAN,
 743         RTE_FLOW_ITEM_TYPE_IPV6,
 744         RTE_FLOW_ITEM_TYPE_UDP,
 745         RTE_FLOW_ITEM_TYPE_RAW,
 746         RTE_FLOW_ITEM_TYPE_RAW,
 747         RTE_FLOW_ITEM_TYPE_END,
 748 };
 749
 750 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3[] = {
 751         RTE_FLOW_ITEM_TYPE_ETH,
 752         RTE_FLOW_ITEM_TYPE_VLAN,
 753         RTE_FLOW_ITEM_TYPE_IPV6,
 754         RTE_FLOW_ITEM_TYPE_UDP,
 755         RTE_FLOW_ITEM_TYPE_RAW,
 756         RTE_FLOW_ITEM_TYPE_RAW,
 757         RTE_FLOW_ITEM_TYPE_RAW,
 758         RTE_FLOW_ITEM_TYPE_END,
 759 };
 760
 761 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1[] = {
 762         RTE_FLOW_ITEM_TYPE_ETH,
 763         RTE_FLOW_ITEM_TYPE_VLAN,
 764         RTE_FLOW_ITEM_TYPE_IPV6,
 765         RTE_FLOW_ITEM_TYPE_TCP,
 766         RTE_FLOW_ITEM_TYPE_RAW,
 767         RTE_FLOW_ITEM_TYPE_END,
 768 };
 769
 770 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2[] = {
 771         RTE_FLOW_ITEM_TYPE_ETH,
 772         RTE_FLOW_ITEM_TYPE_VLAN,
 773         RTE_FLOW_ITEM_TYPE_IPV6,
 774         RTE_FLOW_ITEM_TYPE_TCP,
 775         RTE_FLOW_ITEM_TYPE_RAW,
 776         RTE_FLOW_ITEM_TYPE_RAW,
 777         RTE_FLOW_ITEM_TYPE_END,
 778 };
 779
 780 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3[] = {
 781         RTE_FLOW_ITEM_TYPE_ETH,
 782         RTE_FLOW_ITEM_TYPE_VLAN,
 783         RTE_FLOW_ITEM_TYPE_IPV6,
 784         RTE_FLOW_ITEM_TYPE_TCP,
 785         RTE_FLOW_ITEM_TYPE_RAW,
 786         RTE_FLOW_ITEM_TYPE_RAW,
 787         RTE_FLOW_ITEM_TYPE_RAW,
 788         RTE_FLOW_ITEM_TYPE_END,
 789 };
 790
 791 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1[] = {
 792         RTE_FLOW_ITEM_TYPE_ETH,
 793         RTE_FLOW_ITEM_TYPE_VLAN,
 794         RTE_FLOW_ITEM_TYPE_IPV6,
 795         RTE_FLOW_ITEM_TYPE_SCTP,
 796         RTE_FLOW_ITEM_TYPE_RAW,
 797         RTE_FLOW_ITEM_TYPE_END,
 798 };
 799
 800 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2[] = {
 801         RTE_FLOW_ITEM_TYPE_ETH,
 802         RTE_FLOW_ITEM_TYPE_VLAN,
 803         RTE_FLOW_ITEM_TYPE_IPV6,
 804         RTE_FLOW_ITEM_TYPE_SCTP,
 805         RTE_FLOW_ITEM_TYPE_RAW,
 806         RTE_FLOW_ITEM_TYPE_RAW,
 807         RTE_FLOW_ITEM_TYPE_END,
 808 };
 809
 810 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3[] = {
 811         RTE_FLOW_ITEM_TYPE_ETH,
 812         RTE_FLOW_ITEM_TYPE_VLAN,
 813         RTE_FLOW_ITEM_TYPE_IPV6,
 814         RTE_FLOW_ITEM_TYPE_SCTP,
 815         RTE_FLOW_ITEM_TYPE_RAW,
 816         RTE_FLOW_ITEM_TYPE_RAW,
 817         RTE_FLOW_ITEM_TYPE_RAW,
 818         RTE_FLOW_ITEM_TYPE_END,
 819 };
 820
 821 static enum rte_flow_item_type pattern_fdir_ipv4_vf[] = {
 822         RTE_FLOW_ITEM_TYPE_ETH,
 823         RTE_FLOW_ITEM_TYPE_IPV4,
 824         RTE_FLOW_ITEM_TYPE_VF,
 825         RTE_FLOW_ITEM_TYPE_END,
 826 };
 827
 828 static enum rte_flow_item_type pattern_fdir_ipv4_udp_vf[] = {
 829         RTE_FLOW_ITEM_TYPE_ETH,
 830         RTE_FLOW_ITEM_TYPE_IPV4,
 831         RTE_FLOW_ITEM_TYPE_UDP,
 832         RTE_FLOW_ITEM_TYPE_VF,
 833         RTE_FLOW_ITEM_TYPE_END,
 834 };
 835
 836 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_vf[] = {
 837         RTE_FLOW_ITEM_TYPE_ETH,
 838         RTE_FLOW_ITEM_TYPE_IPV4,
 839         RTE_FLOW_ITEM_TYPE_TCP,
 840         RTE_FLOW_ITEM_TYPE_VF,
 841         RTE_FLOW_ITEM_TYPE_END,
 842 };
 843
 844 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_vf[] = {
 845         RTE_FLOW_ITEM_TYPE_ETH,
 846         RTE_FLOW_ITEM_TYPE_IPV4,
 847         RTE_FLOW_ITEM_TYPE_SCTP,
 848         RTE_FLOW_ITEM_TYPE_VF,
 849         RTE_FLOW_ITEM_TYPE_END,
 850 };
 851
 852 static enum rte_flow_item_type pattern_fdir_ipv6_vf[] = {
 853         RTE_FLOW_ITEM_TYPE_ETH,
 854         RTE_FLOW_ITEM_TYPE_IPV6,
 855         RTE_FLOW_ITEM_TYPE_VF,
 856         RTE_FLOW_ITEM_TYPE_END,
 857 };
 858
 859 static enum rte_flow_item_type pattern_fdir_ipv6_udp_vf[] = {
 860         RTE_FLOW_ITEM_TYPE_ETH,
 861         RTE_FLOW_ITEM_TYPE_IPV6,
 862         RTE_FLOW_ITEM_TYPE_UDP,
 863         RTE_FLOW_ITEM_TYPE_VF,
 864         RTE_FLOW_ITEM_TYPE_END,
 865 };
 866
 867 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_vf[] = {
 868         RTE_FLOW_ITEM_TYPE_ETH,
 869         RTE_FLOW_ITEM_TYPE_IPV6,
 870         RTE_FLOW_ITEM_TYPE_TCP,
 871         RTE_FLOW_ITEM_TYPE_VF,
 872         RTE_FLOW_ITEM_TYPE_END,
 873 };
 874
 875 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_vf[] = {
 876         RTE_FLOW_ITEM_TYPE_ETH,
 877         RTE_FLOW_ITEM_TYPE_IPV6,
 878         RTE_FLOW_ITEM_TYPE_SCTP,
 879         RTE_FLOW_ITEM_TYPE_VF,
 880         RTE_FLOW_ITEM_TYPE_END,
 881 };
 882
 883 static enum rte_flow_item_type pattern_fdir_ethertype_raw_1_vf[] = {
 884         RTE_FLOW_ITEM_TYPE_ETH,
 885         RTE_FLOW_ITEM_TYPE_RAW,
 886         RTE_FLOW_ITEM_TYPE_VF,
 887         RTE_FLOW_ITEM_TYPE_END,
 888 };
 889
 890 static enum rte_flow_item_type pattern_fdir_ethertype_raw_2_vf[] = {
 891         RTE_FLOW_ITEM_TYPE_ETH,
 892         RTE_FLOW_ITEM_TYPE_RAW,
 893         RTE_FLOW_ITEM_TYPE_RAW,
 894         RTE_FLOW_ITEM_TYPE_VF,
 895         RTE_FLOW_ITEM_TYPE_END,
 896 };
 897
 898 static enum rte_flow_item_type pattern_fdir_ethertype_raw_3_vf[] = {
 899         RTE_FLOW_ITEM_TYPE_ETH,
 900         RTE_FLOW_ITEM_TYPE_RAW,
 901         RTE_FLOW_ITEM_TYPE_RAW,
 902         RTE_FLOW_ITEM_TYPE_RAW,
 903         RTE_FLOW_ITEM_TYPE_VF,
 904         RTE_FLOW_ITEM_TYPE_END,
 905 };
 906
 907 static enum rte_flow_item_type pattern_fdir_ipv4_raw_1_vf[] = {
 908         RTE_FLOW_ITEM_TYPE_ETH,
 909         RTE_FLOW_ITEM_TYPE_IPV4,
 910         RTE_FLOW_ITEM_TYPE_RAW,
 911         RTE_FLOW_ITEM_TYPE_VF,
 912         RTE_FLOW_ITEM_TYPE_END,
 913 };
 914
 915 static enum rte_flow_item_type pattern_fdir_ipv4_raw_2_vf[] = {
 916         RTE_FLOW_ITEM_TYPE_ETH,
 917         RTE_FLOW_ITEM_TYPE_IPV4,
 918         RTE_FLOW_ITEM_TYPE_RAW,
 919         RTE_FLOW_ITEM_TYPE_RAW,
 920         RTE_FLOW_ITEM_TYPE_VF,
 921         RTE_FLOW_ITEM_TYPE_END,
 922 };
 923
 924 static enum rte_flow_item_type pattern_fdir_ipv4_raw_3_vf[] = {
 925         RTE_FLOW_ITEM_TYPE_ETH,
 926         RTE_FLOW_ITEM_TYPE_IPV4,
 927         RTE_FLOW_ITEM_TYPE_RAW,
 928         RTE_FLOW_ITEM_TYPE_RAW,
 929         RTE_FLOW_ITEM_TYPE_RAW,
 930         RTE_FLOW_ITEM_TYPE_VF,
 931         RTE_FLOW_ITEM_TYPE_END,
 932 };
 933
 934 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_1_vf[] = {
 935         RTE_FLOW_ITEM_TYPE_ETH,
 936         RTE_FLOW_ITEM_TYPE_IPV4,
 937         RTE_FLOW_ITEM_TYPE_UDP,
 938         RTE_FLOW_ITEM_TYPE_RAW,
 939         RTE_FLOW_ITEM_TYPE_VF,
 940         RTE_FLOW_ITEM_TYPE_END,
 941 };
 942
 943 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_2_vf[] = {
 944         RTE_FLOW_ITEM_TYPE_ETH,
 945         RTE_FLOW_ITEM_TYPE_IPV4,
 946         RTE_FLOW_ITEM_TYPE_UDP,
 947         RTE_FLOW_ITEM_TYPE_RAW,
 948         RTE_FLOW_ITEM_TYPE_RAW,
 949         RTE_FLOW_ITEM_TYPE_VF,
 950         RTE_FLOW_ITEM_TYPE_END,
 951 };
 952
 953 static enum rte_flow_item_type pattern_fdir_ipv4_udp_raw_3_vf[] = {
 954         RTE_FLOW_ITEM_TYPE_ETH,
 955         RTE_FLOW_ITEM_TYPE_IPV4,
 956         RTE_FLOW_ITEM_TYPE_UDP,
 957         RTE_FLOW_ITEM_TYPE_RAW,
 958         RTE_FLOW_ITEM_TYPE_RAW,
 959         RTE_FLOW_ITEM_TYPE_RAW,
 960         RTE_FLOW_ITEM_TYPE_VF,
 961         RTE_FLOW_ITEM_TYPE_END,
 962 };
 963
 964 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_1_vf[] = {
 965         RTE_FLOW_ITEM_TYPE_ETH,
 966         RTE_FLOW_ITEM_TYPE_IPV4,
 967         RTE_FLOW_ITEM_TYPE_TCP,
 968         RTE_FLOW_ITEM_TYPE_RAW,
 969         RTE_FLOW_ITEM_TYPE_VF,
 970         RTE_FLOW_ITEM_TYPE_END,
 971 };
 972
 973 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_2_vf[] = {
 974         RTE_FLOW_ITEM_TYPE_ETH,
 975         RTE_FLOW_ITEM_TYPE_IPV4,
 976         RTE_FLOW_ITEM_TYPE_TCP,
 977         RTE_FLOW_ITEM_TYPE_RAW,
 978         RTE_FLOW_ITEM_TYPE_RAW,
 979         RTE_FLOW_ITEM_TYPE_VF,
 980         RTE_FLOW_ITEM_TYPE_END,
 981 };
 982
 983 static enum rte_flow_item_type pattern_fdir_ipv4_tcp_raw_3_vf[] = {
 984         RTE_FLOW_ITEM_TYPE_ETH,
 985         RTE_FLOW_ITEM_TYPE_IPV4,
 986         RTE_FLOW_ITEM_TYPE_TCP,
 987         RTE_FLOW_ITEM_TYPE_RAW,
 988         RTE_FLOW_ITEM_TYPE_RAW,
 989         RTE_FLOW_ITEM_TYPE_RAW,
 990         RTE_FLOW_ITEM_TYPE_VF,
 991         RTE_FLOW_ITEM_TYPE_END,
 992 };
 993
 994 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_1_vf[] = {
 995         RTE_FLOW_ITEM_TYPE_ETH,
 996         RTE_FLOW_ITEM_TYPE_IPV4,
 997         RTE_FLOW_ITEM_TYPE_SCTP,
 998         RTE_FLOW_ITEM_TYPE_RAW,
 999         RTE_FLOW_ITEM_TYPE_VF,
1000         RTE_FLOW_ITEM_TYPE_END,
1001 };
1002
1003 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_2_vf[] = {
1004         RTE_FLOW_ITEM_TYPE_ETH,
1005         RTE_FLOW_ITEM_TYPE_IPV4,
1006         RTE_FLOW_ITEM_TYPE_SCTP,
1007         RTE_FLOW_ITEM_TYPE_RAW,
1008         RTE_FLOW_ITEM_TYPE_RAW,
1009         RTE_FLOW_ITEM_TYPE_VF,
1010         RTE_FLOW_ITEM_TYPE_END,
1011 };
1012
1013 static enum rte_flow_item_type pattern_fdir_ipv4_sctp_raw_3_vf[] = {
1014         RTE_FLOW_ITEM_TYPE_ETH,
1015         RTE_FLOW_ITEM_TYPE_IPV4,
1016         RTE_FLOW_ITEM_TYPE_SCTP,
1017         RTE_FLOW_ITEM_TYPE_RAW,
1018         RTE_FLOW_ITEM_TYPE_RAW,
1019         RTE_FLOW_ITEM_TYPE_RAW,
1020         RTE_FLOW_ITEM_TYPE_VF,
1021         RTE_FLOW_ITEM_TYPE_END,
1022 };
1023
1024 static enum rte_flow_item_type pattern_fdir_ipv6_raw_1_vf[] = {
1025         RTE_FLOW_ITEM_TYPE_ETH,
1026         RTE_FLOW_ITEM_TYPE_IPV6,
1027         RTE_FLOW_ITEM_TYPE_RAW,
1028         RTE_FLOW_ITEM_TYPE_VF,
1029         RTE_FLOW_ITEM_TYPE_END,
1030 };
1031
1032 static enum rte_flow_item_type pattern_fdir_ipv6_raw_2_vf[] = {
1033         RTE_FLOW_ITEM_TYPE_ETH,
1034         RTE_FLOW_ITEM_TYPE_IPV6,
1035         RTE_FLOW_ITEM_TYPE_RAW,
1036         RTE_FLOW_ITEM_TYPE_RAW,
1037         RTE_FLOW_ITEM_TYPE_VF,
1038         RTE_FLOW_ITEM_TYPE_END,
1039 };
1040
1041 static enum rte_flow_item_type pattern_fdir_ipv6_raw_3_vf[] = {
1042         RTE_FLOW_ITEM_TYPE_ETH,
1043         RTE_FLOW_ITEM_TYPE_IPV6,
1044         RTE_FLOW_ITEM_TYPE_RAW,
1045         RTE_FLOW_ITEM_TYPE_RAW,
1046         RTE_FLOW_ITEM_TYPE_RAW,
1047         RTE_FLOW_ITEM_TYPE_VF,
1048         RTE_FLOW_ITEM_TYPE_END,
1049 };
1050
1051 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_1_vf[] = {
1052         RTE_FLOW_ITEM_TYPE_ETH,
1053         RTE_FLOW_ITEM_TYPE_IPV6,
1054         RTE_FLOW_ITEM_TYPE_UDP,
1055         RTE_FLOW_ITEM_TYPE_RAW,
1056         RTE_FLOW_ITEM_TYPE_VF,
1057         RTE_FLOW_ITEM_TYPE_END,
1058 };
1059
1060 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_2_vf[] = {
1061         RTE_FLOW_ITEM_TYPE_ETH,
1062         RTE_FLOW_ITEM_TYPE_IPV6,
1063         RTE_FLOW_ITEM_TYPE_UDP,
1064         RTE_FLOW_ITEM_TYPE_RAW,
1065         RTE_FLOW_ITEM_TYPE_RAW,
1066         RTE_FLOW_ITEM_TYPE_VF,
1067         RTE_FLOW_ITEM_TYPE_END,
1068 };
1069
1070 static enum rte_flow_item_type pattern_fdir_ipv6_udp_raw_3_vf[] = {
1071         RTE_FLOW_ITEM_TYPE_ETH,
1072         RTE_FLOW_ITEM_TYPE_IPV6,
1073         RTE_FLOW_ITEM_TYPE_UDP,
1074         RTE_FLOW_ITEM_TYPE_RAW,
1075         RTE_FLOW_ITEM_TYPE_RAW,
1076         RTE_FLOW_ITEM_TYPE_RAW,
1077         RTE_FLOW_ITEM_TYPE_VF,
1078         RTE_FLOW_ITEM_TYPE_END,
1079 };
1080
1081 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_1_vf[] = {
1082         RTE_FLOW_ITEM_TYPE_ETH,
1083         RTE_FLOW_ITEM_TYPE_IPV6,
1084         RTE_FLOW_ITEM_TYPE_TCP,
1085         RTE_FLOW_ITEM_TYPE_RAW,
1086         RTE_FLOW_ITEM_TYPE_VF,
1087         RTE_FLOW_ITEM_TYPE_END,
1088 };
1089
1090 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_2_vf[] = {
1091         RTE_FLOW_ITEM_TYPE_ETH,
1092         RTE_FLOW_ITEM_TYPE_IPV6,
1093         RTE_FLOW_ITEM_TYPE_TCP,
1094         RTE_FLOW_ITEM_TYPE_RAW,
1095         RTE_FLOW_ITEM_TYPE_RAW,
1096         RTE_FLOW_ITEM_TYPE_VF,
1097         RTE_FLOW_ITEM_TYPE_END,
1098 };
1099
1100 static enum rte_flow_item_type pattern_fdir_ipv6_tcp_raw_3_vf[] = {
1101         RTE_FLOW_ITEM_TYPE_ETH,
1102         RTE_FLOW_ITEM_TYPE_IPV6,
1103         RTE_FLOW_ITEM_TYPE_TCP,
1104         RTE_FLOW_ITEM_TYPE_RAW,
1105         RTE_FLOW_ITEM_TYPE_RAW,
1106         RTE_FLOW_ITEM_TYPE_RAW,
1107         RTE_FLOW_ITEM_TYPE_VF,
1108         RTE_FLOW_ITEM_TYPE_END,
1109 };
1110
1111 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_1_vf[] = {
1112         RTE_FLOW_ITEM_TYPE_ETH,
1113         RTE_FLOW_ITEM_TYPE_IPV6,
1114         RTE_FLOW_ITEM_TYPE_SCTP,
1115         RTE_FLOW_ITEM_TYPE_RAW,
1116         RTE_FLOW_ITEM_TYPE_VF,
1117         RTE_FLOW_ITEM_TYPE_END,
1118 };
1119
1120 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_2_vf[] = {
1121         RTE_FLOW_ITEM_TYPE_ETH,
1122         RTE_FLOW_ITEM_TYPE_IPV6,
1123         RTE_FLOW_ITEM_TYPE_SCTP,
1124         RTE_FLOW_ITEM_TYPE_RAW,
1125         RTE_FLOW_ITEM_TYPE_RAW,
1126         RTE_FLOW_ITEM_TYPE_VF,
1127         RTE_FLOW_ITEM_TYPE_END,
1128 };
1129
1130 static enum rte_flow_item_type pattern_fdir_ipv6_sctp_raw_3_vf[] = {
1131         RTE_FLOW_ITEM_TYPE_ETH,
1132         RTE_FLOW_ITEM_TYPE_IPV6,
1133         RTE_FLOW_ITEM_TYPE_SCTP,
1134         RTE_FLOW_ITEM_TYPE_RAW,
1135         RTE_FLOW_ITEM_TYPE_RAW,
1136         RTE_FLOW_ITEM_TYPE_RAW,
1137         RTE_FLOW_ITEM_TYPE_VF,
1138         RTE_FLOW_ITEM_TYPE_END,
1139 };
1140
1141 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_vf[] = {
1142         RTE_FLOW_ITEM_TYPE_ETH,
1143         RTE_FLOW_ITEM_TYPE_VLAN,
1144         RTE_FLOW_ITEM_TYPE_VF,
1145         RTE_FLOW_ITEM_TYPE_END,
1146 };
1147
1148 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_vf[] = {
1149         RTE_FLOW_ITEM_TYPE_ETH,
1150         RTE_FLOW_ITEM_TYPE_VLAN,
1151         RTE_FLOW_ITEM_TYPE_IPV4,
1152         RTE_FLOW_ITEM_TYPE_VF,
1153         RTE_FLOW_ITEM_TYPE_END,
1154 };
1155
1156 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_vf[] = {
1157         RTE_FLOW_ITEM_TYPE_ETH,
1158         RTE_FLOW_ITEM_TYPE_VLAN,
1159         RTE_FLOW_ITEM_TYPE_IPV4,
1160         RTE_FLOW_ITEM_TYPE_UDP,
1161         RTE_FLOW_ITEM_TYPE_VF,
1162         RTE_FLOW_ITEM_TYPE_END,
1163 };
1164
1165 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_vf[] = {
1166         RTE_FLOW_ITEM_TYPE_ETH,
1167         RTE_FLOW_ITEM_TYPE_VLAN,
1168         RTE_FLOW_ITEM_TYPE_IPV4,
1169         RTE_FLOW_ITEM_TYPE_TCP,
1170         RTE_FLOW_ITEM_TYPE_VF,
1171         RTE_FLOW_ITEM_TYPE_END,
1172 };
1173
1174 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_vf[] = {
1175         RTE_FLOW_ITEM_TYPE_ETH,
1176         RTE_FLOW_ITEM_TYPE_VLAN,
1177         RTE_FLOW_ITEM_TYPE_IPV4,
1178         RTE_FLOW_ITEM_TYPE_SCTP,
1179         RTE_FLOW_ITEM_TYPE_VF,
1180         RTE_FLOW_ITEM_TYPE_END,
1181 };
1182
1183 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_vf[] = {
1184         RTE_FLOW_ITEM_TYPE_ETH,
1185         RTE_FLOW_ITEM_TYPE_VLAN,
1186         RTE_FLOW_ITEM_TYPE_IPV6,
1187         RTE_FLOW_ITEM_TYPE_VF,
1188         RTE_FLOW_ITEM_TYPE_END,
1189 };
1190
1191 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_vf[] = {
1192         RTE_FLOW_ITEM_TYPE_ETH,
1193         RTE_FLOW_ITEM_TYPE_VLAN,
1194         RTE_FLOW_ITEM_TYPE_IPV6,
1195         RTE_FLOW_ITEM_TYPE_UDP,
1196         RTE_FLOW_ITEM_TYPE_VF,
1197         RTE_FLOW_ITEM_TYPE_END,
1198 };
1199
1200 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_vf[] = {
1201         RTE_FLOW_ITEM_TYPE_ETH,
1202         RTE_FLOW_ITEM_TYPE_VLAN,
1203         RTE_FLOW_ITEM_TYPE_IPV6,
1204         RTE_FLOW_ITEM_TYPE_TCP,
1205         RTE_FLOW_ITEM_TYPE_VF,
1206         RTE_FLOW_ITEM_TYPE_END,
1207 };
1208
1209 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_vf[] = {
1210         RTE_FLOW_ITEM_TYPE_ETH,
1211         RTE_FLOW_ITEM_TYPE_VLAN,
1212         RTE_FLOW_ITEM_TYPE_IPV6,
1213         RTE_FLOW_ITEM_TYPE_SCTP,
1214         RTE_FLOW_ITEM_TYPE_VF,
1215         RTE_FLOW_ITEM_TYPE_END,
1216 };
1217
1218 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_1_vf[] = {
1219         RTE_FLOW_ITEM_TYPE_ETH,
1220         RTE_FLOW_ITEM_TYPE_VLAN,
1221         RTE_FLOW_ITEM_TYPE_RAW,
1222         RTE_FLOW_ITEM_TYPE_VF,
1223         RTE_FLOW_ITEM_TYPE_END,
1224 };
1225
1226 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_2_vf[] = {
1227         RTE_FLOW_ITEM_TYPE_ETH,
1228         RTE_FLOW_ITEM_TYPE_VLAN,
1229         RTE_FLOW_ITEM_TYPE_RAW,
1230         RTE_FLOW_ITEM_TYPE_RAW,
1231         RTE_FLOW_ITEM_TYPE_VF,
1232         RTE_FLOW_ITEM_TYPE_END,
1233 };
1234
1235 static enum rte_flow_item_type pattern_fdir_ethertype_vlan_raw_3_vf[] = {
1236         RTE_FLOW_ITEM_TYPE_ETH,
1237         RTE_FLOW_ITEM_TYPE_VLAN,
1238         RTE_FLOW_ITEM_TYPE_RAW,
1239         RTE_FLOW_ITEM_TYPE_RAW,
1240         RTE_FLOW_ITEM_TYPE_RAW,
1241         RTE_FLOW_ITEM_TYPE_VF,
1242         RTE_FLOW_ITEM_TYPE_END,
1243 };
1244
1245 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_1_vf[] = {
1246         RTE_FLOW_ITEM_TYPE_ETH,
1247         RTE_FLOW_ITEM_TYPE_VLAN,
1248         RTE_FLOW_ITEM_TYPE_IPV4,
1249         RTE_FLOW_ITEM_TYPE_RAW,
1250         RTE_FLOW_ITEM_TYPE_VF,
1251         RTE_FLOW_ITEM_TYPE_END,
1252 };
1253
1254 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_2_vf[] = {
1255         RTE_FLOW_ITEM_TYPE_ETH,
1256         RTE_FLOW_ITEM_TYPE_VLAN,
1257         RTE_FLOW_ITEM_TYPE_IPV4,
1258         RTE_FLOW_ITEM_TYPE_RAW,
1259         RTE_FLOW_ITEM_TYPE_RAW,
1260         RTE_FLOW_ITEM_TYPE_VF,
1261         RTE_FLOW_ITEM_TYPE_END,
1262 };
1263
1264 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_raw_3_vf[] = {
1265         RTE_FLOW_ITEM_TYPE_ETH,
1266         RTE_FLOW_ITEM_TYPE_VLAN,
1267         RTE_FLOW_ITEM_TYPE_IPV4,
1268         RTE_FLOW_ITEM_TYPE_RAW,
1269         RTE_FLOW_ITEM_TYPE_RAW,
1270         RTE_FLOW_ITEM_TYPE_RAW,
1271         RTE_FLOW_ITEM_TYPE_VF,
1272         RTE_FLOW_ITEM_TYPE_END,
1273 };
1274
1275 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_1_vf[] = {
1276         RTE_FLOW_ITEM_TYPE_ETH,
1277         RTE_FLOW_ITEM_TYPE_VLAN,
1278         RTE_FLOW_ITEM_TYPE_IPV4,
1279         RTE_FLOW_ITEM_TYPE_UDP,
1280         RTE_FLOW_ITEM_TYPE_RAW,
1281         RTE_FLOW_ITEM_TYPE_VF,
1282         RTE_FLOW_ITEM_TYPE_END,
1283 };
1284
1285 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_2_vf[] = {
1286         RTE_FLOW_ITEM_TYPE_ETH,
1287         RTE_FLOW_ITEM_TYPE_VLAN,
1288         RTE_FLOW_ITEM_TYPE_IPV4,
1289         RTE_FLOW_ITEM_TYPE_UDP,
1290         RTE_FLOW_ITEM_TYPE_RAW,
1291         RTE_FLOW_ITEM_TYPE_RAW,
1292         RTE_FLOW_ITEM_TYPE_VF,
1293         RTE_FLOW_ITEM_TYPE_END,
1294 };
1295
1296 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_udp_raw_3_vf[] = {
1297         RTE_FLOW_ITEM_TYPE_ETH,
1298         RTE_FLOW_ITEM_TYPE_VLAN,
1299         RTE_FLOW_ITEM_TYPE_IPV4,
1300         RTE_FLOW_ITEM_TYPE_UDP,
1301         RTE_FLOW_ITEM_TYPE_RAW,
1302         RTE_FLOW_ITEM_TYPE_RAW,
1303         RTE_FLOW_ITEM_TYPE_RAW,
1304         RTE_FLOW_ITEM_TYPE_VF,
1305         RTE_FLOW_ITEM_TYPE_END,
1306 };
1307
1308 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_1_vf[] = {
1309         RTE_FLOW_ITEM_TYPE_ETH,
1310         RTE_FLOW_ITEM_TYPE_VLAN,
1311         RTE_FLOW_ITEM_TYPE_IPV4,
1312         RTE_FLOW_ITEM_TYPE_TCP,
1313         RTE_FLOW_ITEM_TYPE_RAW,
1314         RTE_FLOW_ITEM_TYPE_VF,
1315         RTE_FLOW_ITEM_TYPE_END,
1316 };
1317
1318 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_2_vf[] = {
1319         RTE_FLOW_ITEM_TYPE_ETH,
1320         RTE_FLOW_ITEM_TYPE_VLAN,
1321         RTE_FLOW_ITEM_TYPE_IPV4,
1322         RTE_FLOW_ITEM_TYPE_TCP,
1323         RTE_FLOW_ITEM_TYPE_RAW,
1324         RTE_FLOW_ITEM_TYPE_RAW,
1325         RTE_FLOW_ITEM_TYPE_VF,
1326         RTE_FLOW_ITEM_TYPE_END,
1327 };
1328
1329 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_tcp_raw_3_vf[] = {
1330         RTE_FLOW_ITEM_TYPE_ETH,
1331         RTE_FLOW_ITEM_TYPE_VLAN,
1332         RTE_FLOW_ITEM_TYPE_IPV4,
1333         RTE_FLOW_ITEM_TYPE_TCP,
1334         RTE_FLOW_ITEM_TYPE_RAW,
1335         RTE_FLOW_ITEM_TYPE_RAW,
1336         RTE_FLOW_ITEM_TYPE_RAW,
1337         RTE_FLOW_ITEM_TYPE_VF,
1338         RTE_FLOW_ITEM_TYPE_END,
1339 };
1340
1341 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_1_vf[] = {
1342         RTE_FLOW_ITEM_TYPE_ETH,
1343         RTE_FLOW_ITEM_TYPE_VLAN,
1344         RTE_FLOW_ITEM_TYPE_IPV4,
1345         RTE_FLOW_ITEM_TYPE_SCTP,
1346         RTE_FLOW_ITEM_TYPE_RAW,
1347         RTE_FLOW_ITEM_TYPE_VF,
1348         RTE_FLOW_ITEM_TYPE_END,
1349 };
1350
1351 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_2_vf[] = {
1352         RTE_FLOW_ITEM_TYPE_ETH,
1353         RTE_FLOW_ITEM_TYPE_VLAN,
1354         RTE_FLOW_ITEM_TYPE_IPV4,
1355         RTE_FLOW_ITEM_TYPE_SCTP,
1356         RTE_FLOW_ITEM_TYPE_RAW,
1357         RTE_FLOW_ITEM_TYPE_RAW,
1358         RTE_FLOW_ITEM_TYPE_VF,
1359         RTE_FLOW_ITEM_TYPE_END,
1360 };
1361
1362 static enum rte_flow_item_type pattern_fdir_vlan_ipv4_sctp_raw_3_vf[] = {
1363         RTE_FLOW_ITEM_TYPE_ETH,
1364         RTE_FLOW_ITEM_TYPE_VLAN,
1365         RTE_FLOW_ITEM_TYPE_IPV4,
1366         RTE_FLOW_ITEM_TYPE_SCTP,
1367         RTE_FLOW_ITEM_TYPE_RAW,
1368         RTE_FLOW_ITEM_TYPE_RAW,
1369         RTE_FLOW_ITEM_TYPE_RAW,
1370         RTE_FLOW_ITEM_TYPE_VF,
1371         RTE_FLOW_ITEM_TYPE_END,
1372 };
1373
1374 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_1_vf[] = {
1375         RTE_FLOW_ITEM_TYPE_ETH,
1376         RTE_FLOW_ITEM_TYPE_VLAN,
1377         RTE_FLOW_ITEM_TYPE_IPV6,
1378         RTE_FLOW_ITEM_TYPE_RAW,
1379         RTE_FLOW_ITEM_TYPE_VF,
1380         RTE_FLOW_ITEM_TYPE_END,
1381 };
1382
1383 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_2_vf[] = {
1384         RTE_FLOW_ITEM_TYPE_ETH,
1385         RTE_FLOW_ITEM_TYPE_VLAN,
1386         RTE_FLOW_ITEM_TYPE_IPV6,
1387         RTE_FLOW_ITEM_TYPE_RAW,
1388         RTE_FLOW_ITEM_TYPE_RAW,
1389         RTE_FLOW_ITEM_TYPE_VF,
1390         RTE_FLOW_ITEM_TYPE_END,
1391 };
1392
1393 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_raw_3_vf[] = {
1394         RTE_FLOW_ITEM_TYPE_ETH,
1395         RTE_FLOW_ITEM_TYPE_VLAN,
1396         RTE_FLOW_ITEM_TYPE_IPV6,
1397         RTE_FLOW_ITEM_TYPE_RAW,
1398         RTE_FLOW_ITEM_TYPE_RAW,
1399         RTE_FLOW_ITEM_TYPE_RAW,
1400         RTE_FLOW_ITEM_TYPE_VF,
1401         RTE_FLOW_ITEM_TYPE_END,
1402 };
1403
1404 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_1_vf[] = {
1405         RTE_FLOW_ITEM_TYPE_ETH,
1406         RTE_FLOW_ITEM_TYPE_VLAN,
1407         RTE_FLOW_ITEM_TYPE_IPV6,
1408         RTE_FLOW_ITEM_TYPE_UDP,
1409         RTE_FLOW_ITEM_TYPE_RAW,
1410         RTE_FLOW_ITEM_TYPE_VF,
1411         RTE_FLOW_ITEM_TYPE_END,
1412 };
1413
1414 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_2_vf[] = {
1415         RTE_FLOW_ITEM_TYPE_ETH,
1416         RTE_FLOW_ITEM_TYPE_VLAN,
1417         RTE_FLOW_ITEM_TYPE_IPV6,
1418         RTE_FLOW_ITEM_TYPE_UDP,
1419         RTE_FLOW_ITEM_TYPE_RAW,
1420         RTE_FLOW_ITEM_TYPE_RAW,
1421         RTE_FLOW_ITEM_TYPE_VF,
1422         RTE_FLOW_ITEM_TYPE_END,
1423 };
1424
1425 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_udp_raw_3_vf[] = {
1426         RTE_FLOW_ITEM_TYPE_ETH,
1427         RTE_FLOW_ITEM_TYPE_VLAN,
1428         RTE_FLOW_ITEM_TYPE_IPV6,
1429         RTE_FLOW_ITEM_TYPE_UDP,
1430         RTE_FLOW_ITEM_TYPE_RAW,
1431         RTE_FLOW_ITEM_TYPE_RAW,
1432         RTE_FLOW_ITEM_TYPE_RAW,
1433         RTE_FLOW_ITEM_TYPE_VF,
1434         RTE_FLOW_ITEM_TYPE_END,
1435 };
1436
1437 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_1_vf[] = {
1438         RTE_FLOW_ITEM_TYPE_ETH,
1439         RTE_FLOW_ITEM_TYPE_VLAN,
1440         RTE_FLOW_ITEM_TYPE_IPV6,
1441         RTE_FLOW_ITEM_TYPE_TCP,
1442         RTE_FLOW_ITEM_TYPE_RAW,
1443         RTE_FLOW_ITEM_TYPE_VF,
1444         RTE_FLOW_ITEM_TYPE_END,
1445 };
1446
1447 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_2_vf[] = {
1448         RTE_FLOW_ITEM_TYPE_ETH,
1449         RTE_FLOW_ITEM_TYPE_VLAN,
1450         RTE_FLOW_ITEM_TYPE_IPV6,
1451         RTE_FLOW_ITEM_TYPE_TCP,
1452         RTE_FLOW_ITEM_TYPE_RAW,
1453         RTE_FLOW_ITEM_TYPE_RAW,
1454         RTE_FLOW_ITEM_TYPE_VF,
1455         RTE_FLOW_ITEM_TYPE_END,
1456 };
1457
1458 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_tcp_raw_3_vf[] = {
1459         RTE_FLOW_ITEM_TYPE_ETH,
1460         RTE_FLOW_ITEM_TYPE_VLAN,
1461         RTE_FLOW_ITEM_TYPE_IPV6,
1462         RTE_FLOW_ITEM_TYPE_TCP,
1463         RTE_FLOW_ITEM_TYPE_RAW,
1464         RTE_FLOW_ITEM_TYPE_RAW,
1465         RTE_FLOW_ITEM_TYPE_RAW,
1466         RTE_FLOW_ITEM_TYPE_VF,
1467         RTE_FLOW_ITEM_TYPE_END,
1468 };
1469
1470 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_1_vf[] = {
1471         RTE_FLOW_ITEM_TYPE_ETH,
1472         RTE_FLOW_ITEM_TYPE_VLAN,
1473         RTE_FLOW_ITEM_TYPE_IPV6,
1474         RTE_FLOW_ITEM_TYPE_SCTP,
1475         RTE_FLOW_ITEM_TYPE_RAW,
1476         RTE_FLOW_ITEM_TYPE_VF,
1477         RTE_FLOW_ITEM_TYPE_END,
1478 };
1479
1480 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_2_vf[] = {
1481         RTE_FLOW_ITEM_TYPE_ETH,
1482         RTE_FLOW_ITEM_TYPE_VLAN,
1483         RTE_FLOW_ITEM_TYPE_IPV6,
1484         RTE_FLOW_ITEM_TYPE_SCTP,
1485         RTE_FLOW_ITEM_TYPE_RAW,
1486         RTE_FLOW_ITEM_TYPE_RAW,
1487         RTE_FLOW_ITEM_TYPE_VF,
1488         RTE_FLOW_ITEM_TYPE_END,
1489 };
1490
1491 static enum rte_flow_item_type pattern_fdir_vlan_ipv6_sctp_raw_3_vf[] = {
1492         RTE_FLOW_ITEM_TYPE_ETH,
1493         RTE_FLOW_ITEM_TYPE_VLAN,
1494         RTE_FLOW_ITEM_TYPE_IPV6,
1495         RTE_FLOW_ITEM_TYPE_SCTP,
1496         RTE_FLOW_ITEM_TYPE_RAW,
1497         RTE_FLOW_ITEM_TYPE_RAW,
1498         RTE_FLOW_ITEM_TYPE_RAW,
1499         RTE_FLOW_ITEM_TYPE_VF,
1500         RTE_FLOW_ITEM_TYPE_END,
1501 };
1502
1503 /* Pattern matched tunnel filter */
1504 static enum rte_flow_item_type pattern_vxlan_1[] = {
1505         RTE_FLOW_ITEM_TYPE_ETH,
1506         RTE_FLOW_ITEM_TYPE_IPV4,
1507         RTE_FLOW_ITEM_TYPE_UDP,
1508         RTE_FLOW_ITEM_TYPE_VXLAN,
1509         RTE_FLOW_ITEM_TYPE_ETH,
1510         RTE_FLOW_ITEM_TYPE_END,
1511 };
1512
1513 static enum rte_flow_item_type pattern_vxlan_2[] = {
1514         RTE_FLOW_ITEM_TYPE_ETH,
1515         RTE_FLOW_ITEM_TYPE_IPV6,
1516         RTE_FLOW_ITEM_TYPE_UDP,
1517         RTE_FLOW_ITEM_TYPE_VXLAN,
1518         RTE_FLOW_ITEM_TYPE_ETH,
1519         RTE_FLOW_ITEM_TYPE_END,
1520 };
1521
1522 static enum rte_flow_item_type pattern_vxlan_3[] = {
1523         RTE_FLOW_ITEM_TYPE_ETH,
1524         RTE_FLOW_ITEM_TYPE_IPV4,
1525         RTE_FLOW_ITEM_TYPE_UDP,
1526         RTE_FLOW_ITEM_TYPE_VXLAN,
1527         RTE_FLOW_ITEM_TYPE_ETH,
1528         RTE_FLOW_ITEM_TYPE_VLAN,
1529         RTE_FLOW_ITEM_TYPE_END,
1530 };
1531
1532 static enum rte_flow_item_type pattern_vxlan_4[] = {
1533         RTE_FLOW_ITEM_TYPE_ETH,
1534         RTE_FLOW_ITEM_TYPE_IPV6,
1535         RTE_FLOW_ITEM_TYPE_UDP,
1536         RTE_FLOW_ITEM_TYPE_VXLAN,
1537         RTE_FLOW_ITEM_TYPE_ETH,
1538         RTE_FLOW_ITEM_TYPE_VLAN,
1539         RTE_FLOW_ITEM_TYPE_END,
1540 };
1541
1542 static enum rte_flow_item_type pattern_nvgre_1[] = {
1543         RTE_FLOW_ITEM_TYPE_ETH,
1544         RTE_FLOW_ITEM_TYPE_IPV4,
1545         RTE_FLOW_ITEM_TYPE_NVGRE,
1546         RTE_FLOW_ITEM_TYPE_ETH,
1547         RTE_FLOW_ITEM_TYPE_END,
1548 };
1549
1550 static enum rte_flow_item_type pattern_nvgre_2[] = {
1551         RTE_FLOW_ITEM_TYPE_ETH,
1552         RTE_FLOW_ITEM_TYPE_IPV6,
1553         RTE_FLOW_ITEM_TYPE_NVGRE,
1554         RTE_FLOW_ITEM_TYPE_ETH,
1555         RTE_FLOW_ITEM_TYPE_END,
1556 };
1557
1558 static enum rte_flow_item_type pattern_nvgre_3[] = {
1559         RTE_FLOW_ITEM_TYPE_ETH,
1560         RTE_FLOW_ITEM_TYPE_IPV4,
1561         RTE_FLOW_ITEM_TYPE_NVGRE,
1562         RTE_FLOW_ITEM_TYPE_ETH,
1563         RTE_FLOW_ITEM_TYPE_VLAN,
1564         RTE_FLOW_ITEM_TYPE_END,
1565 };
1566
1567 static enum rte_flow_item_type pattern_nvgre_4[] = {
1568         RTE_FLOW_ITEM_TYPE_ETH,
1569         RTE_FLOW_ITEM_TYPE_IPV6,
1570         RTE_FLOW_ITEM_TYPE_NVGRE,
1571         RTE_FLOW_ITEM_TYPE_ETH,
1572         RTE_FLOW_ITEM_TYPE_VLAN,
1573         RTE_FLOW_ITEM_TYPE_END,
1574 };
1575
1576 static enum rte_flow_item_type pattern_mpls_1[] = {
1577         RTE_FLOW_ITEM_TYPE_ETH,
1578         RTE_FLOW_ITEM_TYPE_IPV4,
1579         RTE_FLOW_ITEM_TYPE_UDP,
1580         RTE_FLOW_ITEM_TYPE_MPLS,
1581         RTE_FLOW_ITEM_TYPE_END,
1582 };
1583
1584 static enum rte_flow_item_type pattern_mpls_2[] = {
1585         RTE_FLOW_ITEM_TYPE_ETH,
1586         RTE_FLOW_ITEM_TYPE_IPV6,
1587         RTE_FLOW_ITEM_TYPE_UDP,
1588         RTE_FLOW_ITEM_TYPE_MPLS,
1589         RTE_FLOW_ITEM_TYPE_END,
1590 };
1591
1592 static enum rte_flow_item_type pattern_mpls_3[] = {
1593         RTE_FLOW_ITEM_TYPE_ETH,
1594         RTE_FLOW_ITEM_TYPE_IPV4,
1595         RTE_FLOW_ITEM_TYPE_GRE,
1596         RTE_FLOW_ITEM_TYPE_MPLS,
1597         RTE_FLOW_ITEM_TYPE_END,
1598 };
1599
1600 static enum rte_flow_item_type pattern_mpls_4[] = {
1601         RTE_FLOW_ITEM_TYPE_ETH,
1602         RTE_FLOW_ITEM_TYPE_IPV6,
1603         RTE_FLOW_ITEM_TYPE_GRE,
1604         RTE_FLOW_ITEM_TYPE_MPLS,
1605         RTE_FLOW_ITEM_TYPE_END,
1606 };
1607
1608 static enum rte_flow_item_type pattern_qinq_1[] = {
1609         RTE_FLOW_ITEM_TYPE_ETH,
1610         RTE_FLOW_ITEM_TYPE_VLAN,
1611         RTE_FLOW_ITEM_TYPE_VLAN,
1612         RTE_FLOW_ITEM_TYPE_END,
1613 };
1614
1615 static struct i40e_valid_pattern i40e_supported_patterns[] = {
1616         /* Ethertype */
1617         { pattern_ethertype, i40e_flow_parse_ethertype_filter },
1618         /* FDIR - support default flow type without flexible payload*/
1619         { pattern_ethertype, i40e_flow_parse_fdir_filter },
1620         { pattern_fdir_ipv4, i40e_flow_parse_fdir_filter },
1621         { pattern_fdir_ipv4_udp, i40e_flow_parse_fdir_filter },
1622         { pattern_fdir_ipv4_tcp, i40e_flow_parse_fdir_filter },
1623         { pattern_fdir_ipv4_sctp, i40e_flow_parse_fdir_filter },
1624         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_fdir_filter },
1625         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_fdir_filter },
1626         { pattern_fdir_ipv4_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1627         { pattern_fdir_ipv4_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1628         { pattern_fdir_ipv6, i40e_flow_parse_fdir_filter },
1629         { pattern_fdir_ipv6_udp, i40e_flow_parse_fdir_filter },
1630         { pattern_fdir_ipv6_tcp, i40e_flow_parse_fdir_filter },
1631         { pattern_fdir_ipv6_sctp, i40e_flow_parse_fdir_filter },
1632         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_fdir_filter },
1633         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_fdir_filter },
1634         { pattern_fdir_ipv6_gtpu_ipv4, i40e_flow_parse_fdir_filter },
1635         { pattern_fdir_ipv6_gtpu_ipv6, i40e_flow_parse_fdir_filter },
1636         /* FDIR - support default flow type with flexible payload */
1637         { pattern_fdir_ethertype_raw_1, i40e_flow_parse_fdir_filter },
1638         { pattern_fdir_ethertype_raw_2, i40e_flow_parse_fdir_filter },
1639         { pattern_fdir_ethertype_raw_3, i40e_flow_parse_fdir_filter },
1640         { pattern_fdir_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1641         { pattern_fdir_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1642         { pattern_fdir_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1643         { pattern_fdir_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1644         { pattern_fdir_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1645         { pattern_fdir_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1646         { pattern_fdir_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1647         { pattern_fdir_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1648         { pattern_fdir_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1649         { pattern_fdir_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1650         { pattern_fdir_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1651         { pattern_fdir_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1652         { pattern_fdir_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1653         { pattern_fdir_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1654         { pattern_fdir_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1655         { pattern_fdir_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1656         { pattern_fdir_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1657         { pattern_fdir_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1658         { pattern_fdir_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1659         { pattern_fdir_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1660         { pattern_fdir_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1661         { pattern_fdir_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1662         { pattern_fdir_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1663         { pattern_fdir_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1664         /* FDIR - support single vlan input set */
1665         { pattern_fdir_ethertype_vlan, i40e_flow_parse_fdir_filter },
1666         { pattern_fdir_vlan_ipv4, i40e_flow_parse_fdir_filter },
1667         { pattern_fdir_vlan_ipv4_udp, i40e_flow_parse_fdir_filter },
1668         { pattern_fdir_vlan_ipv4_tcp, i40e_flow_parse_fdir_filter },
1669         { pattern_fdir_vlan_ipv4_sctp, i40e_flow_parse_fdir_filter },
1670         { pattern_fdir_vlan_ipv6, i40e_flow_parse_fdir_filter },
1671         { pattern_fdir_vlan_ipv6_udp, i40e_flow_parse_fdir_filter },
1672         { pattern_fdir_vlan_ipv6_tcp, i40e_flow_parse_fdir_filter },
1673         { pattern_fdir_vlan_ipv6_sctp, i40e_flow_parse_fdir_filter },
1674         { pattern_fdir_ethertype_vlan_raw_1, i40e_flow_parse_fdir_filter },
1675         { pattern_fdir_ethertype_vlan_raw_2, i40e_flow_parse_fdir_filter },
1676         { pattern_fdir_ethertype_vlan_raw_3, i40e_flow_parse_fdir_filter },
1677         { pattern_fdir_vlan_ipv4_raw_1, i40e_flow_parse_fdir_filter },
1678         { pattern_fdir_vlan_ipv4_raw_2, i40e_flow_parse_fdir_filter },
1679         { pattern_fdir_vlan_ipv4_raw_3, i40e_flow_parse_fdir_filter },
1680         { pattern_fdir_vlan_ipv4_udp_raw_1, i40e_flow_parse_fdir_filter },
1681         { pattern_fdir_vlan_ipv4_udp_raw_2, i40e_flow_parse_fdir_filter },
1682         { pattern_fdir_vlan_ipv4_udp_raw_3, i40e_flow_parse_fdir_filter },
1683         { pattern_fdir_vlan_ipv4_tcp_raw_1, i40e_flow_parse_fdir_filter },
1684         { pattern_fdir_vlan_ipv4_tcp_raw_2, i40e_flow_parse_fdir_filter },
1685         { pattern_fdir_vlan_ipv4_tcp_raw_3, i40e_flow_parse_fdir_filter },
1686         { pattern_fdir_vlan_ipv4_sctp_raw_1, i40e_flow_parse_fdir_filter },
1687         { pattern_fdir_vlan_ipv4_sctp_raw_2, i40e_flow_parse_fdir_filter },
1688         { pattern_fdir_vlan_ipv4_sctp_raw_3, i40e_flow_parse_fdir_filter },
1689         { pattern_fdir_vlan_ipv6_raw_1, i40e_flow_parse_fdir_filter },
1690         { pattern_fdir_vlan_ipv6_raw_2, i40e_flow_parse_fdir_filter },
1691         { pattern_fdir_vlan_ipv6_raw_3, i40e_flow_parse_fdir_filter },
1692         { pattern_fdir_vlan_ipv6_udp_raw_1, i40e_flow_parse_fdir_filter },
1693         { pattern_fdir_vlan_ipv6_udp_raw_2, i40e_flow_parse_fdir_filter },
1694         { pattern_fdir_vlan_ipv6_udp_raw_3, i40e_flow_parse_fdir_filter },
1695         { pattern_fdir_vlan_ipv6_tcp_raw_1, i40e_flow_parse_fdir_filter },
1696         { pattern_fdir_vlan_ipv6_tcp_raw_2, i40e_flow_parse_fdir_filter },
1697         { pattern_fdir_vlan_ipv6_tcp_raw_3, i40e_flow_parse_fdir_filter },
1698         { pattern_fdir_vlan_ipv6_sctp_raw_1, i40e_flow_parse_fdir_filter },
1699         { pattern_fdir_vlan_ipv6_sctp_raw_2, i40e_flow_parse_fdir_filter },
1700         { pattern_fdir_vlan_ipv6_sctp_raw_3, i40e_flow_parse_fdir_filter },
1701         /* FDIR - support VF item */
1702         { pattern_fdir_ipv4_vf, i40e_flow_parse_fdir_filter },
1703         { pattern_fdir_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1704         { pattern_fdir_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1705         { pattern_fdir_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1706         { pattern_fdir_ipv6_vf, i40e_flow_parse_fdir_filter },
1707         { pattern_fdir_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1708         { pattern_fdir_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1709         { pattern_fdir_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1710         { pattern_fdir_ethertype_raw_1_vf, i40e_flow_parse_fdir_filter },
1711         { pattern_fdir_ethertype_raw_2_vf, i40e_flow_parse_fdir_filter },
1712         { pattern_fdir_ethertype_raw_3_vf, i40e_flow_parse_fdir_filter },
1713         { pattern_fdir_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1714         { pattern_fdir_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1715         { pattern_fdir_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1716         { pattern_fdir_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1717         { pattern_fdir_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1718         { pattern_fdir_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1719         { pattern_fdir_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1720         { pattern_fdir_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1721         { pattern_fdir_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1722         { pattern_fdir_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1723         { pattern_fdir_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1724         { pattern_fdir_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1725         { pattern_fdir_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1726         { pattern_fdir_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1727         { pattern_fdir_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1728         { pattern_fdir_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1729         { pattern_fdir_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1730         { pattern_fdir_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1731         { pattern_fdir_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1732         { pattern_fdir_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1733         { pattern_fdir_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1734         { pattern_fdir_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1735         { pattern_fdir_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1736         { pattern_fdir_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1737         { pattern_fdir_ethertype_vlan_vf, i40e_flow_parse_fdir_filter },
1738         { pattern_fdir_vlan_ipv4_vf, i40e_flow_parse_fdir_filter },
1739         { pattern_fdir_vlan_ipv4_udp_vf, i40e_flow_parse_fdir_filter },
1740         { pattern_fdir_vlan_ipv4_tcp_vf, i40e_flow_parse_fdir_filter },
1741         { pattern_fdir_vlan_ipv4_sctp_vf, i40e_flow_parse_fdir_filter },
1742         { pattern_fdir_vlan_ipv6_vf, i40e_flow_parse_fdir_filter },
1743         { pattern_fdir_vlan_ipv6_udp_vf, i40e_flow_parse_fdir_filter },
1744         { pattern_fdir_vlan_ipv6_tcp_vf, i40e_flow_parse_fdir_filter },
1745         { pattern_fdir_vlan_ipv6_sctp_vf, i40e_flow_parse_fdir_filter },
1746         { pattern_fdir_ethertype_vlan_raw_1_vf, i40e_flow_parse_fdir_filter },
1747         { pattern_fdir_ethertype_vlan_raw_2_vf, i40e_flow_parse_fdir_filter },
1748         { pattern_fdir_ethertype_vlan_raw_3_vf, i40e_flow_parse_fdir_filter },
1749         { pattern_fdir_vlan_ipv4_raw_1_vf, i40e_flow_parse_fdir_filter },
1750         { pattern_fdir_vlan_ipv4_raw_2_vf, i40e_flow_parse_fdir_filter },
1751         { pattern_fdir_vlan_ipv4_raw_3_vf, i40e_flow_parse_fdir_filter },
1752         { pattern_fdir_vlan_ipv4_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1753         { pattern_fdir_vlan_ipv4_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1754         { pattern_fdir_vlan_ipv4_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1755         { pattern_fdir_vlan_ipv4_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1756         { pattern_fdir_vlan_ipv4_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1757         { pattern_fdir_vlan_ipv4_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1758         { pattern_fdir_vlan_ipv4_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1759         { pattern_fdir_vlan_ipv4_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1760         { pattern_fdir_vlan_ipv4_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1761         { pattern_fdir_vlan_ipv6_raw_1_vf, i40e_flow_parse_fdir_filter },
1762         { pattern_fdir_vlan_ipv6_raw_2_vf, i40e_flow_parse_fdir_filter },
1763         { pattern_fdir_vlan_ipv6_raw_3_vf, i40e_flow_parse_fdir_filter },
1764         { pattern_fdir_vlan_ipv6_udp_raw_1_vf, i40e_flow_parse_fdir_filter },
1765         { pattern_fdir_vlan_ipv6_udp_raw_2_vf, i40e_flow_parse_fdir_filter },
1766         { pattern_fdir_vlan_ipv6_udp_raw_3_vf, i40e_flow_parse_fdir_filter },
1767         { pattern_fdir_vlan_ipv6_tcp_raw_1_vf, i40e_flow_parse_fdir_filter },
1768         { pattern_fdir_vlan_ipv6_tcp_raw_2_vf, i40e_flow_parse_fdir_filter },
1769         { pattern_fdir_vlan_ipv6_tcp_raw_3_vf, i40e_flow_parse_fdir_filter },
1770         { pattern_fdir_vlan_ipv6_sctp_raw_1_vf, i40e_flow_parse_fdir_filter },
1771         { pattern_fdir_vlan_ipv6_sctp_raw_2_vf, i40e_flow_parse_fdir_filter },
1772         { pattern_fdir_vlan_ipv6_sctp_raw_3_vf, i40e_flow_parse_fdir_filter },
1773         /* VXLAN */
1774         { pattern_vxlan_1, i40e_flow_parse_vxlan_filter },
1775         { pattern_vxlan_2, i40e_flow_parse_vxlan_filter },
1776         { pattern_vxlan_3, i40e_flow_parse_vxlan_filter },
1777         { pattern_vxlan_4, i40e_flow_parse_vxlan_filter },
1778         /* NVGRE */
1779         { pattern_nvgre_1, i40e_flow_parse_nvgre_filter },
1780         { pattern_nvgre_2, i40e_flow_parse_nvgre_filter },
1781         { pattern_nvgre_3, i40e_flow_parse_nvgre_filter },
1782         { pattern_nvgre_4, i40e_flow_parse_nvgre_filter },
1783         /* MPLSoUDP & MPLSoGRE */
1784         { pattern_mpls_1, i40e_flow_parse_mpls_filter },
1785         { pattern_mpls_2, i40e_flow_parse_mpls_filter },
1786         { pattern_mpls_3, i40e_flow_parse_mpls_filter },
1787         { pattern_mpls_4, i40e_flow_parse_mpls_filter },
1788         /* GTP-C & GTP-U */
1789         { pattern_fdir_ipv4_gtpc, i40e_flow_parse_gtp_filter },
1790         { pattern_fdir_ipv4_gtpu, i40e_flow_parse_gtp_filter },
1791         { pattern_fdir_ipv6_gtpc, i40e_flow_parse_gtp_filter },
1792         { pattern_fdir_ipv6_gtpu, i40e_flow_parse_gtp_filter },
1793         /* QINQ */
1794         { pattern_qinq_1, i40e_flow_parse_qinq_filter },
1795 };
1796
1797 #define NEXT_ITEM_OF_ACTION(act, actions, index)                        \
1798         do {                                                            \
1799                 act = actions + index;                                  \
1800                 while (act->type == RTE_FLOW_ACTION_TYPE_VOID) {        \
1801                         index++;                                        \
1802                         act = actions + index;                          \
1803                 }                                                       \
1804         } while (0)
1805
1806 /* Find the first VOID or non-VOID item pointer */
1807 static const struct rte_flow_item *
1808 i40e_find_first_item(const struct rte_flow_item *item, bool is_void)
1809 {
1810         bool is_find;
1811
1812         while (item->type != RTE_FLOW_ITEM_TYPE_END) {
1813                 if (is_void)
1814                         is_find = item->type == RTE_FLOW_ITEM_TYPE_VOID;
1815                 else
1816                         is_find = item->type != RTE_FLOW_ITEM_TYPE_VOID;
1817                 if (is_find)
1818                         break;
1819                 item++;
1820         }
1821         return item;
1822 }
1823
1824 /* Skip all VOID items of the pattern */
1825 static void
1826 i40e_pattern_skip_void_item(struct rte_flow_item *items,
1827                             const struct rte_flow_item *pattern)
1828 {
1829         uint32_t cpy_count = 0;
1830         const struct rte_flow_item *pb = pattern, *pe = pattern;
1831
1832         for (;;) {
1833                 /* Find a non-void item first */
1834                 pb = i40e_find_first_item(pb, false);
1835                 if (pb->type == RTE_FLOW_ITEM_TYPE_END) {
1836                         pe = pb;
1837                         break;
1838                 }
1839
1840                 /* Find a void item */
1841                 pe = i40e_find_first_item(pb + 1, true);
1842
1843                 cpy_count = pe - pb;
1844                 rte_memcpy(items, pb, sizeof(struct rte_flow_item) * cpy_count);
1845
1846                 items += cpy_count;
1847
1848                 if (pe->type == RTE_FLOW_ITEM_TYPE_END) {
1849                         pb = pe;
1850                         break;
1851                 }
1852
1853                 pb = pe + 1;
1854         }
1855         /* Copy the END item. */
1856         rte_memcpy(items, pe, sizeof(struct rte_flow_item));
1857 }
1858
1859 /* Check if the pattern matches a supported item type array */
1860 static bool
1861 i40e_match_pattern(enum rte_flow_item_type *item_array,
1862                    struct rte_flow_item *pattern)
1863 {
1864         struct rte_flow_item *item = pattern;
1865
1866         while ((*item_array == item->type) &&
1867                (*item_array != RTE_FLOW_ITEM_TYPE_END)) {
1868                 item_array++;
1869                 item++;
1870         }
1871
1872         return (*item_array == RTE_FLOW_ITEM_TYPE_END &&
1873                 item->type == RTE_FLOW_ITEM_TYPE_END);
1874 }
1875
1876 /* Find if there's parse filter function matched */
1877 static parse_filter_t
1878 i40e_find_parse_filter_func(struct rte_flow_item *pattern, uint32_t *idx)
1879 {
1880         parse_filter_t parse_filter = NULL;
1881         uint8_t i = *idx;
1882
1883         for (; i < RTE_DIM(i40e_supported_patterns); i++) {
1884                 if (i40e_match_pattern(i40e_supported_patterns[i].items,
1885                                         pattern)) {
1886                         parse_filter = i40e_supported_patterns[i].parse_filter;
1887                         break;
1888                 }
1889         }
1890
1891         *idx = ++i;
1892
1893         return parse_filter;
1894 }
1895
1896 /* Parse attributes */
1897 static int
1898 i40e_flow_parse_attr(const struct rte_flow_attr *attr,
1899                      struct rte_flow_error *error)
1900 {
1901         /* Must be input direction */
1902         if (!attr->ingress) {
1903                 rte_flow_error_set(error, EINVAL,
1904                                    RTE_FLOW_ERROR_TYPE_ATTR_INGRESS,
1905                                    attr, "Only support ingress.");
1906                 return -rte_errno;
1907         }
1908
1909         /* Not supported */
1910         if (attr->egress) {
1911                 rte_flow_error_set(error, EINVAL,
1912                                    RTE_FLOW_ERROR_TYPE_ATTR_EGRESS,
1913                                    attr, "Not support egress.");
1914                 return -rte_errno;
1915         }
1916
1917         /* Not supported */
1918         if (attr->priority) {
1919                 rte_flow_error_set(error, EINVAL,
1920                                    RTE_FLOW_ERROR_TYPE_ATTR_PRIORITY,
1921                                    attr, "Not support priority.");
1922                 return -rte_errno;
1923         }
1924
1925         /* Not supported */
1926         if (attr->group) {
1927                 rte_flow_error_set(error, EINVAL,
1928                                    RTE_FLOW_ERROR_TYPE_ATTR_GROUP,
1929                                    attr, "Not support group.");
1930                 return -rte_errno;
1931         }
1932
1933         return 0;
1934 }
1935
1936 static uint16_t
1937 i40e_get_outer_vlan(struct rte_eth_dev *dev)
1938 {
1939         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1940         int qinq = dev->data->dev_conf.rxmode.hw_vlan_extend;
1941         uint64_t reg_r = 0;
1942         uint16_t reg_id;
1943         uint16_t tpid;
1944
1945         if (qinq)
1946                 reg_id = 2;
1947         else
1948                 reg_id = 3;
1949
1950         i40e_aq_debug_read_register(hw, I40E_GL_SWT_L2TAGCTRL(reg_id),
1951                                     &reg_r, NULL);
1952
1953         tpid = (reg_r >> I40E_GL_SWT_L2TAGCTRL_ETHERTYPE_SHIFT) & 0xFFFF;
1954
1955         return tpid;
1956 }
1957
1958 /* 1. Last in item should be NULL as range is not supported.
1959  * 2. Supported filter types: MAC_ETHTYPE and ETHTYPE.
1960  * 3. SRC mac_addr mask should be 00:00:00:00:00:00.
1961  * 4. DST mac_addr mask should be 00:00:00:00:00:00 or
1962  *    FF:FF:FF:FF:FF:FF
1963  * 5. Ether_type mask should be 0xFFFF.
1964  */
1965 static int
1966 i40e_flow_parse_ethertype_pattern(struct rte_eth_dev *dev,
1967                                   const struct rte_flow_item *pattern,
1968                                   struct rte_flow_error *error,
1969                                   struct rte_eth_ethertype_filter *filter)
1970 {
1971         const struct rte_flow_item *item = pattern;
1972         const struct rte_flow_item_eth *eth_spec;
1973         const struct rte_flow_item_eth *eth_mask;
1974         enum rte_flow_item_type item_type;
1975         uint16_t outer_tpid;
1976
1977         outer_tpid = i40e_get_outer_vlan(dev);
1978
1979         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
1980                 if (item->last) {
1981                         rte_flow_error_set(error, EINVAL,
1982                                            RTE_FLOW_ERROR_TYPE_ITEM,
1983                                            item,
1984                                            "Not support range");
1985                         return -rte_errno;
1986                 }
1987                 item_type = item->type;
1988                 switch (item_type) {
1989                 case RTE_FLOW_ITEM_TYPE_ETH:
1990                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
1991                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
1992                         /* Get the MAC info. */
1993                         if (!eth_spec || !eth_mask) {
1994                                 rte_flow_error_set(error, EINVAL,
1995                                                    RTE_FLOW_ERROR_TYPE_ITEM,
1996                                                    item,
1997                                                    "NULL ETH spec/mask");
1998                                 return -rte_errno;
1999                         }
2000
2001                         /* Mask bits of source MAC address must be full of 0.
2002                          * Mask bits of destination MAC address must be full
2003                          * of 1 or full of 0.
2004                          */
2005                         if (!is_zero_ether_addr(&eth_mask->src) ||
2006                             (!is_zero_ether_addr(&eth_mask->dst) &&
2007                              !is_broadcast_ether_addr(&eth_mask->dst))) {
2008                                 rte_flow_error_set(error, EINVAL,
2009                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2010                                                    item,
2011                                                    "Invalid MAC_addr mask");
2012                                 return -rte_errno;
2013                         }
2014
2015                         if ((eth_mask->type & UINT16_MAX) != UINT16_MAX) {
2016                                 rte_flow_error_set(error, EINVAL,
2017                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2018                                                    item,
2019                                                    "Invalid ethertype mask");
2020                                 return -rte_errno;
2021                         }
2022
2023                         /* If mask bits of destination MAC address
2024                          * are full of 1, set RTE_ETHTYPE_FLAGS_MAC.
2025                          */
2026                         if (is_broadcast_ether_addr(&eth_mask->dst)) {
2027                                 filter->mac_addr = eth_spec->dst;
2028                                 filter->flags |= RTE_ETHTYPE_FLAGS_MAC;
2029                         } else {
2030                                 filter->flags &= ~RTE_ETHTYPE_FLAGS_MAC;
2031                         }
2032                         filter->ether_type = rte_be_to_cpu_16(eth_spec->type);
2033
2034                         if (filter->ether_type == ETHER_TYPE_IPv4 ||
2035                             filter->ether_type == ETHER_TYPE_IPv6 ||
2036                             filter->ether_type == ETHER_TYPE_LLDP ||
2037                             filter->ether_type == outer_tpid) {
2038                                 rte_flow_error_set(error, EINVAL,
2039                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2040                                                    item,
2041                                                    "Unsupported ether_type in"
2042                                                    " control packet filter.");
2043                                 return -rte_errno;
2044                         }
2045                         break;
2046                 default:
2047                         break;
2048                 }
2049         }
2050
2051         return 0;
2052 }
2053
2054 /* Ethertype action only supports QUEUE or DROP. */
2055 static int
2056 i40e_flow_parse_ethertype_action(struct rte_eth_dev *dev,
2057                                  const struct rte_flow_action *actions,
2058                                  struct rte_flow_error *error,
2059                                  struct rte_eth_ethertype_filter *filter)
2060 {
2061         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2062         const struct rte_flow_action *act;
2063         const struct rte_flow_action_queue *act_q;
2064         uint32_t index = 0;
2065
2066         /* Check if the first non-void action is QUEUE or DROP. */
2067         NEXT_ITEM_OF_ACTION(act, actions, index);
2068         if (act->type != RTE_FLOW_ACTION_TYPE_QUEUE &&
2069             act->type != RTE_FLOW_ACTION_TYPE_DROP) {
2070                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2071                                    act, "Not supported action.");
2072                 return -rte_errno;
2073         }
2074
2075         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
2076                 act_q = (const struct rte_flow_action_queue *)act->conf;
2077                 filter->queue = act_q->index;
2078                 if (filter->queue >= pf->dev_data->nb_rx_queues) {
2079                         rte_flow_error_set(error, EINVAL,
2080                                            RTE_FLOW_ERROR_TYPE_ACTION,
2081                                            act, "Invalid queue ID for"
2082                                            " ethertype_filter.");
2083                         return -rte_errno;
2084                 }
2085         } else {
2086                 filter->flags |= RTE_ETHTYPE_FLAGS_DROP;
2087         }
2088
2089         /* Check if the next non-void item is END */
2090         index++;
2091         NEXT_ITEM_OF_ACTION(act, actions, index);
2092         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
2093                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
2094                                    act, "Not supported action.");
2095                 return -rte_errno;
2096         }
2097
2098         return 0;
2099 }
2100
2101 static int
2102 i40e_flow_parse_ethertype_filter(struct rte_eth_dev *dev,
2103                                  const struct rte_flow_attr *attr,
2104                                  const struct rte_flow_item pattern[],
2105                                  const struct rte_flow_action actions[],
2106                                  struct rte_flow_error *error,
2107                                  union i40e_filter_t *filter)
2108 {
2109         struct rte_eth_ethertype_filter *ethertype_filter =
2110                 &filter->ethertype_filter;
2111         int ret;
2112
2113         ret = i40e_flow_parse_ethertype_pattern(dev, pattern, error,
2114                                                 ethertype_filter);
2115         if (ret)
2116                 return ret;
2117
2118         ret = i40e_flow_parse_ethertype_action(dev, actions, error,
2119                                                ethertype_filter);
2120         if (ret)
2121                 return ret;
2122
2123         ret = i40e_flow_parse_attr(attr, error);
2124         if (ret)
2125                 return ret;
2126
2127         cons_filter_type = RTE_ETH_FILTER_ETHERTYPE;
2128
2129         return ret;
2130 }
2131
2132 static int
2133 i40e_flow_check_raw_item(const struct rte_flow_item *item,
2134                          const struct rte_flow_item_raw *raw_spec,
2135                          struct rte_flow_error *error)
2136 {
2137         if (!raw_spec->relative) {
2138                 rte_flow_error_set(error, EINVAL,
2139                                    RTE_FLOW_ERROR_TYPE_ITEM,
2140                                    item,
2141                                    "Relative should be 1.");
2142                 return -rte_errno;
2143         }
2144
2145         if (raw_spec->offset % sizeof(uint16_t)) {
2146                 rte_flow_error_set(error, EINVAL,
2147                                    RTE_FLOW_ERROR_TYPE_ITEM,
2148                                    item,
2149                                    "Offset should be even.");
2150                 return -rte_errno;
2151         }
2152
2153         if (raw_spec->search || raw_spec->limit) {
2154                 rte_flow_error_set(error, EINVAL,
2155                                    RTE_FLOW_ERROR_TYPE_ITEM,
2156                                    item,
2157                                    "search or limit is not supported.");
2158                 return -rte_errno;
2159         }
2160
2161         if (raw_spec->offset < 0) {
2162                 rte_flow_error_set(error, EINVAL,
2163                                    RTE_FLOW_ERROR_TYPE_ITEM,
2164                                    item,
2165                                    "Offset should be non-negative.");
2166                 return -rte_errno;
2167         }
2168         return 0;
2169 }
2170
2171 static int
2172 i40e_flow_store_flex_pit(struct i40e_pf *pf,
2173                          struct i40e_fdir_flex_pit *flex_pit,
2174                          enum i40e_flxpld_layer_idx layer_idx,
2175                          uint8_t raw_id)
2176 {
2177         uint8_t field_idx;
2178
2179         field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + raw_id;
2180         /* Check if the configuration is conflicted */
2181         if (pf->fdir.flex_pit_flag[layer_idx] &&
2182             (pf->fdir.flex_set[field_idx].src_offset != flex_pit->src_offset ||
2183              pf->fdir.flex_set[field_idx].size != flex_pit->size ||
2184              pf->fdir.flex_set[field_idx].dst_offset != flex_pit->dst_offset))
2185                 return -1;
2186
2187         /* Check if the configuration exists. */
2188         if (pf->fdir.flex_pit_flag[layer_idx] &&
2189             (pf->fdir.flex_set[field_idx].src_offset == flex_pit->src_offset &&
2190              pf->fdir.flex_set[field_idx].size == flex_pit->size &&
2191              pf->fdir.flex_set[field_idx].dst_offset == flex_pit->dst_offset))
2192                 return 1;
2193
2194         pf->fdir.flex_set[field_idx].src_offset =
2195                 flex_pit->src_offset;
2196         pf->fdir.flex_set[field_idx].size =
2197                 flex_pit->size;
2198         pf->fdir.flex_set[field_idx].dst_offset =
2199                 flex_pit->dst_offset;
2200
2201         return 0;
2202 }
2203
2204 static int
2205 i40e_flow_store_flex_mask(struct i40e_pf *pf,
2206                           enum i40e_filter_pctype pctype,
2207                           uint8_t *mask)
2208 {
2209         struct i40e_fdir_flex_mask flex_mask;
2210         uint16_t mask_tmp;
2211         uint8_t i, nb_bitmask = 0;
2212
2213         memset(&flex_mask, 0, sizeof(struct i40e_fdir_flex_mask));
2214         for (i = 0; i < I40E_FDIR_MAX_FLEX_LEN; i += sizeof(uint16_t)) {
2215                 mask_tmp = I40E_WORD(mask[i], mask[i + 1]);
2216                 if (mask_tmp) {
2217                         flex_mask.word_mask |=
2218                                 I40E_FLEX_WORD_MASK(i / sizeof(uint16_t));
2219                         if (mask_tmp != UINT16_MAX) {
2220                                 flex_mask.bitmask[nb_bitmask].mask = ~mask_tmp;
2221                                 flex_mask.bitmask[nb_bitmask].offset =
2222                                         i / sizeof(uint16_t);
2223                                 nb_bitmask++;
2224                                 if (nb_bitmask > I40E_FDIR_BITMASK_NUM_WORD)
2225                                         return -1;
2226                         }
2227                 }
2228         }
2229         flex_mask.nb_bitmask = nb_bitmask;
2230
2231         if (pf->fdir.flex_mask_flag[pctype] &&
2232             (memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2233                     sizeof(struct i40e_fdir_flex_mask))))
2234                 return -2;
2235         else if (pf->fdir.flex_mask_flag[pctype] &&
2236                  !(memcmp(&flex_mask, &pf->fdir.flex_mask[pctype],
2237                           sizeof(struct i40e_fdir_flex_mask))))
2238                 return 1;
2239
2240         memcpy(&pf->fdir.flex_mask[pctype], &flex_mask,
2241                sizeof(struct i40e_fdir_flex_mask));
2242         return 0;
2243 }
2244
2245 static void
2246 i40e_flow_set_fdir_flex_pit(struct i40e_pf *pf,
2247                             enum i40e_flxpld_layer_idx layer_idx,
2248                             uint8_t raw_id)
2249 {
2250         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2251         uint32_t flx_pit;
2252         uint8_t field_idx;
2253         uint16_t min_next_off = 0;  /* in words */
2254         uint8_t i;
2255
2256         /* Set flex pit */
2257         for (i = 0; i < raw_id; i++) {
2258                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2259                 flx_pit = MK_FLX_PIT(pf->fdir.flex_set[field_idx].src_offset,
2260                                      pf->fdir.flex_set[field_idx].size,
2261                                      pf->fdir.flex_set[field_idx].dst_offset);
2262
2263                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2264                 min_next_off = pf->fdir.flex_set[field_idx].src_offset +
2265                         pf->fdir.flex_set[field_idx].size;
2266         }
2267
2268         for (; i < I40E_MAX_FLXPLD_FIED; i++) {
2269                 /* set the non-used register obeying register's constrain */
2270                 field_idx = layer_idx * I40E_MAX_FLXPLD_FIED + i;
2271                 flx_pit = MK_FLX_PIT(min_next_off, NONUSE_FLX_PIT_FSIZE,
2272                                      NONUSE_FLX_PIT_DEST_OFF);
2273                 I40E_WRITE_REG(hw, I40E_PRTQF_FLX_PIT(field_idx), flx_pit);
2274                 min_next_off++;
2275         }
2276
2277         pf->fdir.flex_pit_flag[layer_idx] = 1;
2278 }
2279
2280 static void
2281 i40e_flow_set_fdir_flex_msk(struct i40e_pf *pf,
2282                             enum i40e_filter_pctype pctype)
2283 {
2284         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2285         struct i40e_fdir_flex_mask *flex_mask;
2286         uint32_t flxinset, fd_mask;
2287         uint8_t i;
2288
2289         /* Set flex mask */
2290         flex_mask = &pf->fdir.flex_mask[pctype];
2291         flxinset = (flex_mask->word_mask <<
2292                     I40E_PRTQF_FD_FLXINSET_INSET_SHIFT) &
2293                 I40E_PRTQF_FD_FLXINSET_INSET_MASK;
2294         i40e_write_rx_ctl(hw, I40E_PRTQF_FD_FLXINSET(pctype), flxinset);
2295
2296         for (i = 0; i < flex_mask->nb_bitmask; i++) {
2297                 fd_mask = (flex_mask->bitmask[i].mask <<
2298                            I40E_PRTQF_FD_MSK_MASK_SHIFT) &
2299                         I40E_PRTQF_FD_MSK_MASK_MASK;
2300                 fd_mask |= ((flex_mask->bitmask[i].offset +
2301                              I40E_FLX_OFFSET_IN_FIELD_VECTOR) <<
2302                             I40E_PRTQF_FD_MSK_OFFSET_SHIFT) &
2303                         I40E_PRTQF_FD_MSK_OFFSET_MASK;
2304                 i40e_write_rx_ctl(hw, I40E_PRTQF_FD_MSK(pctype, i), fd_mask);
2305         }
2306
2307         pf->fdir.flex_mask_flag[pctype] = 1;
2308 }
2309
2310 static int
2311 i40e_flow_set_fdir_inset(struct i40e_pf *pf,
2312                          enum i40e_filter_pctype pctype,
2313                          uint64_t input_set)
2314 {
2315         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
2316         uint64_t inset_reg = 0;
2317         uint32_t mask_reg[I40E_INSET_MASK_NUM_REG] = {0};
2318         int i, num;
2319
2320         /* Check if the input set is valid */
2321         if (i40e_validate_input_set(pctype, RTE_ETH_FILTER_FDIR,
2322                                     input_set) != 0) {
2323                 PMD_DRV_LOG(ERR, "Invalid input set");
2324                 return -EINVAL;
2325         }
2326
2327         /* Check if the configuration is conflicted */
2328         if (pf->fdir.inset_flag[pctype] &&
2329             memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2330                 return -1;
2331
2332         if (pf->fdir.inset_flag[pctype] &&
2333             !memcmp(&pf->fdir.input_set[pctype], &input_set, sizeof(uint64_t)))
2334                 return 0;
2335
2336         num = i40e_generate_inset_mask_reg(input_set, mask_reg,
2337                                            I40E_INSET_MASK_NUM_REG);
2338         if (num < 0)
2339                 return -EINVAL;
2340
2341         inset_reg |= i40e_translate_input_set_reg(hw->mac.type, input_set);
2342
2343         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 0),
2344                              (uint32_t)(inset_reg & UINT32_MAX));
2345         i40e_check_write_reg(hw, I40E_PRTQF_FD_INSET(pctype, 1),
2346                              (uint32_t)((inset_reg >>
2347                                          I40E_32_BIT_WIDTH) & UINT32_MAX));
2348
2349         for (i = 0; i < num; i++)
2350                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype),
2351                                      mask_reg[i]);
2352
2353         /*clear unused mask registers of the pctype */
2354         for (i = num; i < I40E_INSET_MASK_NUM_REG; i++)
2355                 i40e_check_write_reg(hw, I40E_GLQF_FD_MSK(i, pctype), 0);
2356         I40E_WRITE_FLUSH(hw);
2357
2358         pf->fdir.input_set[pctype] = input_set;
2359         pf->fdir.inset_flag[pctype] = 1;
2360         return 0;
2361 }
2362
2363 static uint8_t
2364 i40e_flow_fdir_get_pctype_value(struct i40e_pf *pf,
2365                                 enum rte_flow_item_type item_type,
2366                                 struct i40e_fdir_filter_conf *filter)
2367 {
2368         struct i40e_customized_pctype *cus_pctype = NULL;
2369
2370         switch (item_type) {
2371         case RTE_FLOW_ITEM_TYPE_GTPC:
2372                 cus_pctype = i40e_find_customized_pctype(pf,
2373                                                          I40E_CUSTOMIZED_GTPC);
2374                 break;
2375         case RTE_FLOW_ITEM_TYPE_GTPU:
2376                 if (!filter->input.flow_ext.inner_ip)
2377                         cus_pctype = i40e_find_customized_pctype(pf,
2378                                                          I40E_CUSTOMIZED_GTPU);
2379                 else if (filter->input.flow_ext.iip_type ==
2380                          I40E_FDIR_IPTYPE_IPV4)
2381                         cus_pctype = i40e_find_customized_pctype(pf,
2382                                                  I40E_CUSTOMIZED_GTPU_IPV4);
2383                 else if (filter->input.flow_ext.iip_type ==
2384                          I40E_FDIR_IPTYPE_IPV6)
2385                         cus_pctype = i40e_find_customized_pctype(pf,
2386                                                  I40E_CUSTOMIZED_GTPU_IPV6);
2387                 break;
2388         default:
2389                 PMD_DRV_LOG(ERR, "Unsupported item type");
2390                 break;
2391         }
2392
2393         if (cus_pctype)
2394                 return cus_pctype->pctype;
2395
2396         return I40E_FILTER_PCTYPE_INVALID;
2397 }
2398
2399 /* 1. Last in item should be NULL as range is not supported.
2400  * 2. Supported patterns: refer to array i40e_supported_patterns.
2401  * 3. Default supported flow type and input set: refer to array
2402  *    valid_fdir_inset_table in i40e_ethdev.c.
2403  * 4. Mask of fields which need to be matched should be
2404  *    filled with 1.
2405  * 5. Mask of fields which needn't to be matched should be
2406  *    filled with 0.
2407  * 6. GTP profile supports GTPv1 only.
2408  * 7. GTP-C response message ('source_port' = 2123) is not supported.
2409  */
2410 static int
2411 i40e_flow_parse_fdir_pattern(struct rte_eth_dev *dev,
2412                              const struct rte_flow_item *pattern,
2413                              struct rte_flow_error *error,
2414                              struct i40e_fdir_filter_conf *filter)
2415 {
2416         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2417         const struct rte_flow_item *item = pattern;
2418         const struct rte_flow_item_eth *eth_spec, *eth_mask;
2419         const struct rte_flow_item_vlan *vlan_spec, *vlan_mask;
2420         const struct rte_flow_item_ipv4 *ipv4_spec, *ipv4_mask;
2421         const struct rte_flow_item_ipv6 *ipv6_spec, *ipv6_mask;
2422         const struct rte_flow_item_tcp *tcp_spec, *tcp_mask;
2423         const struct rte_flow_item_udp *udp_spec, *udp_mask;
2424         const struct rte_flow_item_sctp *sctp_spec, *sctp_mask;
2425         const struct rte_flow_item_gtp *gtp_spec, *gtp_mask;
2426         const struct rte_flow_item_raw *raw_spec, *raw_mask;
2427         const struct rte_flow_item_vf *vf_spec;
2428
2429         uint8_t pctype = 0;
2430         uint64_t input_set = I40E_INSET_NONE;
2431         uint16_t frag_off;
2432         enum rte_flow_item_type item_type;
2433         enum rte_flow_item_type l3 = RTE_FLOW_ITEM_TYPE_END;
2434         enum rte_flow_item_type cus_proto = RTE_FLOW_ITEM_TYPE_END;
2435         uint32_t i, j;
2436         uint8_t  ipv6_addr_mask[16] = {
2437                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
2438                 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF };
2439         enum i40e_flxpld_layer_idx layer_idx = I40E_FLXPLD_L2_IDX;
2440         uint8_t raw_id = 0;
2441         int32_t off_arr[I40E_MAX_FLXPLD_FIED];
2442         uint16_t len_arr[I40E_MAX_FLXPLD_FIED];
2443         struct i40e_fdir_flex_pit flex_pit;
2444         uint8_t next_dst_off = 0;
2445         uint8_t flex_mask[I40E_FDIR_MAX_FLEX_LEN];
2446         uint16_t flex_size;
2447         bool cfg_flex_pit = true;
2448         bool cfg_flex_msk = true;
2449         uint16_t outer_tpid;
2450         uint16_t ether_type;
2451         uint32_t vtc_flow_cpu;
2452         bool outer_ip = true;
2453         int ret;
2454
2455         memset(off_arr, 0, sizeof(off_arr));
2456         memset(len_arr, 0, sizeof(len_arr));
2457         memset(flex_mask, 0, I40E_FDIR_MAX_FLEX_LEN);
2458         outer_tpid = i40e_get_outer_vlan(dev);
2459         filter->input.flow_ext.customized_pctype = false;
2460         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
2461                 if (item->last) {
2462                         rte_flow_error_set(error, EINVAL,
2463                                            RTE_FLOW_ERROR_TYPE_ITEM,
2464                                            item,
2465                                            "Not support range");
2466                         return -rte_errno;
2467                 }
2468                 item_type = item->type;
2469                 switch (item_type) {
2470                 case RTE_FLOW_ITEM_TYPE_ETH:
2471                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
2472                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
2473
2474                         if (eth_spec && eth_mask) {
2475                                 if (!is_zero_ether_addr(&eth_mask->src) ||
2476                                     !is_zero_ether_addr(&eth_mask->dst)) {
2477                                         rte_flow_error_set(error, EINVAL,
2478                                                       RTE_FLOW_ERROR_TYPE_ITEM,
2479                                                       item,
2480                                                       "Invalid MAC_addr mask.");
2481                                         return -rte_errno;
2482                                 }
2483
2484                                 if ((eth_mask->type & UINT16_MAX) ==
2485                                     UINT16_MAX) {
2486                                         input_set |= I40E_INSET_LAST_ETHER_TYPE;
2487                                         filter->input.flow.l2_flow.ether_type =
2488                                                 eth_spec->type;
2489                                 }
2490
2491                                 ether_type = rte_be_to_cpu_16(eth_spec->type);
2492                                 if (ether_type == ETHER_TYPE_IPv4 ||
2493                                     ether_type == ETHER_TYPE_IPv6 ||
2494                                     ether_type == ETHER_TYPE_ARP ||
2495                                     ether_type == outer_tpid) {
2496                                         rte_flow_error_set(error, EINVAL,
2497                                                      RTE_FLOW_ERROR_TYPE_ITEM,
2498                                                      item,
2499                                                      "Unsupported ether_type.");
2500                                         return -rte_errno;
2501                                 }
2502                         }
2503
2504                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2505                         layer_idx = I40E_FLXPLD_L2_IDX;
2506
2507                         break;
2508                 case RTE_FLOW_ITEM_TYPE_VLAN:
2509                         vlan_spec =
2510                                 (const struct rte_flow_item_vlan *)item->spec;
2511                         vlan_mask =
2512                                 (const struct rte_flow_item_vlan *)item->mask;
2513                         if (vlan_spec && vlan_mask) {
2514                                 if (vlan_mask->tci ==
2515                                     rte_cpu_to_be_16(I40E_TCI_MASK)) {
2516                                         input_set |= I40E_INSET_VLAN_INNER;
2517                                         filter->input.flow_ext.vlan_tci =
2518                                                 vlan_spec->tci;
2519                                 }
2520                         }
2521
2522                         pctype = I40E_FILTER_PCTYPE_L2_PAYLOAD;
2523                         layer_idx = I40E_FLXPLD_L2_IDX;
2524
2525                         break;
2526                 case RTE_FLOW_ITEM_TYPE_IPV4:
2527                         l3 = RTE_FLOW_ITEM_TYPE_IPV4;
2528                         ipv4_spec =
2529                                 (const struct rte_flow_item_ipv4 *)item->spec;
2530                         ipv4_mask =
2531                                 (const struct rte_flow_item_ipv4 *)item->mask;
2532                         pctype = I40E_FILTER_PCTYPE_NONF_IPV4_OTHER;
2533                         layer_idx = I40E_FLXPLD_L3_IDX;
2534
2535                         if (ipv4_spec && ipv4_mask && outer_ip) {
2536                                 /* Check IPv4 mask and update input set */
2537                                 if (ipv4_mask->hdr.version_ihl ||
2538                                     ipv4_mask->hdr.total_length ||
2539                                     ipv4_mask->hdr.packet_id ||
2540                                     ipv4_mask->hdr.fragment_offset ||
2541                                     ipv4_mask->hdr.hdr_checksum) {
2542                                         rte_flow_error_set(error, EINVAL,
2543                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2544                                                    item,
2545                                                    "Invalid IPv4 mask.");
2546                                         return -rte_errno;
2547                                 }
2548
2549                                 if (ipv4_mask->hdr.src_addr == UINT32_MAX)
2550                                         input_set |= I40E_INSET_IPV4_SRC;
2551                                 if (ipv4_mask->hdr.dst_addr == UINT32_MAX)
2552                                         input_set |= I40E_INSET_IPV4_DST;
2553                                 if (ipv4_mask->hdr.type_of_service == UINT8_MAX)
2554                                         input_set |= I40E_INSET_IPV4_TOS;
2555                                 if (ipv4_mask->hdr.time_to_live == UINT8_MAX)
2556                                         input_set |= I40E_INSET_IPV4_TTL;
2557                                 if (ipv4_mask->hdr.next_proto_id == UINT8_MAX)
2558                                         input_set |= I40E_INSET_IPV4_PROTO;
2559
2560                                 /* Check if it is fragment. */
2561                                 frag_off = ipv4_spec->hdr.fragment_offset;
2562                                 frag_off = rte_be_to_cpu_16(frag_off);
2563                                 if (frag_off & IPV4_HDR_OFFSET_MASK ||
2564                                     frag_off & IPV4_HDR_MF_FLAG)
2565                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV4;
2566
2567                                 /* Get the filter info */
2568                                 filter->input.flow.ip4_flow.proto =
2569                                         ipv4_spec->hdr.next_proto_id;
2570                                 filter->input.flow.ip4_flow.tos =
2571                                         ipv4_spec->hdr.type_of_service;
2572                                 filter->input.flow.ip4_flow.ttl =
2573                                         ipv4_spec->hdr.time_to_live;
2574                                 filter->input.flow.ip4_flow.src_ip =
2575                                         ipv4_spec->hdr.src_addr;
2576                                 filter->input.flow.ip4_flow.dst_ip =
2577                                         ipv4_spec->hdr.dst_addr;
2578                         } else if (!ipv4_spec && !ipv4_mask && !outer_ip) {
2579                                 filter->input.flow_ext.inner_ip = true;
2580                                 filter->input.flow_ext.iip_type =
2581                                         I40E_FDIR_IPTYPE_IPV4;
2582                         } else if ((ipv4_spec || ipv4_mask) && !outer_ip) {
2583                                 rte_flow_error_set(error, EINVAL,
2584                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2585                                                    item,
2586                                                    "Invalid inner IPv4 mask.");
2587                                 return -rte_errno;
2588                         }
2589
2590                         if (outer_ip)
2591                                 outer_ip = false;
2592
2593                         break;
2594                 case RTE_FLOW_ITEM_TYPE_IPV6:
2595                         l3 = RTE_FLOW_ITEM_TYPE_IPV6;
2596                         ipv6_spec =
2597                                 (const struct rte_flow_item_ipv6 *)item->spec;
2598                         ipv6_mask =
2599                                 (const struct rte_flow_item_ipv6 *)item->mask;
2600                         pctype = I40E_FILTER_PCTYPE_NONF_IPV6_OTHER;
2601                         layer_idx = I40E_FLXPLD_L3_IDX;
2602
2603                         if (ipv6_spec && ipv6_mask && outer_ip) {
2604                                 /* Check IPv6 mask and update input set */
2605                                 if (ipv6_mask->hdr.payload_len) {
2606                                         rte_flow_error_set(error, EINVAL,
2607                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2608                                                    item,
2609                                                    "Invalid IPv6 mask");
2610                                         return -rte_errno;
2611                                 }
2612
2613                                 if (!memcmp(ipv6_mask->hdr.src_addr,
2614                                             ipv6_addr_mask,
2615                                             RTE_DIM(ipv6_mask->hdr.src_addr)))
2616                                         input_set |= I40E_INSET_IPV6_SRC;
2617                                 if (!memcmp(ipv6_mask->hdr.dst_addr,
2618                                             ipv6_addr_mask,
2619                                             RTE_DIM(ipv6_mask->hdr.dst_addr)))
2620                                         input_set |= I40E_INSET_IPV6_DST;
2621
2622                                 if ((ipv6_mask->hdr.vtc_flow &
2623                                      rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2624                                     == rte_cpu_to_be_32(I40E_IPV6_TC_MASK))
2625                                         input_set |= I40E_INSET_IPV6_TC;
2626                                 if (ipv6_mask->hdr.proto == UINT8_MAX)
2627                                         input_set |= I40E_INSET_IPV6_NEXT_HDR;
2628                                 if (ipv6_mask->hdr.hop_limits == UINT8_MAX)
2629                                         input_set |= I40E_INSET_IPV6_HOP_LIMIT;
2630
2631                                 /* Get filter info */
2632                                 vtc_flow_cpu =
2633                                       rte_be_to_cpu_32(ipv6_spec->hdr.vtc_flow);
2634                                 filter->input.flow.ipv6_flow.tc =
2635                                         (uint8_t)(vtc_flow_cpu >>
2636                                                   I40E_FDIR_IPv6_TC_OFFSET);
2637                                 filter->input.flow.ipv6_flow.proto =
2638                                         ipv6_spec->hdr.proto;
2639                                 filter->input.flow.ipv6_flow.hop_limits =
2640                                         ipv6_spec->hdr.hop_limits;
2641
2642                                 rte_memcpy(filter->input.flow.ipv6_flow.src_ip,
2643                                            ipv6_spec->hdr.src_addr, 16);
2644                                 rte_memcpy(filter->input.flow.ipv6_flow.dst_ip,
2645                                            ipv6_spec->hdr.dst_addr, 16);
2646
2647                                 /* Check if it is fragment. */
2648                                 if (ipv6_spec->hdr.proto ==
2649                                     I40E_IPV6_FRAG_HEADER)
2650                                         pctype = I40E_FILTER_PCTYPE_FRAG_IPV6;
2651                         } else if (!ipv6_spec && !ipv6_mask && !outer_ip) {
2652                                 filter->input.flow_ext.inner_ip = true;
2653                                 filter->input.flow_ext.iip_type =
2654                                         I40E_FDIR_IPTYPE_IPV6;
2655                         } else if ((ipv6_spec || ipv6_mask) && !outer_ip) {
2656                                 rte_flow_error_set(error, EINVAL,
2657                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2658                                                    item,
2659                                                    "Invalid inner IPv6 mask");
2660                                 return -rte_errno;
2661                         }
2662
2663                         if (outer_ip)
2664                                 outer_ip = false;
2665                         break;
2666                 case RTE_FLOW_ITEM_TYPE_TCP:
2667                         tcp_spec = (const struct rte_flow_item_tcp *)item->spec;
2668                         tcp_mask = (const struct rte_flow_item_tcp *)item->mask;
2669
2670                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2671                                 pctype =
2672                                         I40E_FILTER_PCTYPE_NONF_IPV4_TCP;
2673                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2674                                 pctype =
2675                                         I40E_FILTER_PCTYPE_NONF_IPV6_TCP;
2676                         if (tcp_spec && tcp_mask) {
2677                                 /* Check TCP mask and update input set */
2678                                 if (tcp_mask->hdr.sent_seq ||
2679                                     tcp_mask->hdr.recv_ack ||
2680                                     tcp_mask->hdr.data_off ||
2681                                     tcp_mask->hdr.tcp_flags ||
2682                                     tcp_mask->hdr.rx_win ||
2683                                     tcp_mask->hdr.cksum ||
2684                                     tcp_mask->hdr.tcp_urp) {
2685                                         rte_flow_error_set(error, EINVAL,
2686                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2687                                                    item,
2688                                                    "Invalid TCP mask");
2689                                         return -rte_errno;
2690                                 }
2691
2692                                 if (tcp_mask->hdr.src_port == UINT16_MAX)
2693                                         input_set |= I40E_INSET_SRC_PORT;
2694                                 if (tcp_mask->hdr.dst_port == UINT16_MAX)
2695                                         input_set |= I40E_INSET_DST_PORT;
2696
2697                                 /* Get filter info */
2698                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2699                                         filter->input.flow.tcp4_flow.src_port =
2700                                                 tcp_spec->hdr.src_port;
2701                                         filter->input.flow.tcp4_flow.dst_port =
2702                                                 tcp_spec->hdr.dst_port;
2703                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2704                                         filter->input.flow.tcp6_flow.src_port =
2705                                                 tcp_spec->hdr.src_port;
2706                                         filter->input.flow.tcp6_flow.dst_port =
2707                                                 tcp_spec->hdr.dst_port;
2708                                 }
2709                         }
2710
2711                         layer_idx = I40E_FLXPLD_L4_IDX;
2712
2713                         break;
2714                 case RTE_FLOW_ITEM_TYPE_UDP:
2715                         udp_spec = (const struct rte_flow_item_udp *)item->spec;
2716                         udp_mask = (const struct rte_flow_item_udp *)item->mask;
2717
2718                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2719                                 pctype =
2720                                         I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
2721                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2722                                 pctype =
2723                                         I40E_FILTER_PCTYPE_NONF_IPV6_UDP;
2724
2725                         if (udp_spec && udp_mask) {
2726                                 /* Check UDP mask and update input set*/
2727                                 if (udp_mask->hdr.dgram_len ||
2728                                     udp_mask->hdr.dgram_cksum) {
2729                                         rte_flow_error_set(error, EINVAL,
2730                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2731                                                    item,
2732                                                    "Invalid UDP mask");
2733                                         return -rte_errno;
2734                                 }
2735
2736                                 if (udp_mask->hdr.src_port == UINT16_MAX)
2737                                         input_set |= I40E_INSET_SRC_PORT;
2738                                 if (udp_mask->hdr.dst_port == UINT16_MAX)
2739                                         input_set |= I40E_INSET_DST_PORT;
2740
2741                                 /* Get filter info */
2742                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2743                                         filter->input.flow.udp4_flow.src_port =
2744                                                 udp_spec->hdr.src_port;
2745                                         filter->input.flow.udp4_flow.dst_port =
2746                                                 udp_spec->hdr.dst_port;
2747                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2748                                         filter->input.flow.udp6_flow.src_port =
2749                                                 udp_spec->hdr.src_port;
2750                                         filter->input.flow.udp6_flow.dst_port =
2751                                                 udp_spec->hdr.dst_port;
2752                                 }
2753                         }
2754
2755                         layer_idx = I40E_FLXPLD_L4_IDX;
2756
2757                         break;
2758                 case RTE_FLOW_ITEM_TYPE_GTPC:
2759                 case RTE_FLOW_ITEM_TYPE_GTPU:
2760                         if (!pf->gtp_support) {
2761                                 rte_flow_error_set(error, EINVAL,
2762                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2763                                                    item,
2764                                                    "Unsupported protocol");
2765                                 return -rte_errno;
2766                         }
2767
2768                         gtp_spec = (const struct rte_flow_item_gtp *)item->spec;
2769                         gtp_mask = (const struct rte_flow_item_gtp *)item->mask;
2770
2771                         if (gtp_spec && gtp_mask) {
2772                                 if (gtp_mask->v_pt_rsv_flags ||
2773                                     gtp_mask->msg_type ||
2774                                     gtp_mask->msg_len ||
2775                                     gtp_mask->teid != UINT32_MAX) {
2776                                         rte_flow_error_set(error, EINVAL,
2777                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2778                                                    item,
2779                                                    "Invalid GTP mask");
2780                                         return -rte_errno;
2781                                 }
2782
2783                                 filter->input.flow.gtp_flow.teid =
2784                                         gtp_spec->teid;
2785                                 filter->input.flow_ext.customized_pctype = true;
2786                                 cus_proto = item_type;
2787                         }
2788                         break;
2789                 case RTE_FLOW_ITEM_TYPE_SCTP:
2790                         sctp_spec =
2791                                 (const struct rte_flow_item_sctp *)item->spec;
2792                         sctp_mask =
2793                                 (const struct rte_flow_item_sctp *)item->mask;
2794
2795                         if (l3 == RTE_FLOW_ITEM_TYPE_IPV4)
2796                                 pctype =
2797                                         I40E_FILTER_PCTYPE_NONF_IPV4_SCTP;
2798                         else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6)
2799                                 pctype =
2800                                         I40E_FILTER_PCTYPE_NONF_IPV6_SCTP;
2801
2802                         if (sctp_spec && sctp_mask) {
2803                                 /* Check SCTP mask and update input set */
2804                                 if (sctp_mask->hdr.cksum) {
2805                                         rte_flow_error_set(error, EINVAL,
2806                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2807                                                    item,
2808                                                    "Invalid UDP mask");
2809                                         return -rte_errno;
2810                                 }
2811
2812                                 if (sctp_mask->hdr.src_port == UINT16_MAX)
2813                                         input_set |= I40E_INSET_SRC_PORT;
2814                                 if (sctp_mask->hdr.dst_port == UINT16_MAX)
2815                                         input_set |= I40E_INSET_DST_PORT;
2816                                 if (sctp_mask->hdr.tag == UINT32_MAX)
2817                                         input_set |= I40E_INSET_SCTP_VT;
2818
2819                                 /* Get filter info */
2820                                 if (l3 == RTE_FLOW_ITEM_TYPE_IPV4) {
2821                                         filter->input.flow.sctp4_flow.src_port =
2822                                                 sctp_spec->hdr.src_port;
2823                                         filter->input.flow.sctp4_flow.dst_port =
2824                                                 sctp_spec->hdr.dst_port;
2825                                         filter->input.flow.sctp4_flow.verify_tag
2826                                                 = sctp_spec->hdr.tag;
2827                                 } else if (l3 == RTE_FLOW_ITEM_TYPE_IPV6) {
2828                                         filter->input.flow.sctp6_flow.src_port =
2829                                                 sctp_spec->hdr.src_port;
2830                                         filter->input.flow.sctp6_flow.dst_port =
2831                                                 sctp_spec->hdr.dst_port;
2832                                         filter->input.flow.sctp6_flow.verify_tag
2833                                                 = sctp_spec->hdr.tag;
2834                                 }
2835                         }
2836
2837                         layer_idx = I40E_FLXPLD_L4_IDX;
2838
2839                         break;
2840                 case RTE_FLOW_ITEM_TYPE_RAW:
2841                         raw_spec = (const struct rte_flow_item_raw *)item->spec;
2842                         raw_mask = (const struct rte_flow_item_raw *)item->mask;
2843
2844                         if (!raw_spec || !raw_mask) {
2845                                 rte_flow_error_set(error, EINVAL,
2846                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2847                                                    item,
2848                                                    "NULL RAW spec/mask");
2849                                 return -rte_errno;
2850                         }
2851
2852                         ret = i40e_flow_check_raw_item(item, raw_spec, error);
2853                         if (ret < 0)
2854                                 return ret;
2855
2856                         off_arr[raw_id] = raw_spec->offset;
2857                         len_arr[raw_id] = raw_spec->length;
2858
2859                         flex_size = 0;
2860                         memset(&flex_pit, 0, sizeof(struct i40e_fdir_flex_pit));
2861                         flex_pit.size =
2862                                 raw_spec->length / sizeof(uint16_t);
2863                         flex_pit.dst_offset =
2864                                 next_dst_off / sizeof(uint16_t);
2865
2866                         for (i = 0; i <= raw_id; i++) {
2867                                 if (i == raw_id)
2868                                         flex_pit.src_offset +=
2869                                                 raw_spec->offset /
2870                                                 sizeof(uint16_t);
2871                                 else
2872                                         flex_pit.src_offset +=
2873                                                 (off_arr[i] + len_arr[i]) /
2874                                                 sizeof(uint16_t);
2875                                 flex_size += len_arr[i];
2876                         }
2877                         if (((flex_pit.src_offset + flex_pit.size) >=
2878                              I40E_MAX_FLX_SOURCE_OFF / sizeof(uint16_t)) ||
2879                                 flex_size > I40E_FDIR_MAX_FLEXLEN) {
2880                                 rte_flow_error_set(error, EINVAL,
2881                                            RTE_FLOW_ERROR_TYPE_ITEM,
2882                                            item,
2883                                            "Exceeds maxmial payload limit.");
2884                                 return -rte_errno;
2885                         }
2886
2887                         /* Store flex pit to SW */
2888                         ret = i40e_flow_store_flex_pit(pf, &flex_pit,
2889                                                        layer_idx, raw_id);
2890                         if (ret < 0) {
2891                                 rte_flow_error_set(error, EINVAL,
2892                                    RTE_FLOW_ERROR_TYPE_ITEM,
2893                                    item,
2894                                    "Conflict with the first flexible rule.");
2895                                 return -rte_errno;
2896                         } else if (ret > 0)
2897                                 cfg_flex_pit = false;
2898
2899                         for (i = 0; i < raw_spec->length; i++) {
2900                                 j = i + next_dst_off;
2901                                 filter->input.flow_ext.flexbytes[j] =
2902                                         raw_spec->pattern[i];
2903                                 flex_mask[j] = raw_mask->pattern[i];
2904                         }
2905
2906                         next_dst_off += raw_spec->length;
2907                         raw_id++;
2908                         break;
2909                 case RTE_FLOW_ITEM_TYPE_VF:
2910                         vf_spec = (const struct rte_flow_item_vf *)item->spec;
2911                         filter->input.flow_ext.is_vf = 1;
2912                         filter->input.flow_ext.dst_id = vf_spec->id;
2913                         if (filter->input.flow_ext.is_vf &&
2914                             filter->input.flow_ext.dst_id >= pf->vf_num) {
2915                                 rte_flow_error_set(error, EINVAL,
2916                                                    RTE_FLOW_ERROR_TYPE_ITEM,
2917                                                    item,
2918                                                    "Invalid VF ID for FDIR.");
2919                                 return -rte_errno;
2920                         }
2921                         break;
2922                 default:
2923                         break;
2924                 }
2925         }
2926
2927         /* Get customized pctype value */
2928         if (filter->input.flow_ext.customized_pctype) {
2929                 pctype = i40e_flow_fdir_get_pctype_value(pf, cus_proto, filter);
2930                 if (pctype == I40E_FILTER_PCTYPE_INVALID) {
2931                         rte_flow_error_set(error, EINVAL,
2932                                            RTE_FLOW_ERROR_TYPE_ITEM,
2933                                            item,
2934                                            "Unsupported pctype");
2935                         return -rte_errno;
2936                 }
2937         }
2938
2939         /* If customized pctype is not used, set fdir configuration.*/
2940         if (!filter->input.flow_ext.customized_pctype) {
2941                 ret = i40e_flow_set_fdir_inset(pf, pctype, input_set);
2942                 if (ret == -1) {
2943                         rte_flow_error_set(error, EINVAL,
2944                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2945                                            "Conflict with the first rule's input set.");
2946                         return -rte_errno;
2947                 } else if (ret == -EINVAL) {
2948                         rte_flow_error_set(error, EINVAL,
2949                                            RTE_FLOW_ERROR_TYPE_ITEM, item,
2950                                            "Invalid pattern mask.");
2951                         return -rte_errno;
2952                 }
2953
2954                 /* Store flex mask to SW */
2955                 ret = i40e_flow_store_flex_mask(pf, pctype, flex_mask);
2956                 if (ret == -1) {
2957                         rte_flow_error_set(error, EINVAL,
2958                                            RTE_FLOW_ERROR_TYPE_ITEM,
2959                                            item,
2960                                            "Exceed maximal number of bitmasks");
2961                         return -rte_errno;
2962                 } else if (ret == -2) {
2963                         rte_flow_error_set(error, EINVAL,
2964                                            RTE_FLOW_ERROR_TYPE_ITEM,
2965                                            item,
2966                                            "Conflict with the first flexible rule");
2967                         return -rte_errno;
2968                 } else if (ret > 0)
2969                         cfg_flex_msk = false;
2970
2971                 if (cfg_flex_pit)
2972                         i40e_flow_set_fdir_flex_pit(pf, layer_idx, raw_id);
2973
2974                 if (cfg_flex_msk)
2975                         i40e_flow_set_fdir_flex_msk(pf, pctype);
2976         }
2977
2978         filter->input.pctype = pctype;
2979
2980         return 0;
2981 }
2982
2983 /* Parse to get the action info of a FDIR filter.
2984  * FDIR action supports QUEUE or (QUEUE + MARK).
2985  */
2986 static int
2987 i40e_flow_parse_fdir_action(struct rte_eth_dev *dev,
2988                             const struct rte_flow_action *actions,
2989                             struct rte_flow_error *error,
2990                             struct i40e_fdir_filter_conf *filter)
2991 {
2992         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2993         const struct rte_flow_action *act;
2994         const struct rte_flow_action_queue *act_q;
2995         const struct rte_flow_action_mark *mark_spec;
2996         uint32_t index = 0;
2997
2998         /* Check if the first non-void action is QUEUE or DROP or PASSTHRU. */
2999         NEXT_ITEM_OF_ACTION(act, actions, index);
3000         switch (act->type) {
3001         case RTE_FLOW_ACTION_TYPE_QUEUE:
3002                 act_q = (const struct rte_flow_action_queue *)act->conf;
3003                 filter->action.rx_queue = act_q->index;
3004                 if ((!filter->input.flow_ext.is_vf &&
3005                      filter->action.rx_queue >= pf->dev_data->nb_rx_queues) ||
3006                     (filter->input.flow_ext.is_vf &&
3007                      filter->action.rx_queue >= pf->vf_nb_qps)) {
3008                         rte_flow_error_set(error, EINVAL,
3009                                            RTE_FLOW_ERROR_TYPE_ACTION, act,
3010                                            "Invalid queue ID for FDIR.");
3011                         return -rte_errno;
3012                 }
3013                 filter->action.behavior = I40E_FDIR_ACCEPT;
3014                 break;
3015         case RTE_FLOW_ACTION_TYPE_DROP:
3016                 filter->action.behavior = I40E_FDIR_REJECT;
3017                 break;
3018         case RTE_FLOW_ACTION_TYPE_PASSTHRU:
3019                 filter->action.behavior = I40E_FDIR_PASSTHRU;
3020                 break;
3021         default:
3022                 rte_flow_error_set(error, EINVAL,
3023                                    RTE_FLOW_ERROR_TYPE_ACTION, act,
3024                                    "Invalid action.");
3025                 return -rte_errno;
3026         }
3027
3028         /* Check if the next non-void item is MARK or FLAG or END. */
3029         index++;
3030         NEXT_ITEM_OF_ACTION(act, actions, index);
3031         switch (act->type) {
3032         case RTE_FLOW_ACTION_TYPE_MARK:
3033                 mark_spec = (const struct rte_flow_action_mark *)act->conf;
3034                 filter->action.report_status = I40E_FDIR_REPORT_ID;
3035                 filter->soft_id = mark_spec->id;
3036                 break;
3037         case RTE_FLOW_ACTION_TYPE_FLAG:
3038                 filter->action.report_status = I40E_FDIR_NO_REPORT_STATUS;
3039                 break;
3040         case RTE_FLOW_ACTION_TYPE_END:
3041                 return 0;
3042         default:
3043                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3044                                    act, "Invalid action.");
3045                 return -rte_errno;
3046         }
3047
3048         /* Check if the next non-void item is END */
3049         index++;
3050         NEXT_ITEM_OF_ACTION(act, actions, index);
3051         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3052                 rte_flow_error_set(error, EINVAL,
3053                                    RTE_FLOW_ERROR_TYPE_ACTION,
3054                                    act, "Invalid action.");
3055                 return -rte_errno;
3056         }
3057
3058         return 0;
3059 }
3060
3061 static int
3062 i40e_flow_parse_fdir_filter(struct rte_eth_dev *dev,
3063                             const struct rte_flow_attr *attr,
3064                             const struct rte_flow_item pattern[],
3065                             const struct rte_flow_action actions[],
3066                             struct rte_flow_error *error,
3067                             union i40e_filter_t *filter)
3068 {
3069         struct i40e_fdir_filter_conf *fdir_filter =
3070                 &filter->fdir_filter;
3071         int ret;
3072
3073         ret = i40e_flow_parse_fdir_pattern(dev, pattern, error, fdir_filter);
3074         if (ret)
3075                 return ret;
3076
3077         ret = i40e_flow_parse_fdir_action(dev, actions, error, fdir_filter);
3078         if (ret)
3079                 return ret;
3080
3081         ret = i40e_flow_parse_attr(attr, error);
3082         if (ret)
3083                 return ret;
3084
3085         cons_filter_type = RTE_ETH_FILTER_FDIR;
3086
3087         if (dev->data->dev_conf.fdir_conf.mode !=
3088             RTE_FDIR_MODE_PERFECT) {
3089                 rte_flow_error_set(error, ENOTSUP,
3090                                    RTE_FLOW_ERROR_TYPE_UNSPECIFIED,
3091                                    NULL,
3092                                    "Check the mode in fdir_conf.");
3093                 return -rte_errno;
3094         }
3095
3096         return 0;
3097 }
3098
3099 /* Parse to get the action info of a tunnel filter
3100  * Tunnel action only supports PF, VF and QUEUE.
3101  */
3102 static int
3103 i40e_flow_parse_tunnel_action(struct rte_eth_dev *dev,
3104                               const struct rte_flow_action *actions,
3105                               struct rte_flow_error *error,
3106                               struct i40e_tunnel_filter_conf *filter)
3107 {
3108         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3109         const struct rte_flow_action *act;
3110         const struct rte_flow_action_queue *act_q;
3111         const struct rte_flow_action_vf *act_vf;
3112         uint32_t index = 0;
3113
3114         /* Check if the first non-void action is PF or VF. */
3115         NEXT_ITEM_OF_ACTION(act, actions, index);
3116         if (act->type != RTE_FLOW_ACTION_TYPE_PF &&
3117             act->type != RTE_FLOW_ACTION_TYPE_VF) {
3118                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3119                                    act, "Not supported action.");
3120                 return -rte_errno;
3121         }
3122
3123         if (act->type == RTE_FLOW_ACTION_TYPE_VF) {
3124                 act_vf = (const struct rte_flow_action_vf *)act->conf;
3125                 filter->vf_id = act_vf->id;
3126                 filter->is_to_vf = 1;
3127                 if (filter->vf_id >= pf->vf_num) {
3128                         rte_flow_error_set(error, EINVAL,
3129                                    RTE_FLOW_ERROR_TYPE_ACTION,
3130                                    act, "Invalid VF ID for tunnel filter");
3131                         return -rte_errno;
3132                 }
3133         }
3134
3135         /* Check if the next non-void item is QUEUE */
3136         index++;
3137         NEXT_ITEM_OF_ACTION(act, actions, index);
3138         if (act->type == RTE_FLOW_ACTION_TYPE_QUEUE) {
3139                 act_q = (const struct rte_flow_action_queue *)act->conf;
3140                 filter->queue_id = act_q->index;
3141                 if ((!filter->is_to_vf) &&
3142                     (filter->queue_id >= pf->dev_data->nb_rx_queues)) {
3143                         rte_flow_error_set(error, EINVAL,
3144                                    RTE_FLOW_ERROR_TYPE_ACTION,
3145                                    act, "Invalid queue ID for tunnel filter");
3146                         return -rte_errno;
3147                 } else if (filter->is_to_vf &&
3148                            (filter->queue_id >= pf->vf_nb_qps)) {
3149                         rte_flow_error_set(error, EINVAL,
3150                                    RTE_FLOW_ERROR_TYPE_ACTION,
3151                                    act, "Invalid queue ID for tunnel filter");
3152                         return -rte_errno;
3153                 }
3154         }
3155
3156         /* Check if the next non-void item is END */
3157         index++;
3158         NEXT_ITEM_OF_ACTION(act, actions, index);
3159         if (act->type != RTE_FLOW_ACTION_TYPE_END) {
3160                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ACTION,
3161                                    act, "Not supported action.");
3162                 return -rte_errno;
3163         }
3164
3165         return 0;
3166 }
3167
3168 static uint16_t i40e_supported_tunnel_filter_types[] = {
3169         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID |
3170         ETH_TUNNEL_FILTER_IVLAN,
3171         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_IVLAN,
3172         ETH_TUNNEL_FILTER_IMAC | ETH_TUNNEL_FILTER_TENID,
3173         ETH_TUNNEL_FILTER_OMAC | ETH_TUNNEL_FILTER_TENID |
3174         ETH_TUNNEL_FILTER_IMAC,
3175         ETH_TUNNEL_FILTER_IMAC,
3176 };
3177
3178 static int
3179 i40e_check_tunnel_filter_type(uint8_t filter_type)
3180 {
3181         uint8_t i;
3182
3183         for (i = 0; i < RTE_DIM(i40e_supported_tunnel_filter_types); i++) {
3184                 if (filter_type == i40e_supported_tunnel_filter_types[i])
3185                         return 0;
3186         }
3187
3188         return -1;
3189 }
3190
3191 /* 1. Last in item should be NULL as range is not supported.
3192  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3193  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3194  * 3. Mask of fields which need to be matched should be
3195  *    filled with 1.
3196  * 4. Mask of fields which needn't to be matched should be
3197  *    filled with 0.
3198  */
3199 static int
3200 i40e_flow_parse_vxlan_pattern(__rte_unused struct rte_eth_dev *dev,
3201                               const struct rte_flow_item *pattern,
3202                               struct rte_flow_error *error,
3203                               struct i40e_tunnel_filter_conf *filter)
3204 {
3205         const struct rte_flow_item *item = pattern;
3206         const struct rte_flow_item_eth *eth_spec;
3207         const struct rte_flow_item_eth *eth_mask;
3208         const struct rte_flow_item_vxlan *vxlan_spec;
3209         const struct rte_flow_item_vxlan *vxlan_mask;
3210         const struct rte_flow_item_vlan *vlan_spec;
3211         const struct rte_flow_item_vlan *vlan_mask;
3212         uint8_t filter_type = 0;
3213         bool is_vni_masked = 0;
3214         uint8_t vni_mask[] = {0xFF, 0xFF, 0xFF};
3215         enum rte_flow_item_type item_type;
3216         bool vxlan_flag = 0;
3217         uint32_t tenant_id_be = 0;
3218         int ret;
3219
3220         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3221                 if (item->last) {
3222                         rte_flow_error_set(error, EINVAL,
3223                                            RTE_FLOW_ERROR_TYPE_ITEM,
3224                                            item,
3225                                            "Not support range");
3226                         return -rte_errno;
3227                 }
3228                 item_type = item->type;
3229                 switch (item_type) {
3230                 case RTE_FLOW_ITEM_TYPE_ETH:
3231                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
3232                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
3233
3234                         /* Check if ETH item is used for place holder.
3235                          * If yes, both spec and mask should be NULL.
3236                          * If no, both spec and mask shouldn't be NULL.
3237                          */
3238                         if ((!eth_spec && eth_mask) ||
3239                             (eth_spec && !eth_mask)) {
3240                                 rte_flow_error_set(error, EINVAL,
3241                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3242                                                    item,
3243                                                    "Invalid ether spec/mask");
3244                                 return -rte_errno;
3245                         }
3246
3247                         if (eth_spec && eth_mask) {
3248                                 /* DST address of inner MAC shouldn't be masked.
3249                                  * SRC address of Inner MAC should be masked.
3250                                  */
3251                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3252                                     !is_zero_ether_addr(&eth_mask->src) ||
3253                                     eth_mask->type) {
3254                                         rte_flow_error_set(error, EINVAL,
3255                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3256                                                    item,
3257                                                    "Invalid ether spec/mask");
3258                                         return -rte_errno;
3259                                 }
3260
3261                                 if (!vxlan_flag) {
3262                                         rte_memcpy(&filter->outer_mac,
3263                                                    &eth_spec->dst,
3264                                                    ETHER_ADDR_LEN);
3265                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3266                                 } else {
3267                                         rte_memcpy(&filter->inner_mac,
3268                                                    &eth_spec->dst,
3269                                                    ETHER_ADDR_LEN);
3270                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3271                                 }
3272                         }
3273                         break;
3274                 case RTE_FLOW_ITEM_TYPE_VLAN:
3275                         vlan_spec =
3276                                 (const struct rte_flow_item_vlan *)item->spec;
3277                         vlan_mask =
3278                                 (const struct rte_flow_item_vlan *)item->mask;
3279                         if (!(vlan_spec && vlan_mask)) {
3280                                 rte_flow_error_set(error, EINVAL,
3281                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3282                                                    item,
3283                                                    "Invalid vlan item");
3284                                 return -rte_errno;
3285                         }
3286
3287                         if (vlan_spec && vlan_mask) {
3288                                 if (vlan_mask->tci ==
3289                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3290                                         filter->inner_vlan =
3291                                               rte_be_to_cpu_16(vlan_spec->tci) &
3292                                               I40E_TCI_MASK;
3293                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3294                         }
3295                         break;
3296                 case RTE_FLOW_ITEM_TYPE_IPV4:
3297                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3298                         /* IPv4 is used to describe protocol,
3299                          * spec and mask should be NULL.
3300                          */
3301                         if (item->spec || item->mask) {
3302                                 rte_flow_error_set(error, EINVAL,
3303                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3304                                                    item,
3305                                                    "Invalid IPv4 item");
3306                                 return -rte_errno;
3307                         }
3308                         break;
3309                 case RTE_FLOW_ITEM_TYPE_IPV6:
3310                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3311                         /* IPv6 is used to describe protocol,
3312                          * spec and mask should be NULL.
3313                          */
3314                         if (item->spec || item->mask) {
3315                                 rte_flow_error_set(error, EINVAL,
3316                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3317                                                    item,
3318                                                    "Invalid IPv6 item");
3319                                 return -rte_errno;
3320                         }
3321                         break;
3322                 case RTE_FLOW_ITEM_TYPE_UDP:
3323                         /* UDP is used to describe protocol,
3324                          * spec and mask should be NULL.
3325                          */
3326                         if (item->spec || item->mask) {
3327                                 rte_flow_error_set(error, EINVAL,
3328                                            RTE_FLOW_ERROR_TYPE_ITEM,
3329                                            item,
3330                                            "Invalid UDP item");
3331                                 return -rte_errno;
3332                         }
3333                         break;
3334                 case RTE_FLOW_ITEM_TYPE_VXLAN:
3335                         vxlan_spec =
3336                                 (const struct rte_flow_item_vxlan *)item->spec;
3337                         vxlan_mask =
3338                                 (const struct rte_flow_item_vxlan *)item->mask;
3339                         /* Check if VXLAN item is used to describe protocol.
3340                          * If yes, both spec and mask should be NULL.
3341                          * If no, both spec and mask shouldn't be NULL.
3342                          */
3343                         if ((!vxlan_spec && vxlan_mask) ||
3344                             (vxlan_spec && !vxlan_mask)) {
3345                                 rte_flow_error_set(error, EINVAL,
3346                                            RTE_FLOW_ERROR_TYPE_ITEM,
3347                                            item,
3348                                            "Invalid VXLAN item");
3349                                 return -rte_errno;
3350                         }
3351
3352                         /* Check if VNI is masked. */
3353                         if (vxlan_spec && vxlan_mask) {
3354                                 is_vni_masked =
3355                                         !!memcmp(vxlan_mask->vni, vni_mask,
3356                                                  RTE_DIM(vni_mask));
3357                                 if (is_vni_masked) {
3358                                         rte_flow_error_set(error, EINVAL,
3359                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3360                                                    item,
3361                                                    "Invalid VNI mask");
3362                                         return -rte_errno;
3363                                 }
3364
3365                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3366                                            vxlan_spec->vni, 3);
3367                                 filter->tenant_id =
3368                                         rte_be_to_cpu_32(tenant_id_be);
3369                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3370                         }
3371
3372                         vxlan_flag = 1;
3373                         break;
3374                 default:
3375                         break;
3376                 }
3377         }
3378
3379         ret = i40e_check_tunnel_filter_type(filter_type);
3380         if (ret < 0) {
3381                 rte_flow_error_set(error, EINVAL,
3382                                    RTE_FLOW_ERROR_TYPE_ITEM,
3383                                    NULL,
3384                                    "Invalid filter type");
3385                 return -rte_errno;
3386         }
3387         filter->filter_type = filter_type;
3388
3389         filter->tunnel_type = I40E_TUNNEL_TYPE_VXLAN;
3390
3391         return 0;
3392 }
3393
3394 static int
3395 i40e_flow_parse_vxlan_filter(struct rte_eth_dev *dev,
3396                              const struct rte_flow_attr *attr,
3397                              const struct rte_flow_item pattern[],
3398                              const struct rte_flow_action actions[],
3399                              struct rte_flow_error *error,
3400                              union i40e_filter_t *filter)
3401 {
3402         struct i40e_tunnel_filter_conf *tunnel_filter =
3403                 &filter->consistent_tunnel_filter;
3404         int ret;
3405
3406         ret = i40e_flow_parse_vxlan_pattern(dev, pattern,
3407                                             error, tunnel_filter);
3408         if (ret)
3409                 return ret;
3410
3411         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3412         if (ret)
3413                 return ret;
3414
3415         ret = i40e_flow_parse_attr(attr, error);
3416         if (ret)
3417                 return ret;
3418
3419         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3420
3421         return ret;
3422 }
3423
3424 /* 1. Last in item should be NULL as range is not supported.
3425  * 2. Supported filter types: IMAC_IVLAN_TENID, IMAC_IVLAN,
3426  *    IMAC_TENID, OMAC_TENID_IMAC and IMAC.
3427  * 3. Mask of fields which need to be matched should be
3428  *    filled with 1.
3429  * 4. Mask of fields which needn't to be matched should be
3430  *    filled with 0.
3431  */
3432 static int
3433 i40e_flow_parse_nvgre_pattern(__rte_unused struct rte_eth_dev *dev,
3434                               const struct rte_flow_item *pattern,
3435                               struct rte_flow_error *error,
3436                               struct i40e_tunnel_filter_conf *filter)
3437 {
3438         const struct rte_flow_item *item = pattern;
3439         const struct rte_flow_item_eth *eth_spec;
3440         const struct rte_flow_item_eth *eth_mask;
3441         const struct rte_flow_item_nvgre *nvgre_spec;
3442         const struct rte_flow_item_nvgre *nvgre_mask;
3443         const struct rte_flow_item_vlan *vlan_spec;
3444         const struct rte_flow_item_vlan *vlan_mask;
3445         enum rte_flow_item_type item_type;
3446         uint8_t filter_type = 0;
3447         bool is_tni_masked = 0;
3448         uint8_t tni_mask[] = {0xFF, 0xFF, 0xFF};
3449         bool nvgre_flag = 0;
3450         uint32_t tenant_id_be = 0;
3451         int ret;
3452
3453         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3454                 if (item->last) {
3455                         rte_flow_error_set(error, EINVAL,
3456                                            RTE_FLOW_ERROR_TYPE_ITEM,
3457                                            item,
3458                                            "Not support range");
3459                         return -rte_errno;
3460                 }
3461                 item_type = item->type;
3462                 switch (item_type) {
3463                 case RTE_FLOW_ITEM_TYPE_ETH:
3464                         eth_spec = (const struct rte_flow_item_eth *)item->spec;
3465                         eth_mask = (const struct rte_flow_item_eth *)item->mask;
3466
3467                         /* Check if ETH item is used for place holder.
3468                          * If yes, both spec and mask should be NULL.
3469                          * If no, both spec and mask shouldn't be NULL.
3470                          */
3471                         if ((!eth_spec && eth_mask) ||
3472                             (eth_spec && !eth_mask)) {
3473                                 rte_flow_error_set(error, EINVAL,
3474                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3475                                                    item,
3476                                                    "Invalid ether spec/mask");
3477                                 return -rte_errno;
3478                         }
3479
3480                         if (eth_spec && eth_mask) {
3481                                 /* DST address of inner MAC shouldn't be masked.
3482                                  * SRC address of Inner MAC should be masked.
3483                                  */
3484                                 if (!is_broadcast_ether_addr(&eth_mask->dst) ||
3485                                     !is_zero_ether_addr(&eth_mask->src) ||
3486                                     eth_mask->type) {
3487                                         rte_flow_error_set(error, EINVAL,
3488                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3489                                                    item,
3490                                                    "Invalid ether spec/mask");
3491                                         return -rte_errno;
3492                                 }
3493
3494                                 if (!nvgre_flag) {
3495                                         rte_memcpy(&filter->outer_mac,
3496                                                    &eth_spec->dst,
3497                                                    ETHER_ADDR_LEN);
3498                                         filter_type |= ETH_TUNNEL_FILTER_OMAC;
3499                                 } else {
3500                                         rte_memcpy(&filter->inner_mac,
3501                                                    &eth_spec->dst,
3502                                                    ETHER_ADDR_LEN);
3503                                         filter_type |= ETH_TUNNEL_FILTER_IMAC;
3504                                 }
3505                         }
3506
3507                         break;
3508                 case RTE_FLOW_ITEM_TYPE_VLAN:
3509                         vlan_spec =
3510                                 (const struct rte_flow_item_vlan *)item->spec;
3511                         vlan_mask =
3512                                 (const struct rte_flow_item_vlan *)item->mask;
3513                         if (!(vlan_spec && vlan_mask)) {
3514                                 rte_flow_error_set(error, EINVAL,
3515                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3516                                                    item,
3517                                                    "Invalid vlan item");
3518                                 return -rte_errno;
3519                         }
3520
3521                         if (vlan_spec && vlan_mask) {
3522                                 if (vlan_mask->tci ==
3523                                     rte_cpu_to_be_16(I40E_TCI_MASK))
3524                                         filter->inner_vlan =
3525                                               rte_be_to_cpu_16(vlan_spec->tci) &
3526                                               I40E_TCI_MASK;
3527                                 filter_type |= ETH_TUNNEL_FILTER_IVLAN;
3528                         }
3529                         break;
3530                 case RTE_FLOW_ITEM_TYPE_IPV4:
3531                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3532                         /* IPv4 is used to describe protocol,
3533                          * spec and mask should be NULL.
3534                          */
3535                         if (item->spec || item->mask) {
3536                                 rte_flow_error_set(error, EINVAL,
3537                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3538                                                    item,
3539                                                    "Invalid IPv4 item");
3540                                 return -rte_errno;
3541                         }
3542                         break;
3543                 case RTE_FLOW_ITEM_TYPE_IPV6:
3544                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3545                         /* IPv6 is used to describe protocol,
3546                          * spec and mask should be NULL.
3547                          */
3548                         if (item->spec || item->mask) {
3549                                 rte_flow_error_set(error, EINVAL,
3550                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3551                                                    item,
3552                                                    "Invalid IPv6 item");
3553                                 return -rte_errno;
3554                         }
3555                         break;
3556                 case RTE_FLOW_ITEM_TYPE_NVGRE:
3557                         nvgre_spec =
3558                                 (const struct rte_flow_item_nvgre *)item->spec;
3559                         nvgre_mask =
3560                                 (const struct rte_flow_item_nvgre *)item->mask;
3561                         /* Check if NVGRE item is used to describe protocol.
3562                          * If yes, both spec and mask should be NULL.
3563                          * If no, both spec and mask shouldn't be NULL.
3564                          */
3565                         if ((!nvgre_spec && nvgre_mask) ||
3566                             (nvgre_spec && !nvgre_mask)) {
3567                                 rte_flow_error_set(error, EINVAL,
3568                                            RTE_FLOW_ERROR_TYPE_ITEM,
3569                                            item,
3570                                            "Invalid NVGRE item");
3571                                 return -rte_errno;
3572                         }
3573
3574                         if (nvgre_spec && nvgre_mask) {
3575                                 is_tni_masked =
3576                                         !!memcmp(nvgre_mask->tni, tni_mask,
3577                                                  RTE_DIM(tni_mask));
3578                                 if (is_tni_masked) {
3579                                         rte_flow_error_set(error, EINVAL,
3580                                                        RTE_FLOW_ERROR_TYPE_ITEM,
3581                                                        item,
3582                                                        "Invalid TNI mask");
3583                                         return -rte_errno;
3584                                 }
3585                                 rte_memcpy(((uint8_t *)&tenant_id_be + 1),
3586                                            nvgre_spec->tni, 3);
3587                                 filter->tenant_id =
3588                                         rte_be_to_cpu_32(tenant_id_be);
3589                                 filter_type |= ETH_TUNNEL_FILTER_TENID;
3590                         }
3591
3592                         nvgre_flag = 1;
3593                         break;
3594                 default:
3595                         break;
3596                 }
3597         }
3598
3599         ret = i40e_check_tunnel_filter_type(filter_type);
3600         if (ret < 0) {
3601                 rte_flow_error_set(error, EINVAL,
3602                                    RTE_FLOW_ERROR_TYPE_ITEM,
3603                                    NULL,
3604                                    "Invalid filter type");
3605                 return -rte_errno;
3606         }
3607         filter->filter_type = filter_type;
3608
3609         filter->tunnel_type = I40E_TUNNEL_TYPE_NVGRE;
3610
3611         return 0;
3612 }
3613
3614 static int
3615 i40e_flow_parse_nvgre_filter(struct rte_eth_dev *dev,
3616                              const struct rte_flow_attr *attr,
3617                              const struct rte_flow_item pattern[],
3618                              const struct rte_flow_action actions[],
3619                              struct rte_flow_error *error,
3620                              union i40e_filter_t *filter)
3621 {
3622         struct i40e_tunnel_filter_conf *tunnel_filter =
3623                 &filter->consistent_tunnel_filter;
3624         int ret;
3625
3626         ret = i40e_flow_parse_nvgre_pattern(dev, pattern,
3627                                             error, tunnel_filter);
3628         if (ret)
3629                 return ret;
3630
3631         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3632         if (ret)
3633                 return ret;
3634
3635         ret = i40e_flow_parse_attr(attr, error);
3636         if (ret)
3637                 return ret;
3638
3639         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3640
3641         return ret;
3642 }
3643
3644 /* 1. Last in item should be NULL as range is not supported.
3645  * 2. Supported filter types: MPLS label.
3646  * 3. Mask of fields which need to be matched should be
3647  *    filled with 1.
3648  * 4. Mask of fields which needn't to be matched should be
3649  *    filled with 0.
3650  */
3651 static int
3652 i40e_flow_parse_mpls_pattern(__rte_unused struct rte_eth_dev *dev,
3653                              const struct rte_flow_item *pattern,
3654                              struct rte_flow_error *error,
3655                              struct i40e_tunnel_filter_conf *filter)
3656 {
3657         const struct rte_flow_item *item = pattern;
3658         const struct rte_flow_item_mpls *mpls_spec;
3659         const struct rte_flow_item_mpls *mpls_mask;
3660         enum rte_flow_item_type item_type;
3661         bool is_mplsoudp = 0; /* 1 - MPLSoUDP, 0 - MPLSoGRE */
3662         const uint8_t label_mask[3] = {0xFF, 0xFF, 0xF0};
3663         uint32_t label_be = 0;
3664
3665         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3666                 if (item->last) {
3667                         rte_flow_error_set(error, EINVAL,
3668                                            RTE_FLOW_ERROR_TYPE_ITEM,
3669                                            item,
3670                                            "Not support range");
3671                         return -rte_errno;
3672                 }
3673                 item_type = item->type;
3674                 switch (item_type) {
3675                 case RTE_FLOW_ITEM_TYPE_ETH:
3676                         if (item->spec || item->mask) {
3677                                 rte_flow_error_set(error, EINVAL,
3678                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3679                                                    item,
3680                                                    "Invalid ETH item");
3681                                 return -rte_errno;
3682                         }
3683                         break;
3684                 case RTE_FLOW_ITEM_TYPE_IPV4:
3685                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3686                         /* IPv4 is used to describe protocol,
3687                          * spec and mask should be NULL.
3688                          */
3689                         if (item->spec || item->mask) {
3690                                 rte_flow_error_set(error, EINVAL,
3691                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3692                                                    item,
3693                                                    "Invalid IPv4 item");
3694                                 return -rte_errno;
3695                         }
3696                         break;
3697                 case RTE_FLOW_ITEM_TYPE_IPV6:
3698                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV6;
3699                         /* IPv6 is used to describe protocol,
3700                          * spec and mask should be NULL.
3701                          */
3702                         if (item->spec || item->mask) {
3703                                 rte_flow_error_set(error, EINVAL,
3704                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3705                                                    item,
3706                                                    "Invalid IPv6 item");
3707                                 return -rte_errno;
3708                         }
3709                         break;
3710                 case RTE_FLOW_ITEM_TYPE_UDP:
3711                         /* UDP is used to describe protocol,
3712                          * spec and mask should be NULL.
3713                          */
3714                         if (item->spec || item->mask) {
3715                                 rte_flow_error_set(error, EINVAL,
3716                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3717                                                    item,
3718                                                    "Invalid UDP item");
3719                                 return -rte_errno;
3720                         }
3721                         is_mplsoudp = 1;
3722                         break;
3723                 case RTE_FLOW_ITEM_TYPE_GRE:
3724                         /* GRE is used to describe protocol,
3725                          * spec and mask should be NULL.
3726                          */
3727                         if (item->spec || item->mask) {
3728                                 rte_flow_error_set(error, EINVAL,
3729                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3730                                                    item,
3731                                                    "Invalid GRE item");
3732                                 return -rte_errno;
3733                         }
3734                         break;
3735                 case RTE_FLOW_ITEM_TYPE_MPLS:
3736                         mpls_spec =
3737                                 (const struct rte_flow_item_mpls *)item->spec;
3738                         mpls_mask =
3739                                 (const struct rte_flow_item_mpls *)item->mask;
3740
3741                         if (!mpls_spec || !mpls_mask) {
3742                                 rte_flow_error_set(error, EINVAL,
3743                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3744                                                    item,
3745                                                    "Invalid MPLS item");
3746                                 return -rte_errno;
3747                         }
3748
3749                         if (memcmp(mpls_mask->label_tc_s, label_mask, 3)) {
3750                                 rte_flow_error_set(error, EINVAL,
3751                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3752                                                    item,
3753                                                    "Invalid MPLS label mask");
3754                                 return -rte_errno;
3755                         }
3756                         rte_memcpy(((uint8_t *)&label_be + 1),
3757                                    mpls_spec->label_tc_s, 3);
3758                         filter->tenant_id = rte_be_to_cpu_32(label_be) >> 4;
3759                         break;
3760                 default:
3761                         break;
3762                 }
3763         }
3764
3765         if (is_mplsoudp)
3766                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoUDP;
3767         else
3768                 filter->tunnel_type = I40E_TUNNEL_TYPE_MPLSoGRE;
3769
3770         return 0;
3771 }
3772
3773 static int
3774 i40e_flow_parse_mpls_filter(struct rte_eth_dev *dev,
3775                             const struct rte_flow_attr *attr,
3776                             const struct rte_flow_item pattern[],
3777                             const struct rte_flow_action actions[],
3778                             struct rte_flow_error *error,
3779                             union i40e_filter_t *filter)
3780 {
3781         struct i40e_tunnel_filter_conf *tunnel_filter =
3782                 &filter->consistent_tunnel_filter;
3783         int ret;
3784
3785         ret = i40e_flow_parse_mpls_pattern(dev, pattern,
3786                                            error, tunnel_filter);
3787         if (ret)
3788                 return ret;
3789
3790         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3791         if (ret)
3792                 return ret;
3793
3794         ret = i40e_flow_parse_attr(attr, error);
3795         if (ret)
3796                 return ret;
3797
3798         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3799
3800         return ret;
3801 }
3802
3803 /* 1. Last in item should be NULL as range is not supported.
3804  * 2. Supported filter types: GTP TEID.
3805  * 3. Mask of fields which need to be matched should be
3806  *    filled with 1.
3807  * 4. Mask of fields which needn't to be matched should be
3808  *    filled with 0.
3809  * 5. GTP profile supports GTPv1 only.
3810  * 6. GTP-C response message ('source_port' = 2123) is not supported.
3811  */
3812 static int
3813 i40e_flow_parse_gtp_pattern(struct rte_eth_dev *dev,
3814                             const struct rte_flow_item *pattern,
3815                             struct rte_flow_error *error,
3816                             struct i40e_tunnel_filter_conf *filter)
3817 {
3818         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3819         const struct rte_flow_item *item = pattern;
3820         const struct rte_flow_item_gtp *gtp_spec;
3821         const struct rte_flow_item_gtp *gtp_mask;
3822         enum rte_flow_item_type item_type;
3823
3824         if (!pf->gtp_support) {
3825                 rte_flow_error_set(error, EINVAL,
3826                                    RTE_FLOW_ERROR_TYPE_ITEM,
3827                                    item,
3828                                    "GTP is not supported by default.");
3829                 return -rte_errno;
3830         }
3831
3832         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3833                 if (item->last) {
3834                         rte_flow_error_set(error, EINVAL,
3835                                            RTE_FLOW_ERROR_TYPE_ITEM,
3836                                            item,
3837                                            "Not support range");
3838                         return -rte_errno;
3839                 }
3840                 item_type = item->type;
3841                 switch (item_type) {
3842                 case RTE_FLOW_ITEM_TYPE_ETH:
3843                         if (item->spec || item->mask) {
3844                                 rte_flow_error_set(error, EINVAL,
3845                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3846                                                    item,
3847                                                    "Invalid ETH item");
3848                                 return -rte_errno;
3849                         }
3850                         break;
3851                 case RTE_FLOW_ITEM_TYPE_IPV4:
3852                         filter->ip_type = I40E_TUNNEL_IPTYPE_IPV4;
3853                         /* IPv4 is used to describe protocol,
3854                          * spec and mask should be NULL.
3855                          */
3856                         if (item->spec || item->mask) {
3857                                 rte_flow_error_set(error, EINVAL,
3858                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3859                                                    item,
3860                                                    "Invalid IPv4 item");
3861                                 return -rte_errno;
3862                         }
3863                         break;
3864                 case RTE_FLOW_ITEM_TYPE_UDP:
3865                         if (item->spec || item->mask) {
3866                                 rte_flow_error_set(error, EINVAL,
3867                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3868                                                    item,
3869                                                    "Invalid UDP item");
3870                                 return -rte_errno;
3871                         }
3872                         break;
3873                 case RTE_FLOW_ITEM_TYPE_GTPC:
3874                 case RTE_FLOW_ITEM_TYPE_GTPU:
3875                         gtp_spec =
3876                                 (const struct rte_flow_item_gtp *)item->spec;
3877                         gtp_mask =
3878                                 (const struct rte_flow_item_gtp *)item->mask;
3879
3880                         if (!gtp_spec || !gtp_mask) {
3881                                 rte_flow_error_set(error, EINVAL,
3882                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3883                                                    item,
3884                                                    "Invalid GTP item");
3885                                 return -rte_errno;
3886                         }
3887
3888                         if (gtp_mask->v_pt_rsv_flags ||
3889                             gtp_mask->msg_type ||
3890                             gtp_mask->msg_len ||
3891                             gtp_mask->teid != UINT32_MAX) {
3892                                 rte_flow_error_set(error, EINVAL,
3893                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3894                                                    item,
3895                                                    "Invalid GTP mask");
3896                                 return -rte_errno;
3897                         }
3898
3899                         if (item_type == RTE_FLOW_ITEM_TYPE_GTPC)
3900                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPC;
3901                         else if (item_type == RTE_FLOW_ITEM_TYPE_GTPU)
3902                                 filter->tunnel_type = I40E_TUNNEL_TYPE_GTPU;
3903
3904                         filter->tenant_id = rte_be_to_cpu_32(gtp_spec->teid);
3905
3906                         break;
3907                 default:
3908                         break;
3909                 }
3910         }
3911
3912         return 0;
3913 }
3914
3915 static int
3916 i40e_flow_parse_gtp_filter(struct rte_eth_dev *dev,
3917                            const struct rte_flow_attr *attr,
3918                            const struct rte_flow_item pattern[],
3919                            const struct rte_flow_action actions[],
3920                            struct rte_flow_error *error,
3921                            union i40e_filter_t *filter)
3922 {
3923         struct i40e_tunnel_filter_conf *tunnel_filter =
3924                 &filter->consistent_tunnel_filter;
3925         int ret;
3926
3927         ret = i40e_flow_parse_gtp_pattern(dev, pattern,
3928                                           error, tunnel_filter);
3929         if (ret)
3930                 return ret;
3931
3932         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
3933         if (ret)
3934                 return ret;
3935
3936         ret = i40e_flow_parse_attr(attr, error);
3937         if (ret)
3938                 return ret;
3939
3940         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
3941
3942         return ret;
3943 }
3944
3945 /* 1. Last in item should be NULL as range is not supported.
3946  * 2. Supported filter types: QINQ.
3947  * 3. Mask of fields which need to be matched should be
3948  *    filled with 1.
3949  * 4. Mask of fields which needn't to be matched should be
3950  *    filled with 0.
3951  */
3952 static int
3953 i40e_flow_parse_qinq_pattern(__rte_unused struct rte_eth_dev *dev,
3954                               const struct rte_flow_item *pattern,
3955                               struct rte_flow_error *error,
3956                               struct i40e_tunnel_filter_conf *filter)
3957 {
3958         const struct rte_flow_item *item = pattern;
3959         const struct rte_flow_item_vlan *vlan_spec = NULL;
3960         const struct rte_flow_item_vlan *vlan_mask = NULL;
3961         const struct rte_flow_item_vlan *i_vlan_spec = NULL;
3962         const struct rte_flow_item_vlan *i_vlan_mask = NULL;
3963         const struct rte_flow_item_vlan *o_vlan_spec = NULL;
3964         const struct rte_flow_item_vlan *o_vlan_mask = NULL;
3965
3966         enum rte_flow_item_type item_type;
3967         bool vlan_flag = 0;
3968
3969         for (; item->type != RTE_FLOW_ITEM_TYPE_END; item++) {
3970                 if (item->last) {
3971                         rte_flow_error_set(error, EINVAL,
3972                                            RTE_FLOW_ERROR_TYPE_ITEM,
3973                                            item,
3974                                            "Not support range");
3975                         return -rte_errno;
3976                 }
3977                 item_type = item->type;
3978                 switch (item_type) {
3979                 case RTE_FLOW_ITEM_TYPE_ETH:
3980                         if (item->spec || item->mask) {
3981                                 rte_flow_error_set(error, EINVAL,
3982                                                    RTE_FLOW_ERROR_TYPE_ITEM,
3983                                                    item,
3984                                                    "Invalid ETH item");
3985                                 return -rte_errno;
3986                         }
3987                         break;
3988                 case RTE_FLOW_ITEM_TYPE_VLAN:
3989                         vlan_spec =
3990                                 (const struct rte_flow_item_vlan *)item->spec;
3991                         vlan_mask =
3992                                 (const struct rte_flow_item_vlan *)item->mask;
3993
3994                         if (!(vlan_spec && vlan_mask)) {
3995                                 rte_flow_error_set(error, EINVAL,
3996                                            RTE_FLOW_ERROR_TYPE_ITEM,
3997                                            item,
3998                                            "Invalid vlan item");
3999                                 return -rte_errno;
4000                         }
4001
4002                         if (!vlan_flag) {
4003                                 o_vlan_spec = vlan_spec;
4004                                 o_vlan_mask = vlan_mask;
4005                                 vlan_flag = 1;
4006                         } else {
4007                                 i_vlan_spec = vlan_spec;
4008                                 i_vlan_mask = vlan_mask;
4009                                 vlan_flag = 0;
4010                         }
4011                         break;
4012
4013                 default:
4014                         break;
4015                 }
4016         }
4017
4018         /* Get filter specification */
4019         if ((o_vlan_mask != NULL) && (o_vlan_mask->tci ==
4020                         rte_cpu_to_be_16(I40E_TCI_MASK)) &&
4021                         (i_vlan_mask != NULL) &&
4022                         (i_vlan_mask->tci == rte_cpu_to_be_16(I40E_TCI_MASK))) {
4023                 filter->outer_vlan = rte_be_to_cpu_16(o_vlan_spec->tci)
4024                         & I40E_TCI_MASK;
4025                 filter->inner_vlan = rte_be_to_cpu_16(i_vlan_spec->tci)
4026                         & I40E_TCI_MASK;
4027         } else {
4028                         rte_flow_error_set(error, EINVAL,
4029                                            RTE_FLOW_ERROR_TYPE_ITEM,
4030                                            NULL,
4031                                            "Invalid filter type");
4032                         return -rte_errno;
4033         }
4034
4035         filter->tunnel_type = I40E_TUNNEL_TYPE_QINQ;
4036         return 0;
4037 }
4038
4039 static int
4040 i40e_flow_parse_qinq_filter(struct rte_eth_dev *dev,
4041                               const struct rte_flow_attr *attr,
4042                               const struct rte_flow_item pattern[],
4043                               const struct rte_flow_action actions[],
4044                               struct rte_flow_error *error,
4045                               union i40e_filter_t *filter)
4046 {
4047         struct i40e_tunnel_filter_conf *tunnel_filter =
4048                 &filter->consistent_tunnel_filter;
4049         int ret;
4050
4051         ret = i40e_flow_parse_qinq_pattern(dev, pattern,
4052                                              error, tunnel_filter);
4053         if (ret)
4054                 return ret;
4055
4056         ret = i40e_flow_parse_tunnel_action(dev, actions, error, tunnel_filter);
4057         if (ret)
4058                 return ret;
4059
4060         ret = i40e_flow_parse_attr(attr, error);
4061         if (ret)
4062                 return ret;
4063
4064         cons_filter_type = RTE_ETH_FILTER_TUNNEL;
4065
4066         return ret;
4067 }
4068
4069 static int
4070 i40e_flow_validate(struct rte_eth_dev *dev,
4071                    const struct rte_flow_attr *attr,
4072                    const struct rte_flow_item pattern[],
4073                    const struct rte_flow_action actions[],
4074                    struct rte_flow_error *error)
4075 {
4076         struct rte_flow_item *items; /* internal pattern w/o VOID items */
4077         parse_filter_t parse_filter;
4078         uint32_t item_num = 0; /* non-void item number of pattern*/
4079         uint32_t i = 0;
4080         bool flag = false;
4081         int ret = I40E_NOT_SUPPORTED;
4082
4083         if (!pattern) {
4084                 rte_flow_error_set(error, EINVAL, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4085                                    NULL, "NULL pattern.");
4086                 return -rte_errno;
4087         }
4088
4089         if (!actions) {
4090                 rte_flow_error_set(error, EINVAL,
4091                                    RTE_FLOW_ERROR_TYPE_ACTION_NUM,
4092                                    NULL, "NULL action.");
4093                 return -rte_errno;
4094         }
4095
4096         if (!attr) {
4097                 rte_flow_error_set(error, EINVAL,
4098                                    RTE_FLOW_ERROR_TYPE_ATTR,
4099                                    NULL, "NULL attribute.");
4100                 return -rte_errno;
4101         }
4102
4103         memset(&cons_filter, 0, sizeof(cons_filter));
4104
4105         /* Get the non-void item number of pattern */
4106         while ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_END) {
4107                 if ((pattern + i)->type != RTE_FLOW_ITEM_TYPE_VOID)
4108                         item_num++;
4109                 i++;
4110         }
4111         item_num++;
4112
4113         items = rte_zmalloc("i40e_pattern",
4114                             item_num * sizeof(struct rte_flow_item), 0);
4115         if (!items) {
4116                 rte_flow_error_set(error, ENOMEM, RTE_FLOW_ERROR_TYPE_ITEM_NUM,
4117                                    NULL, "No memory for PMD internal items.");
4118                 return -ENOMEM;
4119         }
4120
4121         i40e_pattern_skip_void_item(items, pattern);
4122
4123         i = 0;
4124         do {
4125                 parse_filter = i40e_find_parse_filter_func(items, &i);
4126                 if (!parse_filter && !flag) {
4127                         rte_flow_error_set(error, EINVAL,
4128                                            RTE_FLOW_ERROR_TYPE_ITEM,
4129                                            pattern, "Unsupported pattern");
4130                         rte_free(items);
4131                         return -rte_errno;
4132                 }
4133                 if (parse_filter)
4134                         ret = parse_filter(dev, attr, items, actions,
4135                                            error, &cons_filter);
4136                 flag = true;
4137         } while ((ret < 0) && (i < RTE_DIM(i40e_supported_patterns)));
4138
4139         rte_free(items);
4140
4141         return ret;
4142 }
4143
4144 static struct rte_flow *
4145 i40e_flow_create(struct rte_eth_dev *dev,
4146                  const struct rte_flow_attr *attr,
4147                  const struct rte_flow_item pattern[],
4148                  const struct rte_flow_action actions[],
4149                  struct rte_flow_error *error)
4150 {
4151         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4152         struct rte_flow *flow;
4153         int ret;
4154
4155         flow = rte_zmalloc("i40e_flow", sizeof(struct rte_flow), 0);
4156         if (!flow) {
4157                 rte_flow_error_set(error, ENOMEM,
4158                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4159                                    "Failed to allocate memory");
4160                 return flow;
4161         }
4162
4163         ret = i40e_flow_validate(dev, attr, pattern, actions, error);
4164         if (ret < 0)
4165                 return NULL;
4166
4167         switch (cons_filter_type) {
4168         case RTE_ETH_FILTER_ETHERTYPE:
4169                 ret = i40e_ethertype_filter_set(pf,
4170                                         &cons_filter.ethertype_filter, 1);
4171                 if (ret)
4172                         goto free_flow;
4173                 flow->rule = TAILQ_LAST(&pf->ethertype.ethertype_list,
4174                                         i40e_ethertype_filter_list);
4175                 break;
4176         case RTE_ETH_FILTER_FDIR:
4177                 ret = i40e_flow_add_del_fdir_filter(dev,
4178                                        &cons_filter.fdir_filter, 1);
4179                 if (ret)
4180                         goto free_flow;
4181                 flow->rule = TAILQ_LAST(&pf->fdir.fdir_list,
4182                                         i40e_fdir_filter_list);
4183                 break;
4184         case RTE_ETH_FILTER_TUNNEL:
4185                 ret = i40e_dev_consistent_tunnel_filter_set(pf,
4186                             &cons_filter.consistent_tunnel_filter, 1);
4187                 if (ret)
4188                         goto free_flow;
4189                 flow->rule = TAILQ_LAST(&pf->tunnel.tunnel_list,
4190                                         i40e_tunnel_filter_list);
4191                 break;
4192         default:
4193                 goto free_flow;
4194         }
4195
4196         flow->filter_type = cons_filter_type;
4197         TAILQ_INSERT_TAIL(&pf->flow_list, flow, node);
4198         return flow;
4199
4200 free_flow:
4201         rte_flow_error_set(error, -ret,
4202                            RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4203                            "Failed to create flow.");
4204         rte_free(flow);
4205         return NULL;
4206 }
4207
4208 static int
4209 i40e_flow_destroy(struct rte_eth_dev *dev,
4210                   struct rte_flow *flow,
4211                   struct rte_flow_error *error)
4212 {
4213         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4214         enum rte_filter_type filter_type = flow->filter_type;
4215         int ret = 0;
4216
4217         switch (filter_type) {
4218         case RTE_ETH_FILTER_ETHERTYPE:
4219                 ret = i40e_flow_destroy_ethertype_filter(pf,
4220                          (struct i40e_ethertype_filter *)flow->rule);
4221                 break;
4222         case RTE_ETH_FILTER_TUNNEL:
4223                 ret = i40e_flow_destroy_tunnel_filter(pf,
4224                               (struct i40e_tunnel_filter *)flow->rule);
4225                 break;
4226         case RTE_ETH_FILTER_FDIR:
4227                 ret = i40e_flow_add_del_fdir_filter(dev,
4228                        &((struct i40e_fdir_filter *)flow->rule)->fdir, 0);
4229                 break;
4230         default:
4231                 PMD_DRV_LOG(WARNING, "Filter type (%d) not supported",
4232                             filter_type);
4233                 ret = -EINVAL;
4234                 break;
4235         }
4236
4237         if (!ret) {
4238                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4239                 rte_free(flow);
4240         } else
4241                 rte_flow_error_set(error, -ret,
4242                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4243                                    "Failed to destroy flow.");
4244
4245         return ret;
4246 }
4247
4248 static int
4249 i40e_flow_destroy_ethertype_filter(struct i40e_pf *pf,
4250                                    struct i40e_ethertype_filter *filter)
4251 {
4252         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4253         struct i40e_ethertype_rule *ethertype_rule = &pf->ethertype;
4254         struct i40e_ethertype_filter *node;
4255         struct i40e_control_filter_stats stats;
4256         uint16_t flags = 0;
4257         int ret = 0;
4258
4259         if (!(filter->flags & RTE_ETHTYPE_FLAGS_MAC))
4260                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC;
4261         if (filter->flags & RTE_ETHTYPE_FLAGS_DROP)
4262                 flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP;
4263         flags |= I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE;
4264
4265         memset(&stats, 0, sizeof(stats));
4266         ret = i40e_aq_add_rem_control_packet_filter(hw,
4267                                     filter->input.mac_addr.addr_bytes,
4268                                     filter->input.ether_type,
4269                                     flags, pf->main_vsi->seid,
4270                                     filter->queue, 0, &stats, NULL);
4271         if (ret < 0)
4272                 return ret;
4273
4274         node = i40e_sw_ethertype_filter_lookup(ethertype_rule, &filter->input);
4275         if (!node)
4276                 return -EINVAL;
4277
4278         ret = i40e_sw_ethertype_filter_del(pf, &node->input);
4279
4280         return ret;
4281 }
4282
4283 static int
4284 i40e_flow_destroy_tunnel_filter(struct i40e_pf *pf,
4285                                 struct i40e_tunnel_filter *filter)
4286 {
4287         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
4288         struct i40e_vsi *vsi;
4289         struct i40e_pf_vf *vf;
4290         struct i40e_aqc_add_rm_cloud_filt_elem_ext cld_filter;
4291         struct i40e_tunnel_rule *tunnel_rule = &pf->tunnel;
4292         struct i40e_tunnel_filter *node;
4293         bool big_buffer = 0;
4294         int ret = 0;
4295
4296         memset(&cld_filter, 0, sizeof(cld_filter));
4297         ether_addr_copy((struct ether_addr *)&filter->input.outer_mac,
4298                         (struct ether_addr *)&cld_filter.element.outer_mac);
4299         ether_addr_copy((struct ether_addr *)&filter->input.inner_mac,
4300                         (struct ether_addr *)&cld_filter.element.inner_mac);
4301         cld_filter.element.inner_vlan = filter->input.inner_vlan;
4302         cld_filter.element.flags = filter->input.flags;
4303         cld_filter.element.tenant_id = filter->input.tenant_id;
4304         cld_filter.element.queue_number = filter->queue;
4305         rte_memcpy(cld_filter.general_fields,
4306                    filter->input.general_fields,
4307                    sizeof(cld_filter.general_fields));
4308
4309         if (!filter->is_to_vf)
4310                 vsi = pf->main_vsi;
4311         else {
4312                 vf = &pf->vfs[filter->vf_id];
4313                 vsi = vf->vsi;
4314         }
4315
4316         if (((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X11) ==
4317             I40E_AQC_ADD_CLOUD_FILTER_0X11) ||
4318             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X12) ==
4319             I40E_AQC_ADD_CLOUD_FILTER_0X12) ||
4320             ((filter->input.flags & I40E_AQC_ADD_CLOUD_FILTER_0X10) ==
4321             I40E_AQC_ADD_CLOUD_FILTER_0X10))
4322                 big_buffer = 1;
4323
4324         if (big_buffer)
4325                 ret = i40e_aq_remove_cloud_filters_big_buffer(hw, vsi->seid,
4326                                                               &cld_filter, 1);
4327         else
4328                 ret = i40e_aq_remove_cloud_filters(hw, vsi->seid,
4329                                                    &cld_filter.element, 1);
4330         if (ret < 0)
4331                 return -ENOTSUP;
4332
4333         node = i40e_sw_tunnel_filter_lookup(tunnel_rule, &filter->input);
4334         if (!node)
4335                 return -EINVAL;
4336
4337         ret = i40e_sw_tunnel_filter_del(pf, &node->input);
4338
4339         return ret;
4340 }
4341
4342 static int
4343 i40e_flow_flush(struct rte_eth_dev *dev, struct rte_flow_error *error)
4344 {
4345         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4346         int ret;
4347
4348         ret = i40e_flow_flush_fdir_filter(pf);
4349         if (ret) {
4350                 rte_flow_error_set(error, -ret,
4351                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4352                                    "Failed to flush FDIR flows.");
4353                 return -rte_errno;
4354         }
4355
4356         ret = i40e_flow_flush_ethertype_filter(pf);
4357         if (ret) {
4358                 rte_flow_error_set(error, -ret,
4359                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4360                                    "Failed to ethertype flush flows.");
4361                 return -rte_errno;
4362         }
4363
4364         ret = i40e_flow_flush_tunnel_filter(pf);
4365         if (ret) {
4366                 rte_flow_error_set(error, -ret,
4367                                    RTE_FLOW_ERROR_TYPE_HANDLE, NULL,
4368                                    "Failed to flush tunnel flows.");
4369                 return -rte_errno;
4370         }
4371
4372         return ret;
4373 }
4374
4375 static int
4376 i40e_flow_flush_fdir_filter(struct i40e_pf *pf)
4377 {
4378         struct rte_eth_dev *dev = pf->adapter->eth_dev;
4379         struct i40e_fdir_info *fdir_info = &pf->fdir;
4380         struct i40e_fdir_filter *fdir_filter;
4381         enum i40e_filter_pctype pctype;
4382         struct rte_flow *flow;
4383         void *temp;
4384         int ret;
4385
4386         ret = i40e_fdir_flush(dev);
4387         if (!ret) {
4388                 /* Delete FDIR filters in FDIR list. */
4389                 while ((fdir_filter = TAILQ_FIRST(&fdir_info->fdir_list))) {
4390                         ret = i40e_sw_fdir_filter_del(pf,
4391                                                       &fdir_filter->fdir.input);
4392                         if (ret < 0)
4393                                 return ret;
4394                 }
4395
4396                 /* Delete FDIR flows in flow list. */
4397                 TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4398                         if (flow->filter_type == RTE_ETH_FILTER_FDIR) {
4399                                 TAILQ_REMOVE(&pf->flow_list, flow, node);
4400                                 rte_free(flow);
4401                         }
4402                 }
4403
4404                 for (pctype = I40E_FILTER_PCTYPE_NONF_IPV4_UDP;
4405                      pctype <= I40E_FILTER_PCTYPE_L2_PAYLOAD; pctype++)
4406                         pf->fdir.inset_flag[pctype] = 0;
4407         }
4408
4409         return ret;
4410 }
4411
4412 /* Flush all ethertype filters */
4413 static int
4414 i40e_flow_flush_ethertype_filter(struct i40e_pf *pf)
4415 {
4416         struct i40e_ethertype_filter_list
4417                 *ethertype_list = &pf->ethertype.ethertype_list;
4418         struct i40e_ethertype_filter *filter;
4419         struct rte_flow *flow;
4420         void *temp;
4421         int ret = 0;
4422
4423         while ((filter = TAILQ_FIRST(ethertype_list))) {
4424                 ret = i40e_flow_destroy_ethertype_filter(pf, filter);
4425                 if (ret)
4426                         return ret;
4427         }
4428
4429         /* Delete ethertype flows in flow list. */
4430         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4431                 if (flow->filter_type == RTE_ETH_FILTER_ETHERTYPE) {
4432                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4433                         rte_free(flow);
4434                 }
4435         }
4436
4437         return ret;
4438 }
4439
4440 /* Flush all tunnel filters */
4441 static int
4442 i40e_flow_flush_tunnel_filter(struct i40e_pf *pf)
4443 {
4444         struct i40e_tunnel_filter_list
4445                 *tunnel_list = &pf->tunnel.tunnel_list;
4446         struct i40e_tunnel_filter *filter;
4447         struct rte_flow *flow;
4448         void *temp;
4449         int ret = 0;
4450
4451         while ((filter = TAILQ_FIRST(tunnel_list))) {
4452                 ret = i40e_flow_destroy_tunnel_filter(pf, filter);
4453                 if (ret)
4454                         return ret;
4455         }
4456
4457         /* Delete tunnel flows in flow list. */
4458         TAILQ_FOREACH_SAFE(flow, &pf->flow_list, node, temp) {
4459                 if (flow->filter_type == RTE_ETH_FILTER_TUNNEL) {
4460                         TAILQ_REMOVE(&pf->flow_list, flow, node);
4461                         rte_free(flow);
4462                 }
4463         }
4464
4465         return ret;
4466 }