drivers/net/i40e/i40e_pf.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <sys/queue.h>
  35 #include <stdio.h>
  36 #include <errno.h>
  37 #include <stdint.h>
  38 #include <string.h>
  39 #include <unistd.h>
  40 #include <stdarg.h>
  41 #include <inttypes.h>
  42
  43 #include <rte_string_fns.h>
  44 #include <rte_pci.h>
  45 #include <rte_ether.h>
  46 #include <rte_ethdev.h>
  47 #include <rte_memzone.h>
  48 #include <rte_malloc.h>
  49 #include <rte_memcpy.h>
  50
  51 #include "i40e_logs.h"
  52 #include "base/i40e_prototype.h"
  53 #include "base/i40e_adminq_cmd.h"
  54 #include "base/i40e_type.h"
  55 #include "i40e_ethdev.h"
  56 #include "i40e_rxtx.h"
  57 #include "i40e_pf.h"
  58
  59 #define I40E_CFG_CRCSTRIP_DEFAULT 1
  60
  61 static int
  62 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
  63                            struct i40e_virtchnl_queue_select *qsel,
  64                            bool on);
  65
  66 /**
  67  * Bind PF queues with VSI and VF.
  68  **/
  69 static int
  70 i40e_pf_vf_queues_mapping(struct i40e_pf_vf *vf)
  71 {
  72         int i;
  73         struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
  74         uint16_t vsi_id = vf->vsi->vsi_id;
  75         uint16_t vf_id  = vf->vf_idx;
  76         uint16_t nb_qps = vf->vsi->nb_qps;
  77         uint16_t qbase  = vf->vsi->base_queue;
  78         uint16_t q1, q2;
  79         uint32_t val;
  80
  81         /*
  82          * VF should use scatter range queues. So, it needn't
  83          * to set QBASE in this register.
  84          */
  85         i40e_write_rx_ctl(hw, I40E_VSILAN_QBASE(vsi_id),
  86                           I40E_VSILAN_QBASE_VSIQTABLE_ENA_MASK);
  87
  88         /* Set to enable VFLAN_QTABLE[] registers valid */
  89         I40E_WRITE_REG(hw, I40E_VPLAN_MAPENA(vf_id),
  90                 I40E_VPLAN_MAPENA_TXRX_ENA_MASK);
  91
  92         /* map PF queues to VF */
  93         for (i = 0; i < nb_qps; i++) {
  94                 val = ((qbase + i) & I40E_VPLAN_QTABLE_QINDEX_MASK);
  95                 I40E_WRITE_REG(hw, I40E_VPLAN_QTABLE(i, vf_id), val);
  96         }
  97
  98         /* map PF queues to VSI */
  99         for (i = 0; i < I40E_MAX_QP_NUM_PER_VF / 2; i++) {
 100                 if (2 * i > nb_qps - 1)
 101                         q1 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
 102                 else
 103                         q1 = qbase + 2 * i;
 104
 105                 if (2 * i + 1 > nb_qps - 1)
 106                         q2 = I40E_VSILAN_QTABLE_QINDEX_0_MASK;
 107                 else
 108                         q2 = qbase + 2 * i + 1;
 109
 110                 val = (q2 << I40E_VSILAN_QTABLE_QINDEX_1_SHIFT) + q1;
 111                 i40e_write_rx_ctl(hw, I40E_VSILAN_QTABLE(i, vsi_id), val);
 112         }
 113         I40E_WRITE_FLUSH(hw);
 114
 115         return I40E_SUCCESS;
 116 }
 117
 118
 119 /**
 120  * Proceed VF reset operation.
 121  */
 122 int
 123 i40e_pf_host_vf_reset(struct i40e_pf_vf *vf, bool do_hw_reset)
 124 {
 125         uint32_t val, i;
 126         struct i40e_hw *hw;
 127         uint16_t vf_id, abs_vf_id, vf_msix_num;
 128         int ret;
 129         struct i40e_virtchnl_queue_select qsel;
 130
 131         if (vf == NULL)
 132                 return -EINVAL;
 133
 134         hw = I40E_PF_TO_HW(vf->pf);
 135         vf_id = vf->vf_idx;
 136         abs_vf_id = vf_id + hw->func_caps.vf_base_id;
 137
 138         /* Notify VF that we are in VFR progress */
 139         I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_INPROGRESS);
 140
 141         /*
 142          * If require a SW VF reset, a VFLR interrupt will be generated,
 143          * this function will be called again. To avoid it,
 144          * disable interrupt first.
 145          */
 146         if (do_hw_reset) {
 147                 vf->state = I40E_VF_INRESET;
 148                 val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
 149                 val |= I40E_VPGEN_VFRTRIG_VFSWR_MASK;
 150                 I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
 151                 I40E_WRITE_FLUSH(hw);
 152         }
 153
 154 #define VFRESET_MAX_WAIT_CNT 100
 155         /* Wait until VF reset is done */
 156         for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
 157                 rte_delay_us(10);
 158                 val = I40E_READ_REG(hw, I40E_VPGEN_VFRSTAT(vf_id));
 159                 if (val & I40E_VPGEN_VFRSTAT_VFRD_MASK)
 160                         break;
 161         }
 162
 163         if (i >= VFRESET_MAX_WAIT_CNT) {
 164                 PMD_DRV_LOG(ERR, "VF reset timeout");
 165                 return -ETIMEDOUT;
 166         }
 167
 168         /* This is not first time to do reset, do cleanup job first */
 169         if (vf->vsi) {
 170                 /* Disable queues */
 171                 memset(&qsel, 0, sizeof(qsel));
 172                 for (i = 0; i < vf->vsi->nb_qps; i++)
 173                         qsel.rx_queues |= 1 << i;
 174                 qsel.tx_queues = qsel.rx_queues;
 175                 ret = i40e_pf_host_switch_queues(vf, &qsel, false);
 176                 if (ret != I40E_SUCCESS) {
 177                         PMD_DRV_LOG(ERR, "Disable VF queues failed");
 178                         return -EFAULT;
 179                 }
 180
 181                 /* Disable VF interrupt setting */
 182                 vf_msix_num = hw->func_caps.num_msix_vectors_vf;
 183                 for (i = 0; i < vf_msix_num; i++) {
 184                         if (!i)
 185                                 val = I40E_VFINT_DYN_CTL0(vf_id);
 186                         else
 187                                 val = I40E_VFINT_DYN_CTLN(((vf_msix_num - 1) *
 188                                                         (vf_id)) + (i - 1));
 189                         I40E_WRITE_REG(hw, val, I40E_VFINT_DYN_CTLN_CLEARPBA_MASK);
 190                 }
 191                 I40E_WRITE_FLUSH(hw);
 192
 193                 /* remove VSI */
 194                 ret = i40e_vsi_release(vf->vsi);
 195                 if (ret != I40E_SUCCESS) {
 196                         PMD_DRV_LOG(ERR, "Release VSI failed");
 197                         return -EFAULT;
 198                 }
 199         }
 200
 201 #define I40E_VF_PCI_ADDR  0xAA
 202 #define I40E_VF_PEND_MASK 0x20
 203         /* Check the pending transactions of this VF */
 204         /* Use absolute VF id, refer to datasheet for details */
 205         I40E_WRITE_REG(hw, I40E_PF_PCI_CIAA, I40E_VF_PCI_ADDR |
 206                 (abs_vf_id << I40E_PF_PCI_CIAA_VF_NUM_SHIFT));
 207         for (i = 0; i < VFRESET_MAX_WAIT_CNT; i++) {
 208                 rte_delay_us(1);
 209                 val = I40E_READ_REG(hw, I40E_PF_PCI_CIAD);
 210                 if ((val & I40E_VF_PEND_MASK) == 0)
 211                         break;
 212         }
 213
 214         if (i >= VFRESET_MAX_WAIT_CNT) {
 215                 PMD_DRV_LOG(ERR, "Wait VF PCI transaction end timeout");
 216                 return -ETIMEDOUT;
 217         }
 218
 219         /* Reset done, Set COMPLETE flag and clear reset bit */
 220         I40E_WRITE_REG(hw, I40E_VFGEN_RSTAT1(vf_id), I40E_PF_VFR_COMPLETED);
 221         val = I40E_READ_REG(hw, I40E_VPGEN_VFRTRIG(vf_id));
 222         val &= ~I40E_VPGEN_VFRTRIG_VFSWR_MASK;
 223         I40E_WRITE_REG(hw, I40E_VPGEN_VFRTRIG(vf_id), val);
 224         vf->reset_cnt++;
 225         I40E_WRITE_FLUSH(hw);
 226
 227         /* Allocate resource again */
 228         vf->vsi = i40e_vsi_setup(vf->pf, I40E_VSI_SRIOV,
 229                         vf->pf->main_vsi, vf->vf_idx);
 230         if (vf->vsi == NULL) {
 231                 PMD_DRV_LOG(ERR, "Add vsi failed");
 232                 return -EFAULT;
 233         }
 234
 235         ret = i40e_pf_vf_queues_mapping(vf);
 236         if (ret != I40E_SUCCESS) {
 237                 PMD_DRV_LOG(ERR, "queue mapping error");
 238                 i40e_vsi_release(vf->vsi);
 239                 return -EFAULT;
 240         }
 241
 242         return ret;
 243 }
 244
 245 static int
 246 i40e_pf_host_send_msg_to_vf(struct i40e_pf_vf *vf,
 247                             uint32_t opcode,
 248                             uint32_t retval,
 249                             uint8_t *msg,
 250                             uint16_t msglen)
 251 {
 252         struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
 253         uint16_t abs_vf_id = hw->func_caps.vf_base_id + vf->vf_idx;
 254         int ret;
 255
 256         ret = i40e_aq_send_msg_to_vf(hw, abs_vf_id, opcode, retval,
 257                                                 msg, msglen, NULL);
 258         if (ret) {
 259                 PMD_INIT_LOG(ERR, "Fail to send message to VF, err %u",
 260                              hw->aq.asq_last_status);
 261         }
 262
 263         return ret;
 264 }
 265
 266 static void
 267 i40e_pf_host_process_cmd_version(struct i40e_pf_vf *vf)
 268 {
 269         struct i40e_virtchnl_version_info info;
 270
 271         info.major = I40E_DPDK_VERSION_MAJOR;
 272         info.minor = I40E_DPDK_VERSION_MINOR;
 273         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_VERSION,
 274                 I40E_SUCCESS, (uint8_t *)&info, sizeof(info));
 275 }
 276
 277 static int
 278 i40e_pf_host_process_cmd_reset_vf(struct i40e_pf_vf *vf)
 279 {
 280         i40e_pf_host_vf_reset(vf, 1);
 281
 282         /* No feedback will be sent to VF for VFLR */
 283         return I40E_SUCCESS;
 284 }
 285
 286 static int
 287 i40e_pf_host_process_cmd_get_vf_resource(struct i40e_pf_vf *vf)
 288 {
 289         struct i40e_virtchnl_vf_resource *vf_res = NULL;
 290         struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
 291         uint32_t len = 0;
 292         int ret = I40E_SUCCESS;
 293
 294         /* only have 1 VSI by default */
 295         len =  sizeof(struct i40e_virtchnl_vf_resource) +
 296                                 I40E_DEFAULT_VF_VSI_NUM *
 297                 sizeof(struct i40e_virtchnl_vsi_resource);
 298
 299         vf_res = rte_zmalloc("i40e_vf_res", len, 0);
 300         if (vf_res == NULL) {
 301                 PMD_DRV_LOG(ERR, "failed to allocate mem");
 302                 ret = I40E_ERR_NO_MEMORY;
 303                 vf_res = NULL;
 304                 len = 0;
 305                 goto send_msg;
 306         }
 307
 308         vf_res->vf_offload_flags = I40E_VIRTCHNL_VF_OFFLOAD_L2 |
 309                                 I40E_VIRTCHNL_VF_OFFLOAD_VLAN;
 310         vf_res->max_vectors = hw->func_caps.num_msix_vectors_vf;
 311         vf_res->num_queue_pairs = vf->vsi->nb_qps;
 312         vf_res->num_vsis = I40E_DEFAULT_VF_VSI_NUM;
 313
 314         /* Change below setting if PF host can support more VSIs for VF */
 315         vf_res->vsi_res[0].vsi_type = I40E_VSI_SRIOV;
 316         /* As assume Vf only has single VSI now, always return 0 */
 317         vf_res->vsi_res[0].vsi_id = 0;
 318         vf_res->vsi_res[0].num_queue_pairs = vf->vsi->nb_qps;
 319         ether_addr_copy(&vf->mac_addr,
 320                 (struct ether_addr *)vf_res->vsi_res[0].default_mac_addr);
 321
 322 send_msg:
 323         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_VF_RESOURCES,
 324                                         ret, (uint8_t *)vf_res, len);
 325         rte_free(vf_res);
 326
 327         return ret;
 328 }
 329
 330 static int
 331 i40e_pf_host_hmc_config_rxq(struct i40e_hw *hw,
 332                             struct i40e_pf_vf *vf,
 333                             struct i40e_virtchnl_rxq_info *rxq,
 334                             uint8_t crcstrip)
 335 {
 336         int err = I40E_SUCCESS;
 337         struct i40e_hmc_obj_rxq rx_ctx;
 338         uint16_t abs_queue_id = vf->vsi->base_queue + rxq->queue_id;
 339
 340         /* Clear the context structure first */
 341         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
 342         rx_ctx.dbuff = rxq->databuffer_size >> I40E_RXQ_CTX_DBUFF_SHIFT;
 343         rx_ctx.hbuff = rxq->hdr_size >> I40E_RXQ_CTX_HBUFF_SHIFT;
 344         rx_ctx.base = rxq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 345         rx_ctx.qlen = rxq->ring_len;
 346 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 347         rx_ctx.dsize = 1;
 348 #endif
 349
 350         if (rxq->splithdr_enabled) {
 351                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
 352                 rx_ctx.dtype = i40e_header_split_enabled;
 353         } else {
 354                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
 355                 rx_ctx.dtype = i40e_header_split_none;
 356         }
 357         rx_ctx.rxmax = rxq->max_pkt_size;
 358         rx_ctx.tphrdesc_ena = 1;
 359         rx_ctx.tphwdesc_ena = 1;
 360         rx_ctx.tphdata_ena = 1;
 361         rx_ctx.tphhead_ena = 1;
 362         rx_ctx.lrxqthresh = 2;
 363         rx_ctx.crcstrip = crcstrip;
 364         rx_ctx.l2tsel = 1;
 365         rx_ctx.prefena = 1;
 366
 367         err = i40e_clear_lan_rx_queue_context(hw, abs_queue_id);
 368         if (err != I40E_SUCCESS)
 369                 return err;
 370         err = i40e_set_lan_rx_queue_context(hw, abs_queue_id, &rx_ctx);
 371
 372         return err;
 373 }
 374
 375 static int
 376 i40e_pf_host_hmc_config_txq(struct i40e_hw *hw,
 377                             struct i40e_pf_vf *vf,
 378                             struct i40e_virtchnl_txq_info *txq)
 379 {
 380         int err = I40E_SUCCESS;
 381         struct i40e_hmc_obj_txq tx_ctx;
 382         uint32_t qtx_ctl;
 383         uint16_t abs_queue_id = vf->vsi->base_queue + txq->queue_id;
 384
 385
 386         /* clear the context structure first */
 387         memset(&tx_ctx, 0, sizeof(tx_ctx));
 388         tx_ctx.new_context = 1;
 389         tx_ctx.base = txq->dma_ring_addr / I40E_QUEUE_BASE_ADDR_UNIT;
 390         tx_ctx.qlen = txq->ring_len;
 391         tx_ctx.rdylist = rte_le_to_cpu_16(vf->vsi->info.qs_handle[0]);
 392         err = i40e_clear_lan_tx_queue_context(hw, abs_queue_id);
 393         if (err != I40E_SUCCESS)
 394                 return err;
 395
 396         err = i40e_set_lan_tx_queue_context(hw, abs_queue_id, &tx_ctx);
 397         if (err != I40E_SUCCESS)
 398                 return err;
 399
 400         /* bind queue with VF function, since TX/QX will appear in pair,
 401          * so only has QTX_CTL to set.
 402          */
 403         qtx_ctl = (I40E_QTX_CTL_VF_QUEUE << I40E_QTX_CTL_PFVF_Q_SHIFT) |
 404                                 ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
 405                                 I40E_QTX_CTL_PF_INDX_MASK) |
 406                                 (((vf->vf_idx + hw->func_caps.vf_base_id) <<
 407                                 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
 408                                 I40E_QTX_CTL_VFVM_INDX_MASK);
 409         I40E_WRITE_REG(hw, I40E_QTX_CTL(abs_queue_id), qtx_ctl);
 410         I40E_WRITE_FLUSH(hw);
 411
 412         return I40E_SUCCESS;
 413 }
 414
 415 static int
 416 i40e_pf_host_process_cmd_config_vsi_queues(struct i40e_pf_vf *vf,
 417                                            uint8_t *msg,
 418                                            uint16_t msglen)
 419 {
 420         struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
 421         struct i40e_vsi *vsi = vf->vsi;
 422         struct i40e_virtchnl_vsi_queue_config_info *vc_vqci =
 423                 (struct i40e_virtchnl_vsi_queue_config_info *)msg;
 424         struct i40e_virtchnl_queue_pair_info *vc_qpi;
 425         int i, ret = I40E_SUCCESS;
 426
 427         if (!msg || vc_vqci->num_queue_pairs > vsi->nb_qps ||
 428                 vc_vqci->num_queue_pairs > I40E_MAX_VSI_QP ||
 429                 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqci,
 430                                         vc_vqci->num_queue_pairs)) {
 431                 PMD_DRV_LOG(ERR, "vsi_queue_config_info argument wrong\n");
 432                 ret = I40E_ERR_PARAM;
 433                 goto send_msg;
 434         }
 435
 436         vc_qpi = vc_vqci->qpair;
 437         for (i = 0; i < vc_vqci->num_queue_pairs; i++) {
 438                 if (vc_qpi[i].rxq.queue_id > vsi->nb_qps - 1 ||
 439                         vc_qpi[i].txq.queue_id > vsi->nb_qps - 1) {
 440                         ret = I40E_ERR_PARAM;
 441                         goto send_msg;
 442                 }
 443
 444                 /*
 445                  * Apply VF RX queue setting to HMC.
 446                  * If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
 447                  * then the extra information of
 448                  * 'struct i40e_virtchnl_queue_pair_extra_info' is needed,
 449                  * otherwise set the last parameter to NULL.
 450                  */
 451                 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpi[i].rxq,
 452                         I40E_CFG_CRCSTRIP_DEFAULT) != I40E_SUCCESS) {
 453                         PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
 454                         ret = I40E_ERR_PARAM;
 455                         goto send_msg;
 456                 }
 457
 458                 /* Apply VF TX queue setting to HMC */
 459                 if (i40e_pf_host_hmc_config_txq(hw, vf,
 460                         &vc_qpi[i].txq) != I40E_SUCCESS) {
 461                         PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
 462                         ret = I40E_ERR_PARAM;
 463                         goto send_msg;
 464                 }
 465         }
 466
 467 send_msg:
 468         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES,
 469                                                         ret, NULL, 0);
 470
 471         return ret;
 472 }
 473
 474 static int
 475 i40e_pf_host_process_cmd_config_vsi_queues_ext(struct i40e_pf_vf *vf,
 476                                                uint8_t *msg,
 477                                                uint16_t msglen)
 478 {
 479         struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
 480         struct i40e_vsi *vsi = vf->vsi;
 481         struct i40e_virtchnl_vsi_queue_config_ext_info *vc_vqcei =
 482                 (struct i40e_virtchnl_vsi_queue_config_ext_info *)msg;
 483         struct i40e_virtchnl_queue_pair_ext_info *vc_qpei;
 484         int i, ret = I40E_SUCCESS;
 485
 486         if (!msg || vc_vqcei->num_queue_pairs > vsi->nb_qps ||
 487                 vc_vqcei->num_queue_pairs > I40E_MAX_VSI_QP ||
 488                 msglen < I40E_VIRTCHNL_CONFIG_VSI_QUEUES_SIZE(vc_vqcei,
 489                                         vc_vqcei->num_queue_pairs)) {
 490                 PMD_DRV_LOG(ERR, "vsi_queue_config_ext_info argument wrong\n");
 491                 ret = I40E_ERR_PARAM;
 492                 goto send_msg;
 493         }
 494
 495         vc_qpei = vc_vqcei->qpair;
 496         for (i = 0; i < vc_vqcei->num_queue_pairs; i++) {
 497                 if (vc_qpei[i].rxq.queue_id > vsi->nb_qps - 1 ||
 498                         vc_qpei[i].txq.queue_id > vsi->nb_qps - 1) {
 499                         ret = I40E_ERR_PARAM;
 500                         goto send_msg;
 501                 }
 502                 /*
 503                  * Apply VF RX queue setting to HMC.
 504                  * If the opcode is I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
 505                  * then the extra information of
 506                  * 'struct i40e_virtchnl_queue_pair_ext_info' is needed,
 507                  * otherwise set the last parameter to NULL.
 508                  */
 509                 if (i40e_pf_host_hmc_config_rxq(hw, vf, &vc_qpei[i].rxq,
 510                         vc_qpei[i].rxq_ext.crcstrip) != I40E_SUCCESS) {
 511                         PMD_DRV_LOG(ERR, "Configure RX queue HMC failed");
 512                         ret = I40E_ERR_PARAM;
 513                         goto send_msg;
 514                 }
 515
 516                 /* Apply VF TX queue setting to HMC */
 517                 if (i40e_pf_host_hmc_config_txq(hw, vf, &vc_qpei[i].txq) !=
 518                                                         I40E_SUCCESS) {
 519                         PMD_DRV_LOG(ERR, "Configure TX queue HMC failed");
 520                         ret = I40E_ERR_PARAM;
 521                         goto send_msg;
 522                 }
 523         }
 524
 525 send_msg:
 526         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT,
 527                                                                 ret, NULL, 0);
 528
 529         return ret;
 530 }
 531
 532 static int
 533 i40e_pf_host_process_cmd_config_irq_map(struct i40e_pf_vf *vf,
 534                                         uint8_t *msg, uint16_t msglen)
 535 {
 536         int ret = I40E_SUCCESS;
 537         struct i40e_virtchnl_irq_map_info *irqmap =
 538             (struct i40e_virtchnl_irq_map_info *)msg;
 539
 540         if (msg == NULL || msglen < sizeof(struct i40e_virtchnl_irq_map_info)) {
 541                 PMD_DRV_LOG(ERR, "buffer too short");
 542                 ret = I40E_ERR_PARAM;
 543                 goto send_msg;
 544         }
 545
 546         /* Assume VF only have 1 vector to bind all queues */
 547         if (irqmap->num_vectors != 1) {
 548                 PMD_DRV_LOG(ERR, "DKDK host only support 1 vector");
 549                 ret = I40E_ERR_PARAM;
 550                 goto send_msg;
 551         }
 552
 553         /* This MSIX intr store the intr in VF range */
 554         vf->vsi->msix_intr = irqmap->vecmap[0].vector_id;
 555         vf->vsi->nb_msix = irqmap->num_vectors;
 556         vf->vsi->nb_used_qps = vf->vsi->nb_qps;
 557
 558         /* Don't care how the TX/RX queue mapping with this vector.
 559          * Link all VF RX queues together. Only did mapping work.
 560          * VF can disable/enable the intr by itself.
 561          */
 562         i40e_vsi_queues_bind_intr(vf->vsi);
 563 send_msg:
 564         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP,
 565                                                         ret, NULL, 0);
 566
 567         return ret;
 568 }
 569
 570 static int
 571 i40e_pf_host_switch_queues(struct i40e_pf_vf *vf,
 572                            struct i40e_virtchnl_queue_select *qsel,
 573                            bool on)
 574 {
 575         int ret = I40E_SUCCESS;
 576         int i;
 577         struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
 578         uint16_t baseq = vf->vsi->base_queue;
 579
 580         if (qsel->rx_queues + qsel->tx_queues == 0)
 581                 return I40E_ERR_PARAM;
 582
 583         /* always enable RX first and disable last */
 584         /* Enable RX if it's enable */
 585         if (on) {
 586                 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
 587                         if (qsel->rx_queues & (1 << i)) {
 588                                 ret = i40e_switch_rx_queue(hw, baseq + i, on);
 589                                 if (ret != I40E_SUCCESS)
 590                                         return ret;
 591                         }
 592         }
 593
 594         /* Enable/Disable TX */
 595         for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
 596                 if (qsel->tx_queues & (1 << i)) {
 597                         ret = i40e_switch_tx_queue(hw, baseq + i, on);
 598                         if (ret != I40E_SUCCESS)
 599                                 return ret;
 600                 }
 601
 602         /* disable RX last if it's disable */
 603         if (!on) {
 604                 /* disable RX */
 605                 for (i = 0; i < I40E_MAX_QP_NUM_PER_VF; i++)
 606                         if (qsel->rx_queues & (1 << i)) {
 607                                 ret = i40e_switch_rx_queue(hw, baseq + i, on);
 608                                 if (ret != I40E_SUCCESS)
 609                                         return ret;
 610                         }
 611         }
 612
 613         return ret;
 614 }
 615
 616 static int
 617 i40e_pf_host_process_cmd_enable_queues(struct i40e_pf_vf *vf,
 618                                        uint8_t *msg,
 619                                        uint16_t msglen)
 620 {
 621         int ret = I40E_SUCCESS;
 622         struct i40e_virtchnl_queue_select *q_sel =
 623                 (struct i40e_virtchnl_queue_select *)msg;
 624
 625         if (msg == NULL || msglen != sizeof(*q_sel)) {
 626                 ret = I40E_ERR_PARAM;
 627                 goto send_msg;
 628         }
 629         ret = i40e_pf_host_switch_queues(vf, q_sel, true);
 630
 631 send_msg:
 632         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ENABLE_QUEUES,
 633                                                         ret, NULL, 0);
 634
 635         return ret;
 636 }
 637
 638 static int
 639 i40e_pf_host_process_cmd_disable_queues(struct i40e_pf_vf *vf,
 640                                         uint8_t *msg,
 641                                         uint16_t msglen)
 642 {
 643         int ret = I40E_SUCCESS;
 644         struct i40e_virtchnl_queue_select *q_sel =
 645                 (struct i40e_virtchnl_queue_select *)msg;
 646
 647         if (msg == NULL || msglen != sizeof(*q_sel)) {
 648                 ret = I40E_ERR_PARAM;
 649                 goto send_msg;
 650         }
 651         ret = i40e_pf_host_switch_queues(vf, q_sel, false);
 652
 653 send_msg:
 654         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DISABLE_QUEUES,
 655                                                         ret, NULL, 0);
 656
 657         return ret;
 658 }
 659
 660
 661 static int
 662 i40e_pf_host_process_cmd_add_ether_address(struct i40e_pf_vf *vf,
 663                                            uint8_t *msg,
 664                                            uint16_t msglen)
 665 {
 666         int ret = I40E_SUCCESS;
 667         struct i40e_virtchnl_ether_addr_list *addr_list =
 668                         (struct i40e_virtchnl_ether_addr_list *)msg;
 669         struct i40e_mac_filter_info filter;
 670         int i;
 671         struct ether_addr *mac;
 672
 673         memset(&filter, 0 , sizeof(struct i40e_mac_filter_info));
 674
 675         if (msg == NULL || msglen <= sizeof(*addr_list)) {
 676                 PMD_DRV_LOG(ERR, "add_ether_address argument too short");
 677                 ret = I40E_ERR_PARAM;
 678                 goto send_msg;
 679         }
 680
 681         for (i = 0; i < addr_list->num_elements; i++) {
 682                 mac = (struct ether_addr *)(addr_list->list[i].addr);
 683                 (void)rte_memcpy(&filter.mac_addr, mac, ETHER_ADDR_LEN);
 684                 filter.filter_type = RTE_MACVLAN_PERFECT_MATCH;
 685                 if(!is_valid_assigned_ether_addr(mac) ||
 686                         i40e_vsi_add_mac(vf->vsi, &filter)) {
 687                         ret = I40E_ERR_INVALID_MAC_ADDR;
 688                         goto send_msg;
 689                 }
 690         }
 691
 692 send_msg:
 693         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS,
 694                                                         ret, NULL, 0);
 695
 696         return ret;
 697 }
 698
 699 static int
 700 i40e_pf_host_process_cmd_del_ether_address(struct i40e_pf_vf *vf,
 701                                            uint8_t *msg,
 702                                            uint16_t msglen)
 703 {
 704         int ret = I40E_SUCCESS;
 705         struct i40e_virtchnl_ether_addr_list *addr_list =
 706                 (struct i40e_virtchnl_ether_addr_list *)msg;
 707         int i;
 708         struct ether_addr *mac;
 709
 710         if (msg == NULL || msglen <= sizeof(*addr_list)) {
 711                 PMD_DRV_LOG(ERR, "delete_ether_address argument too short");
 712                 ret = I40E_ERR_PARAM;
 713                 goto send_msg;
 714         }
 715
 716         for (i = 0; i < addr_list->num_elements; i++) {
 717                 mac = (struct ether_addr *)(addr_list->list[i].addr);
 718                 if(!is_valid_assigned_ether_addr(mac) ||
 719                         i40e_vsi_delete_mac(vf->vsi, mac)) {
 720                         ret = I40E_ERR_INVALID_MAC_ADDR;
 721                         goto send_msg;
 722                 }
 723         }
 724
 725 send_msg:
 726         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS,
 727                                                         ret, NULL, 0);
 728
 729         return ret;
 730 }
 731
 732 static int
 733 i40e_pf_host_process_cmd_add_vlan(struct i40e_pf_vf *vf,
 734                                 uint8_t *msg, uint16_t msglen)
 735 {
 736         int ret = I40E_SUCCESS;
 737         struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
 738                 (struct i40e_virtchnl_vlan_filter_list *)msg;
 739         int i;
 740         uint16_t *vid;
 741
 742         if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
 743                 PMD_DRV_LOG(ERR, "add_vlan argument too short");
 744                 ret = I40E_ERR_PARAM;
 745                 goto send_msg;
 746         }
 747
 748         vid = vlan_filter_list->vlan_id;
 749
 750         for (i = 0; i < vlan_filter_list->num_elements; i++) {
 751                 ret = i40e_vsi_add_vlan(vf->vsi, vid[i]);
 752                 if(ret != I40E_SUCCESS)
 753                         goto send_msg;
 754         }
 755
 756 send_msg:
 757         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_ADD_VLAN,
 758                                                 ret, NULL, 0);
 759
 760         return ret;
 761 }
 762
 763 static int
 764 i40e_pf_host_process_cmd_del_vlan(struct i40e_pf_vf *vf,
 765                                   uint8_t *msg,
 766                                   uint16_t msglen)
 767 {
 768         int ret = I40E_SUCCESS;
 769         struct i40e_virtchnl_vlan_filter_list *vlan_filter_list =
 770                         (struct i40e_virtchnl_vlan_filter_list *)msg;
 771         int i;
 772         uint16_t *vid;
 773
 774         if (msg == NULL || msglen <= sizeof(*vlan_filter_list)) {
 775                 PMD_DRV_LOG(ERR, "delete_vlan argument too short");
 776                 ret = I40E_ERR_PARAM;
 777                 goto send_msg;
 778         }
 779
 780         vid = vlan_filter_list->vlan_id;
 781         for (i = 0; i < vlan_filter_list->num_elements; i++) {
 782                 ret = i40e_vsi_delete_vlan(vf->vsi, vid[i]);
 783                 if(ret != I40E_SUCCESS)
 784                         goto send_msg;
 785         }
 786
 787 send_msg:
 788         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_DEL_VLAN,
 789                                                 ret, NULL, 0);
 790
 791         return ret;
 792 }
 793
 794 static int
 795 i40e_pf_host_process_cmd_config_promisc_mode(
 796                                         struct i40e_pf_vf *vf,
 797                                         uint8_t *msg,
 798                                         uint16_t msglen)
 799 {
 800         int ret = I40E_SUCCESS;
 801         struct i40e_virtchnl_promisc_info *promisc =
 802                                 (struct i40e_virtchnl_promisc_info *)msg;
 803         struct i40e_hw *hw = I40E_PF_TO_HW(vf->pf);
 804         bool unicast = FALSE, multicast = FALSE;
 805
 806         if (msg == NULL || msglen != sizeof(*promisc)) {
 807                 ret = I40E_ERR_PARAM;
 808                 goto send_msg;
 809         }
 810
 811         if (promisc->flags & I40E_FLAG_VF_UNICAST_PROMISC)
 812                 unicast = TRUE;
 813         ret = i40e_aq_set_vsi_unicast_promiscuous(hw,
 814                         vf->vsi->seid, unicast, NULL, true);
 815         if (ret != I40E_SUCCESS)
 816                 goto send_msg;
 817
 818         if (promisc->flags & I40E_FLAG_VF_MULTICAST_PROMISC)
 819                 multicast = TRUE;
 820         ret = i40e_aq_set_vsi_multicast_promiscuous(hw, vf->vsi->seid,
 821                                                 multicast, NULL);
 822
 823 send_msg:
 824         i40e_pf_host_send_msg_to_vf(vf,
 825                 I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE, ret, NULL, 0);
 826
 827         return ret;
 828 }
 829
 830 static int
 831 i40e_pf_host_process_cmd_get_stats(struct i40e_pf_vf *vf)
 832 {
 833         i40e_update_vsi_stats(vf->vsi);
 834
 835         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_STATS,
 836                 I40E_SUCCESS, (uint8_t *)&vf->vsi->eth_stats,
 837                                 sizeof(vf->vsi->eth_stats));
 838
 839         return I40E_SUCCESS;
 840 }
 841
 842 static void
 843 i40e_pf_host_process_cmd_get_link_status(struct i40e_pf_vf *vf)
 844 {
 845         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(vf->pf->main_vsi);
 846
 847         /* Update link status first to acquire latest link change */
 848         i40e_dev_link_update(dev, 1);
 849         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_GET_LINK_STAT,
 850                 I40E_SUCCESS, (uint8_t *)&dev->data->dev_link,
 851                                 sizeof(struct rte_eth_link));
 852 }
 853
 854 static int
 855 i40e_pf_host_process_cmd_cfg_vlan_offload(
 856                                         struct i40e_pf_vf *vf,
 857                                         uint8_t *msg,
 858                                         uint16_t msglen)
 859 {
 860         int ret = I40E_SUCCESS;
 861         struct i40e_virtchnl_vlan_offload_info *offload =
 862                         (struct i40e_virtchnl_vlan_offload_info *)msg;
 863
 864         if (msg == NULL || msglen != sizeof(*offload)) {
 865                 ret = I40E_ERR_PARAM;
 866                 goto send_msg;
 867         }
 868
 869         ret = i40e_vsi_config_vlan_stripping(vf->vsi,
 870                                                 !!offload->enable_vlan_strip);
 871         if (ret != 0)
 872                 PMD_DRV_LOG(ERR, "Failed to configure vlan stripping");
 873
 874 send_msg:
 875         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD,
 876                                         ret, NULL, 0);
 877
 878         return ret;
 879 }
 880
 881 static int
 882 i40e_pf_host_process_cmd_cfg_pvid(struct i40e_pf_vf *vf,
 883                                         uint8_t *msg,
 884                                         uint16_t msglen)
 885 {
 886         int ret = I40E_SUCCESS;
 887         struct i40e_virtchnl_pvid_info  *tpid_info =
 888                         (struct i40e_virtchnl_pvid_info *)msg;
 889
 890         if (msg == NULL || msglen != sizeof(*tpid_info)) {
 891                 ret = I40E_ERR_PARAM;
 892                 goto send_msg;
 893         }
 894
 895         ret = i40e_vsi_vlan_pvid_set(vf->vsi, &tpid_info->info);
 896
 897 send_msg:
 898         i40e_pf_host_send_msg_to_vf(vf, I40E_VIRTCHNL_OP_CFG_VLAN_PVID,
 899                                         ret, NULL, 0);
 900
 901         return ret;
 902 }
 903
 904 void
 905 i40e_pf_host_handle_vf_msg(struct rte_eth_dev *dev,
 906                            uint16_t abs_vf_id, uint32_t opcode,
 907                            __rte_unused uint32_t retval,
 908                            uint8_t *msg,
 909                            uint16_t msglen)
 910 {
 911         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
 912         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 913         struct i40e_pf_vf *vf;
 914         /* AdminQ will pass absolute VF id, transfer to internal vf id */
 915         uint16_t vf_id = abs_vf_id - hw->func_caps.vf_base_id;
 916
 917         if (vf_id > pf->vf_num - 1 || !pf->vfs) {
 918                 PMD_DRV_LOG(ERR, "invalid argument");
 919                 return;
 920         }
 921
 922         vf = &pf->vfs[vf_id];
 923         if (!vf->vsi) {
 924                 PMD_DRV_LOG(ERR, "NO VSI associated with VF found");
 925                 i40e_pf_host_send_msg_to_vf(vf, opcode,
 926                         I40E_ERR_NO_AVAILABLE_VSI, NULL, 0);
 927                 return;
 928         }
 929
 930         switch (opcode) {
 931         case I40E_VIRTCHNL_OP_VERSION :
 932                 PMD_DRV_LOG(INFO, "OP_VERSION received");
 933                 i40e_pf_host_process_cmd_version(vf);
 934                 break;
 935         case I40E_VIRTCHNL_OP_RESET_VF :
 936                 PMD_DRV_LOG(INFO, "OP_RESET_VF received");
 937                 i40e_pf_host_process_cmd_reset_vf(vf);
 938                 break;
 939         case I40E_VIRTCHNL_OP_GET_VF_RESOURCES:
 940                 PMD_DRV_LOG(INFO, "OP_GET_VF_RESOURCES received");
 941                 i40e_pf_host_process_cmd_get_vf_resource(vf);
 942                 break;
 943         case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES:
 944                 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES received");
 945                 i40e_pf_host_process_cmd_config_vsi_queues(vf, msg, msglen);
 946                 break;
 947         case I40E_VIRTCHNL_OP_CONFIG_VSI_QUEUES_EXT:
 948                 PMD_DRV_LOG(INFO, "OP_CONFIG_VSI_QUEUES_EXT received");
 949                 i40e_pf_host_process_cmd_config_vsi_queues_ext(vf, msg,
 950                                                                 msglen);
 951                 break;
 952         case I40E_VIRTCHNL_OP_CONFIG_IRQ_MAP:
 953                 PMD_DRV_LOG(INFO, "OP_CONFIG_IRQ_MAP received");
 954                 i40e_pf_host_process_cmd_config_irq_map(vf, msg, msglen);
 955                 break;
 956         case I40E_VIRTCHNL_OP_ENABLE_QUEUES:
 957                 PMD_DRV_LOG(INFO, "OP_ENABLE_QUEUES received");
 958                 i40e_pf_host_process_cmd_enable_queues(vf, msg, msglen);
 959                 break;
 960         case I40E_VIRTCHNL_OP_DISABLE_QUEUES:
 961                 PMD_DRV_LOG(INFO, "OP_DISABLE_QUEUE received");
 962                 i40e_pf_host_process_cmd_disable_queues(vf, msg, msglen);
 963                 break;
 964         case I40E_VIRTCHNL_OP_ADD_ETHER_ADDRESS:
 965                 PMD_DRV_LOG(INFO, "OP_ADD_ETHER_ADDRESS received");
 966                 i40e_pf_host_process_cmd_add_ether_address(vf, msg, msglen);
 967                 break;
 968         case I40E_VIRTCHNL_OP_DEL_ETHER_ADDRESS:
 969                 PMD_DRV_LOG(INFO, "OP_DEL_ETHER_ADDRESS received");
 970                 i40e_pf_host_process_cmd_del_ether_address(vf, msg, msglen);
 971                 break;
 972         case I40E_VIRTCHNL_OP_ADD_VLAN:
 973                 PMD_DRV_LOG(INFO, "OP_ADD_VLAN received");
 974                 i40e_pf_host_process_cmd_add_vlan(vf, msg, msglen);
 975                 break;
 976         case I40E_VIRTCHNL_OP_DEL_VLAN:
 977                 PMD_DRV_LOG(INFO, "OP_DEL_VLAN received");
 978                 i40e_pf_host_process_cmd_del_vlan(vf, msg, msglen);
 979                 break;
 980         case I40E_VIRTCHNL_OP_CONFIG_PROMISCUOUS_MODE:
 981                 PMD_DRV_LOG(INFO, "OP_CONFIG_PROMISCUOUS_MODE received");
 982                 i40e_pf_host_process_cmd_config_promisc_mode(vf, msg, msglen);
 983                 break;
 984         case I40E_VIRTCHNL_OP_GET_STATS:
 985                 PMD_DRV_LOG(INFO, "OP_GET_STATS received");
 986                 i40e_pf_host_process_cmd_get_stats(vf);
 987                 break;
 988         case I40E_VIRTCHNL_OP_GET_LINK_STAT:
 989                 PMD_DRV_LOG(INFO, "OP_GET_LINK_STAT received");
 990                 i40e_pf_host_process_cmd_get_link_status(vf);
 991                 break;
 992         case I40E_VIRTCHNL_OP_CFG_VLAN_OFFLOAD:
 993                 PMD_DRV_LOG(INFO, "OP_CFG_VLAN_OFFLOAD received");
 994                 i40e_pf_host_process_cmd_cfg_vlan_offload(vf, msg, msglen);
 995                 break;
 996         case I40E_VIRTCHNL_OP_CFG_VLAN_PVID:
 997                 PMD_DRV_LOG(INFO, "OP_CFG_VLAN_PVID received");
 998                 i40e_pf_host_process_cmd_cfg_pvid(vf, msg, msglen);
 999                 break;
1000         /* Don't add command supported below, which will
1001          * return an error code.
1002          */
1003         default:
1004                 PMD_DRV_LOG(ERR, "%u received, not supported", opcode);
1005                 i40e_pf_host_send_msg_to_vf(vf, opcode, I40E_ERR_PARAM,
1006                                                                 NULL, 0);
1007                 break;
1008         }
1009 }
1010
1011 int
1012 i40e_pf_host_init(struct rte_eth_dev *dev)
1013 {
1014         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1015         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1016         int ret, i;
1017         uint32_t val;
1018
1019         PMD_INIT_FUNC_TRACE();
1020
1021         /**
1022          * return if SRIOV not enabled, VF number not configured or
1023          * no queue assigned.
1024          */
1025         if(!hw->func_caps.sr_iov_1_1 || pf->vf_num == 0 || pf->vf_nb_qps == 0)
1026                 return I40E_SUCCESS;
1027
1028         /* Allocate memory to store VF structure */
1029         pf->vfs = rte_zmalloc("i40e_pf_vf",sizeof(*pf->vfs) * pf->vf_num, 0);
1030         if(pf->vfs == NULL)
1031                 return -ENOMEM;
1032
1033         /* Disable irq0 for VFR event */
1034         i40e_pf_disable_irq0(hw);
1035
1036         /* Disable VF link status interrupt */
1037         val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1038         val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1039         I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1040         I40E_WRITE_FLUSH(hw);
1041
1042         for (i = 0; i < pf->vf_num; i++) {
1043                 pf->vfs[i].pf = pf;
1044                 pf->vfs[i].state = I40E_VF_INACTIVE;
1045                 pf->vfs[i].vf_idx = i;
1046                 ret = i40e_pf_host_vf_reset(&pf->vfs[i], 0);
1047                 if (ret != I40E_SUCCESS)
1048                         goto fail;
1049                 eth_random_addr(pf->vfs[i].mac_addr.addr_bytes);
1050         }
1051
1052         /* restore irq0 */
1053         i40e_pf_enable_irq0(hw);
1054
1055         return I40E_SUCCESS;
1056
1057 fail:
1058         rte_free(pf->vfs);
1059         i40e_pf_enable_irq0(hw);
1060
1061         return ret;
1062 }
1063
1064 int
1065 i40e_pf_host_uninit(struct rte_eth_dev *dev)
1066 {
1067         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1068         struct i40e_hw *hw = I40E_PF_TO_HW(pf);
1069         uint32_t val;
1070
1071         PMD_INIT_FUNC_TRACE();
1072
1073         /**
1074          * return if SRIOV not enabled, VF number not configured or
1075          * no queue assigned.
1076          */
1077         if ((!hw->func_caps.sr_iov_1_1) ||
1078                 (pf->vf_num == 0) ||
1079                 (pf->vf_nb_qps == 0))
1080                 return I40E_SUCCESS;
1081
1082         /* free memory to store VF structure */
1083         rte_free(pf->vfs);
1084         pf->vfs = NULL;
1085
1086         /* Disable irq0 for VFR event */
1087         i40e_pf_disable_irq0(hw);
1088
1089         /* Disable VF link status interrupt */
1090         val = I40E_READ_REG(hw, I40E_PFGEN_PORTMDIO_NUM);
1091         val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
1092         I40E_WRITE_REG(hw, I40E_PFGEN_PORTMDIO_NUM, val);
1093         I40E_WRITE_FLUSH(hw);
1094
1095         return I40E_SUCCESS;
1096 }