drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define DEFAULT_TX_RS_THRESH   32
  61 #define DEFAULT_TX_FREE_THRESH 32
  62 #define I40E_MAX_PKT_TYPE      256
  63
  64 #define I40E_TX_MAX_BURST  32
  65
  66 #define I40E_DMA_MEM_ALIGN 4096
  67
  68 /* Base address of the HW descriptor ring should be 128B aligned. */
  69 #define I40E_RING_BASE_ALIGN    128
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  82         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  83
  84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  85         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  86
  87 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  88                                       struct rte_mbuf **tx_pkts,
  89                                       uint16_t nb_pkts);
  90
  91 static inline void
  92 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  93 {
  94         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  95                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  96                 mb->ol_flags |= PKT_RX_VLAN_PKT;
  97                 mb->vlan_tci =
  98                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  99                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 100                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 101         } else {
 102                 mb->vlan_tci = 0;
 103         }
 104 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 105         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 106                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 107                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 108                 mb->vlan_tci_outer = mb->vlan_tci;
 109                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 110                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 111                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 112                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 113         } else {
 114                 mb->vlan_tci_outer = 0;
 115         }
 116 #endif
 117         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 118                    mb->vlan_tci, mb->vlan_tci_outer);
 119 }
 120
 121 /* Translate the rx descriptor status to pkt flags */
 122 static inline uint64_t
 123 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 124 {
 125         uint64_t flags;
 126
 127         /* Check if RSS_HASH */
 128         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 129                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 130                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 131
 132         /* Check if FDIR Match */
 133         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 134                                                         PKT_RX_FDIR : 0);
 135
 136         return flags;
 137 }
 138
 139 static inline uint64_t
 140 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 141 {
 142         uint64_t flags = 0;
 143         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 144
 145 #define I40E_RX_ERR_BITS 0x3f
 146         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 147                 return flags;
 148         /* If RXE bit set, all other status bits are meaningless */
 149         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 150                 flags |= PKT_RX_MAC_ERR;
 151                 return flags;
 152         }
 153
 154         /* If RECIPE bit set, all other status indications should be ignored */
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 156                 flags |= PKT_RX_RECIP_ERR;
 157                 return flags;
 158         }
 159         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 160                 flags |= PKT_RX_HBUF_OVERFLOW;
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 162                 flags |= PKT_RX_IP_CKSUM_BAD;
 163         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 164                 flags |= PKT_RX_L4_CKSUM_BAD;
 165         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 166                 flags |= PKT_RX_EIP_CKSUM_BAD;
 167         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 168                 flags |= PKT_RX_OVERSIZE;
 169
 170         return flags;
 171 }
 172
 173 /* Function to check and set the ieee1588 timesync index and get the
 174  * appropriate flags.
 175  */
 176 #ifdef RTE_LIBRTE_IEEE1588
 177 static inline uint64_t
 178 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 179 {
 180         uint64_t pkt_flags = 0;
 181         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 182                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 183                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 184
 185         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 186                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 187                 pkt_flags = PKT_RX_IEEE1588_PTP;
 188         if (tsyn & 0x04) {
 189                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 190                 mb->timesync = tsyn & 0x03;
 191         }
 192
 193         return pkt_flags;
 194 }
 195 #endif
 196
 197 /* For each value it means, datasheet of hardware can tell more details */
 198 static inline uint32_t
 199 i40e_rxd_pkt_type_mapping(uint8_t ptype)
 200 {
 201         static const uint32_t ptype_table[UINT8_MAX] __rte_cache_aligned = {
 202                 /* L2 types */
 203                 /* [0] reserved */
 204                 [1] = RTE_PTYPE_L2_ETHER,
 205                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
 206                 /* [3] - [5] reserved */
 207                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
 208                 /* [7] - [10] reserved */
 209                 [11] = RTE_PTYPE_L2_ETHER_ARP,
 210                 /* [12] - [21] reserved */
 211
 212                 /* Non tunneled IPv4 */
 213                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 214                         RTE_PTYPE_L4_FRAG,
 215                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 216                         RTE_PTYPE_L4_NONFRAG,
 217                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 218                         RTE_PTYPE_L4_UDP,
 219                 /* [25] reserved */
 220                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 221                         RTE_PTYPE_L4_TCP,
 222                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 223                         RTE_PTYPE_L4_SCTP,
 224                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 225                         RTE_PTYPE_L4_ICMP,
 226
 227                 /* IPv4 --> IPv4 */
 228                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 229                         RTE_PTYPE_TUNNEL_IP |
 230                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 231                         RTE_PTYPE_INNER_L4_FRAG,
 232                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 233                         RTE_PTYPE_TUNNEL_IP |
 234                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 235                         RTE_PTYPE_INNER_L4_NONFRAG,
 236                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 237                         RTE_PTYPE_TUNNEL_IP |
 238                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 239                         RTE_PTYPE_INNER_L4_UDP,
 240                 /* [32] reserved */
 241                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 242                         RTE_PTYPE_TUNNEL_IP |
 243                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 244                         RTE_PTYPE_INNER_L4_TCP,
 245                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 246                         RTE_PTYPE_TUNNEL_IP |
 247                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 248                         RTE_PTYPE_INNER_L4_SCTP,
 249                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 250                         RTE_PTYPE_TUNNEL_IP |
 251                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 252                         RTE_PTYPE_INNER_L4_ICMP,
 253
 254                 /* IPv4 --> IPv6 */
 255                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 256                         RTE_PTYPE_TUNNEL_IP |
 257                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 258                         RTE_PTYPE_INNER_L4_FRAG,
 259                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 260                         RTE_PTYPE_TUNNEL_IP |
 261                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 262                         RTE_PTYPE_INNER_L4_NONFRAG,
 263                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 264                         RTE_PTYPE_TUNNEL_IP |
 265                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 266                         RTE_PTYPE_INNER_L4_UDP,
 267                 /* [39] reserved */
 268                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 269                         RTE_PTYPE_TUNNEL_IP |
 270                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 271                         RTE_PTYPE_INNER_L4_TCP,
 272                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 273                         RTE_PTYPE_TUNNEL_IP |
 274                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 275                         RTE_PTYPE_INNER_L4_SCTP,
 276                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 277                         RTE_PTYPE_TUNNEL_IP |
 278                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 279                         RTE_PTYPE_INNER_L4_ICMP,
 280
 281                 /* IPv4 --> GRE/Teredo/VXLAN */
 282                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 283                         RTE_PTYPE_TUNNEL_GRENAT,
 284
 285                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
 286                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 287                         RTE_PTYPE_TUNNEL_GRENAT |
 288                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 289                         RTE_PTYPE_INNER_L4_FRAG,
 290                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 291                         RTE_PTYPE_TUNNEL_GRENAT |
 292                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 293                         RTE_PTYPE_INNER_L4_NONFRAG,
 294                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 295                         RTE_PTYPE_TUNNEL_GRENAT |
 296                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 297                         RTE_PTYPE_INNER_L4_UDP,
 298                 /* [47] reserved */
 299                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 300                         RTE_PTYPE_TUNNEL_GRENAT |
 301                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 302                         RTE_PTYPE_INNER_L4_TCP,
 303                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 304                         RTE_PTYPE_TUNNEL_GRENAT |
 305                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 306                         RTE_PTYPE_INNER_L4_SCTP,
 307                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 308                         RTE_PTYPE_TUNNEL_GRENAT |
 309                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 310                         RTE_PTYPE_INNER_L4_ICMP,
 311
 312                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
 313                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 314                         RTE_PTYPE_TUNNEL_GRENAT |
 315                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 316                         RTE_PTYPE_INNER_L4_FRAG,
 317                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 318                         RTE_PTYPE_TUNNEL_GRENAT |
 319                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 320                         RTE_PTYPE_INNER_L4_NONFRAG,
 321                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 322                         RTE_PTYPE_TUNNEL_GRENAT |
 323                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 324                         RTE_PTYPE_INNER_L4_UDP,
 325                 /* [54] reserved */
 326                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 327                         RTE_PTYPE_TUNNEL_GRENAT |
 328                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 329                         RTE_PTYPE_INNER_L4_TCP,
 330                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 331                         RTE_PTYPE_TUNNEL_GRENAT |
 332                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 333                         RTE_PTYPE_INNER_L4_SCTP,
 334                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 335                         RTE_PTYPE_TUNNEL_GRENAT |
 336                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 337                         RTE_PTYPE_INNER_L4_ICMP,
 338
 339                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
 340                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 341                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 342
 343                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 344                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 345                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 346                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 347                         RTE_PTYPE_INNER_L4_FRAG,
 348                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 349                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 350                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 351                         RTE_PTYPE_INNER_L4_NONFRAG,
 352                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 353                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 354                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 355                         RTE_PTYPE_INNER_L4_UDP,
 356                 /* [62] reserved */
 357                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 358                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 359                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 360                         RTE_PTYPE_INNER_L4_TCP,
 361                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 362                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 363                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 364                         RTE_PTYPE_INNER_L4_SCTP,
 365                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 366                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 367                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 368                         RTE_PTYPE_INNER_L4_ICMP,
 369
 370                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 371                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 372                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 373                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 374                         RTE_PTYPE_INNER_L4_FRAG,
 375                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 376                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 377                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 378                         RTE_PTYPE_INNER_L4_NONFRAG,
 379                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 380                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 381                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 382                         RTE_PTYPE_INNER_L4_UDP,
 383                 /* [69] reserved */
 384                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 385                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 386                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 387                         RTE_PTYPE_INNER_L4_TCP,
 388                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 389                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 390                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 391                         RTE_PTYPE_INNER_L4_SCTP,
 392                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 393                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 394                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 395                         RTE_PTYPE_INNER_L4_ICMP,
 396
 397                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 398                 [73] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 399                         RTE_PTYPE_TUNNEL_GRENAT |
 400                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 401
 402                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 403                 [74] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 404                         RTE_PTYPE_TUNNEL_GRENAT |
 405                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 406                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 407                         RTE_PTYPE_INNER_L4_FRAG,
 408                 [75] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 409                         RTE_PTYPE_TUNNEL_GRENAT |
 410                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 411                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 412                         RTE_PTYPE_INNER_L4_NONFRAG,
 413                 [76] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 414                         RTE_PTYPE_TUNNEL_GRENAT |
 415                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 416                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 417                         RTE_PTYPE_INNER_L4_UDP,
 418                 /* [77] reserved */
 419                 [78] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 420                         RTE_PTYPE_TUNNEL_GRENAT |
 421                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 422                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 423                         RTE_PTYPE_INNER_L4_TCP,
 424                 [79] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 425                         RTE_PTYPE_TUNNEL_GRENAT |
 426                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 427                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 428                         RTE_PTYPE_INNER_L4_SCTP,
 429                 [80] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 430                         RTE_PTYPE_TUNNEL_GRENAT |
 431                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 432                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 433                         RTE_PTYPE_INNER_L4_ICMP,
 434
 435                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 436                 [81] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 437                         RTE_PTYPE_TUNNEL_GRENAT |
 438                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 439                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 440                         RTE_PTYPE_INNER_L4_FRAG,
 441                 [82] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 442                         RTE_PTYPE_TUNNEL_GRENAT |
 443                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 444                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 445                         RTE_PTYPE_INNER_L4_NONFRAG,
 446                 [83] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 447                         RTE_PTYPE_TUNNEL_GRENAT |
 448                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 449                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 450                         RTE_PTYPE_INNER_L4_UDP,
 451                 /* [84] reserved */
 452                 [85] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 453                         RTE_PTYPE_TUNNEL_GRENAT |
 454                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 455                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 456                         RTE_PTYPE_INNER_L4_TCP,
 457                 [86] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 458                         RTE_PTYPE_TUNNEL_GRENAT |
 459                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 460                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 461                         RTE_PTYPE_INNER_L4_SCTP,
 462                 [87] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 463                         RTE_PTYPE_TUNNEL_GRENAT |
 464                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 465                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 466                         RTE_PTYPE_INNER_L4_ICMP,
 467
 468                 /* Non tunneled IPv6 */
 469                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 470                         RTE_PTYPE_L4_FRAG,
 471                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 472                         RTE_PTYPE_L4_NONFRAG,
 473                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 474                         RTE_PTYPE_L4_UDP,
 475                 /* [91] reserved */
 476                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 477                         RTE_PTYPE_L4_TCP,
 478                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 479                         RTE_PTYPE_L4_SCTP,
 480                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 481                         RTE_PTYPE_L4_ICMP,
 482
 483                 /* IPv6 --> IPv4 */
 484                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 485                         RTE_PTYPE_TUNNEL_IP |
 486                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 487                         RTE_PTYPE_INNER_L4_FRAG,
 488                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 489                         RTE_PTYPE_TUNNEL_IP |
 490                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 491                         RTE_PTYPE_INNER_L4_NONFRAG,
 492                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 493                         RTE_PTYPE_TUNNEL_IP |
 494                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 495                         RTE_PTYPE_INNER_L4_UDP,
 496                 /* [98] reserved */
 497                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 498                         RTE_PTYPE_TUNNEL_IP |
 499                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 500                         RTE_PTYPE_INNER_L4_TCP,
 501                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 502                         RTE_PTYPE_TUNNEL_IP |
 503                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 504                         RTE_PTYPE_INNER_L4_SCTP,
 505                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 506                         RTE_PTYPE_TUNNEL_IP |
 507                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 508                         RTE_PTYPE_INNER_L4_ICMP,
 509
 510                 /* IPv6 --> IPv6 */
 511                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 512                         RTE_PTYPE_TUNNEL_IP |
 513                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 514                         RTE_PTYPE_INNER_L4_FRAG,
 515                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 516                         RTE_PTYPE_TUNNEL_IP |
 517                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 518                         RTE_PTYPE_INNER_L4_NONFRAG,
 519                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 520                         RTE_PTYPE_TUNNEL_IP |
 521                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 522                         RTE_PTYPE_INNER_L4_UDP,
 523                 /* [105] reserved */
 524                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 525                         RTE_PTYPE_TUNNEL_IP |
 526                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 527                         RTE_PTYPE_INNER_L4_TCP,
 528                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 529                         RTE_PTYPE_TUNNEL_IP |
 530                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 531                         RTE_PTYPE_INNER_L4_SCTP,
 532                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 533                         RTE_PTYPE_TUNNEL_IP |
 534                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 535                         RTE_PTYPE_INNER_L4_ICMP,
 536
 537                 /* IPv6 --> GRE/Teredo/VXLAN */
 538                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 539                         RTE_PTYPE_TUNNEL_GRENAT,
 540
 541                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
 542                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 543                         RTE_PTYPE_TUNNEL_GRENAT |
 544                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 545                         RTE_PTYPE_INNER_L4_FRAG,
 546                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 547                         RTE_PTYPE_TUNNEL_GRENAT |
 548                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 549                         RTE_PTYPE_INNER_L4_NONFRAG,
 550                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 551                         RTE_PTYPE_TUNNEL_GRENAT |
 552                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 553                         RTE_PTYPE_INNER_L4_UDP,
 554                 /* [113] reserved */
 555                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 556                         RTE_PTYPE_TUNNEL_GRENAT |
 557                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 558                         RTE_PTYPE_INNER_L4_TCP,
 559                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 560                         RTE_PTYPE_TUNNEL_GRENAT |
 561                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 562                         RTE_PTYPE_INNER_L4_SCTP,
 563                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 564                         RTE_PTYPE_TUNNEL_GRENAT |
 565                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 566                         RTE_PTYPE_INNER_L4_ICMP,
 567
 568                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
 569                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 570                         RTE_PTYPE_TUNNEL_GRENAT |
 571                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 572                         RTE_PTYPE_INNER_L4_FRAG,
 573                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 574                         RTE_PTYPE_TUNNEL_GRENAT |
 575                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 576                         RTE_PTYPE_INNER_L4_NONFRAG,
 577                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 578                         RTE_PTYPE_TUNNEL_GRENAT |
 579                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 580                         RTE_PTYPE_INNER_L4_UDP,
 581                 /* [120] reserved */
 582                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 583                         RTE_PTYPE_TUNNEL_GRENAT |
 584                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 585                         RTE_PTYPE_INNER_L4_TCP,
 586                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 587                         RTE_PTYPE_TUNNEL_GRENAT |
 588                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 589                         RTE_PTYPE_INNER_L4_SCTP,
 590                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 591                         RTE_PTYPE_TUNNEL_GRENAT |
 592                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 593                         RTE_PTYPE_INNER_L4_ICMP,
 594
 595                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
 596                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 597                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
 598
 599                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
 600                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 601                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 602                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 603                         RTE_PTYPE_INNER_L4_FRAG,
 604                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 605                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 606                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 607                         RTE_PTYPE_INNER_L4_NONFRAG,
 608                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 609                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 610                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 611                         RTE_PTYPE_INNER_L4_UDP,
 612                 /* [128] reserved */
 613                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 614                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 615                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 616                         RTE_PTYPE_INNER_L4_TCP,
 617                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 618                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 619                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 620                         RTE_PTYPE_INNER_L4_SCTP,
 621                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 622                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 623                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 624                         RTE_PTYPE_INNER_L4_ICMP,
 625
 626                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
 627                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 628                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 629                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 630                         RTE_PTYPE_INNER_L4_FRAG,
 631                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 632                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 633                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 634                         RTE_PTYPE_INNER_L4_NONFRAG,
 635                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 636                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 637                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 638                         RTE_PTYPE_INNER_L4_UDP,
 639                 /* [135] reserved */
 640                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 641                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 642                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 643                         RTE_PTYPE_INNER_L4_TCP,
 644                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 645                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 646                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 647                         RTE_PTYPE_INNER_L4_SCTP,
 648                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 649                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
 650                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 651                         RTE_PTYPE_INNER_L4_ICMP,
 652
 653                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN */
 654                 [139] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 655                         RTE_PTYPE_TUNNEL_GRENAT |
 656                         RTE_PTYPE_INNER_L2_ETHER_VLAN,
 657
 658                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv4 */
 659                 [140] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 660                         RTE_PTYPE_TUNNEL_GRENAT |
 661                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 662                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 663                         RTE_PTYPE_INNER_L4_FRAG,
 664                 [141] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 665                         RTE_PTYPE_TUNNEL_GRENAT |
 666                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 667                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 668                         RTE_PTYPE_INNER_L4_NONFRAG,
 669                 [142] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 670                         RTE_PTYPE_TUNNEL_GRENAT |
 671                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 672                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 673                         RTE_PTYPE_INNER_L4_UDP,
 674                 /* [143] reserved */
 675                 [144] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 676                         RTE_PTYPE_TUNNEL_GRENAT |
 677                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 678                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 679                         RTE_PTYPE_INNER_L4_TCP,
 680                 [145] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 681                         RTE_PTYPE_TUNNEL_GRENAT |
 682                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 683                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 684                         RTE_PTYPE_INNER_L4_SCTP,
 685                 [146] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 686                         RTE_PTYPE_TUNNEL_GRENAT |
 687                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 688                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
 689                         RTE_PTYPE_INNER_L4_ICMP,
 690
 691                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC/VLAN --> IPv6 */
 692                 [147] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 693                         RTE_PTYPE_TUNNEL_GRENAT |
 694                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 695                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 696                         RTE_PTYPE_INNER_L4_FRAG,
 697                 [148] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 698                         RTE_PTYPE_TUNNEL_GRENAT |
 699                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 700                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 701                         RTE_PTYPE_INNER_L4_NONFRAG,
 702                 [149] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 703                         RTE_PTYPE_TUNNEL_GRENAT |
 704                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 705                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 706                         RTE_PTYPE_INNER_L4_UDP,
 707                 /* [150] reserved */
 708                 [151] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 709                         RTE_PTYPE_TUNNEL_GRENAT |
 710                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 711                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 712                         RTE_PTYPE_INNER_L4_TCP,
 713                 [152] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 714                         RTE_PTYPE_TUNNEL_GRENAT |
 715                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 716                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 717                         RTE_PTYPE_INNER_L4_SCTP,
 718                 [153] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
 719                         RTE_PTYPE_TUNNEL_GRENAT |
 720                         RTE_PTYPE_INNER_L2_ETHER_VLAN |
 721                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
 722                         RTE_PTYPE_INNER_L4_ICMP,
 723
 724                 /* All others reserved */
 725         };
 726
 727         return ptype_table[ptype];
 728 }
 729
 730 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 731 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 732 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 733 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 734 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 735
 736 static inline uint64_t
 737 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 738 {
 739         uint64_t flags = 0;
 740 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 741         uint16_t flexbh, flexbl;
 742
 743         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 744                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 745                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 746         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 747                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 748                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 749
 750
 751         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 752                 mb->hash.fdir.hi =
 753                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 754                 flags |= PKT_RX_FDIR_ID;
 755         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 756                 mb->hash.fdir.hi =
 757                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 758                 flags |= PKT_RX_FDIR_FLX;
 759         }
 760         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 761                 mb->hash.fdir.lo =
 762                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 763                 flags |= PKT_RX_FDIR_FLX;
 764         }
 765 #else
 766         mb->hash.fdir.hi =
 767                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 768         flags |= PKT_RX_FDIR_ID;
 769 #endif
 770         return flags;
 771 }
 772 static inline void
 773 i40e_txd_enable_checksum(uint64_t ol_flags,
 774                         uint32_t *td_cmd,
 775                         uint32_t *td_offset,
 776                         union i40e_tx_offload tx_offload,
 777                         uint32_t *cd_tunneling)
 778 {
 779         /* UDP tunneling packet TX checksum offload */
 780         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 781
 782                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 783                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 784
 785                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 786                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 787                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 788                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 789                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 790                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 791
 792                 /* Now set the ctx descriptor fields */
 793                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 794                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 795                                 (tx_offload.l2_len >> 1) <<
 796                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 797
 798         } else
 799                 *td_offset |= (tx_offload.l2_len >> 1)
 800                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 801
 802         /* Enable L3 checksum offloads */
 803         if (ol_flags & PKT_TX_IP_CKSUM) {
 804                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 805                 *td_offset |= (tx_offload.l3_len >> 2)
 806                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 807         } else if (ol_flags & PKT_TX_IPV4) {
 808                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 809                 *td_offset |= (tx_offload.l3_len >> 2)
 810                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 811         } else if (ol_flags & PKT_TX_IPV6) {
 812                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 813                 *td_offset |= (tx_offload.l3_len >> 2)
 814                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 815         }
 816
 817         if (ol_flags & PKT_TX_TCP_SEG) {
 818                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 819                 *td_offset |= (tx_offload.l4_len >> 2)
 820                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 821                 return;
 822         }
 823
 824         /* Enable L4 checksum offloads */
 825         switch (ol_flags & PKT_TX_L4_MASK) {
 826         case PKT_TX_TCP_CKSUM:
 827                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 828                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 829                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 830                 break;
 831         case PKT_TX_SCTP_CKSUM:
 832                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 833                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 834                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 835                 break;
 836         case PKT_TX_UDP_CKSUM:
 837                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 838                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 839                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 840                 break;
 841         default:
 842                 break;
 843         }
 844 }
 845
 846 static inline struct rte_mbuf *
 847 rte_rxmbuf_alloc(struct rte_mempool *mp)
 848 {
 849         struct rte_mbuf *m;
 850
 851         m = __rte_mbuf_raw_alloc(mp);
 852         __rte_mbuf_sanity_check_raw(m, 0);
 853
 854         return m;
 855 }
 856
 857 /* Construct the tx flags */
 858 static inline uint64_t
 859 i40e_build_ctob(uint32_t td_cmd,
 860                 uint32_t td_offset,
 861                 unsigned int size,
 862                 uint32_t td_tag)
 863 {
 864         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 865                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 866                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 867                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 868                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 869 }
 870
 871 static inline int
 872 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 873 {
 874         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 875         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 876         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 877         uint16_t nb_tx_desc = txq->nb_tx_desc;
 878         uint16_t desc_to_clean_to;
 879         uint16_t nb_tx_to_clean;
 880
 881         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 882         if (desc_to_clean_to >= nb_tx_desc)
 883                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 884
 885         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 886         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 887                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 888                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 889                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 890                         "(port=%d queue=%d)", desc_to_clean_to,
 891                                 txq->port_id, txq->queue_id);
 892                 return -1;
 893         }
 894
 895         if (last_desc_cleaned > desc_to_clean_to)
 896                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 897                                                         desc_to_clean_to);
 898         else
 899                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 900                                         last_desc_cleaned);
 901
 902         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 903
 904         txq->last_desc_cleaned = desc_to_clean_to;
 905         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 906
 907         return 0;
 908 }
 909
 910 static inline int
 911 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 912 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 913 #else
 914 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 915 #endif
 916 {
 917         int ret = 0;
 918
 919 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 920         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 921                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 922                              "rxq->rx_free_thresh=%d, "
 923                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 924                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 925                 ret = -EINVAL;
 926         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 927                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 928                              "rxq->rx_free_thresh=%d, "
 929                              "rxq->nb_rx_desc=%d",
 930                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 931                 ret = -EINVAL;
 932         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 933                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 934                              "rxq->nb_rx_desc=%d, "
 935                              "rxq->rx_free_thresh=%d",
 936                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 937                 ret = -EINVAL;
 938         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 939                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 940                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 941                              "rxq->nb_rx_desc=%d, "
 942                              "I40E_MAX_RING_DESC=%d, "
 943                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 944                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 945                              RTE_PMD_I40E_RX_MAX_BURST);
 946                 ret = -EINVAL;
 947         }
 948 #else
 949         ret = -EINVAL;
 950 #endif
 951
 952         return ret;
 953 }
 954
 955 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 956 #define I40E_LOOK_AHEAD 8
 957 #if (I40E_LOOK_AHEAD != 8)
 958 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 959 #endif
 960 static inline int
 961 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 962 {
 963         volatile union i40e_rx_desc *rxdp;
 964         struct i40e_rx_entry *rxep;
 965         struct rte_mbuf *mb;
 966         uint16_t pkt_len;
 967         uint64_t qword1;
 968         uint32_t rx_status;
 969         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 970         int32_t i, j, nb_rx = 0;
 971         uint64_t pkt_flags;
 972
 973         rxdp = &rxq->rx_ring[rxq->rx_tail];
 974         rxep = &rxq->sw_ring[rxq->rx_tail];
 975
 976         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 977         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 978                                 I40E_RXD_QW1_STATUS_SHIFT;
 979
 980         /* Make sure there is at least 1 packet to receive */
 981         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 982                 return 0;
 983
 984         /**
 985          * Scan LOOK_AHEAD descriptors at a time to determine which
 986          * descriptors reference packets that are ready to be received.
 987          */
 988         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 989                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 990                 /* Read desc statuses backwards to avoid race condition */
 991                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 992                         qword1 = rte_le_to_cpu_64(\
 993                                 rxdp[j].wb.qword1.status_error_len);
 994                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 995                                         I40E_RXD_QW1_STATUS_SHIFT;
 996                 }
 997
 998                 /* Compute how many status bits were set */
 999                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
1000                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
1001
1002                 nb_rx += nb_dd;
1003
1004                 /* Translate descriptor info to mbuf parameters */
1005                 for (j = 0; j < nb_dd; j++) {
1006                         mb = rxep[j].mbuf;
1007                         qword1 = rte_le_to_cpu_64(\
1008                                 rxdp[j].wb.qword1.status_error_len);
1009                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1010                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1011                         mb->data_len = pkt_len;
1012                         mb->pkt_len = pkt_len;
1013                         mb->ol_flags = 0;
1014                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
1015                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1016                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1017                         mb->packet_type =
1018                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1019                                                 I40E_RXD_QW1_PTYPE_MASK) >>
1020                                                 I40E_RXD_QW1_PTYPE_SHIFT));
1021                         if (pkt_flags & PKT_RX_RSS_HASH)
1022                                 mb->hash.rss = rte_le_to_cpu_32(\
1023                                         rxdp[j].wb.qword0.hi_dword.rss);
1024                         if (pkt_flags & PKT_RX_FDIR)
1025                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
1026
1027 #ifdef RTE_LIBRTE_IEEE1588
1028                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
1029 #endif
1030                         mb->ol_flags |= pkt_flags;
1031
1032                 }
1033
1034                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
1035                         rxq->rx_stage[i + j] = rxep[j].mbuf;
1036
1037                 if (nb_dd != I40E_LOOK_AHEAD)
1038                         break;
1039         }
1040
1041         /* Clear software ring entries */
1042         for (i = 0; i < nb_rx; i++)
1043                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
1044
1045         return nb_rx;
1046 }
1047
1048 static inline uint16_t
1049 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
1050                         struct rte_mbuf **rx_pkts,
1051                         uint16_t nb_pkts)
1052 {
1053         uint16_t i;
1054         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1055
1056         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1057
1058         for (i = 0; i < nb_pkts; i++)
1059                 rx_pkts[i] = stage[i];
1060
1061         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1062         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1063
1064         return nb_pkts;
1065 }
1066
1067 static inline int
1068 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
1069 {
1070         volatile union i40e_rx_desc *rxdp;
1071         struct i40e_rx_entry *rxep;
1072         struct rte_mbuf *mb;
1073         uint16_t alloc_idx, i;
1074         uint64_t dma_addr;
1075         int diag;
1076
1077         /* Allocate buffers in bulk */
1078         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1079                                 (rxq->rx_free_thresh - 1));
1080         rxep = &(rxq->sw_ring[alloc_idx]);
1081         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1082                                         rxq->rx_free_thresh);
1083         if (unlikely(diag != 0)) {
1084                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
1085                 return -ENOMEM;
1086         }
1087
1088         rxdp = &rxq->rx_ring[alloc_idx];
1089         for (i = 0; i < rxq->rx_free_thresh; i++) {
1090                 if (likely(i < (rxq->rx_free_thresh - 1)))
1091                         /* Prefetch next mbuf */
1092                         rte_prefetch0(rxep[i + 1].mbuf);
1093
1094                 mb = rxep[i].mbuf;
1095                 rte_mbuf_refcnt_set(mb, 1);
1096                 mb->next = NULL;
1097                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1098                 mb->nb_segs = 1;
1099                 mb->port = rxq->port_id;
1100                 dma_addr = rte_cpu_to_le_64(\
1101                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
1102                 rxdp[i].read.hdr_addr = 0;
1103                 rxdp[i].read.pkt_addr = dma_addr;
1104         }
1105
1106         /* Update rx tail regsiter */
1107         rte_wmb();
1108         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
1109
1110         rxq->rx_free_trigger =
1111                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1112         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1113                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1114
1115         return 0;
1116 }
1117
1118 static inline uint16_t
1119 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1120 {
1121         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
1122         uint16_t nb_rx = 0;
1123
1124         if (!nb_pkts)
1125                 return 0;
1126
1127         if (rxq->rx_nb_avail)
1128                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1129
1130         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
1131         rxq->rx_next_avail = 0;
1132         rxq->rx_nb_avail = nb_rx;
1133         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1134
1135         if (rxq->rx_tail > rxq->rx_free_trigger) {
1136                 if (i40e_rx_alloc_bufs(rxq) != 0) {
1137                         uint16_t i, j;
1138
1139                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
1140                                    "port_id=%u, queue_id=%u",
1141                                    rxq->port_id, rxq->queue_id);
1142                         rxq->rx_nb_avail = 0;
1143                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1144                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1145                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
1146
1147                         return 0;
1148                 }
1149         }
1150
1151         if (rxq->rx_tail >= rxq->nb_rx_desc)
1152                 rxq->rx_tail = 0;
1153
1154         if (rxq->rx_nb_avail)
1155                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1156
1157         return 0;
1158 }
1159
1160 static uint16_t
1161 i40e_recv_pkts_bulk_alloc(void *rx_queue,
1162                           struct rte_mbuf **rx_pkts,
1163                           uint16_t nb_pkts)
1164 {
1165         uint16_t nb_rx = 0, n, count;
1166
1167         if (unlikely(nb_pkts == 0))
1168                 return 0;
1169
1170         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
1171                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1172
1173         while (nb_pkts) {
1174                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
1175                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1176                 nb_rx = (uint16_t)(nb_rx + count);
1177                 nb_pkts = (uint16_t)(nb_pkts - count);
1178                 if (count < n)
1179                         break;
1180         }
1181
1182         return nb_rx;
1183 }
1184 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1185
1186 uint16_t
1187 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1188 {
1189         struct i40e_rx_queue *rxq;
1190         volatile union i40e_rx_desc *rx_ring;
1191         volatile union i40e_rx_desc *rxdp;
1192         union i40e_rx_desc rxd;
1193         struct i40e_rx_entry *sw_ring;
1194         struct i40e_rx_entry *rxe;
1195         struct rte_mbuf *rxm;
1196         struct rte_mbuf *nmb;
1197         uint16_t nb_rx;
1198         uint32_t rx_status;
1199         uint64_t qword1;
1200         uint16_t rx_packet_len;
1201         uint16_t rx_id, nb_hold;
1202         uint64_t dma_addr;
1203         uint64_t pkt_flags;
1204
1205         nb_rx = 0;
1206         nb_hold = 0;
1207         rxq = rx_queue;
1208         rx_id = rxq->rx_tail;
1209         rx_ring = rxq->rx_ring;
1210         sw_ring = rxq->sw_ring;
1211
1212         while (nb_rx < nb_pkts) {
1213                 rxdp = &rx_ring[rx_id];
1214                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1215                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
1216                                 >> I40E_RXD_QW1_STATUS_SHIFT;
1217
1218                 /* Check the DD bit first */
1219                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1220                         break;
1221
1222                 nmb = rte_rxmbuf_alloc(rxq->mp);
1223                 if (unlikely(!nmb))
1224                         break;
1225                 rxd = *rxdp;
1226
1227                 nb_hold++;
1228                 rxe = &sw_ring[rx_id];
1229                 rx_id++;
1230                 if (unlikely(rx_id == rxq->nb_rx_desc))
1231                         rx_id = 0;
1232
1233                 /* Prefetch next mbuf */
1234                 rte_prefetch0(sw_ring[rx_id].mbuf);
1235
1236                 /**
1237                  * When next RX descriptor is on a cache line boundary,
1238                  * prefetch the next 4 RX descriptors and next 8 pointers
1239                  * to mbufs.
1240                  */
1241                 if ((rx_id & 0x3) == 0) {
1242                         rte_prefetch0(&rx_ring[rx_id]);
1243                         rte_prefetch0(&sw_ring[rx_id]);
1244                 }
1245                 rxm = rxe->mbuf;
1246                 rxe->mbuf = nmb;
1247                 dma_addr =
1248                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1249                 rxdp->read.hdr_addr = 0;
1250                 rxdp->read.pkt_addr = dma_addr;
1251
1252                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1253                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1254
1255                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1256                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1257                 rxm->nb_segs = 1;
1258                 rxm->next = NULL;
1259                 rxm->pkt_len = rx_packet_len;
1260                 rxm->data_len = rx_packet_len;
1261                 rxm->port = rxq->port_id;
1262                 rxm->ol_flags = 0;
1263                 i40e_rxd_to_vlan_tci(rxm, &rxd);
1264                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1265                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1266                 rxm->packet_type =
1267                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1268                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1269                 if (pkt_flags & PKT_RX_RSS_HASH)
1270                         rxm->hash.rss =
1271                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1272                 if (pkt_flags & PKT_RX_FDIR)
1273                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1274
1275 #ifdef RTE_LIBRTE_IEEE1588
1276                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
1277 #endif
1278                 rxm->ol_flags |= pkt_flags;
1279
1280                 rx_pkts[nb_rx++] = rxm;
1281         }
1282         rxq->rx_tail = rx_id;
1283
1284         /**
1285          * If the number of free RX descriptors is greater than the RX free
1286          * threshold of the queue, advance the receive tail register of queue.
1287          * Update that register with the value of the last processed RX
1288          * descriptor minus 1.
1289          */
1290         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1291         if (nb_hold > rxq->rx_free_thresh) {
1292                 rx_id = (uint16_t) ((rx_id == 0) ?
1293                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1294                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1295                 nb_hold = 0;
1296         }
1297         rxq->nb_rx_hold = nb_hold;
1298
1299         return nb_rx;
1300 }
1301
1302 uint16_t
1303 i40e_recv_scattered_pkts(void *rx_queue,
1304                          struct rte_mbuf **rx_pkts,
1305                          uint16_t nb_pkts)
1306 {
1307         struct i40e_rx_queue *rxq = rx_queue;
1308         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1309         volatile union i40e_rx_desc *rxdp;
1310         union i40e_rx_desc rxd;
1311         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1312         struct i40e_rx_entry *rxe;
1313         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1314         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1315         struct rte_mbuf *nmb, *rxm;
1316         uint16_t rx_id = rxq->rx_tail;
1317         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1318         uint32_t rx_status;
1319         uint64_t qword1;
1320         uint64_t dma_addr;
1321         uint64_t pkt_flags;
1322
1323         while (nb_rx < nb_pkts) {
1324                 rxdp = &rx_ring[rx_id];
1325                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1326                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1327                                         I40E_RXD_QW1_STATUS_SHIFT;
1328
1329                 /* Check the DD bit */
1330                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1331                         break;
1332
1333                 nmb = rte_rxmbuf_alloc(rxq->mp);
1334                 if (unlikely(!nmb))
1335                         break;
1336                 rxd = *rxdp;
1337                 nb_hold++;
1338                 rxe = &sw_ring[rx_id];
1339                 rx_id++;
1340                 if (rx_id == rxq->nb_rx_desc)
1341                         rx_id = 0;
1342
1343                 /* Prefetch next mbuf */
1344                 rte_prefetch0(sw_ring[rx_id].mbuf);
1345
1346                 /**
1347                  * When next RX descriptor is on a cache line boundary,
1348                  * prefetch the next 4 RX descriptors and next 8 pointers
1349                  * to mbufs.
1350                  */
1351                 if ((rx_id & 0x3) == 0) {
1352                         rte_prefetch0(&rx_ring[rx_id]);
1353                         rte_prefetch0(&sw_ring[rx_id]);
1354                 }
1355
1356                 rxm = rxe->mbuf;
1357                 rxe->mbuf = nmb;
1358                 dma_addr =
1359                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1360
1361                 /* Set data buffer address and data length of the mbuf */
1362                 rxdp->read.hdr_addr = 0;
1363                 rxdp->read.pkt_addr = dma_addr;
1364                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1365                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1366                 rxm->data_len = rx_packet_len;
1367                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1368
1369                 /**
1370                  * If this is the first buffer of the received packet, set the
1371                  * pointer to the first mbuf of the packet and initialize its
1372                  * context. Otherwise, update the total length and the number
1373                  * of segments of the current scattered packet, and update the
1374                  * pointer to the last mbuf of the current packet.
1375                  */
1376                 if (!first_seg) {
1377                         first_seg = rxm;
1378                         first_seg->nb_segs = 1;
1379                         first_seg->pkt_len = rx_packet_len;
1380                 } else {
1381                         first_seg->pkt_len =
1382                                 (uint16_t)(first_seg->pkt_len +
1383                                                 rx_packet_len);
1384                         first_seg->nb_segs++;
1385                         last_seg->next = rxm;
1386                 }
1387
1388                 /**
1389                  * If this is not the last buffer of the received packet,
1390                  * update the pointer to the last mbuf of the current scattered
1391                  * packet and continue to parse the RX ring.
1392                  */
1393                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1394                         last_seg = rxm;
1395                         continue;
1396                 }
1397
1398                 /**
1399                  * This is the last buffer of the received packet. If the CRC
1400                  * is not stripped by the hardware:
1401                  *  - Subtract the CRC length from the total packet length.
1402                  *  - If the last buffer only contains the whole CRC or a part
1403                  *  of it, free the mbuf associated to the last buffer. If part
1404                  *  of the CRC is also contained in the previous mbuf, subtract
1405                  *  the length of that CRC part from the data length of the
1406                  *  previous mbuf.
1407                  */
1408                 rxm->next = NULL;
1409                 if (unlikely(rxq->crc_len > 0)) {
1410                         first_seg->pkt_len -= ETHER_CRC_LEN;
1411                         if (rx_packet_len <= ETHER_CRC_LEN) {
1412                                 rte_pktmbuf_free_seg(rxm);
1413                                 first_seg->nb_segs--;
1414                                 last_seg->data_len =
1415                                         (uint16_t)(last_seg->data_len -
1416                                         (ETHER_CRC_LEN - rx_packet_len));
1417                                 last_seg->next = NULL;
1418                         } else
1419                                 rxm->data_len = (uint16_t)(rx_packet_len -
1420                                                                 ETHER_CRC_LEN);
1421                 }
1422
1423                 first_seg->port = rxq->port_id;
1424                 first_seg->ol_flags = 0;
1425                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1426                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1427                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1428                 first_seg->packet_type =
1429                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
1430                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
1431                 if (pkt_flags & PKT_RX_RSS_HASH)
1432                         rxm->hash.rss =
1433                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1434                 if (pkt_flags & PKT_RX_FDIR)
1435                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1436
1437 #ifdef RTE_LIBRTE_IEEE1588
1438                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
1439 #endif
1440                 first_seg->ol_flags |= pkt_flags;
1441
1442                 /* Prefetch data of first segment, if configured to do so. */
1443                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1444                         first_seg->data_off));
1445                 rx_pkts[nb_rx++] = first_seg;
1446                 first_seg = NULL;
1447         }
1448
1449         /* Record index of the next RX descriptor to probe. */
1450         rxq->rx_tail = rx_id;
1451         rxq->pkt_first_seg = first_seg;
1452         rxq->pkt_last_seg = last_seg;
1453
1454         /**
1455          * If the number of free RX descriptors is greater than the RX free
1456          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1457          * register. Update the RDT with the value of the last processed RX
1458          * descriptor minus 1, to guarantee that the RDT register is never
1459          * equal to the RDH register, which creates a "full" ring situtation
1460          * from the hardware point of view.
1461          */
1462         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1463         if (nb_hold > rxq->rx_free_thresh) {
1464                 rx_id = (uint16_t)(rx_id == 0 ?
1465                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1466                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1467                 nb_hold = 0;
1468         }
1469         rxq->nb_rx_hold = nb_hold;
1470
1471         return nb_rx;
1472 }
1473
1474 /* Check if the context descriptor is needed for TX offloading */
1475 static inline uint16_t
1476 i40e_calc_context_desc(uint64_t flags)
1477 {
1478         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1479                 PKT_TX_TCP_SEG |
1480                 PKT_TX_QINQ_PKT;
1481
1482 #ifdef RTE_LIBRTE_IEEE1588
1483         mask |= PKT_TX_IEEE1588_TMST;
1484 #endif
1485
1486         return (flags & mask) ? 1 : 0;
1487 }
1488
1489 /* set i40e TSO context descriptor */
1490 static inline uint64_t
1491 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1492 {
1493         uint64_t ctx_desc = 0;
1494         uint32_t cd_cmd, hdr_len, cd_tso_len;
1495
1496         if (!tx_offload.l4_len) {
1497                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1498                 return ctx_desc;
1499         }
1500
1501         /**
1502          * in case of tunneling packet, the outer_l2_len and
1503          * outer_l3_len must be 0.
1504          */
1505         hdr_len = tx_offload.outer_l2_len +
1506                 tx_offload.outer_l3_len +
1507                 tx_offload.l2_len +
1508                 tx_offload.l3_len +
1509                 tx_offload.l4_len;
1510
1511         cd_cmd = I40E_TX_CTX_DESC_TSO;
1512         cd_tso_len = mbuf->pkt_len - hdr_len;
1513         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1514                 ((uint64_t)cd_tso_len <<
1515                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1516                 ((uint64_t)mbuf->tso_segsz <<
1517                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1518
1519         return ctx_desc;
1520 }
1521
1522 uint16_t
1523 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1524 {
1525         struct i40e_tx_queue *txq;
1526         struct i40e_tx_entry *sw_ring;
1527         struct i40e_tx_entry *txe, *txn;
1528         volatile struct i40e_tx_desc *txd;
1529         volatile struct i40e_tx_desc *txr;
1530         struct rte_mbuf *tx_pkt;
1531         struct rte_mbuf *m_seg;
1532         uint32_t cd_tunneling_params;
1533         uint16_t tx_id;
1534         uint16_t nb_tx;
1535         uint32_t td_cmd;
1536         uint32_t td_offset;
1537         uint32_t tx_flags;
1538         uint32_t td_tag;
1539         uint64_t ol_flags;
1540         uint16_t nb_used;
1541         uint16_t nb_ctx;
1542         uint16_t tx_last;
1543         uint16_t slen;
1544         uint64_t buf_dma_addr;
1545         union i40e_tx_offload tx_offload = {0};
1546
1547         txq = tx_queue;
1548         sw_ring = txq->sw_ring;
1549         txr = txq->tx_ring;
1550         tx_id = txq->tx_tail;
1551         txe = &sw_ring[tx_id];
1552
1553         /* Check if the descriptor ring needs to be cleaned. */
1554         if (txq->nb_tx_free < txq->tx_free_thresh)
1555                 i40e_xmit_cleanup(txq);
1556
1557         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1558                 td_cmd = 0;
1559                 td_tag = 0;
1560                 td_offset = 0;
1561                 tx_flags = 0;
1562
1563                 tx_pkt = *tx_pkts++;
1564                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1565
1566                 ol_flags = tx_pkt->ol_flags;
1567                 tx_offload.l2_len = tx_pkt->l2_len;
1568                 tx_offload.l3_len = tx_pkt->l3_len;
1569                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1570                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1571                 tx_offload.l4_len = tx_pkt->l4_len;
1572                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1573
1574                 /* Calculate the number of context descriptors needed. */
1575                 nb_ctx = i40e_calc_context_desc(ol_flags);
1576
1577                 /**
1578                  * The number of descriptors that must be allocated for
1579                  * a packet equals to the number of the segments of that
1580                  * packet plus 1 context descriptor if needed.
1581                  */
1582                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1583                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1584
1585                 /* Circular ring */
1586                 if (tx_last >= txq->nb_tx_desc)
1587                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1588
1589                 if (nb_used > txq->nb_tx_free) {
1590                         if (i40e_xmit_cleanup(txq) != 0) {
1591                                 if (nb_tx == 0)
1592                                         return 0;
1593                                 goto end_of_tx;
1594                         }
1595                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1596                                 while (nb_used > txq->nb_tx_free) {
1597                                         if (i40e_xmit_cleanup(txq) != 0) {
1598                                                 if (nb_tx == 0)
1599                                                         return 0;
1600                                                 goto end_of_tx;
1601                                         }
1602                                 }
1603                         }
1604                 }
1605
1606                 /* Descriptor based VLAN insertion */
1607                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1608                         tx_flags |= tx_pkt->vlan_tci <<
1609                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1610                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1611                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1612                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1613                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1614                 }
1615
1616                 /* Always enable CRC offload insertion */
1617                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1618
1619                 /* Enable checksum offloading */
1620                 cd_tunneling_params = 0;
1621                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK) {
1622                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1623                                 tx_offload, &cd_tunneling_params);
1624                 }
1625
1626                 if (nb_ctx) {
1627                         /* Setup TX context descriptor if required */
1628                         volatile struct i40e_tx_context_desc *ctx_txd =
1629                                 (volatile struct i40e_tx_context_desc *)\
1630                                                         &txr[tx_id];
1631                         uint16_t cd_l2tag2 = 0;
1632                         uint64_t cd_type_cmd_tso_mss =
1633                                 I40E_TX_DESC_DTYPE_CONTEXT;
1634
1635                         txn = &sw_ring[txe->next_id];
1636                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1637                         if (txe->mbuf != NULL) {
1638                                 rte_pktmbuf_free_seg(txe->mbuf);
1639                                 txe->mbuf = NULL;
1640                         }
1641
1642                         /* TSO enabled means no timestamp */
1643                         if (ol_flags & PKT_TX_TCP_SEG)
1644                                 cd_type_cmd_tso_mss |=
1645                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1646                         else {
1647 #ifdef RTE_LIBRTE_IEEE1588
1648                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1649                                         cd_type_cmd_tso_mss |=
1650                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1651                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1652 #endif
1653                         }
1654
1655                         ctx_txd->tunneling_params =
1656                                 rte_cpu_to_le_32(cd_tunneling_params);
1657                         if (ol_flags & PKT_TX_QINQ_PKT) {
1658                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1659                                 cd_type_cmd_tso_mss |=
1660                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1661                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1662                         }
1663                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1664                         ctx_txd->type_cmd_tso_mss =
1665                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1666
1667                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1668                                 "tunneling_params: %#x;\n"
1669                                 "l2tag2: %#hx;\n"
1670                                 "rsvd: %#hx;\n"
1671                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1672                                 tx_pkt, tx_id,
1673                                 ctx_txd->tunneling_params,
1674                                 ctx_txd->l2tag2,
1675                                 ctx_txd->rsvd,
1676                                 ctx_txd->type_cmd_tso_mss);
1677
1678                         txe->last_id = tx_last;
1679                         tx_id = txe->next_id;
1680                         txe = txn;
1681                 }
1682
1683                 m_seg = tx_pkt;
1684                 do {
1685                         txd = &txr[tx_id];
1686                         txn = &sw_ring[txe->next_id];
1687
1688                         if (txe->mbuf)
1689                                 rte_pktmbuf_free_seg(txe->mbuf);
1690                         txe->mbuf = m_seg;
1691
1692                         /* Setup TX Descriptor */
1693                         slen = m_seg->data_len;
1694                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1695
1696                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1697                                 "buf_dma_addr: %#"PRIx64";\n"
1698                                 "td_cmd: %#x;\n"
1699                                 "td_offset: %#x;\n"
1700                                 "td_len: %u;\n"
1701                                 "td_tag: %#x;\n",
1702                                 tx_pkt, tx_id, buf_dma_addr,
1703                                 td_cmd, td_offset, slen, td_tag);
1704
1705                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1706                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1707                                                 td_offset, slen, td_tag);
1708                         txe->last_id = tx_last;
1709                         tx_id = txe->next_id;
1710                         txe = txn;
1711                         m_seg = m_seg->next;
1712                 } while (m_seg != NULL);
1713
1714                 /* The last packet data descriptor needs End Of Packet (EOP) */
1715                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1716                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1717                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1718
1719                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1720                         PMD_TX_FREE_LOG(DEBUG,
1721                                         "Setting RS bit on TXD id="
1722                                         "%4u (port=%d queue=%d)",
1723                                         tx_last, txq->port_id, txq->queue_id);
1724
1725                         td_cmd |= I40E_TX_DESC_CMD_RS;
1726
1727                         /* Update txq RS bit counters */
1728                         txq->nb_tx_used = 0;
1729                 }
1730
1731                 txd->cmd_type_offset_bsz |=
1732                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1733                                         I40E_TXD_QW1_CMD_SHIFT);
1734         }
1735
1736 end_of_tx:
1737         rte_wmb();
1738
1739         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1740                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1741                    (unsigned) tx_id, (unsigned) nb_tx);
1742
1743         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1744         txq->tx_tail = tx_id;
1745
1746         return nb_tx;
1747 }
1748
1749 static inline int __attribute__((always_inline))
1750 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1751 {
1752         struct i40e_tx_entry *txep;
1753         uint16_t i;
1754
1755         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1756                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1757                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1758                 return 0;
1759
1760         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1761
1762         for (i = 0; i < txq->tx_rs_thresh; i++)
1763                 rte_prefetch0((txep + i)->mbuf);
1764
1765         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1766                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1767                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1768                         txep->mbuf = NULL;
1769                 }
1770         } else {
1771                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1772                         rte_pktmbuf_free_seg(txep->mbuf);
1773                         txep->mbuf = NULL;
1774                 }
1775         }
1776
1777         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1778         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1779         if (txq->tx_next_dd >= txq->nb_tx_desc)
1780                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1781
1782         return txq->tx_rs_thresh;
1783 }
1784
1785 /* Populate 4 descriptors with data from 4 mbufs */
1786 static inline void
1787 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1788 {
1789         uint64_t dma_addr;
1790         uint32_t i;
1791
1792         for (i = 0; i < 4; i++, txdp++, pkts++) {
1793                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1794                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1795                 txdp->cmd_type_offset_bsz =
1796                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1797                                         (*pkts)->data_len, 0);
1798         }
1799 }
1800
1801 /* Populate 1 descriptor with data from 1 mbuf */
1802 static inline void
1803 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1804 {
1805         uint64_t dma_addr;
1806
1807         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1808         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1809         txdp->cmd_type_offset_bsz =
1810                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1811                                 (*pkts)->data_len, 0);
1812 }
1813
1814 /* Fill hardware descriptor ring with mbuf data */
1815 static inline void
1816 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1817                      struct rte_mbuf **pkts,
1818                      uint16_t nb_pkts)
1819 {
1820         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1821         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1822         const int N_PER_LOOP = 4;
1823         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1824         int mainpart, leftover;
1825         int i, j;
1826
1827         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1828         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1829         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1830                 for (j = 0; j < N_PER_LOOP; ++j) {
1831                         (txep + i + j)->mbuf = *(pkts + i + j);
1832                 }
1833                 tx4(txdp + i, pkts + i);
1834         }
1835         if (unlikely(leftover > 0)) {
1836                 for (i = 0; i < leftover; ++i) {
1837                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1838                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1839                 }
1840         }
1841 }
1842
1843 static inline uint16_t
1844 tx_xmit_pkts(struct i40e_tx_queue *txq,
1845              struct rte_mbuf **tx_pkts,
1846              uint16_t nb_pkts)
1847 {
1848         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1849         uint16_t n = 0;
1850
1851         /**
1852          * Begin scanning the H/W ring for done descriptors when the number
1853          * of available descriptors drops below tx_free_thresh. For each done
1854          * descriptor, free the associated buffer.
1855          */
1856         if (txq->nb_tx_free < txq->tx_free_thresh)
1857                 i40e_tx_free_bufs(txq);
1858
1859         /* Use available descriptor only */
1860         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1861         if (unlikely(!nb_pkts))
1862                 return 0;
1863
1864         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1865         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1866                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1867                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1868                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1869                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1870                                                 I40E_TXD_QW1_CMD_SHIFT);
1871                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1872                 txq->tx_tail = 0;
1873         }
1874
1875         /* Fill hardware descriptor ring with mbuf data */
1876         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1877         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1878
1879         /* Determin if RS bit needs to be set */
1880         if (txq->tx_tail > txq->tx_next_rs) {
1881                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1882                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1883                                                 I40E_TXD_QW1_CMD_SHIFT);
1884                 txq->tx_next_rs =
1885                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1886                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1887                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1888         }
1889
1890         if (txq->tx_tail >= txq->nb_tx_desc)
1891                 txq->tx_tail = 0;
1892
1893         /* Update the tx tail register */
1894         rte_wmb();
1895         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1896
1897         return nb_pkts;
1898 }
1899
1900 static uint16_t
1901 i40e_xmit_pkts_simple(void *tx_queue,
1902                       struct rte_mbuf **tx_pkts,
1903                       uint16_t nb_pkts)
1904 {
1905         uint16_t nb_tx = 0;
1906
1907         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1908                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1909                                                 tx_pkts, nb_pkts);
1910
1911         while (nb_pkts) {
1912                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1913                                                 I40E_TX_MAX_BURST);
1914
1915                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1916                                                 &tx_pkts[nb_tx], num);
1917                 nb_tx = (uint16_t)(nb_tx + ret);
1918                 nb_pkts = (uint16_t)(nb_pkts - ret);
1919                 if (ret < num)
1920                         break;
1921         }
1922
1923         return nb_tx;
1924 }
1925
1926 /*
1927  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1928  * application used, which assume having sequential ones. But from driver's
1929  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1930  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1931  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1932  * use queue_idx from 0 to 95 to access queues, while real queue would be
1933  * different. This function will do a queue mapping to find VSI the queue
1934  * belongs to.
1935  */
1936 static struct i40e_vsi*
1937 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1938 {
1939         /* the queue in MAIN VSI range */
1940         if (queue_idx < pf->main_vsi->nb_qps)
1941                 return pf->main_vsi;
1942
1943         queue_idx -= pf->main_vsi->nb_qps;
1944
1945         /* queue_idx is greater than VMDQ VSIs range */
1946         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1947                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1948                 return NULL;
1949         }
1950
1951         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1952 }
1953
1954 static uint16_t
1955 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1956 {
1957         /* the queue in MAIN VSI range */
1958         if (queue_idx < pf->main_vsi->nb_qps)
1959                 return queue_idx;
1960
1961         /* It's VMDQ queues */
1962         queue_idx -= pf->main_vsi->nb_qps;
1963
1964         if (pf->nb_cfg_vmdq_vsi)
1965                 return queue_idx % pf->vmdq_nb_qps;
1966         else {
1967                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1968                 return (uint16_t)(-1);
1969         }
1970 }
1971
1972 int
1973 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1974 {
1975         struct i40e_rx_queue *rxq;
1976         int err = -1;
1977         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1978
1979         PMD_INIT_FUNC_TRACE();
1980
1981         if (rx_queue_id < dev->data->nb_rx_queues) {
1982                 rxq = dev->data->rx_queues[rx_queue_id];
1983
1984                 err = i40e_alloc_rx_queue_mbufs(rxq);
1985                 if (err) {
1986                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1987                         return err;
1988                 }
1989
1990                 rte_wmb();
1991
1992                 /* Init the RX tail regieter. */
1993                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1994
1995                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1996
1997                 if (err) {
1998                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1999                                     rx_queue_id);
2000
2001                         i40e_rx_queue_release_mbufs(rxq);
2002                         i40e_reset_rx_queue(rxq);
2003                 } else
2004                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2005         }
2006
2007         return err;
2008 }
2009
2010 int
2011 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2012 {
2013         struct i40e_rx_queue *rxq;
2014         int err;
2015         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2016
2017         if (rx_queue_id < dev->data->nb_rx_queues) {
2018                 rxq = dev->data->rx_queues[rx_queue_id];
2019
2020                 /*
2021                 * rx_queue_id is queue id aplication refers to, while
2022                 * rxq->reg_idx is the real queue index.
2023                 */
2024                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
2025
2026                 if (err) {
2027                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
2028                                     rx_queue_id);
2029                         return err;
2030                 }
2031                 i40e_rx_queue_release_mbufs(rxq);
2032                 i40e_reset_rx_queue(rxq);
2033                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2034         }
2035
2036         return 0;
2037 }
2038
2039 int
2040 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2041 {
2042         int err = -1;
2043         struct i40e_tx_queue *txq;
2044         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2045
2046         PMD_INIT_FUNC_TRACE();
2047
2048         if (tx_queue_id < dev->data->nb_tx_queues) {
2049                 txq = dev->data->tx_queues[tx_queue_id];
2050
2051                 /*
2052                 * tx_queue_id is queue id aplication refers to, while
2053                 * rxq->reg_idx is the real queue index.
2054                 */
2055                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
2056                 if (err)
2057                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
2058                                     tx_queue_id);
2059                 else
2060                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
2061         }
2062
2063         return err;
2064 }
2065
2066 int
2067 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
2068 {
2069         struct i40e_tx_queue *txq;
2070         int err;
2071         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2072
2073         if (tx_queue_id < dev->data->nb_tx_queues) {
2074                 txq = dev->data->tx_queues[tx_queue_id];
2075
2076                 /*
2077                 * tx_queue_id is queue id aplication refers to, while
2078                 * txq->reg_idx is the real queue index.
2079                 */
2080                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
2081
2082                 if (err) {
2083                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
2084                                     tx_queue_id);
2085                         return err;
2086                 }
2087
2088                 i40e_tx_queue_release_mbufs(txq);
2089                 i40e_reset_tx_queue(txq);
2090                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
2091         }
2092
2093         return 0;
2094 }
2095
2096 int
2097 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
2098                         uint16_t queue_idx,
2099                         uint16_t nb_desc,
2100                         unsigned int socket_id,
2101                         const struct rte_eth_rxconf *rx_conf,
2102                         struct rte_mempool *mp)
2103 {
2104         struct i40e_vsi *vsi;
2105         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2106         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2107         struct i40e_adapter *ad =
2108                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2109         struct i40e_rx_queue *rxq;
2110         const struct rte_memzone *rz;
2111         uint32_t ring_size;
2112         uint16_t len, i;
2113         uint16_t base, bsf, tc_mapping;
2114         int use_def_burst_func = 1;
2115
2116         if (hw->mac.type == I40E_MAC_VF) {
2117                 struct i40e_vf *vf =
2118                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2119                 vsi = &vf->vsi;
2120         } else
2121                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2122
2123         if (vsi == NULL) {
2124                 PMD_DRV_LOG(ERR, "VSI not available or queue "
2125                             "index exceeds the maximum");
2126                 return I40E_ERR_PARAM;
2127         }
2128         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2129                         (nb_desc > I40E_MAX_RING_DESC) ||
2130                         (nb_desc < I40E_MIN_RING_DESC)) {
2131                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
2132                             "invalid", nb_desc);
2133                 return I40E_ERR_PARAM;
2134         }
2135
2136         /* Free memory if needed */
2137         if (dev->data->rx_queues[queue_idx]) {
2138                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
2139                 dev->data->rx_queues[queue_idx] = NULL;
2140         }
2141
2142         /* Allocate the rx queue data structure */
2143         rxq = rte_zmalloc_socket("i40e rx queue",
2144                                  sizeof(struct i40e_rx_queue),
2145                                  RTE_CACHE_LINE_SIZE,
2146                                  socket_id);
2147         if (!rxq) {
2148                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2149                             "rx queue data structure");
2150                 return -ENOMEM;
2151         }
2152         rxq->mp = mp;
2153         rxq->nb_rx_desc = nb_desc;
2154         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
2155         rxq->queue_id = queue_idx;
2156         if (hw->mac.type == I40E_MAC_VF)
2157                 rxq->reg_idx = queue_idx;
2158         else /* PF device */
2159                 rxq->reg_idx = vsi->base_queue +
2160                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2161
2162         rxq->port_id = dev->data->port_id;
2163         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
2164                                                         0 : ETHER_CRC_LEN);
2165         rxq->drop_en = rx_conf->rx_drop_en;
2166         rxq->vsi = vsi;
2167         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
2168
2169         /* Allocate the maximun number of RX ring hardware descriptor. */
2170         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
2171         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2172         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
2173                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2174         if (!rz) {
2175                 i40e_dev_rx_queue_release(rxq);
2176                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
2177                 return -ENOMEM;
2178         }
2179
2180         /* Zero all the descriptors in the ring. */
2181         memset(rz->addr, 0, ring_size);
2182
2183         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2184         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2185
2186 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2187         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
2188 #else
2189         len = nb_desc;
2190 #endif
2191
2192         /* Allocate the software ring. */
2193         rxq->sw_ring =
2194                 rte_zmalloc_socket("i40e rx sw ring",
2195                                    sizeof(struct i40e_rx_entry) * len,
2196                                    RTE_CACHE_LINE_SIZE,
2197                                    socket_id);
2198         if (!rxq->sw_ring) {
2199                 i40e_dev_rx_queue_release(rxq);
2200                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
2201                 return -ENOMEM;
2202         }
2203
2204         i40e_reset_rx_queue(rxq);
2205         rxq->q_set = TRUE;
2206         dev->data->rx_queues[queue_idx] = rxq;
2207
2208         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
2209
2210         if (!use_def_burst_func) {
2211 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2212                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2213                              "satisfied. Rx Burst Bulk Alloc function will be "
2214                              "used on port=%d, queue=%d.",
2215                              rxq->port_id, rxq->queue_id);
2216 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2217         } else {
2218                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2219                              "not satisfied, Scattered Rx is requested, "
2220                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
2221                              "not enabled on port=%d, queue=%d.",
2222                              rxq->port_id, rxq->queue_id);
2223                 ad->rx_bulk_alloc_allowed = false;
2224         }
2225
2226         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2227                 if (!(vsi->enabled_tc & (1 << i)))
2228                         continue;
2229                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2230                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2231                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2232                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2233                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2234
2235                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2236                         rxq->dcb_tc = i;
2237         }
2238
2239         return 0;
2240 }
2241
2242 void
2243 i40e_dev_rx_queue_release(void *rxq)
2244 {
2245         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
2246
2247         if (!q) {
2248                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2249                 return;
2250         }
2251
2252         i40e_rx_queue_release_mbufs(q);
2253         rte_free(q->sw_ring);
2254         rte_free(q);
2255 }
2256
2257 uint32_t
2258 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
2259 {
2260 #define I40E_RXQ_SCAN_INTERVAL 4
2261         volatile union i40e_rx_desc *rxdp;
2262         struct i40e_rx_queue *rxq;
2263         uint16_t desc = 0;
2264
2265         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
2266                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
2267                 return 0;
2268         }
2269
2270         rxq = dev->data->rx_queues[rx_queue_id];
2271         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2272         while ((desc < rxq->nb_rx_desc) &&
2273                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2274                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2275                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2276                 /**
2277                  * Check the DD bit of a rx descriptor of each 4 in a group,
2278                  * to avoid checking too frequently and downgrading performance
2279                  * too much.
2280                  */
2281                 desc += I40E_RXQ_SCAN_INTERVAL;
2282                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2283                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2284                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2285                                         desc - rxq->nb_rx_desc]);
2286         }
2287
2288         return desc;
2289 }
2290
2291 int
2292 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2293 {
2294         volatile union i40e_rx_desc *rxdp;
2295         struct i40e_rx_queue *rxq = rx_queue;
2296         uint16_t desc;
2297         int ret;
2298
2299         if (unlikely(offset >= rxq->nb_rx_desc)) {
2300                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2301                 return 0;
2302         }
2303
2304         desc = rxq->rx_tail + offset;
2305         if (desc >= rxq->nb_rx_desc)
2306                 desc -= rxq->nb_rx_desc;
2307
2308         rxdp = &(rxq->rx_ring[desc]);
2309
2310         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2311                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2312                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2313
2314         return ret;
2315 }
2316
2317 int
2318 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2319                         uint16_t queue_idx,
2320                         uint16_t nb_desc,
2321                         unsigned int socket_id,
2322                         const struct rte_eth_txconf *tx_conf)
2323 {
2324         struct i40e_vsi *vsi;
2325         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2326         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2327         struct i40e_tx_queue *txq;
2328         const struct rte_memzone *tz;
2329         uint32_t ring_size;
2330         uint16_t tx_rs_thresh, tx_free_thresh;
2331         uint16_t i, base, bsf, tc_mapping;
2332
2333         if (hw->mac.type == I40E_MAC_VF) {
2334                 struct i40e_vf *vf =
2335                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2336                 vsi = &vf->vsi;
2337         } else
2338                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2339
2340         if (vsi == NULL) {
2341                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2342                             "exceeds the maximum", queue_idx);
2343                 return I40E_ERR_PARAM;
2344         }
2345
2346         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2347                         (nb_desc > I40E_MAX_RING_DESC) ||
2348                         (nb_desc < I40E_MIN_RING_DESC)) {
2349                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2350                             "invalid", nb_desc);
2351                 return I40E_ERR_PARAM;
2352         }
2353
2354         /**
2355          * The following two parameters control the setting of the RS bit on
2356          * transmit descriptors. TX descriptors will have their RS bit set
2357          * after txq->tx_rs_thresh descriptors have been used. The TX
2358          * descriptor ring will be cleaned after txq->tx_free_thresh
2359          * descriptors are used or if the number of descriptors required to
2360          * transmit a packet is greater than the number of free TX descriptors.
2361          *
2362          * The following constraints must be satisfied:
2363          *  - tx_rs_thresh must be greater than 0.
2364          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2365          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2366          *  - tx_rs_thresh must be a divisor of the ring size.
2367          *  - tx_free_thresh must be greater than 0.
2368          *  - tx_free_thresh must be less than the size of the ring minus 3.
2369          *
2370          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2371          * race condition, hence the maximum threshold constraints. When set
2372          * to zero use default values.
2373          */
2374         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2375                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2376         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2377                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2378         if (tx_rs_thresh >= (nb_desc - 2)) {
2379                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2380                              "number of TX descriptors minus 2. "
2381                              "(tx_rs_thresh=%u port=%d queue=%d)",
2382                              (unsigned int)tx_rs_thresh,
2383                              (int)dev->data->port_id,
2384                              (int)queue_idx);
2385                 return I40E_ERR_PARAM;
2386         }
2387         if (tx_free_thresh >= (nb_desc - 3)) {
2388                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2389                              "tx_free_thresh must be less than the "
2390                              "number of TX descriptors minus 3. "
2391                              "(tx_free_thresh=%u port=%d queue=%d)",
2392                              (unsigned int)tx_free_thresh,
2393                              (int)dev->data->port_id,
2394                              (int)queue_idx);
2395                 return I40E_ERR_PARAM;
2396         }
2397         if (tx_rs_thresh > tx_free_thresh) {
2398                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2399                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2400                              " tx_rs_thresh=%u port=%d queue=%d)",
2401                              (unsigned int)tx_free_thresh,
2402                              (unsigned int)tx_rs_thresh,
2403                              (int)dev->data->port_id,
2404                              (int)queue_idx);
2405                 return I40E_ERR_PARAM;
2406         }
2407         if ((nb_desc % tx_rs_thresh) != 0) {
2408                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2409                              "number of TX descriptors. (tx_rs_thresh=%u"
2410                              " port=%d queue=%d)",
2411                              (unsigned int)tx_rs_thresh,
2412                              (int)dev->data->port_id,
2413                              (int)queue_idx);
2414                 return I40E_ERR_PARAM;
2415         }
2416         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2417                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2418                              "tx_rs_thresh is greater than 1. "
2419                              "(tx_rs_thresh=%u port=%d queue=%d)",
2420                              (unsigned int)tx_rs_thresh,
2421                              (int)dev->data->port_id,
2422                              (int)queue_idx);
2423                 return I40E_ERR_PARAM;
2424         }
2425
2426         /* Free memory if needed. */
2427         if (dev->data->tx_queues[queue_idx]) {
2428                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2429                 dev->data->tx_queues[queue_idx] = NULL;
2430         }
2431
2432         /* Allocate the TX queue data structure. */
2433         txq = rte_zmalloc_socket("i40e tx queue",
2434                                   sizeof(struct i40e_tx_queue),
2435                                   RTE_CACHE_LINE_SIZE,
2436                                   socket_id);
2437         if (!txq) {
2438                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2439                             "tx queue structure");
2440                 return -ENOMEM;
2441         }
2442
2443         /* Allocate TX hardware ring descriptors. */
2444         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2445         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2446         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2447                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2448         if (!tz) {
2449                 i40e_dev_tx_queue_release(txq);
2450                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2451                 return -ENOMEM;
2452         }
2453
2454         txq->nb_tx_desc = nb_desc;
2455         txq->tx_rs_thresh = tx_rs_thresh;
2456         txq->tx_free_thresh = tx_free_thresh;
2457         txq->pthresh = tx_conf->tx_thresh.pthresh;
2458         txq->hthresh = tx_conf->tx_thresh.hthresh;
2459         txq->wthresh = tx_conf->tx_thresh.wthresh;
2460         txq->queue_id = queue_idx;
2461         if (hw->mac.type == I40E_MAC_VF)
2462                 txq->reg_idx = queue_idx;
2463         else /* PF device */
2464                 txq->reg_idx = vsi->base_queue +
2465                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2466
2467         txq->port_id = dev->data->port_id;
2468         txq->txq_flags = tx_conf->txq_flags;
2469         txq->vsi = vsi;
2470         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2471
2472         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2473         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2474
2475         /* Allocate software ring */
2476         txq->sw_ring =
2477                 rte_zmalloc_socket("i40e tx sw ring",
2478                                    sizeof(struct i40e_tx_entry) * nb_desc,
2479                                    RTE_CACHE_LINE_SIZE,
2480                                    socket_id);
2481         if (!txq->sw_ring) {
2482                 i40e_dev_tx_queue_release(txq);
2483                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2484                 return -ENOMEM;
2485         }
2486
2487         i40e_reset_tx_queue(txq);
2488         txq->q_set = TRUE;
2489         dev->data->tx_queues[queue_idx] = txq;
2490
2491         /* Use a simple TX queue without offloads or multi segs if possible */
2492         i40e_set_tx_function_flag(dev, txq);
2493
2494         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2495                 if (!(vsi->enabled_tc & (1 << i)))
2496                         continue;
2497                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2498                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2499                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2500                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2501                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2502
2503                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2504                         txq->dcb_tc = i;
2505         }
2506
2507         return 0;
2508 }
2509
2510 void
2511 i40e_dev_tx_queue_release(void *txq)
2512 {
2513         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2514
2515         if (!q) {
2516                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2517                 return;
2518         }
2519
2520         i40e_tx_queue_release_mbufs(q);
2521         rte_free(q->sw_ring);
2522         rte_free(q);
2523 }
2524
2525 const struct rte_memzone *
2526 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2527 {
2528         const struct rte_memzone *mz;
2529
2530         mz = rte_memzone_lookup(name);
2531         if (mz)
2532                 return mz;
2533
2534         if (rte_xen_dom0_supported())
2535                 mz = rte_memzone_reserve_bounded(name, len,
2536                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2537         else
2538                 mz = rte_memzone_reserve_aligned(name, len,
2539                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2540         return mz;
2541 }
2542
2543 void
2544 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2545 {
2546         uint16_t i;
2547
2548         /* SSE Vector driver has a different way of releasing mbufs. */
2549         if (rxq->rx_using_sse) {
2550                 i40e_rx_queue_release_mbufs_vec(rxq);
2551                 return;
2552         }
2553
2554         if (!rxq || !rxq->sw_ring) {
2555                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2556                 return;
2557         }
2558
2559         for (i = 0; i < rxq->nb_rx_desc; i++) {
2560                 if (rxq->sw_ring[i].mbuf) {
2561                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2562                         rxq->sw_ring[i].mbuf = NULL;
2563                 }
2564         }
2565 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2566         if (rxq->rx_nb_avail == 0)
2567                 return;
2568         for (i = 0; i < rxq->rx_nb_avail; i++) {
2569                 struct rte_mbuf *mbuf;
2570
2571                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2572                 rte_pktmbuf_free_seg(mbuf);
2573         }
2574         rxq->rx_nb_avail = 0;
2575 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2576 }
2577
2578 void
2579 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2580 {
2581         unsigned i;
2582         uint16_t len;
2583
2584         if (!rxq) {
2585                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2586                 return;
2587         }
2588
2589 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2590         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2591                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2592         else
2593 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2594                 len = rxq->nb_rx_desc;
2595
2596         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2597                 ((volatile char *)rxq->rx_ring)[i] = 0;
2598
2599 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2600         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2601         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2602                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2603
2604         rxq->rx_nb_avail = 0;
2605         rxq->rx_next_avail = 0;
2606         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2607 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2608         rxq->rx_tail = 0;
2609         rxq->nb_rx_hold = 0;
2610         rxq->pkt_first_seg = NULL;
2611         rxq->pkt_last_seg = NULL;
2612
2613         rxq->rxrearm_start = 0;
2614         rxq->rxrearm_nb = 0;
2615 }
2616
2617 void
2618 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2619 {
2620         uint16_t i;
2621
2622         if (!txq || !txq->sw_ring) {
2623                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2624                 return;
2625         }
2626
2627         for (i = 0; i < txq->nb_tx_desc; i++) {
2628                 if (txq->sw_ring[i].mbuf) {
2629                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2630                         txq->sw_ring[i].mbuf = NULL;
2631                 }
2632         }
2633 }
2634
2635 void
2636 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2637 {
2638         struct i40e_tx_entry *txe;
2639         uint16_t i, prev, size;
2640
2641         if (!txq) {
2642                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2643                 return;
2644         }
2645
2646         txe = txq->sw_ring;
2647         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2648         for (i = 0; i < size; i++)
2649                 ((volatile char *)txq->tx_ring)[i] = 0;
2650
2651         prev = (uint16_t)(txq->nb_tx_desc - 1);
2652         for (i = 0; i < txq->nb_tx_desc; i++) {
2653                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2654
2655                 txd->cmd_type_offset_bsz =
2656                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2657                 txe[i].mbuf =  NULL;
2658                 txe[i].last_id = i;
2659                 txe[prev].next_id = i;
2660                 prev = i;
2661         }
2662
2663         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2664         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2665
2666         txq->tx_tail = 0;
2667         txq->nb_tx_used = 0;
2668
2669         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2670         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2671 }
2672
2673 /* Init the TX queue in hardware */
2674 int
2675 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2676 {
2677         enum i40e_status_code err = I40E_SUCCESS;
2678         struct i40e_vsi *vsi = txq->vsi;
2679         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2680         uint16_t pf_q = txq->reg_idx;
2681         struct i40e_hmc_obj_txq tx_ctx;
2682         uint32_t qtx_ctl;
2683
2684         /* clear the context structure first */
2685         memset(&tx_ctx, 0, sizeof(tx_ctx));
2686         tx_ctx.new_context = 1;
2687         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2688         tx_ctx.qlen = txq->nb_tx_desc;
2689
2690 #ifdef RTE_LIBRTE_IEEE1588
2691         tx_ctx.timesync_ena = 1;
2692 #endif
2693         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2694         if (vsi->type == I40E_VSI_FDIR)
2695                 tx_ctx.fd_ena = TRUE;
2696
2697         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2698         if (err != I40E_SUCCESS) {
2699                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2700                 return err;
2701         }
2702
2703         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2704         if (err != I40E_SUCCESS) {
2705                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2706                 return err;
2707         }
2708
2709         /* Now associate this queue with this PCI function */
2710         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2711         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2712                                         I40E_QTX_CTL_PF_INDX_MASK);
2713         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2714         I40E_WRITE_FLUSH(hw);
2715
2716         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2717
2718         return err;
2719 }
2720
2721 int
2722 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2723 {
2724         struct i40e_rx_entry *rxe = rxq->sw_ring;
2725         uint64_t dma_addr;
2726         uint16_t i;
2727
2728         for (i = 0; i < rxq->nb_rx_desc; i++) {
2729                 volatile union i40e_rx_desc *rxd;
2730                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2731
2732                 if (unlikely(!mbuf)) {
2733                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2734                         return -ENOMEM;
2735                 }
2736
2737                 rte_mbuf_refcnt_set(mbuf, 1);
2738                 mbuf->next = NULL;
2739                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2740                 mbuf->nb_segs = 1;
2741                 mbuf->port = rxq->port_id;
2742
2743                 dma_addr =
2744                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2745
2746                 rxd = &rxq->rx_ring[i];
2747                 rxd->read.pkt_addr = dma_addr;
2748                 rxd->read.hdr_addr = 0;
2749 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2750                 rxd->read.rsvd1 = 0;
2751                 rxd->read.rsvd2 = 0;
2752 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2753
2754                 rxe[i].mbuf = mbuf;
2755         }
2756
2757         return 0;
2758 }
2759
2760 /*
2761  * Calculate the buffer length, and check the jumbo frame
2762  * and maximum packet length.
2763  */
2764 static int
2765 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2766 {
2767         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2768         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2769         struct rte_eth_dev_data *data = pf->dev_data;
2770         uint16_t buf_size, len;
2771
2772         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2773                 RTE_PKTMBUF_HEADROOM);
2774
2775         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2776                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2777         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2778                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2779                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2780                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2781                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2782                 rxq->hs_mode = i40e_header_split_enabled;
2783                 break;
2784         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2785         default:
2786                 rxq->rx_hdr_len = 0;
2787                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2788                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2789                 rxq->hs_mode = i40e_header_split_none;
2790                 break;
2791         }
2792
2793         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2794         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2795         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2796                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2797                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2798                         PMD_DRV_LOG(ERR, "maximum packet length must "
2799                                     "be larger than %u and smaller than %u,"
2800                                     "as jumbo frame is enabled",
2801                                     (uint32_t)ETHER_MAX_LEN,
2802                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2803                         return I40E_ERR_CONFIG;
2804                 }
2805         } else {
2806                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2807                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2808                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2809                                     "larger than %u and smaller than %u, "
2810                                     "as jumbo frame is disabled",
2811                                     (uint32_t)ETHER_MIN_LEN,
2812                                     (uint32_t)ETHER_MAX_LEN);
2813                         return I40E_ERR_CONFIG;
2814                 }
2815         }
2816
2817         return 0;
2818 }
2819
2820 /* Init the RX queue in hardware */
2821 int
2822 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2823 {
2824         int err = I40E_SUCCESS;
2825         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2826         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2827         uint16_t pf_q = rxq->reg_idx;
2828         uint16_t buf_size;
2829         struct i40e_hmc_obj_rxq rx_ctx;
2830
2831         err = i40e_rx_queue_config(rxq);
2832         if (err < 0) {
2833                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2834                 return err;
2835         }
2836
2837         /* Clear the context structure first */
2838         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2839         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2840         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2841
2842         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2843         rx_ctx.qlen = rxq->nb_rx_desc;
2844 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2845         rx_ctx.dsize = 1;
2846 #endif
2847         rx_ctx.dtype = rxq->hs_mode;
2848         if (rxq->hs_mode)
2849                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2850         else
2851                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2852         rx_ctx.rxmax = rxq->max_pkt_len;
2853         rx_ctx.tphrdesc_ena = 1;
2854         rx_ctx.tphwdesc_ena = 1;
2855         rx_ctx.tphdata_ena = 1;
2856         rx_ctx.tphhead_ena = 1;
2857         rx_ctx.lrxqthresh = 2;
2858         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2859         rx_ctx.l2tsel = 1;
2860         rx_ctx.showiv = 1;
2861         rx_ctx.prefena = 1;
2862
2863         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2864         if (err != I40E_SUCCESS) {
2865                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2866                 return err;
2867         }
2868         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2869         if (err != I40E_SUCCESS) {
2870                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2871                 return err;
2872         }
2873
2874         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2875
2876         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2877                 RTE_PKTMBUF_HEADROOM);
2878
2879         /* Check if scattered RX needs to be used. */
2880         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2881                 dev_data->scattered_rx = 1;
2882         }
2883
2884         /* Init the RX tail regieter. */
2885         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2886
2887         return 0;
2888 }
2889
2890 void
2891 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2892 {
2893         uint16_t i;
2894
2895         PMD_INIT_FUNC_TRACE();
2896
2897         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2898                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2899                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2900         }
2901
2902         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2903                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2904                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2905         }
2906 }
2907
2908 void
2909 i40e_dev_free_queues(struct rte_eth_dev *dev)
2910 {
2911         uint16_t i;
2912
2913         PMD_INIT_FUNC_TRACE();
2914
2915         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2916                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2917                 dev->data->rx_queues[i] = NULL;
2918         }
2919         dev->data->nb_rx_queues = 0;
2920
2921         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2922                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2923                 dev->data->tx_queues[i] = NULL;
2924         }
2925         dev->data->nb_tx_queues = 0;
2926 }
2927
2928 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2929 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2930
2931 enum i40e_status_code
2932 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2933 {
2934         struct i40e_tx_queue *txq;
2935         const struct rte_memzone *tz = NULL;
2936         uint32_t ring_size;
2937         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2938
2939         if (!pf) {
2940                 PMD_DRV_LOG(ERR, "PF is not available");
2941                 return I40E_ERR_BAD_PTR;
2942         }
2943
2944         /* Allocate the TX queue data structure. */
2945         txq = rte_zmalloc_socket("i40e fdir tx queue",
2946                                   sizeof(struct i40e_tx_queue),
2947                                   RTE_CACHE_LINE_SIZE,
2948                                   SOCKET_ID_ANY);
2949         if (!txq) {
2950                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2951                                         "tx queue structure.");
2952                 return I40E_ERR_NO_MEMORY;
2953         }
2954
2955         /* Allocate TX hardware ring descriptors. */
2956         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2957         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2958
2959         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2960                                       I40E_FDIR_QUEUE_ID, ring_size,
2961                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2962         if (!tz) {
2963                 i40e_dev_tx_queue_release(txq);
2964                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2965                 return I40E_ERR_NO_MEMORY;
2966         }
2967
2968         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2969         txq->queue_id = I40E_FDIR_QUEUE_ID;
2970         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2971         txq->vsi = pf->fdir.fdir_vsi;
2972
2973         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2974         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2975         /*
2976          * don't need to allocate software ring and reset for the fdir
2977          * program queue just set the queue has been configured.
2978          */
2979         txq->q_set = TRUE;
2980         pf->fdir.txq = txq;
2981
2982         return I40E_SUCCESS;
2983 }
2984
2985 enum i40e_status_code
2986 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2987 {
2988         struct i40e_rx_queue *rxq;
2989         const struct rte_memzone *rz = NULL;
2990         uint32_t ring_size;
2991         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2992
2993         if (!pf) {
2994                 PMD_DRV_LOG(ERR, "PF is not available");
2995                 return I40E_ERR_BAD_PTR;
2996         }
2997
2998         /* Allocate the RX queue data structure. */
2999         rxq = rte_zmalloc_socket("i40e fdir rx queue",
3000                                   sizeof(struct i40e_rx_queue),
3001                                   RTE_CACHE_LINE_SIZE,
3002                                   SOCKET_ID_ANY);
3003         if (!rxq) {
3004                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
3005                                         "rx queue structure.");
3006                 return I40E_ERR_NO_MEMORY;
3007         }
3008
3009         /* Allocate RX hardware ring descriptors. */
3010         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
3011         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
3012
3013         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
3014                                       I40E_FDIR_QUEUE_ID, ring_size,
3015                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
3016         if (!rz) {
3017                 i40e_dev_rx_queue_release(rxq);
3018                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
3019                 return I40E_ERR_NO_MEMORY;
3020         }
3021
3022         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
3023         rxq->queue_id = I40E_FDIR_QUEUE_ID;
3024         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
3025         rxq->vsi = pf->fdir.fdir_vsi;
3026
3027         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
3028         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
3029
3030         /*
3031          * Don't need to allocate software ring and reset for the fdir
3032          * rx queue, just set the queue has been configured.
3033          */
3034         rxq->q_set = TRUE;
3035         pf->fdir.rxq = rxq;
3036
3037         return I40E_SUCCESS;
3038 }
3039
3040 void
3041 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3042         struct rte_eth_rxq_info *qinfo)
3043 {
3044         struct i40e_rx_queue *rxq;
3045
3046         rxq = dev->data->rx_queues[queue_id];
3047
3048         qinfo->mp = rxq->mp;
3049         qinfo->scattered_rx = dev->data->scattered_rx;
3050         qinfo->nb_desc = rxq->nb_rx_desc;
3051
3052         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
3053         qinfo->conf.rx_drop_en = rxq->drop_en;
3054         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
3055 }
3056
3057 void
3058 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
3059         struct rte_eth_txq_info *qinfo)
3060 {
3061         struct i40e_tx_queue *txq;
3062
3063         txq = dev->data->tx_queues[queue_id];
3064
3065         qinfo->nb_desc = txq->nb_tx_desc;
3066
3067         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
3068         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
3069         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
3070
3071         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
3072         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
3073         qinfo->conf.txq_flags = txq->txq_flags;
3074         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
3075 }
3076
3077 void __attribute__((cold))
3078 i40e_set_rx_function(struct rte_eth_dev *dev)
3079 {
3080         struct i40e_adapter *ad =
3081                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3082         uint16_t rx_using_sse, i;
3083         /* In order to allow Vector Rx there are a few configuration
3084          * conditions to be met and Rx Bulk Allocation should be allowed.
3085          */
3086         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3087                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
3088                     !ad->rx_bulk_alloc_allowed) {
3089                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
3090                                      " Vector Rx preconditions",
3091                                      dev->data->port_id);
3092
3093                         ad->rx_vec_allowed = false;
3094                 }
3095                 if (ad->rx_vec_allowed) {
3096                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
3097                                 struct i40e_rx_queue *rxq =
3098                                         dev->data->rx_queues[i];
3099
3100                                 if (i40e_rxq_vec_setup(rxq)) {
3101                                         ad->rx_vec_allowed = false;
3102                                         break;
3103                                 }
3104                         }
3105                 }
3106         }
3107
3108         if (dev->data->scattered_rx) {
3109                 /* Set the non-LRO scattered callback: there are Vector and
3110                  * single allocation versions.
3111                  */
3112                 if (ad->rx_vec_allowed) {
3113                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
3114                                             "callback (port=%d).",
3115                                      dev->data->port_id);
3116
3117                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
3118                 } else {
3119                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3120                                            "allocation callback (port=%d).",
3121                                      dev->data->port_id);
3122                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3123                 }
3124         /* If parameters allow we are going to choose between the following
3125          * callbacks:
3126          *    - Vector
3127          *    - Bulk Allocation
3128          *    - Single buffer allocation (the simplest one)
3129          */
3130         } else if (ad->rx_vec_allowed) {
3131                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3132                                     "burst size no less than %d (port=%d).",
3133                              RTE_I40E_DESCS_PER_LOOP,
3134                              dev->data->port_id);
3135
3136                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3137         } else if (ad->rx_bulk_alloc_allowed) {
3138                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3139                                     "satisfied. Rx Burst Bulk Alloc function "
3140                                     "will be used on port=%d.",
3141                              dev->data->port_id);
3142
3143                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3144         } else {
3145                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3146                                     "satisfied, or Scattered Rx is requested "
3147                                     "(port=%d).",
3148                              dev->data->port_id);
3149
3150                 dev->rx_pkt_burst = i40e_recv_pkts;
3151         }
3152
3153         /* Propagate information about RX function choice through all queues. */
3154         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3155                 rx_using_sse =
3156                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3157                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
3158
3159                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3160                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3161
3162                         rxq->rx_using_sse = rx_using_sse;
3163                 }
3164         }
3165 }
3166
3167 void __attribute__((cold))
3168 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3169 {
3170         struct i40e_adapter *ad =
3171                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3172
3173         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3174         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
3175                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
3176                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
3177                         PMD_INIT_LOG(DEBUG, "Vector tx"
3178                                      " can be enabled on this txq.");
3179
3180                 } else {
3181                         ad->tx_vec_allowed = false;
3182                 }
3183         } else {
3184                 ad->tx_simple_allowed = false;
3185         }
3186 }
3187
3188 void __attribute__((cold))
3189 i40e_set_tx_function(struct rte_eth_dev *dev)
3190 {
3191         struct i40e_adapter *ad =
3192                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3193         int i;
3194
3195         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3196                 if (ad->tx_vec_allowed) {
3197                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3198                                 struct i40e_tx_queue *txq =
3199                                         dev->data->tx_queues[i];
3200
3201                                 if (i40e_txq_vec_setup(txq)) {
3202                                         ad->tx_vec_allowed = false;
3203                                         break;
3204                                 }
3205                         }
3206                 }
3207         }
3208
3209         if (ad->tx_simple_allowed) {
3210                 if (ad->tx_vec_allowed) {
3211                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3212                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3213                 } else {
3214                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3215                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3216                 }
3217         } else {
3218                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3219                 dev->tx_pkt_burst = i40e_xmit_pkts;
3220         }
3221 }
3222
3223 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3224 int __attribute__((weak))
3225 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3226 {
3227         return -1;
3228 }
3229
3230 uint16_t __attribute__((weak))
3231 i40e_recv_pkts_vec(
3232         void __rte_unused *rx_queue,
3233         struct rte_mbuf __rte_unused **rx_pkts,
3234         uint16_t __rte_unused nb_pkts)
3235 {
3236         return 0;
3237 }
3238
3239 uint16_t __attribute__((weak))
3240 i40e_recv_scattered_pkts_vec(
3241         void __rte_unused *rx_queue,
3242         struct rte_mbuf __rte_unused **rx_pkts,
3243         uint16_t __rte_unused nb_pkts)
3244 {
3245         return 0;
3246 }
3247
3248 int __attribute__((weak))
3249 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3250 {
3251         return -1;
3252 }
3253
3254 int __attribute__((weak))
3255 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3256 {
3257         return -1;
3258 }
3259
3260 void __attribute__((weak))
3261 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3262 {
3263         return;
3264 }
3265
3266 uint16_t __attribute__((weak))
3267 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
3268                    struct rte_mbuf __rte_unused **tx_pkts,
3269                    uint16_t __rte_unused nb_pkts)
3270 {
3271         return 0;
3272 }