drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53 #include <rte_ip.h>
  54 #include <rte_net.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_type.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61
  62 #define DEFAULT_TX_RS_THRESH   32
  63 #define DEFAULT_TX_FREE_THRESH 32
  64 #define I40E_MAX_PKT_TYPE      256
  65
  66 #define I40E_TX_MAX_BURST  32
  67
  68 #define I40E_DMA_MEM_ALIGN 4096
  69
  70 /* Base address of the HW descriptor ring should be 128B aligned. */
  71 #define I40E_RING_BASE_ALIGN    128
  72
  73 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  74                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  75
  76 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  77
  78 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  79                 PKT_TX_IP_CKSUM |                \
  80                 PKT_TX_L4_MASK |                 \
  81                 PKT_TX_TCP_SEG |                 \
  82                 PKT_TX_OUTER_IP_CKSUM)
  83
  84 #define I40E_TX_OFFLOAD_MASK (  \
  85                 PKT_TX_IP_CKSUM |       \
  86                 PKT_TX_L4_MASK |        \
  87                 PKT_TX_OUTER_IP_CKSUM | \
  88                 PKT_TX_TCP_SEG |        \
  89                 PKT_TX_QINQ_PKT |       \
  90                 PKT_TX_VLAN_PKT)
  91
  92 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  93                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  94
  95 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  96                                       struct rte_mbuf **tx_pkts,
  97                                       uint16_t nb_pkts);
  98
  99 static inline void
 100 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 101 {
 102         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 103                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 104                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 105                 mb->vlan_tci =
 106                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 107                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 108                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 109         } else {
 110                 mb->vlan_tci = 0;
 111         }
 112 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 113         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 114                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 115                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 116                 mb->vlan_tci_outer = mb->vlan_tci;
 117                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 118                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 119                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 120                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 121         } else {
 122                 mb->vlan_tci_outer = 0;
 123         }
 124 #endif
 125         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 126                    mb->vlan_tci, mb->vlan_tci_outer);
 127 }
 128
 129 /* Translate the rx descriptor status to pkt flags */
 130 static inline uint64_t
 131 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 132 {
 133         uint64_t flags;
 134
 135         /* Check if RSS_HASH */
 136         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 137                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 138                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 139
 140         /* Check if FDIR Match */
 141         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 142                                                         PKT_RX_FDIR : 0);
 143
 144         return flags;
 145 }
 146
 147 static inline uint64_t
 148 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 149 {
 150         uint64_t flags = 0;
 151         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 152
 153 #define I40E_RX_ERR_BITS 0x3f
 154         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 155                 return flags;
 156         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 157                 flags |= PKT_RX_IP_CKSUM_BAD;
 158         else
 159                 flags |= PKT_RX_IP_CKSUM_GOOD;
 160
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 162                 flags |= PKT_RX_L4_CKSUM_BAD;
 163         else
 164                 flags |= PKT_RX_L4_CKSUM_GOOD;
 165
 166         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 167                 flags |= PKT_RX_EIP_CKSUM_BAD;
 168
 169         return flags;
 170 }
 171
 172 /* Function to check and set the ieee1588 timesync index and get the
 173  * appropriate flags.
 174  */
 175 #ifdef RTE_LIBRTE_IEEE1588
 176 static inline uint64_t
 177 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 178 {
 179         uint64_t pkt_flags = 0;
 180         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 181                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 182                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 183
 184         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 185                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 186                 pkt_flags = PKT_RX_IEEE1588_PTP;
 187         if (tsyn & 0x04) {
 188                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 189                 mb->timesync = tsyn & 0x03;
 190         }
 191
 192         return pkt_flags;
 193 }
 194 #endif
 195
 196 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 197 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 198 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 199 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 200 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 201
 202 static inline uint64_t
 203 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 204 {
 205         uint64_t flags = 0;
 206 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 207         uint16_t flexbh, flexbl;
 208
 209         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 210                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 211                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 212         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 213                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 214                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 215
 216
 217         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 218                 mb->hash.fdir.hi =
 219                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 220                 flags |= PKT_RX_FDIR_ID;
 221         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 222                 mb->hash.fdir.hi =
 223                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 224                 flags |= PKT_RX_FDIR_FLX;
 225         }
 226         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 227                 mb->hash.fdir.lo =
 228                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 229                 flags |= PKT_RX_FDIR_FLX;
 230         }
 231 #else
 232         mb->hash.fdir.hi =
 233                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 234         flags |= PKT_RX_FDIR_ID;
 235 #endif
 236         return flags;
 237 }
 238
 239 static inline void
 240 i40e_parse_tunneling_params(uint64_t ol_flags,
 241                             union i40e_tx_offload tx_offload,
 242                             uint32_t *cd_tunneling)
 243 {
 244         /* EIPT: External (outer) IP header type */
 245         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 246                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 247         else if (ol_flags & PKT_TX_OUTER_IPV4)
 248                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 249         else if (ol_flags & PKT_TX_OUTER_IPV6)
 250                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 251
 252         /* EIPLEN: External (outer) IP header length, in DWords */
 253         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 254                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 255
 256         /* L4TUNT: L4 Tunneling Type */
 257         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 258         case PKT_TX_TUNNEL_IPIP:
 259                 /* for non UDP / GRE tunneling, set to 00b */
 260                 break;
 261         case PKT_TX_TUNNEL_VXLAN:
 262         case PKT_TX_TUNNEL_GENEVE:
 263                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 264                 break;
 265         case PKT_TX_TUNNEL_GRE:
 266                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 267                 break;
 268         default:
 269                 PMD_TX_LOG(ERR, "Tunnel type not supported\n");
 270                 return;
 271         }
 272
 273         /* L4TUNLEN: L4 Tunneling Length, in Words
 274          *
 275          * We depend on app to set rte_mbuf.l2_len correctly.
 276          * For IP in GRE it should be set to the length of the GRE
 277          * header;
 278          * for MAC in GRE or MAC in UDP it should be set to the length
 279          * of the GRE or UDP headers plus the inner MAC up to including
 280          * its last Ethertype.
 281          */
 282         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 283                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 284 }
 285
 286 static inline void
 287 i40e_txd_enable_checksum(uint64_t ol_flags,
 288                         uint32_t *td_cmd,
 289                         uint32_t *td_offset,
 290                         union i40e_tx_offload tx_offload)
 291 {
 292         /* Set MACLEN */
 293         if (ol_flags & PKT_TX_TUNNEL_MASK)
 294                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 295                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 296         else
 297                 *td_offset |= (tx_offload.l2_len >> 1)
 298                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 299
 300         /* Enable L3 checksum offloads */
 301         if (ol_flags & PKT_TX_IP_CKSUM) {
 302                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 303                 *td_offset |= (tx_offload.l3_len >> 2)
 304                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 305         } else if (ol_flags & PKT_TX_IPV4) {
 306                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 307                 *td_offset |= (tx_offload.l3_len >> 2)
 308                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 309         } else if (ol_flags & PKT_TX_IPV6) {
 310                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 311                 *td_offset |= (tx_offload.l3_len >> 2)
 312                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 313         }
 314
 315         if (ol_flags & PKT_TX_TCP_SEG) {
 316                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 317                 *td_offset |= (tx_offload.l4_len >> 2)
 318                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 319                 return;
 320         }
 321
 322         /* Enable L4 checksum offloads */
 323         switch (ol_flags & PKT_TX_L4_MASK) {
 324         case PKT_TX_TCP_CKSUM:
 325                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 326                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 327                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 328                 break;
 329         case PKT_TX_SCTP_CKSUM:
 330                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 331                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 332                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 333                 break;
 334         case PKT_TX_UDP_CKSUM:
 335                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 336                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 337                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 338                 break;
 339         default:
 340                 break;
 341         }
 342 }
 343
 344 /* Construct the tx flags */
 345 static inline uint64_t
 346 i40e_build_ctob(uint32_t td_cmd,
 347                 uint32_t td_offset,
 348                 unsigned int size,
 349                 uint32_t td_tag)
 350 {
 351         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 352                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 353                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 354                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 355                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 356 }
 357
 358 static inline int
 359 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 360 {
 361         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 362         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 363         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 364         uint16_t nb_tx_desc = txq->nb_tx_desc;
 365         uint16_t desc_to_clean_to;
 366         uint16_t nb_tx_to_clean;
 367
 368         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 369         if (desc_to_clean_to >= nb_tx_desc)
 370                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 371
 372         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 373         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 374                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 375                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 376                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 377                         "(port=%d queue=%d)", desc_to_clean_to,
 378                                 txq->port_id, txq->queue_id);
 379                 return -1;
 380         }
 381
 382         if (last_desc_cleaned > desc_to_clean_to)
 383                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 384                                                         desc_to_clean_to);
 385         else
 386                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 387                                         last_desc_cleaned);
 388
 389         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 390
 391         txq->last_desc_cleaned = desc_to_clean_to;
 392         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 393
 394         return 0;
 395 }
 396
 397 static inline int
 398 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 399 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 400 #else
 401 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 402 #endif
 403 {
 404         int ret = 0;
 405
 406 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 407         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 408                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 409                              "rxq->rx_free_thresh=%d, "
 410                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 411                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 412                 ret = -EINVAL;
 413         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 414                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 415                              "rxq->rx_free_thresh=%d, "
 416                              "rxq->nb_rx_desc=%d",
 417                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 418                 ret = -EINVAL;
 419         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 420                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 421                              "rxq->nb_rx_desc=%d, "
 422                              "rxq->rx_free_thresh=%d",
 423                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 424                 ret = -EINVAL;
 425         }
 426 #else
 427         ret = -EINVAL;
 428 #endif
 429
 430         return ret;
 431 }
 432
 433 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 434 #define I40E_LOOK_AHEAD 8
 435 #if (I40E_LOOK_AHEAD != 8)
 436 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 437 #endif
 438 static inline int
 439 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 440 {
 441         volatile union i40e_rx_desc *rxdp;
 442         struct i40e_rx_entry *rxep;
 443         struct rte_mbuf *mb;
 444         uint16_t pkt_len;
 445         uint64_t qword1;
 446         uint32_t rx_status;
 447         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 448         int32_t i, j, nb_rx = 0;
 449         uint64_t pkt_flags;
 450
 451         rxdp = &rxq->rx_ring[rxq->rx_tail];
 452         rxep = &rxq->sw_ring[rxq->rx_tail];
 453
 454         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 455         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 456                                 I40E_RXD_QW1_STATUS_SHIFT;
 457
 458         /* Make sure there is at least 1 packet to receive */
 459         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 460                 return 0;
 461
 462         /**
 463          * Scan LOOK_AHEAD descriptors at a time to determine which
 464          * descriptors reference packets that are ready to be received.
 465          */
 466         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 467                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 468                 /* Read desc statuses backwards to avoid race condition */
 469                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 470                         qword1 = rte_le_to_cpu_64(\
 471                                 rxdp[j].wb.qword1.status_error_len);
 472                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 473                                         I40E_RXD_QW1_STATUS_SHIFT;
 474                 }
 475
 476                 rte_smp_rmb();
 477
 478                 /* Compute how many status bits were set */
 479                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 480                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 481
 482                 nb_rx += nb_dd;
 483
 484                 /* Translate descriptor info to mbuf parameters */
 485                 for (j = 0; j < nb_dd; j++) {
 486                         mb = rxep[j].mbuf;
 487                         qword1 = rte_le_to_cpu_64(\
 488                                 rxdp[j].wb.qword1.status_error_len);
 489                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 490                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 491                         mb->data_len = pkt_len;
 492                         mb->pkt_len = pkt_len;
 493                         mb->ol_flags = 0;
 494                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 495                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 496                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 497                         mb->packet_type =
 498                                 i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 499                                                 I40E_RXD_QW1_PTYPE_MASK) >>
 500                                                 I40E_RXD_QW1_PTYPE_SHIFT));
 501                         if (pkt_flags & PKT_RX_RSS_HASH)
 502                                 mb->hash.rss = rte_le_to_cpu_32(\
 503                                         rxdp[j].wb.qword0.hi_dword.rss);
 504                         if (pkt_flags & PKT_RX_FDIR)
 505                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 506
 507 #ifdef RTE_LIBRTE_IEEE1588
 508                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 509 #endif
 510                         mb->ol_flags |= pkt_flags;
 511
 512                 }
 513
 514                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 515                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 516
 517                 if (nb_dd != I40E_LOOK_AHEAD)
 518                         break;
 519         }
 520
 521         /* Clear software ring entries */
 522         for (i = 0; i < nb_rx; i++)
 523                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 524
 525         return nb_rx;
 526 }
 527
 528 static inline uint16_t
 529 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 530                         struct rte_mbuf **rx_pkts,
 531                         uint16_t nb_pkts)
 532 {
 533         uint16_t i;
 534         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 535
 536         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 537
 538         for (i = 0; i < nb_pkts; i++)
 539                 rx_pkts[i] = stage[i];
 540
 541         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 542         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 543
 544         return nb_pkts;
 545 }
 546
 547 static inline int
 548 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 549 {
 550         volatile union i40e_rx_desc *rxdp;
 551         struct i40e_rx_entry *rxep;
 552         struct rte_mbuf *mb;
 553         uint16_t alloc_idx, i;
 554         uint64_t dma_addr;
 555         int diag;
 556
 557         /* Allocate buffers in bulk */
 558         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 559                                 (rxq->rx_free_thresh - 1));
 560         rxep = &(rxq->sw_ring[alloc_idx]);
 561         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 562                                         rxq->rx_free_thresh);
 563         if (unlikely(diag != 0)) {
 564                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 565                 return -ENOMEM;
 566         }
 567
 568         rxdp = &rxq->rx_ring[alloc_idx];
 569         for (i = 0; i < rxq->rx_free_thresh; i++) {
 570                 if (likely(i < (rxq->rx_free_thresh - 1)))
 571                         /* Prefetch next mbuf */
 572                         rte_prefetch0(rxep[i + 1].mbuf);
 573
 574                 mb = rxep[i].mbuf;
 575                 rte_mbuf_refcnt_set(mb, 1);
 576                 mb->next = NULL;
 577                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 578                 mb->nb_segs = 1;
 579                 mb->port = rxq->port_id;
 580                 dma_addr = rte_cpu_to_le_64(\
 581                         rte_mbuf_data_dma_addr_default(mb));
 582                 rxdp[i].read.hdr_addr = 0;
 583                 rxdp[i].read.pkt_addr = dma_addr;
 584         }
 585
 586         /* Update rx tail regsiter */
 587         rte_wmb();
 588         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 589
 590         rxq->rx_free_trigger =
 591                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 592         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 593                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 594
 595         return 0;
 596 }
 597
 598 static inline uint16_t
 599 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 600 {
 601         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 602         uint16_t nb_rx = 0;
 603
 604         if (!nb_pkts)
 605                 return 0;
 606
 607         if (rxq->rx_nb_avail)
 608                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 609
 610         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 611         rxq->rx_next_avail = 0;
 612         rxq->rx_nb_avail = nb_rx;
 613         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 614
 615         if (rxq->rx_tail > rxq->rx_free_trigger) {
 616                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 617                         uint16_t i, j;
 618
 619                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 620                                    "port_id=%u, queue_id=%u",
 621                                    rxq->port_id, rxq->queue_id);
 622                         rxq->rx_nb_avail = 0;
 623                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 624                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 625                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 626
 627                         return 0;
 628                 }
 629         }
 630
 631         if (rxq->rx_tail >= rxq->nb_rx_desc)
 632                 rxq->rx_tail = 0;
 633
 634         if (rxq->rx_nb_avail)
 635                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 636
 637         return 0;
 638 }
 639
 640 static uint16_t
 641 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 642                           struct rte_mbuf **rx_pkts,
 643                           uint16_t nb_pkts)
 644 {
 645         uint16_t nb_rx = 0, n, count;
 646
 647         if (unlikely(nb_pkts == 0))
 648                 return 0;
 649
 650         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 651                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 652
 653         while (nb_pkts) {
 654                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 655                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 656                 nb_rx = (uint16_t)(nb_rx + count);
 657                 nb_pkts = (uint16_t)(nb_pkts - count);
 658                 if (count < n)
 659                         break;
 660         }
 661
 662         return nb_rx;
 663 }
 664 #else
 665 static uint16_t
 666 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 667                           struct rte_mbuf __rte_unused **rx_pkts,
 668                           uint16_t __rte_unused nb_pkts)
 669 {
 670         return 0;
 671 }
 672 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 673
 674 uint16_t
 675 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 676 {
 677         struct i40e_rx_queue *rxq;
 678         volatile union i40e_rx_desc *rx_ring;
 679         volatile union i40e_rx_desc *rxdp;
 680         union i40e_rx_desc rxd;
 681         struct i40e_rx_entry *sw_ring;
 682         struct i40e_rx_entry *rxe;
 683         struct rte_mbuf *rxm;
 684         struct rte_mbuf *nmb;
 685         uint16_t nb_rx;
 686         uint32_t rx_status;
 687         uint64_t qword1;
 688         uint16_t rx_packet_len;
 689         uint16_t rx_id, nb_hold;
 690         uint64_t dma_addr;
 691         uint64_t pkt_flags;
 692
 693         nb_rx = 0;
 694         nb_hold = 0;
 695         rxq = rx_queue;
 696         rx_id = rxq->rx_tail;
 697         rx_ring = rxq->rx_ring;
 698         sw_ring = rxq->sw_ring;
 699
 700         while (nb_rx < nb_pkts) {
 701                 rxdp = &rx_ring[rx_id];
 702                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 703                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 704                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 705
 706                 /* Check the DD bit first */
 707                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 708                         break;
 709
 710                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 711                 if (unlikely(!nmb))
 712                         break;
 713                 rxd = *rxdp;
 714
 715                 nb_hold++;
 716                 rxe = &sw_ring[rx_id];
 717                 rx_id++;
 718                 if (unlikely(rx_id == rxq->nb_rx_desc))
 719                         rx_id = 0;
 720
 721                 /* Prefetch next mbuf */
 722                 rte_prefetch0(sw_ring[rx_id].mbuf);
 723
 724                 /**
 725                  * When next RX descriptor is on a cache line boundary,
 726                  * prefetch the next 4 RX descriptors and next 8 pointers
 727                  * to mbufs.
 728                  */
 729                 if ((rx_id & 0x3) == 0) {
 730                         rte_prefetch0(&rx_ring[rx_id]);
 731                         rte_prefetch0(&sw_ring[rx_id]);
 732                 }
 733                 rxm = rxe->mbuf;
 734                 rxe->mbuf = nmb;
 735                 dma_addr =
 736                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 737                 rxdp->read.hdr_addr = 0;
 738                 rxdp->read.pkt_addr = dma_addr;
 739
 740                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 741                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 742
 743                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 744                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 745                 rxm->nb_segs = 1;
 746                 rxm->next = NULL;
 747                 rxm->pkt_len = rx_packet_len;
 748                 rxm->data_len = rx_packet_len;
 749                 rxm->port = rxq->port_id;
 750                 rxm->ol_flags = 0;
 751                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 752                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 753                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 754                 rxm->packet_type =
 755                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 756                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 757                 if (pkt_flags & PKT_RX_RSS_HASH)
 758                         rxm->hash.rss =
 759                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 760                 if (pkt_flags & PKT_RX_FDIR)
 761                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 762
 763 #ifdef RTE_LIBRTE_IEEE1588
 764                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 765 #endif
 766                 rxm->ol_flags |= pkt_flags;
 767
 768                 rx_pkts[nb_rx++] = rxm;
 769         }
 770         rxq->rx_tail = rx_id;
 771
 772         /**
 773          * If the number of free RX descriptors is greater than the RX free
 774          * threshold of the queue, advance the receive tail register of queue.
 775          * Update that register with the value of the last processed RX
 776          * descriptor minus 1.
 777          */
 778         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 779         if (nb_hold > rxq->rx_free_thresh) {
 780                 rx_id = (uint16_t) ((rx_id == 0) ?
 781                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 782                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 783                 nb_hold = 0;
 784         }
 785         rxq->nb_rx_hold = nb_hold;
 786
 787         return nb_rx;
 788 }
 789
 790 uint16_t
 791 i40e_recv_scattered_pkts(void *rx_queue,
 792                          struct rte_mbuf **rx_pkts,
 793                          uint16_t nb_pkts)
 794 {
 795         struct i40e_rx_queue *rxq = rx_queue;
 796         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 797         volatile union i40e_rx_desc *rxdp;
 798         union i40e_rx_desc rxd;
 799         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 800         struct i40e_rx_entry *rxe;
 801         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 802         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 803         struct rte_mbuf *nmb, *rxm;
 804         uint16_t rx_id = rxq->rx_tail;
 805         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 806         uint32_t rx_status;
 807         uint64_t qword1;
 808         uint64_t dma_addr;
 809         uint64_t pkt_flags;
 810
 811         while (nb_rx < nb_pkts) {
 812                 rxdp = &rx_ring[rx_id];
 813                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 814                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 815                                         I40E_RXD_QW1_STATUS_SHIFT;
 816
 817                 /* Check the DD bit */
 818                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 819                         break;
 820
 821                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 822                 if (unlikely(!nmb))
 823                         break;
 824                 rxd = *rxdp;
 825                 nb_hold++;
 826                 rxe = &sw_ring[rx_id];
 827                 rx_id++;
 828                 if (rx_id == rxq->nb_rx_desc)
 829                         rx_id = 0;
 830
 831                 /* Prefetch next mbuf */
 832                 rte_prefetch0(sw_ring[rx_id].mbuf);
 833
 834                 /**
 835                  * When next RX descriptor is on a cache line boundary,
 836                  * prefetch the next 4 RX descriptors and next 8 pointers
 837                  * to mbufs.
 838                  */
 839                 if ((rx_id & 0x3) == 0) {
 840                         rte_prefetch0(&rx_ring[rx_id]);
 841                         rte_prefetch0(&sw_ring[rx_id]);
 842                 }
 843
 844                 rxm = rxe->mbuf;
 845                 rxe->mbuf = nmb;
 846                 dma_addr =
 847                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 848
 849                 /* Set data buffer address and data length of the mbuf */
 850                 rxdp->read.hdr_addr = 0;
 851                 rxdp->read.pkt_addr = dma_addr;
 852                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 853                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 854                 rxm->data_len = rx_packet_len;
 855                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 856
 857                 /**
 858                  * If this is the first buffer of the received packet, set the
 859                  * pointer to the first mbuf of the packet and initialize its
 860                  * context. Otherwise, update the total length and the number
 861                  * of segments of the current scattered packet, and update the
 862                  * pointer to the last mbuf of the current packet.
 863                  */
 864                 if (!first_seg) {
 865                         first_seg = rxm;
 866                         first_seg->nb_segs = 1;
 867                         first_seg->pkt_len = rx_packet_len;
 868                 } else {
 869                         first_seg->pkt_len =
 870                                 (uint16_t)(first_seg->pkt_len +
 871                                                 rx_packet_len);
 872                         first_seg->nb_segs++;
 873                         last_seg->next = rxm;
 874                 }
 875
 876                 /**
 877                  * If this is not the last buffer of the received packet,
 878                  * update the pointer to the last mbuf of the current scattered
 879                  * packet and continue to parse the RX ring.
 880                  */
 881                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 882                         last_seg = rxm;
 883                         continue;
 884                 }
 885
 886                 /**
 887                  * This is the last buffer of the received packet. If the CRC
 888                  * is not stripped by the hardware:
 889                  *  - Subtract the CRC length from the total packet length.
 890                  *  - If the last buffer only contains the whole CRC or a part
 891                  *  of it, free the mbuf associated to the last buffer. If part
 892                  *  of the CRC is also contained in the previous mbuf, subtract
 893                  *  the length of that CRC part from the data length of the
 894                  *  previous mbuf.
 895                  */
 896                 rxm->next = NULL;
 897                 if (unlikely(rxq->crc_len > 0)) {
 898                         first_seg->pkt_len -= ETHER_CRC_LEN;
 899                         if (rx_packet_len <= ETHER_CRC_LEN) {
 900                                 rte_pktmbuf_free_seg(rxm);
 901                                 first_seg->nb_segs--;
 902                                 last_seg->data_len =
 903                                         (uint16_t)(last_seg->data_len -
 904                                         (ETHER_CRC_LEN - rx_packet_len));
 905                                 last_seg->next = NULL;
 906                         } else
 907                                 rxm->data_len = (uint16_t)(rx_packet_len -
 908                                                                 ETHER_CRC_LEN);
 909                 }
 910
 911                 first_seg->port = rxq->port_id;
 912                 first_seg->ol_flags = 0;
 913                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 914                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 915                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 916                 first_seg->packet_type =
 917                         i40e_rxd_pkt_type_mapping((uint8_t)((qword1 &
 918                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT));
 919                 if (pkt_flags & PKT_RX_RSS_HASH)
 920                         first_seg->hash.rss =
 921                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 922                 if (pkt_flags & PKT_RX_FDIR)
 923                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 924
 925 #ifdef RTE_LIBRTE_IEEE1588
 926                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 927 #endif
 928                 first_seg->ol_flags |= pkt_flags;
 929
 930                 /* Prefetch data of first segment, if configured to do so. */
 931                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 932                         first_seg->data_off));
 933                 rx_pkts[nb_rx++] = first_seg;
 934                 first_seg = NULL;
 935         }
 936
 937         /* Record index of the next RX descriptor to probe. */
 938         rxq->rx_tail = rx_id;
 939         rxq->pkt_first_seg = first_seg;
 940         rxq->pkt_last_seg = last_seg;
 941
 942         /**
 943          * If the number of free RX descriptors is greater than the RX free
 944          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 945          * register. Update the RDT with the value of the last processed RX
 946          * descriptor minus 1, to guarantee that the RDT register is never
 947          * equal to the RDH register, which creates a "full" ring situtation
 948          * from the hardware point of view.
 949          */
 950         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 951         if (nb_hold > rxq->rx_free_thresh) {
 952                 rx_id = (uint16_t)(rx_id == 0 ?
 953                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 954                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 955                 nb_hold = 0;
 956         }
 957         rxq->nb_rx_hold = nb_hold;
 958
 959         return nb_rx;
 960 }
 961
 962 /* Check if the context descriptor is needed for TX offloading */
 963 static inline uint16_t
 964 i40e_calc_context_desc(uint64_t flags)
 965 {
 966         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 967                 PKT_TX_TCP_SEG |
 968                 PKT_TX_QINQ_PKT |
 969                 PKT_TX_TUNNEL_MASK;
 970
 971 #ifdef RTE_LIBRTE_IEEE1588
 972         mask |= PKT_TX_IEEE1588_TMST;
 973 #endif
 974
 975         return (flags & mask) ? 1 : 0;
 976 }
 977
 978 /* set i40e TSO context descriptor */
 979 static inline uint64_t
 980 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 981 {
 982         uint64_t ctx_desc = 0;
 983         uint32_t cd_cmd, hdr_len, cd_tso_len;
 984
 985         if (!tx_offload.l4_len) {
 986                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 987                 return ctx_desc;
 988         }
 989
 990         /**
 991          * in case of non tunneling packet, the outer_l2_len and
 992          * outer_l3_len must be 0.
 993          */
 994         hdr_len = tx_offload.outer_l2_len +
 995                 tx_offload.outer_l3_len +
 996                 tx_offload.l2_len +
 997                 tx_offload.l3_len +
 998                 tx_offload.l4_len;
 999
1000         cd_cmd = I40E_TX_CTX_DESC_TSO;
1001         cd_tso_len = mbuf->pkt_len - hdr_len;
1002         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1003                 ((uint64_t)cd_tso_len <<
1004                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1005                 ((uint64_t)mbuf->tso_segsz <<
1006                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1007
1008         return ctx_desc;
1009 }
1010
1011 uint16_t
1012 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1013 {
1014         struct i40e_tx_queue *txq;
1015         struct i40e_tx_entry *sw_ring;
1016         struct i40e_tx_entry *txe, *txn;
1017         volatile struct i40e_tx_desc *txd;
1018         volatile struct i40e_tx_desc *txr;
1019         struct rte_mbuf *tx_pkt;
1020         struct rte_mbuf *m_seg;
1021         uint32_t cd_tunneling_params;
1022         uint16_t tx_id;
1023         uint16_t nb_tx;
1024         uint32_t td_cmd;
1025         uint32_t td_offset;
1026         uint32_t tx_flags;
1027         uint32_t td_tag;
1028         uint64_t ol_flags;
1029         uint16_t nb_used;
1030         uint16_t nb_ctx;
1031         uint16_t tx_last;
1032         uint16_t slen;
1033         uint64_t buf_dma_addr;
1034         union i40e_tx_offload tx_offload = {0};
1035
1036         txq = tx_queue;
1037         sw_ring = txq->sw_ring;
1038         txr = txq->tx_ring;
1039         tx_id = txq->tx_tail;
1040         txe = &sw_ring[tx_id];
1041
1042         /* Check if the descriptor ring needs to be cleaned. */
1043         if (txq->nb_tx_free < txq->tx_free_thresh)
1044                 i40e_xmit_cleanup(txq);
1045
1046         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1047                 td_cmd = 0;
1048                 td_tag = 0;
1049                 td_offset = 0;
1050                 tx_flags = 0;
1051
1052                 tx_pkt = *tx_pkts++;
1053                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1054
1055                 ol_flags = tx_pkt->ol_flags;
1056                 tx_offload.l2_len = tx_pkt->l2_len;
1057                 tx_offload.l3_len = tx_pkt->l3_len;
1058                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1059                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1060                 tx_offload.l4_len = tx_pkt->l4_len;
1061                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1062
1063                 /* Calculate the number of context descriptors needed. */
1064                 nb_ctx = i40e_calc_context_desc(ol_flags);
1065
1066                 /**
1067                  * The number of descriptors that must be allocated for
1068                  * a packet equals to the number of the segments of that
1069                  * packet plus 1 context descriptor if needed.
1070                  */
1071                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1072                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1073
1074                 /* Circular ring */
1075                 if (tx_last >= txq->nb_tx_desc)
1076                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1077
1078                 if (nb_used > txq->nb_tx_free) {
1079                         if (i40e_xmit_cleanup(txq) != 0) {
1080                                 if (nb_tx == 0)
1081                                         return 0;
1082                                 goto end_of_tx;
1083                         }
1084                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1085                                 while (nb_used > txq->nb_tx_free) {
1086                                         if (i40e_xmit_cleanup(txq) != 0) {
1087                                                 if (nb_tx == 0)
1088                                                         return 0;
1089                                                 goto end_of_tx;
1090                                         }
1091                                 }
1092                         }
1093                 }
1094
1095                 /* Descriptor based VLAN insertion */
1096                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1097                         tx_flags |= tx_pkt->vlan_tci <<
1098                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1099                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1100                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1101                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1102                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1103                 }
1104
1105                 /* Always enable CRC offload insertion */
1106                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1107
1108                 /* Fill in tunneling parameters if necessary */
1109                 cd_tunneling_params = 0;
1110                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1111                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1112                                                     &cd_tunneling_params);
1113                 /* Enable checksum offloading */
1114                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1115                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1116                                                  &td_offset, tx_offload);
1117
1118                 if (nb_ctx) {
1119                         /* Setup TX context descriptor if required */
1120                         volatile struct i40e_tx_context_desc *ctx_txd =
1121                                 (volatile struct i40e_tx_context_desc *)\
1122                                                         &txr[tx_id];
1123                         uint16_t cd_l2tag2 = 0;
1124                         uint64_t cd_type_cmd_tso_mss =
1125                                 I40E_TX_DESC_DTYPE_CONTEXT;
1126
1127                         txn = &sw_ring[txe->next_id];
1128                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1129                         if (txe->mbuf != NULL) {
1130                                 rte_pktmbuf_free_seg(txe->mbuf);
1131                                 txe->mbuf = NULL;
1132                         }
1133
1134                         /* TSO enabled means no timestamp */
1135                         if (ol_flags & PKT_TX_TCP_SEG)
1136                                 cd_type_cmd_tso_mss |=
1137                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1138                         else {
1139 #ifdef RTE_LIBRTE_IEEE1588
1140                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1141                                         cd_type_cmd_tso_mss |=
1142                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1143                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1144 #endif
1145                         }
1146
1147                         ctx_txd->tunneling_params =
1148                                 rte_cpu_to_le_32(cd_tunneling_params);
1149                         if (ol_flags & PKT_TX_QINQ_PKT) {
1150                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1151                                 cd_type_cmd_tso_mss |=
1152                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1153                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1154                         }
1155                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1156                         ctx_txd->type_cmd_tso_mss =
1157                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1158
1159                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1160                                 "tunneling_params: %#x;\n"
1161                                 "l2tag2: %#hx;\n"
1162                                 "rsvd: %#hx;\n"
1163                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1164                                 tx_pkt, tx_id,
1165                                 ctx_txd->tunneling_params,
1166                                 ctx_txd->l2tag2,
1167                                 ctx_txd->rsvd,
1168                                 ctx_txd->type_cmd_tso_mss);
1169
1170                         txe->last_id = tx_last;
1171                         tx_id = txe->next_id;
1172                         txe = txn;
1173                 }
1174
1175                 m_seg = tx_pkt;
1176                 do {
1177                         txd = &txr[tx_id];
1178                         txn = &sw_ring[txe->next_id];
1179
1180                         if (txe->mbuf)
1181                                 rte_pktmbuf_free_seg(txe->mbuf);
1182                         txe->mbuf = m_seg;
1183
1184                         /* Setup TX Descriptor */
1185                         slen = m_seg->data_len;
1186                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1187
1188                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1189                                 "buf_dma_addr: %#"PRIx64";\n"
1190                                 "td_cmd: %#x;\n"
1191                                 "td_offset: %#x;\n"
1192                                 "td_len: %u;\n"
1193                                 "td_tag: %#x;\n",
1194                                 tx_pkt, tx_id, buf_dma_addr,
1195                                 td_cmd, td_offset, slen, td_tag);
1196
1197                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1198                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1199                                                 td_offset, slen, td_tag);
1200                         txe->last_id = tx_last;
1201                         tx_id = txe->next_id;
1202                         txe = txn;
1203                         m_seg = m_seg->next;
1204                 } while (m_seg != NULL);
1205
1206                 /* The last packet data descriptor needs End Of Packet (EOP) */
1207                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1208                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1209                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1210
1211                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1212                         PMD_TX_FREE_LOG(DEBUG,
1213                                         "Setting RS bit on TXD id="
1214                                         "%4u (port=%d queue=%d)",
1215                                         tx_last, txq->port_id, txq->queue_id);
1216
1217                         td_cmd |= I40E_TX_DESC_CMD_RS;
1218
1219                         /* Update txq RS bit counters */
1220                         txq->nb_tx_used = 0;
1221                 }
1222
1223                 txd->cmd_type_offset_bsz |=
1224                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1225                                         I40E_TXD_QW1_CMD_SHIFT);
1226         }
1227
1228 end_of_tx:
1229         rte_wmb();
1230
1231         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1232                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1233                    (unsigned) tx_id, (unsigned) nb_tx);
1234
1235         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1236         txq->tx_tail = tx_id;
1237
1238         return nb_tx;
1239 }
1240
1241 static inline int __attribute__((always_inline))
1242 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1243 {
1244         struct i40e_tx_entry *txep;
1245         uint16_t i;
1246
1247         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1248                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1249                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1250                 return 0;
1251
1252         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1253
1254         for (i = 0; i < txq->tx_rs_thresh; i++)
1255                 rte_prefetch0((txep + i)->mbuf);
1256
1257         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1258                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1259                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1260                         txep->mbuf = NULL;
1261                 }
1262         } else {
1263                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1264                         rte_pktmbuf_free_seg(txep->mbuf);
1265                         txep->mbuf = NULL;
1266                 }
1267         }
1268
1269         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1270         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1271         if (txq->tx_next_dd >= txq->nb_tx_desc)
1272                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1273
1274         return txq->tx_rs_thresh;
1275 }
1276
1277 /* Populate 4 descriptors with data from 4 mbufs */
1278 static inline void
1279 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1280 {
1281         uint64_t dma_addr;
1282         uint32_t i;
1283
1284         for (i = 0; i < 4; i++, txdp++, pkts++) {
1285                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1286                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1287                 txdp->cmd_type_offset_bsz =
1288                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1289                                         (*pkts)->data_len, 0);
1290         }
1291 }
1292
1293 /* Populate 1 descriptor with data from 1 mbuf */
1294 static inline void
1295 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1296 {
1297         uint64_t dma_addr;
1298
1299         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1300         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1301         txdp->cmd_type_offset_bsz =
1302                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1303                                 (*pkts)->data_len, 0);
1304 }
1305
1306 /* Fill hardware descriptor ring with mbuf data */
1307 static inline void
1308 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1309                      struct rte_mbuf **pkts,
1310                      uint16_t nb_pkts)
1311 {
1312         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1313         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1314         const int N_PER_LOOP = 4;
1315         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1316         int mainpart, leftover;
1317         int i, j;
1318
1319         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1320         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1321         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1322                 for (j = 0; j < N_PER_LOOP; ++j) {
1323                         (txep + i + j)->mbuf = *(pkts + i + j);
1324                 }
1325                 tx4(txdp + i, pkts + i);
1326         }
1327         if (unlikely(leftover > 0)) {
1328                 for (i = 0; i < leftover; ++i) {
1329                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1330                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1331                 }
1332         }
1333 }
1334
1335 static inline uint16_t
1336 tx_xmit_pkts(struct i40e_tx_queue *txq,
1337              struct rte_mbuf **tx_pkts,
1338              uint16_t nb_pkts)
1339 {
1340         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1341         uint16_t n = 0;
1342
1343         /**
1344          * Begin scanning the H/W ring for done descriptors when the number
1345          * of available descriptors drops below tx_free_thresh. For each done
1346          * descriptor, free the associated buffer.
1347          */
1348         if (txq->nb_tx_free < txq->tx_free_thresh)
1349                 i40e_tx_free_bufs(txq);
1350
1351         /* Use available descriptor only */
1352         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1353         if (unlikely(!nb_pkts))
1354                 return 0;
1355
1356         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1357         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1358                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1359                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1360                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1361                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1362                                                 I40E_TXD_QW1_CMD_SHIFT);
1363                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1364                 txq->tx_tail = 0;
1365         }
1366
1367         /* Fill hardware descriptor ring with mbuf data */
1368         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1369         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1370
1371         /* Determin if RS bit needs to be set */
1372         if (txq->tx_tail > txq->tx_next_rs) {
1373                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1374                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1375                                                 I40E_TXD_QW1_CMD_SHIFT);
1376                 txq->tx_next_rs =
1377                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1378                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1379                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1380         }
1381
1382         if (txq->tx_tail >= txq->nb_tx_desc)
1383                 txq->tx_tail = 0;
1384
1385         /* Update the tx tail register */
1386         rte_wmb();
1387         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1388
1389         return nb_pkts;
1390 }
1391
1392 static uint16_t
1393 i40e_xmit_pkts_simple(void *tx_queue,
1394                       struct rte_mbuf **tx_pkts,
1395                       uint16_t nb_pkts)
1396 {
1397         uint16_t nb_tx = 0;
1398
1399         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1400                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1401                                                 tx_pkts, nb_pkts);
1402
1403         while (nb_pkts) {
1404                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1405                                                 I40E_TX_MAX_BURST);
1406
1407                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1408                                                 &tx_pkts[nb_tx], num);
1409                 nb_tx = (uint16_t)(nb_tx + ret);
1410                 nb_pkts = (uint16_t)(nb_pkts - ret);
1411                 if (ret < num)
1412                         break;
1413         }
1414
1415         return nb_tx;
1416 }
1417
1418 /*********************************************************************
1419  *
1420  *  TX prep functions
1421  *
1422  **********************************************************************/
1423 uint16_t
1424 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1425                 uint16_t nb_pkts)
1426 {
1427         int i, ret;
1428         uint64_t ol_flags;
1429         struct rte_mbuf *m;
1430
1431         for (i = 0; i < nb_pkts; i++) {
1432                 m = tx_pkts[i];
1433                 ol_flags = m->ol_flags;
1434
1435                 /**
1436                  * m->nb_segs is uint8_t, so nb_segs is always less than
1437                  * I40E_TX_MAX_SEG.
1438                  * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1439                  */
1440                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1441                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1442                                 rte_errno = -EINVAL;
1443                                 return i;
1444                         }
1445                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1446                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1447                         /* MSS outside the range (256B - 9674B) are considered
1448                          * malicious
1449                          */
1450                         rte_errno = -EINVAL;
1451                         return i;
1452                 }
1453
1454                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1455                         rte_errno = -ENOTSUP;
1456                         return i;
1457                 }
1458
1459 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1460                 ret = rte_validate_tx_offload(m);
1461                 if (ret != 0) {
1462                         rte_errno = ret;
1463                         return i;
1464                 }
1465 #endif
1466                 ret = rte_net_intel_cksum_prepare(m);
1467                 if (ret != 0) {
1468                         rte_errno = ret;
1469                         return i;
1470                 }
1471         }
1472         return i;
1473 }
1474
1475 /*
1476  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1477  * application used, which assume having sequential ones. But from driver's
1478  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1479  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1480  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1481  * use queue_idx from 0 to 95 to access queues, while real queue would be
1482  * different. This function will do a queue mapping to find VSI the queue
1483  * belongs to.
1484  */
1485 static struct i40e_vsi*
1486 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1487 {
1488         /* the queue in MAIN VSI range */
1489         if (queue_idx < pf->main_vsi->nb_qps)
1490                 return pf->main_vsi;
1491
1492         queue_idx -= pf->main_vsi->nb_qps;
1493
1494         /* queue_idx is greater than VMDQ VSIs range */
1495         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1496                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1497                 return NULL;
1498         }
1499
1500         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1501 }
1502
1503 static uint16_t
1504 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1505 {
1506         /* the queue in MAIN VSI range */
1507         if (queue_idx < pf->main_vsi->nb_qps)
1508                 return queue_idx;
1509
1510         /* It's VMDQ queues */
1511         queue_idx -= pf->main_vsi->nb_qps;
1512
1513         if (pf->nb_cfg_vmdq_vsi)
1514                 return queue_idx % pf->vmdq_nb_qps;
1515         else {
1516                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1517                 return (uint16_t)(-1);
1518         }
1519 }
1520
1521 int
1522 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1523 {
1524         struct i40e_rx_queue *rxq;
1525         int err = -1;
1526         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1527
1528         PMD_INIT_FUNC_TRACE();
1529
1530         if (rx_queue_id < dev->data->nb_rx_queues) {
1531                 rxq = dev->data->rx_queues[rx_queue_id];
1532
1533                 err = i40e_alloc_rx_queue_mbufs(rxq);
1534                 if (err) {
1535                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1536                         return err;
1537                 }
1538
1539                 rte_wmb();
1540
1541                 /* Init the RX tail regieter. */
1542                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1543
1544                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1545
1546                 if (err) {
1547                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1548                                     rx_queue_id);
1549
1550                         i40e_rx_queue_release_mbufs(rxq);
1551                         i40e_reset_rx_queue(rxq);
1552                 } else
1553                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1554         }
1555
1556         return err;
1557 }
1558
1559 int
1560 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1561 {
1562         struct i40e_rx_queue *rxq;
1563         int err;
1564         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1565
1566         if (rx_queue_id < dev->data->nb_rx_queues) {
1567                 rxq = dev->data->rx_queues[rx_queue_id];
1568
1569                 /*
1570                 * rx_queue_id is queue id aplication refers to, while
1571                 * rxq->reg_idx is the real queue index.
1572                 */
1573                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1574
1575                 if (err) {
1576                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1577                                     rx_queue_id);
1578                         return err;
1579                 }
1580                 i40e_rx_queue_release_mbufs(rxq);
1581                 i40e_reset_rx_queue(rxq);
1582                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1583         }
1584
1585         return 0;
1586 }
1587
1588 int
1589 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1590 {
1591         int err = -1;
1592         struct i40e_tx_queue *txq;
1593         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1594
1595         PMD_INIT_FUNC_TRACE();
1596
1597         if (tx_queue_id < dev->data->nb_tx_queues) {
1598                 txq = dev->data->tx_queues[tx_queue_id];
1599
1600                 /*
1601                 * tx_queue_id is queue id aplication refers to, while
1602                 * rxq->reg_idx is the real queue index.
1603                 */
1604                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1605                 if (err)
1606                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1607                                     tx_queue_id);
1608                 else
1609                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1610         }
1611
1612         return err;
1613 }
1614
1615 int
1616 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1617 {
1618         struct i40e_tx_queue *txq;
1619         int err;
1620         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1621
1622         if (tx_queue_id < dev->data->nb_tx_queues) {
1623                 txq = dev->data->tx_queues[tx_queue_id];
1624
1625                 /*
1626                 * tx_queue_id is queue id aplication refers to, while
1627                 * txq->reg_idx is the real queue index.
1628                 */
1629                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1630
1631                 if (err) {
1632                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1633                                     tx_queue_id);
1634                         return err;
1635                 }
1636
1637                 i40e_tx_queue_release_mbufs(txq);
1638                 i40e_reset_tx_queue(txq);
1639                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1640         }
1641
1642         return 0;
1643 }
1644
1645 const uint32_t *
1646 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1647 {
1648         static const uint32_t ptypes[] = {
1649                 /* refers to i40e_rxd_pkt_type_mapping() */
1650                 RTE_PTYPE_L2_ETHER,
1651                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1652                 RTE_PTYPE_L2_ETHER_LLDP,
1653                 RTE_PTYPE_L2_ETHER_ARP,
1654                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1655                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1656                 RTE_PTYPE_L4_FRAG,
1657                 RTE_PTYPE_L4_ICMP,
1658                 RTE_PTYPE_L4_NONFRAG,
1659                 RTE_PTYPE_L4_SCTP,
1660                 RTE_PTYPE_L4_TCP,
1661                 RTE_PTYPE_L4_UDP,
1662                 RTE_PTYPE_TUNNEL_GRENAT,
1663                 RTE_PTYPE_TUNNEL_IP,
1664                 RTE_PTYPE_INNER_L2_ETHER,
1665                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1666                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1667                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1668                 RTE_PTYPE_INNER_L4_FRAG,
1669                 RTE_PTYPE_INNER_L4_ICMP,
1670                 RTE_PTYPE_INNER_L4_NONFRAG,
1671                 RTE_PTYPE_INNER_L4_SCTP,
1672                 RTE_PTYPE_INNER_L4_TCP,
1673                 RTE_PTYPE_INNER_L4_UDP,
1674                 RTE_PTYPE_UNKNOWN
1675         };
1676
1677         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1678 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1679             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1680 #endif
1681             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1682             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1683             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1684                 return ptypes;
1685         return NULL;
1686 }
1687
1688 int
1689 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1690                         uint16_t queue_idx,
1691                         uint16_t nb_desc,
1692                         unsigned int socket_id,
1693                         const struct rte_eth_rxconf *rx_conf,
1694                         struct rte_mempool *mp)
1695 {
1696         struct i40e_vsi *vsi;
1697         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1698         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1699         struct i40e_adapter *ad =
1700                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1701         struct i40e_rx_queue *rxq;
1702         const struct rte_memzone *rz;
1703         uint32_t ring_size;
1704         uint16_t len, i;
1705         uint16_t base, bsf, tc_mapping;
1706         int use_def_burst_func = 1;
1707
1708         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1709                 struct i40e_vf *vf =
1710                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1711                 vsi = &vf->vsi;
1712         } else
1713                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1714
1715         if (vsi == NULL) {
1716                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1717                             "index exceeds the maximum");
1718                 return I40E_ERR_PARAM;
1719         }
1720         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1721                         (nb_desc > I40E_MAX_RING_DESC) ||
1722                         (nb_desc < I40E_MIN_RING_DESC)) {
1723                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1724                             "invalid", nb_desc);
1725                 return I40E_ERR_PARAM;
1726         }
1727
1728         /* Free memory if needed */
1729         if (dev->data->rx_queues[queue_idx]) {
1730                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1731                 dev->data->rx_queues[queue_idx] = NULL;
1732         }
1733
1734         /* Allocate the rx queue data structure */
1735         rxq = rte_zmalloc_socket("i40e rx queue",
1736                                  sizeof(struct i40e_rx_queue),
1737                                  RTE_CACHE_LINE_SIZE,
1738                                  socket_id);
1739         if (!rxq) {
1740                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1741                             "rx queue data structure");
1742                 return -ENOMEM;
1743         }
1744         rxq->mp = mp;
1745         rxq->nb_rx_desc = nb_desc;
1746         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1747         rxq->queue_id = queue_idx;
1748         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1749                 rxq->reg_idx = queue_idx;
1750         else /* PF device */
1751                 rxq->reg_idx = vsi->base_queue +
1752                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1753
1754         rxq->port_id = dev->data->port_id;
1755         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1756                                                         0 : ETHER_CRC_LEN);
1757         rxq->drop_en = rx_conf->rx_drop_en;
1758         rxq->vsi = vsi;
1759         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1760
1761         /* Allocate the maximun number of RX ring hardware descriptor. */
1762         len = I40E_MAX_RING_DESC;
1763
1764 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1765         /**
1766          * Allocating a little more memory because vectorized/bulk_alloc Rx
1767          * functions doesn't check boundaries each time.
1768          */
1769         len += RTE_PMD_I40E_RX_MAX_BURST;
1770 #endif
1771
1772         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1773                               I40E_DMA_MEM_ALIGN);
1774
1775         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1776                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1777         if (!rz) {
1778                 i40e_dev_rx_queue_release(rxq);
1779                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1780                 return -ENOMEM;
1781         }
1782
1783         /* Zero all the descriptors in the ring. */
1784         memset(rz->addr, 0, ring_size);
1785
1786         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1787         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1788
1789 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1790         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1791 #else
1792         len = nb_desc;
1793 #endif
1794
1795         /* Allocate the software ring. */
1796         rxq->sw_ring =
1797                 rte_zmalloc_socket("i40e rx sw ring",
1798                                    sizeof(struct i40e_rx_entry) * len,
1799                                    RTE_CACHE_LINE_SIZE,
1800                                    socket_id);
1801         if (!rxq->sw_ring) {
1802                 i40e_dev_rx_queue_release(rxq);
1803                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1804                 return -ENOMEM;
1805         }
1806
1807         i40e_reset_rx_queue(rxq);
1808         rxq->q_set = TRUE;
1809         dev->data->rx_queues[queue_idx] = rxq;
1810
1811         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1812
1813         if (!use_def_burst_func) {
1814 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1815                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1816                              "satisfied. Rx Burst Bulk Alloc function will be "
1817                              "used on port=%d, queue=%d.",
1818                              rxq->port_id, rxq->queue_id);
1819 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1820         } else {
1821                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1822                              "not satisfied, Scattered Rx is requested, "
1823                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1824                              "not enabled on port=%d, queue=%d.",
1825                              rxq->port_id, rxq->queue_id);
1826                 ad->rx_bulk_alloc_allowed = false;
1827         }
1828
1829         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1830                 if (!(vsi->enabled_tc & (1 << i)))
1831                         continue;
1832                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1833                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1834                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1835                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1836                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1837
1838                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1839                         rxq->dcb_tc = i;
1840         }
1841
1842         return 0;
1843 }
1844
1845 void
1846 i40e_dev_rx_queue_release(void *rxq)
1847 {
1848         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1849
1850         if (!q) {
1851                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1852                 return;
1853         }
1854
1855         i40e_rx_queue_release_mbufs(q);
1856         rte_free(q->sw_ring);
1857         rte_free(q);
1858 }
1859
1860 uint32_t
1861 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1862 {
1863 #define I40E_RXQ_SCAN_INTERVAL 4
1864         volatile union i40e_rx_desc *rxdp;
1865         struct i40e_rx_queue *rxq;
1866         uint16_t desc = 0;
1867
1868         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1869                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1870                 return 0;
1871         }
1872
1873         rxq = dev->data->rx_queues[rx_queue_id];
1874         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1875         while ((desc < rxq->nb_rx_desc) &&
1876                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1877                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1878                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1879                 /**
1880                  * Check the DD bit of a rx descriptor of each 4 in a group,
1881                  * to avoid checking too frequently and downgrading performance
1882                  * too much.
1883                  */
1884                 desc += I40E_RXQ_SCAN_INTERVAL;
1885                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1886                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1887                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1888                                         desc - rxq->nb_rx_desc]);
1889         }
1890
1891         return desc;
1892 }
1893
1894 int
1895 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1896 {
1897         volatile union i40e_rx_desc *rxdp;
1898         struct i40e_rx_queue *rxq = rx_queue;
1899         uint16_t desc;
1900         int ret;
1901
1902         if (unlikely(offset >= rxq->nb_rx_desc)) {
1903                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1904                 return 0;
1905         }
1906
1907         desc = rxq->rx_tail + offset;
1908         if (desc >= rxq->nb_rx_desc)
1909                 desc -= rxq->nb_rx_desc;
1910
1911         rxdp = &(rxq->rx_ring[desc]);
1912
1913         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1914                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1915                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1916
1917         return ret;
1918 }
1919
1920 int
1921 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1922                         uint16_t queue_idx,
1923                         uint16_t nb_desc,
1924                         unsigned int socket_id,
1925                         const struct rte_eth_txconf *tx_conf)
1926 {
1927         struct i40e_vsi *vsi;
1928         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1929         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1930         struct i40e_tx_queue *txq;
1931         const struct rte_memzone *tz;
1932         uint32_t ring_size;
1933         uint16_t tx_rs_thresh, tx_free_thresh;
1934         uint16_t i, base, bsf, tc_mapping;
1935
1936         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1937                 struct i40e_vf *vf =
1938                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1939                 vsi = &vf->vsi;
1940         } else
1941                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1942
1943         if (vsi == NULL) {
1944                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
1945                             "exceeds the maximum", queue_idx);
1946                 return I40E_ERR_PARAM;
1947         }
1948
1949         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1950                         (nb_desc > I40E_MAX_RING_DESC) ||
1951                         (nb_desc < I40E_MIN_RING_DESC)) {
1952                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
1953                             "invalid", nb_desc);
1954                 return I40E_ERR_PARAM;
1955         }
1956
1957         /**
1958          * The following two parameters control the setting of the RS bit on
1959          * transmit descriptors. TX descriptors will have their RS bit set
1960          * after txq->tx_rs_thresh descriptors have been used. The TX
1961          * descriptor ring will be cleaned after txq->tx_free_thresh
1962          * descriptors are used or if the number of descriptors required to
1963          * transmit a packet is greater than the number of free TX descriptors.
1964          *
1965          * The following constraints must be satisfied:
1966          *  - tx_rs_thresh must be greater than 0.
1967          *  - tx_rs_thresh must be less than the size of the ring minus 2.
1968          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
1969          *  - tx_rs_thresh must be a divisor of the ring size.
1970          *  - tx_free_thresh must be greater than 0.
1971          *  - tx_free_thresh must be less than the size of the ring minus 3.
1972          *
1973          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
1974          * race condition, hence the maximum threshold constraints. When set
1975          * to zero use default values.
1976          */
1977         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
1978                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
1979         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
1980                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
1981         if (tx_rs_thresh >= (nb_desc - 2)) {
1982                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
1983                              "number of TX descriptors minus 2. "
1984                              "(tx_rs_thresh=%u port=%d queue=%d)",
1985                              (unsigned int)tx_rs_thresh,
1986                              (int)dev->data->port_id,
1987                              (int)queue_idx);
1988                 return I40E_ERR_PARAM;
1989         }
1990         if (tx_free_thresh >= (nb_desc - 3)) {
1991                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
1992                              "number of TX descriptors minus 3. "
1993                              "(tx_free_thresh=%u port=%d queue=%d)",
1994                              (unsigned int)tx_free_thresh,
1995                              (int)dev->data->port_id,
1996                              (int)queue_idx);
1997                 return I40E_ERR_PARAM;
1998         }
1999         if (tx_rs_thresh > tx_free_thresh) {
2000                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2001                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2002                              " tx_rs_thresh=%u port=%d queue=%d)",
2003                              (unsigned int)tx_free_thresh,
2004                              (unsigned int)tx_rs_thresh,
2005                              (int)dev->data->port_id,
2006                              (int)queue_idx);
2007                 return I40E_ERR_PARAM;
2008         }
2009         if ((nb_desc % tx_rs_thresh) != 0) {
2010                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2011                              "number of TX descriptors. (tx_rs_thresh=%u"
2012                              " port=%d queue=%d)",
2013                              (unsigned int)tx_rs_thresh,
2014                              (int)dev->data->port_id,
2015                              (int)queue_idx);
2016                 return I40E_ERR_PARAM;
2017         }
2018         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2019                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2020                              "tx_rs_thresh is greater than 1. "
2021                              "(tx_rs_thresh=%u port=%d queue=%d)",
2022                              (unsigned int)tx_rs_thresh,
2023                              (int)dev->data->port_id,
2024                              (int)queue_idx);
2025                 return I40E_ERR_PARAM;
2026         }
2027
2028         /* Free memory if needed. */
2029         if (dev->data->tx_queues[queue_idx]) {
2030                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2031                 dev->data->tx_queues[queue_idx] = NULL;
2032         }
2033
2034         /* Allocate the TX queue data structure. */
2035         txq = rte_zmalloc_socket("i40e tx queue",
2036                                   sizeof(struct i40e_tx_queue),
2037                                   RTE_CACHE_LINE_SIZE,
2038                                   socket_id);
2039         if (!txq) {
2040                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2041                             "tx queue structure");
2042                 return -ENOMEM;
2043         }
2044
2045         /* Allocate TX hardware ring descriptors. */
2046         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2047         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2048         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2049                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2050         if (!tz) {
2051                 i40e_dev_tx_queue_release(txq);
2052                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2053                 return -ENOMEM;
2054         }
2055
2056         txq->nb_tx_desc = nb_desc;
2057         txq->tx_rs_thresh = tx_rs_thresh;
2058         txq->tx_free_thresh = tx_free_thresh;
2059         txq->pthresh = tx_conf->tx_thresh.pthresh;
2060         txq->hthresh = tx_conf->tx_thresh.hthresh;
2061         txq->wthresh = tx_conf->tx_thresh.wthresh;
2062         txq->queue_id = queue_idx;
2063         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2064                 txq->reg_idx = queue_idx;
2065         else /* PF device */
2066                 txq->reg_idx = vsi->base_queue +
2067                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2068
2069         txq->port_id = dev->data->port_id;
2070         txq->txq_flags = tx_conf->txq_flags;
2071         txq->vsi = vsi;
2072         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2073
2074         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2075         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2076
2077         /* Allocate software ring */
2078         txq->sw_ring =
2079                 rte_zmalloc_socket("i40e tx sw ring",
2080                                    sizeof(struct i40e_tx_entry) * nb_desc,
2081                                    RTE_CACHE_LINE_SIZE,
2082                                    socket_id);
2083         if (!txq->sw_ring) {
2084                 i40e_dev_tx_queue_release(txq);
2085                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2086                 return -ENOMEM;
2087         }
2088
2089         i40e_reset_tx_queue(txq);
2090         txq->q_set = TRUE;
2091         dev->data->tx_queues[queue_idx] = txq;
2092
2093         /* Use a simple TX queue without offloads or multi segs if possible */
2094         i40e_set_tx_function_flag(dev, txq);
2095
2096         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2097                 if (!(vsi->enabled_tc & (1 << i)))
2098                         continue;
2099                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2100                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2101                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2102                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2103                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2104
2105                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2106                         txq->dcb_tc = i;
2107         }
2108
2109         return 0;
2110 }
2111
2112 void
2113 i40e_dev_tx_queue_release(void *txq)
2114 {
2115         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2116
2117         if (!q) {
2118                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2119                 return;
2120         }
2121
2122         i40e_tx_queue_release_mbufs(q);
2123         rte_free(q->sw_ring);
2124         rte_free(q);
2125 }
2126
2127 const struct rte_memzone *
2128 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2129 {
2130         const struct rte_memzone *mz;
2131
2132         mz = rte_memzone_lookup(name);
2133         if (mz)
2134                 return mz;
2135
2136         if (rte_xen_dom0_supported())
2137                 mz = rte_memzone_reserve_bounded(name, len,
2138                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2139         else
2140                 mz = rte_memzone_reserve_aligned(name, len,
2141                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2142         return mz;
2143 }
2144
2145 void
2146 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2147 {
2148         uint16_t i;
2149
2150         /* SSE Vector driver has a different way of releasing mbufs. */
2151         if (rxq->rx_using_sse) {
2152                 i40e_rx_queue_release_mbufs_vec(rxq);
2153                 return;
2154         }
2155
2156         if (!rxq->sw_ring) {
2157                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2158                 return;
2159         }
2160
2161         for (i = 0; i < rxq->nb_rx_desc; i++) {
2162                 if (rxq->sw_ring[i].mbuf) {
2163                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2164                         rxq->sw_ring[i].mbuf = NULL;
2165                 }
2166         }
2167 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2168         if (rxq->rx_nb_avail == 0)
2169                 return;
2170         for (i = 0; i < rxq->rx_nb_avail; i++) {
2171                 struct rte_mbuf *mbuf;
2172
2173                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2174                 rte_pktmbuf_free_seg(mbuf);
2175         }
2176         rxq->rx_nb_avail = 0;
2177 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2178 }
2179
2180 void
2181 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2182 {
2183         unsigned i;
2184         uint16_t len;
2185
2186         if (!rxq) {
2187                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2188                 return;
2189         }
2190
2191 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2192         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2193                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2194         else
2195 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2196                 len = rxq->nb_rx_desc;
2197
2198         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2199                 ((volatile char *)rxq->rx_ring)[i] = 0;
2200
2201 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2202         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2203         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2204                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2205
2206         rxq->rx_nb_avail = 0;
2207         rxq->rx_next_avail = 0;
2208         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2209 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2210         rxq->rx_tail = 0;
2211         rxq->nb_rx_hold = 0;
2212         rxq->pkt_first_seg = NULL;
2213         rxq->pkt_last_seg = NULL;
2214
2215         rxq->rxrearm_start = 0;
2216         rxq->rxrearm_nb = 0;
2217 }
2218
2219 void
2220 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2221 {
2222         uint16_t i;
2223
2224         if (!txq || !txq->sw_ring) {
2225                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2226                 return;
2227         }
2228
2229         for (i = 0; i < txq->nb_tx_desc; i++) {
2230                 if (txq->sw_ring[i].mbuf) {
2231                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2232                         txq->sw_ring[i].mbuf = NULL;
2233                 }
2234         }
2235 }
2236
2237 void
2238 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2239 {
2240         struct i40e_tx_entry *txe;
2241         uint16_t i, prev, size;
2242
2243         if (!txq) {
2244                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2245                 return;
2246         }
2247
2248         txe = txq->sw_ring;
2249         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2250         for (i = 0; i < size; i++)
2251                 ((volatile char *)txq->tx_ring)[i] = 0;
2252
2253         prev = (uint16_t)(txq->nb_tx_desc - 1);
2254         for (i = 0; i < txq->nb_tx_desc; i++) {
2255                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2256
2257                 txd->cmd_type_offset_bsz =
2258                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2259                 txe[i].mbuf =  NULL;
2260                 txe[i].last_id = i;
2261                 txe[prev].next_id = i;
2262                 prev = i;
2263         }
2264
2265         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2266         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2267
2268         txq->tx_tail = 0;
2269         txq->nb_tx_used = 0;
2270
2271         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2272         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2273 }
2274
2275 /* Init the TX queue in hardware */
2276 int
2277 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2278 {
2279         enum i40e_status_code err = I40E_SUCCESS;
2280         struct i40e_vsi *vsi = txq->vsi;
2281         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2282         uint16_t pf_q = txq->reg_idx;
2283         struct i40e_hmc_obj_txq tx_ctx;
2284         uint32_t qtx_ctl;
2285
2286         /* clear the context structure first */
2287         memset(&tx_ctx, 0, sizeof(tx_ctx));
2288         tx_ctx.new_context = 1;
2289         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2290         tx_ctx.qlen = txq->nb_tx_desc;
2291
2292 #ifdef RTE_LIBRTE_IEEE1588
2293         tx_ctx.timesync_ena = 1;
2294 #endif
2295         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2296         if (vsi->type == I40E_VSI_FDIR)
2297                 tx_ctx.fd_ena = TRUE;
2298
2299         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2300         if (err != I40E_SUCCESS) {
2301                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2302                 return err;
2303         }
2304
2305         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2306         if (err != I40E_SUCCESS) {
2307                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2308                 return err;
2309         }
2310
2311         /* Now associate this queue with this PCI function */
2312         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2313         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2314                                         I40E_QTX_CTL_PF_INDX_MASK);
2315         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2316         I40E_WRITE_FLUSH(hw);
2317
2318         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2319
2320         return err;
2321 }
2322
2323 int
2324 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2325 {
2326         struct i40e_rx_entry *rxe = rxq->sw_ring;
2327         uint64_t dma_addr;
2328         uint16_t i;
2329
2330         for (i = 0; i < rxq->nb_rx_desc; i++) {
2331                 volatile union i40e_rx_desc *rxd;
2332                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2333
2334                 if (unlikely(!mbuf)) {
2335                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2336                         return -ENOMEM;
2337                 }
2338
2339                 rte_mbuf_refcnt_set(mbuf, 1);
2340                 mbuf->next = NULL;
2341                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2342                 mbuf->nb_segs = 1;
2343                 mbuf->port = rxq->port_id;
2344
2345                 dma_addr =
2346                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2347
2348                 rxd = &rxq->rx_ring[i];
2349                 rxd->read.pkt_addr = dma_addr;
2350                 rxd->read.hdr_addr = 0;
2351 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2352                 rxd->read.rsvd1 = 0;
2353                 rxd->read.rsvd2 = 0;
2354 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2355
2356                 rxe[i].mbuf = mbuf;
2357         }
2358
2359         return 0;
2360 }
2361
2362 /*
2363  * Calculate the buffer length, and check the jumbo frame
2364  * and maximum packet length.
2365  */
2366 static int
2367 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2368 {
2369         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2370         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2371         struct rte_eth_dev_data *data = pf->dev_data;
2372         uint16_t buf_size, len;
2373
2374         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2375                 RTE_PKTMBUF_HEADROOM);
2376
2377         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2378                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2379         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2380                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2381                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2382                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2383                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2384                 rxq->hs_mode = i40e_header_split_enabled;
2385                 break;
2386         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2387         default:
2388                 rxq->rx_hdr_len = 0;
2389                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2390                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2391                 rxq->hs_mode = i40e_header_split_none;
2392                 break;
2393         }
2394
2395         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2396         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2397         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2398                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2399                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2400                         PMD_DRV_LOG(ERR, "maximum packet length must "
2401                                     "be larger than %u and smaller than %u,"
2402                                     "as jumbo frame is enabled",
2403                                     (uint32_t)ETHER_MAX_LEN,
2404                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2405                         return I40E_ERR_CONFIG;
2406                 }
2407         } else {
2408                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2409                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2410                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2411                                     "larger than %u and smaller than %u, "
2412                                     "as jumbo frame is disabled",
2413                                     (uint32_t)ETHER_MIN_LEN,
2414                                     (uint32_t)ETHER_MAX_LEN);
2415                         return I40E_ERR_CONFIG;
2416                 }
2417         }
2418
2419         return 0;
2420 }
2421
2422 /* Init the RX queue in hardware */
2423 int
2424 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2425 {
2426         int err = I40E_SUCCESS;
2427         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2428         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2429         uint16_t pf_q = rxq->reg_idx;
2430         uint16_t buf_size;
2431         struct i40e_hmc_obj_rxq rx_ctx;
2432
2433         err = i40e_rx_queue_config(rxq);
2434         if (err < 0) {
2435                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2436                 return err;
2437         }
2438
2439         /* Clear the context structure first */
2440         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2441         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2442         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2443
2444         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2445         rx_ctx.qlen = rxq->nb_rx_desc;
2446 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2447         rx_ctx.dsize = 1;
2448 #endif
2449         rx_ctx.dtype = rxq->hs_mode;
2450         if (rxq->hs_mode)
2451                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2452         else
2453                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2454         rx_ctx.rxmax = rxq->max_pkt_len;
2455         rx_ctx.tphrdesc_ena = 1;
2456         rx_ctx.tphwdesc_ena = 1;
2457         rx_ctx.tphdata_ena = 1;
2458         rx_ctx.tphhead_ena = 1;
2459         rx_ctx.lrxqthresh = 2;
2460         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2461         rx_ctx.l2tsel = 1;
2462         /* showiv indicates if inner VLAN is stripped inside of tunnel
2463          * packet. When set it to 1, vlan information is stripped from
2464          * the inner header, but the hardware does not put it in the
2465          * descriptor. So set it zero by default.
2466          */
2467         rx_ctx.showiv = 0;
2468         rx_ctx.prefena = 1;
2469
2470         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2471         if (err != I40E_SUCCESS) {
2472                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2473                 return err;
2474         }
2475         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2476         if (err != I40E_SUCCESS) {
2477                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2478                 return err;
2479         }
2480
2481         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2482
2483         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2484                 RTE_PKTMBUF_HEADROOM);
2485
2486         /* Check if scattered RX needs to be used. */
2487         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2488                 dev_data->scattered_rx = 1;
2489         }
2490
2491         /* Init the RX tail regieter. */
2492         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2493
2494         return 0;
2495 }
2496
2497 void
2498 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2499 {
2500         uint16_t i;
2501
2502         PMD_INIT_FUNC_TRACE();
2503
2504         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2505                 if (!dev->data->tx_queues[i])
2506                         continue;
2507                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2508                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2509         }
2510
2511         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2512                 if (!dev->data->rx_queues[i])
2513                         continue;
2514                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2515                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2516         }
2517 }
2518
2519 void
2520 i40e_dev_free_queues(struct rte_eth_dev *dev)
2521 {
2522         uint16_t i;
2523
2524         PMD_INIT_FUNC_TRACE();
2525
2526         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2527                 if (!dev->data->rx_queues[i])
2528                         continue;
2529                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2530                 dev->data->rx_queues[i] = NULL;
2531         }
2532         dev->data->nb_rx_queues = 0;
2533
2534         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2535                 if (!dev->data->tx_queues[i])
2536                         continue;
2537                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2538                 dev->data->tx_queues[i] = NULL;
2539         }
2540         dev->data->nb_tx_queues = 0;
2541 }
2542
2543 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2544 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2545
2546 enum i40e_status_code
2547 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2548 {
2549         struct i40e_tx_queue *txq;
2550         const struct rte_memzone *tz = NULL;
2551         uint32_t ring_size;
2552         struct rte_eth_dev *dev;
2553
2554         if (!pf) {
2555                 PMD_DRV_LOG(ERR, "PF is not available");
2556                 return I40E_ERR_BAD_PTR;
2557         }
2558
2559         dev = pf->adapter->eth_dev;
2560
2561         /* Allocate the TX queue data structure. */
2562         txq = rte_zmalloc_socket("i40e fdir tx queue",
2563                                   sizeof(struct i40e_tx_queue),
2564                                   RTE_CACHE_LINE_SIZE,
2565                                   SOCKET_ID_ANY);
2566         if (!txq) {
2567                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2568                                         "tx queue structure.");
2569                 return I40E_ERR_NO_MEMORY;
2570         }
2571
2572         /* Allocate TX hardware ring descriptors. */
2573         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2574         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2575
2576         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2577                                       I40E_FDIR_QUEUE_ID, ring_size,
2578                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2579         if (!tz) {
2580                 i40e_dev_tx_queue_release(txq);
2581                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2582                 return I40E_ERR_NO_MEMORY;
2583         }
2584
2585         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2586         txq->queue_id = I40E_FDIR_QUEUE_ID;
2587         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2588         txq->vsi = pf->fdir.fdir_vsi;
2589
2590         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2591         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2592         /*
2593          * don't need to allocate software ring and reset for the fdir
2594          * program queue just set the queue has been configured.
2595          */
2596         txq->q_set = TRUE;
2597         pf->fdir.txq = txq;
2598
2599         return I40E_SUCCESS;
2600 }
2601
2602 enum i40e_status_code
2603 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2604 {
2605         struct i40e_rx_queue *rxq;
2606         const struct rte_memzone *rz = NULL;
2607         uint32_t ring_size;
2608         struct rte_eth_dev *dev;
2609
2610         if (!pf) {
2611                 PMD_DRV_LOG(ERR, "PF is not available");
2612                 return I40E_ERR_BAD_PTR;
2613         }
2614
2615         dev = pf->adapter->eth_dev;
2616
2617         /* Allocate the RX queue data structure. */
2618         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2619                                   sizeof(struct i40e_rx_queue),
2620                                   RTE_CACHE_LINE_SIZE,
2621                                   SOCKET_ID_ANY);
2622         if (!rxq) {
2623                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2624                                         "rx queue structure.");
2625                 return I40E_ERR_NO_MEMORY;
2626         }
2627
2628         /* Allocate RX hardware ring descriptors. */
2629         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2630         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2631
2632         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2633                                       I40E_FDIR_QUEUE_ID, ring_size,
2634                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2635         if (!rz) {
2636                 i40e_dev_rx_queue_release(rxq);
2637                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2638                 return I40E_ERR_NO_MEMORY;
2639         }
2640
2641         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2642         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2643         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2644         rxq->vsi = pf->fdir.fdir_vsi;
2645
2646         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2647         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2648
2649         /*
2650          * Don't need to allocate software ring and reset for the fdir
2651          * rx queue, just set the queue has been configured.
2652          */
2653         rxq->q_set = TRUE;
2654         pf->fdir.rxq = rxq;
2655
2656         return I40E_SUCCESS;
2657 }
2658
2659 void
2660 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2661         struct rte_eth_rxq_info *qinfo)
2662 {
2663         struct i40e_rx_queue *rxq;
2664
2665         rxq = dev->data->rx_queues[queue_id];
2666
2667         qinfo->mp = rxq->mp;
2668         qinfo->scattered_rx = dev->data->scattered_rx;
2669         qinfo->nb_desc = rxq->nb_rx_desc;
2670
2671         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2672         qinfo->conf.rx_drop_en = rxq->drop_en;
2673         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2674 }
2675
2676 void
2677 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2678         struct rte_eth_txq_info *qinfo)
2679 {
2680         struct i40e_tx_queue *txq;
2681
2682         txq = dev->data->tx_queues[queue_id];
2683
2684         qinfo->nb_desc = txq->nb_tx_desc;
2685
2686         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2687         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2688         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2689
2690         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2691         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2692         qinfo->conf.txq_flags = txq->txq_flags;
2693         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2694 }
2695
2696 void __attribute__((cold))
2697 i40e_set_rx_function(struct rte_eth_dev *dev)
2698 {
2699         struct i40e_adapter *ad =
2700                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2701         uint16_t rx_using_sse, i;
2702         /* In order to allow Vector Rx there are a few configuration
2703          * conditions to be met and Rx Bulk Allocation should be allowed.
2704          */
2705         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2706                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2707                     !ad->rx_bulk_alloc_allowed) {
2708                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2709                                      " Vector Rx preconditions",
2710                                      dev->data->port_id);
2711
2712                         ad->rx_vec_allowed = false;
2713                 }
2714                 if (ad->rx_vec_allowed) {
2715                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2716                                 struct i40e_rx_queue *rxq =
2717                                         dev->data->rx_queues[i];
2718
2719                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2720                                         ad->rx_vec_allowed = false;
2721                                         break;
2722                                 }
2723                         }
2724                 }
2725         }
2726
2727         if (dev->data->scattered_rx) {
2728                 /* Set the non-LRO scattered callback: there are Vector and
2729                  * single allocation versions.
2730                  */
2731                 if (ad->rx_vec_allowed) {
2732                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2733                                             "callback (port=%d).",
2734                                      dev->data->port_id);
2735
2736                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2737                 } else {
2738                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2739                                            "allocation callback (port=%d).",
2740                                      dev->data->port_id);
2741                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2742                 }
2743         /* If parameters allow we are going to choose between the following
2744          * callbacks:
2745          *    - Vector
2746          *    - Bulk Allocation
2747          *    - Single buffer allocation (the simplest one)
2748          */
2749         } else if (ad->rx_vec_allowed) {
2750                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2751                                     "burst size no less than %d (port=%d).",
2752                              RTE_I40E_DESCS_PER_LOOP,
2753                              dev->data->port_id);
2754
2755                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2756         } else if (ad->rx_bulk_alloc_allowed) {
2757                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2758                                     "satisfied. Rx Burst Bulk Alloc function "
2759                                     "will be used on port=%d.",
2760                              dev->data->port_id);
2761
2762                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2763         } else {
2764                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2765                                     "satisfied, or Scattered Rx is requested "
2766                                     "(port=%d).",
2767                              dev->data->port_id);
2768
2769                 dev->rx_pkt_burst = i40e_recv_pkts;
2770         }
2771
2772         /* Propagate information about RX function choice through all queues. */
2773         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2774                 rx_using_sse =
2775                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2776                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2777
2778                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2779                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2780
2781                         if (rxq)
2782                                 rxq->rx_using_sse = rx_using_sse;
2783                 }
2784         }
2785 }
2786
2787 void __attribute__((cold))
2788 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2789 {
2790         struct i40e_adapter *ad =
2791                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2792
2793         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2794         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2795                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2796                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2797                         PMD_INIT_LOG(DEBUG, "Vector tx"
2798                                      " can be enabled on this txq.");
2799
2800                 } else {
2801                         ad->tx_vec_allowed = false;
2802                 }
2803         } else {
2804                 ad->tx_simple_allowed = false;
2805         }
2806 }
2807
2808 void __attribute__((cold))
2809 i40e_set_tx_function(struct rte_eth_dev *dev)
2810 {
2811         struct i40e_adapter *ad =
2812                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2813         int i;
2814
2815         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2816                 if (ad->tx_vec_allowed) {
2817                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2818                                 struct i40e_tx_queue *txq =
2819                                         dev->data->tx_queues[i];
2820
2821                                 if (txq && i40e_txq_vec_setup(txq)) {
2822                                         ad->tx_vec_allowed = false;
2823                                         break;
2824                                 }
2825                         }
2826                 }
2827         }
2828
2829         if (ad->tx_simple_allowed) {
2830                 if (ad->tx_vec_allowed) {
2831                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2832                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2833                 } else {
2834                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2835                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2836                 }
2837                 dev->tx_pkt_prepare = NULL;
2838         } else {
2839                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2840                 dev->tx_pkt_burst = i40e_xmit_pkts;
2841                 dev->tx_pkt_prepare = i40e_prep_pkts;
2842         }
2843 }
2844
2845 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2846 int __attribute__((weak))
2847 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2848 {
2849         return -1;
2850 }
2851
2852 uint16_t __attribute__((weak))
2853 i40e_recv_pkts_vec(
2854         void __rte_unused *rx_queue,
2855         struct rte_mbuf __rte_unused **rx_pkts,
2856         uint16_t __rte_unused nb_pkts)
2857 {
2858         return 0;
2859 }
2860
2861 uint16_t __attribute__((weak))
2862 i40e_recv_scattered_pkts_vec(
2863         void __rte_unused *rx_queue,
2864         struct rte_mbuf __rte_unused **rx_pkts,
2865         uint16_t __rte_unused nb_pkts)
2866 {
2867         return 0;
2868 }
2869
2870 int __attribute__((weak))
2871 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2872 {
2873         return -1;
2874 }
2875
2876 int __attribute__((weak))
2877 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2878 {
2879         return -1;
2880 }
2881
2882 void __attribute__((weak))
2883 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2884 {
2885         return;
2886 }
2887
2888 uint16_t __attribute__((weak))
2889 i40e_xmit_pkts_vec(void __rte_unused *tx_queue,
2890                    struct rte_mbuf __rte_unused **tx_pkts,
2891                    uint16_t __rte_unused nb_pkts)
2892 {
2893         return 0;
2894 }