drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53 #include <rte_ip.h>
  54 #include <rte_net.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_type.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61
  62 #define DEFAULT_TX_RS_THRESH   32
  63 #define DEFAULT_TX_FREE_THRESH 32
  64
  65 #define I40E_TX_MAX_BURST  32
  66
  67 #define I40E_DMA_MEM_ALIGN 4096
  68
  69 /* Base address of the HW descriptor ring should be 128B aligned. */
  70 #define I40E_RING_BASE_ALIGN    128
  71
  72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  73                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  74
  75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  76
  77 #ifdef RTE_LIBRTE_IEEE1588
  78 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  79 #else
  80 #define I40E_TX_IEEE1588_TMST 0
  81 #endif
  82
  83 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  84                 PKT_TX_IP_CKSUM |                \
  85                 PKT_TX_L4_MASK |                 \
  86                 PKT_TX_TCP_SEG |                 \
  87                 PKT_TX_OUTER_IP_CKSUM)
  88
  89 #define I40E_TX_OFFLOAD_MASK (  \
  90                 PKT_TX_IP_CKSUM |       \
  91                 PKT_TX_L4_MASK |        \
  92                 PKT_TX_OUTER_IP_CKSUM | \
  93                 PKT_TX_TCP_SEG |        \
  94                 PKT_TX_QINQ_PKT |       \
  95                 PKT_TX_VLAN_PKT |       \
  96                 PKT_TX_TUNNEL_MASK |    \
  97                 I40E_TX_IEEE1588_TMST)
  98
  99 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
 100                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
 101
 102 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
 103                                       struct rte_mbuf **tx_pkts,
 104                                       uint16_t nb_pkts);
 105
 106 static inline void
 107 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 108 {
 109         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 110                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 111                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 112                 mb->vlan_tci =
 113                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 114                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 115                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 116         } else {
 117                 mb->vlan_tci = 0;
 118         }
 119 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 120         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 121                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 122                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 123                 mb->vlan_tci_outer = mb->vlan_tci;
 124                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 125                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 126                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 127                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 128         } else {
 129                 mb->vlan_tci_outer = 0;
 130         }
 131 #endif
 132         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 133                    mb->vlan_tci, mb->vlan_tci_outer);
 134 }
 135
 136 /* Translate the rx descriptor status to pkt flags */
 137 static inline uint64_t
 138 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 139 {
 140         uint64_t flags;
 141
 142         /* Check if RSS_HASH */
 143         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 144                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 145                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 146
 147         /* Check if FDIR Match */
 148         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 149                                                         PKT_RX_FDIR : 0);
 150
 151         return flags;
 152 }
 153
 154 static inline uint64_t
 155 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 156 {
 157         uint64_t flags = 0;
 158         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 159
 160 #define I40E_RX_ERR_BITS 0x3f
 161         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 162                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 163                 return flags;
 164         }
 165
 166         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 167                 flags |= PKT_RX_IP_CKSUM_BAD;
 168         else
 169                 flags |= PKT_RX_IP_CKSUM_GOOD;
 170
 171         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 172                 flags |= PKT_RX_L4_CKSUM_BAD;
 173         else
 174                 flags |= PKT_RX_L4_CKSUM_GOOD;
 175
 176         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 177                 flags |= PKT_RX_EIP_CKSUM_BAD;
 178
 179         return flags;
 180 }
 181
 182 /* Function to check and set the ieee1588 timesync index and get the
 183  * appropriate flags.
 184  */
 185 #ifdef RTE_LIBRTE_IEEE1588
 186 static inline uint64_t
 187 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 188 {
 189         uint64_t pkt_flags = 0;
 190         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 191                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 192                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 193
 194         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 195                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 196                 pkt_flags = PKT_RX_IEEE1588_PTP;
 197         if (tsyn & 0x04) {
 198                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 199                 mb->timesync = tsyn & 0x03;
 200         }
 201
 202         return pkt_flags;
 203 }
 204 #endif
 205
 206 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 207 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 208 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 209 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 210 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 211
 212 static inline uint64_t
 213 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 214 {
 215         uint64_t flags = 0;
 216 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 217         uint16_t flexbh, flexbl;
 218
 219         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 220                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 221                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 222         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 223                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 224                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 225
 226
 227         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 228                 mb->hash.fdir.hi =
 229                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 230                 flags |= PKT_RX_FDIR_ID;
 231         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 232                 mb->hash.fdir.hi =
 233                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 234                 flags |= PKT_RX_FDIR_FLX;
 235         }
 236         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 237                 mb->hash.fdir.lo =
 238                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 239                 flags |= PKT_RX_FDIR_FLX;
 240         }
 241 #else
 242         mb->hash.fdir.hi =
 243                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 244         flags |= PKT_RX_FDIR_ID;
 245 #endif
 246         return flags;
 247 }
 248
 249 static inline void
 250 i40e_parse_tunneling_params(uint64_t ol_flags,
 251                             union i40e_tx_offload tx_offload,
 252                             uint32_t *cd_tunneling)
 253 {
 254         /* EIPT: External (outer) IP header type */
 255         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 256                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 257         else if (ol_flags & PKT_TX_OUTER_IPV4)
 258                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 259         else if (ol_flags & PKT_TX_OUTER_IPV6)
 260                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 261
 262         /* EIPLEN: External (outer) IP header length, in DWords */
 263         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 264                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 265
 266         /* L4TUNT: L4 Tunneling Type */
 267         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 268         case PKT_TX_TUNNEL_IPIP:
 269                 /* for non UDP / GRE tunneling, set to 00b */
 270                 break;
 271         case PKT_TX_TUNNEL_VXLAN:
 272         case PKT_TX_TUNNEL_GENEVE:
 273                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 274                 break;
 275         case PKT_TX_TUNNEL_GRE:
 276                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 277                 break;
 278         default:
 279                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 280                 return;
 281         }
 282
 283         /* L4TUNLEN: L4 Tunneling Length, in Words
 284          *
 285          * We depend on app to set rte_mbuf.l2_len correctly.
 286          * For IP in GRE it should be set to the length of the GRE
 287          * header;
 288          * for MAC in GRE or MAC in UDP it should be set to the length
 289          * of the GRE or UDP headers plus the inner MAC up to including
 290          * its last Ethertype.
 291          */
 292         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 293                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 294 }
 295
 296 static inline void
 297 i40e_txd_enable_checksum(uint64_t ol_flags,
 298                         uint32_t *td_cmd,
 299                         uint32_t *td_offset,
 300                         union i40e_tx_offload tx_offload)
 301 {
 302         /* Set MACLEN */
 303         if (ol_flags & PKT_TX_TUNNEL_MASK)
 304                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 305                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 306         else
 307                 *td_offset |= (tx_offload.l2_len >> 1)
 308                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 309
 310         /* Enable L3 checksum offloads */
 311         if (ol_flags & PKT_TX_IP_CKSUM) {
 312                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 313                 *td_offset |= (tx_offload.l3_len >> 2)
 314                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 315         } else if (ol_flags & PKT_TX_IPV4) {
 316                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 317                 *td_offset |= (tx_offload.l3_len >> 2)
 318                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 319         } else if (ol_flags & PKT_TX_IPV6) {
 320                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 321                 *td_offset |= (tx_offload.l3_len >> 2)
 322                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 323         }
 324
 325         if (ol_flags & PKT_TX_TCP_SEG) {
 326                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 327                 *td_offset |= (tx_offload.l4_len >> 2)
 328                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 329                 return;
 330         }
 331
 332         /* Enable L4 checksum offloads */
 333         switch (ol_flags & PKT_TX_L4_MASK) {
 334         case PKT_TX_TCP_CKSUM:
 335                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 336                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 337                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 338                 break;
 339         case PKT_TX_SCTP_CKSUM:
 340                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 341                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 342                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 343                 break;
 344         case PKT_TX_UDP_CKSUM:
 345                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 346                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 347                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 348                 break;
 349         default:
 350                 break;
 351         }
 352 }
 353
 354 /* Construct the tx flags */
 355 static inline uint64_t
 356 i40e_build_ctob(uint32_t td_cmd,
 357                 uint32_t td_offset,
 358                 unsigned int size,
 359                 uint32_t td_tag)
 360 {
 361         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 362                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 363                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 364                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 365                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 366 }
 367
 368 static inline int
 369 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 370 {
 371         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 372         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 373         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 374         uint16_t nb_tx_desc = txq->nb_tx_desc;
 375         uint16_t desc_to_clean_to;
 376         uint16_t nb_tx_to_clean;
 377
 378         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 379         if (desc_to_clean_to >= nb_tx_desc)
 380                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 381
 382         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 383         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 384                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 385                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 386                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 387                         "(port=%d queue=%d)", desc_to_clean_to,
 388                                 txq->port_id, txq->queue_id);
 389                 return -1;
 390         }
 391
 392         if (last_desc_cleaned > desc_to_clean_to)
 393                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 394                                                         desc_to_clean_to);
 395         else
 396                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 397                                         last_desc_cleaned);
 398
 399         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 400
 401         txq->last_desc_cleaned = desc_to_clean_to;
 402         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 403
 404         return 0;
 405 }
 406
 407 static inline int
 408 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 409 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 410 #else
 411 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 412 #endif
 413 {
 414         int ret = 0;
 415
 416 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 417         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 418                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 419                              "rxq->rx_free_thresh=%d, "
 420                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 421                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 422                 ret = -EINVAL;
 423         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 424                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 425                              "rxq->rx_free_thresh=%d, "
 426                              "rxq->nb_rx_desc=%d",
 427                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 428                 ret = -EINVAL;
 429         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 430                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 431                              "rxq->nb_rx_desc=%d, "
 432                              "rxq->rx_free_thresh=%d",
 433                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 434                 ret = -EINVAL;
 435         }
 436 #else
 437         ret = -EINVAL;
 438 #endif
 439
 440         return ret;
 441 }
 442
 443 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 444 #define I40E_LOOK_AHEAD 8
 445 #if (I40E_LOOK_AHEAD != 8)
 446 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 447 #endif
 448 static inline int
 449 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 450 {
 451         volatile union i40e_rx_desc *rxdp;
 452         struct i40e_rx_entry *rxep;
 453         struct rte_mbuf *mb;
 454         uint16_t pkt_len;
 455         uint64_t qword1;
 456         uint32_t rx_status;
 457         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 458         int32_t i, j, nb_rx = 0;
 459         uint64_t pkt_flags;
 460         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 461
 462         rxdp = &rxq->rx_ring[rxq->rx_tail];
 463         rxep = &rxq->sw_ring[rxq->rx_tail];
 464
 465         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 466         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 467                                 I40E_RXD_QW1_STATUS_SHIFT;
 468
 469         /* Make sure there is at least 1 packet to receive */
 470         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 471                 return 0;
 472
 473         /**
 474          * Scan LOOK_AHEAD descriptors at a time to determine which
 475          * descriptors reference packets that are ready to be received.
 476          */
 477         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 478                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 479                 /* Read desc statuses backwards to avoid race condition */
 480                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 481                         qword1 = rte_le_to_cpu_64(\
 482                                 rxdp[j].wb.qword1.status_error_len);
 483                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 484                                         I40E_RXD_QW1_STATUS_SHIFT;
 485                 }
 486
 487                 rte_smp_rmb();
 488
 489                 /* Compute how many status bits were set */
 490                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 491                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 492
 493                 nb_rx += nb_dd;
 494
 495                 /* Translate descriptor info to mbuf parameters */
 496                 for (j = 0; j < nb_dd; j++) {
 497                         mb = rxep[j].mbuf;
 498                         qword1 = rte_le_to_cpu_64(\
 499                                 rxdp[j].wb.qword1.status_error_len);
 500                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 501                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 502                         mb->data_len = pkt_len;
 503                         mb->pkt_len = pkt_len;
 504                         mb->ol_flags = 0;
 505                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 506                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 507                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 508                         mb->packet_type =
 509                                 ptype_tbl[(uint8_t)((qword1 &
 510                                 I40E_RXD_QW1_PTYPE_MASK) >>
 511                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 512                         if (pkt_flags & PKT_RX_RSS_HASH)
 513                                 mb->hash.rss = rte_le_to_cpu_32(\
 514                                         rxdp[j].wb.qword0.hi_dword.rss);
 515                         if (pkt_flags & PKT_RX_FDIR)
 516                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 517
 518 #ifdef RTE_LIBRTE_IEEE1588
 519                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 520 #endif
 521                         mb->ol_flags |= pkt_flags;
 522
 523                 }
 524
 525                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 526                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 527
 528                 if (nb_dd != I40E_LOOK_AHEAD)
 529                         break;
 530         }
 531
 532         /* Clear software ring entries */
 533         for (i = 0; i < nb_rx; i++)
 534                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 535
 536         return nb_rx;
 537 }
 538
 539 static inline uint16_t
 540 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 541                         struct rte_mbuf **rx_pkts,
 542                         uint16_t nb_pkts)
 543 {
 544         uint16_t i;
 545         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 546
 547         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 548
 549         for (i = 0; i < nb_pkts; i++)
 550                 rx_pkts[i] = stage[i];
 551
 552         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 553         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 554
 555         return nb_pkts;
 556 }
 557
 558 static inline int
 559 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 560 {
 561         volatile union i40e_rx_desc *rxdp;
 562         struct i40e_rx_entry *rxep;
 563         struct rte_mbuf *mb;
 564         uint16_t alloc_idx, i;
 565         uint64_t dma_addr;
 566         int diag;
 567
 568         /* Allocate buffers in bulk */
 569         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 570                                 (rxq->rx_free_thresh - 1));
 571         rxep = &(rxq->sw_ring[alloc_idx]);
 572         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 573                                         rxq->rx_free_thresh);
 574         if (unlikely(diag != 0)) {
 575                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 576                 return -ENOMEM;
 577         }
 578
 579         rxdp = &rxq->rx_ring[alloc_idx];
 580         for (i = 0; i < rxq->rx_free_thresh; i++) {
 581                 if (likely(i < (rxq->rx_free_thresh - 1)))
 582                         /* Prefetch next mbuf */
 583                         rte_prefetch0(rxep[i + 1].mbuf);
 584
 585                 mb = rxep[i].mbuf;
 586                 rte_mbuf_refcnt_set(mb, 1);
 587                 mb->next = NULL;
 588                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 589                 mb->nb_segs = 1;
 590                 mb->port = rxq->port_id;
 591                 dma_addr = rte_cpu_to_le_64(\
 592                         rte_mbuf_data_iova_default(mb));
 593                 rxdp[i].read.hdr_addr = 0;
 594                 rxdp[i].read.pkt_addr = dma_addr;
 595         }
 596
 597         /* Update rx tail regsiter */
 598         rte_wmb();
 599         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 600
 601         rxq->rx_free_trigger =
 602                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 603         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 604                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 605
 606         return 0;
 607 }
 608
 609 static inline uint16_t
 610 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 611 {
 612         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 613         struct rte_eth_dev *dev;
 614         uint16_t nb_rx = 0;
 615
 616         if (!nb_pkts)
 617                 return 0;
 618
 619         if (rxq->rx_nb_avail)
 620                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 621
 622         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 623         rxq->rx_next_avail = 0;
 624         rxq->rx_nb_avail = nb_rx;
 625         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 626
 627         if (rxq->rx_tail > rxq->rx_free_trigger) {
 628                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 629                         uint16_t i, j;
 630
 631                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 632                         dev->data->rx_mbuf_alloc_failed +=
 633                                 rxq->rx_free_thresh;
 634
 635                         rxq->rx_nb_avail = 0;
 636                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 637                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 638                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 639
 640                         return 0;
 641                 }
 642         }
 643
 644         if (rxq->rx_tail >= rxq->nb_rx_desc)
 645                 rxq->rx_tail = 0;
 646
 647         if (rxq->rx_nb_avail)
 648                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 649
 650         return 0;
 651 }
 652
 653 static uint16_t
 654 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 655                           struct rte_mbuf **rx_pkts,
 656                           uint16_t nb_pkts)
 657 {
 658         uint16_t nb_rx = 0, n, count;
 659
 660         if (unlikely(nb_pkts == 0))
 661                 return 0;
 662
 663         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 664                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 665
 666         while (nb_pkts) {
 667                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 668                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 669                 nb_rx = (uint16_t)(nb_rx + count);
 670                 nb_pkts = (uint16_t)(nb_pkts - count);
 671                 if (count < n)
 672                         break;
 673         }
 674
 675         return nb_rx;
 676 }
 677 #else
 678 static uint16_t
 679 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 680                           struct rte_mbuf __rte_unused **rx_pkts,
 681                           uint16_t __rte_unused nb_pkts)
 682 {
 683         return 0;
 684 }
 685 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 686
 687 uint16_t
 688 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 689 {
 690         struct i40e_rx_queue *rxq;
 691         volatile union i40e_rx_desc *rx_ring;
 692         volatile union i40e_rx_desc *rxdp;
 693         union i40e_rx_desc rxd;
 694         struct i40e_rx_entry *sw_ring;
 695         struct i40e_rx_entry *rxe;
 696         struct rte_eth_dev *dev;
 697         struct rte_mbuf *rxm;
 698         struct rte_mbuf *nmb;
 699         uint16_t nb_rx;
 700         uint32_t rx_status;
 701         uint64_t qword1;
 702         uint16_t rx_packet_len;
 703         uint16_t rx_id, nb_hold;
 704         uint64_t dma_addr;
 705         uint64_t pkt_flags;
 706         uint32_t *ptype_tbl;
 707
 708         nb_rx = 0;
 709         nb_hold = 0;
 710         rxq = rx_queue;
 711         rx_id = rxq->rx_tail;
 712         rx_ring = rxq->rx_ring;
 713         sw_ring = rxq->sw_ring;
 714         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 715
 716         while (nb_rx < nb_pkts) {
 717                 rxdp = &rx_ring[rx_id];
 718                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 719                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 720                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 721
 722                 /* Check the DD bit first */
 723                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 724                         break;
 725
 726                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 727                 if (unlikely(!nmb)) {
 728                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 729                         dev->data->rx_mbuf_alloc_failed++;
 730                         break;
 731                 }
 732
 733                 rxd = *rxdp;
 734                 nb_hold++;
 735                 rxe = &sw_ring[rx_id];
 736                 rx_id++;
 737                 if (unlikely(rx_id == rxq->nb_rx_desc))
 738                         rx_id = 0;
 739
 740                 /* Prefetch next mbuf */
 741                 rte_prefetch0(sw_ring[rx_id].mbuf);
 742
 743                 /**
 744                  * When next RX descriptor is on a cache line boundary,
 745                  * prefetch the next 4 RX descriptors and next 8 pointers
 746                  * to mbufs.
 747                  */
 748                 if ((rx_id & 0x3) == 0) {
 749                         rte_prefetch0(&rx_ring[rx_id]);
 750                         rte_prefetch0(&sw_ring[rx_id]);
 751                 }
 752                 rxm = rxe->mbuf;
 753                 rxe->mbuf = nmb;
 754                 dma_addr =
 755                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 756                 rxdp->read.hdr_addr = 0;
 757                 rxdp->read.pkt_addr = dma_addr;
 758
 759                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 760                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 761
 762                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 763                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 764                 rxm->nb_segs = 1;
 765                 rxm->next = NULL;
 766                 rxm->pkt_len = rx_packet_len;
 767                 rxm->data_len = rx_packet_len;
 768                 rxm->port = rxq->port_id;
 769                 rxm->ol_flags = 0;
 770                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 771                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 772                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 773                 rxm->packet_type =
 774                         ptype_tbl[(uint8_t)((qword1 &
 775                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 776                 if (pkt_flags & PKT_RX_RSS_HASH)
 777                         rxm->hash.rss =
 778                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 779                 if (pkt_flags & PKT_RX_FDIR)
 780                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 781
 782 #ifdef RTE_LIBRTE_IEEE1588
 783                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 784 #endif
 785                 rxm->ol_flags |= pkt_flags;
 786
 787                 rx_pkts[nb_rx++] = rxm;
 788         }
 789         rxq->rx_tail = rx_id;
 790
 791         /**
 792          * If the number of free RX descriptors is greater than the RX free
 793          * threshold of the queue, advance the receive tail register of queue.
 794          * Update that register with the value of the last processed RX
 795          * descriptor minus 1.
 796          */
 797         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 798         if (nb_hold > rxq->rx_free_thresh) {
 799                 rx_id = (uint16_t) ((rx_id == 0) ?
 800                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 801                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 802                 nb_hold = 0;
 803         }
 804         rxq->nb_rx_hold = nb_hold;
 805
 806         return nb_rx;
 807 }
 808
 809 uint16_t
 810 i40e_recv_scattered_pkts(void *rx_queue,
 811                          struct rte_mbuf **rx_pkts,
 812                          uint16_t nb_pkts)
 813 {
 814         struct i40e_rx_queue *rxq = rx_queue;
 815         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 816         volatile union i40e_rx_desc *rxdp;
 817         union i40e_rx_desc rxd;
 818         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 819         struct i40e_rx_entry *rxe;
 820         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 821         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 822         struct rte_mbuf *nmb, *rxm;
 823         uint16_t rx_id = rxq->rx_tail;
 824         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 825         struct rte_eth_dev *dev;
 826         uint32_t rx_status;
 827         uint64_t qword1;
 828         uint64_t dma_addr;
 829         uint64_t pkt_flags;
 830         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 831
 832         while (nb_rx < nb_pkts) {
 833                 rxdp = &rx_ring[rx_id];
 834                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 835                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 836                                         I40E_RXD_QW1_STATUS_SHIFT;
 837
 838                 /* Check the DD bit */
 839                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 840                         break;
 841
 842                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 843                 if (unlikely(!nmb)) {
 844                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 845                         dev->data->rx_mbuf_alloc_failed++;
 846                         break;
 847                 }
 848
 849                 rxd = *rxdp;
 850                 nb_hold++;
 851                 rxe = &sw_ring[rx_id];
 852                 rx_id++;
 853                 if (rx_id == rxq->nb_rx_desc)
 854                         rx_id = 0;
 855
 856                 /* Prefetch next mbuf */
 857                 rte_prefetch0(sw_ring[rx_id].mbuf);
 858
 859                 /**
 860                  * When next RX descriptor is on a cache line boundary,
 861                  * prefetch the next 4 RX descriptors and next 8 pointers
 862                  * to mbufs.
 863                  */
 864                 if ((rx_id & 0x3) == 0) {
 865                         rte_prefetch0(&rx_ring[rx_id]);
 866                         rte_prefetch0(&sw_ring[rx_id]);
 867                 }
 868
 869                 rxm = rxe->mbuf;
 870                 rxe->mbuf = nmb;
 871                 dma_addr =
 872                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 873
 874                 /* Set data buffer address and data length of the mbuf */
 875                 rxdp->read.hdr_addr = 0;
 876                 rxdp->read.pkt_addr = dma_addr;
 877                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 878                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 879                 rxm->data_len = rx_packet_len;
 880                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 881
 882                 /**
 883                  * If this is the first buffer of the received packet, set the
 884                  * pointer to the first mbuf of the packet and initialize its
 885                  * context. Otherwise, update the total length and the number
 886                  * of segments of the current scattered packet, and update the
 887                  * pointer to the last mbuf of the current packet.
 888                  */
 889                 if (!first_seg) {
 890                         first_seg = rxm;
 891                         first_seg->nb_segs = 1;
 892                         first_seg->pkt_len = rx_packet_len;
 893                 } else {
 894                         first_seg->pkt_len =
 895                                 (uint16_t)(first_seg->pkt_len +
 896                                                 rx_packet_len);
 897                         first_seg->nb_segs++;
 898                         last_seg->next = rxm;
 899                 }
 900
 901                 /**
 902                  * If this is not the last buffer of the received packet,
 903                  * update the pointer to the last mbuf of the current scattered
 904                  * packet and continue to parse the RX ring.
 905                  */
 906                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 907                         last_seg = rxm;
 908                         continue;
 909                 }
 910
 911                 /**
 912                  * This is the last buffer of the received packet. If the CRC
 913                  * is not stripped by the hardware:
 914                  *  - Subtract the CRC length from the total packet length.
 915                  *  - If the last buffer only contains the whole CRC or a part
 916                  *  of it, free the mbuf associated to the last buffer. If part
 917                  *  of the CRC is also contained in the previous mbuf, subtract
 918                  *  the length of that CRC part from the data length of the
 919                  *  previous mbuf.
 920                  */
 921                 rxm->next = NULL;
 922                 if (unlikely(rxq->crc_len > 0)) {
 923                         first_seg->pkt_len -= ETHER_CRC_LEN;
 924                         if (rx_packet_len <= ETHER_CRC_LEN) {
 925                                 rte_pktmbuf_free_seg(rxm);
 926                                 first_seg->nb_segs--;
 927                                 last_seg->data_len =
 928                                         (uint16_t)(last_seg->data_len -
 929                                         (ETHER_CRC_LEN - rx_packet_len));
 930                                 last_seg->next = NULL;
 931                         } else
 932                                 rxm->data_len = (uint16_t)(rx_packet_len -
 933                                                                 ETHER_CRC_LEN);
 934                 }
 935
 936                 first_seg->port = rxq->port_id;
 937                 first_seg->ol_flags = 0;
 938                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 939                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 940                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 941                 first_seg->packet_type =
 942                         ptype_tbl[(uint8_t)((qword1 &
 943                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 944                 if (pkt_flags & PKT_RX_RSS_HASH)
 945                         first_seg->hash.rss =
 946                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 947                 if (pkt_flags & PKT_RX_FDIR)
 948                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 949
 950 #ifdef RTE_LIBRTE_IEEE1588
 951                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 952 #endif
 953                 first_seg->ol_flags |= pkt_flags;
 954
 955                 /* Prefetch data of first segment, if configured to do so. */
 956                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 957                         first_seg->data_off));
 958                 rx_pkts[nb_rx++] = first_seg;
 959                 first_seg = NULL;
 960         }
 961
 962         /* Record index of the next RX descriptor to probe. */
 963         rxq->rx_tail = rx_id;
 964         rxq->pkt_first_seg = first_seg;
 965         rxq->pkt_last_seg = last_seg;
 966
 967         /**
 968          * If the number of free RX descriptors is greater than the RX free
 969          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 970          * register. Update the RDT with the value of the last processed RX
 971          * descriptor minus 1, to guarantee that the RDT register is never
 972          * equal to the RDH register, which creates a "full" ring situtation
 973          * from the hardware point of view.
 974          */
 975         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 976         if (nb_hold > rxq->rx_free_thresh) {
 977                 rx_id = (uint16_t)(rx_id == 0 ?
 978                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 979                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 980                 nb_hold = 0;
 981         }
 982         rxq->nb_rx_hold = nb_hold;
 983
 984         return nb_rx;
 985 }
 986
 987 /* Check if the context descriptor is needed for TX offloading */
 988 static inline uint16_t
 989 i40e_calc_context_desc(uint64_t flags)
 990 {
 991         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 992                 PKT_TX_TCP_SEG |
 993                 PKT_TX_QINQ_PKT |
 994                 PKT_TX_TUNNEL_MASK;
 995
 996 #ifdef RTE_LIBRTE_IEEE1588
 997         mask |= PKT_TX_IEEE1588_TMST;
 998 #endif
 999
1000         return (flags & mask) ? 1 : 0;
1001 }
1002
1003 /* set i40e TSO context descriptor */
1004 static inline uint64_t
1005 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1006 {
1007         uint64_t ctx_desc = 0;
1008         uint32_t cd_cmd, hdr_len, cd_tso_len;
1009
1010         if (!tx_offload.l4_len) {
1011                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1012                 return ctx_desc;
1013         }
1014
1015         /**
1016          * in case of non tunneling packet, the outer_l2_len and
1017          * outer_l3_len must be 0.
1018          */
1019         hdr_len = tx_offload.outer_l2_len +
1020                 tx_offload.outer_l3_len +
1021                 tx_offload.l2_len +
1022                 tx_offload.l3_len +
1023                 tx_offload.l4_len;
1024
1025         cd_cmd = I40E_TX_CTX_DESC_TSO;
1026         cd_tso_len = mbuf->pkt_len - hdr_len;
1027         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1028                 ((uint64_t)cd_tso_len <<
1029                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1030                 ((uint64_t)mbuf->tso_segsz <<
1031                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1032
1033         return ctx_desc;
1034 }
1035
1036 uint16_t
1037 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1038 {
1039         struct i40e_tx_queue *txq;
1040         struct i40e_tx_entry *sw_ring;
1041         struct i40e_tx_entry *txe, *txn;
1042         volatile struct i40e_tx_desc *txd;
1043         volatile struct i40e_tx_desc *txr;
1044         struct rte_mbuf *tx_pkt;
1045         struct rte_mbuf *m_seg;
1046         uint32_t cd_tunneling_params;
1047         uint16_t tx_id;
1048         uint16_t nb_tx;
1049         uint32_t td_cmd;
1050         uint32_t td_offset;
1051         uint32_t td_tag;
1052         uint64_t ol_flags;
1053         uint16_t nb_used;
1054         uint16_t nb_ctx;
1055         uint16_t tx_last;
1056         uint16_t slen;
1057         uint64_t buf_dma_addr;
1058         union i40e_tx_offload tx_offload = {0};
1059
1060         txq = tx_queue;
1061         sw_ring = txq->sw_ring;
1062         txr = txq->tx_ring;
1063         tx_id = txq->tx_tail;
1064         txe = &sw_ring[tx_id];
1065
1066         /* Check if the descriptor ring needs to be cleaned. */
1067         if (txq->nb_tx_free < txq->tx_free_thresh)
1068                 i40e_xmit_cleanup(txq);
1069
1070         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1071                 td_cmd = 0;
1072                 td_tag = 0;
1073                 td_offset = 0;
1074
1075                 tx_pkt = *tx_pkts++;
1076                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1077
1078                 ol_flags = tx_pkt->ol_flags;
1079                 tx_offload.l2_len = tx_pkt->l2_len;
1080                 tx_offload.l3_len = tx_pkt->l3_len;
1081                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1082                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1083                 tx_offload.l4_len = tx_pkt->l4_len;
1084                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1085
1086                 /* Calculate the number of context descriptors needed. */
1087                 nb_ctx = i40e_calc_context_desc(ol_flags);
1088
1089                 /**
1090                  * The number of descriptors that must be allocated for
1091                  * a packet equals to the number of the segments of that
1092                  * packet plus 1 context descriptor if needed.
1093                  */
1094                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1095                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1096
1097                 /* Circular ring */
1098                 if (tx_last >= txq->nb_tx_desc)
1099                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1100
1101                 if (nb_used > txq->nb_tx_free) {
1102                         if (i40e_xmit_cleanup(txq) != 0) {
1103                                 if (nb_tx == 0)
1104                                         return 0;
1105                                 goto end_of_tx;
1106                         }
1107                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1108                                 while (nb_used > txq->nb_tx_free) {
1109                                         if (i40e_xmit_cleanup(txq) != 0) {
1110                                                 if (nb_tx == 0)
1111                                                         return 0;
1112                                                 goto end_of_tx;
1113                                         }
1114                                 }
1115                         }
1116                 }
1117
1118                 /* Descriptor based VLAN insertion */
1119                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1120                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1121                         td_tag = tx_pkt->vlan_tci;
1122                 }
1123
1124                 /* Always enable CRC offload insertion */
1125                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1126
1127                 /* Fill in tunneling parameters if necessary */
1128                 cd_tunneling_params = 0;
1129                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1130                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1131                                                     &cd_tunneling_params);
1132                 /* Enable checksum offloading */
1133                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1134                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1135                                                  &td_offset, tx_offload);
1136
1137                 if (nb_ctx) {
1138                         /* Setup TX context descriptor if required */
1139                         volatile struct i40e_tx_context_desc *ctx_txd =
1140                                 (volatile struct i40e_tx_context_desc *)\
1141                                                         &txr[tx_id];
1142                         uint16_t cd_l2tag2 = 0;
1143                         uint64_t cd_type_cmd_tso_mss =
1144                                 I40E_TX_DESC_DTYPE_CONTEXT;
1145
1146                         txn = &sw_ring[txe->next_id];
1147                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1148                         if (txe->mbuf != NULL) {
1149                                 rte_pktmbuf_free_seg(txe->mbuf);
1150                                 txe->mbuf = NULL;
1151                         }
1152
1153                         /* TSO enabled means no timestamp */
1154                         if (ol_flags & PKT_TX_TCP_SEG)
1155                                 cd_type_cmd_tso_mss |=
1156                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1157                         else {
1158 #ifdef RTE_LIBRTE_IEEE1588
1159                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1160                                         cd_type_cmd_tso_mss |=
1161                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1162                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1163 #endif
1164                         }
1165
1166                         ctx_txd->tunneling_params =
1167                                 rte_cpu_to_le_32(cd_tunneling_params);
1168                         if (ol_flags & PKT_TX_QINQ_PKT) {
1169                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1170                                 cd_type_cmd_tso_mss |=
1171                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1172                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1173                         }
1174                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1175                         ctx_txd->type_cmd_tso_mss =
1176                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1177
1178                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1179                                 "tunneling_params: %#x;\n"
1180                                 "l2tag2: %#hx;\n"
1181                                 "rsvd: %#hx;\n"
1182                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1183                                 tx_pkt, tx_id,
1184                                 ctx_txd->tunneling_params,
1185                                 ctx_txd->l2tag2,
1186                                 ctx_txd->rsvd,
1187                                 ctx_txd->type_cmd_tso_mss);
1188
1189                         txe->last_id = tx_last;
1190                         tx_id = txe->next_id;
1191                         txe = txn;
1192                 }
1193
1194                 m_seg = tx_pkt;
1195                 do {
1196                         txd = &txr[tx_id];
1197                         txn = &sw_ring[txe->next_id];
1198
1199                         if (txe->mbuf)
1200                                 rte_pktmbuf_free_seg(txe->mbuf);
1201                         txe->mbuf = m_seg;
1202
1203                         /* Setup TX Descriptor */
1204                         slen = m_seg->data_len;
1205                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1206
1207                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1208                                 "buf_dma_addr: %#"PRIx64";\n"
1209                                 "td_cmd: %#x;\n"
1210                                 "td_offset: %#x;\n"
1211                                 "td_len: %u;\n"
1212                                 "td_tag: %#x;\n",
1213                                 tx_pkt, tx_id, buf_dma_addr,
1214                                 td_cmd, td_offset, slen, td_tag);
1215
1216                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1217                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1218                                                 td_offset, slen, td_tag);
1219                         txe->last_id = tx_last;
1220                         tx_id = txe->next_id;
1221                         txe = txn;
1222                         m_seg = m_seg->next;
1223                 } while (m_seg != NULL);
1224
1225                 /* The last packet data descriptor needs End Of Packet (EOP) */
1226                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1227                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1228                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1229
1230                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1231                         PMD_TX_FREE_LOG(DEBUG,
1232                                         "Setting RS bit on TXD id="
1233                                         "%4u (port=%d queue=%d)",
1234                                         tx_last, txq->port_id, txq->queue_id);
1235
1236                         td_cmd |= I40E_TX_DESC_CMD_RS;
1237
1238                         /* Update txq RS bit counters */
1239                         txq->nb_tx_used = 0;
1240                 }
1241
1242                 txd->cmd_type_offset_bsz |=
1243                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1244                                         I40E_TXD_QW1_CMD_SHIFT);
1245         }
1246
1247 end_of_tx:
1248         rte_wmb();
1249
1250         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1251                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1252                    (unsigned) tx_id, (unsigned) nb_tx);
1253
1254         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1255         txq->tx_tail = tx_id;
1256
1257         return nb_tx;
1258 }
1259
1260 static __rte_always_inline int
1261 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1262 {
1263         struct i40e_tx_entry *txep;
1264         uint16_t i;
1265
1266         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1267                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1268                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1269                 return 0;
1270
1271         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1272
1273         for (i = 0; i < txq->tx_rs_thresh; i++)
1274                 rte_prefetch0((txep + i)->mbuf);
1275
1276         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1277                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1278                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1279                         txep->mbuf = NULL;
1280                 }
1281         } else {
1282                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1283                         rte_pktmbuf_free_seg(txep->mbuf);
1284                         txep->mbuf = NULL;
1285                 }
1286         }
1287
1288         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1289         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1290         if (txq->tx_next_dd >= txq->nb_tx_desc)
1291                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1292
1293         return txq->tx_rs_thresh;
1294 }
1295
1296 /* Populate 4 descriptors with data from 4 mbufs */
1297 static inline void
1298 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1299 {
1300         uint64_t dma_addr;
1301         uint32_t i;
1302
1303         for (i = 0; i < 4; i++, txdp++, pkts++) {
1304                 dma_addr = rte_mbuf_data_iova(*pkts);
1305                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1306                 txdp->cmd_type_offset_bsz =
1307                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1308                                         (*pkts)->data_len, 0);
1309         }
1310 }
1311
1312 /* Populate 1 descriptor with data from 1 mbuf */
1313 static inline void
1314 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1315 {
1316         uint64_t dma_addr;
1317
1318         dma_addr = rte_mbuf_data_iova(*pkts);
1319         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1320         txdp->cmd_type_offset_bsz =
1321                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1322                                 (*pkts)->data_len, 0);
1323 }
1324
1325 /* Fill hardware descriptor ring with mbuf data */
1326 static inline void
1327 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1328                      struct rte_mbuf **pkts,
1329                      uint16_t nb_pkts)
1330 {
1331         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1332         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1333         const int N_PER_LOOP = 4;
1334         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1335         int mainpart, leftover;
1336         int i, j;
1337
1338         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1339         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1340         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1341                 for (j = 0; j < N_PER_LOOP; ++j) {
1342                         (txep + i + j)->mbuf = *(pkts + i + j);
1343                 }
1344                 tx4(txdp + i, pkts + i);
1345         }
1346         if (unlikely(leftover > 0)) {
1347                 for (i = 0; i < leftover; ++i) {
1348                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1349                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1350                 }
1351         }
1352 }
1353
1354 static inline uint16_t
1355 tx_xmit_pkts(struct i40e_tx_queue *txq,
1356              struct rte_mbuf **tx_pkts,
1357              uint16_t nb_pkts)
1358 {
1359         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1360         uint16_t n = 0;
1361
1362         /**
1363          * Begin scanning the H/W ring for done descriptors when the number
1364          * of available descriptors drops below tx_free_thresh. For each done
1365          * descriptor, free the associated buffer.
1366          */
1367         if (txq->nb_tx_free < txq->tx_free_thresh)
1368                 i40e_tx_free_bufs(txq);
1369
1370         /* Use available descriptor only */
1371         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1372         if (unlikely(!nb_pkts))
1373                 return 0;
1374
1375         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1376         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1377                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1378                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1379                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1380                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1381                                                 I40E_TXD_QW1_CMD_SHIFT);
1382                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1383                 txq->tx_tail = 0;
1384         }
1385
1386         /* Fill hardware descriptor ring with mbuf data */
1387         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1388         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1389
1390         /* Determin if RS bit needs to be set */
1391         if (txq->tx_tail > txq->tx_next_rs) {
1392                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1393                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1394                                                 I40E_TXD_QW1_CMD_SHIFT);
1395                 txq->tx_next_rs =
1396                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1397                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1398                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1399         }
1400
1401         if (txq->tx_tail >= txq->nb_tx_desc)
1402                 txq->tx_tail = 0;
1403
1404         /* Update the tx tail register */
1405         rte_wmb();
1406         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1407
1408         return nb_pkts;
1409 }
1410
1411 static uint16_t
1412 i40e_xmit_pkts_simple(void *tx_queue,
1413                       struct rte_mbuf **tx_pkts,
1414                       uint16_t nb_pkts)
1415 {
1416         uint16_t nb_tx = 0;
1417
1418         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1419                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1420                                                 tx_pkts, nb_pkts);
1421
1422         while (nb_pkts) {
1423                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1424                                                 I40E_TX_MAX_BURST);
1425
1426                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1427                                                 &tx_pkts[nb_tx], num);
1428                 nb_tx = (uint16_t)(nb_tx + ret);
1429                 nb_pkts = (uint16_t)(nb_pkts - ret);
1430                 if (ret < num)
1431                         break;
1432         }
1433
1434         return nb_tx;
1435 }
1436
1437 static uint16_t
1438 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1439                    uint16_t nb_pkts)
1440 {
1441         uint16_t nb_tx = 0;
1442         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1443
1444         while (nb_pkts) {
1445                 uint16_t ret, num;
1446
1447                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1448                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1449                                                 num);
1450                 nb_tx += ret;
1451                 nb_pkts -= ret;
1452                 if (ret < num)
1453                         break;
1454         }
1455
1456         return nb_tx;
1457 }
1458
1459 /*********************************************************************
1460  *
1461  *  TX prep functions
1462  *
1463  **********************************************************************/
1464 uint16_t
1465 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1466                 uint16_t nb_pkts)
1467 {
1468         int i, ret;
1469         uint64_t ol_flags;
1470         struct rte_mbuf *m;
1471
1472         for (i = 0; i < nb_pkts; i++) {
1473                 m = tx_pkts[i];
1474                 ol_flags = m->ol_flags;
1475
1476                 /**
1477                  * m->nb_segs is uint8_t, so nb_segs is always less than
1478                  * I40E_TX_MAX_SEG.
1479                  * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1480                  */
1481                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1482                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1483                                 rte_errno = -EINVAL;
1484                                 return i;
1485                         }
1486                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1487                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1488                         /* MSS outside the range (256B - 9674B) are considered
1489                          * malicious
1490                          */
1491                         rte_errno = -EINVAL;
1492                         return i;
1493                 }
1494
1495                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1496                         rte_errno = -ENOTSUP;
1497                         return i;
1498                 }
1499
1500 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1501                 ret = rte_validate_tx_offload(m);
1502                 if (ret != 0) {
1503                         rte_errno = ret;
1504                         return i;
1505                 }
1506 #endif
1507                 ret = rte_net_intel_cksum_prepare(m);
1508                 if (ret != 0) {
1509                         rte_errno = ret;
1510                         return i;
1511                 }
1512         }
1513         return i;
1514 }
1515
1516 /*
1517  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1518  * application used, which assume having sequential ones. But from driver's
1519  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1520  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1521  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1522  * use queue_idx from 0 to 95 to access queues, while real queue would be
1523  * different. This function will do a queue mapping to find VSI the queue
1524  * belongs to.
1525  */
1526 static struct i40e_vsi*
1527 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1528 {
1529         /* the queue in MAIN VSI range */
1530         if (queue_idx < pf->main_vsi->nb_qps)
1531                 return pf->main_vsi;
1532
1533         queue_idx -= pf->main_vsi->nb_qps;
1534
1535         /* queue_idx is greater than VMDQ VSIs range */
1536         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1537                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1538                 return NULL;
1539         }
1540
1541         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1542 }
1543
1544 static uint16_t
1545 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1546 {
1547         /* the queue in MAIN VSI range */
1548         if (queue_idx < pf->main_vsi->nb_qps)
1549                 return queue_idx;
1550
1551         /* It's VMDQ queues */
1552         queue_idx -= pf->main_vsi->nb_qps;
1553
1554         if (pf->nb_cfg_vmdq_vsi)
1555                 return queue_idx % pf->vmdq_nb_qps;
1556         else {
1557                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1558                 return (uint16_t)(-1);
1559         }
1560 }
1561
1562 int
1563 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1564 {
1565         struct i40e_rx_queue *rxq;
1566         int err = -1;
1567         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1568
1569         PMD_INIT_FUNC_TRACE();
1570
1571         if (rx_queue_id < dev->data->nb_rx_queues) {
1572                 rxq = dev->data->rx_queues[rx_queue_id];
1573
1574                 err = i40e_alloc_rx_queue_mbufs(rxq);
1575                 if (err) {
1576                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1577                         return err;
1578                 }
1579
1580                 rte_wmb();
1581
1582                 /* Init the RX tail regieter. */
1583                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1584
1585                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1586
1587                 if (err) {
1588                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1589                                     rx_queue_id);
1590
1591                         i40e_rx_queue_release_mbufs(rxq);
1592                         i40e_reset_rx_queue(rxq);
1593                 } else
1594                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1595         }
1596
1597         return err;
1598 }
1599
1600 int
1601 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1602 {
1603         struct i40e_rx_queue *rxq;
1604         int err;
1605         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1606
1607         if (rx_queue_id < dev->data->nb_rx_queues) {
1608                 rxq = dev->data->rx_queues[rx_queue_id];
1609
1610                 /*
1611                 * rx_queue_id is queue id application refers to, while
1612                 * rxq->reg_idx is the real queue index.
1613                 */
1614                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1615
1616                 if (err) {
1617                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1618                                     rx_queue_id);
1619                         return err;
1620                 }
1621                 i40e_rx_queue_release_mbufs(rxq);
1622                 i40e_reset_rx_queue(rxq);
1623                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1624         }
1625
1626         return 0;
1627 }
1628
1629 int
1630 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1631 {
1632         int err = -1;
1633         struct i40e_tx_queue *txq;
1634         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1635
1636         PMD_INIT_FUNC_TRACE();
1637
1638         if (tx_queue_id < dev->data->nb_tx_queues) {
1639                 txq = dev->data->tx_queues[tx_queue_id];
1640
1641                 /*
1642                 * tx_queue_id is queue id application refers to, while
1643                 * rxq->reg_idx is the real queue index.
1644                 */
1645                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1646                 if (err)
1647                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1648                                     tx_queue_id);
1649                 else
1650                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1651         }
1652
1653         return err;
1654 }
1655
1656 int
1657 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1658 {
1659         struct i40e_tx_queue *txq;
1660         int err;
1661         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1662
1663         if (tx_queue_id < dev->data->nb_tx_queues) {
1664                 txq = dev->data->tx_queues[tx_queue_id];
1665
1666                 /*
1667                 * tx_queue_id is queue id application refers to, while
1668                 * txq->reg_idx is the real queue index.
1669                 */
1670                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1671
1672                 if (err) {
1673                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1674                                     tx_queue_id);
1675                         return err;
1676                 }
1677
1678                 i40e_tx_queue_release_mbufs(txq);
1679                 i40e_reset_tx_queue(txq);
1680                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1681         }
1682
1683         return 0;
1684 }
1685
1686 const uint32_t *
1687 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1688 {
1689         static const uint32_t ptypes[] = {
1690                 /* refers to i40e_rxd_pkt_type_mapping() */
1691                 RTE_PTYPE_L2_ETHER,
1692                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1693                 RTE_PTYPE_L2_ETHER_LLDP,
1694                 RTE_PTYPE_L2_ETHER_ARP,
1695                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1696                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1697                 RTE_PTYPE_L4_FRAG,
1698                 RTE_PTYPE_L4_ICMP,
1699                 RTE_PTYPE_L4_NONFRAG,
1700                 RTE_PTYPE_L4_SCTP,
1701                 RTE_PTYPE_L4_TCP,
1702                 RTE_PTYPE_L4_UDP,
1703                 RTE_PTYPE_TUNNEL_GRENAT,
1704                 RTE_PTYPE_TUNNEL_IP,
1705                 RTE_PTYPE_INNER_L2_ETHER,
1706                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1707                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1708                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1709                 RTE_PTYPE_INNER_L4_FRAG,
1710                 RTE_PTYPE_INNER_L4_ICMP,
1711                 RTE_PTYPE_INNER_L4_NONFRAG,
1712                 RTE_PTYPE_INNER_L4_SCTP,
1713                 RTE_PTYPE_INNER_L4_TCP,
1714                 RTE_PTYPE_INNER_L4_UDP,
1715                 RTE_PTYPE_UNKNOWN
1716         };
1717
1718         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1719 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1720             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1721 #endif
1722             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1723             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1724             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1725                 return ptypes;
1726         return NULL;
1727 }
1728
1729 int
1730 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1731                         uint16_t queue_idx,
1732                         uint16_t nb_desc,
1733                         unsigned int socket_id,
1734                         const struct rte_eth_rxconf *rx_conf,
1735                         struct rte_mempool *mp)
1736 {
1737         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1738         struct i40e_adapter *ad =
1739                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1740         struct i40e_vsi *vsi;
1741         struct i40e_pf *pf = NULL;
1742         struct i40e_vf *vf = NULL;
1743         struct i40e_rx_queue *rxq;
1744         const struct rte_memzone *rz;
1745         uint32_t ring_size;
1746         uint16_t len, i;
1747         uint16_t reg_idx, base, bsf, tc_mapping;
1748         int q_offset, use_def_burst_func = 1;
1749
1750         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1751                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1752                 vsi = &vf->vsi;
1753                 if (!vsi)
1754                         return -EINVAL;
1755                 reg_idx = queue_idx;
1756         } else {
1757                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1758                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1759                 if (!vsi)
1760                         return -EINVAL;
1761                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1762                 if (q_offset < 0)
1763                         return -EINVAL;
1764                 reg_idx = vsi->base_queue + q_offset;
1765         }
1766
1767         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1768             (nb_desc > I40E_MAX_RING_DESC) ||
1769             (nb_desc < I40E_MIN_RING_DESC)) {
1770                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1771                             "invalid", nb_desc);
1772                 return -EINVAL;
1773         }
1774
1775         /* Free memory if needed */
1776         if (dev->data->rx_queues[queue_idx]) {
1777                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1778                 dev->data->rx_queues[queue_idx] = NULL;
1779         }
1780
1781         /* Allocate the rx queue data structure */
1782         rxq = rte_zmalloc_socket("i40e rx queue",
1783                                  sizeof(struct i40e_rx_queue),
1784                                  RTE_CACHE_LINE_SIZE,
1785                                  socket_id);
1786         if (!rxq) {
1787                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1788                             "rx queue data structure");
1789                 return -ENOMEM;
1790         }
1791         rxq->mp = mp;
1792         rxq->nb_rx_desc = nb_desc;
1793         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1794         rxq->queue_id = queue_idx;
1795         rxq->reg_idx = reg_idx;
1796         rxq->port_id = dev->data->port_id;
1797         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1798                                                         0 : ETHER_CRC_LEN);
1799         rxq->drop_en = rx_conf->rx_drop_en;
1800         rxq->vsi = vsi;
1801         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1802
1803         /* Allocate the maximun number of RX ring hardware descriptor. */
1804         len = I40E_MAX_RING_DESC;
1805
1806         /**
1807          * Allocating a little more memory because vectorized/bulk_alloc Rx
1808          * functions doesn't check boundaries each time.
1809          */
1810         len += RTE_PMD_I40E_RX_MAX_BURST;
1811
1812         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1813                               I40E_DMA_MEM_ALIGN);
1814
1815         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1816                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1817         if (!rz) {
1818                 i40e_dev_rx_queue_release(rxq);
1819                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1820                 return -ENOMEM;
1821         }
1822
1823         /* Zero all the descriptors in the ring. */
1824         memset(rz->addr, 0, ring_size);
1825
1826         rxq->rx_ring_phys_addr = rz->iova;
1827         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1828
1829         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1830
1831         /* Allocate the software ring. */
1832         rxq->sw_ring =
1833                 rte_zmalloc_socket("i40e rx sw ring",
1834                                    sizeof(struct i40e_rx_entry) * len,
1835                                    RTE_CACHE_LINE_SIZE,
1836                                    socket_id);
1837         if (!rxq->sw_ring) {
1838                 i40e_dev_rx_queue_release(rxq);
1839                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1840                 return -ENOMEM;
1841         }
1842
1843         i40e_reset_rx_queue(rxq);
1844         rxq->q_set = TRUE;
1845         dev->data->rx_queues[queue_idx] = rxq;
1846
1847         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1848
1849         if (!use_def_burst_func) {
1850 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1851                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1852                              "satisfied. Rx Burst Bulk Alloc function will be "
1853                              "used on port=%d, queue=%d.",
1854                              rxq->port_id, rxq->queue_id);
1855 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1856         } else {
1857                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1858                              "not satisfied, Scattered Rx is requested, "
1859                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1860                              "not enabled on port=%d, queue=%d.",
1861                              rxq->port_id, rxq->queue_id);
1862                 ad->rx_bulk_alloc_allowed = false;
1863         }
1864
1865         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1866                 if (!(vsi->enabled_tc & (1 << i)))
1867                         continue;
1868                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1869                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1870                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1871                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1872                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1873
1874                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1875                         rxq->dcb_tc = i;
1876         }
1877
1878         return 0;
1879 }
1880
1881 void
1882 i40e_dev_rx_queue_release(void *rxq)
1883 {
1884         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1885
1886         if (!q) {
1887                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1888                 return;
1889         }
1890
1891         i40e_rx_queue_release_mbufs(q);
1892         rte_free(q->sw_ring);
1893         rte_free(q);
1894 }
1895
1896 uint32_t
1897 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1898 {
1899 #define I40E_RXQ_SCAN_INTERVAL 4
1900         volatile union i40e_rx_desc *rxdp;
1901         struct i40e_rx_queue *rxq;
1902         uint16_t desc = 0;
1903
1904         rxq = dev->data->rx_queues[rx_queue_id];
1905         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1906         while ((desc < rxq->nb_rx_desc) &&
1907                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1908                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1909                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1910                 /**
1911                  * Check the DD bit of a rx descriptor of each 4 in a group,
1912                  * to avoid checking too frequently and downgrading performance
1913                  * too much.
1914                  */
1915                 desc += I40E_RXQ_SCAN_INTERVAL;
1916                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1917                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1918                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1919                                         desc - rxq->nb_rx_desc]);
1920         }
1921
1922         return desc;
1923 }
1924
1925 int
1926 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1927 {
1928         volatile union i40e_rx_desc *rxdp;
1929         struct i40e_rx_queue *rxq = rx_queue;
1930         uint16_t desc;
1931         int ret;
1932
1933         if (unlikely(offset >= rxq->nb_rx_desc)) {
1934                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1935                 return 0;
1936         }
1937
1938         desc = rxq->rx_tail + offset;
1939         if (desc >= rxq->nb_rx_desc)
1940                 desc -= rxq->nb_rx_desc;
1941
1942         rxdp = &(rxq->rx_ring[desc]);
1943
1944         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1945                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1946                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1947
1948         return ret;
1949 }
1950
1951 int
1952 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1953 {
1954         struct i40e_rx_queue *rxq = rx_queue;
1955         volatile uint64_t *status;
1956         uint64_t mask;
1957         uint32_t desc;
1958
1959         if (unlikely(offset >= rxq->nb_rx_desc))
1960                 return -EINVAL;
1961
1962         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1963                 return RTE_ETH_RX_DESC_UNAVAIL;
1964
1965         desc = rxq->rx_tail + offset;
1966         if (desc >= rxq->nb_rx_desc)
1967                 desc -= rxq->nb_rx_desc;
1968
1969         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1970         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1971                 << I40E_RXD_QW1_STATUS_SHIFT);
1972         if (*status & mask)
1973                 return RTE_ETH_RX_DESC_DONE;
1974
1975         return RTE_ETH_RX_DESC_AVAIL;
1976 }
1977
1978 int
1979 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1980 {
1981         struct i40e_tx_queue *txq = tx_queue;
1982         volatile uint64_t *status;
1983         uint64_t mask, expect;
1984         uint32_t desc;
1985
1986         if (unlikely(offset >= txq->nb_tx_desc))
1987                 return -EINVAL;
1988
1989         desc = txq->tx_tail + offset;
1990         /* go to next desc that has the RS bit */
1991         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1992                 txq->tx_rs_thresh;
1993         if (desc >= txq->nb_tx_desc) {
1994                 desc -= txq->nb_tx_desc;
1995                 if (desc >= txq->nb_tx_desc)
1996                         desc -= txq->nb_tx_desc;
1997         }
1998
1999         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2000         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2001         expect = rte_cpu_to_le_64(
2002                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2003         if ((*status & mask) == expect)
2004                 return RTE_ETH_TX_DESC_DONE;
2005
2006         return RTE_ETH_TX_DESC_FULL;
2007 }
2008
2009 int
2010 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2011                         uint16_t queue_idx,
2012                         uint16_t nb_desc,
2013                         unsigned int socket_id,
2014                         const struct rte_eth_txconf *tx_conf)
2015 {
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         struct i40e_vsi *vsi;
2018         struct i40e_pf *pf = NULL;
2019         struct i40e_vf *vf = NULL;
2020         struct i40e_tx_queue *txq;
2021         const struct rte_memzone *tz;
2022         uint32_t ring_size;
2023         uint16_t tx_rs_thresh, tx_free_thresh;
2024         uint16_t reg_idx, i, base, bsf, tc_mapping;
2025         int q_offset;
2026
2027         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2028                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2029                 vsi = &vf->vsi;
2030                 if (!vsi)
2031                         return -EINVAL;
2032                 reg_idx = queue_idx;
2033         } else {
2034                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2035                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2036                 if (!vsi)
2037                         return -EINVAL;
2038                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2039                 if (q_offset < 0)
2040                         return -EINVAL;
2041                 reg_idx = vsi->base_queue + q_offset;
2042         }
2043
2044         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2045             (nb_desc > I40E_MAX_RING_DESC) ||
2046             (nb_desc < I40E_MIN_RING_DESC)) {
2047                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2048                             "invalid", nb_desc);
2049                 return -EINVAL;
2050         }
2051
2052         /**
2053          * The following two parameters control the setting of the RS bit on
2054          * transmit descriptors. TX descriptors will have their RS bit set
2055          * after txq->tx_rs_thresh descriptors have been used. The TX
2056          * descriptor ring will be cleaned after txq->tx_free_thresh
2057          * descriptors are used or if the number of descriptors required to
2058          * transmit a packet is greater than the number of free TX descriptors.
2059          *
2060          * The following constraints must be satisfied:
2061          *  - tx_rs_thresh must be greater than 0.
2062          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2063          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2064          *  - tx_rs_thresh must be a divisor of the ring size.
2065          *  - tx_free_thresh must be greater than 0.
2066          *  - tx_free_thresh must be less than the size of the ring minus 3.
2067          *
2068          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2069          * race condition, hence the maximum threshold constraints. When set
2070          * to zero use default values.
2071          */
2072         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2073                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2074         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2075                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2076         if (tx_rs_thresh >= (nb_desc - 2)) {
2077                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2078                              "number of TX descriptors minus 2. "
2079                              "(tx_rs_thresh=%u port=%d queue=%d)",
2080                              (unsigned int)tx_rs_thresh,
2081                              (int)dev->data->port_id,
2082                              (int)queue_idx);
2083                 return I40E_ERR_PARAM;
2084         }
2085         if (tx_free_thresh >= (nb_desc - 3)) {
2086                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2087                              "number of TX descriptors minus 3. "
2088                              "(tx_free_thresh=%u port=%d queue=%d)",
2089                              (unsigned int)tx_free_thresh,
2090                              (int)dev->data->port_id,
2091                              (int)queue_idx);
2092                 return I40E_ERR_PARAM;
2093         }
2094         if (tx_rs_thresh > tx_free_thresh) {
2095                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2096                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2097                              " tx_rs_thresh=%u port=%d queue=%d)",
2098                              (unsigned int)tx_free_thresh,
2099                              (unsigned int)tx_rs_thresh,
2100                              (int)dev->data->port_id,
2101                              (int)queue_idx);
2102                 return I40E_ERR_PARAM;
2103         }
2104         if ((nb_desc % tx_rs_thresh) != 0) {
2105                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2106                              "number of TX descriptors. (tx_rs_thresh=%u"
2107                              " port=%d queue=%d)",
2108                              (unsigned int)tx_rs_thresh,
2109                              (int)dev->data->port_id,
2110                              (int)queue_idx);
2111                 return I40E_ERR_PARAM;
2112         }
2113         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2114                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2115                              "tx_rs_thresh is greater than 1. "
2116                              "(tx_rs_thresh=%u port=%d queue=%d)",
2117                              (unsigned int)tx_rs_thresh,
2118                              (int)dev->data->port_id,
2119                              (int)queue_idx);
2120                 return I40E_ERR_PARAM;
2121         }
2122
2123         /* Free memory if needed. */
2124         if (dev->data->tx_queues[queue_idx]) {
2125                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2126                 dev->data->tx_queues[queue_idx] = NULL;
2127         }
2128
2129         /* Allocate the TX queue data structure. */
2130         txq = rte_zmalloc_socket("i40e tx queue",
2131                                   sizeof(struct i40e_tx_queue),
2132                                   RTE_CACHE_LINE_SIZE,
2133                                   socket_id);
2134         if (!txq) {
2135                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2136                             "tx queue structure");
2137                 return -ENOMEM;
2138         }
2139
2140         /* Allocate TX hardware ring descriptors. */
2141         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2142         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2143         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2144                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2145         if (!tz) {
2146                 i40e_dev_tx_queue_release(txq);
2147                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2148                 return -ENOMEM;
2149         }
2150
2151         txq->nb_tx_desc = nb_desc;
2152         txq->tx_rs_thresh = tx_rs_thresh;
2153         txq->tx_free_thresh = tx_free_thresh;
2154         txq->pthresh = tx_conf->tx_thresh.pthresh;
2155         txq->hthresh = tx_conf->tx_thresh.hthresh;
2156         txq->wthresh = tx_conf->tx_thresh.wthresh;
2157         txq->queue_id = queue_idx;
2158         txq->reg_idx = reg_idx;
2159         txq->port_id = dev->data->port_id;
2160         txq->txq_flags = tx_conf->txq_flags;
2161         txq->vsi = vsi;
2162         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2163
2164         txq->tx_ring_phys_addr = tz->iova;
2165         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2166
2167         /* Allocate software ring */
2168         txq->sw_ring =
2169                 rte_zmalloc_socket("i40e tx sw ring",
2170                                    sizeof(struct i40e_tx_entry) * nb_desc,
2171                                    RTE_CACHE_LINE_SIZE,
2172                                    socket_id);
2173         if (!txq->sw_ring) {
2174                 i40e_dev_tx_queue_release(txq);
2175                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2176                 return -ENOMEM;
2177         }
2178
2179         i40e_reset_tx_queue(txq);
2180         txq->q_set = TRUE;
2181         dev->data->tx_queues[queue_idx] = txq;
2182
2183         /* Use a simple TX queue without offloads or multi segs if possible */
2184         i40e_set_tx_function_flag(dev, txq);
2185
2186         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2187                 if (!(vsi->enabled_tc & (1 << i)))
2188                         continue;
2189                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2190                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2191                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2192                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2193                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2194
2195                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2196                         txq->dcb_tc = i;
2197         }
2198
2199         return 0;
2200 }
2201
2202 void
2203 i40e_dev_tx_queue_release(void *txq)
2204 {
2205         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2206
2207         if (!q) {
2208                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2209                 return;
2210         }
2211
2212         i40e_tx_queue_release_mbufs(q);
2213         rte_free(q->sw_ring);
2214         rte_free(q);
2215 }
2216
2217 const struct rte_memzone *
2218 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2219 {
2220         const struct rte_memzone *mz;
2221
2222         mz = rte_memzone_lookup(name);
2223         if (mz)
2224                 return mz;
2225
2226         mz = rte_memzone_reserve_aligned(name, len,
2227                                          socket_id, 0, I40E_RING_BASE_ALIGN);
2228         return mz;
2229 }
2230
2231 void
2232 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2233 {
2234         uint16_t i;
2235
2236         /* SSE Vector driver has a different way of releasing mbufs. */
2237         if (rxq->rx_using_sse) {
2238                 i40e_rx_queue_release_mbufs_vec(rxq);
2239                 return;
2240         }
2241
2242         if (!rxq->sw_ring) {
2243                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2244                 return;
2245         }
2246
2247         for (i = 0; i < rxq->nb_rx_desc; i++) {
2248                 if (rxq->sw_ring[i].mbuf) {
2249                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2250                         rxq->sw_ring[i].mbuf = NULL;
2251                 }
2252         }
2253 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2254         if (rxq->rx_nb_avail == 0)
2255                 return;
2256         for (i = 0; i < rxq->rx_nb_avail; i++) {
2257                 struct rte_mbuf *mbuf;
2258
2259                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2260                 rte_pktmbuf_free_seg(mbuf);
2261         }
2262         rxq->rx_nb_avail = 0;
2263 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2264 }
2265
2266 void
2267 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2268 {
2269         unsigned i;
2270         uint16_t len;
2271
2272         if (!rxq) {
2273                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2274                 return;
2275         }
2276
2277 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2278         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2279                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2280         else
2281 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2282                 len = rxq->nb_rx_desc;
2283
2284         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2285                 ((volatile char *)rxq->rx_ring)[i] = 0;
2286
2287         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2288         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2289                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2290
2291 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2292         rxq->rx_nb_avail = 0;
2293         rxq->rx_next_avail = 0;
2294         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2295 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2296         rxq->rx_tail = 0;
2297         rxq->nb_rx_hold = 0;
2298         rxq->pkt_first_seg = NULL;
2299         rxq->pkt_last_seg = NULL;
2300
2301         rxq->rxrearm_start = 0;
2302         rxq->rxrearm_nb = 0;
2303 }
2304
2305 void
2306 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2307 {
2308         struct rte_eth_dev *dev;
2309         uint16_t i;
2310
2311         dev = &rte_eth_devices[txq->port_id];
2312
2313         if (!txq || !txq->sw_ring) {
2314                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2315                 return;
2316         }
2317
2318         /**
2319          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2320          *  so need to free remains more carefully.
2321          */
2322         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2323                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2324                 if (txq->tx_tail < i) {
2325                         for (; i < txq->nb_tx_desc; i++) {
2326                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2327                                 txq->sw_ring[i].mbuf = NULL;
2328                         }
2329                         i = 0;
2330                 }
2331                 for (; i < txq->tx_tail; i++) {
2332                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2333                         txq->sw_ring[i].mbuf = NULL;
2334                 }
2335         } else {
2336                 for (i = 0; i < txq->nb_tx_desc; i++) {
2337                         if (txq->sw_ring[i].mbuf) {
2338                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2339                                 txq->sw_ring[i].mbuf = NULL;
2340                         }
2341                 }
2342         }
2343 }
2344
2345 void
2346 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2347 {
2348         struct i40e_tx_entry *txe;
2349         uint16_t i, prev, size;
2350
2351         if (!txq) {
2352                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2353                 return;
2354         }
2355
2356         txe = txq->sw_ring;
2357         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2358         for (i = 0; i < size; i++)
2359                 ((volatile char *)txq->tx_ring)[i] = 0;
2360
2361         prev = (uint16_t)(txq->nb_tx_desc - 1);
2362         for (i = 0; i < txq->nb_tx_desc; i++) {
2363                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2364
2365                 txd->cmd_type_offset_bsz =
2366                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2367                 txe[i].mbuf =  NULL;
2368                 txe[i].last_id = i;
2369                 txe[prev].next_id = i;
2370                 prev = i;
2371         }
2372
2373         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2374         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2375
2376         txq->tx_tail = 0;
2377         txq->nb_tx_used = 0;
2378
2379         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2380         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2381 }
2382
2383 /* Init the TX queue in hardware */
2384 int
2385 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2386 {
2387         enum i40e_status_code err = I40E_SUCCESS;
2388         struct i40e_vsi *vsi = txq->vsi;
2389         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2390         uint16_t pf_q = txq->reg_idx;
2391         struct i40e_hmc_obj_txq tx_ctx;
2392         uint32_t qtx_ctl;
2393
2394         /* clear the context structure first */
2395         memset(&tx_ctx, 0, sizeof(tx_ctx));
2396         tx_ctx.new_context = 1;
2397         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2398         tx_ctx.qlen = txq->nb_tx_desc;
2399
2400 #ifdef RTE_LIBRTE_IEEE1588
2401         tx_ctx.timesync_ena = 1;
2402 #endif
2403         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2404         if (vsi->type == I40E_VSI_FDIR)
2405                 tx_ctx.fd_ena = TRUE;
2406
2407         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2408         if (err != I40E_SUCCESS) {
2409                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2410                 return err;
2411         }
2412
2413         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2414         if (err != I40E_SUCCESS) {
2415                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2416                 return err;
2417         }
2418
2419         /* Now associate this queue with this PCI function */
2420         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2421         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2422                                         I40E_QTX_CTL_PF_INDX_MASK);
2423         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2424         I40E_WRITE_FLUSH(hw);
2425
2426         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2427
2428         return err;
2429 }
2430
2431 int
2432 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2433 {
2434         struct i40e_rx_entry *rxe = rxq->sw_ring;
2435         uint64_t dma_addr;
2436         uint16_t i;
2437
2438         for (i = 0; i < rxq->nb_rx_desc; i++) {
2439                 volatile union i40e_rx_desc *rxd;
2440                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2441
2442                 if (unlikely(!mbuf)) {
2443                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2444                         return -ENOMEM;
2445                 }
2446
2447                 rte_mbuf_refcnt_set(mbuf, 1);
2448                 mbuf->next = NULL;
2449                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2450                 mbuf->nb_segs = 1;
2451                 mbuf->port = rxq->port_id;
2452
2453                 dma_addr =
2454                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2455
2456                 rxd = &rxq->rx_ring[i];
2457                 rxd->read.pkt_addr = dma_addr;
2458                 rxd->read.hdr_addr = 0;
2459 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2460                 rxd->read.rsvd1 = 0;
2461                 rxd->read.rsvd2 = 0;
2462 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2463
2464                 rxe[i].mbuf = mbuf;
2465         }
2466
2467         return 0;
2468 }
2469
2470 /*
2471  * Calculate the buffer length, and check the jumbo frame
2472  * and maximum packet length.
2473  */
2474 static int
2475 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2476 {
2477         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2478         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2479         struct rte_eth_dev_data *data = pf->dev_data;
2480         uint16_t buf_size, len;
2481
2482         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2483                 RTE_PKTMBUF_HEADROOM);
2484
2485         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2486                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2487         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2488                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2489                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2490                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2491                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2492                 rxq->hs_mode = i40e_header_split_enabled;
2493                 break;
2494         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2495         default:
2496                 rxq->rx_hdr_len = 0;
2497                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2498                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2499                 rxq->hs_mode = i40e_header_split_none;
2500                 break;
2501         }
2502
2503         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2504         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2505         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2506                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2507                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2508                         PMD_DRV_LOG(ERR, "maximum packet length must "
2509                                     "be larger than %u and smaller than %u,"
2510                                     "as jumbo frame is enabled",
2511                                     (uint32_t)ETHER_MAX_LEN,
2512                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2513                         return I40E_ERR_CONFIG;
2514                 }
2515         } else {
2516                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2517                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2518                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2519                                     "larger than %u and smaller than %u, "
2520                                     "as jumbo frame is disabled",
2521                                     (uint32_t)ETHER_MIN_LEN,
2522                                     (uint32_t)ETHER_MAX_LEN);
2523                         return I40E_ERR_CONFIG;
2524                 }
2525         }
2526
2527         return 0;
2528 }
2529
2530 /* Init the RX queue in hardware */
2531 int
2532 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2533 {
2534         int err = I40E_SUCCESS;
2535         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2536         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2537         uint16_t pf_q = rxq->reg_idx;
2538         uint16_t buf_size;
2539         struct i40e_hmc_obj_rxq rx_ctx;
2540
2541         err = i40e_rx_queue_config(rxq);
2542         if (err < 0) {
2543                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2544                 return err;
2545         }
2546
2547         /* Clear the context structure first */
2548         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2549         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2550         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2551
2552         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2553         rx_ctx.qlen = rxq->nb_rx_desc;
2554 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2555         rx_ctx.dsize = 1;
2556 #endif
2557         rx_ctx.dtype = rxq->hs_mode;
2558         if (rxq->hs_mode)
2559                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2560         else
2561                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2562         rx_ctx.rxmax = rxq->max_pkt_len;
2563         rx_ctx.tphrdesc_ena = 1;
2564         rx_ctx.tphwdesc_ena = 1;
2565         rx_ctx.tphdata_ena = 1;
2566         rx_ctx.tphhead_ena = 1;
2567         rx_ctx.lrxqthresh = 2;
2568         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2569         rx_ctx.l2tsel = 1;
2570         /* showiv indicates if inner VLAN is stripped inside of tunnel
2571          * packet. When set it to 1, vlan information is stripped from
2572          * the inner header, but the hardware does not put it in the
2573          * descriptor. So set it zero by default.
2574          */
2575         rx_ctx.showiv = 0;
2576         rx_ctx.prefena = 1;
2577
2578         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2579         if (err != I40E_SUCCESS) {
2580                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2581                 return err;
2582         }
2583         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2584         if (err != I40E_SUCCESS) {
2585                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2586                 return err;
2587         }
2588
2589         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2590
2591         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2592                 RTE_PKTMBUF_HEADROOM);
2593
2594         /* Check if scattered RX needs to be used. */
2595         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2596                 dev_data->scattered_rx = 1;
2597         }
2598
2599         /* Init the RX tail regieter. */
2600         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2601
2602         return 0;
2603 }
2604
2605 void
2606 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2607 {
2608         uint16_t i;
2609
2610         PMD_INIT_FUNC_TRACE();
2611
2612         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2613                 if (!dev->data->tx_queues[i])
2614                         continue;
2615                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2616                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2617         }
2618
2619         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2620                 if (!dev->data->rx_queues[i])
2621                         continue;
2622                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2623                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2624         }
2625 }
2626
2627 void
2628 i40e_dev_free_queues(struct rte_eth_dev *dev)
2629 {
2630         uint16_t i;
2631
2632         PMD_INIT_FUNC_TRACE();
2633
2634         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2635                 if (!dev->data->rx_queues[i])
2636                         continue;
2637                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2638                 dev->data->rx_queues[i] = NULL;
2639         }
2640         dev->data->nb_rx_queues = 0;
2641
2642         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2643                 if (!dev->data->tx_queues[i])
2644                         continue;
2645                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2646                 dev->data->tx_queues[i] = NULL;
2647         }
2648         dev->data->nb_tx_queues = 0;
2649 }
2650
2651 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2652 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2653
2654 enum i40e_status_code
2655 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2656 {
2657         struct i40e_tx_queue *txq;
2658         const struct rte_memzone *tz = NULL;
2659         uint32_t ring_size;
2660         struct rte_eth_dev *dev;
2661
2662         if (!pf) {
2663                 PMD_DRV_LOG(ERR, "PF is not available");
2664                 return I40E_ERR_BAD_PTR;
2665         }
2666
2667         dev = pf->adapter->eth_dev;
2668
2669         /* Allocate the TX queue data structure. */
2670         txq = rte_zmalloc_socket("i40e fdir tx queue",
2671                                   sizeof(struct i40e_tx_queue),
2672                                   RTE_CACHE_LINE_SIZE,
2673                                   SOCKET_ID_ANY);
2674         if (!txq) {
2675                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2676                                         "tx queue structure.");
2677                 return I40E_ERR_NO_MEMORY;
2678         }
2679
2680         /* Allocate TX hardware ring descriptors. */
2681         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2682         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2683
2684         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2685                                       I40E_FDIR_QUEUE_ID, ring_size,
2686                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2687         if (!tz) {
2688                 i40e_dev_tx_queue_release(txq);
2689                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2690                 return I40E_ERR_NO_MEMORY;
2691         }
2692
2693         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2694         txq->queue_id = I40E_FDIR_QUEUE_ID;
2695         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2696         txq->vsi = pf->fdir.fdir_vsi;
2697
2698         txq->tx_ring_phys_addr = tz->iova;
2699         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2700         /*
2701          * don't need to allocate software ring and reset for the fdir
2702          * program queue just set the queue has been configured.
2703          */
2704         txq->q_set = TRUE;
2705         pf->fdir.txq = txq;
2706
2707         return I40E_SUCCESS;
2708 }
2709
2710 enum i40e_status_code
2711 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2712 {
2713         struct i40e_rx_queue *rxq;
2714         const struct rte_memzone *rz = NULL;
2715         uint32_t ring_size;
2716         struct rte_eth_dev *dev;
2717
2718         if (!pf) {
2719                 PMD_DRV_LOG(ERR, "PF is not available");
2720                 return I40E_ERR_BAD_PTR;
2721         }
2722
2723         dev = pf->adapter->eth_dev;
2724
2725         /* Allocate the RX queue data structure. */
2726         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2727                                   sizeof(struct i40e_rx_queue),
2728                                   RTE_CACHE_LINE_SIZE,
2729                                   SOCKET_ID_ANY);
2730         if (!rxq) {
2731                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2732                                         "rx queue structure.");
2733                 return I40E_ERR_NO_MEMORY;
2734         }
2735
2736         /* Allocate RX hardware ring descriptors. */
2737         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2738         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2739
2740         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2741                                       I40E_FDIR_QUEUE_ID, ring_size,
2742                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2743         if (!rz) {
2744                 i40e_dev_rx_queue_release(rxq);
2745                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2746                 return I40E_ERR_NO_MEMORY;
2747         }
2748
2749         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2750         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2751         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2752         rxq->vsi = pf->fdir.fdir_vsi;
2753
2754         rxq->rx_ring_phys_addr = rz->iova;
2755         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2756
2757         /*
2758          * Don't need to allocate software ring and reset for the fdir
2759          * rx queue, just set the queue has been configured.
2760          */
2761         rxq->q_set = TRUE;
2762         pf->fdir.rxq = rxq;
2763
2764         return I40E_SUCCESS;
2765 }
2766
2767 void
2768 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2769         struct rte_eth_rxq_info *qinfo)
2770 {
2771         struct i40e_rx_queue *rxq;
2772
2773         rxq = dev->data->rx_queues[queue_id];
2774
2775         qinfo->mp = rxq->mp;
2776         qinfo->scattered_rx = dev->data->scattered_rx;
2777         qinfo->nb_desc = rxq->nb_rx_desc;
2778
2779         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2780         qinfo->conf.rx_drop_en = rxq->drop_en;
2781         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2782 }
2783
2784 void
2785 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2786         struct rte_eth_txq_info *qinfo)
2787 {
2788         struct i40e_tx_queue *txq;
2789
2790         txq = dev->data->tx_queues[queue_id];
2791
2792         qinfo->nb_desc = txq->nb_tx_desc;
2793
2794         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2795         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2796         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2797
2798         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2799         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2800         qinfo->conf.txq_flags = txq->txq_flags;
2801         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2802 }
2803
2804 void __attribute__((cold))
2805 i40e_set_rx_function(struct rte_eth_dev *dev)
2806 {
2807         struct i40e_adapter *ad =
2808                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2809         uint16_t rx_using_sse, i;
2810         /* In order to allow Vector Rx there are a few configuration
2811          * conditions to be met and Rx Bulk Allocation should be allowed.
2812          */
2813         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2814                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2815                     !ad->rx_bulk_alloc_allowed) {
2816                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2817                                      " Vector Rx preconditions",
2818                                      dev->data->port_id);
2819
2820                         ad->rx_vec_allowed = false;
2821                 }
2822                 if (ad->rx_vec_allowed) {
2823                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2824                                 struct i40e_rx_queue *rxq =
2825                                         dev->data->rx_queues[i];
2826
2827                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2828                                         ad->rx_vec_allowed = false;
2829                                         break;
2830                                 }
2831                         }
2832                 }
2833         }
2834
2835         if (dev->data->scattered_rx) {
2836                 /* Set the non-LRO scattered callback: there are Vector and
2837                  * single allocation versions.
2838                  */
2839                 if (ad->rx_vec_allowed) {
2840                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2841                                             "callback (port=%d).",
2842                                      dev->data->port_id);
2843
2844                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2845                 } else {
2846                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2847                                            "allocation callback (port=%d).",
2848                                      dev->data->port_id);
2849                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2850                 }
2851         /* If parameters allow we are going to choose between the following
2852          * callbacks:
2853          *    - Vector
2854          *    - Bulk Allocation
2855          *    - Single buffer allocation (the simplest one)
2856          */
2857         } else if (ad->rx_vec_allowed) {
2858                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2859                                     "burst size no less than %d (port=%d).",
2860                              RTE_I40E_DESCS_PER_LOOP,
2861                              dev->data->port_id);
2862
2863                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2864         } else if (ad->rx_bulk_alloc_allowed) {
2865                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2866                                     "satisfied. Rx Burst Bulk Alloc function "
2867                                     "will be used on port=%d.",
2868                              dev->data->port_id);
2869
2870                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2871         } else {
2872                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2873                                     "satisfied, or Scattered Rx is requested "
2874                                     "(port=%d).",
2875                              dev->data->port_id);
2876
2877                 dev->rx_pkt_burst = i40e_recv_pkts;
2878         }
2879
2880         /* Propagate information about RX function choice through all queues. */
2881         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2882                 rx_using_sse =
2883                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2884                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2885
2886                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2887                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2888
2889                         if (rxq)
2890                                 rxq->rx_using_sse = rx_using_sse;
2891                 }
2892         }
2893 }
2894
2895 void __attribute__((cold))
2896 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2897 {
2898         struct i40e_adapter *ad =
2899                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2900
2901         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2902         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2903                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2904                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2905                         PMD_INIT_LOG(DEBUG, "Vector tx"
2906                                      " can be enabled on this txq.");
2907
2908                 } else {
2909                         ad->tx_vec_allowed = false;
2910                 }
2911         } else {
2912                 ad->tx_simple_allowed = false;
2913         }
2914 }
2915
2916 void __attribute__((cold))
2917 i40e_set_tx_function(struct rte_eth_dev *dev)
2918 {
2919         struct i40e_adapter *ad =
2920                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2921         int i;
2922
2923         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2924                 if (ad->tx_vec_allowed) {
2925                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2926                                 struct i40e_tx_queue *txq =
2927                                         dev->data->tx_queues[i];
2928
2929                                 if (txq && i40e_txq_vec_setup(txq)) {
2930                                         ad->tx_vec_allowed = false;
2931                                         break;
2932                                 }
2933                         }
2934                 }
2935         }
2936
2937         if (ad->tx_simple_allowed) {
2938                 if (ad->tx_vec_allowed) {
2939                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2940                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2941                 } else {
2942                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2943                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2944                 }
2945                 dev->tx_pkt_prepare = NULL;
2946         } else {
2947                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2948                 dev->tx_pkt_burst = i40e_xmit_pkts;
2949                 dev->tx_pkt_prepare = i40e_prep_pkts;
2950         }
2951 }
2952
2953 void __attribute__((cold))
2954 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
2955 {
2956         struct i40e_adapter *ad =
2957                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2958         int i;
2959
2960         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
2961                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
2962 }
2963
2964 void __attribute__((cold))
2965 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
2966 {
2967         struct i40e_adapter *ad =
2968                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2969         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970         int i;
2971
2972         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
2973                 ad->pctypes_tbl[i] = 0ULL;
2974         ad->flow_types_mask = 0ULL;
2975         ad->pctypes_mask = 0ULL;
2976
2977         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
2978                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
2979         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
2980                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
2981         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
2982                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
2983         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
2984                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
2985         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
2986                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
2987         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
2988                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
2989         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
2990                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
2991         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
2992                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
2993         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
2994                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
2995         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
2996                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
2997         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
2998                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
2999
3000         if (hw->mac.type == I40E_MAC_X722) {
3001                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3002                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3003                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3004                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3005                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3006                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3007                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3008                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3009                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3010                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3011                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3012                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3013         }
3014
3015         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3016                 if (ad->pctypes_tbl[i])
3017                         ad->flow_types_mask |= (1ULL << i);
3018                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3019         }
3020 }
3021
3022 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3023 int __attribute__((weak))
3024 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3025 {
3026         return -1;
3027 }
3028
3029 uint16_t __attribute__((weak))
3030 i40e_recv_pkts_vec(
3031         void __rte_unused *rx_queue,
3032         struct rte_mbuf __rte_unused **rx_pkts,
3033         uint16_t __rte_unused nb_pkts)
3034 {
3035         return 0;
3036 }
3037
3038 uint16_t __attribute__((weak))
3039 i40e_recv_scattered_pkts_vec(
3040         void __rte_unused *rx_queue,
3041         struct rte_mbuf __rte_unused **rx_pkts,
3042         uint16_t __rte_unused nb_pkts)
3043 {
3044         return 0;
3045 }
3046
3047 int __attribute__((weak))
3048 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3049 {
3050         return -1;
3051 }
3052
3053 int __attribute__((weak))
3054 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3055 {
3056         return -1;
3057 }
3058
3059 void __attribute__((weak))
3060 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3061 {
3062         return;
3063 }
3064
3065 uint16_t __attribute__((weak))
3066 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3067                           struct rte_mbuf __rte_unused **tx_pkts,
3068                           uint16_t __rte_unused nb_pkts)
3069 {
3070         return 0;
3071 }