drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  44                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  45
  46 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  47
  48 #ifdef RTE_LIBRTE_IEEE1588
  49 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  50 #else
  51 #define I40E_TX_IEEE1588_TMST 0
  52 #endif
  53
  54 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  55                 PKT_TX_IP_CKSUM |                \
  56                 PKT_TX_L4_MASK |                 \
  57                 PKT_TX_TCP_SEG |                 \
  58                 PKT_TX_OUTER_IP_CKSUM)
  59
  60 #define I40E_TX_OFFLOAD_MASK (  \
  61                 PKT_TX_IP_CKSUM |       \
  62                 PKT_TX_L4_MASK |        \
  63                 PKT_TX_OUTER_IP_CKSUM | \
  64                 PKT_TX_TCP_SEG |        \
  65                 PKT_TX_QINQ_PKT |       \
  66                 PKT_TX_VLAN_PKT |       \
  67                 PKT_TX_TUNNEL_MASK |    \
  68                 I40E_TX_IEEE1588_TMST)
  69
  70 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  71                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  72
  73 static inline void
  74 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  75 {
  76         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  77                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  78                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  79                 mb->vlan_tci =
  80                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  81                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  82                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  83         } else {
  84                 mb->vlan_tci = 0;
  85         }
  86 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  87         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  88                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  89                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
  90                 mb->vlan_tci_outer = mb->vlan_tci;
  91                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  92                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  93                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  94                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  95         } else {
  96                 mb->vlan_tci_outer = 0;
  97         }
  98 #endif
  99         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 100                    mb->vlan_tci, mb->vlan_tci_outer);
 101 }
 102
 103 /* Translate the rx descriptor status to pkt flags */
 104 static inline uint64_t
 105 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 106 {
 107         uint64_t flags;
 108
 109         /* Check if RSS_HASH */
 110         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 111                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 112                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 113
 114         /* Check if FDIR Match */
 115         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 116                                                         PKT_RX_FDIR : 0);
 117
 118         return flags;
 119 }
 120
 121 static inline uint64_t
 122 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 123 {
 124         uint64_t flags = 0;
 125         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 126
 127 #define I40E_RX_ERR_BITS 0x3f
 128         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 129                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 130                 return flags;
 131         }
 132
 133         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 134                 flags |= PKT_RX_IP_CKSUM_BAD;
 135         else
 136                 flags |= PKT_RX_IP_CKSUM_GOOD;
 137
 138         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 139                 flags |= PKT_RX_L4_CKSUM_BAD;
 140         else
 141                 flags |= PKT_RX_L4_CKSUM_GOOD;
 142
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 144                 flags |= PKT_RX_EIP_CKSUM_BAD;
 145
 146         return flags;
 147 }
 148
 149 /* Function to check and set the ieee1588 timesync index and get the
 150  * appropriate flags.
 151  */
 152 #ifdef RTE_LIBRTE_IEEE1588
 153 static inline uint64_t
 154 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 155 {
 156         uint64_t pkt_flags = 0;
 157         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 158                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 159                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 160
 161         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 162                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 163                 pkt_flags = PKT_RX_IEEE1588_PTP;
 164         if (tsyn & 0x04) {
 165                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 166                 mb->timesync = tsyn & 0x03;
 167         }
 168
 169         return pkt_flags;
 170 }
 171 #endif
 172
 173 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 174 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 175 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 176 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 177 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 178
 179 static inline uint64_t
 180 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 181 {
 182         uint64_t flags = 0;
 183 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 184         uint16_t flexbh, flexbl;
 185
 186         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 187                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 188                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 189         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 190                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 191                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 192
 193
 194         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 195                 mb->hash.fdir.hi =
 196                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 197                 flags |= PKT_RX_FDIR_ID;
 198         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 199                 mb->hash.fdir.hi =
 200                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 201                 flags |= PKT_RX_FDIR_FLX;
 202         }
 203         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 204                 mb->hash.fdir.lo =
 205                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 206                 flags |= PKT_RX_FDIR_FLX;
 207         }
 208 #else
 209         mb->hash.fdir.hi =
 210                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 211         flags |= PKT_RX_FDIR_ID;
 212 #endif
 213         return flags;
 214 }
 215
 216 static inline void
 217 i40e_parse_tunneling_params(uint64_t ol_flags,
 218                             union i40e_tx_offload tx_offload,
 219                             uint32_t *cd_tunneling)
 220 {
 221         /* EIPT: External (outer) IP header type */
 222         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 223                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 224         else if (ol_flags & PKT_TX_OUTER_IPV4)
 225                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 226         else if (ol_flags & PKT_TX_OUTER_IPV6)
 227                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 228
 229         /* EIPLEN: External (outer) IP header length, in DWords */
 230         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 231                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 232
 233         /* L4TUNT: L4 Tunneling Type */
 234         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 235         case PKT_TX_TUNNEL_IPIP:
 236                 /* for non UDP / GRE tunneling, set to 00b */
 237                 break;
 238         case PKT_TX_TUNNEL_VXLAN:
 239         case PKT_TX_TUNNEL_GENEVE:
 240                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 241                 break;
 242         case PKT_TX_TUNNEL_GRE:
 243                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 244                 break;
 245         default:
 246                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 247                 return;
 248         }
 249
 250         /* L4TUNLEN: L4 Tunneling Length, in Words
 251          *
 252          * We depend on app to set rte_mbuf.l2_len correctly.
 253          * For IP in GRE it should be set to the length of the GRE
 254          * header;
 255          * for MAC in GRE or MAC in UDP it should be set to the length
 256          * of the GRE or UDP headers plus the inner MAC up to including
 257          * its last Ethertype.
 258          */
 259         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 260                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 261 }
 262
 263 static inline void
 264 i40e_txd_enable_checksum(uint64_t ol_flags,
 265                         uint32_t *td_cmd,
 266                         uint32_t *td_offset,
 267                         union i40e_tx_offload tx_offload)
 268 {
 269         /* Set MACLEN */
 270         if (ol_flags & PKT_TX_TUNNEL_MASK)
 271                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 272                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 273         else
 274                 *td_offset |= (tx_offload.l2_len >> 1)
 275                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 276
 277         /* Enable L3 checksum offloads */
 278         if (ol_flags & PKT_TX_IP_CKSUM) {
 279                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 280                 *td_offset |= (tx_offload.l3_len >> 2)
 281                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 282         } else if (ol_flags & PKT_TX_IPV4) {
 283                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 284                 *td_offset |= (tx_offload.l3_len >> 2)
 285                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 286         } else if (ol_flags & PKT_TX_IPV6) {
 287                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 288                 *td_offset |= (tx_offload.l3_len >> 2)
 289                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 290         }
 291
 292         if (ol_flags & PKT_TX_TCP_SEG) {
 293                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 294                 *td_offset |= (tx_offload.l4_len >> 2)
 295                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 296                 return;
 297         }
 298
 299         /* Enable L4 checksum offloads */
 300         switch (ol_flags & PKT_TX_L4_MASK) {
 301         case PKT_TX_TCP_CKSUM:
 302                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 303                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 304                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 305                 break;
 306         case PKT_TX_SCTP_CKSUM:
 307                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 308                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 309                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 310                 break;
 311         case PKT_TX_UDP_CKSUM:
 312                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 313                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 314                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 315                 break;
 316         default:
 317                 break;
 318         }
 319 }
 320
 321 /* Construct the tx flags */
 322 static inline uint64_t
 323 i40e_build_ctob(uint32_t td_cmd,
 324                 uint32_t td_offset,
 325                 unsigned int size,
 326                 uint32_t td_tag)
 327 {
 328         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 329                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 330                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 331                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 332                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 333 }
 334
 335 static inline int
 336 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 337 {
 338         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 339         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 340         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 341         uint16_t nb_tx_desc = txq->nb_tx_desc;
 342         uint16_t desc_to_clean_to;
 343         uint16_t nb_tx_to_clean;
 344
 345         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 346         if (desc_to_clean_to >= nb_tx_desc)
 347                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 348
 349         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 350         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 351                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 352                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 353                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 354                         "(port=%d queue=%d)", desc_to_clean_to,
 355                                 txq->port_id, txq->queue_id);
 356                 return -1;
 357         }
 358
 359         if (last_desc_cleaned > desc_to_clean_to)
 360                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 361                                                         desc_to_clean_to);
 362         else
 363                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 364                                         last_desc_cleaned);
 365
 366         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 367
 368         txq->last_desc_cleaned = desc_to_clean_to;
 369         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 370
 371         return 0;
 372 }
 373
 374 static inline int
 375 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 376 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 377 #else
 378 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 379 #endif
 380 {
 381         int ret = 0;
 382
 383 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 384         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 385                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 386                              "rxq->rx_free_thresh=%d, "
 387                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 388                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 389                 ret = -EINVAL;
 390         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 391                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 392                              "rxq->rx_free_thresh=%d, "
 393                              "rxq->nb_rx_desc=%d",
 394                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 395                 ret = -EINVAL;
 396         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 397                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 398                              "rxq->nb_rx_desc=%d, "
 399                              "rxq->rx_free_thresh=%d",
 400                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 401                 ret = -EINVAL;
 402         }
 403 #else
 404         ret = -EINVAL;
 405 #endif
 406
 407         return ret;
 408 }
 409
 410 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 411 #define I40E_LOOK_AHEAD 8
 412 #if (I40E_LOOK_AHEAD != 8)
 413 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 414 #endif
 415 static inline int
 416 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 417 {
 418         volatile union i40e_rx_desc *rxdp;
 419         struct i40e_rx_entry *rxep;
 420         struct rte_mbuf *mb;
 421         uint16_t pkt_len;
 422         uint64_t qword1;
 423         uint32_t rx_status;
 424         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 425         int32_t i, j, nb_rx = 0;
 426         uint64_t pkt_flags;
 427         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 428
 429         rxdp = &rxq->rx_ring[rxq->rx_tail];
 430         rxep = &rxq->sw_ring[rxq->rx_tail];
 431
 432         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 433         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 434                                 I40E_RXD_QW1_STATUS_SHIFT;
 435
 436         /* Make sure there is at least 1 packet to receive */
 437         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 438                 return 0;
 439
 440         /**
 441          * Scan LOOK_AHEAD descriptors at a time to determine which
 442          * descriptors reference packets that are ready to be received.
 443          */
 444         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 445                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 446                 /* Read desc statuses backwards to avoid race condition */
 447                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 448                         qword1 = rte_le_to_cpu_64(\
 449                                 rxdp[j].wb.qword1.status_error_len);
 450                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 451                                         I40E_RXD_QW1_STATUS_SHIFT;
 452                 }
 453
 454                 rte_smp_rmb();
 455
 456                 /* Compute how many status bits were set */
 457                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 458                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 459
 460                 nb_rx += nb_dd;
 461
 462                 /* Translate descriptor info to mbuf parameters */
 463                 for (j = 0; j < nb_dd; j++) {
 464                         mb = rxep[j].mbuf;
 465                         qword1 = rte_le_to_cpu_64(\
 466                                 rxdp[j].wb.qword1.status_error_len);
 467                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 468                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 469                         mb->data_len = pkt_len;
 470                         mb->pkt_len = pkt_len;
 471                         mb->ol_flags = 0;
 472                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 473                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 474                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 475                         mb->packet_type =
 476                                 ptype_tbl[(uint8_t)((qword1 &
 477                                 I40E_RXD_QW1_PTYPE_MASK) >>
 478                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 479                         if (pkt_flags & PKT_RX_RSS_HASH)
 480                                 mb->hash.rss = rte_le_to_cpu_32(\
 481                                         rxdp[j].wb.qword0.hi_dword.rss);
 482                         if (pkt_flags & PKT_RX_FDIR)
 483                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 484
 485 #ifdef RTE_LIBRTE_IEEE1588
 486                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 487 #endif
 488                         mb->ol_flags |= pkt_flags;
 489
 490                 }
 491
 492                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 493                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 494
 495                 if (nb_dd != I40E_LOOK_AHEAD)
 496                         break;
 497         }
 498
 499         /* Clear software ring entries */
 500         for (i = 0; i < nb_rx; i++)
 501                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 502
 503         return nb_rx;
 504 }
 505
 506 static inline uint16_t
 507 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 508                         struct rte_mbuf **rx_pkts,
 509                         uint16_t nb_pkts)
 510 {
 511         uint16_t i;
 512         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 513
 514         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 515
 516         for (i = 0; i < nb_pkts; i++)
 517                 rx_pkts[i] = stage[i];
 518
 519         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 520         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 521
 522         return nb_pkts;
 523 }
 524
 525 static inline int
 526 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 527 {
 528         volatile union i40e_rx_desc *rxdp;
 529         struct i40e_rx_entry *rxep;
 530         struct rte_mbuf *mb;
 531         uint16_t alloc_idx, i;
 532         uint64_t dma_addr;
 533         int diag;
 534
 535         /* Allocate buffers in bulk */
 536         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 537                                 (rxq->rx_free_thresh - 1));
 538         rxep = &(rxq->sw_ring[alloc_idx]);
 539         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 540                                         rxq->rx_free_thresh);
 541         if (unlikely(diag != 0)) {
 542                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 543                 return -ENOMEM;
 544         }
 545
 546         rxdp = &rxq->rx_ring[alloc_idx];
 547         for (i = 0; i < rxq->rx_free_thresh; i++) {
 548                 if (likely(i < (rxq->rx_free_thresh - 1)))
 549                         /* Prefetch next mbuf */
 550                         rte_prefetch0(rxep[i + 1].mbuf);
 551
 552                 mb = rxep[i].mbuf;
 553                 rte_mbuf_refcnt_set(mb, 1);
 554                 mb->next = NULL;
 555                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 556                 mb->nb_segs = 1;
 557                 mb->port = rxq->port_id;
 558                 dma_addr = rte_cpu_to_le_64(\
 559                         rte_mbuf_data_iova_default(mb));
 560                 rxdp[i].read.hdr_addr = 0;
 561                 rxdp[i].read.pkt_addr = dma_addr;
 562         }
 563
 564         /* Update rx tail regsiter */
 565         rte_wmb();
 566         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 567
 568         rxq->rx_free_trigger =
 569                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 570         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 571                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 572
 573         return 0;
 574 }
 575
 576 static inline uint16_t
 577 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 578 {
 579         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 580         struct rte_eth_dev *dev;
 581         uint16_t nb_rx = 0;
 582
 583         if (!nb_pkts)
 584                 return 0;
 585
 586         if (rxq->rx_nb_avail)
 587                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 588
 589         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 590         rxq->rx_next_avail = 0;
 591         rxq->rx_nb_avail = nb_rx;
 592         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 593
 594         if (rxq->rx_tail > rxq->rx_free_trigger) {
 595                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 596                         uint16_t i, j;
 597
 598                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 599                         dev->data->rx_mbuf_alloc_failed +=
 600                                 rxq->rx_free_thresh;
 601
 602                         rxq->rx_nb_avail = 0;
 603                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 604                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 605                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 606
 607                         return 0;
 608                 }
 609         }
 610
 611         if (rxq->rx_tail >= rxq->nb_rx_desc)
 612                 rxq->rx_tail = 0;
 613
 614         if (rxq->rx_nb_avail)
 615                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 616
 617         return 0;
 618 }
 619
 620 static uint16_t
 621 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 622                           struct rte_mbuf **rx_pkts,
 623                           uint16_t nb_pkts)
 624 {
 625         uint16_t nb_rx = 0, n, count;
 626
 627         if (unlikely(nb_pkts == 0))
 628                 return 0;
 629
 630         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 631                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 632
 633         while (nb_pkts) {
 634                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 635                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 636                 nb_rx = (uint16_t)(nb_rx + count);
 637                 nb_pkts = (uint16_t)(nb_pkts - count);
 638                 if (count < n)
 639                         break;
 640         }
 641
 642         return nb_rx;
 643 }
 644 #else
 645 static uint16_t
 646 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 647                           struct rte_mbuf __rte_unused **rx_pkts,
 648                           uint16_t __rte_unused nb_pkts)
 649 {
 650         return 0;
 651 }
 652 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 653
 654 uint16_t
 655 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 656 {
 657         struct i40e_rx_queue *rxq;
 658         volatile union i40e_rx_desc *rx_ring;
 659         volatile union i40e_rx_desc *rxdp;
 660         union i40e_rx_desc rxd;
 661         struct i40e_rx_entry *sw_ring;
 662         struct i40e_rx_entry *rxe;
 663         struct rte_eth_dev *dev;
 664         struct rte_mbuf *rxm;
 665         struct rte_mbuf *nmb;
 666         uint16_t nb_rx;
 667         uint32_t rx_status;
 668         uint64_t qword1;
 669         uint16_t rx_packet_len;
 670         uint16_t rx_id, nb_hold;
 671         uint64_t dma_addr;
 672         uint64_t pkt_flags;
 673         uint32_t *ptype_tbl;
 674
 675         nb_rx = 0;
 676         nb_hold = 0;
 677         rxq = rx_queue;
 678         rx_id = rxq->rx_tail;
 679         rx_ring = rxq->rx_ring;
 680         sw_ring = rxq->sw_ring;
 681         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 682
 683         while (nb_rx < nb_pkts) {
 684                 rxdp = &rx_ring[rx_id];
 685                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 686                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 687                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 688
 689                 /* Check the DD bit first */
 690                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 691                         break;
 692
 693                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 694                 if (unlikely(!nmb)) {
 695                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 696                         dev->data->rx_mbuf_alloc_failed++;
 697                         break;
 698                 }
 699
 700                 rxd = *rxdp;
 701                 nb_hold++;
 702                 rxe = &sw_ring[rx_id];
 703                 rx_id++;
 704                 if (unlikely(rx_id == rxq->nb_rx_desc))
 705                         rx_id = 0;
 706
 707                 /* Prefetch next mbuf */
 708                 rte_prefetch0(sw_ring[rx_id].mbuf);
 709
 710                 /**
 711                  * When next RX descriptor is on a cache line boundary,
 712                  * prefetch the next 4 RX descriptors and next 8 pointers
 713                  * to mbufs.
 714                  */
 715                 if ((rx_id & 0x3) == 0) {
 716                         rte_prefetch0(&rx_ring[rx_id]);
 717                         rte_prefetch0(&sw_ring[rx_id]);
 718                 }
 719                 rxm = rxe->mbuf;
 720                 rxe->mbuf = nmb;
 721                 dma_addr =
 722                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 723                 rxdp->read.hdr_addr = 0;
 724                 rxdp->read.pkt_addr = dma_addr;
 725
 726                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 727                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 728
 729                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 730                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 731                 rxm->nb_segs = 1;
 732                 rxm->next = NULL;
 733                 rxm->pkt_len = rx_packet_len;
 734                 rxm->data_len = rx_packet_len;
 735                 rxm->port = rxq->port_id;
 736                 rxm->ol_flags = 0;
 737                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 738                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 739                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 740                 rxm->packet_type =
 741                         ptype_tbl[(uint8_t)((qword1 &
 742                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 743                 if (pkt_flags & PKT_RX_RSS_HASH)
 744                         rxm->hash.rss =
 745                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 746                 if (pkt_flags & PKT_RX_FDIR)
 747                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 748
 749 #ifdef RTE_LIBRTE_IEEE1588
 750                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 751 #endif
 752                 rxm->ol_flags |= pkt_flags;
 753
 754                 rx_pkts[nb_rx++] = rxm;
 755         }
 756         rxq->rx_tail = rx_id;
 757
 758         /**
 759          * If the number of free RX descriptors is greater than the RX free
 760          * threshold of the queue, advance the receive tail register of queue.
 761          * Update that register with the value of the last processed RX
 762          * descriptor minus 1.
 763          */
 764         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 765         if (nb_hold > rxq->rx_free_thresh) {
 766                 rx_id = (uint16_t) ((rx_id == 0) ?
 767                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 768                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 769                 nb_hold = 0;
 770         }
 771         rxq->nb_rx_hold = nb_hold;
 772
 773         return nb_rx;
 774 }
 775
 776 uint16_t
 777 i40e_recv_scattered_pkts(void *rx_queue,
 778                          struct rte_mbuf **rx_pkts,
 779                          uint16_t nb_pkts)
 780 {
 781         struct i40e_rx_queue *rxq = rx_queue;
 782         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 783         volatile union i40e_rx_desc *rxdp;
 784         union i40e_rx_desc rxd;
 785         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 786         struct i40e_rx_entry *rxe;
 787         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 788         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 789         struct rte_mbuf *nmb, *rxm;
 790         uint16_t rx_id = rxq->rx_tail;
 791         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 792         struct rte_eth_dev *dev;
 793         uint32_t rx_status;
 794         uint64_t qword1;
 795         uint64_t dma_addr;
 796         uint64_t pkt_flags;
 797         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 798
 799         while (nb_rx < nb_pkts) {
 800                 rxdp = &rx_ring[rx_id];
 801                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 802                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 803                                         I40E_RXD_QW1_STATUS_SHIFT;
 804
 805                 /* Check the DD bit */
 806                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 807                         break;
 808
 809                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 810                 if (unlikely(!nmb)) {
 811                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 812                         dev->data->rx_mbuf_alloc_failed++;
 813                         break;
 814                 }
 815
 816                 rxd = *rxdp;
 817                 nb_hold++;
 818                 rxe = &sw_ring[rx_id];
 819                 rx_id++;
 820                 if (rx_id == rxq->nb_rx_desc)
 821                         rx_id = 0;
 822
 823                 /* Prefetch next mbuf */
 824                 rte_prefetch0(sw_ring[rx_id].mbuf);
 825
 826                 /**
 827                  * When next RX descriptor is on a cache line boundary,
 828                  * prefetch the next 4 RX descriptors and next 8 pointers
 829                  * to mbufs.
 830                  */
 831                 if ((rx_id & 0x3) == 0) {
 832                         rte_prefetch0(&rx_ring[rx_id]);
 833                         rte_prefetch0(&sw_ring[rx_id]);
 834                 }
 835
 836                 rxm = rxe->mbuf;
 837                 rxe->mbuf = nmb;
 838                 dma_addr =
 839                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 840
 841                 /* Set data buffer address and data length of the mbuf */
 842                 rxdp->read.hdr_addr = 0;
 843                 rxdp->read.pkt_addr = dma_addr;
 844                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 845                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 846                 rxm->data_len = rx_packet_len;
 847                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 848
 849                 /**
 850                  * If this is the first buffer of the received packet, set the
 851                  * pointer to the first mbuf of the packet and initialize its
 852                  * context. Otherwise, update the total length and the number
 853                  * of segments of the current scattered packet, and update the
 854                  * pointer to the last mbuf of the current packet.
 855                  */
 856                 if (!first_seg) {
 857                         first_seg = rxm;
 858                         first_seg->nb_segs = 1;
 859                         first_seg->pkt_len = rx_packet_len;
 860                 } else {
 861                         first_seg->pkt_len =
 862                                 (uint16_t)(first_seg->pkt_len +
 863                                                 rx_packet_len);
 864                         first_seg->nb_segs++;
 865                         last_seg->next = rxm;
 866                 }
 867
 868                 /**
 869                  * If this is not the last buffer of the received packet,
 870                  * update the pointer to the last mbuf of the current scattered
 871                  * packet and continue to parse the RX ring.
 872                  */
 873                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 874                         last_seg = rxm;
 875                         continue;
 876                 }
 877
 878                 /**
 879                  * This is the last buffer of the received packet. If the CRC
 880                  * is not stripped by the hardware:
 881                  *  - Subtract the CRC length from the total packet length.
 882                  *  - If the last buffer only contains the whole CRC or a part
 883                  *  of it, free the mbuf associated to the last buffer. If part
 884                  *  of the CRC is also contained in the previous mbuf, subtract
 885                  *  the length of that CRC part from the data length of the
 886                  *  previous mbuf.
 887                  */
 888                 rxm->next = NULL;
 889                 if (unlikely(rxq->crc_len > 0)) {
 890                         first_seg->pkt_len -= ETHER_CRC_LEN;
 891                         if (rx_packet_len <= ETHER_CRC_LEN) {
 892                                 rte_pktmbuf_free_seg(rxm);
 893                                 first_seg->nb_segs--;
 894                                 last_seg->data_len =
 895                                         (uint16_t)(last_seg->data_len -
 896                                         (ETHER_CRC_LEN - rx_packet_len));
 897                                 last_seg->next = NULL;
 898                         } else
 899                                 rxm->data_len = (uint16_t)(rx_packet_len -
 900                                                                 ETHER_CRC_LEN);
 901                 }
 902
 903                 first_seg->port = rxq->port_id;
 904                 first_seg->ol_flags = 0;
 905                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 906                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 907                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 908                 first_seg->packet_type =
 909                         ptype_tbl[(uint8_t)((qword1 &
 910                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 911                 if (pkt_flags & PKT_RX_RSS_HASH)
 912                         first_seg->hash.rss =
 913                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 914                 if (pkt_flags & PKT_RX_FDIR)
 915                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 916
 917 #ifdef RTE_LIBRTE_IEEE1588
 918                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 919 #endif
 920                 first_seg->ol_flags |= pkt_flags;
 921
 922                 /* Prefetch data of first segment, if configured to do so. */
 923                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 924                         first_seg->data_off));
 925                 rx_pkts[nb_rx++] = first_seg;
 926                 first_seg = NULL;
 927         }
 928
 929         /* Record index of the next RX descriptor to probe. */
 930         rxq->rx_tail = rx_id;
 931         rxq->pkt_first_seg = first_seg;
 932         rxq->pkt_last_seg = last_seg;
 933
 934         /**
 935          * If the number of free RX descriptors is greater than the RX free
 936          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 937          * register. Update the RDT with the value of the last processed RX
 938          * descriptor minus 1, to guarantee that the RDT register is never
 939          * equal to the RDH register, which creates a "full" ring situtation
 940          * from the hardware point of view.
 941          */
 942         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 943         if (nb_hold > rxq->rx_free_thresh) {
 944                 rx_id = (uint16_t)(rx_id == 0 ?
 945                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 946                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 947                 nb_hold = 0;
 948         }
 949         rxq->nb_rx_hold = nb_hold;
 950
 951         return nb_rx;
 952 }
 953
 954 /* Check if the context descriptor is needed for TX offloading */
 955 static inline uint16_t
 956 i40e_calc_context_desc(uint64_t flags)
 957 {
 958         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 959                 PKT_TX_TCP_SEG |
 960                 PKT_TX_QINQ_PKT |
 961                 PKT_TX_TUNNEL_MASK;
 962
 963 #ifdef RTE_LIBRTE_IEEE1588
 964         mask |= PKT_TX_IEEE1588_TMST;
 965 #endif
 966
 967         return (flags & mask) ? 1 : 0;
 968 }
 969
 970 /* set i40e TSO context descriptor */
 971 static inline uint64_t
 972 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 973 {
 974         uint64_t ctx_desc = 0;
 975         uint32_t cd_cmd, hdr_len, cd_tso_len;
 976
 977         if (!tx_offload.l4_len) {
 978                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 979                 return ctx_desc;
 980         }
 981
 982         /**
 983          * in case of non tunneling packet, the outer_l2_len and
 984          * outer_l3_len must be 0.
 985          */
 986         hdr_len = tx_offload.outer_l2_len +
 987                 tx_offload.outer_l3_len +
 988                 tx_offload.l2_len +
 989                 tx_offload.l3_len +
 990                 tx_offload.l4_len;
 991
 992         cd_cmd = I40E_TX_CTX_DESC_TSO;
 993         cd_tso_len = mbuf->pkt_len - hdr_len;
 994         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 995                 ((uint64_t)cd_tso_len <<
 996                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 997                 ((uint64_t)mbuf->tso_segsz <<
 998                  I40E_TXD_CTX_QW1_MSS_SHIFT);
 999
1000         return ctx_desc;
1001 }
1002
1003 uint16_t
1004 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1005 {
1006         struct i40e_tx_queue *txq;
1007         struct i40e_tx_entry *sw_ring;
1008         struct i40e_tx_entry *txe, *txn;
1009         volatile struct i40e_tx_desc *txd;
1010         volatile struct i40e_tx_desc *txr;
1011         struct rte_mbuf *tx_pkt;
1012         struct rte_mbuf *m_seg;
1013         uint32_t cd_tunneling_params;
1014         uint16_t tx_id;
1015         uint16_t nb_tx;
1016         uint32_t td_cmd;
1017         uint32_t td_offset;
1018         uint32_t td_tag;
1019         uint64_t ol_flags;
1020         uint16_t nb_used;
1021         uint16_t nb_ctx;
1022         uint16_t tx_last;
1023         uint16_t slen;
1024         uint64_t buf_dma_addr;
1025         union i40e_tx_offload tx_offload = {0};
1026
1027         txq = tx_queue;
1028         sw_ring = txq->sw_ring;
1029         txr = txq->tx_ring;
1030         tx_id = txq->tx_tail;
1031         txe = &sw_ring[tx_id];
1032
1033         /* Check if the descriptor ring needs to be cleaned. */
1034         if (txq->nb_tx_free < txq->tx_free_thresh)
1035                 i40e_xmit_cleanup(txq);
1036
1037         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1038                 td_cmd = 0;
1039                 td_tag = 0;
1040                 td_offset = 0;
1041
1042                 tx_pkt = *tx_pkts++;
1043                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1044
1045                 ol_flags = tx_pkt->ol_flags;
1046                 tx_offload.l2_len = tx_pkt->l2_len;
1047                 tx_offload.l3_len = tx_pkt->l3_len;
1048                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1049                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1050                 tx_offload.l4_len = tx_pkt->l4_len;
1051                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1052
1053                 /* Calculate the number of context descriptors needed. */
1054                 nb_ctx = i40e_calc_context_desc(ol_flags);
1055
1056                 /**
1057                  * The number of descriptors that must be allocated for
1058                  * a packet equals to the number of the segments of that
1059                  * packet plus 1 context descriptor if needed.
1060                  */
1061                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1062                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1063
1064                 /* Circular ring */
1065                 if (tx_last >= txq->nb_tx_desc)
1066                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1067
1068                 if (nb_used > txq->nb_tx_free) {
1069                         if (i40e_xmit_cleanup(txq) != 0) {
1070                                 if (nb_tx == 0)
1071                                         return 0;
1072                                 goto end_of_tx;
1073                         }
1074                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1075                                 while (nb_used > txq->nb_tx_free) {
1076                                         if (i40e_xmit_cleanup(txq) != 0) {
1077                                                 if (nb_tx == 0)
1078                                                         return 0;
1079                                                 goto end_of_tx;
1080                                         }
1081                                 }
1082                         }
1083                 }
1084
1085                 /* Descriptor based VLAN insertion */
1086                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1087                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1088                         td_tag = tx_pkt->vlan_tci;
1089                 }
1090
1091                 /* Always enable CRC offload insertion */
1092                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1093
1094                 /* Fill in tunneling parameters if necessary */
1095                 cd_tunneling_params = 0;
1096                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1097                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1098                                                     &cd_tunneling_params);
1099                 /* Enable checksum offloading */
1100                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1101                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1102                                                  &td_offset, tx_offload);
1103
1104                 if (nb_ctx) {
1105                         /* Setup TX context descriptor if required */
1106                         volatile struct i40e_tx_context_desc *ctx_txd =
1107                                 (volatile struct i40e_tx_context_desc *)\
1108                                                         &txr[tx_id];
1109                         uint16_t cd_l2tag2 = 0;
1110                         uint64_t cd_type_cmd_tso_mss =
1111                                 I40E_TX_DESC_DTYPE_CONTEXT;
1112
1113                         txn = &sw_ring[txe->next_id];
1114                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1115                         if (txe->mbuf != NULL) {
1116                                 rte_pktmbuf_free_seg(txe->mbuf);
1117                                 txe->mbuf = NULL;
1118                         }
1119
1120                         /* TSO enabled means no timestamp */
1121                         if (ol_flags & PKT_TX_TCP_SEG)
1122                                 cd_type_cmd_tso_mss |=
1123                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1124                         else {
1125 #ifdef RTE_LIBRTE_IEEE1588
1126                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1127                                         cd_type_cmd_tso_mss |=
1128                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1129                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1130 #endif
1131                         }
1132
1133                         ctx_txd->tunneling_params =
1134                                 rte_cpu_to_le_32(cd_tunneling_params);
1135                         if (ol_flags & PKT_TX_QINQ_PKT) {
1136                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1137                                 cd_type_cmd_tso_mss |=
1138                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1139                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1140                         }
1141                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1142                         ctx_txd->type_cmd_tso_mss =
1143                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1144
1145                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1146                                 "tunneling_params: %#x;\n"
1147                                 "l2tag2: %#hx;\n"
1148                                 "rsvd: %#hx;\n"
1149                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1150                                 tx_pkt, tx_id,
1151                                 ctx_txd->tunneling_params,
1152                                 ctx_txd->l2tag2,
1153                                 ctx_txd->rsvd,
1154                                 ctx_txd->type_cmd_tso_mss);
1155
1156                         txe->last_id = tx_last;
1157                         tx_id = txe->next_id;
1158                         txe = txn;
1159                 }
1160
1161                 m_seg = tx_pkt;
1162                 do {
1163                         txd = &txr[tx_id];
1164                         txn = &sw_ring[txe->next_id];
1165
1166                         if (txe->mbuf)
1167                                 rte_pktmbuf_free_seg(txe->mbuf);
1168                         txe->mbuf = m_seg;
1169
1170                         /* Setup TX Descriptor */
1171                         slen = m_seg->data_len;
1172                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1173
1174                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1175                                 "buf_dma_addr: %#"PRIx64";\n"
1176                                 "td_cmd: %#x;\n"
1177                                 "td_offset: %#x;\n"
1178                                 "td_len: %u;\n"
1179                                 "td_tag: %#x;\n",
1180                                 tx_pkt, tx_id, buf_dma_addr,
1181                                 td_cmd, td_offset, slen, td_tag);
1182
1183                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1184                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1185                                                 td_offset, slen, td_tag);
1186                         txe->last_id = tx_last;
1187                         tx_id = txe->next_id;
1188                         txe = txn;
1189                         m_seg = m_seg->next;
1190                 } while (m_seg != NULL);
1191
1192                 /* The last packet data descriptor needs End Of Packet (EOP) */
1193                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1194                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1195                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1196
1197                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1198                         PMD_TX_FREE_LOG(DEBUG,
1199                                         "Setting RS bit on TXD id="
1200                                         "%4u (port=%d queue=%d)",
1201                                         tx_last, txq->port_id, txq->queue_id);
1202
1203                         td_cmd |= I40E_TX_DESC_CMD_RS;
1204
1205                         /* Update txq RS bit counters */
1206                         txq->nb_tx_used = 0;
1207                 }
1208
1209                 txd->cmd_type_offset_bsz |=
1210                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1211                                         I40E_TXD_QW1_CMD_SHIFT);
1212         }
1213
1214 end_of_tx:
1215         rte_wmb();
1216
1217         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1218                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1219                    (unsigned) tx_id, (unsigned) nb_tx);
1220
1221         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1222         txq->tx_tail = tx_id;
1223
1224         return nb_tx;
1225 }
1226
1227 static __rte_always_inline int
1228 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1229 {
1230         struct i40e_tx_entry *txep;
1231         uint16_t i;
1232
1233         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1234                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1235                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1236                 return 0;
1237
1238         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1239
1240         for (i = 0; i < txq->tx_rs_thresh; i++)
1241                 rte_prefetch0((txep + i)->mbuf);
1242
1243         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1244                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1245                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1246                         txep->mbuf = NULL;
1247                 }
1248         } else {
1249                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1250                         rte_pktmbuf_free_seg(txep->mbuf);
1251                         txep->mbuf = NULL;
1252                 }
1253         }
1254
1255         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1256         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1257         if (txq->tx_next_dd >= txq->nb_tx_desc)
1258                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1259
1260         return txq->tx_rs_thresh;
1261 }
1262
1263 /* Populate 4 descriptors with data from 4 mbufs */
1264 static inline void
1265 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1266 {
1267         uint64_t dma_addr;
1268         uint32_t i;
1269
1270         for (i = 0; i < 4; i++, txdp++, pkts++) {
1271                 dma_addr = rte_mbuf_data_iova(*pkts);
1272                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1273                 txdp->cmd_type_offset_bsz =
1274                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1275                                         (*pkts)->data_len, 0);
1276         }
1277 }
1278
1279 /* Populate 1 descriptor with data from 1 mbuf */
1280 static inline void
1281 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1282 {
1283         uint64_t dma_addr;
1284
1285         dma_addr = rte_mbuf_data_iova(*pkts);
1286         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1287         txdp->cmd_type_offset_bsz =
1288                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1289                                 (*pkts)->data_len, 0);
1290 }
1291
1292 /* Fill hardware descriptor ring with mbuf data */
1293 static inline void
1294 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1295                      struct rte_mbuf **pkts,
1296                      uint16_t nb_pkts)
1297 {
1298         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1299         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1300         const int N_PER_LOOP = 4;
1301         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1302         int mainpart, leftover;
1303         int i, j;
1304
1305         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1306         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1307         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1308                 for (j = 0; j < N_PER_LOOP; ++j) {
1309                         (txep + i + j)->mbuf = *(pkts + i + j);
1310                 }
1311                 tx4(txdp + i, pkts + i);
1312         }
1313         if (unlikely(leftover > 0)) {
1314                 for (i = 0; i < leftover; ++i) {
1315                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1316                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1317                 }
1318         }
1319 }
1320
1321 static inline uint16_t
1322 tx_xmit_pkts(struct i40e_tx_queue *txq,
1323              struct rte_mbuf **tx_pkts,
1324              uint16_t nb_pkts)
1325 {
1326         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1327         uint16_t n = 0;
1328
1329         /**
1330          * Begin scanning the H/W ring for done descriptors when the number
1331          * of available descriptors drops below tx_free_thresh. For each done
1332          * descriptor, free the associated buffer.
1333          */
1334         if (txq->nb_tx_free < txq->tx_free_thresh)
1335                 i40e_tx_free_bufs(txq);
1336
1337         /* Use available descriptor only */
1338         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1339         if (unlikely(!nb_pkts))
1340                 return 0;
1341
1342         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1343         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1344                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1345                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1346                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1347                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1348                                                 I40E_TXD_QW1_CMD_SHIFT);
1349                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1350                 txq->tx_tail = 0;
1351         }
1352
1353         /* Fill hardware descriptor ring with mbuf data */
1354         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1355         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1356
1357         /* Determin if RS bit needs to be set */
1358         if (txq->tx_tail > txq->tx_next_rs) {
1359                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1360                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1361                                                 I40E_TXD_QW1_CMD_SHIFT);
1362                 txq->tx_next_rs =
1363                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1364                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1365                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1366         }
1367
1368         if (txq->tx_tail >= txq->nb_tx_desc)
1369                 txq->tx_tail = 0;
1370
1371         /* Update the tx tail register */
1372         rte_wmb();
1373         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1374
1375         return nb_pkts;
1376 }
1377
1378 static uint16_t
1379 i40e_xmit_pkts_simple(void *tx_queue,
1380                       struct rte_mbuf **tx_pkts,
1381                       uint16_t nb_pkts)
1382 {
1383         uint16_t nb_tx = 0;
1384
1385         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1386                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1387                                                 tx_pkts, nb_pkts);
1388
1389         while (nb_pkts) {
1390                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1391                                                 I40E_TX_MAX_BURST);
1392
1393                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1394                                                 &tx_pkts[nb_tx], num);
1395                 nb_tx = (uint16_t)(nb_tx + ret);
1396                 nb_pkts = (uint16_t)(nb_pkts - ret);
1397                 if (ret < num)
1398                         break;
1399         }
1400
1401         return nb_tx;
1402 }
1403
1404 static uint16_t
1405 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1406                    uint16_t nb_pkts)
1407 {
1408         uint16_t nb_tx = 0;
1409         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1410
1411         while (nb_pkts) {
1412                 uint16_t ret, num;
1413
1414                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1415                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1416                                                 num);
1417                 nb_tx += ret;
1418                 nb_pkts -= ret;
1419                 if (ret < num)
1420                         break;
1421         }
1422
1423         return nb_tx;
1424 }
1425
1426 /*********************************************************************
1427  *
1428  *  TX prep functions
1429  *
1430  **********************************************************************/
1431 uint16_t
1432 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1433                 uint16_t nb_pkts)
1434 {
1435         int i, ret;
1436         uint64_t ol_flags;
1437         struct rte_mbuf *m;
1438
1439         for (i = 0; i < nb_pkts; i++) {
1440                 m = tx_pkts[i];
1441                 ol_flags = m->ol_flags;
1442
1443                 /* Check for m->nb_segs to not exceed the limits. */
1444                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1445                         if (m->nb_segs > I40E_TX_MAX_SEG ||
1446                             m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1447                                 rte_errno = -EINVAL;
1448                                 return i;
1449                         }
1450                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1451                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1452                         /* MSS outside the range (256B - 9674B) are considered
1453                          * malicious
1454                          */
1455                         rte_errno = -EINVAL;
1456                         return i;
1457                 }
1458
1459                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1460                         rte_errno = -ENOTSUP;
1461                         return i;
1462                 }
1463
1464 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1465                 ret = rte_validate_tx_offload(m);
1466                 if (ret != 0) {
1467                         rte_errno = ret;
1468                         return i;
1469                 }
1470 #endif
1471                 ret = rte_net_intel_cksum_prepare(m);
1472                 if (ret != 0) {
1473                         rte_errno = ret;
1474                         return i;
1475                 }
1476         }
1477         return i;
1478 }
1479
1480 /*
1481  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1482  * application used, which assume having sequential ones. But from driver's
1483  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1484  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1485  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1486  * use queue_idx from 0 to 95 to access queues, while real queue would be
1487  * different. This function will do a queue mapping to find VSI the queue
1488  * belongs to.
1489  */
1490 static struct i40e_vsi*
1491 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1492 {
1493         /* the queue in MAIN VSI range */
1494         if (queue_idx < pf->main_vsi->nb_qps)
1495                 return pf->main_vsi;
1496
1497         queue_idx -= pf->main_vsi->nb_qps;
1498
1499         /* queue_idx is greater than VMDQ VSIs range */
1500         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1501                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1502                 return NULL;
1503         }
1504
1505         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1506 }
1507
1508 static uint16_t
1509 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1510 {
1511         /* the queue in MAIN VSI range */
1512         if (queue_idx < pf->main_vsi->nb_qps)
1513                 return queue_idx;
1514
1515         /* It's VMDQ queues */
1516         queue_idx -= pf->main_vsi->nb_qps;
1517
1518         if (pf->nb_cfg_vmdq_vsi)
1519                 return queue_idx % pf->vmdq_nb_qps;
1520         else {
1521                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1522                 return (uint16_t)(-1);
1523         }
1524 }
1525
1526 int
1527 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1528 {
1529         struct i40e_rx_queue *rxq;
1530         int err = -1;
1531         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1532
1533         PMD_INIT_FUNC_TRACE();
1534
1535         if (rx_queue_id < dev->data->nb_rx_queues) {
1536                 rxq = dev->data->rx_queues[rx_queue_id];
1537
1538                 err = i40e_alloc_rx_queue_mbufs(rxq);
1539                 if (err) {
1540                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1541                         return err;
1542                 }
1543
1544                 rte_wmb();
1545
1546                 /* Init the RX tail regieter. */
1547                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1548
1549                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1550
1551                 if (err) {
1552                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1553                                     rx_queue_id);
1554
1555                         i40e_rx_queue_release_mbufs(rxq);
1556                         i40e_reset_rx_queue(rxq);
1557                 } else
1558                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1559         }
1560
1561         return err;
1562 }
1563
1564 int
1565 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1566 {
1567         struct i40e_rx_queue *rxq;
1568         int err;
1569         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1570
1571         if (rx_queue_id < dev->data->nb_rx_queues) {
1572                 rxq = dev->data->rx_queues[rx_queue_id];
1573
1574                 /*
1575                 * rx_queue_id is queue id application refers to, while
1576                 * rxq->reg_idx is the real queue index.
1577                 */
1578                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1579
1580                 if (err) {
1581                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1582                                     rx_queue_id);
1583                         return err;
1584                 }
1585                 i40e_rx_queue_release_mbufs(rxq);
1586                 i40e_reset_rx_queue(rxq);
1587                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1588         }
1589
1590         return 0;
1591 }
1592
1593 int
1594 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1595 {
1596         int err = -1;
1597         struct i40e_tx_queue *txq;
1598         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1599
1600         PMD_INIT_FUNC_TRACE();
1601
1602         if (tx_queue_id < dev->data->nb_tx_queues) {
1603                 txq = dev->data->tx_queues[tx_queue_id];
1604
1605                 /*
1606                 * tx_queue_id is queue id application refers to, while
1607                 * rxq->reg_idx is the real queue index.
1608                 */
1609                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1610                 if (err)
1611                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1612                                     tx_queue_id);
1613                 else
1614                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1615         }
1616
1617         return err;
1618 }
1619
1620 int
1621 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1622 {
1623         struct i40e_tx_queue *txq;
1624         int err;
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626
1627         if (tx_queue_id < dev->data->nb_tx_queues) {
1628                 txq = dev->data->tx_queues[tx_queue_id];
1629
1630                 /*
1631                 * tx_queue_id is queue id application refers to, while
1632                 * txq->reg_idx is the real queue index.
1633                 */
1634                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1635
1636                 if (err) {
1637                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1638                                     tx_queue_id);
1639                         return err;
1640                 }
1641
1642                 i40e_tx_queue_release_mbufs(txq);
1643                 i40e_reset_tx_queue(txq);
1644                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1645         }
1646
1647         return 0;
1648 }
1649
1650 const uint32_t *
1651 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1652 {
1653         static const uint32_t ptypes[] = {
1654                 /* refers to i40e_rxd_pkt_type_mapping() */
1655                 RTE_PTYPE_L2_ETHER,
1656                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1657                 RTE_PTYPE_L2_ETHER_LLDP,
1658                 RTE_PTYPE_L2_ETHER_ARP,
1659                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1660                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1661                 RTE_PTYPE_L4_FRAG,
1662                 RTE_PTYPE_L4_ICMP,
1663                 RTE_PTYPE_L4_NONFRAG,
1664                 RTE_PTYPE_L4_SCTP,
1665                 RTE_PTYPE_L4_TCP,
1666                 RTE_PTYPE_L4_UDP,
1667                 RTE_PTYPE_TUNNEL_GRENAT,
1668                 RTE_PTYPE_TUNNEL_IP,
1669                 RTE_PTYPE_INNER_L2_ETHER,
1670                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1671                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1672                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1673                 RTE_PTYPE_INNER_L4_FRAG,
1674                 RTE_PTYPE_INNER_L4_ICMP,
1675                 RTE_PTYPE_INNER_L4_NONFRAG,
1676                 RTE_PTYPE_INNER_L4_SCTP,
1677                 RTE_PTYPE_INNER_L4_TCP,
1678                 RTE_PTYPE_INNER_L4_UDP,
1679                 RTE_PTYPE_UNKNOWN
1680         };
1681
1682         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1683 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1684             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1685 #endif
1686             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1687             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1688             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1689             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1690             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1691                 return ptypes;
1692         return NULL;
1693 }
1694
1695 static int
1696 i40e_check_rx_queue_offloads(struct rte_eth_dev *dev, uint64_t requested)
1697 {
1698         struct rte_eth_dev_info dev_info;
1699         uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1700         uint64_t supported; /* All per port offloads */
1701
1702         dev->dev_ops->dev_infos_get(dev, &dev_info);
1703         supported = dev_info.rx_offload_capa ^ dev_info.rx_queue_offload_capa;
1704         if ((requested & dev_info.rx_offload_capa) != requested)
1705                 return 0; /* requested range check */
1706         return !((mandatory ^ requested) & supported);
1707 }
1708
1709 int
1710 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1711                         uint16_t queue_idx,
1712                         uint16_t nb_desc,
1713                         unsigned int socket_id,
1714                         const struct rte_eth_rxconf *rx_conf,
1715                         struct rte_mempool *mp)
1716 {
1717         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1718         struct i40e_adapter *ad =
1719                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1720         struct i40e_vsi *vsi;
1721         struct i40e_pf *pf = NULL;
1722         struct i40e_vf *vf = NULL;
1723         struct i40e_rx_queue *rxq;
1724         const struct rte_memzone *rz;
1725         uint32_t ring_size;
1726         uint16_t len, i;
1727         uint16_t reg_idx, base, bsf, tc_mapping;
1728         int q_offset, use_def_burst_func = 1;
1729         struct rte_eth_dev_info dev_info;
1730
1731         if (!i40e_check_rx_queue_offloads(dev, rx_conf->offloads)) {
1732                 dev->dev_ops->dev_infos_get(dev, &dev_info);
1733                 PMD_INIT_LOG(ERR, "%p: Rx queue offloads 0x%" PRIx64
1734                         " don't match port  offloads 0x%" PRIx64
1735                         " or supported offloads 0x%" PRIx64,
1736                         (void *)dev, rx_conf->offloads,
1737                         dev->data->dev_conf.rxmode.offloads,
1738                         dev_info.rx_offload_capa);
1739                 return -ENOTSUP;
1740         }
1741
1742         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1743                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1744                 vsi = &vf->vsi;
1745                 if (!vsi)
1746                         return -EINVAL;
1747                 reg_idx = queue_idx;
1748         } else {
1749                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1750                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1751                 if (!vsi)
1752                         return -EINVAL;
1753                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1754                 if (q_offset < 0)
1755                         return -EINVAL;
1756                 reg_idx = vsi->base_queue + q_offset;
1757         }
1758
1759         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1760             (nb_desc > I40E_MAX_RING_DESC) ||
1761             (nb_desc < I40E_MIN_RING_DESC)) {
1762                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1763                             "invalid", nb_desc);
1764                 return -EINVAL;
1765         }
1766
1767         /* Free memory if needed */
1768         if (dev->data->rx_queues[queue_idx]) {
1769                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1770                 dev->data->rx_queues[queue_idx] = NULL;
1771         }
1772
1773         /* Allocate the rx queue data structure */
1774         rxq = rte_zmalloc_socket("i40e rx queue",
1775                                  sizeof(struct i40e_rx_queue),
1776                                  RTE_CACHE_LINE_SIZE,
1777                                  socket_id);
1778         if (!rxq) {
1779                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1780                             "rx queue data structure");
1781                 return -ENOMEM;
1782         }
1783         rxq->mp = mp;
1784         rxq->nb_rx_desc = nb_desc;
1785         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1786         rxq->queue_id = queue_idx;
1787         rxq->reg_idx = reg_idx;
1788         rxq->port_id = dev->data->port_id;
1789         rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.offloads &
1790                         DEV_RX_OFFLOAD_CRC_STRIP) ? 0 : ETHER_CRC_LEN);
1791         rxq->drop_en = rx_conf->rx_drop_en;
1792         rxq->vsi = vsi;
1793         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1794
1795         /* Allocate the maximun number of RX ring hardware descriptor. */
1796         len = I40E_MAX_RING_DESC;
1797
1798         /**
1799          * Allocating a little more memory because vectorized/bulk_alloc Rx
1800          * functions doesn't check boundaries each time.
1801          */
1802         len += RTE_PMD_I40E_RX_MAX_BURST;
1803
1804         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1805                               I40E_DMA_MEM_ALIGN);
1806
1807         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1808                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1809         if (!rz) {
1810                 i40e_dev_rx_queue_release(rxq);
1811                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1812                 return -ENOMEM;
1813         }
1814
1815         /* Zero all the descriptors in the ring. */
1816         memset(rz->addr, 0, ring_size);
1817
1818         rxq->rx_ring_phys_addr = rz->iova;
1819         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1820
1821         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1822
1823         /* Allocate the software ring. */
1824         rxq->sw_ring =
1825                 rte_zmalloc_socket("i40e rx sw ring",
1826                                    sizeof(struct i40e_rx_entry) * len,
1827                                    RTE_CACHE_LINE_SIZE,
1828                                    socket_id);
1829         if (!rxq->sw_ring) {
1830                 i40e_dev_rx_queue_release(rxq);
1831                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1832                 return -ENOMEM;
1833         }
1834
1835         i40e_reset_rx_queue(rxq);
1836         rxq->q_set = TRUE;
1837         dev->data->rx_queues[queue_idx] = rxq;
1838
1839         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1840
1841         if (!use_def_burst_func) {
1842 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1843                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1844                              "satisfied. Rx Burst Bulk Alloc function will be "
1845                              "used on port=%d, queue=%d.",
1846                              rxq->port_id, rxq->queue_id);
1847 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1848         } else {
1849                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1850                              "not satisfied, Scattered Rx is requested, "
1851                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1852                              "not enabled on port=%d, queue=%d.",
1853                              rxq->port_id, rxq->queue_id);
1854                 ad->rx_bulk_alloc_allowed = false;
1855         }
1856
1857         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1858                 if (!(vsi->enabled_tc & (1 << i)))
1859                         continue;
1860                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1861                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1862                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1863                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1864                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1865
1866                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1867                         rxq->dcb_tc = i;
1868         }
1869
1870         return 0;
1871 }
1872
1873 void
1874 i40e_dev_rx_queue_release(void *rxq)
1875 {
1876         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1877
1878         if (!q) {
1879                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1880                 return;
1881         }
1882
1883         i40e_rx_queue_release_mbufs(q);
1884         rte_free(q->sw_ring);
1885         rte_free(q);
1886 }
1887
1888 uint32_t
1889 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1890 {
1891 #define I40E_RXQ_SCAN_INTERVAL 4
1892         volatile union i40e_rx_desc *rxdp;
1893         struct i40e_rx_queue *rxq;
1894         uint16_t desc = 0;
1895
1896         rxq = dev->data->rx_queues[rx_queue_id];
1897         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1898         while ((desc < rxq->nb_rx_desc) &&
1899                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1900                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1901                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1902                 /**
1903                  * Check the DD bit of a rx descriptor of each 4 in a group,
1904                  * to avoid checking too frequently and downgrading performance
1905                  * too much.
1906                  */
1907                 desc += I40E_RXQ_SCAN_INTERVAL;
1908                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1909                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1910                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1911                                         desc - rxq->nb_rx_desc]);
1912         }
1913
1914         return desc;
1915 }
1916
1917 int
1918 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1919 {
1920         volatile union i40e_rx_desc *rxdp;
1921         struct i40e_rx_queue *rxq = rx_queue;
1922         uint16_t desc;
1923         int ret;
1924
1925         if (unlikely(offset >= rxq->nb_rx_desc)) {
1926                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1927                 return 0;
1928         }
1929
1930         desc = rxq->rx_tail + offset;
1931         if (desc >= rxq->nb_rx_desc)
1932                 desc -= rxq->nb_rx_desc;
1933
1934         rxdp = &(rxq->rx_ring[desc]);
1935
1936         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1937                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1938                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1939
1940         return ret;
1941 }
1942
1943 int
1944 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1945 {
1946         struct i40e_rx_queue *rxq = rx_queue;
1947         volatile uint64_t *status;
1948         uint64_t mask;
1949         uint32_t desc;
1950
1951         if (unlikely(offset >= rxq->nb_rx_desc))
1952                 return -EINVAL;
1953
1954         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1955                 return RTE_ETH_RX_DESC_UNAVAIL;
1956
1957         desc = rxq->rx_tail + offset;
1958         if (desc >= rxq->nb_rx_desc)
1959                 desc -= rxq->nb_rx_desc;
1960
1961         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1962         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1963                 << I40E_RXD_QW1_STATUS_SHIFT);
1964         if (*status & mask)
1965                 return RTE_ETH_RX_DESC_DONE;
1966
1967         return RTE_ETH_RX_DESC_AVAIL;
1968 }
1969
1970 int
1971 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1972 {
1973         struct i40e_tx_queue *txq = tx_queue;
1974         volatile uint64_t *status;
1975         uint64_t mask, expect;
1976         uint32_t desc;
1977
1978         if (unlikely(offset >= txq->nb_tx_desc))
1979                 return -EINVAL;
1980
1981         desc = txq->tx_tail + offset;
1982         /* go to next desc that has the RS bit */
1983         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1984                 txq->tx_rs_thresh;
1985         if (desc >= txq->nb_tx_desc) {
1986                 desc -= txq->nb_tx_desc;
1987                 if (desc >= txq->nb_tx_desc)
1988                         desc -= txq->nb_tx_desc;
1989         }
1990
1991         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1992         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
1993         expect = rte_cpu_to_le_64(
1994                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
1995         if ((*status & mask) == expect)
1996                 return RTE_ETH_TX_DESC_DONE;
1997
1998         return RTE_ETH_TX_DESC_FULL;
1999 }
2000
2001 static int
2002 i40e_check_tx_queue_offloads(struct rte_eth_dev *dev, uint64_t requested)
2003 {
2004         struct rte_eth_dev_info dev_info;
2005         uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
2006         uint64_t supported; /* All per port offloads */
2007
2008         dev->dev_ops->dev_infos_get(dev, &dev_info);
2009         supported = dev_info.tx_offload_capa ^ dev_info.tx_queue_offload_capa;
2010         if ((requested & dev_info.tx_offload_capa) != requested)
2011                 return 0; /* requested range check */
2012         return !((mandatory ^ requested) & supported);
2013 }
2014
2015 int
2016 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2017                         uint16_t queue_idx,
2018                         uint16_t nb_desc,
2019                         unsigned int socket_id,
2020                         const struct rte_eth_txconf *tx_conf)
2021 {
2022         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2023         struct i40e_vsi *vsi;
2024         struct i40e_pf *pf = NULL;
2025         struct i40e_vf *vf = NULL;
2026         struct i40e_tx_queue *txq;
2027         const struct rte_memzone *tz;
2028         uint32_t ring_size;
2029         uint16_t tx_rs_thresh, tx_free_thresh;
2030         uint16_t reg_idx, i, base, bsf, tc_mapping;
2031         int q_offset;
2032         struct rte_eth_dev_info dev_info;
2033
2034         if (!i40e_check_tx_queue_offloads(dev, tx_conf->offloads)) {
2035                 dev->dev_ops->dev_infos_get(dev, &dev_info);
2036                 PMD_INIT_LOG(ERR, "%p: Tx queue offloads 0x%" PRIx64
2037                         " don't match port  offloads 0x%" PRIx64
2038                         " or supported offloads 0x%" PRIx64,
2039                         (void *)dev, tx_conf->offloads,
2040                         dev->data->dev_conf.txmode.offloads,
2041                         dev_info.tx_offload_capa); }
2042
2043         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2044                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2045                 vsi = &vf->vsi;
2046                 if (!vsi)
2047                         return -EINVAL;
2048                 reg_idx = queue_idx;
2049         } else {
2050                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2051                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2052                 if (!vsi)
2053                         return -EINVAL;
2054                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2055                 if (q_offset < 0)
2056                         return -EINVAL;
2057                 reg_idx = vsi->base_queue + q_offset;
2058         }
2059
2060         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2061             (nb_desc > I40E_MAX_RING_DESC) ||
2062             (nb_desc < I40E_MIN_RING_DESC)) {
2063                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2064                             "invalid", nb_desc);
2065                 return -EINVAL;
2066         }
2067
2068         /**
2069          * The following two parameters control the setting of the RS bit on
2070          * transmit descriptors. TX descriptors will have their RS bit set
2071          * after txq->tx_rs_thresh descriptors have been used. The TX
2072          * descriptor ring will be cleaned after txq->tx_free_thresh
2073          * descriptors are used or if the number of descriptors required to
2074          * transmit a packet is greater than the number of free TX descriptors.
2075          *
2076          * The following constraints must be satisfied:
2077          *  - tx_rs_thresh must be greater than 0.
2078          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2079          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2080          *  - tx_rs_thresh must be a divisor of the ring size.
2081          *  - tx_free_thresh must be greater than 0.
2082          *  - tx_free_thresh must be less than the size of the ring minus 3.
2083          *
2084          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2085          * race condition, hence the maximum threshold constraints. When set
2086          * to zero use default values.
2087          */
2088         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2089                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2090         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2091                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2092         if (tx_rs_thresh >= (nb_desc - 2)) {
2093                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2094                              "number of TX descriptors minus 2. "
2095                              "(tx_rs_thresh=%u port=%d queue=%d)",
2096                              (unsigned int)tx_rs_thresh,
2097                              (int)dev->data->port_id,
2098                              (int)queue_idx);
2099                 return I40E_ERR_PARAM;
2100         }
2101         if (tx_free_thresh >= (nb_desc - 3)) {
2102                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2103                              "number of TX descriptors minus 3. "
2104                              "(tx_free_thresh=%u port=%d queue=%d)",
2105                              (unsigned int)tx_free_thresh,
2106                              (int)dev->data->port_id,
2107                              (int)queue_idx);
2108                 return I40E_ERR_PARAM;
2109         }
2110         if (tx_rs_thresh > tx_free_thresh) {
2111                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2112                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2113                              " tx_rs_thresh=%u port=%d queue=%d)",
2114                              (unsigned int)tx_free_thresh,
2115                              (unsigned int)tx_rs_thresh,
2116                              (int)dev->data->port_id,
2117                              (int)queue_idx);
2118                 return I40E_ERR_PARAM;
2119         }
2120         if ((nb_desc % tx_rs_thresh) != 0) {
2121                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2122                              "number of TX descriptors. (tx_rs_thresh=%u"
2123                              " port=%d queue=%d)",
2124                              (unsigned int)tx_rs_thresh,
2125                              (int)dev->data->port_id,
2126                              (int)queue_idx);
2127                 return I40E_ERR_PARAM;
2128         }
2129         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2130                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2131                              "tx_rs_thresh is greater than 1. "
2132                              "(tx_rs_thresh=%u port=%d queue=%d)",
2133                              (unsigned int)tx_rs_thresh,
2134                              (int)dev->data->port_id,
2135                              (int)queue_idx);
2136                 return I40E_ERR_PARAM;
2137         }
2138
2139         /* Free memory if needed. */
2140         if (dev->data->tx_queues[queue_idx]) {
2141                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2142                 dev->data->tx_queues[queue_idx] = NULL;
2143         }
2144
2145         /* Allocate the TX queue data structure. */
2146         txq = rte_zmalloc_socket("i40e tx queue",
2147                                   sizeof(struct i40e_tx_queue),
2148                                   RTE_CACHE_LINE_SIZE,
2149                                   socket_id);
2150         if (!txq) {
2151                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2152                             "tx queue structure");
2153                 return -ENOMEM;
2154         }
2155
2156         /* Allocate TX hardware ring descriptors. */
2157         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2158         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2159         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2160                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2161         if (!tz) {
2162                 i40e_dev_tx_queue_release(txq);
2163                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2164                 return -ENOMEM;
2165         }
2166
2167         txq->nb_tx_desc = nb_desc;
2168         txq->tx_rs_thresh = tx_rs_thresh;
2169         txq->tx_free_thresh = tx_free_thresh;
2170         txq->pthresh = tx_conf->tx_thresh.pthresh;
2171         txq->hthresh = tx_conf->tx_thresh.hthresh;
2172         txq->wthresh = tx_conf->tx_thresh.wthresh;
2173         txq->queue_id = queue_idx;
2174         txq->reg_idx = reg_idx;
2175         txq->port_id = dev->data->port_id;
2176         txq->txq_flags = tx_conf->txq_flags;
2177         txq->vsi = vsi;
2178         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2179
2180         txq->tx_ring_phys_addr = tz->iova;
2181         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2182
2183         /* Allocate software ring */
2184         txq->sw_ring =
2185                 rte_zmalloc_socket("i40e tx sw ring",
2186                                    sizeof(struct i40e_tx_entry) * nb_desc,
2187                                    RTE_CACHE_LINE_SIZE,
2188                                    socket_id);
2189         if (!txq->sw_ring) {
2190                 i40e_dev_tx_queue_release(txq);
2191                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2192                 return -ENOMEM;
2193         }
2194
2195         i40e_reset_tx_queue(txq);
2196         txq->q_set = TRUE;
2197         dev->data->tx_queues[queue_idx] = txq;
2198
2199         /* Use a simple TX queue without offloads or multi segs if possible */
2200         i40e_set_tx_function_flag(dev, txq);
2201
2202         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2203                 if (!(vsi->enabled_tc & (1 << i)))
2204                         continue;
2205                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2206                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2207                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2208                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2209                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2210
2211                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2212                         txq->dcb_tc = i;
2213         }
2214
2215         return 0;
2216 }
2217
2218 void
2219 i40e_dev_tx_queue_release(void *txq)
2220 {
2221         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2222
2223         if (!q) {
2224                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2225                 return;
2226         }
2227
2228         i40e_tx_queue_release_mbufs(q);
2229         rte_free(q->sw_ring);
2230         rte_free(q);
2231 }
2232
2233 const struct rte_memzone *
2234 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2235 {
2236         const struct rte_memzone *mz;
2237
2238         mz = rte_memzone_lookup(name);
2239         if (mz)
2240                 return mz;
2241
2242         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2243                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2244         return mz;
2245 }
2246
2247 void
2248 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2249 {
2250         uint16_t i;
2251
2252         /* SSE Vector driver has a different way of releasing mbufs. */
2253         if (rxq->rx_using_sse) {
2254                 i40e_rx_queue_release_mbufs_vec(rxq);
2255                 return;
2256         }
2257
2258         if (!rxq->sw_ring) {
2259                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2260                 return;
2261         }
2262
2263         for (i = 0; i < rxq->nb_rx_desc; i++) {
2264                 if (rxq->sw_ring[i].mbuf) {
2265                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2266                         rxq->sw_ring[i].mbuf = NULL;
2267                 }
2268         }
2269 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2270         if (rxq->rx_nb_avail == 0)
2271                 return;
2272         for (i = 0; i < rxq->rx_nb_avail; i++) {
2273                 struct rte_mbuf *mbuf;
2274
2275                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2276                 rte_pktmbuf_free_seg(mbuf);
2277         }
2278         rxq->rx_nb_avail = 0;
2279 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2280 }
2281
2282 void
2283 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2284 {
2285         unsigned i;
2286         uint16_t len;
2287
2288         if (!rxq) {
2289                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2290                 return;
2291         }
2292
2293 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2294         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2295                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2296         else
2297 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2298                 len = rxq->nb_rx_desc;
2299
2300         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2301                 ((volatile char *)rxq->rx_ring)[i] = 0;
2302
2303         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2304         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2305                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2306
2307 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2308         rxq->rx_nb_avail = 0;
2309         rxq->rx_next_avail = 0;
2310         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2311 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2312         rxq->rx_tail = 0;
2313         rxq->nb_rx_hold = 0;
2314         rxq->pkt_first_seg = NULL;
2315         rxq->pkt_last_seg = NULL;
2316
2317         rxq->rxrearm_start = 0;
2318         rxq->rxrearm_nb = 0;
2319 }
2320
2321 void
2322 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2323 {
2324         struct rte_eth_dev *dev;
2325         uint16_t i;
2326
2327         dev = &rte_eth_devices[txq->port_id];
2328
2329         if (!txq || !txq->sw_ring) {
2330                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2331                 return;
2332         }
2333
2334         /**
2335          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2336          *  so need to free remains more carefully.
2337          */
2338         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2339                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2340                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2341                 if (txq->tx_tail < i) {
2342                         for (; i < txq->nb_tx_desc; i++) {
2343                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2344                                 txq->sw_ring[i].mbuf = NULL;
2345                         }
2346                         i = 0;
2347                 }
2348                 for (; i < txq->tx_tail; i++) {
2349                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2350                         txq->sw_ring[i].mbuf = NULL;
2351                 }
2352         } else {
2353                 for (i = 0; i < txq->nb_tx_desc; i++) {
2354                         if (txq->sw_ring[i].mbuf) {
2355                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2356                                 txq->sw_ring[i].mbuf = NULL;
2357                         }
2358                 }
2359         }
2360 }
2361
2362 void
2363 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2364 {
2365         struct i40e_tx_entry *txe;
2366         uint16_t i, prev, size;
2367
2368         if (!txq) {
2369                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2370                 return;
2371         }
2372
2373         txe = txq->sw_ring;
2374         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2375         for (i = 0; i < size; i++)
2376                 ((volatile char *)txq->tx_ring)[i] = 0;
2377
2378         prev = (uint16_t)(txq->nb_tx_desc - 1);
2379         for (i = 0; i < txq->nb_tx_desc; i++) {
2380                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2381
2382                 txd->cmd_type_offset_bsz =
2383                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2384                 txe[i].mbuf =  NULL;
2385                 txe[i].last_id = i;
2386                 txe[prev].next_id = i;
2387                 prev = i;
2388         }
2389
2390         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2391         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2392
2393         txq->tx_tail = 0;
2394         txq->nb_tx_used = 0;
2395
2396         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2397         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2398 }
2399
2400 /* Init the TX queue in hardware */
2401 int
2402 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2403 {
2404         enum i40e_status_code err = I40E_SUCCESS;
2405         struct i40e_vsi *vsi = txq->vsi;
2406         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2407         uint16_t pf_q = txq->reg_idx;
2408         struct i40e_hmc_obj_txq tx_ctx;
2409         uint32_t qtx_ctl;
2410
2411         /* clear the context structure first */
2412         memset(&tx_ctx, 0, sizeof(tx_ctx));
2413         tx_ctx.new_context = 1;
2414         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2415         tx_ctx.qlen = txq->nb_tx_desc;
2416
2417 #ifdef RTE_LIBRTE_IEEE1588
2418         tx_ctx.timesync_ena = 1;
2419 #endif
2420         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2421         if (vsi->type == I40E_VSI_FDIR)
2422                 tx_ctx.fd_ena = TRUE;
2423
2424         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2425         if (err != I40E_SUCCESS) {
2426                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2427                 return err;
2428         }
2429
2430         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2431         if (err != I40E_SUCCESS) {
2432                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2433                 return err;
2434         }
2435
2436         /* Now associate this queue with this PCI function */
2437         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2438         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2439                                         I40E_QTX_CTL_PF_INDX_MASK);
2440         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2441         I40E_WRITE_FLUSH(hw);
2442
2443         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2444
2445         return err;
2446 }
2447
2448 int
2449 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2450 {
2451         struct i40e_rx_entry *rxe = rxq->sw_ring;
2452         uint64_t dma_addr;
2453         uint16_t i;
2454
2455         for (i = 0; i < rxq->nb_rx_desc; i++) {
2456                 volatile union i40e_rx_desc *rxd;
2457                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2458
2459                 if (unlikely(!mbuf)) {
2460                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2461                         return -ENOMEM;
2462                 }
2463
2464                 rte_mbuf_refcnt_set(mbuf, 1);
2465                 mbuf->next = NULL;
2466                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2467                 mbuf->nb_segs = 1;
2468                 mbuf->port = rxq->port_id;
2469
2470                 dma_addr =
2471                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2472
2473                 rxd = &rxq->rx_ring[i];
2474                 rxd->read.pkt_addr = dma_addr;
2475                 rxd->read.hdr_addr = 0;
2476 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2477                 rxd->read.rsvd1 = 0;
2478                 rxd->read.rsvd2 = 0;
2479 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2480
2481                 rxe[i].mbuf = mbuf;
2482         }
2483
2484         return 0;
2485 }
2486
2487 /*
2488  * Calculate the buffer length, and check the jumbo frame
2489  * and maximum packet length.
2490  */
2491 static int
2492 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2493 {
2494         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2495         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2496         struct rte_eth_dev_data *data = pf->dev_data;
2497         uint16_t buf_size, len;
2498
2499         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2500                 RTE_PKTMBUF_HEADROOM);
2501
2502         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2503                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2504         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2505                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2506                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2507                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2508                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2509                 rxq->hs_mode = i40e_header_split_enabled;
2510                 break;
2511         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2512         default:
2513                 rxq->rx_hdr_len = 0;
2514                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2515                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2516                 rxq->hs_mode = i40e_header_split_none;
2517                 break;
2518         }
2519
2520         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2521         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2522         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2523                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2524                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2525                         PMD_DRV_LOG(ERR, "maximum packet length must "
2526                                     "be larger than %u and smaller than %u,"
2527                                     "as jumbo frame is enabled",
2528                                     (uint32_t)ETHER_MAX_LEN,
2529                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2530                         return I40E_ERR_CONFIG;
2531                 }
2532         } else {
2533                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2534                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2535                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2536                                     "larger than %u and smaller than %u, "
2537                                     "as jumbo frame is disabled",
2538                                     (uint32_t)ETHER_MIN_LEN,
2539                                     (uint32_t)ETHER_MAX_LEN);
2540                         return I40E_ERR_CONFIG;
2541                 }
2542         }
2543
2544         return 0;
2545 }
2546
2547 /* Init the RX queue in hardware */
2548 int
2549 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2550 {
2551         int err = I40E_SUCCESS;
2552         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2553         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2554         uint16_t pf_q = rxq->reg_idx;
2555         uint16_t buf_size;
2556         struct i40e_hmc_obj_rxq rx_ctx;
2557
2558         err = i40e_rx_queue_config(rxq);
2559         if (err < 0) {
2560                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2561                 return err;
2562         }
2563
2564         /* Clear the context structure first */
2565         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2566         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2567         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2568
2569         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2570         rx_ctx.qlen = rxq->nb_rx_desc;
2571 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2572         rx_ctx.dsize = 1;
2573 #endif
2574         rx_ctx.dtype = rxq->hs_mode;
2575         if (rxq->hs_mode)
2576                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2577         else
2578                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2579         rx_ctx.rxmax = rxq->max_pkt_len;
2580         rx_ctx.tphrdesc_ena = 1;
2581         rx_ctx.tphwdesc_ena = 1;
2582         rx_ctx.tphdata_ena = 1;
2583         rx_ctx.tphhead_ena = 1;
2584         rx_ctx.lrxqthresh = 2;
2585         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2586         rx_ctx.l2tsel = 1;
2587         /* showiv indicates if inner VLAN is stripped inside of tunnel
2588          * packet. When set it to 1, vlan information is stripped from
2589          * the inner header, but the hardware does not put it in the
2590          * descriptor. So set it zero by default.
2591          */
2592         rx_ctx.showiv = 0;
2593         rx_ctx.prefena = 1;
2594
2595         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2596         if (err != I40E_SUCCESS) {
2597                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2598                 return err;
2599         }
2600         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2601         if (err != I40E_SUCCESS) {
2602                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2603                 return err;
2604         }
2605
2606         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2607
2608         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2609                 RTE_PKTMBUF_HEADROOM);
2610
2611         /* Check if scattered RX needs to be used. */
2612         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2613                 dev_data->scattered_rx = 1;
2614         }
2615
2616         /* Init the RX tail regieter. */
2617         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2618
2619         return 0;
2620 }
2621
2622 void
2623 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2624 {
2625         uint16_t i;
2626
2627         PMD_INIT_FUNC_TRACE();
2628
2629         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2630                 if (!dev->data->tx_queues[i])
2631                         continue;
2632                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2633                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2634         }
2635
2636         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2637                 if (!dev->data->rx_queues[i])
2638                         continue;
2639                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2640                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2641         }
2642 }
2643
2644 void
2645 i40e_dev_free_queues(struct rte_eth_dev *dev)
2646 {
2647         uint16_t i;
2648
2649         PMD_INIT_FUNC_TRACE();
2650
2651         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2652                 if (!dev->data->rx_queues[i])
2653                         continue;
2654                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2655                 dev->data->rx_queues[i] = NULL;
2656         }
2657         dev->data->nb_rx_queues = 0;
2658
2659         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2660                 if (!dev->data->tx_queues[i])
2661                         continue;
2662                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2663                 dev->data->tx_queues[i] = NULL;
2664         }
2665         dev->data->nb_tx_queues = 0;
2666 }
2667
2668 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2669 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2670
2671 enum i40e_status_code
2672 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2673 {
2674         struct i40e_tx_queue *txq;
2675         const struct rte_memzone *tz = NULL;
2676         uint32_t ring_size;
2677         struct rte_eth_dev *dev;
2678
2679         if (!pf) {
2680                 PMD_DRV_LOG(ERR, "PF is not available");
2681                 return I40E_ERR_BAD_PTR;
2682         }
2683
2684         dev = pf->adapter->eth_dev;
2685
2686         /* Allocate the TX queue data structure. */
2687         txq = rte_zmalloc_socket("i40e fdir tx queue",
2688                                   sizeof(struct i40e_tx_queue),
2689                                   RTE_CACHE_LINE_SIZE,
2690                                   SOCKET_ID_ANY);
2691         if (!txq) {
2692                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2693                                         "tx queue structure.");
2694                 return I40E_ERR_NO_MEMORY;
2695         }
2696
2697         /* Allocate TX hardware ring descriptors. */
2698         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2699         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2700
2701         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2702                                       I40E_FDIR_QUEUE_ID, ring_size,
2703                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2704         if (!tz) {
2705                 i40e_dev_tx_queue_release(txq);
2706                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2707                 return I40E_ERR_NO_MEMORY;
2708         }
2709
2710         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2711         txq->queue_id = I40E_FDIR_QUEUE_ID;
2712         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2713         txq->vsi = pf->fdir.fdir_vsi;
2714
2715         txq->tx_ring_phys_addr = tz->iova;
2716         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2717         /*
2718          * don't need to allocate software ring and reset for the fdir
2719          * program queue just set the queue has been configured.
2720          */
2721         txq->q_set = TRUE;
2722         pf->fdir.txq = txq;
2723
2724         return I40E_SUCCESS;
2725 }
2726
2727 enum i40e_status_code
2728 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2729 {
2730         struct i40e_rx_queue *rxq;
2731         const struct rte_memzone *rz = NULL;
2732         uint32_t ring_size;
2733         struct rte_eth_dev *dev;
2734
2735         if (!pf) {
2736                 PMD_DRV_LOG(ERR, "PF is not available");
2737                 return I40E_ERR_BAD_PTR;
2738         }
2739
2740         dev = pf->adapter->eth_dev;
2741
2742         /* Allocate the RX queue data structure. */
2743         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2744                                   sizeof(struct i40e_rx_queue),
2745                                   RTE_CACHE_LINE_SIZE,
2746                                   SOCKET_ID_ANY);
2747         if (!rxq) {
2748                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2749                                         "rx queue structure.");
2750                 return I40E_ERR_NO_MEMORY;
2751         }
2752
2753         /* Allocate RX hardware ring descriptors. */
2754         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2755         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2756
2757         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2758                                       I40E_FDIR_QUEUE_ID, ring_size,
2759                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2760         if (!rz) {
2761                 i40e_dev_rx_queue_release(rxq);
2762                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2763                 return I40E_ERR_NO_MEMORY;
2764         }
2765
2766         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2767         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2768         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2769         rxq->vsi = pf->fdir.fdir_vsi;
2770
2771         rxq->rx_ring_phys_addr = rz->iova;
2772         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2773         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2774
2775         /*
2776          * Don't need to allocate software ring and reset for the fdir
2777          * rx queue, just set the queue has been configured.
2778          */
2779         rxq->q_set = TRUE;
2780         pf->fdir.rxq = rxq;
2781
2782         return I40E_SUCCESS;
2783 }
2784
2785 void
2786 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2787         struct rte_eth_rxq_info *qinfo)
2788 {
2789         struct i40e_rx_queue *rxq;
2790
2791         rxq = dev->data->rx_queues[queue_id];
2792
2793         qinfo->mp = rxq->mp;
2794         qinfo->scattered_rx = dev->data->scattered_rx;
2795         qinfo->nb_desc = rxq->nb_rx_desc;
2796
2797         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2798         qinfo->conf.rx_drop_en = rxq->drop_en;
2799         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2800         qinfo->conf.offloads = rxq->offloads;
2801 }
2802
2803 void
2804 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2805         struct rte_eth_txq_info *qinfo)
2806 {
2807         struct i40e_tx_queue *txq;
2808
2809         txq = dev->data->tx_queues[queue_id];
2810
2811         qinfo->nb_desc = txq->nb_tx_desc;
2812
2813         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2814         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2815         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2816
2817         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2818         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2819         qinfo->conf.txq_flags = txq->txq_flags;
2820         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2821 }
2822
2823 void __attribute__((cold))
2824 i40e_set_rx_function(struct rte_eth_dev *dev)
2825 {
2826         struct i40e_adapter *ad =
2827                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2828         uint16_t rx_using_sse, i;
2829         /* In order to allow Vector Rx there are a few configuration
2830          * conditions to be met and Rx Bulk Allocation should be allowed.
2831          */
2832         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2833                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2834                     !ad->rx_bulk_alloc_allowed) {
2835                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2836                                      " Vector Rx preconditions",
2837                                      dev->data->port_id);
2838
2839                         ad->rx_vec_allowed = false;
2840                 }
2841                 if (ad->rx_vec_allowed) {
2842                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2843                                 struct i40e_rx_queue *rxq =
2844                                         dev->data->rx_queues[i];
2845
2846                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2847                                         ad->rx_vec_allowed = false;
2848                                         break;
2849                                 }
2850                         }
2851                 }
2852         }
2853
2854         if (dev->data->scattered_rx) {
2855                 /* Set the non-LRO scattered callback: there are Vector and
2856                  * single allocation versions.
2857                  */
2858                 if (ad->rx_vec_allowed) {
2859                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2860                                             "callback (port=%d).",
2861                                      dev->data->port_id);
2862
2863                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2864 #ifdef RTE_ARCH_X86
2865                         /*
2866                          * since AVX frequency can be different to base
2867                          * frequency, limit use of AVX2 version to later
2868                          * plaforms, not all those that could theoretically
2869                          * run it.
2870                          */
2871                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2872                                 dev->rx_pkt_burst =
2873                                         i40e_recv_scattered_pkts_vec_avx2;
2874 #endif
2875                 } else {
2876                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2877                                            "allocation callback (port=%d).",
2878                                      dev->data->port_id);
2879                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2880                 }
2881         /* If parameters allow we are going to choose between the following
2882          * callbacks:
2883          *    - Vector
2884          *    - Bulk Allocation
2885          *    - Single buffer allocation (the simplest one)
2886          */
2887         } else if (ad->rx_vec_allowed) {
2888                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2889                                     "burst size no less than %d (port=%d).",
2890                              RTE_I40E_DESCS_PER_LOOP,
2891                              dev->data->port_id);
2892
2893                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2894 #ifdef RTE_ARCH_X86
2895                 /*
2896                  * since AVX frequency can be different to base
2897                  * frequency, limit use of AVX2 version to later
2898                  * plaforms, not all those that could theoretically
2899                  * run it.
2900                  */
2901                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2902                         dev->rx_pkt_burst = i40e_recv_pkts_vec_avx2;
2903 #endif
2904         } else if (ad->rx_bulk_alloc_allowed) {
2905                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2906                                     "satisfied. Rx Burst Bulk Alloc function "
2907                                     "will be used on port=%d.",
2908                              dev->data->port_id);
2909
2910                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2911         } else {
2912                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2913                                     "satisfied, or Scattered Rx is requested "
2914                                     "(port=%d).",
2915                              dev->data->port_id);
2916
2917                 dev->rx_pkt_burst = i40e_recv_pkts;
2918         }
2919
2920         /* Propagate information about RX function choice through all queues. */
2921         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2922                 rx_using_sse =
2923                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2924                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
2925                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
2926                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
2927
2928                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2929                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2930
2931                         if (rxq)
2932                                 rxq->rx_using_sse = rx_using_sse;
2933                 }
2934         }
2935 }
2936
2937 void __attribute__((cold))
2938 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2939 {
2940         struct i40e_adapter *ad =
2941                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2942
2943         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2944         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2945                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2946                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2947                         PMD_INIT_LOG(DEBUG, "Vector tx"
2948                                      " can be enabled on this txq.");
2949
2950                 } else {
2951                         ad->tx_vec_allowed = false;
2952                 }
2953         } else {
2954                 ad->tx_simple_allowed = false;
2955         }
2956 }
2957
2958 void __attribute__((cold))
2959 i40e_set_tx_function(struct rte_eth_dev *dev)
2960 {
2961         struct i40e_adapter *ad =
2962                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2963         int i;
2964
2965         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2966                 if (ad->tx_vec_allowed) {
2967                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2968                                 struct i40e_tx_queue *txq =
2969                                         dev->data->tx_queues[i];
2970
2971                                 if (txq && i40e_txq_vec_setup(txq)) {
2972                                         ad->tx_vec_allowed = false;
2973                                         break;
2974                                 }
2975                         }
2976                 }
2977         }
2978
2979         if (ad->tx_simple_allowed) {
2980                 if (ad->tx_vec_allowed) {
2981                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2982                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2983 #ifdef RTE_ARCH_X86
2984                         /*
2985                          * since AVX frequency can be different to base
2986                          * frequency, limit use of AVX2 version to later
2987                          * plaforms, not all those that could theoretically
2988                          * run it.
2989                          */
2990                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2991                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx2;
2992 #endif
2993                 } else {
2994                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2995                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2996                 }
2997                 dev->tx_pkt_prepare = NULL;
2998         } else {
2999                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3000                 dev->tx_pkt_burst = i40e_xmit_pkts;
3001                 dev->tx_pkt_prepare = i40e_prep_pkts;
3002         }
3003 }
3004
3005 void __attribute__((cold))
3006 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3007 {
3008         struct i40e_adapter *ad =
3009                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3010         int i;
3011
3012         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3013                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3014 }
3015
3016 void __attribute__((cold))
3017 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3018 {
3019         struct i40e_adapter *ad =
3020                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3021         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3022         int i;
3023
3024         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3025                 ad->pctypes_tbl[i] = 0ULL;
3026         ad->flow_types_mask = 0ULL;
3027         ad->pctypes_mask = 0ULL;
3028
3029         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3030                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3031         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3032                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3033         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3034                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3035         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3036                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3037         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3038                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3039         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3040                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3041         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3042                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3043         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3044                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3045         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3046                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3047         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3048                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3049         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3050                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3051
3052         if (hw->mac.type == I40E_MAC_X722) {
3053                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3054                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3055                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3056                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3057                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3058                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3059                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3060                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3061                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3062                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3063                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3064                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3065         }
3066
3067         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3068                 if (ad->pctypes_tbl[i])
3069                         ad->flow_types_mask |= (1ULL << i);
3070                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3071         }
3072 }
3073
3074 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3075 int __attribute__((weak))
3076 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3077 {
3078         return -1;
3079 }
3080
3081 uint16_t __attribute__((weak))
3082 i40e_recv_pkts_vec(
3083         void __rte_unused *rx_queue,
3084         struct rte_mbuf __rte_unused **rx_pkts,
3085         uint16_t __rte_unused nb_pkts)
3086 {
3087         return 0;
3088 }
3089
3090 uint16_t __attribute__((weak))
3091 i40e_recv_scattered_pkts_vec(
3092         void __rte_unused *rx_queue,
3093         struct rte_mbuf __rte_unused **rx_pkts,
3094         uint16_t __rte_unused nb_pkts)
3095 {
3096         return 0;
3097 }
3098
3099 uint16_t __attribute__((weak))
3100 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3101                         struct rte_mbuf __rte_unused **rx_pkts,
3102                         uint16_t __rte_unused nb_pkts)
3103 {
3104         return 0;
3105 }
3106
3107 uint16_t __attribute__((weak))
3108 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3109                         struct rte_mbuf __rte_unused **rx_pkts,
3110                         uint16_t __rte_unused nb_pkts)
3111 {
3112         return 0;
3113 }
3114
3115 int __attribute__((weak))
3116 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3117 {
3118         return -1;
3119 }
3120
3121 int __attribute__((weak))
3122 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3123 {
3124         return -1;
3125 }
3126
3127 void __attribute__((weak))
3128 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3129 {
3130         return;
3131 }
3132
3133 uint16_t __attribute__((weak))
3134 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3135                           struct rte_mbuf __rte_unused **tx_pkts,
3136                           uint16_t __rte_unused nb_pkts)
3137 {
3138         return 0;
3139 }
3140
3141 uint16_t __attribute__((weak))
3142 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3143                           struct rte_mbuf __rte_unused **tx_pkts,
3144                           uint16_t __rte_unused nb_pkts)
3145 {
3146         return 0;
3147 }