drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 #ifdef RTE_LIBRTE_IEEE1588
  46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  47 #else
  48 #define I40E_TX_IEEE1588_TMST 0
  49 #endif
  50
  51 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  52                 PKT_TX_IP_CKSUM |                \
  53                 PKT_TX_L4_MASK |                 \
  54                 PKT_TX_TCP_SEG |                 \
  55                 PKT_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (  \
  58                 PKT_TX_IP_CKSUM |       \
  59                 PKT_TX_L4_MASK |        \
  60                 PKT_TX_OUTER_IP_CKSUM | \
  61                 PKT_TX_TCP_SEG |        \
  62                 PKT_TX_QINQ_PKT |       \
  63                 PKT_TX_VLAN_PKT |       \
  64                 PKT_TX_TUNNEL_MASK |    \
  65                 I40E_TX_IEEE1588_TMST)
  66
  67 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  68                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  69
  70 static inline void
  71 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  72 {
  73         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  74                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  75                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  76                 mb->vlan_tci =
  77                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  78                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  79                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  80         } else {
  81                 mb->vlan_tci = 0;
  82         }
  83 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  84         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  85                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  86                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED | PKT_RX_QINQ |
  87                         PKT_RX_VLAN_STRIPPED | PKT_RX_VLAN;
  88                 mb->vlan_tci_outer = mb->vlan_tci;
  89                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  90                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  91                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  92                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  93         } else {
  94                 mb->vlan_tci_outer = 0;
  95         }
  96 #endif
  97         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
  98                    mb->vlan_tci, mb->vlan_tci_outer);
  99 }
 100
 101 /* Translate the rx descriptor status to pkt flags */
 102 static inline uint64_t
 103 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 104 {
 105         uint64_t flags;
 106
 107         /* Check if RSS_HASH */
 108         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 109                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 110                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 111
 112         /* Check if FDIR Match */
 113         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 114                                                         PKT_RX_FDIR : 0);
 115
 116         return flags;
 117 }
 118
 119 static inline uint64_t
 120 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 121 {
 122         uint64_t flags = 0;
 123         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 124
 125 #define I40E_RX_ERR_BITS 0x3f
 126         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 127                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 128                 return flags;
 129         }
 130
 131         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 132                 flags |= PKT_RX_IP_CKSUM_BAD;
 133         else
 134                 flags |= PKT_RX_IP_CKSUM_GOOD;
 135
 136         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 137                 flags |= PKT_RX_L4_CKSUM_BAD;
 138         else
 139                 flags |= PKT_RX_L4_CKSUM_GOOD;
 140
 141         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 142                 flags |= PKT_RX_EIP_CKSUM_BAD;
 143
 144         return flags;
 145 }
 146
 147 /* Function to check and set the ieee1588 timesync index and get the
 148  * appropriate flags.
 149  */
 150 #ifdef RTE_LIBRTE_IEEE1588
 151 static inline uint64_t
 152 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 153 {
 154         uint64_t pkt_flags = 0;
 155         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 156                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 157                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 158
 159         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 160                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 161                 pkt_flags = PKT_RX_IEEE1588_PTP;
 162         if (tsyn & 0x04) {
 163                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 164                 mb->timesync = tsyn & 0x03;
 165         }
 166
 167         return pkt_flags;
 168 }
 169 #endif
 170
 171 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 172 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 173 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 174 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 175 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 176
 177 static inline uint64_t
 178 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 179 {
 180         uint64_t flags = 0;
 181 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 182         uint16_t flexbh, flexbl;
 183
 184         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 185                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 186                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 187         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 188                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 189                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 190
 191
 192         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 193                 mb->hash.fdir.hi =
 194                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 195                 flags |= PKT_RX_FDIR_ID;
 196         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 197                 mb->hash.fdir.hi =
 198                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 199                 flags |= PKT_RX_FDIR_FLX;
 200         }
 201         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 202                 mb->hash.fdir.lo =
 203                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 204                 flags |= PKT_RX_FDIR_FLX;
 205         }
 206 #else
 207         mb->hash.fdir.hi =
 208                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 209         flags |= PKT_RX_FDIR_ID;
 210 #endif
 211         return flags;
 212 }
 213
 214 static inline void
 215 i40e_parse_tunneling_params(uint64_t ol_flags,
 216                             union i40e_tx_offload tx_offload,
 217                             uint32_t *cd_tunneling)
 218 {
 219         /* EIPT: External (outer) IP header type */
 220         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 221                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 222         else if (ol_flags & PKT_TX_OUTER_IPV4)
 223                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 224         else if (ol_flags & PKT_TX_OUTER_IPV6)
 225                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 226
 227         /* EIPLEN: External (outer) IP header length, in DWords */
 228         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 229                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 230
 231         /* L4TUNT: L4 Tunneling Type */
 232         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 233         case PKT_TX_TUNNEL_IPIP:
 234                 /* for non UDP / GRE tunneling, set to 00b */
 235                 break;
 236         case PKT_TX_TUNNEL_VXLAN:
 237         case PKT_TX_TUNNEL_GENEVE:
 238                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 239                 break;
 240         case PKT_TX_TUNNEL_GRE:
 241                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 242                 break;
 243         default:
 244                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 245                 return;
 246         }
 247
 248         /* L4TUNLEN: L4 Tunneling Length, in Words
 249          *
 250          * We depend on app to set rte_mbuf.l2_len correctly.
 251          * For IP in GRE it should be set to the length of the GRE
 252          * header;
 253          * for MAC in GRE or MAC in UDP it should be set to the length
 254          * of the GRE or UDP headers plus the inner MAC up to including
 255          * its last Ethertype.
 256          */
 257         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 258                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 259 }
 260
 261 static inline void
 262 i40e_txd_enable_checksum(uint64_t ol_flags,
 263                         uint32_t *td_cmd,
 264                         uint32_t *td_offset,
 265                         union i40e_tx_offload tx_offload)
 266 {
 267         /* Set MACLEN */
 268         if (ol_flags & PKT_TX_TUNNEL_MASK)
 269                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 270                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 271         else
 272                 *td_offset |= (tx_offload.l2_len >> 1)
 273                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 274
 275         /* Enable L3 checksum offloads */
 276         if (ol_flags & PKT_TX_IP_CKSUM) {
 277                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 278                 *td_offset |= (tx_offload.l3_len >> 2)
 279                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 280         } else if (ol_flags & PKT_TX_IPV4) {
 281                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 282                 *td_offset |= (tx_offload.l3_len >> 2)
 283                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 284         } else if (ol_flags & PKT_TX_IPV6) {
 285                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 286                 *td_offset |= (tx_offload.l3_len >> 2)
 287                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 288         }
 289
 290         if (ol_flags & PKT_TX_TCP_SEG) {
 291                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 292                 *td_offset |= (tx_offload.l4_len >> 2)
 293                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 294                 return;
 295         }
 296
 297         /* Enable L4 checksum offloads */
 298         switch (ol_flags & PKT_TX_L4_MASK) {
 299         case PKT_TX_TCP_CKSUM:
 300                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 301                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 302                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 303                 break;
 304         case PKT_TX_SCTP_CKSUM:
 305                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 306                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 307                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 308                 break;
 309         case PKT_TX_UDP_CKSUM:
 310                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 311                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 312                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 313                 break;
 314         default:
 315                 break;
 316         }
 317 }
 318
 319 /* Construct the tx flags */
 320 static inline uint64_t
 321 i40e_build_ctob(uint32_t td_cmd,
 322                 uint32_t td_offset,
 323                 unsigned int size,
 324                 uint32_t td_tag)
 325 {
 326         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 327                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 328                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 329                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 330                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 331 }
 332
 333 static inline int
 334 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 335 {
 336         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 337         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 338         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 339         uint16_t nb_tx_desc = txq->nb_tx_desc;
 340         uint16_t desc_to_clean_to;
 341         uint16_t nb_tx_to_clean;
 342
 343         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 344         if (desc_to_clean_to >= nb_tx_desc)
 345                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 346
 347         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 348         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 349                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 350                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 351                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 352                         "(port=%d queue=%d)", desc_to_clean_to,
 353                                 txq->port_id, txq->queue_id);
 354                 return -1;
 355         }
 356
 357         if (last_desc_cleaned > desc_to_clean_to)
 358                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 359                                                         desc_to_clean_to);
 360         else
 361                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 362                                         last_desc_cleaned);
 363
 364         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 365
 366         txq->last_desc_cleaned = desc_to_clean_to;
 367         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 368
 369         return 0;
 370 }
 371
 372 static inline int
 373 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 374 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 375 #else
 376 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 377 #endif
 378 {
 379         int ret = 0;
 380
 381 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 382         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 383                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 384                              "rxq->rx_free_thresh=%d, "
 385                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 386                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 387                 ret = -EINVAL;
 388         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 389                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 390                              "rxq->rx_free_thresh=%d, "
 391                              "rxq->nb_rx_desc=%d",
 392                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 393                 ret = -EINVAL;
 394         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 395                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 396                              "rxq->nb_rx_desc=%d, "
 397                              "rxq->rx_free_thresh=%d",
 398                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 399                 ret = -EINVAL;
 400         }
 401 #else
 402         ret = -EINVAL;
 403 #endif
 404
 405         return ret;
 406 }
 407
 408 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 409 #define I40E_LOOK_AHEAD 8
 410 #if (I40E_LOOK_AHEAD != 8)
 411 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 412 #endif
 413 static inline int
 414 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 415 {
 416         volatile union i40e_rx_desc *rxdp;
 417         struct i40e_rx_entry *rxep;
 418         struct rte_mbuf *mb;
 419         uint16_t pkt_len;
 420         uint64_t qword1;
 421         uint32_t rx_status;
 422         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 423         int32_t i, j, nb_rx = 0;
 424         uint64_t pkt_flags;
 425         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 426
 427         rxdp = &rxq->rx_ring[rxq->rx_tail];
 428         rxep = &rxq->sw_ring[rxq->rx_tail];
 429
 430         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 431         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 432                                 I40E_RXD_QW1_STATUS_SHIFT;
 433
 434         /* Make sure there is at least 1 packet to receive */
 435         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 436                 return 0;
 437
 438         /**
 439          * Scan LOOK_AHEAD descriptors at a time to determine which
 440          * descriptors reference packets that are ready to be received.
 441          */
 442         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 443                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 444                 /* Read desc statuses backwards to avoid race condition */
 445                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 446                         qword1 = rte_le_to_cpu_64(\
 447                                 rxdp[j].wb.qword1.status_error_len);
 448                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 449                                         I40E_RXD_QW1_STATUS_SHIFT;
 450                 }
 451
 452                 rte_smp_rmb();
 453
 454                 /* Compute how many status bits were set */
 455                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 456                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 457
 458                 nb_rx += nb_dd;
 459
 460                 /* Translate descriptor info to mbuf parameters */
 461                 for (j = 0; j < nb_dd; j++) {
 462                         mb = rxep[j].mbuf;
 463                         qword1 = rte_le_to_cpu_64(\
 464                                 rxdp[j].wb.qword1.status_error_len);
 465                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 466                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 467                         mb->data_len = pkt_len;
 468                         mb->pkt_len = pkt_len;
 469                         mb->ol_flags = 0;
 470                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 471                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 472                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 473                         mb->packet_type =
 474                                 ptype_tbl[(uint8_t)((qword1 &
 475                                 I40E_RXD_QW1_PTYPE_MASK) >>
 476                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 477                         if (pkt_flags & PKT_RX_RSS_HASH)
 478                                 mb->hash.rss = rte_le_to_cpu_32(\
 479                                         rxdp[j].wb.qword0.hi_dword.rss);
 480                         if (pkt_flags & PKT_RX_FDIR)
 481                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 482
 483 #ifdef RTE_LIBRTE_IEEE1588
 484                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 485 #endif
 486                         mb->ol_flags |= pkt_flags;
 487
 488                 }
 489
 490                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 491                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 492
 493                 if (nb_dd != I40E_LOOK_AHEAD)
 494                         break;
 495         }
 496
 497         /* Clear software ring entries */
 498         for (i = 0; i < nb_rx; i++)
 499                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 500
 501         return nb_rx;
 502 }
 503
 504 static inline uint16_t
 505 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 506                         struct rte_mbuf **rx_pkts,
 507                         uint16_t nb_pkts)
 508 {
 509         uint16_t i;
 510         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 511
 512         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 513
 514         for (i = 0; i < nb_pkts; i++)
 515                 rx_pkts[i] = stage[i];
 516
 517         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 518         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 519
 520         return nb_pkts;
 521 }
 522
 523 static inline int
 524 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 525 {
 526         volatile union i40e_rx_desc *rxdp;
 527         struct i40e_rx_entry *rxep;
 528         struct rte_mbuf *mb;
 529         uint16_t alloc_idx, i;
 530         uint64_t dma_addr;
 531         int diag;
 532
 533         /* Allocate buffers in bulk */
 534         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 535                                 (rxq->rx_free_thresh - 1));
 536         rxep = &(rxq->sw_ring[alloc_idx]);
 537         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 538                                         rxq->rx_free_thresh);
 539         if (unlikely(diag != 0)) {
 540                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 541                 return -ENOMEM;
 542         }
 543
 544         rxdp = &rxq->rx_ring[alloc_idx];
 545         for (i = 0; i < rxq->rx_free_thresh; i++) {
 546                 if (likely(i < (rxq->rx_free_thresh - 1)))
 547                         /* Prefetch next mbuf */
 548                         rte_prefetch0(rxep[i + 1].mbuf);
 549
 550                 mb = rxep[i].mbuf;
 551                 rte_mbuf_refcnt_set(mb, 1);
 552                 mb->next = NULL;
 553                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 554                 mb->nb_segs = 1;
 555                 mb->port = rxq->port_id;
 556                 dma_addr = rte_cpu_to_le_64(\
 557                         rte_mbuf_data_iova_default(mb));
 558                 rxdp[i].read.hdr_addr = 0;
 559                 rxdp[i].read.pkt_addr = dma_addr;
 560         }
 561
 562         /* Update rx tail regsiter */
 563         rte_wmb();
 564         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 565
 566         rxq->rx_free_trigger =
 567                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 568         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 569                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 570
 571         return 0;
 572 }
 573
 574 static inline uint16_t
 575 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 576 {
 577         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 578         struct rte_eth_dev *dev;
 579         uint16_t nb_rx = 0;
 580
 581         if (!nb_pkts)
 582                 return 0;
 583
 584         if (rxq->rx_nb_avail)
 585                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 586
 587         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 588         rxq->rx_next_avail = 0;
 589         rxq->rx_nb_avail = nb_rx;
 590         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 591
 592         if (rxq->rx_tail > rxq->rx_free_trigger) {
 593                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 594                         uint16_t i, j;
 595
 596                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 597                         dev->data->rx_mbuf_alloc_failed +=
 598                                 rxq->rx_free_thresh;
 599
 600                         rxq->rx_nb_avail = 0;
 601                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 602                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 603                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 604
 605                         return 0;
 606                 }
 607         }
 608
 609         if (rxq->rx_tail >= rxq->nb_rx_desc)
 610                 rxq->rx_tail = 0;
 611
 612         if (rxq->rx_nb_avail)
 613                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 614
 615         return 0;
 616 }
 617
 618 static uint16_t
 619 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 620                           struct rte_mbuf **rx_pkts,
 621                           uint16_t nb_pkts)
 622 {
 623         uint16_t nb_rx = 0, n, count;
 624
 625         if (unlikely(nb_pkts == 0))
 626                 return 0;
 627
 628         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 629                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 630
 631         while (nb_pkts) {
 632                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 633                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 634                 nb_rx = (uint16_t)(nb_rx + count);
 635                 nb_pkts = (uint16_t)(nb_pkts - count);
 636                 if (count < n)
 637                         break;
 638         }
 639
 640         return nb_rx;
 641 }
 642 #else
 643 static uint16_t
 644 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 645                           struct rte_mbuf __rte_unused **rx_pkts,
 646                           uint16_t __rte_unused nb_pkts)
 647 {
 648         return 0;
 649 }
 650 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 651
 652 uint16_t
 653 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 654 {
 655         struct i40e_rx_queue *rxq;
 656         volatile union i40e_rx_desc *rx_ring;
 657         volatile union i40e_rx_desc *rxdp;
 658         union i40e_rx_desc rxd;
 659         struct i40e_rx_entry *sw_ring;
 660         struct i40e_rx_entry *rxe;
 661         struct rte_eth_dev *dev;
 662         struct rte_mbuf *rxm;
 663         struct rte_mbuf *nmb;
 664         uint16_t nb_rx;
 665         uint32_t rx_status;
 666         uint64_t qword1;
 667         uint16_t rx_packet_len;
 668         uint16_t rx_id, nb_hold;
 669         uint64_t dma_addr;
 670         uint64_t pkt_flags;
 671         uint32_t *ptype_tbl;
 672
 673         nb_rx = 0;
 674         nb_hold = 0;
 675         rxq = rx_queue;
 676         rx_id = rxq->rx_tail;
 677         rx_ring = rxq->rx_ring;
 678         sw_ring = rxq->sw_ring;
 679         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 680
 681         while (nb_rx < nb_pkts) {
 682                 rxdp = &rx_ring[rx_id];
 683                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 684                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 685                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 686
 687                 /* Check the DD bit first */
 688                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 689                         break;
 690
 691                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 692                 if (unlikely(!nmb)) {
 693                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 694                         dev->data->rx_mbuf_alloc_failed++;
 695                         break;
 696                 }
 697
 698                 rxd = *rxdp;
 699                 nb_hold++;
 700                 rxe = &sw_ring[rx_id];
 701                 rx_id++;
 702                 if (unlikely(rx_id == rxq->nb_rx_desc))
 703                         rx_id = 0;
 704
 705                 /* Prefetch next mbuf */
 706                 rte_prefetch0(sw_ring[rx_id].mbuf);
 707
 708                 /**
 709                  * When next RX descriptor is on a cache line boundary,
 710                  * prefetch the next 4 RX descriptors and next 8 pointers
 711                  * to mbufs.
 712                  */
 713                 if ((rx_id & 0x3) == 0) {
 714                         rte_prefetch0(&rx_ring[rx_id]);
 715                         rte_prefetch0(&sw_ring[rx_id]);
 716                 }
 717                 rxm = rxe->mbuf;
 718                 rxe->mbuf = nmb;
 719                 dma_addr =
 720                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 721                 rxdp->read.hdr_addr = 0;
 722                 rxdp->read.pkt_addr = dma_addr;
 723
 724                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 725                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 726
 727                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 728                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 729                 rxm->nb_segs = 1;
 730                 rxm->next = NULL;
 731                 rxm->pkt_len = rx_packet_len;
 732                 rxm->data_len = rx_packet_len;
 733                 rxm->port = rxq->port_id;
 734                 rxm->ol_flags = 0;
 735                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 736                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 737                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 738                 rxm->packet_type =
 739                         ptype_tbl[(uint8_t)((qword1 &
 740                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 741                 if (pkt_flags & PKT_RX_RSS_HASH)
 742                         rxm->hash.rss =
 743                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 744                 if (pkt_flags & PKT_RX_FDIR)
 745                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 746
 747 #ifdef RTE_LIBRTE_IEEE1588
 748                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 749 #endif
 750                 rxm->ol_flags |= pkt_flags;
 751
 752                 rx_pkts[nb_rx++] = rxm;
 753         }
 754         rxq->rx_tail = rx_id;
 755
 756         /**
 757          * If the number of free RX descriptors is greater than the RX free
 758          * threshold of the queue, advance the receive tail register of queue.
 759          * Update that register with the value of the last processed RX
 760          * descriptor minus 1.
 761          */
 762         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 763         if (nb_hold > rxq->rx_free_thresh) {
 764                 rx_id = (uint16_t) ((rx_id == 0) ?
 765                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 766                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 767                 nb_hold = 0;
 768         }
 769         rxq->nb_rx_hold = nb_hold;
 770
 771         return nb_rx;
 772 }
 773
 774 uint16_t
 775 i40e_recv_scattered_pkts(void *rx_queue,
 776                          struct rte_mbuf **rx_pkts,
 777                          uint16_t nb_pkts)
 778 {
 779         struct i40e_rx_queue *rxq = rx_queue;
 780         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 781         volatile union i40e_rx_desc *rxdp;
 782         union i40e_rx_desc rxd;
 783         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 784         struct i40e_rx_entry *rxe;
 785         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 786         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 787         struct rte_mbuf *nmb, *rxm;
 788         uint16_t rx_id = rxq->rx_tail;
 789         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 790         struct rte_eth_dev *dev;
 791         uint32_t rx_status;
 792         uint64_t qword1;
 793         uint64_t dma_addr;
 794         uint64_t pkt_flags;
 795         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 796
 797         while (nb_rx < nb_pkts) {
 798                 rxdp = &rx_ring[rx_id];
 799                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 800                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 801                                         I40E_RXD_QW1_STATUS_SHIFT;
 802
 803                 /* Check the DD bit */
 804                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 805                         break;
 806
 807                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 808                 if (unlikely(!nmb)) {
 809                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 810                         dev->data->rx_mbuf_alloc_failed++;
 811                         break;
 812                 }
 813
 814                 rxd = *rxdp;
 815                 nb_hold++;
 816                 rxe = &sw_ring[rx_id];
 817                 rx_id++;
 818                 if (rx_id == rxq->nb_rx_desc)
 819                         rx_id = 0;
 820
 821                 /* Prefetch next mbuf */
 822                 rte_prefetch0(sw_ring[rx_id].mbuf);
 823
 824                 /**
 825                  * When next RX descriptor is on a cache line boundary,
 826                  * prefetch the next 4 RX descriptors and next 8 pointers
 827                  * to mbufs.
 828                  */
 829                 if ((rx_id & 0x3) == 0) {
 830                         rte_prefetch0(&rx_ring[rx_id]);
 831                         rte_prefetch0(&sw_ring[rx_id]);
 832                 }
 833
 834                 rxm = rxe->mbuf;
 835                 rxe->mbuf = nmb;
 836                 dma_addr =
 837                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 838
 839                 /* Set data buffer address and data length of the mbuf */
 840                 rxdp->read.hdr_addr = 0;
 841                 rxdp->read.pkt_addr = dma_addr;
 842                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 843                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 844                 rxm->data_len = rx_packet_len;
 845                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 846
 847                 /**
 848                  * If this is the first buffer of the received packet, set the
 849                  * pointer to the first mbuf of the packet and initialize its
 850                  * context. Otherwise, update the total length and the number
 851                  * of segments of the current scattered packet, and update the
 852                  * pointer to the last mbuf of the current packet.
 853                  */
 854                 if (!first_seg) {
 855                         first_seg = rxm;
 856                         first_seg->nb_segs = 1;
 857                         first_seg->pkt_len = rx_packet_len;
 858                 } else {
 859                         first_seg->pkt_len =
 860                                 (uint16_t)(first_seg->pkt_len +
 861                                                 rx_packet_len);
 862                         first_seg->nb_segs++;
 863                         last_seg->next = rxm;
 864                 }
 865
 866                 /**
 867                  * If this is not the last buffer of the received packet,
 868                  * update the pointer to the last mbuf of the current scattered
 869                  * packet and continue to parse the RX ring.
 870                  */
 871                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 872                         last_seg = rxm;
 873                         continue;
 874                 }
 875
 876                 /**
 877                  * This is the last buffer of the received packet. If the CRC
 878                  * is not stripped by the hardware:
 879                  *  - Subtract the CRC length from the total packet length.
 880                  *  - If the last buffer only contains the whole CRC or a part
 881                  *  of it, free the mbuf associated to the last buffer. If part
 882                  *  of the CRC is also contained in the previous mbuf, subtract
 883                  *  the length of that CRC part from the data length of the
 884                  *  previous mbuf.
 885                  */
 886                 rxm->next = NULL;
 887                 if (unlikely(rxq->crc_len > 0)) {
 888                         first_seg->pkt_len -= ETHER_CRC_LEN;
 889                         if (rx_packet_len <= ETHER_CRC_LEN) {
 890                                 rte_pktmbuf_free_seg(rxm);
 891                                 first_seg->nb_segs--;
 892                                 last_seg->data_len =
 893                                         (uint16_t)(last_seg->data_len -
 894                                         (ETHER_CRC_LEN - rx_packet_len));
 895                                 last_seg->next = NULL;
 896                         } else
 897                                 rxm->data_len = (uint16_t)(rx_packet_len -
 898                                                                 ETHER_CRC_LEN);
 899                 }
 900
 901                 first_seg->port = rxq->port_id;
 902                 first_seg->ol_flags = 0;
 903                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 904                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 905                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 906                 first_seg->packet_type =
 907                         ptype_tbl[(uint8_t)((qword1 &
 908                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 909                 if (pkt_flags & PKT_RX_RSS_HASH)
 910                         first_seg->hash.rss =
 911                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 912                 if (pkt_flags & PKT_RX_FDIR)
 913                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 914
 915 #ifdef RTE_LIBRTE_IEEE1588
 916                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 917 #endif
 918                 first_seg->ol_flags |= pkt_flags;
 919
 920                 /* Prefetch data of first segment, if configured to do so. */
 921                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 922                         first_seg->data_off));
 923                 rx_pkts[nb_rx++] = first_seg;
 924                 first_seg = NULL;
 925         }
 926
 927         /* Record index of the next RX descriptor to probe. */
 928         rxq->rx_tail = rx_id;
 929         rxq->pkt_first_seg = first_seg;
 930         rxq->pkt_last_seg = last_seg;
 931
 932         /**
 933          * If the number of free RX descriptors is greater than the RX free
 934          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 935          * register. Update the RDT with the value of the last processed RX
 936          * descriptor minus 1, to guarantee that the RDT register is never
 937          * equal to the RDH register, which creates a "full" ring situtation
 938          * from the hardware point of view.
 939          */
 940         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 941         if (nb_hold > rxq->rx_free_thresh) {
 942                 rx_id = (uint16_t)(rx_id == 0 ?
 943                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 944                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 945                 nb_hold = 0;
 946         }
 947         rxq->nb_rx_hold = nb_hold;
 948
 949         return nb_rx;
 950 }
 951
 952 /* Check if the context descriptor is needed for TX offloading */
 953 static inline uint16_t
 954 i40e_calc_context_desc(uint64_t flags)
 955 {
 956         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 957                 PKT_TX_TCP_SEG |
 958                 PKT_TX_QINQ_PKT |
 959                 PKT_TX_TUNNEL_MASK;
 960
 961 #ifdef RTE_LIBRTE_IEEE1588
 962         mask |= PKT_TX_IEEE1588_TMST;
 963 #endif
 964
 965         return (flags & mask) ? 1 : 0;
 966 }
 967
 968 /* set i40e TSO context descriptor */
 969 static inline uint64_t
 970 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 971 {
 972         uint64_t ctx_desc = 0;
 973         uint32_t cd_cmd, hdr_len, cd_tso_len;
 974
 975         if (!tx_offload.l4_len) {
 976                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 977                 return ctx_desc;
 978         }
 979
 980         /**
 981          * in case of non tunneling packet, the outer_l2_len and
 982          * outer_l3_len must be 0.
 983          */
 984         hdr_len = tx_offload.outer_l2_len +
 985                 tx_offload.outer_l3_len +
 986                 tx_offload.l2_len +
 987                 tx_offload.l3_len +
 988                 tx_offload.l4_len;
 989
 990         cd_cmd = I40E_TX_CTX_DESC_TSO;
 991         cd_tso_len = mbuf->pkt_len - hdr_len;
 992         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 993                 ((uint64_t)cd_tso_len <<
 994                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 995                 ((uint64_t)mbuf->tso_segsz <<
 996                  I40E_TXD_CTX_QW1_MSS_SHIFT);
 997
 998         return ctx_desc;
 999 }
1000
1001 uint16_t
1002 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1003 {
1004         struct i40e_tx_queue *txq;
1005         struct i40e_tx_entry *sw_ring;
1006         struct i40e_tx_entry *txe, *txn;
1007         volatile struct i40e_tx_desc *txd;
1008         volatile struct i40e_tx_desc *txr;
1009         struct rte_mbuf *tx_pkt;
1010         struct rte_mbuf *m_seg;
1011         uint32_t cd_tunneling_params;
1012         uint16_t tx_id;
1013         uint16_t nb_tx;
1014         uint32_t td_cmd;
1015         uint32_t td_offset;
1016         uint32_t td_tag;
1017         uint64_t ol_flags;
1018         uint16_t nb_used;
1019         uint16_t nb_ctx;
1020         uint16_t tx_last;
1021         uint16_t slen;
1022         uint64_t buf_dma_addr;
1023         union i40e_tx_offload tx_offload = {0};
1024
1025         txq = tx_queue;
1026         sw_ring = txq->sw_ring;
1027         txr = txq->tx_ring;
1028         tx_id = txq->tx_tail;
1029         txe = &sw_ring[tx_id];
1030
1031         /* Check if the descriptor ring needs to be cleaned. */
1032         if (txq->nb_tx_free < txq->tx_free_thresh)
1033                 i40e_xmit_cleanup(txq);
1034
1035         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1036                 td_cmd = 0;
1037                 td_tag = 0;
1038                 td_offset = 0;
1039
1040                 tx_pkt = *tx_pkts++;
1041                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1042
1043                 ol_flags = tx_pkt->ol_flags;
1044                 tx_offload.l2_len = tx_pkt->l2_len;
1045                 tx_offload.l3_len = tx_pkt->l3_len;
1046                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1047                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1048                 tx_offload.l4_len = tx_pkt->l4_len;
1049                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1050
1051                 /* Calculate the number of context descriptors needed. */
1052                 nb_ctx = i40e_calc_context_desc(ol_flags);
1053
1054                 /**
1055                  * The number of descriptors that must be allocated for
1056                  * a packet equals to the number of the segments of that
1057                  * packet plus 1 context descriptor if needed.
1058                  */
1059                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1060                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1061
1062                 /* Circular ring */
1063                 if (tx_last >= txq->nb_tx_desc)
1064                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1065
1066                 if (nb_used > txq->nb_tx_free) {
1067                         if (i40e_xmit_cleanup(txq) != 0) {
1068                                 if (nb_tx == 0)
1069                                         return 0;
1070                                 goto end_of_tx;
1071                         }
1072                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1073                                 while (nb_used > txq->nb_tx_free) {
1074                                         if (i40e_xmit_cleanup(txq) != 0) {
1075                                                 if (nb_tx == 0)
1076                                                         return 0;
1077                                                 goto end_of_tx;
1078                                         }
1079                                 }
1080                         }
1081                 }
1082
1083                 /* Descriptor based VLAN insertion */
1084                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1085                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1086                         td_tag = tx_pkt->vlan_tci;
1087                 }
1088
1089                 /* Always enable CRC offload insertion */
1090                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1091
1092                 /* Fill in tunneling parameters if necessary */
1093                 cd_tunneling_params = 0;
1094                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1095                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1096                                                     &cd_tunneling_params);
1097                 /* Enable checksum offloading */
1098                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1099                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1100                                                  &td_offset, tx_offload);
1101
1102                 if (nb_ctx) {
1103                         /* Setup TX context descriptor if required */
1104                         volatile struct i40e_tx_context_desc *ctx_txd =
1105                                 (volatile struct i40e_tx_context_desc *)\
1106                                                         &txr[tx_id];
1107                         uint16_t cd_l2tag2 = 0;
1108                         uint64_t cd_type_cmd_tso_mss =
1109                                 I40E_TX_DESC_DTYPE_CONTEXT;
1110
1111                         txn = &sw_ring[txe->next_id];
1112                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1113                         if (txe->mbuf != NULL) {
1114                                 rte_pktmbuf_free_seg(txe->mbuf);
1115                                 txe->mbuf = NULL;
1116                         }
1117
1118                         /* TSO enabled means no timestamp */
1119                         if (ol_flags & PKT_TX_TCP_SEG)
1120                                 cd_type_cmd_tso_mss |=
1121                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1122                         else {
1123 #ifdef RTE_LIBRTE_IEEE1588
1124                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1125                                         cd_type_cmd_tso_mss |=
1126                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1127                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1128 #endif
1129                         }
1130
1131                         ctx_txd->tunneling_params =
1132                                 rte_cpu_to_le_32(cd_tunneling_params);
1133                         if (ol_flags & PKT_TX_QINQ_PKT) {
1134                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1135                                 cd_type_cmd_tso_mss |=
1136                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1137                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1138                         }
1139                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1140                         ctx_txd->type_cmd_tso_mss =
1141                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1142
1143                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1144                                 "tunneling_params: %#x;\n"
1145                                 "l2tag2: %#hx;\n"
1146                                 "rsvd: %#hx;\n"
1147                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1148                                 tx_pkt, tx_id,
1149                                 ctx_txd->tunneling_params,
1150                                 ctx_txd->l2tag2,
1151                                 ctx_txd->rsvd,
1152                                 ctx_txd->type_cmd_tso_mss);
1153
1154                         txe->last_id = tx_last;
1155                         tx_id = txe->next_id;
1156                         txe = txn;
1157                 }
1158
1159                 m_seg = tx_pkt;
1160                 do {
1161                         txd = &txr[tx_id];
1162                         txn = &sw_ring[txe->next_id];
1163
1164                         if (txe->mbuf)
1165                                 rte_pktmbuf_free_seg(txe->mbuf);
1166                         txe->mbuf = m_seg;
1167
1168                         /* Setup TX Descriptor */
1169                         slen = m_seg->data_len;
1170                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1171
1172                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1173                                 "buf_dma_addr: %#"PRIx64";\n"
1174                                 "td_cmd: %#x;\n"
1175                                 "td_offset: %#x;\n"
1176                                 "td_len: %u;\n"
1177                                 "td_tag: %#x;\n",
1178                                 tx_pkt, tx_id, buf_dma_addr,
1179                                 td_cmd, td_offset, slen, td_tag);
1180
1181                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1182                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1183                                                 td_offset, slen, td_tag);
1184                         txe->last_id = tx_last;
1185                         tx_id = txe->next_id;
1186                         txe = txn;
1187                         m_seg = m_seg->next;
1188                 } while (m_seg != NULL);
1189
1190                 /* The last packet data descriptor needs End Of Packet (EOP) */
1191                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1192                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1193                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1194
1195                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1196                         PMD_TX_FREE_LOG(DEBUG,
1197                                         "Setting RS bit on TXD id="
1198                                         "%4u (port=%d queue=%d)",
1199                                         tx_last, txq->port_id, txq->queue_id);
1200
1201                         td_cmd |= I40E_TX_DESC_CMD_RS;
1202
1203                         /* Update txq RS bit counters */
1204                         txq->nb_tx_used = 0;
1205                 }
1206
1207                 txd->cmd_type_offset_bsz |=
1208                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1209                                         I40E_TXD_QW1_CMD_SHIFT);
1210         }
1211
1212 end_of_tx:
1213         rte_wmb();
1214
1215         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1216                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1217                    (unsigned) tx_id, (unsigned) nb_tx);
1218
1219         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1220         txq->tx_tail = tx_id;
1221
1222         return nb_tx;
1223 }
1224
1225 static __rte_always_inline int
1226 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1227 {
1228         struct i40e_tx_entry *txep;
1229         uint16_t i;
1230
1231         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1232                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1233                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1234                 return 0;
1235
1236         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1237
1238         for (i = 0; i < txq->tx_rs_thresh; i++)
1239                 rte_prefetch0((txep + i)->mbuf);
1240
1241         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1242                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1243                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1244                         txep->mbuf = NULL;
1245                 }
1246         } else {
1247                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1248                         rte_pktmbuf_free_seg(txep->mbuf);
1249                         txep->mbuf = NULL;
1250                 }
1251         }
1252
1253         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1254         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1255         if (txq->tx_next_dd >= txq->nb_tx_desc)
1256                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1257
1258         return txq->tx_rs_thresh;
1259 }
1260
1261 /* Populate 4 descriptors with data from 4 mbufs */
1262 static inline void
1263 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1264 {
1265         uint64_t dma_addr;
1266         uint32_t i;
1267
1268         for (i = 0; i < 4; i++, txdp++, pkts++) {
1269                 dma_addr = rte_mbuf_data_iova(*pkts);
1270                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1271                 txdp->cmd_type_offset_bsz =
1272                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1273                                         (*pkts)->data_len, 0);
1274         }
1275 }
1276
1277 /* Populate 1 descriptor with data from 1 mbuf */
1278 static inline void
1279 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1280 {
1281         uint64_t dma_addr;
1282
1283         dma_addr = rte_mbuf_data_iova(*pkts);
1284         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1285         txdp->cmd_type_offset_bsz =
1286                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1287                                 (*pkts)->data_len, 0);
1288 }
1289
1290 /* Fill hardware descriptor ring with mbuf data */
1291 static inline void
1292 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1293                      struct rte_mbuf **pkts,
1294                      uint16_t nb_pkts)
1295 {
1296         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1297         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1298         const int N_PER_LOOP = 4;
1299         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1300         int mainpart, leftover;
1301         int i, j;
1302
1303         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1304         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1305         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1306                 for (j = 0; j < N_PER_LOOP; ++j) {
1307                         (txep + i + j)->mbuf = *(pkts + i + j);
1308                 }
1309                 tx4(txdp + i, pkts + i);
1310         }
1311         if (unlikely(leftover > 0)) {
1312                 for (i = 0; i < leftover; ++i) {
1313                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1314                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1315                 }
1316         }
1317 }
1318
1319 static inline uint16_t
1320 tx_xmit_pkts(struct i40e_tx_queue *txq,
1321              struct rte_mbuf **tx_pkts,
1322              uint16_t nb_pkts)
1323 {
1324         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1325         uint16_t n = 0;
1326
1327         /**
1328          * Begin scanning the H/W ring for done descriptors when the number
1329          * of available descriptors drops below tx_free_thresh. For each done
1330          * descriptor, free the associated buffer.
1331          */
1332         if (txq->nb_tx_free < txq->tx_free_thresh)
1333                 i40e_tx_free_bufs(txq);
1334
1335         /* Use available descriptor only */
1336         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1337         if (unlikely(!nb_pkts))
1338                 return 0;
1339
1340         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1341         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1342                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1343                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1344                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1345                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1346                                                 I40E_TXD_QW1_CMD_SHIFT);
1347                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1348                 txq->tx_tail = 0;
1349         }
1350
1351         /* Fill hardware descriptor ring with mbuf data */
1352         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1353         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1354
1355         /* Determin if RS bit needs to be set */
1356         if (txq->tx_tail > txq->tx_next_rs) {
1357                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1358                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1359                                                 I40E_TXD_QW1_CMD_SHIFT);
1360                 txq->tx_next_rs =
1361                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1362                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1363                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1364         }
1365
1366         if (txq->tx_tail >= txq->nb_tx_desc)
1367                 txq->tx_tail = 0;
1368
1369         /* Update the tx tail register */
1370         rte_wmb();
1371         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1372
1373         return nb_pkts;
1374 }
1375
1376 static uint16_t
1377 i40e_xmit_pkts_simple(void *tx_queue,
1378                       struct rte_mbuf **tx_pkts,
1379                       uint16_t nb_pkts)
1380 {
1381         uint16_t nb_tx = 0;
1382
1383         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1384                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1385                                                 tx_pkts, nb_pkts);
1386
1387         while (nb_pkts) {
1388                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1389                                                 I40E_TX_MAX_BURST);
1390
1391                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1392                                                 &tx_pkts[nb_tx], num);
1393                 nb_tx = (uint16_t)(nb_tx + ret);
1394                 nb_pkts = (uint16_t)(nb_pkts - ret);
1395                 if (ret < num)
1396                         break;
1397         }
1398
1399         return nb_tx;
1400 }
1401
1402 static uint16_t
1403 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1404                    uint16_t nb_pkts)
1405 {
1406         uint16_t nb_tx = 0;
1407         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1408
1409         while (nb_pkts) {
1410                 uint16_t ret, num;
1411
1412                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1413                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1414                                                 num);
1415                 nb_tx += ret;
1416                 nb_pkts -= ret;
1417                 if (ret < num)
1418                         break;
1419         }
1420
1421         return nb_tx;
1422 }
1423
1424 /*********************************************************************
1425  *
1426  *  TX prep functions
1427  *
1428  **********************************************************************/
1429 uint16_t
1430 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1431                 uint16_t nb_pkts)
1432 {
1433         int i, ret;
1434         uint64_t ol_flags;
1435         struct rte_mbuf *m;
1436
1437         for (i = 0; i < nb_pkts; i++) {
1438                 m = tx_pkts[i];
1439                 ol_flags = m->ol_flags;
1440
1441                 /* Check for m->nb_segs to not exceed the limits. */
1442                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1443                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG ||
1444                             m->pkt_len > I40E_FRAME_SIZE_MAX) {
1445                                 rte_errno = -EINVAL;
1446                                 return i;
1447                         }
1448                 } else if (m->nb_segs > I40E_TX_MAX_SEG ||
1449                            m->tso_segsz < I40E_MIN_TSO_MSS ||
1450                            m->tso_segsz > I40E_MAX_TSO_MSS ||
1451                            m->pkt_len > I40E_TSO_FRAME_SIZE_MAX) {
1452                         /* MSS outside the range (256B - 9674B) are considered
1453                          * malicious
1454                          */
1455                         rte_errno = -EINVAL;
1456                         return i;
1457                 }
1458
1459                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1460                         rte_errno = -ENOTSUP;
1461                         return i;
1462                 }
1463
1464                 /* check the size of packet */
1465                 if (m->pkt_len < I40E_TX_MIN_PKT_LEN) {
1466                         rte_errno = -EINVAL;
1467                         return i;
1468                 }
1469
1470 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1471                 ret = rte_validate_tx_offload(m);
1472                 if (ret != 0) {
1473                         rte_errno = ret;
1474                         return i;
1475                 }
1476 #endif
1477                 ret = rte_net_intel_cksum_prepare(m);
1478                 if (ret != 0) {
1479                         rte_errno = ret;
1480                         return i;
1481                 }
1482         }
1483         return i;
1484 }
1485
1486 /*
1487  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1488  * application used, which assume having sequential ones. But from driver's
1489  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1490  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1491  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1492  * use queue_idx from 0 to 95 to access queues, while real queue would be
1493  * different. This function will do a queue mapping to find VSI the queue
1494  * belongs to.
1495  */
1496 static struct i40e_vsi*
1497 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1498 {
1499         /* the queue in MAIN VSI range */
1500         if (queue_idx < pf->main_vsi->nb_qps)
1501                 return pf->main_vsi;
1502
1503         queue_idx -= pf->main_vsi->nb_qps;
1504
1505         /* queue_idx is greater than VMDQ VSIs range */
1506         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1507                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1508                 return NULL;
1509         }
1510
1511         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1512 }
1513
1514 static uint16_t
1515 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1516 {
1517         /* the queue in MAIN VSI range */
1518         if (queue_idx < pf->main_vsi->nb_qps)
1519                 return queue_idx;
1520
1521         /* It's VMDQ queues */
1522         queue_idx -= pf->main_vsi->nb_qps;
1523
1524         if (pf->nb_cfg_vmdq_vsi)
1525                 return queue_idx % pf->vmdq_nb_qps;
1526         else {
1527                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1528                 return (uint16_t)(-1);
1529         }
1530 }
1531
1532 int
1533 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1534 {
1535         struct i40e_rx_queue *rxq;
1536         int err;
1537         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1538
1539         PMD_INIT_FUNC_TRACE();
1540
1541         rxq = dev->data->rx_queues[rx_queue_id];
1542
1543         err = i40e_alloc_rx_queue_mbufs(rxq);
1544         if (err) {
1545                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1546                 return err;
1547         }
1548
1549         rte_wmb();
1550
1551         /* Init the RX tail regieter. */
1552         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1553
1554         err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1555         if (err) {
1556                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1557                             rx_queue_id);
1558
1559                 i40e_rx_queue_release_mbufs(rxq);
1560                 i40e_reset_rx_queue(rxq);
1561                 return err;
1562         }
1563         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1564
1565         return 0;
1566 }
1567
1568 int
1569 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1570 {
1571         struct i40e_rx_queue *rxq;
1572         int err;
1573         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1574
1575         rxq = dev->data->rx_queues[rx_queue_id];
1576
1577         /*
1578          * rx_queue_id is queue id application refers to, while
1579          * rxq->reg_idx is the real queue index.
1580          */
1581         err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1582         if (err) {
1583                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1584                             rx_queue_id);
1585                 return err;
1586         }
1587         i40e_rx_queue_release_mbufs(rxq);
1588         i40e_reset_rx_queue(rxq);
1589         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1590
1591         return 0;
1592 }
1593
1594 int
1595 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1596 {
1597         int err;
1598         struct i40e_tx_queue *txq;
1599         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1600
1601         PMD_INIT_FUNC_TRACE();
1602
1603         txq = dev->data->tx_queues[tx_queue_id];
1604
1605         /*
1606          * tx_queue_id is queue id application refers to, while
1607          * rxq->reg_idx is the real queue index.
1608          */
1609         err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1610         if (err) {
1611                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1612                             tx_queue_id);
1613                 return err;
1614         }
1615         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1616
1617         return 0;
1618 }
1619
1620 int
1621 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1622 {
1623         struct i40e_tx_queue *txq;
1624         int err;
1625         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1626
1627         txq = dev->data->tx_queues[tx_queue_id];
1628
1629         /*
1630          * tx_queue_id is queue id application refers to, while
1631          * txq->reg_idx is the real queue index.
1632          */
1633         err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1634         if (err) {
1635                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1636                             tx_queue_id);
1637                 return err;
1638         }
1639
1640         i40e_tx_queue_release_mbufs(txq);
1641         i40e_reset_tx_queue(txq);
1642         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1643
1644         return 0;
1645 }
1646
1647 const uint32_t *
1648 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1649 {
1650         static const uint32_t ptypes[] = {
1651                 /* refers to i40e_rxd_pkt_type_mapping() */
1652                 RTE_PTYPE_L2_ETHER,
1653                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1654                 RTE_PTYPE_L2_ETHER_LLDP,
1655                 RTE_PTYPE_L2_ETHER_ARP,
1656                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1657                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1658                 RTE_PTYPE_L4_FRAG,
1659                 RTE_PTYPE_L4_ICMP,
1660                 RTE_PTYPE_L4_NONFRAG,
1661                 RTE_PTYPE_L4_SCTP,
1662                 RTE_PTYPE_L4_TCP,
1663                 RTE_PTYPE_L4_UDP,
1664                 RTE_PTYPE_TUNNEL_GRENAT,
1665                 RTE_PTYPE_TUNNEL_IP,
1666                 RTE_PTYPE_INNER_L2_ETHER,
1667                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1668                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1669                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1670                 RTE_PTYPE_INNER_L4_FRAG,
1671                 RTE_PTYPE_INNER_L4_ICMP,
1672                 RTE_PTYPE_INNER_L4_NONFRAG,
1673                 RTE_PTYPE_INNER_L4_SCTP,
1674                 RTE_PTYPE_INNER_L4_TCP,
1675                 RTE_PTYPE_INNER_L4_UDP,
1676                 RTE_PTYPE_UNKNOWN
1677         };
1678
1679         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1680 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1681             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1682 #endif
1683             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1684             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1685             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1686             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1687             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1688                 return ptypes;
1689         return NULL;
1690 }
1691
1692 static int
1693 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1694 {
1695         uint16_t i;
1696
1697         for (i = 0; i < num; i++) {
1698                 if (i != idx && queues[i])
1699                         return 0;
1700         }
1701
1702         return 1;
1703 }
1704
1705 static int
1706 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1707                                 struct i40e_rx_queue *rxq)
1708 {
1709         struct i40e_adapter *ad =
1710                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1711         int use_def_burst_func =
1712                 check_rx_burst_bulk_alloc_preconditions(rxq);
1713         uint16_t buf_size =
1714                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1715                            RTE_PKTMBUF_HEADROOM);
1716         int use_scattered_rx =
1717                 ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size);
1718
1719         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1720                 PMD_DRV_LOG(ERR,
1721                             "Failed to do RX queue initialization");
1722                 return -EINVAL;
1723         }
1724
1725         if (i40e_dev_first_queue(rxq->queue_id,
1726                                  dev->data->rx_queues,
1727                                  dev->data->nb_rx_queues)) {
1728                 /**
1729                  * If it is the first queue to setup,
1730                  * set all flags to default and call
1731                  * i40e_set_rx_function.
1732                  */
1733                 ad->rx_bulk_alloc_allowed = true;
1734                 ad->rx_vec_allowed = true;
1735                 dev->data->scattered_rx = use_scattered_rx;
1736                 if (use_def_burst_func)
1737                         ad->rx_bulk_alloc_allowed = false;
1738                 i40e_set_rx_function(dev);
1739                 return 0;
1740         }
1741
1742         /* check bulk alloc conflict */
1743         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1744                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1745                 return -EINVAL;
1746         }
1747         /* check scatterred conflict */
1748         if (!dev->data->scattered_rx && use_scattered_rx) {
1749                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1750                 return -EINVAL;
1751         }
1752         /* check vector conflict */
1753         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1754                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1755                 return -EINVAL;
1756         }
1757
1758         return 0;
1759 }
1760
1761 int
1762 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1763                         uint16_t queue_idx,
1764                         uint16_t nb_desc,
1765                         unsigned int socket_id,
1766                         const struct rte_eth_rxconf *rx_conf,
1767                         struct rte_mempool *mp)
1768 {
1769         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1770         struct i40e_adapter *ad =
1771                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1772         struct i40e_vsi *vsi;
1773         struct i40e_pf *pf = NULL;
1774         struct i40e_vf *vf = NULL;
1775         struct i40e_rx_queue *rxq;
1776         const struct rte_memzone *rz;
1777         uint32_t ring_size;
1778         uint16_t len, i;
1779         uint16_t reg_idx, base, bsf, tc_mapping;
1780         int q_offset, use_def_burst_func = 1;
1781         uint64_t offloads;
1782
1783         offloads = rx_conf->offloads | dev->data->dev_conf.rxmode.offloads;
1784
1785         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1786                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1787                 vsi = &vf->vsi;
1788                 if (!vsi)
1789                         return -EINVAL;
1790                 reg_idx = queue_idx;
1791         } else {
1792                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1793                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1794                 if (!vsi)
1795                         return -EINVAL;
1796                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1797                 if (q_offset < 0)
1798                         return -EINVAL;
1799                 reg_idx = vsi->base_queue + q_offset;
1800         }
1801
1802         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1803             (nb_desc > I40E_MAX_RING_DESC) ||
1804             (nb_desc < I40E_MIN_RING_DESC)) {
1805                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1806                             "invalid", nb_desc);
1807                 return -EINVAL;
1808         }
1809
1810         /* Free memory if needed */
1811         if (dev->data->rx_queues[queue_idx]) {
1812                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1813                 dev->data->rx_queues[queue_idx] = NULL;
1814         }
1815
1816         /* Allocate the rx queue data structure */
1817         rxq = rte_zmalloc_socket("i40e rx queue",
1818                                  sizeof(struct i40e_rx_queue),
1819                                  RTE_CACHE_LINE_SIZE,
1820                                  socket_id);
1821         if (!rxq) {
1822                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1823                             "rx queue data structure");
1824                 return -ENOMEM;
1825         }
1826         rxq->mp = mp;
1827         rxq->nb_rx_desc = nb_desc;
1828         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1829         rxq->queue_id = queue_idx;
1830         rxq->reg_idx = reg_idx;
1831         rxq->port_id = dev->data->port_id;
1832         if (dev->data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_KEEP_CRC)
1833                 rxq->crc_len = ETHER_CRC_LEN;
1834         else
1835                 rxq->crc_len = 0;
1836         rxq->drop_en = rx_conf->rx_drop_en;
1837         rxq->vsi = vsi;
1838         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1839         rxq->offloads = offloads;
1840
1841         /* Allocate the maximun number of RX ring hardware descriptor. */
1842         len = I40E_MAX_RING_DESC;
1843
1844         /**
1845          * Allocating a little more memory because vectorized/bulk_alloc Rx
1846          * functions doesn't check boundaries each time.
1847          */
1848         len += RTE_PMD_I40E_RX_MAX_BURST;
1849
1850         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1851                               I40E_DMA_MEM_ALIGN);
1852
1853         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1854                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1855         if (!rz) {
1856                 i40e_dev_rx_queue_release(rxq);
1857                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1858                 return -ENOMEM;
1859         }
1860
1861         /* Zero all the descriptors in the ring. */
1862         memset(rz->addr, 0, ring_size);
1863
1864         rxq->rx_ring_phys_addr = rz->iova;
1865         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1866
1867         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1868
1869         /* Allocate the software ring. */
1870         rxq->sw_ring =
1871                 rte_zmalloc_socket("i40e rx sw ring",
1872                                    sizeof(struct i40e_rx_entry) * len,
1873                                    RTE_CACHE_LINE_SIZE,
1874                                    socket_id);
1875         if (!rxq->sw_ring) {
1876                 i40e_dev_rx_queue_release(rxq);
1877                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1878                 return -ENOMEM;
1879         }
1880
1881         i40e_reset_rx_queue(rxq);
1882         rxq->q_set = TRUE;
1883
1884         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1885                 if (!(vsi->enabled_tc & (1 << i)))
1886                         continue;
1887                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1888                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1889                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1890                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1891                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1892
1893                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1894                         rxq->dcb_tc = i;
1895         }
1896
1897         if (dev->data->dev_started) {
1898                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1899                         i40e_dev_rx_queue_release(rxq);
1900                         return -EINVAL;
1901                 }
1902         } else {
1903                 use_def_burst_func =
1904                         check_rx_burst_bulk_alloc_preconditions(rxq);
1905                 if (!use_def_burst_func) {
1906 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1907                         PMD_INIT_LOG(DEBUG,
1908                           "Rx Burst Bulk Alloc Preconditions are "
1909                           "satisfied. Rx Burst Bulk Alloc function will be "
1910                           "used on port=%d, queue=%d.",
1911                           rxq->port_id, rxq->queue_id);
1912 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1913                 } else {
1914                         PMD_INIT_LOG(DEBUG,
1915                           "Rx Burst Bulk Alloc Preconditions are "
1916                           "not satisfied, Scattered Rx is requested, "
1917                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1918                           "not enabled on port=%d, queue=%d.",
1919                           rxq->port_id, rxq->queue_id);
1920                         ad->rx_bulk_alloc_allowed = false;
1921                 }
1922         }
1923
1924         dev->data->rx_queues[queue_idx] = rxq;
1925         return 0;
1926 }
1927
1928 void
1929 i40e_dev_rx_queue_release(void *rxq)
1930 {
1931         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1932
1933         if (!q) {
1934                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1935                 return;
1936         }
1937
1938         i40e_rx_queue_release_mbufs(q);
1939         rte_free(q->sw_ring);
1940         rte_free(q);
1941 }
1942
1943 uint32_t
1944 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1945 {
1946 #define I40E_RXQ_SCAN_INTERVAL 4
1947         volatile union i40e_rx_desc *rxdp;
1948         struct i40e_rx_queue *rxq;
1949         uint16_t desc = 0;
1950
1951         rxq = dev->data->rx_queues[rx_queue_id];
1952         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1953         while ((desc < rxq->nb_rx_desc) &&
1954                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1955                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1956                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1957                 /**
1958                  * Check the DD bit of a rx descriptor of each 4 in a group,
1959                  * to avoid checking too frequently and downgrading performance
1960                  * too much.
1961                  */
1962                 desc += I40E_RXQ_SCAN_INTERVAL;
1963                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1964                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1965                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1966                                         desc - rxq->nb_rx_desc]);
1967         }
1968
1969         return desc;
1970 }
1971
1972 int
1973 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1974 {
1975         volatile union i40e_rx_desc *rxdp;
1976         struct i40e_rx_queue *rxq = rx_queue;
1977         uint16_t desc;
1978         int ret;
1979
1980         if (unlikely(offset >= rxq->nb_rx_desc)) {
1981                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1982                 return 0;
1983         }
1984
1985         desc = rxq->rx_tail + offset;
1986         if (desc >= rxq->nb_rx_desc)
1987                 desc -= rxq->nb_rx_desc;
1988
1989         rxdp = &(rxq->rx_ring[desc]);
1990
1991         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1992                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1993                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1994
1995         return ret;
1996 }
1997
1998 int
1999 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2000 {
2001         struct i40e_rx_queue *rxq = rx_queue;
2002         volatile uint64_t *status;
2003         uint64_t mask;
2004         uint32_t desc;
2005
2006         if (unlikely(offset >= rxq->nb_rx_desc))
2007                 return -EINVAL;
2008
2009         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2010                 return RTE_ETH_RX_DESC_UNAVAIL;
2011
2012         desc = rxq->rx_tail + offset;
2013         if (desc >= rxq->nb_rx_desc)
2014                 desc -= rxq->nb_rx_desc;
2015
2016         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2017         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2018                 << I40E_RXD_QW1_STATUS_SHIFT);
2019         if (*status & mask)
2020                 return RTE_ETH_RX_DESC_DONE;
2021
2022         return RTE_ETH_RX_DESC_AVAIL;
2023 }
2024
2025 int
2026 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2027 {
2028         struct i40e_tx_queue *txq = tx_queue;
2029         volatile uint64_t *status;
2030         uint64_t mask, expect;
2031         uint32_t desc;
2032
2033         if (unlikely(offset >= txq->nb_tx_desc))
2034                 return -EINVAL;
2035
2036         desc = txq->tx_tail + offset;
2037         /* go to next desc that has the RS bit */
2038         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2039                 txq->tx_rs_thresh;
2040         if (desc >= txq->nb_tx_desc) {
2041                 desc -= txq->nb_tx_desc;
2042                 if (desc >= txq->nb_tx_desc)
2043                         desc -= txq->nb_tx_desc;
2044         }
2045
2046         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2047         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2048         expect = rte_cpu_to_le_64(
2049                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2050         if ((*status & mask) == expect)
2051                 return RTE_ETH_TX_DESC_DONE;
2052
2053         return RTE_ETH_TX_DESC_FULL;
2054 }
2055
2056 static int
2057 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2058                                 struct i40e_tx_queue *txq)
2059 {
2060         struct i40e_adapter *ad =
2061                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2062
2063         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2064                 PMD_DRV_LOG(ERR,
2065                             "Failed to do TX queue initialization");
2066                 return -EINVAL;
2067         }
2068
2069         if (i40e_dev_first_queue(txq->queue_id,
2070                                  dev->data->tx_queues,
2071                                  dev->data->nb_tx_queues)) {
2072                 /**
2073                  * If it is the first queue to setup,
2074                  * set all flags and call
2075                  * i40e_set_tx_function.
2076                  */
2077                 i40e_set_tx_function_flag(dev, txq);
2078                 i40e_set_tx_function(dev);
2079                 return 0;
2080         }
2081
2082         /* check vector conflict */
2083         if (ad->tx_vec_allowed) {
2084                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2085                     i40e_txq_vec_setup(txq)) {
2086                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2087                         return -EINVAL;
2088                 }
2089         }
2090         /* check simple tx conflict */
2091         if (ad->tx_simple_allowed) {
2092                 if ((txq->offloads & ~DEV_TX_OFFLOAD_MBUF_FAST_FREE) != 0 ||
2093                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2094                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2095                         return -EINVAL;
2096                 }
2097         }
2098
2099         return 0;
2100 }
2101
2102 int
2103 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2104                         uint16_t queue_idx,
2105                         uint16_t nb_desc,
2106                         unsigned int socket_id,
2107                         const struct rte_eth_txconf *tx_conf)
2108 {
2109         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2110         struct i40e_vsi *vsi;
2111         struct i40e_pf *pf = NULL;
2112         struct i40e_vf *vf = NULL;
2113         struct i40e_tx_queue *txq;
2114         const struct rte_memzone *tz;
2115         uint32_t ring_size;
2116         uint16_t tx_rs_thresh, tx_free_thresh;
2117         uint16_t reg_idx, i, base, bsf, tc_mapping;
2118         int q_offset;
2119         uint64_t offloads;
2120
2121         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
2122
2123         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2124                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2125                 vsi = &vf->vsi;
2126                 if (!vsi)
2127                         return -EINVAL;
2128                 reg_idx = queue_idx;
2129         } else {
2130                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2131                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2132                 if (!vsi)
2133                         return -EINVAL;
2134                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2135                 if (q_offset < 0)
2136                         return -EINVAL;
2137                 reg_idx = vsi->base_queue + q_offset;
2138         }
2139
2140         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2141             (nb_desc > I40E_MAX_RING_DESC) ||
2142             (nb_desc < I40E_MIN_RING_DESC)) {
2143                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2144                             "invalid", nb_desc);
2145                 return -EINVAL;
2146         }
2147
2148         /**
2149          * The following two parameters control the setting of the RS bit on
2150          * transmit descriptors. TX descriptors will have their RS bit set
2151          * after txq->tx_rs_thresh descriptors have been used. The TX
2152          * descriptor ring will be cleaned after txq->tx_free_thresh
2153          * descriptors are used or if the number of descriptors required to
2154          * transmit a packet is greater than the number of free TX descriptors.
2155          *
2156          * The following constraints must be satisfied:
2157          *  - tx_rs_thresh must be greater than 0.
2158          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2159          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2160          *  - tx_rs_thresh must be a divisor of the ring size.
2161          *  - tx_free_thresh must be greater than 0.
2162          *  - tx_free_thresh must be less than the size of the ring minus 3.
2163          *
2164          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2165          * race condition, hence the maximum threshold constraints. When set
2166          * to zero use default values.
2167          */
2168         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2169                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2170         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2171                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2172         if (tx_rs_thresh >= (nb_desc - 2)) {
2173                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2174                              "number of TX descriptors minus 2. "
2175                              "(tx_rs_thresh=%u port=%d queue=%d)",
2176                              (unsigned int)tx_rs_thresh,
2177                              (int)dev->data->port_id,
2178                              (int)queue_idx);
2179                 return I40E_ERR_PARAM;
2180         }
2181         if (tx_free_thresh >= (nb_desc - 3)) {
2182                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2183                              "number of TX descriptors minus 3. "
2184                              "(tx_free_thresh=%u port=%d queue=%d)",
2185                              (unsigned int)tx_free_thresh,
2186                              (int)dev->data->port_id,
2187                              (int)queue_idx);
2188                 return I40E_ERR_PARAM;
2189         }
2190         if (tx_rs_thresh > tx_free_thresh) {
2191                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2192                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2193                              " tx_rs_thresh=%u port=%d queue=%d)",
2194                              (unsigned int)tx_free_thresh,
2195                              (unsigned int)tx_rs_thresh,
2196                              (int)dev->data->port_id,
2197                              (int)queue_idx);
2198                 return I40E_ERR_PARAM;
2199         }
2200         if ((nb_desc % tx_rs_thresh) != 0) {
2201                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2202                              "number of TX descriptors. (tx_rs_thresh=%u"
2203                              " port=%d queue=%d)",
2204                              (unsigned int)tx_rs_thresh,
2205                              (int)dev->data->port_id,
2206                              (int)queue_idx);
2207                 return I40E_ERR_PARAM;
2208         }
2209         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2210                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2211                              "tx_rs_thresh is greater than 1. "
2212                              "(tx_rs_thresh=%u port=%d queue=%d)",
2213                              (unsigned int)tx_rs_thresh,
2214                              (int)dev->data->port_id,
2215                              (int)queue_idx);
2216                 return I40E_ERR_PARAM;
2217         }
2218
2219         /* Free memory if needed. */
2220         if (dev->data->tx_queues[queue_idx]) {
2221                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2222                 dev->data->tx_queues[queue_idx] = NULL;
2223         }
2224
2225         /* Allocate the TX queue data structure. */
2226         txq = rte_zmalloc_socket("i40e tx queue",
2227                                   sizeof(struct i40e_tx_queue),
2228                                   RTE_CACHE_LINE_SIZE,
2229                                   socket_id);
2230         if (!txq) {
2231                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2232                             "tx queue structure");
2233                 return -ENOMEM;
2234         }
2235
2236         /* Allocate TX hardware ring descriptors. */
2237         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2238         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2239         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2240                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2241         if (!tz) {
2242                 i40e_dev_tx_queue_release(txq);
2243                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2244                 return -ENOMEM;
2245         }
2246
2247         txq->nb_tx_desc = nb_desc;
2248         txq->tx_rs_thresh = tx_rs_thresh;
2249         txq->tx_free_thresh = tx_free_thresh;
2250         txq->pthresh = tx_conf->tx_thresh.pthresh;
2251         txq->hthresh = tx_conf->tx_thresh.hthresh;
2252         txq->wthresh = tx_conf->tx_thresh.wthresh;
2253         txq->queue_id = queue_idx;
2254         txq->reg_idx = reg_idx;
2255         txq->port_id = dev->data->port_id;
2256         txq->offloads = offloads;
2257         txq->vsi = vsi;
2258         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2259
2260         txq->tx_ring_phys_addr = tz->iova;
2261         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2262
2263         /* Allocate software ring */
2264         txq->sw_ring =
2265                 rte_zmalloc_socket("i40e tx sw ring",
2266                                    sizeof(struct i40e_tx_entry) * nb_desc,
2267                                    RTE_CACHE_LINE_SIZE,
2268                                    socket_id);
2269         if (!txq->sw_ring) {
2270                 i40e_dev_tx_queue_release(txq);
2271                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2272                 return -ENOMEM;
2273         }
2274
2275         i40e_reset_tx_queue(txq);
2276         txq->q_set = TRUE;
2277
2278         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2279                 if (!(vsi->enabled_tc & (1 << i)))
2280                         continue;
2281                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2282                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2283                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2284                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2285                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2286
2287                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2288                         txq->dcb_tc = i;
2289         }
2290
2291         if (dev->data->dev_started) {
2292                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2293                         i40e_dev_tx_queue_release(txq);
2294                         return -EINVAL;
2295                 }
2296         } else {
2297                 /**
2298                  * Use a simple TX queue without offloads or
2299                  * multi segs if possible
2300                  */
2301                 i40e_set_tx_function_flag(dev, txq);
2302         }
2303         dev->data->tx_queues[queue_idx] = txq;
2304
2305         return 0;
2306 }
2307
2308 void
2309 i40e_dev_tx_queue_release(void *txq)
2310 {
2311         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2312
2313         if (!q) {
2314                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2315                 return;
2316         }
2317
2318         i40e_tx_queue_release_mbufs(q);
2319         rte_free(q->sw_ring);
2320         rte_free(q);
2321 }
2322
2323 const struct rte_memzone *
2324 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2325 {
2326         const struct rte_memzone *mz;
2327
2328         mz = rte_memzone_lookup(name);
2329         if (mz)
2330                 return mz;
2331
2332         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2333                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2334         return mz;
2335 }
2336
2337 void
2338 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2339 {
2340         uint16_t i;
2341
2342         /* SSE Vector driver has a different way of releasing mbufs. */
2343         if (rxq->rx_using_sse) {
2344                 i40e_rx_queue_release_mbufs_vec(rxq);
2345                 return;
2346         }
2347
2348         if (!rxq->sw_ring) {
2349                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2350                 return;
2351         }
2352
2353         for (i = 0; i < rxq->nb_rx_desc; i++) {
2354                 if (rxq->sw_ring[i].mbuf) {
2355                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2356                         rxq->sw_ring[i].mbuf = NULL;
2357                 }
2358         }
2359 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2360         if (rxq->rx_nb_avail == 0)
2361                 return;
2362         for (i = 0; i < rxq->rx_nb_avail; i++) {
2363                 struct rte_mbuf *mbuf;
2364
2365                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2366                 rte_pktmbuf_free_seg(mbuf);
2367         }
2368         rxq->rx_nb_avail = 0;
2369 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2370 }
2371
2372 void
2373 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2374 {
2375         unsigned i;
2376         uint16_t len;
2377
2378         if (!rxq) {
2379                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2380                 return;
2381         }
2382
2383 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2384         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2385                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2386         else
2387 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2388                 len = rxq->nb_rx_desc;
2389
2390         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2391                 ((volatile char *)rxq->rx_ring)[i] = 0;
2392
2393         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2394         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2395                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2396
2397 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2398         rxq->rx_nb_avail = 0;
2399         rxq->rx_next_avail = 0;
2400         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2401 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2402         rxq->rx_tail = 0;
2403         rxq->nb_rx_hold = 0;
2404         rxq->pkt_first_seg = NULL;
2405         rxq->pkt_last_seg = NULL;
2406
2407         rxq->rxrearm_start = 0;
2408         rxq->rxrearm_nb = 0;
2409 }
2410
2411 void
2412 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2413 {
2414         struct rte_eth_dev *dev;
2415         uint16_t i;
2416
2417         dev = &rte_eth_devices[txq->port_id];
2418
2419         if (!txq || !txq->sw_ring) {
2420                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2421                 return;
2422         }
2423
2424         /**
2425          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2426          *  so need to free remains more carefully.
2427          */
2428         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2429                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2430                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2431                 if (txq->tx_tail < i) {
2432                         for (; i < txq->nb_tx_desc; i++) {
2433                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2434                                 txq->sw_ring[i].mbuf = NULL;
2435                         }
2436                         i = 0;
2437                 }
2438                 for (; i < txq->tx_tail; i++) {
2439                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2440                         txq->sw_ring[i].mbuf = NULL;
2441                 }
2442         } else {
2443                 for (i = 0; i < txq->nb_tx_desc; i++) {
2444                         if (txq->sw_ring[i].mbuf) {
2445                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2446                                 txq->sw_ring[i].mbuf = NULL;
2447                         }
2448                 }
2449         }
2450 }
2451
2452 void
2453 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2454 {
2455         struct i40e_tx_entry *txe;
2456         uint16_t i, prev, size;
2457
2458         if (!txq) {
2459                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2460                 return;
2461         }
2462
2463         txe = txq->sw_ring;
2464         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2465         for (i = 0; i < size; i++)
2466                 ((volatile char *)txq->tx_ring)[i] = 0;
2467
2468         prev = (uint16_t)(txq->nb_tx_desc - 1);
2469         for (i = 0; i < txq->nb_tx_desc; i++) {
2470                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2471
2472                 txd->cmd_type_offset_bsz =
2473                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2474                 txe[i].mbuf =  NULL;
2475                 txe[i].last_id = i;
2476                 txe[prev].next_id = i;
2477                 prev = i;
2478         }
2479
2480         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2481         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2482
2483         txq->tx_tail = 0;
2484         txq->nb_tx_used = 0;
2485
2486         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2487         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2488 }
2489
2490 /* Init the TX queue in hardware */
2491 int
2492 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2493 {
2494         enum i40e_status_code err = I40E_SUCCESS;
2495         struct i40e_vsi *vsi = txq->vsi;
2496         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2497         uint16_t pf_q = txq->reg_idx;
2498         struct i40e_hmc_obj_txq tx_ctx;
2499         uint32_t qtx_ctl;
2500
2501         /* clear the context structure first */
2502         memset(&tx_ctx, 0, sizeof(tx_ctx));
2503         tx_ctx.new_context = 1;
2504         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2505         tx_ctx.qlen = txq->nb_tx_desc;
2506
2507 #ifdef RTE_LIBRTE_IEEE1588
2508         tx_ctx.timesync_ena = 1;
2509 #endif
2510         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2511         if (vsi->type == I40E_VSI_FDIR)
2512                 tx_ctx.fd_ena = TRUE;
2513
2514         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2515         if (err != I40E_SUCCESS) {
2516                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2517                 return err;
2518         }
2519
2520         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2521         if (err != I40E_SUCCESS) {
2522                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2523                 return err;
2524         }
2525
2526         /* Now associate this queue with this PCI function */
2527         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2528         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2529                                         I40E_QTX_CTL_PF_INDX_MASK);
2530         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2531         I40E_WRITE_FLUSH(hw);
2532
2533         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2534
2535         return err;
2536 }
2537
2538 int
2539 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2540 {
2541         struct i40e_rx_entry *rxe = rxq->sw_ring;
2542         uint64_t dma_addr;
2543         uint16_t i;
2544
2545         for (i = 0; i < rxq->nb_rx_desc; i++) {
2546                 volatile union i40e_rx_desc *rxd;
2547                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2548
2549                 if (unlikely(!mbuf)) {
2550                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2551                         return -ENOMEM;
2552                 }
2553
2554                 rte_mbuf_refcnt_set(mbuf, 1);
2555                 mbuf->next = NULL;
2556                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2557                 mbuf->nb_segs = 1;
2558                 mbuf->port = rxq->port_id;
2559
2560                 dma_addr =
2561                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2562
2563                 rxd = &rxq->rx_ring[i];
2564                 rxd->read.pkt_addr = dma_addr;
2565                 rxd->read.hdr_addr = 0;
2566 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2567                 rxd->read.rsvd1 = 0;
2568                 rxd->read.rsvd2 = 0;
2569 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2570
2571                 rxe[i].mbuf = mbuf;
2572         }
2573
2574         return 0;
2575 }
2576
2577 /*
2578  * Calculate the buffer length, and check the jumbo frame
2579  * and maximum packet length.
2580  */
2581 static int
2582 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2583 {
2584         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2585         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2586         struct rte_eth_dev_data *data = pf->dev_data;
2587         uint16_t buf_size, len;
2588
2589         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2590                 RTE_PKTMBUF_HEADROOM);
2591
2592         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2593                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2594         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2595                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2596                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2597                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2598                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2599                 rxq->hs_mode = i40e_header_split_enabled;
2600                 break;
2601         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2602         default:
2603                 rxq->rx_hdr_len = 0;
2604                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2605                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2606                 rxq->hs_mode = i40e_header_split_none;
2607                 break;
2608         }
2609
2610         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2611         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2612         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2613                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2614                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2615                         PMD_DRV_LOG(ERR, "maximum packet length must "
2616                                     "be larger than %u and smaller than %u,"
2617                                     "as jumbo frame is enabled",
2618                                     (uint32_t)ETHER_MAX_LEN,
2619                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2620                         return I40E_ERR_CONFIG;
2621                 }
2622         } else {
2623                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2624                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2625                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2626                                     "larger than %u and smaller than %u, "
2627                                     "as jumbo frame is disabled",
2628                                     (uint32_t)ETHER_MIN_LEN,
2629                                     (uint32_t)ETHER_MAX_LEN);
2630                         return I40E_ERR_CONFIG;
2631                 }
2632         }
2633
2634         return 0;
2635 }
2636
2637 /* Init the RX queue in hardware */
2638 int
2639 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2640 {
2641         int err = I40E_SUCCESS;
2642         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2643         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2644         uint16_t pf_q = rxq->reg_idx;
2645         uint16_t buf_size;
2646         struct i40e_hmc_obj_rxq rx_ctx;
2647
2648         err = i40e_rx_queue_config(rxq);
2649         if (err < 0) {
2650                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2651                 return err;
2652         }
2653
2654         /* Clear the context structure first */
2655         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2656         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2657         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2658
2659         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2660         rx_ctx.qlen = rxq->nb_rx_desc;
2661 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2662         rx_ctx.dsize = 1;
2663 #endif
2664         rx_ctx.dtype = rxq->hs_mode;
2665         if (rxq->hs_mode)
2666                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2667         else
2668                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2669         rx_ctx.rxmax = rxq->max_pkt_len;
2670         rx_ctx.tphrdesc_ena = 1;
2671         rx_ctx.tphwdesc_ena = 1;
2672         rx_ctx.tphdata_ena = 1;
2673         rx_ctx.tphhead_ena = 1;
2674         rx_ctx.lrxqthresh = 2;
2675         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2676         rx_ctx.l2tsel = 1;
2677         /* showiv indicates if inner VLAN is stripped inside of tunnel
2678          * packet. When set it to 1, vlan information is stripped from
2679          * the inner header, but the hardware does not put it in the
2680          * descriptor. So set it zero by default.
2681          */
2682         rx_ctx.showiv = 0;
2683         rx_ctx.prefena = 1;
2684
2685         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2686         if (err != I40E_SUCCESS) {
2687                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2688                 return err;
2689         }
2690         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2691         if (err != I40E_SUCCESS) {
2692                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2693                 return err;
2694         }
2695
2696         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2697
2698         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2699                 RTE_PKTMBUF_HEADROOM);
2700
2701         /* Check if scattered RX needs to be used. */
2702         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2703                 dev_data->scattered_rx = 1;
2704         }
2705
2706         /* Init the RX tail regieter. */
2707         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2708
2709         return 0;
2710 }
2711
2712 void
2713 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2714 {
2715         uint16_t i;
2716
2717         PMD_INIT_FUNC_TRACE();
2718
2719         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2720                 if (!dev->data->tx_queues[i])
2721                         continue;
2722                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2723                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2724         }
2725
2726         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2727                 if (!dev->data->rx_queues[i])
2728                         continue;
2729                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2730                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2731         }
2732 }
2733
2734 void
2735 i40e_dev_free_queues(struct rte_eth_dev *dev)
2736 {
2737         uint16_t i;
2738
2739         PMD_INIT_FUNC_TRACE();
2740
2741         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2742                 if (!dev->data->rx_queues[i])
2743                         continue;
2744                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2745                 dev->data->rx_queues[i] = NULL;
2746         }
2747         dev->data->nb_rx_queues = 0;
2748
2749         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2750                 if (!dev->data->tx_queues[i])
2751                         continue;
2752                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2753                 dev->data->tx_queues[i] = NULL;
2754         }
2755         dev->data->nb_tx_queues = 0;
2756 }
2757
2758 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2759 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2760
2761 enum i40e_status_code
2762 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2763 {
2764         struct i40e_tx_queue *txq;
2765         const struct rte_memzone *tz = NULL;
2766         uint32_t ring_size;
2767         struct rte_eth_dev *dev;
2768
2769         if (!pf) {
2770                 PMD_DRV_LOG(ERR, "PF is not available");
2771                 return I40E_ERR_BAD_PTR;
2772         }
2773
2774         dev = pf->adapter->eth_dev;
2775
2776         /* Allocate the TX queue data structure. */
2777         txq = rte_zmalloc_socket("i40e fdir tx queue",
2778                                   sizeof(struct i40e_tx_queue),
2779                                   RTE_CACHE_LINE_SIZE,
2780                                   SOCKET_ID_ANY);
2781         if (!txq) {
2782                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2783                                         "tx queue structure.");
2784                 return I40E_ERR_NO_MEMORY;
2785         }
2786
2787         /* Allocate TX hardware ring descriptors. */
2788         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2789         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2790
2791         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2792                                       I40E_FDIR_QUEUE_ID, ring_size,
2793                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2794         if (!tz) {
2795                 i40e_dev_tx_queue_release(txq);
2796                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2797                 return I40E_ERR_NO_MEMORY;
2798         }
2799
2800         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2801         txq->queue_id = I40E_FDIR_QUEUE_ID;
2802         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2803         txq->vsi = pf->fdir.fdir_vsi;
2804
2805         txq->tx_ring_phys_addr = tz->iova;
2806         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2807         /*
2808          * don't need to allocate software ring and reset for the fdir
2809          * program queue just set the queue has been configured.
2810          */
2811         txq->q_set = TRUE;
2812         pf->fdir.txq = txq;
2813
2814         return I40E_SUCCESS;
2815 }
2816
2817 enum i40e_status_code
2818 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2819 {
2820         struct i40e_rx_queue *rxq;
2821         const struct rte_memzone *rz = NULL;
2822         uint32_t ring_size;
2823         struct rte_eth_dev *dev;
2824
2825         if (!pf) {
2826                 PMD_DRV_LOG(ERR, "PF is not available");
2827                 return I40E_ERR_BAD_PTR;
2828         }
2829
2830         dev = pf->adapter->eth_dev;
2831
2832         /* Allocate the RX queue data structure. */
2833         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2834                                   sizeof(struct i40e_rx_queue),
2835                                   RTE_CACHE_LINE_SIZE,
2836                                   SOCKET_ID_ANY);
2837         if (!rxq) {
2838                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2839                                         "rx queue structure.");
2840                 return I40E_ERR_NO_MEMORY;
2841         }
2842
2843         /* Allocate RX hardware ring descriptors. */
2844         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2845         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2846
2847         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2848                                       I40E_FDIR_QUEUE_ID, ring_size,
2849                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2850         if (!rz) {
2851                 i40e_dev_rx_queue_release(rxq);
2852                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2853                 return I40E_ERR_NO_MEMORY;
2854         }
2855
2856         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2857         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2858         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2859         rxq->vsi = pf->fdir.fdir_vsi;
2860
2861         rxq->rx_ring_phys_addr = rz->iova;
2862         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2863         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2864
2865         /*
2866          * Don't need to allocate software ring and reset for the fdir
2867          * rx queue, just set the queue has been configured.
2868          */
2869         rxq->q_set = TRUE;
2870         pf->fdir.rxq = rxq;
2871
2872         return I40E_SUCCESS;
2873 }
2874
2875 void
2876 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2877         struct rte_eth_rxq_info *qinfo)
2878 {
2879         struct i40e_rx_queue *rxq;
2880
2881         rxq = dev->data->rx_queues[queue_id];
2882
2883         qinfo->mp = rxq->mp;
2884         qinfo->scattered_rx = dev->data->scattered_rx;
2885         qinfo->nb_desc = rxq->nb_rx_desc;
2886
2887         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2888         qinfo->conf.rx_drop_en = rxq->drop_en;
2889         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2890         qinfo->conf.offloads = rxq->offloads;
2891 }
2892
2893 void
2894 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2895         struct rte_eth_txq_info *qinfo)
2896 {
2897         struct i40e_tx_queue *txq;
2898
2899         txq = dev->data->tx_queues[queue_id];
2900
2901         qinfo->nb_desc = txq->nb_tx_desc;
2902
2903         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2904         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2905         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2906
2907         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2908         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2909         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2910         qinfo->conf.offloads = txq->offloads;
2911 }
2912
2913 static eth_rx_burst_t
2914 i40e_get_latest_rx_vec(bool scatter)
2915 {
2916 #ifdef RTE_ARCH_X86
2917         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
2918                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2919                                  i40e_recv_pkts_vec_avx2;
2920 #endif
2921         return scatter ? i40e_recv_scattered_pkts_vec :
2922                          i40e_recv_pkts_vec;
2923 }
2924
2925 static eth_rx_burst_t
2926 i40e_get_recommend_rx_vec(bool scatter)
2927 {
2928 #ifdef RTE_ARCH_X86
2929         /*
2930          * since AVX frequency can be different to base frequency, limit
2931          * use of AVX2 version to later plaforms, not all those that could
2932          * theoretically run it.
2933          */
2934         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
2935                 return scatter ? i40e_recv_scattered_pkts_vec_avx2 :
2936                                  i40e_recv_pkts_vec_avx2;
2937 #endif
2938         return scatter ? i40e_recv_scattered_pkts_vec :
2939                          i40e_recv_pkts_vec;
2940 }
2941
2942 void __attribute__((cold))
2943 i40e_set_rx_function(struct rte_eth_dev *dev)
2944 {
2945         struct i40e_adapter *ad =
2946                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2947         uint16_t rx_using_sse, i;
2948         /* In order to allow Vector Rx there are a few configuration
2949          * conditions to be met and Rx Bulk Allocation should be allowed.
2950          */
2951         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2952                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2953                     !ad->rx_bulk_alloc_allowed) {
2954                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2955                                      " Vector Rx preconditions",
2956                                      dev->data->port_id);
2957
2958                         ad->rx_vec_allowed = false;
2959                 }
2960                 if (ad->rx_vec_allowed) {
2961                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2962                                 struct i40e_rx_queue *rxq =
2963                                         dev->data->rx_queues[i];
2964
2965                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2966                                         ad->rx_vec_allowed = false;
2967                                         break;
2968                                 }
2969                         }
2970                 }
2971         }
2972
2973         if (ad->rx_vec_allowed) {
2974                 /* Vec Rx path */
2975                 PMD_INIT_LOG(DEBUG, "Vector Rx path will be used on port=%d.",
2976                                 dev->data->port_id);
2977                 if (ad->use_latest_vec)
2978                         dev->rx_pkt_burst =
2979                         i40e_get_latest_rx_vec(dev->data->scattered_rx);
2980                 else
2981                         dev->rx_pkt_burst =
2982                         i40e_get_recommend_rx_vec(dev->data->scattered_rx);
2983         } else if (!dev->data->scattered_rx && ad->rx_bulk_alloc_allowed) {
2984                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2985                                     "satisfied. Rx Burst Bulk Alloc function "
2986                                     "will be used on port=%d.",
2987                              dev->data->port_id);
2988
2989                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2990         } else {
2991                 /* Simple Rx Path. */
2992                 PMD_INIT_LOG(DEBUG, "Simple Rx path will be used on port=%d.",
2993                              dev->data->port_id);
2994                 dev->rx_pkt_burst = dev->data->scattered_rx ?
2995                                         i40e_recv_scattered_pkts :
2996                                         i40e_recv_pkts;
2997         }
2998
2999         /* Propagate information about RX function choice through all queues. */
3000         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3001                 rx_using_sse =
3002                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3003                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3004                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3005                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3006
3007                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3008                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3009
3010                         if (rxq)
3011                                 rxq->rx_using_sse = rx_using_sse;
3012                 }
3013         }
3014 }
3015
3016 void __attribute__((cold))
3017 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3018 {
3019         struct i40e_adapter *ad =
3020                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3021
3022         /* Use a simple Tx queue if possible (only fast free is allowed) */
3023         ad->tx_simple_allowed =
3024                 (txq->offloads ==
3025                  (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) &&
3026                  txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3027         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3028                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3029
3030         if (ad->tx_vec_allowed)
3031                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3032                                 txq->queue_id);
3033         else if (ad->tx_simple_allowed)
3034                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3035                                 txq->queue_id);
3036         else
3037                 PMD_INIT_LOG(DEBUG,
3038                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3039                                 txq->queue_id);
3040 }
3041
3042 static eth_tx_burst_t
3043 i40e_get_latest_tx_vec(void)
3044 {
3045 #ifdef RTE_ARCH_X86
3046         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2))
3047                 return i40e_xmit_pkts_vec_avx2;
3048 #endif
3049         return i40e_xmit_pkts_vec;
3050 }
3051
3052 static eth_tx_burst_t
3053 i40e_get_recommend_tx_vec(void)
3054 {
3055 #ifdef RTE_ARCH_X86
3056         /*
3057          * since AVX frequency can be different to base frequency, limit
3058          * use of AVX2 version to later plaforms, not all those that could
3059          * theoretically run it.
3060          */
3061         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3062                 return i40e_xmit_pkts_vec_avx2;
3063 #endif
3064         return i40e_xmit_pkts_vec;
3065 }
3066
3067 void __attribute__((cold))
3068 i40e_set_tx_function(struct rte_eth_dev *dev)
3069 {
3070         struct i40e_adapter *ad =
3071                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3072         int i;
3073
3074         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3075                 if (ad->tx_vec_allowed) {
3076                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3077                                 struct i40e_tx_queue *txq =
3078                                         dev->data->tx_queues[i];
3079
3080                                 if (txq && i40e_txq_vec_setup(txq)) {
3081                                         ad->tx_vec_allowed = false;
3082                                         break;
3083                                 }
3084                         }
3085                 }
3086         }
3087
3088         if (ad->tx_simple_allowed) {
3089                 if (ad->tx_vec_allowed) {
3090                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3091                         if (ad->use_latest_vec)
3092                                 dev->tx_pkt_burst =
3093                                         i40e_get_latest_tx_vec();
3094                         else
3095                                 dev->tx_pkt_burst =
3096                                         i40e_get_recommend_tx_vec();
3097                 } else {
3098                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3099                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3100                 }
3101                 dev->tx_pkt_prepare = NULL;
3102         } else {
3103                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3104                 dev->tx_pkt_burst = i40e_xmit_pkts;
3105                 dev->tx_pkt_prepare = i40e_prep_pkts;
3106         }
3107 }
3108
3109 void __attribute__((cold))
3110 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3111 {
3112         struct i40e_adapter *ad =
3113                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3114         int i;
3115
3116         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3117                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3118 }
3119
3120 void __attribute__((cold))
3121 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3122 {
3123         struct i40e_adapter *ad =
3124                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3125         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3126         int i;
3127
3128         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3129                 ad->pctypes_tbl[i] = 0ULL;
3130         ad->flow_types_mask = 0ULL;
3131         ad->pctypes_mask = 0ULL;
3132
3133         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3134                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3135         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3136                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3137         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3138                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3139         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3140                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3141         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3142                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3143         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3144                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3145         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3146                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3147         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3148                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3149         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3150                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3151         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3152                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3153         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3154                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3155
3156         if (hw->mac.type == I40E_MAC_X722) {
3157                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3158                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3159                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3160                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3161                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3162                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3163                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3164                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3165                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3166                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3167                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3168                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3169         }
3170
3171         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3172                 if (ad->pctypes_tbl[i])
3173                         ad->flow_types_mask |= (1ULL << i);
3174                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3175         }
3176 }
3177
3178 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3179 __rte_weak int
3180 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3181 {
3182         return -1;
3183 }
3184
3185 __rte_weak uint16_t
3186 i40e_recv_pkts_vec(
3187         void __rte_unused *rx_queue,
3188         struct rte_mbuf __rte_unused **rx_pkts,
3189         uint16_t __rte_unused nb_pkts)
3190 {
3191         return 0;
3192 }
3193
3194 __rte_weak uint16_t
3195 i40e_recv_scattered_pkts_vec(
3196         void __rte_unused *rx_queue,
3197         struct rte_mbuf __rte_unused **rx_pkts,
3198         uint16_t __rte_unused nb_pkts)
3199 {
3200         return 0;
3201 }
3202
3203 __rte_weak uint16_t
3204 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3205                         struct rte_mbuf __rte_unused **rx_pkts,
3206                         uint16_t __rte_unused nb_pkts)
3207 {
3208         return 0;
3209 }
3210
3211 __rte_weak uint16_t
3212 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3213                         struct rte_mbuf __rte_unused **rx_pkts,
3214                         uint16_t __rte_unused nb_pkts)
3215 {
3216         return 0;
3217 }
3218
3219 __rte_weak int
3220 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3221 {
3222         return -1;
3223 }
3224
3225 __rte_weak int
3226 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3227 {
3228         return -1;
3229 }
3230
3231 __rte_weak void
3232 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3233 {
3234         return;
3235 }
3236
3237 __rte_weak uint16_t
3238 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3239                           struct rte_mbuf __rte_unused **tx_pkts,
3240                           uint16_t __rte_unused nb_pkts)
3241 {
3242         return 0;
3243 }
3244
3245 __rte_weak uint16_t
3246 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3247                           struct rte_mbuf __rte_unused **tx_pkts,
3248                           uint16_t __rte_unused nb_pkts)
3249 {
3250         return 0;
3251 }