drivers/net/i40e/i40e_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2010-2016 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "i40e_logs.h"
  28 #include "base/i40e_prototype.h"
  29 #include "base/i40e_type.h"
  30 #include "i40e_ethdev.h"
  31 #include "i40e_rxtx.h"
  32
  33 #define DEFAULT_TX_RS_THRESH   32
  34 #define DEFAULT_TX_FREE_THRESH 32
  35
  36 #define I40E_TX_MAX_BURST  32
  37
  38 #define I40E_DMA_MEM_ALIGN 4096
  39
  40 /* Base address of the HW descriptor ring should be 128B aligned. */
  41 #define I40E_RING_BASE_ALIGN    128
  42
  43 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  44
  45 #ifdef RTE_LIBRTE_IEEE1588
  46 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  47 #else
  48 #define I40E_TX_IEEE1588_TMST 0
  49 #endif
  50
  51 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  52                 PKT_TX_IP_CKSUM |                \
  53                 PKT_TX_L4_MASK |                 \
  54                 PKT_TX_TCP_SEG |                 \
  55                 PKT_TX_OUTER_IP_CKSUM)
  56
  57 #define I40E_TX_OFFLOAD_MASK (  \
  58                 PKT_TX_IP_CKSUM |       \
  59                 PKT_TX_L4_MASK |        \
  60                 PKT_TX_OUTER_IP_CKSUM | \
  61                 PKT_TX_TCP_SEG |        \
  62                 PKT_TX_QINQ_PKT |       \
  63                 PKT_TX_VLAN_PKT |       \
  64                 PKT_TX_TUNNEL_MASK |    \
  65                 I40E_TX_IEEE1588_TMST)
  66
  67 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
  68                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
  69
  70 static inline void
  71 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  72 {
  73         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
  74                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
  75                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
  76                 mb->vlan_tci =
  77                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
  78                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
  79                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
  80         } else {
  81                 mb->vlan_tci = 0;
  82         }
  83 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
  84         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
  85                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
  86                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
  87                 mb->vlan_tci_outer = mb->vlan_tci;
  88                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
  89                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
  90                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
  91                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
  92         } else {
  93                 mb->vlan_tci_outer = 0;
  94         }
  95 #endif
  96         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
  97                    mb->vlan_tci, mb->vlan_tci_outer);
  98 }
  99
 100 /* Translate the rx descriptor status to pkt flags */
 101 static inline uint64_t
 102 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 103 {
 104         uint64_t flags;
 105
 106         /* Check if RSS_HASH */
 107         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 108                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 109                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 110
 111         /* Check if FDIR Match */
 112         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 113                                                         PKT_RX_FDIR : 0);
 114
 115         return flags;
 116 }
 117
 118 static inline uint64_t
 119 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 120 {
 121         uint64_t flags = 0;
 122         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 123
 124 #define I40E_RX_ERR_BITS 0x3f
 125         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 126                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 127                 return flags;
 128         }
 129
 130         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 131                 flags |= PKT_RX_IP_CKSUM_BAD;
 132         else
 133                 flags |= PKT_RX_IP_CKSUM_GOOD;
 134
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 136                 flags |= PKT_RX_L4_CKSUM_BAD;
 137         else
 138                 flags |= PKT_RX_L4_CKSUM_GOOD;
 139
 140         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 141                 flags |= PKT_RX_EIP_CKSUM_BAD;
 142
 143         return flags;
 144 }
 145
 146 /* Function to check and set the ieee1588 timesync index and get the
 147  * appropriate flags.
 148  */
 149 #ifdef RTE_LIBRTE_IEEE1588
 150 static inline uint64_t
 151 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 152 {
 153         uint64_t pkt_flags = 0;
 154         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 155                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 156                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 157
 158         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 159                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 160                 pkt_flags = PKT_RX_IEEE1588_PTP;
 161         if (tsyn & 0x04) {
 162                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 163                 mb->timesync = tsyn & 0x03;
 164         }
 165
 166         return pkt_flags;
 167 }
 168 #endif
 169
 170 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 171 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 172 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 173 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 174 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 175
 176 static inline uint64_t
 177 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 178 {
 179         uint64_t flags = 0;
 180 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 181         uint16_t flexbh, flexbl;
 182
 183         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 184                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 185                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 186         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 187                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 188                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 189
 190
 191         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 192                 mb->hash.fdir.hi =
 193                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 194                 flags |= PKT_RX_FDIR_ID;
 195         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 196                 mb->hash.fdir.hi =
 197                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 198                 flags |= PKT_RX_FDIR_FLX;
 199         }
 200         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 201                 mb->hash.fdir.lo =
 202                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 203                 flags |= PKT_RX_FDIR_FLX;
 204         }
 205 #else
 206         mb->hash.fdir.hi =
 207                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 208         flags |= PKT_RX_FDIR_ID;
 209 #endif
 210         return flags;
 211 }
 212
 213 static inline void
 214 i40e_parse_tunneling_params(uint64_t ol_flags,
 215                             union i40e_tx_offload tx_offload,
 216                             uint32_t *cd_tunneling)
 217 {
 218         /* EIPT: External (outer) IP header type */
 219         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 220                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 221         else if (ol_flags & PKT_TX_OUTER_IPV4)
 222                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 223         else if (ol_flags & PKT_TX_OUTER_IPV6)
 224                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 225
 226         /* EIPLEN: External (outer) IP header length, in DWords */
 227         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 228                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 229
 230         /* L4TUNT: L4 Tunneling Type */
 231         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 232         case PKT_TX_TUNNEL_IPIP:
 233                 /* for non UDP / GRE tunneling, set to 00b */
 234                 break;
 235         case PKT_TX_TUNNEL_VXLAN:
 236         case PKT_TX_TUNNEL_GENEVE:
 237                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 238                 break;
 239         case PKT_TX_TUNNEL_GRE:
 240                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 241                 break;
 242         default:
 243                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 244                 return;
 245         }
 246
 247         /* L4TUNLEN: L4 Tunneling Length, in Words
 248          *
 249          * We depend on app to set rte_mbuf.l2_len correctly.
 250          * For IP in GRE it should be set to the length of the GRE
 251          * header;
 252          * for MAC in GRE or MAC in UDP it should be set to the length
 253          * of the GRE or UDP headers plus the inner MAC up to including
 254          * its last Ethertype.
 255          */
 256         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 257                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 258 }
 259
 260 static inline void
 261 i40e_txd_enable_checksum(uint64_t ol_flags,
 262                         uint32_t *td_cmd,
 263                         uint32_t *td_offset,
 264                         union i40e_tx_offload tx_offload)
 265 {
 266         /* Set MACLEN */
 267         if (ol_flags & PKT_TX_TUNNEL_MASK)
 268                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 269                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 270         else
 271                 *td_offset |= (tx_offload.l2_len >> 1)
 272                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 273
 274         /* Enable L3 checksum offloads */
 275         if (ol_flags & PKT_TX_IP_CKSUM) {
 276                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 277                 *td_offset |= (tx_offload.l3_len >> 2)
 278                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 279         } else if (ol_flags & PKT_TX_IPV4) {
 280                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 281                 *td_offset |= (tx_offload.l3_len >> 2)
 282                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 283         } else if (ol_flags & PKT_TX_IPV6) {
 284                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 285                 *td_offset |= (tx_offload.l3_len >> 2)
 286                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 287         }
 288
 289         if (ol_flags & PKT_TX_TCP_SEG) {
 290                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 291                 *td_offset |= (tx_offload.l4_len >> 2)
 292                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 293                 return;
 294         }
 295
 296         /* Enable L4 checksum offloads */
 297         switch (ol_flags & PKT_TX_L4_MASK) {
 298         case PKT_TX_TCP_CKSUM:
 299                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 300                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 301                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 302                 break;
 303         case PKT_TX_SCTP_CKSUM:
 304                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 305                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 306                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 307                 break;
 308         case PKT_TX_UDP_CKSUM:
 309                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 310                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 311                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 312                 break;
 313         default:
 314                 break;
 315         }
 316 }
 317
 318 /* Construct the tx flags */
 319 static inline uint64_t
 320 i40e_build_ctob(uint32_t td_cmd,
 321                 uint32_t td_offset,
 322                 unsigned int size,
 323                 uint32_t td_tag)
 324 {
 325         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 326                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 327                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 328                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 329                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 330 }
 331
 332 static inline int
 333 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 334 {
 335         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 336         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 337         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 338         uint16_t nb_tx_desc = txq->nb_tx_desc;
 339         uint16_t desc_to_clean_to;
 340         uint16_t nb_tx_to_clean;
 341
 342         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 343         if (desc_to_clean_to >= nb_tx_desc)
 344                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 345
 346         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 347         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 348                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 349                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 350                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 351                         "(port=%d queue=%d)", desc_to_clean_to,
 352                                 txq->port_id, txq->queue_id);
 353                 return -1;
 354         }
 355
 356         if (last_desc_cleaned > desc_to_clean_to)
 357                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 358                                                         desc_to_clean_to);
 359         else
 360                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 361                                         last_desc_cleaned);
 362
 363         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 364
 365         txq->last_desc_cleaned = desc_to_clean_to;
 366         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 367
 368         return 0;
 369 }
 370
 371 static inline int
 372 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 373 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 374 #else
 375 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 376 #endif
 377 {
 378         int ret = 0;
 379
 380 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 381         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 382                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 383                              "rxq->rx_free_thresh=%d, "
 384                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 385                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 386                 ret = -EINVAL;
 387         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 388                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 389                              "rxq->rx_free_thresh=%d, "
 390                              "rxq->nb_rx_desc=%d",
 391                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 392                 ret = -EINVAL;
 393         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 394                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 395                              "rxq->nb_rx_desc=%d, "
 396                              "rxq->rx_free_thresh=%d",
 397                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 398                 ret = -EINVAL;
 399         }
 400 #else
 401         ret = -EINVAL;
 402 #endif
 403
 404         return ret;
 405 }
 406
 407 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 408 #define I40E_LOOK_AHEAD 8
 409 #if (I40E_LOOK_AHEAD != 8)
 410 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 411 #endif
 412 static inline int
 413 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 414 {
 415         volatile union i40e_rx_desc *rxdp;
 416         struct i40e_rx_entry *rxep;
 417         struct rte_mbuf *mb;
 418         uint16_t pkt_len;
 419         uint64_t qword1;
 420         uint32_t rx_status;
 421         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 422         int32_t i, j, nb_rx = 0;
 423         uint64_t pkt_flags;
 424         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 425
 426         rxdp = &rxq->rx_ring[rxq->rx_tail];
 427         rxep = &rxq->sw_ring[rxq->rx_tail];
 428
 429         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 430         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 431                                 I40E_RXD_QW1_STATUS_SHIFT;
 432
 433         /* Make sure there is at least 1 packet to receive */
 434         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 435                 return 0;
 436
 437         /**
 438          * Scan LOOK_AHEAD descriptors at a time to determine which
 439          * descriptors reference packets that are ready to be received.
 440          */
 441         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 442                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 443                 /* Read desc statuses backwards to avoid race condition */
 444                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 445                         qword1 = rte_le_to_cpu_64(\
 446                                 rxdp[j].wb.qword1.status_error_len);
 447                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 448                                         I40E_RXD_QW1_STATUS_SHIFT;
 449                 }
 450
 451                 rte_smp_rmb();
 452
 453                 /* Compute how many status bits were set */
 454                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 455                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 456
 457                 nb_rx += nb_dd;
 458
 459                 /* Translate descriptor info to mbuf parameters */
 460                 for (j = 0; j < nb_dd; j++) {
 461                         mb = rxep[j].mbuf;
 462                         qword1 = rte_le_to_cpu_64(\
 463                                 rxdp[j].wb.qword1.status_error_len);
 464                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 465                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 466                         mb->data_len = pkt_len;
 467                         mb->pkt_len = pkt_len;
 468                         mb->ol_flags = 0;
 469                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 470                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 471                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 472                         mb->packet_type =
 473                                 ptype_tbl[(uint8_t)((qword1 &
 474                                 I40E_RXD_QW1_PTYPE_MASK) >>
 475                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 476                         if (pkt_flags & PKT_RX_RSS_HASH)
 477                                 mb->hash.rss = rte_le_to_cpu_32(\
 478                                         rxdp[j].wb.qword0.hi_dword.rss);
 479                         if (pkt_flags & PKT_RX_FDIR)
 480                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 481
 482 #ifdef RTE_LIBRTE_IEEE1588
 483                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 484 #endif
 485                         mb->ol_flags |= pkt_flags;
 486
 487                 }
 488
 489                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 490                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 491
 492                 if (nb_dd != I40E_LOOK_AHEAD)
 493                         break;
 494         }
 495
 496         /* Clear software ring entries */
 497         for (i = 0; i < nb_rx; i++)
 498                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 499
 500         return nb_rx;
 501 }
 502
 503 static inline uint16_t
 504 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 505                         struct rte_mbuf **rx_pkts,
 506                         uint16_t nb_pkts)
 507 {
 508         uint16_t i;
 509         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 510
 511         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 512
 513         for (i = 0; i < nb_pkts; i++)
 514                 rx_pkts[i] = stage[i];
 515
 516         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 517         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 518
 519         return nb_pkts;
 520 }
 521
 522 static inline int
 523 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 524 {
 525         volatile union i40e_rx_desc *rxdp;
 526         struct i40e_rx_entry *rxep;
 527         struct rte_mbuf *mb;
 528         uint16_t alloc_idx, i;
 529         uint64_t dma_addr;
 530         int diag;
 531
 532         /* Allocate buffers in bulk */
 533         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 534                                 (rxq->rx_free_thresh - 1));
 535         rxep = &(rxq->sw_ring[alloc_idx]);
 536         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 537                                         rxq->rx_free_thresh);
 538         if (unlikely(diag != 0)) {
 539                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 540                 return -ENOMEM;
 541         }
 542
 543         rxdp = &rxq->rx_ring[alloc_idx];
 544         for (i = 0; i < rxq->rx_free_thresh; i++) {
 545                 if (likely(i < (rxq->rx_free_thresh - 1)))
 546                         /* Prefetch next mbuf */
 547                         rte_prefetch0(rxep[i + 1].mbuf);
 548
 549                 mb = rxep[i].mbuf;
 550                 rte_mbuf_refcnt_set(mb, 1);
 551                 mb->next = NULL;
 552                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 553                 mb->nb_segs = 1;
 554                 mb->port = rxq->port_id;
 555                 dma_addr = rte_cpu_to_le_64(\
 556                         rte_mbuf_data_iova_default(mb));
 557                 rxdp[i].read.hdr_addr = 0;
 558                 rxdp[i].read.pkt_addr = dma_addr;
 559         }
 560
 561         /* Update rx tail regsiter */
 562         rte_wmb();
 563         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 564
 565         rxq->rx_free_trigger =
 566                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 567         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 568                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 569
 570         return 0;
 571 }
 572
 573 static inline uint16_t
 574 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 575 {
 576         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 577         struct rte_eth_dev *dev;
 578         uint16_t nb_rx = 0;
 579
 580         if (!nb_pkts)
 581                 return 0;
 582
 583         if (rxq->rx_nb_avail)
 584                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 585
 586         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 587         rxq->rx_next_avail = 0;
 588         rxq->rx_nb_avail = nb_rx;
 589         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 590
 591         if (rxq->rx_tail > rxq->rx_free_trigger) {
 592                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 593                         uint16_t i, j;
 594
 595                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 596                         dev->data->rx_mbuf_alloc_failed +=
 597                                 rxq->rx_free_thresh;
 598
 599                         rxq->rx_nb_avail = 0;
 600                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 601                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 602                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 603
 604                         return 0;
 605                 }
 606         }
 607
 608         if (rxq->rx_tail >= rxq->nb_rx_desc)
 609                 rxq->rx_tail = 0;
 610
 611         if (rxq->rx_nb_avail)
 612                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 613
 614         return 0;
 615 }
 616
 617 static uint16_t
 618 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 619                           struct rte_mbuf **rx_pkts,
 620                           uint16_t nb_pkts)
 621 {
 622         uint16_t nb_rx = 0, n, count;
 623
 624         if (unlikely(nb_pkts == 0))
 625                 return 0;
 626
 627         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 628                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 629
 630         while (nb_pkts) {
 631                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 632                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 633                 nb_rx = (uint16_t)(nb_rx + count);
 634                 nb_pkts = (uint16_t)(nb_pkts - count);
 635                 if (count < n)
 636                         break;
 637         }
 638
 639         return nb_rx;
 640 }
 641 #else
 642 static uint16_t
 643 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 644                           struct rte_mbuf __rte_unused **rx_pkts,
 645                           uint16_t __rte_unused nb_pkts)
 646 {
 647         return 0;
 648 }
 649 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 650
 651 uint16_t
 652 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 653 {
 654         struct i40e_rx_queue *rxq;
 655         volatile union i40e_rx_desc *rx_ring;
 656         volatile union i40e_rx_desc *rxdp;
 657         union i40e_rx_desc rxd;
 658         struct i40e_rx_entry *sw_ring;
 659         struct i40e_rx_entry *rxe;
 660         struct rte_eth_dev *dev;
 661         struct rte_mbuf *rxm;
 662         struct rte_mbuf *nmb;
 663         uint16_t nb_rx;
 664         uint32_t rx_status;
 665         uint64_t qword1;
 666         uint16_t rx_packet_len;
 667         uint16_t rx_id, nb_hold;
 668         uint64_t dma_addr;
 669         uint64_t pkt_flags;
 670         uint32_t *ptype_tbl;
 671
 672         nb_rx = 0;
 673         nb_hold = 0;
 674         rxq = rx_queue;
 675         rx_id = rxq->rx_tail;
 676         rx_ring = rxq->rx_ring;
 677         sw_ring = rxq->sw_ring;
 678         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 679
 680         while (nb_rx < nb_pkts) {
 681                 rxdp = &rx_ring[rx_id];
 682                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 683                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 684                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 685
 686                 /* Check the DD bit first */
 687                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 688                         break;
 689
 690                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 691                 if (unlikely(!nmb)) {
 692                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 693                         dev->data->rx_mbuf_alloc_failed++;
 694                         break;
 695                 }
 696
 697                 rxd = *rxdp;
 698                 nb_hold++;
 699                 rxe = &sw_ring[rx_id];
 700                 rx_id++;
 701                 if (unlikely(rx_id == rxq->nb_rx_desc))
 702                         rx_id = 0;
 703
 704                 /* Prefetch next mbuf */
 705                 rte_prefetch0(sw_ring[rx_id].mbuf);
 706
 707                 /**
 708                  * When next RX descriptor is on a cache line boundary,
 709                  * prefetch the next 4 RX descriptors and next 8 pointers
 710                  * to mbufs.
 711                  */
 712                 if ((rx_id & 0x3) == 0) {
 713                         rte_prefetch0(&rx_ring[rx_id]);
 714                         rte_prefetch0(&sw_ring[rx_id]);
 715                 }
 716                 rxm = rxe->mbuf;
 717                 rxe->mbuf = nmb;
 718                 dma_addr =
 719                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 720                 rxdp->read.hdr_addr = 0;
 721                 rxdp->read.pkt_addr = dma_addr;
 722
 723                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 724                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 725
 726                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 727                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 728                 rxm->nb_segs = 1;
 729                 rxm->next = NULL;
 730                 rxm->pkt_len = rx_packet_len;
 731                 rxm->data_len = rx_packet_len;
 732                 rxm->port = rxq->port_id;
 733                 rxm->ol_flags = 0;
 734                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 735                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 736                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 737                 rxm->packet_type =
 738                         ptype_tbl[(uint8_t)((qword1 &
 739                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 740                 if (pkt_flags & PKT_RX_RSS_HASH)
 741                         rxm->hash.rss =
 742                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 743                 if (pkt_flags & PKT_RX_FDIR)
 744                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 745
 746 #ifdef RTE_LIBRTE_IEEE1588
 747                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 748 #endif
 749                 rxm->ol_flags |= pkt_flags;
 750
 751                 rx_pkts[nb_rx++] = rxm;
 752         }
 753         rxq->rx_tail = rx_id;
 754
 755         /**
 756          * If the number of free RX descriptors is greater than the RX free
 757          * threshold of the queue, advance the receive tail register of queue.
 758          * Update that register with the value of the last processed RX
 759          * descriptor minus 1.
 760          */
 761         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 762         if (nb_hold > rxq->rx_free_thresh) {
 763                 rx_id = (uint16_t) ((rx_id == 0) ?
 764                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 765                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 766                 nb_hold = 0;
 767         }
 768         rxq->nb_rx_hold = nb_hold;
 769
 770         return nb_rx;
 771 }
 772
 773 uint16_t
 774 i40e_recv_scattered_pkts(void *rx_queue,
 775                          struct rte_mbuf **rx_pkts,
 776                          uint16_t nb_pkts)
 777 {
 778         struct i40e_rx_queue *rxq = rx_queue;
 779         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 780         volatile union i40e_rx_desc *rxdp;
 781         union i40e_rx_desc rxd;
 782         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 783         struct i40e_rx_entry *rxe;
 784         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 785         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 786         struct rte_mbuf *nmb, *rxm;
 787         uint16_t rx_id = rxq->rx_tail;
 788         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 789         struct rte_eth_dev *dev;
 790         uint32_t rx_status;
 791         uint64_t qword1;
 792         uint64_t dma_addr;
 793         uint64_t pkt_flags;
 794         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 795
 796         while (nb_rx < nb_pkts) {
 797                 rxdp = &rx_ring[rx_id];
 798                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 799                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 800                                         I40E_RXD_QW1_STATUS_SHIFT;
 801
 802                 /* Check the DD bit */
 803                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 804                         break;
 805
 806                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 807                 if (unlikely(!nmb)) {
 808                         dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
 809                         dev->data->rx_mbuf_alloc_failed++;
 810                         break;
 811                 }
 812
 813                 rxd = *rxdp;
 814                 nb_hold++;
 815                 rxe = &sw_ring[rx_id];
 816                 rx_id++;
 817                 if (rx_id == rxq->nb_rx_desc)
 818                         rx_id = 0;
 819
 820                 /* Prefetch next mbuf */
 821                 rte_prefetch0(sw_ring[rx_id].mbuf);
 822
 823                 /**
 824                  * When next RX descriptor is on a cache line boundary,
 825                  * prefetch the next 4 RX descriptors and next 8 pointers
 826                  * to mbufs.
 827                  */
 828                 if ((rx_id & 0x3) == 0) {
 829                         rte_prefetch0(&rx_ring[rx_id]);
 830                         rte_prefetch0(&sw_ring[rx_id]);
 831                 }
 832
 833                 rxm = rxe->mbuf;
 834                 rxe->mbuf = nmb;
 835                 dma_addr =
 836                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 837
 838                 /* Set data buffer address and data length of the mbuf */
 839                 rxdp->read.hdr_addr = 0;
 840                 rxdp->read.pkt_addr = dma_addr;
 841                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 842                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 843                 rxm->data_len = rx_packet_len;
 844                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 845
 846                 /**
 847                  * If this is the first buffer of the received packet, set the
 848                  * pointer to the first mbuf of the packet and initialize its
 849                  * context. Otherwise, update the total length and the number
 850                  * of segments of the current scattered packet, and update the
 851                  * pointer to the last mbuf of the current packet.
 852                  */
 853                 if (!first_seg) {
 854                         first_seg = rxm;
 855                         first_seg->nb_segs = 1;
 856                         first_seg->pkt_len = rx_packet_len;
 857                 } else {
 858                         first_seg->pkt_len =
 859                                 (uint16_t)(first_seg->pkt_len +
 860                                                 rx_packet_len);
 861                         first_seg->nb_segs++;
 862                         last_seg->next = rxm;
 863                 }
 864
 865                 /**
 866                  * If this is not the last buffer of the received packet,
 867                  * update the pointer to the last mbuf of the current scattered
 868                  * packet and continue to parse the RX ring.
 869                  */
 870                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 871                         last_seg = rxm;
 872                         continue;
 873                 }
 874
 875                 /**
 876                  * This is the last buffer of the received packet. If the CRC
 877                  * is not stripped by the hardware:
 878                  *  - Subtract the CRC length from the total packet length.
 879                  *  - If the last buffer only contains the whole CRC or a part
 880                  *  of it, free the mbuf associated to the last buffer. If part
 881                  *  of the CRC is also contained in the previous mbuf, subtract
 882                  *  the length of that CRC part from the data length of the
 883                  *  previous mbuf.
 884                  */
 885                 rxm->next = NULL;
 886                 if (unlikely(rxq->crc_len > 0)) {
 887                         first_seg->pkt_len -= ETHER_CRC_LEN;
 888                         if (rx_packet_len <= ETHER_CRC_LEN) {
 889                                 rte_pktmbuf_free_seg(rxm);
 890                                 first_seg->nb_segs--;
 891                                 last_seg->data_len =
 892                                         (uint16_t)(last_seg->data_len -
 893                                         (ETHER_CRC_LEN - rx_packet_len));
 894                                 last_seg->next = NULL;
 895                         } else
 896                                 rxm->data_len = (uint16_t)(rx_packet_len -
 897                                                                 ETHER_CRC_LEN);
 898                 }
 899
 900                 first_seg->port = rxq->port_id;
 901                 first_seg->ol_flags = 0;
 902                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 903                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 904                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 905                 first_seg->packet_type =
 906                         ptype_tbl[(uint8_t)((qword1 &
 907                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 908                 if (pkt_flags & PKT_RX_RSS_HASH)
 909                         first_seg->hash.rss =
 910                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 911                 if (pkt_flags & PKT_RX_FDIR)
 912                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 913
 914 #ifdef RTE_LIBRTE_IEEE1588
 915                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 916 #endif
 917                 first_seg->ol_flags |= pkt_flags;
 918
 919                 /* Prefetch data of first segment, if configured to do so. */
 920                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 921                         first_seg->data_off));
 922                 rx_pkts[nb_rx++] = first_seg;
 923                 first_seg = NULL;
 924         }
 925
 926         /* Record index of the next RX descriptor to probe. */
 927         rxq->rx_tail = rx_id;
 928         rxq->pkt_first_seg = first_seg;
 929         rxq->pkt_last_seg = last_seg;
 930
 931         /**
 932          * If the number of free RX descriptors is greater than the RX free
 933          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 934          * register. Update the RDT with the value of the last processed RX
 935          * descriptor minus 1, to guarantee that the RDT register is never
 936          * equal to the RDH register, which creates a "full" ring situtation
 937          * from the hardware point of view.
 938          */
 939         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 940         if (nb_hold > rxq->rx_free_thresh) {
 941                 rx_id = (uint16_t)(rx_id == 0 ?
 942                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 943                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 944                 nb_hold = 0;
 945         }
 946         rxq->nb_rx_hold = nb_hold;
 947
 948         return nb_rx;
 949 }
 950
 951 /* Check if the context descriptor is needed for TX offloading */
 952 static inline uint16_t
 953 i40e_calc_context_desc(uint64_t flags)
 954 {
 955         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 956                 PKT_TX_TCP_SEG |
 957                 PKT_TX_QINQ_PKT |
 958                 PKT_TX_TUNNEL_MASK;
 959
 960 #ifdef RTE_LIBRTE_IEEE1588
 961         mask |= PKT_TX_IEEE1588_TMST;
 962 #endif
 963
 964         return (flags & mask) ? 1 : 0;
 965 }
 966
 967 /* set i40e TSO context descriptor */
 968 static inline uint64_t
 969 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 970 {
 971         uint64_t ctx_desc = 0;
 972         uint32_t cd_cmd, hdr_len, cd_tso_len;
 973
 974         if (!tx_offload.l4_len) {
 975                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
 976                 return ctx_desc;
 977         }
 978
 979         /**
 980          * in case of non tunneling packet, the outer_l2_len and
 981          * outer_l3_len must be 0.
 982          */
 983         hdr_len = tx_offload.outer_l2_len +
 984                 tx_offload.outer_l3_len +
 985                 tx_offload.l2_len +
 986                 tx_offload.l3_len +
 987                 tx_offload.l4_len;
 988
 989         cd_cmd = I40E_TX_CTX_DESC_TSO;
 990         cd_tso_len = mbuf->pkt_len - hdr_len;
 991         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
 992                 ((uint64_t)cd_tso_len <<
 993                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
 994                 ((uint64_t)mbuf->tso_segsz <<
 995                  I40E_TXD_CTX_QW1_MSS_SHIFT);
 996
 997         return ctx_desc;
 998 }
 999
1000 uint16_t
1001 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1002 {
1003         struct i40e_tx_queue *txq;
1004         struct i40e_tx_entry *sw_ring;
1005         struct i40e_tx_entry *txe, *txn;
1006         volatile struct i40e_tx_desc *txd;
1007         volatile struct i40e_tx_desc *txr;
1008         struct rte_mbuf *tx_pkt;
1009         struct rte_mbuf *m_seg;
1010         uint32_t cd_tunneling_params;
1011         uint16_t tx_id;
1012         uint16_t nb_tx;
1013         uint32_t td_cmd;
1014         uint32_t td_offset;
1015         uint32_t td_tag;
1016         uint64_t ol_flags;
1017         uint16_t nb_used;
1018         uint16_t nb_ctx;
1019         uint16_t tx_last;
1020         uint16_t slen;
1021         uint64_t buf_dma_addr;
1022         union i40e_tx_offload tx_offload = {0};
1023
1024         txq = tx_queue;
1025         sw_ring = txq->sw_ring;
1026         txr = txq->tx_ring;
1027         tx_id = txq->tx_tail;
1028         txe = &sw_ring[tx_id];
1029
1030         /* Check if the descriptor ring needs to be cleaned. */
1031         if (txq->nb_tx_free < txq->tx_free_thresh)
1032                 i40e_xmit_cleanup(txq);
1033
1034         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1035                 td_cmd = 0;
1036                 td_tag = 0;
1037                 td_offset = 0;
1038
1039                 tx_pkt = *tx_pkts++;
1040                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1041
1042                 ol_flags = tx_pkt->ol_flags;
1043                 tx_offload.l2_len = tx_pkt->l2_len;
1044                 tx_offload.l3_len = tx_pkt->l3_len;
1045                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1046                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1047                 tx_offload.l4_len = tx_pkt->l4_len;
1048                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1049
1050                 /* Calculate the number of context descriptors needed. */
1051                 nb_ctx = i40e_calc_context_desc(ol_flags);
1052
1053                 /**
1054                  * The number of descriptors that must be allocated for
1055                  * a packet equals to the number of the segments of that
1056                  * packet plus 1 context descriptor if needed.
1057                  */
1058                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1059                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1060
1061                 /* Circular ring */
1062                 if (tx_last >= txq->nb_tx_desc)
1063                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1064
1065                 if (nb_used > txq->nb_tx_free) {
1066                         if (i40e_xmit_cleanup(txq) != 0) {
1067                                 if (nb_tx == 0)
1068                                         return 0;
1069                                 goto end_of_tx;
1070                         }
1071                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1072                                 while (nb_used > txq->nb_tx_free) {
1073                                         if (i40e_xmit_cleanup(txq) != 0) {
1074                                                 if (nb_tx == 0)
1075                                                         return 0;
1076                                                 goto end_of_tx;
1077                                         }
1078                                 }
1079                         }
1080                 }
1081
1082                 /* Descriptor based VLAN insertion */
1083                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1084                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1085                         td_tag = tx_pkt->vlan_tci;
1086                 }
1087
1088                 /* Always enable CRC offload insertion */
1089                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1090
1091                 /* Fill in tunneling parameters if necessary */
1092                 cd_tunneling_params = 0;
1093                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1094                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1095                                                     &cd_tunneling_params);
1096                 /* Enable checksum offloading */
1097                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1098                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1099                                                  &td_offset, tx_offload);
1100
1101                 if (nb_ctx) {
1102                         /* Setup TX context descriptor if required */
1103                         volatile struct i40e_tx_context_desc *ctx_txd =
1104                                 (volatile struct i40e_tx_context_desc *)\
1105                                                         &txr[tx_id];
1106                         uint16_t cd_l2tag2 = 0;
1107                         uint64_t cd_type_cmd_tso_mss =
1108                                 I40E_TX_DESC_DTYPE_CONTEXT;
1109
1110                         txn = &sw_ring[txe->next_id];
1111                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1112                         if (txe->mbuf != NULL) {
1113                                 rte_pktmbuf_free_seg(txe->mbuf);
1114                                 txe->mbuf = NULL;
1115                         }
1116
1117                         /* TSO enabled means no timestamp */
1118                         if (ol_flags & PKT_TX_TCP_SEG)
1119                                 cd_type_cmd_tso_mss |=
1120                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1121                         else {
1122 #ifdef RTE_LIBRTE_IEEE1588
1123                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1124                                         cd_type_cmd_tso_mss |=
1125                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1126                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1127 #endif
1128                         }
1129
1130                         ctx_txd->tunneling_params =
1131                                 rte_cpu_to_le_32(cd_tunneling_params);
1132                         if (ol_flags & PKT_TX_QINQ_PKT) {
1133                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1134                                 cd_type_cmd_tso_mss |=
1135                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1136                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1137                         }
1138                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1139                         ctx_txd->type_cmd_tso_mss =
1140                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1141
1142                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1143                                 "tunneling_params: %#x;\n"
1144                                 "l2tag2: %#hx;\n"
1145                                 "rsvd: %#hx;\n"
1146                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1147                                 tx_pkt, tx_id,
1148                                 ctx_txd->tunneling_params,
1149                                 ctx_txd->l2tag2,
1150                                 ctx_txd->rsvd,
1151                                 ctx_txd->type_cmd_tso_mss);
1152
1153                         txe->last_id = tx_last;
1154                         tx_id = txe->next_id;
1155                         txe = txn;
1156                 }
1157
1158                 m_seg = tx_pkt;
1159                 do {
1160                         txd = &txr[tx_id];
1161                         txn = &sw_ring[txe->next_id];
1162
1163                         if (txe->mbuf)
1164                                 rte_pktmbuf_free_seg(txe->mbuf);
1165                         txe->mbuf = m_seg;
1166
1167                         /* Setup TX Descriptor */
1168                         slen = m_seg->data_len;
1169                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1170
1171                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1172                                 "buf_dma_addr: %#"PRIx64";\n"
1173                                 "td_cmd: %#x;\n"
1174                                 "td_offset: %#x;\n"
1175                                 "td_len: %u;\n"
1176                                 "td_tag: %#x;\n",
1177                                 tx_pkt, tx_id, buf_dma_addr,
1178                                 td_cmd, td_offset, slen, td_tag);
1179
1180                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1181                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1182                                                 td_offset, slen, td_tag);
1183                         txe->last_id = tx_last;
1184                         tx_id = txe->next_id;
1185                         txe = txn;
1186                         m_seg = m_seg->next;
1187                 } while (m_seg != NULL);
1188
1189                 /* The last packet data descriptor needs End Of Packet (EOP) */
1190                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1191                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1192                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1193
1194                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1195                         PMD_TX_FREE_LOG(DEBUG,
1196                                         "Setting RS bit on TXD id="
1197                                         "%4u (port=%d queue=%d)",
1198                                         tx_last, txq->port_id, txq->queue_id);
1199
1200                         td_cmd |= I40E_TX_DESC_CMD_RS;
1201
1202                         /* Update txq RS bit counters */
1203                         txq->nb_tx_used = 0;
1204                 }
1205
1206                 txd->cmd_type_offset_bsz |=
1207                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1208                                         I40E_TXD_QW1_CMD_SHIFT);
1209         }
1210
1211 end_of_tx:
1212         rte_wmb();
1213
1214         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1215                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1216                    (unsigned) tx_id, (unsigned) nb_tx);
1217
1218         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1219         txq->tx_tail = tx_id;
1220
1221         return nb_tx;
1222 }
1223
1224 static __rte_always_inline int
1225 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1226 {
1227         struct i40e_tx_entry *txep;
1228         uint16_t i;
1229
1230         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1231                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1232                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1233                 return 0;
1234
1235         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1236
1237         for (i = 0; i < txq->tx_rs_thresh; i++)
1238                 rte_prefetch0((txep + i)->mbuf);
1239
1240         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE) {
1241                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1242                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1243                         txep->mbuf = NULL;
1244                 }
1245         } else {
1246                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1247                         rte_pktmbuf_free_seg(txep->mbuf);
1248                         txep->mbuf = NULL;
1249                 }
1250         }
1251
1252         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1253         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1254         if (txq->tx_next_dd >= txq->nb_tx_desc)
1255                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1256
1257         return txq->tx_rs_thresh;
1258 }
1259
1260 /* Populate 4 descriptors with data from 4 mbufs */
1261 static inline void
1262 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1263 {
1264         uint64_t dma_addr;
1265         uint32_t i;
1266
1267         for (i = 0; i < 4; i++, txdp++, pkts++) {
1268                 dma_addr = rte_mbuf_data_iova(*pkts);
1269                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1270                 txdp->cmd_type_offset_bsz =
1271                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1272                                         (*pkts)->data_len, 0);
1273         }
1274 }
1275
1276 /* Populate 1 descriptor with data from 1 mbuf */
1277 static inline void
1278 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1279 {
1280         uint64_t dma_addr;
1281
1282         dma_addr = rte_mbuf_data_iova(*pkts);
1283         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1284         txdp->cmd_type_offset_bsz =
1285                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1286                                 (*pkts)->data_len, 0);
1287 }
1288
1289 /* Fill hardware descriptor ring with mbuf data */
1290 static inline void
1291 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1292                      struct rte_mbuf **pkts,
1293                      uint16_t nb_pkts)
1294 {
1295         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1296         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1297         const int N_PER_LOOP = 4;
1298         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1299         int mainpart, leftover;
1300         int i, j;
1301
1302         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1303         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1304         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1305                 for (j = 0; j < N_PER_LOOP; ++j) {
1306                         (txep + i + j)->mbuf = *(pkts + i + j);
1307                 }
1308                 tx4(txdp + i, pkts + i);
1309         }
1310         if (unlikely(leftover > 0)) {
1311                 for (i = 0; i < leftover; ++i) {
1312                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1313                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1314                 }
1315         }
1316 }
1317
1318 static inline uint16_t
1319 tx_xmit_pkts(struct i40e_tx_queue *txq,
1320              struct rte_mbuf **tx_pkts,
1321              uint16_t nb_pkts)
1322 {
1323         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1324         uint16_t n = 0;
1325
1326         /**
1327          * Begin scanning the H/W ring for done descriptors when the number
1328          * of available descriptors drops below tx_free_thresh. For each done
1329          * descriptor, free the associated buffer.
1330          */
1331         if (txq->nb_tx_free < txq->tx_free_thresh)
1332                 i40e_tx_free_bufs(txq);
1333
1334         /* Use available descriptor only */
1335         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1336         if (unlikely(!nb_pkts))
1337                 return 0;
1338
1339         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1340         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1341                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1342                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1343                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1344                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1345                                                 I40E_TXD_QW1_CMD_SHIFT);
1346                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1347                 txq->tx_tail = 0;
1348         }
1349
1350         /* Fill hardware descriptor ring with mbuf data */
1351         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1352         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1353
1354         /* Determin if RS bit needs to be set */
1355         if (txq->tx_tail > txq->tx_next_rs) {
1356                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1357                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1358                                                 I40E_TXD_QW1_CMD_SHIFT);
1359                 txq->tx_next_rs =
1360                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1361                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1362                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1363         }
1364
1365         if (txq->tx_tail >= txq->nb_tx_desc)
1366                 txq->tx_tail = 0;
1367
1368         /* Update the tx tail register */
1369         rte_wmb();
1370         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1371
1372         return nb_pkts;
1373 }
1374
1375 static uint16_t
1376 i40e_xmit_pkts_simple(void *tx_queue,
1377                       struct rte_mbuf **tx_pkts,
1378                       uint16_t nb_pkts)
1379 {
1380         uint16_t nb_tx = 0;
1381
1382         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1383                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1384                                                 tx_pkts, nb_pkts);
1385
1386         while (nb_pkts) {
1387                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1388                                                 I40E_TX_MAX_BURST);
1389
1390                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1391                                                 &tx_pkts[nb_tx], num);
1392                 nb_tx = (uint16_t)(nb_tx + ret);
1393                 nb_pkts = (uint16_t)(nb_pkts - ret);
1394                 if (ret < num)
1395                         break;
1396         }
1397
1398         return nb_tx;
1399 }
1400
1401 static uint16_t
1402 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1403                    uint16_t nb_pkts)
1404 {
1405         uint16_t nb_tx = 0;
1406         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1407
1408         while (nb_pkts) {
1409                 uint16_t ret, num;
1410
1411                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1412                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1413                                                 num);
1414                 nb_tx += ret;
1415                 nb_pkts -= ret;
1416                 if (ret < num)
1417                         break;
1418         }
1419
1420         return nb_tx;
1421 }
1422
1423 /*********************************************************************
1424  *
1425  *  TX prep functions
1426  *
1427  **********************************************************************/
1428 uint16_t
1429 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1430                 uint16_t nb_pkts)
1431 {
1432         int i, ret;
1433         uint64_t ol_flags;
1434         struct rte_mbuf *m;
1435
1436         for (i = 0; i < nb_pkts; i++) {
1437                 m = tx_pkts[i];
1438                 ol_flags = m->ol_flags;
1439
1440                 /* Check for m->nb_segs to not exceed the limits. */
1441                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1442                         if (m->nb_segs > I40E_TX_MAX_SEG ||
1443                             m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1444                                 rte_errno = -EINVAL;
1445                                 return i;
1446                         }
1447                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1448                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1449                         /* MSS outside the range (256B - 9674B) are considered
1450                          * malicious
1451                          */
1452                         rte_errno = -EINVAL;
1453                         return i;
1454                 }
1455
1456                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1457                         rte_errno = -ENOTSUP;
1458                         return i;
1459                 }
1460
1461 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1462                 ret = rte_validate_tx_offload(m);
1463                 if (ret != 0) {
1464                         rte_errno = ret;
1465                         return i;
1466                 }
1467 #endif
1468                 ret = rte_net_intel_cksum_prepare(m);
1469                 if (ret != 0) {
1470                         rte_errno = ret;
1471                         return i;
1472                 }
1473         }
1474         return i;
1475 }
1476
1477 /*
1478  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1479  * application used, which assume having sequential ones. But from driver's
1480  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1481  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1482  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1483  * use queue_idx from 0 to 95 to access queues, while real queue would be
1484  * different. This function will do a queue mapping to find VSI the queue
1485  * belongs to.
1486  */
1487 static struct i40e_vsi*
1488 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1489 {
1490         /* the queue in MAIN VSI range */
1491         if (queue_idx < pf->main_vsi->nb_qps)
1492                 return pf->main_vsi;
1493
1494         queue_idx -= pf->main_vsi->nb_qps;
1495
1496         /* queue_idx is greater than VMDQ VSIs range */
1497         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1498                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1499                 return NULL;
1500         }
1501
1502         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1503 }
1504
1505 static uint16_t
1506 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1507 {
1508         /* the queue in MAIN VSI range */
1509         if (queue_idx < pf->main_vsi->nb_qps)
1510                 return queue_idx;
1511
1512         /* It's VMDQ queues */
1513         queue_idx -= pf->main_vsi->nb_qps;
1514
1515         if (pf->nb_cfg_vmdq_vsi)
1516                 return queue_idx % pf->vmdq_nb_qps;
1517         else {
1518                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1519                 return (uint16_t)(-1);
1520         }
1521 }
1522
1523 int
1524 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1525 {
1526         struct i40e_rx_queue *rxq;
1527         int err = -1;
1528         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1529
1530         PMD_INIT_FUNC_TRACE();
1531
1532         if (rx_queue_id < dev->data->nb_rx_queues) {
1533                 rxq = dev->data->rx_queues[rx_queue_id];
1534
1535                 err = i40e_alloc_rx_queue_mbufs(rxq);
1536                 if (err) {
1537                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1538                         return err;
1539                 }
1540
1541                 rte_wmb();
1542
1543                 /* Init the RX tail regieter. */
1544                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1545
1546                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1547
1548                 if (err) {
1549                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1550                                     rx_queue_id);
1551
1552                         i40e_rx_queue_release_mbufs(rxq);
1553                         i40e_reset_rx_queue(rxq);
1554                 } else
1555                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1556         }
1557
1558         return err;
1559 }
1560
1561 int
1562 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1563 {
1564         struct i40e_rx_queue *rxq;
1565         int err;
1566         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1567
1568         if (rx_queue_id < dev->data->nb_rx_queues) {
1569                 rxq = dev->data->rx_queues[rx_queue_id];
1570
1571                 /*
1572                 * rx_queue_id is queue id application refers to, while
1573                 * rxq->reg_idx is the real queue index.
1574                 */
1575                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1576
1577                 if (err) {
1578                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1579                                     rx_queue_id);
1580                         return err;
1581                 }
1582                 i40e_rx_queue_release_mbufs(rxq);
1583                 i40e_reset_rx_queue(rxq);
1584                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1585         }
1586
1587         return 0;
1588 }
1589
1590 int
1591 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1592 {
1593         int err = -1;
1594         struct i40e_tx_queue *txq;
1595         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1596
1597         PMD_INIT_FUNC_TRACE();
1598
1599         if (tx_queue_id < dev->data->nb_tx_queues) {
1600                 txq = dev->data->tx_queues[tx_queue_id];
1601
1602                 /*
1603                 * tx_queue_id is queue id application refers to, while
1604                 * rxq->reg_idx is the real queue index.
1605                 */
1606                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1607                 if (err)
1608                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1609                                     tx_queue_id);
1610                 else
1611                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1612         }
1613
1614         return err;
1615 }
1616
1617 int
1618 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1619 {
1620         struct i40e_tx_queue *txq;
1621         int err;
1622         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1623
1624         if (tx_queue_id < dev->data->nb_tx_queues) {
1625                 txq = dev->data->tx_queues[tx_queue_id];
1626
1627                 /*
1628                 * tx_queue_id is queue id application refers to, while
1629                 * txq->reg_idx is the real queue index.
1630                 */
1631                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1632
1633                 if (err) {
1634                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1635                                     tx_queue_id);
1636                         return err;
1637                 }
1638
1639                 i40e_tx_queue_release_mbufs(txq);
1640                 i40e_reset_tx_queue(txq);
1641                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1642         }
1643
1644         return 0;
1645 }
1646
1647 const uint32_t *
1648 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1649 {
1650         static const uint32_t ptypes[] = {
1651                 /* refers to i40e_rxd_pkt_type_mapping() */
1652                 RTE_PTYPE_L2_ETHER,
1653                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1654                 RTE_PTYPE_L2_ETHER_LLDP,
1655                 RTE_PTYPE_L2_ETHER_ARP,
1656                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1657                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1658                 RTE_PTYPE_L4_FRAG,
1659                 RTE_PTYPE_L4_ICMP,
1660                 RTE_PTYPE_L4_NONFRAG,
1661                 RTE_PTYPE_L4_SCTP,
1662                 RTE_PTYPE_L4_TCP,
1663                 RTE_PTYPE_L4_UDP,
1664                 RTE_PTYPE_TUNNEL_GRENAT,
1665                 RTE_PTYPE_TUNNEL_IP,
1666                 RTE_PTYPE_INNER_L2_ETHER,
1667                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1668                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1669                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1670                 RTE_PTYPE_INNER_L4_FRAG,
1671                 RTE_PTYPE_INNER_L4_ICMP,
1672                 RTE_PTYPE_INNER_L4_NONFRAG,
1673                 RTE_PTYPE_INNER_L4_SCTP,
1674                 RTE_PTYPE_INNER_L4_TCP,
1675                 RTE_PTYPE_INNER_L4_UDP,
1676                 RTE_PTYPE_UNKNOWN
1677         };
1678
1679         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1680 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1681             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1682 #endif
1683             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1684             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1685             dev->rx_pkt_burst == i40e_recv_pkts_vec ||
1686             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
1687             dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2)
1688                 return ptypes;
1689         return NULL;
1690 }
1691
1692 static int
1693 i40e_check_rx_queue_offloads(struct rte_eth_dev *dev, uint64_t requested)
1694 {
1695         struct rte_eth_dev_info dev_info;
1696         uint64_t mandatory = dev->data->dev_conf.rxmode.offloads;
1697         uint64_t supported; /* All per port offloads */
1698
1699         dev->dev_ops->dev_infos_get(dev, &dev_info);
1700         supported = dev_info.rx_offload_capa ^ dev_info.rx_queue_offload_capa;
1701         if ((requested & dev_info.rx_offload_capa) != requested)
1702                 return 0; /* requested range check */
1703         return !((mandatory ^ requested) & supported);
1704 }
1705
1706 static int
1707 i40e_dev_first_queue(uint16_t idx, void **queues, int num)
1708 {
1709         uint16_t i;
1710
1711         for (i = 0; i < num; i++) {
1712                 if (i != idx && queues[i])
1713                         return 0;
1714         }
1715
1716         return 1;
1717 }
1718
1719 static int
1720 i40e_dev_rx_queue_setup_runtime(struct rte_eth_dev *dev,
1721                                 struct i40e_rx_queue *rxq)
1722 {
1723         struct i40e_adapter *ad =
1724                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1725         int use_def_burst_func =
1726                 check_rx_burst_bulk_alloc_preconditions(rxq);
1727         uint16_t buf_size =
1728                 (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
1729                            RTE_PKTMBUF_HEADROOM);
1730         int use_scattered_rx =
1731                 ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size);
1732
1733         if (i40e_rx_queue_init(rxq) != I40E_SUCCESS) {
1734                 PMD_DRV_LOG(ERR,
1735                             "Failed to do RX queue initialization");
1736                 return -EINVAL;
1737         }
1738
1739         if (i40e_dev_first_queue(rxq->queue_id,
1740                                  dev->data->rx_queues,
1741                                  dev->data->nb_rx_queues)) {
1742                 /**
1743                  * If it is the first queue to setup,
1744                  * set all flags to default and call
1745                  * i40e_set_rx_function.
1746                  */
1747                 ad->rx_bulk_alloc_allowed = true;
1748                 ad->rx_vec_allowed = true;
1749                 dev->data->scattered_rx = use_scattered_rx;
1750                 if (use_def_burst_func)
1751                         ad->rx_bulk_alloc_allowed = false;
1752                 i40e_set_rx_function(dev);
1753                 return 0;
1754         }
1755
1756         /* check bulk alloc conflict */
1757         if (ad->rx_bulk_alloc_allowed && use_def_burst_func) {
1758                 PMD_DRV_LOG(ERR, "Can't use default burst.");
1759                 return -EINVAL;
1760         }
1761         /* check scatterred conflict */
1762         if (!dev->data->scattered_rx && use_scattered_rx) {
1763                 PMD_DRV_LOG(ERR, "Scattered rx is required.");
1764                 return -EINVAL;
1765         }
1766         /* check vector conflict */
1767         if (ad->rx_vec_allowed && i40e_rxq_vec_setup(rxq)) {
1768                 PMD_DRV_LOG(ERR, "Failed vector rx setup.");
1769                 return -EINVAL;
1770         }
1771
1772         return 0;
1773 }
1774
1775 int
1776 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1777                         uint16_t queue_idx,
1778                         uint16_t nb_desc,
1779                         unsigned int socket_id,
1780                         const struct rte_eth_rxconf *rx_conf,
1781                         struct rte_mempool *mp)
1782 {
1783         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1784         struct i40e_adapter *ad =
1785                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1786         struct i40e_vsi *vsi;
1787         struct i40e_pf *pf = NULL;
1788         struct i40e_vf *vf = NULL;
1789         struct i40e_rx_queue *rxq;
1790         const struct rte_memzone *rz;
1791         uint32_t ring_size;
1792         uint16_t len, i;
1793         uint16_t reg_idx, base, bsf, tc_mapping;
1794         int q_offset, use_def_burst_func = 1;
1795         struct rte_eth_dev_info dev_info;
1796
1797         if (!i40e_check_rx_queue_offloads(dev, rx_conf->offloads)) {
1798                 dev->dev_ops->dev_infos_get(dev, &dev_info);
1799                 PMD_INIT_LOG(ERR, "%p: Rx queue offloads 0x%" PRIx64
1800                         " don't match port  offloads 0x%" PRIx64
1801                         " or supported offloads 0x%" PRIx64,
1802                         (void *)dev, rx_conf->offloads,
1803                         dev->data->dev_conf.rxmode.offloads,
1804                         dev_info.rx_offload_capa);
1805                 return -ENOTSUP;
1806         }
1807
1808         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1809                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1810                 vsi = &vf->vsi;
1811                 if (!vsi)
1812                         return -EINVAL;
1813                 reg_idx = queue_idx;
1814         } else {
1815                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1816                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1817                 if (!vsi)
1818                         return -EINVAL;
1819                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
1820                 if (q_offset < 0)
1821                         return -EINVAL;
1822                 reg_idx = vsi->base_queue + q_offset;
1823         }
1824
1825         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1826             (nb_desc > I40E_MAX_RING_DESC) ||
1827             (nb_desc < I40E_MIN_RING_DESC)) {
1828                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1829                             "invalid", nb_desc);
1830                 return -EINVAL;
1831         }
1832
1833         /* Free memory if needed */
1834         if (dev->data->rx_queues[queue_idx]) {
1835                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1836                 dev->data->rx_queues[queue_idx] = NULL;
1837         }
1838
1839         /* Allocate the rx queue data structure */
1840         rxq = rte_zmalloc_socket("i40e rx queue",
1841                                  sizeof(struct i40e_rx_queue),
1842                                  RTE_CACHE_LINE_SIZE,
1843                                  socket_id);
1844         if (!rxq) {
1845                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1846                             "rx queue data structure");
1847                 return -ENOMEM;
1848         }
1849         rxq->mp = mp;
1850         rxq->nb_rx_desc = nb_desc;
1851         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1852         rxq->queue_id = queue_idx;
1853         rxq->reg_idx = reg_idx;
1854         rxq->port_id = dev->data->port_id;
1855         rxq->crc_len = (uint8_t)((dev->data->dev_conf.rxmode.offloads &
1856                         DEV_RX_OFFLOAD_CRC_STRIP) ? 0 : ETHER_CRC_LEN);
1857         rxq->drop_en = rx_conf->rx_drop_en;
1858         rxq->vsi = vsi;
1859         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1860         rxq->offloads = rx_conf->offloads;
1861
1862         /* Allocate the maximun number of RX ring hardware descriptor. */
1863         len = I40E_MAX_RING_DESC;
1864
1865         /**
1866          * Allocating a little more memory because vectorized/bulk_alloc Rx
1867          * functions doesn't check boundaries each time.
1868          */
1869         len += RTE_PMD_I40E_RX_MAX_BURST;
1870
1871         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1872                               I40E_DMA_MEM_ALIGN);
1873
1874         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1875                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1876         if (!rz) {
1877                 i40e_dev_rx_queue_release(rxq);
1878                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1879                 return -ENOMEM;
1880         }
1881
1882         /* Zero all the descriptors in the ring. */
1883         memset(rz->addr, 0, ring_size);
1884
1885         rxq->rx_ring_phys_addr = rz->iova;
1886         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1887
1888         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1889
1890         /* Allocate the software ring. */
1891         rxq->sw_ring =
1892                 rte_zmalloc_socket("i40e rx sw ring",
1893                                    sizeof(struct i40e_rx_entry) * len,
1894                                    RTE_CACHE_LINE_SIZE,
1895                                    socket_id);
1896         if (!rxq->sw_ring) {
1897                 i40e_dev_rx_queue_release(rxq);
1898                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1899                 return -ENOMEM;
1900         }
1901
1902         i40e_reset_rx_queue(rxq);
1903         rxq->q_set = TRUE;
1904
1905         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1906                 if (!(vsi->enabled_tc & (1 << i)))
1907                         continue;
1908                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1909                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1910                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1911                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1912                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1913
1914                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1915                         rxq->dcb_tc = i;
1916         }
1917
1918         if (dev->data->dev_started) {
1919                 if (i40e_dev_rx_queue_setup_runtime(dev, rxq)) {
1920                         i40e_dev_rx_queue_release(rxq);
1921                         return -EINVAL;
1922                 }
1923         } else {
1924                 use_def_burst_func =
1925                         check_rx_burst_bulk_alloc_preconditions(rxq);
1926                 if (!use_def_burst_func) {
1927 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1928                         PMD_INIT_LOG(DEBUG,
1929                           "Rx Burst Bulk Alloc Preconditions are "
1930                           "satisfied. Rx Burst Bulk Alloc function will be "
1931                           "used on port=%d, queue=%d.",
1932                           rxq->port_id, rxq->queue_id);
1933 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1934                 } else {
1935                         PMD_INIT_LOG(DEBUG,
1936                           "Rx Burst Bulk Alloc Preconditions are "
1937                           "not satisfied, Scattered Rx is requested, "
1938                           "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1939                           "not enabled on port=%d, queue=%d.",
1940                           rxq->port_id, rxq->queue_id);
1941                         ad->rx_bulk_alloc_allowed = false;
1942                 }
1943         }
1944
1945         dev->data->rx_queues[queue_idx] = rxq;
1946         return 0;
1947 }
1948
1949 void
1950 i40e_dev_rx_queue_release(void *rxq)
1951 {
1952         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1953
1954         if (!q) {
1955                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1956                 return;
1957         }
1958
1959         i40e_rx_queue_release_mbufs(q);
1960         rte_free(q->sw_ring);
1961         rte_free(q);
1962 }
1963
1964 uint32_t
1965 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1966 {
1967 #define I40E_RXQ_SCAN_INTERVAL 4
1968         volatile union i40e_rx_desc *rxdp;
1969         struct i40e_rx_queue *rxq;
1970         uint16_t desc = 0;
1971
1972         rxq = dev->data->rx_queues[rx_queue_id];
1973         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1974         while ((desc < rxq->nb_rx_desc) &&
1975                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1976                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1977                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1978                 /**
1979                  * Check the DD bit of a rx descriptor of each 4 in a group,
1980                  * to avoid checking too frequently and downgrading performance
1981                  * too much.
1982                  */
1983                 desc += I40E_RXQ_SCAN_INTERVAL;
1984                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1985                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1986                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1987                                         desc - rxq->nb_rx_desc]);
1988         }
1989
1990         return desc;
1991 }
1992
1993 int
1994 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1995 {
1996         volatile union i40e_rx_desc *rxdp;
1997         struct i40e_rx_queue *rxq = rx_queue;
1998         uint16_t desc;
1999         int ret;
2000
2001         if (unlikely(offset >= rxq->nb_rx_desc)) {
2002                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
2003                 return 0;
2004         }
2005
2006         desc = rxq->rx_tail + offset;
2007         if (desc >= rxq->nb_rx_desc)
2008                 desc -= rxq->nb_rx_desc;
2009
2010         rxdp = &(rxq->rx_ring[desc]);
2011
2012         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2013                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2014                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2015
2016         return ret;
2017 }
2018
2019 int
2020 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
2021 {
2022         struct i40e_rx_queue *rxq = rx_queue;
2023         volatile uint64_t *status;
2024         uint64_t mask;
2025         uint32_t desc;
2026
2027         if (unlikely(offset >= rxq->nb_rx_desc))
2028                 return -EINVAL;
2029
2030         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2031                 return RTE_ETH_RX_DESC_UNAVAIL;
2032
2033         desc = rxq->rx_tail + offset;
2034         if (desc >= rxq->nb_rx_desc)
2035                 desc -= rxq->nb_rx_desc;
2036
2037         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2038         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
2039                 << I40E_RXD_QW1_STATUS_SHIFT);
2040         if (*status & mask)
2041                 return RTE_ETH_RX_DESC_DONE;
2042
2043         return RTE_ETH_RX_DESC_AVAIL;
2044 }
2045
2046 int
2047 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
2048 {
2049         struct i40e_tx_queue *txq = tx_queue;
2050         volatile uint64_t *status;
2051         uint64_t mask, expect;
2052         uint32_t desc;
2053
2054         if (unlikely(offset >= txq->nb_tx_desc))
2055                 return -EINVAL;
2056
2057         desc = txq->tx_tail + offset;
2058         /* go to next desc that has the RS bit */
2059         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
2060                 txq->tx_rs_thresh;
2061         if (desc >= txq->nb_tx_desc) {
2062                 desc -= txq->nb_tx_desc;
2063                 if (desc >= txq->nb_tx_desc)
2064                         desc -= txq->nb_tx_desc;
2065         }
2066
2067         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2068         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
2069         expect = rte_cpu_to_le_64(
2070                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
2071         if ((*status & mask) == expect)
2072                 return RTE_ETH_TX_DESC_DONE;
2073
2074         return RTE_ETH_TX_DESC_FULL;
2075 }
2076
2077 static int
2078 i40e_check_tx_queue_offloads(struct rte_eth_dev *dev, uint64_t requested)
2079 {
2080         struct rte_eth_dev_info dev_info;
2081         uint64_t mandatory = dev->data->dev_conf.txmode.offloads;
2082         uint64_t supported; /* All per port offloads */
2083
2084         dev->dev_ops->dev_infos_get(dev, &dev_info);
2085         supported = dev_info.tx_offload_capa ^ dev_info.tx_queue_offload_capa;
2086         if ((requested & dev_info.tx_offload_capa) != requested)
2087                 return 0; /* requested range check */
2088         return !((mandatory ^ requested) & supported);
2089 }
2090
2091 static int
2092 i40e_dev_tx_queue_setup_runtime(struct rte_eth_dev *dev,
2093                                 struct i40e_tx_queue *txq)
2094 {
2095         struct i40e_adapter *ad =
2096                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2097
2098         if (i40e_tx_queue_init(txq) != I40E_SUCCESS) {
2099                 PMD_DRV_LOG(ERR,
2100                             "Failed to do TX queue initialization");
2101                 return -EINVAL;
2102         }
2103
2104         if (i40e_dev_first_queue(txq->queue_id,
2105                                  dev->data->tx_queues,
2106                                  dev->data->nb_tx_queues)) {
2107                 /**
2108                  * If it is the first queue to setup,
2109                  * set all flags and call
2110                  * i40e_set_tx_function.
2111                  */
2112                 i40e_set_tx_function_flag(dev, txq);
2113                 i40e_set_tx_function(dev);
2114                 return 0;
2115         }
2116
2117         /* check vector conflict */
2118         if (ad->tx_vec_allowed) {
2119                 if (txq->tx_rs_thresh > RTE_I40E_TX_MAX_FREE_BUF_SZ ||
2120                     i40e_txq_vec_setup(txq)) {
2121                         PMD_DRV_LOG(ERR, "Failed vector tx setup.");
2122                         return -EINVAL;
2123                 }
2124         }
2125         /* check simple tx conflict */
2126         if (ad->tx_simple_allowed) {
2127                 if (txq->offloads != 0 ||
2128                                 txq->tx_rs_thresh < RTE_PMD_I40E_TX_MAX_BURST) {
2129                         PMD_DRV_LOG(ERR, "No-simple tx is required.");
2130                         return -EINVAL;
2131                 }
2132         }
2133
2134         return 0;
2135 }
2136
2137 int
2138 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2139                         uint16_t queue_idx,
2140                         uint16_t nb_desc,
2141                         unsigned int socket_id,
2142                         const struct rte_eth_txconf *tx_conf)
2143 {
2144         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2145         struct i40e_vsi *vsi;
2146         struct i40e_pf *pf = NULL;
2147         struct i40e_vf *vf = NULL;
2148         struct i40e_tx_queue *txq;
2149         const struct rte_memzone *tz;
2150         uint32_t ring_size;
2151         uint16_t tx_rs_thresh, tx_free_thresh;
2152         uint16_t reg_idx, i, base, bsf, tc_mapping;
2153         int q_offset;
2154         struct rte_eth_dev_info dev_info;
2155
2156         if (!i40e_check_tx_queue_offloads(dev, tx_conf->offloads)) {
2157                 dev->dev_ops->dev_infos_get(dev, &dev_info);
2158                 PMD_INIT_LOG(ERR, "%p: Tx queue offloads 0x%" PRIx64
2159                         " don't match port  offloads 0x%" PRIx64
2160                         " or supported offloads 0x%" PRIx64,
2161                         (void *)dev, tx_conf->offloads,
2162                         dev->data->dev_conf.txmode.offloads,
2163                         dev_info.tx_offload_capa);
2164                         return -ENOTSUP;
2165         }
2166
2167         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2168                 vf = I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2169                 vsi = &vf->vsi;
2170                 if (!vsi)
2171                         return -EINVAL;
2172                 reg_idx = queue_idx;
2173         } else {
2174                 pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2175                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2176                 if (!vsi)
2177                         return -EINVAL;
2178                 q_offset = i40e_get_queue_offset_by_qindex(pf, queue_idx);
2179                 if (q_offset < 0)
2180                         return -EINVAL;
2181                 reg_idx = vsi->base_queue + q_offset;
2182         }
2183
2184         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2185             (nb_desc > I40E_MAX_RING_DESC) ||
2186             (nb_desc < I40E_MIN_RING_DESC)) {
2187                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2188                             "invalid", nb_desc);
2189                 return -EINVAL;
2190         }
2191
2192         /**
2193          * The following two parameters control the setting of the RS bit on
2194          * transmit descriptors. TX descriptors will have their RS bit set
2195          * after txq->tx_rs_thresh descriptors have been used. The TX
2196          * descriptor ring will be cleaned after txq->tx_free_thresh
2197          * descriptors are used or if the number of descriptors required to
2198          * transmit a packet is greater than the number of free TX descriptors.
2199          *
2200          * The following constraints must be satisfied:
2201          *  - tx_rs_thresh must be greater than 0.
2202          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2203          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2204          *  - tx_rs_thresh must be a divisor of the ring size.
2205          *  - tx_free_thresh must be greater than 0.
2206          *  - tx_free_thresh must be less than the size of the ring minus 3.
2207          *
2208          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2209          * race condition, hence the maximum threshold constraints. When set
2210          * to zero use default values.
2211          */
2212         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2213                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2214         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2215                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2216         if (tx_rs_thresh >= (nb_desc - 2)) {
2217                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2218                              "number of TX descriptors minus 2. "
2219                              "(tx_rs_thresh=%u port=%d queue=%d)",
2220                              (unsigned int)tx_rs_thresh,
2221                              (int)dev->data->port_id,
2222                              (int)queue_idx);
2223                 return I40E_ERR_PARAM;
2224         }
2225         if (tx_free_thresh >= (nb_desc - 3)) {
2226                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2227                              "number of TX descriptors minus 3. "
2228                              "(tx_free_thresh=%u port=%d queue=%d)",
2229                              (unsigned int)tx_free_thresh,
2230                              (int)dev->data->port_id,
2231                              (int)queue_idx);
2232                 return I40E_ERR_PARAM;
2233         }
2234         if (tx_rs_thresh > tx_free_thresh) {
2235                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2236                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2237                              " tx_rs_thresh=%u port=%d queue=%d)",
2238                              (unsigned int)tx_free_thresh,
2239                              (unsigned int)tx_rs_thresh,
2240                              (int)dev->data->port_id,
2241                              (int)queue_idx);
2242                 return I40E_ERR_PARAM;
2243         }
2244         if ((nb_desc % tx_rs_thresh) != 0) {
2245                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2246                              "number of TX descriptors. (tx_rs_thresh=%u"
2247                              " port=%d queue=%d)",
2248                              (unsigned int)tx_rs_thresh,
2249                              (int)dev->data->port_id,
2250                              (int)queue_idx);
2251                 return I40E_ERR_PARAM;
2252         }
2253         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2254                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2255                              "tx_rs_thresh is greater than 1. "
2256                              "(tx_rs_thresh=%u port=%d queue=%d)",
2257                              (unsigned int)tx_rs_thresh,
2258                              (int)dev->data->port_id,
2259                              (int)queue_idx);
2260                 return I40E_ERR_PARAM;
2261         }
2262
2263         /* Free memory if needed. */
2264         if (dev->data->tx_queues[queue_idx]) {
2265                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2266                 dev->data->tx_queues[queue_idx] = NULL;
2267         }
2268
2269         /* Allocate the TX queue data structure. */
2270         txq = rte_zmalloc_socket("i40e tx queue",
2271                                   sizeof(struct i40e_tx_queue),
2272                                   RTE_CACHE_LINE_SIZE,
2273                                   socket_id);
2274         if (!txq) {
2275                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2276                             "tx queue structure");
2277                 return -ENOMEM;
2278         }
2279
2280         /* Allocate TX hardware ring descriptors. */
2281         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2282         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2283         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2284                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2285         if (!tz) {
2286                 i40e_dev_tx_queue_release(txq);
2287                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2288                 return -ENOMEM;
2289         }
2290
2291         txq->nb_tx_desc = nb_desc;
2292         txq->tx_rs_thresh = tx_rs_thresh;
2293         txq->tx_free_thresh = tx_free_thresh;
2294         txq->pthresh = tx_conf->tx_thresh.pthresh;
2295         txq->hthresh = tx_conf->tx_thresh.hthresh;
2296         txq->wthresh = tx_conf->tx_thresh.wthresh;
2297         txq->queue_id = queue_idx;
2298         txq->reg_idx = reg_idx;
2299         txq->port_id = dev->data->port_id;
2300         txq->offloads = tx_conf->offloads;
2301         txq->vsi = vsi;
2302         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2303
2304         txq->tx_ring_phys_addr = tz->iova;
2305         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2306
2307         /* Allocate software ring */
2308         txq->sw_ring =
2309                 rte_zmalloc_socket("i40e tx sw ring",
2310                                    sizeof(struct i40e_tx_entry) * nb_desc,
2311                                    RTE_CACHE_LINE_SIZE,
2312                                    socket_id);
2313         if (!txq->sw_ring) {
2314                 i40e_dev_tx_queue_release(txq);
2315                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2316                 return -ENOMEM;
2317         }
2318
2319         i40e_reset_tx_queue(txq);
2320         txq->q_set = TRUE;
2321
2322         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2323                 if (!(vsi->enabled_tc & (1 << i)))
2324                         continue;
2325                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2326                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2327                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2328                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2329                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2330
2331                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2332                         txq->dcb_tc = i;
2333         }
2334
2335         if (dev->data->dev_started) {
2336                 if (i40e_dev_tx_queue_setup_runtime(dev, txq)) {
2337                         i40e_dev_tx_queue_release(txq);
2338                         return -EINVAL;
2339                 }
2340         } else {
2341                 /**
2342                  * Use a simple TX queue without offloads or
2343                  * multi segs if possible
2344                  */
2345                 i40e_set_tx_function_flag(dev, txq);
2346         }
2347         dev->data->tx_queues[queue_idx] = txq;
2348
2349         return 0;
2350 }
2351
2352 void
2353 i40e_dev_tx_queue_release(void *txq)
2354 {
2355         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2356
2357         if (!q) {
2358                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2359                 return;
2360         }
2361
2362         i40e_tx_queue_release_mbufs(q);
2363         rte_free(q->sw_ring);
2364         rte_free(q);
2365 }
2366
2367 const struct rte_memzone *
2368 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2369 {
2370         const struct rte_memzone *mz;
2371
2372         mz = rte_memzone_lookup(name);
2373         if (mz)
2374                 return mz;
2375
2376         mz = rte_memzone_reserve_aligned(name, len, socket_id,
2377                         RTE_MEMZONE_IOVA_CONTIG, I40E_RING_BASE_ALIGN);
2378         return mz;
2379 }
2380
2381 void
2382 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2383 {
2384         uint16_t i;
2385
2386         /* SSE Vector driver has a different way of releasing mbufs. */
2387         if (rxq->rx_using_sse) {
2388                 i40e_rx_queue_release_mbufs_vec(rxq);
2389                 return;
2390         }
2391
2392         if (!rxq->sw_ring) {
2393                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2394                 return;
2395         }
2396
2397         for (i = 0; i < rxq->nb_rx_desc; i++) {
2398                 if (rxq->sw_ring[i].mbuf) {
2399                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2400                         rxq->sw_ring[i].mbuf = NULL;
2401                 }
2402         }
2403 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2404         if (rxq->rx_nb_avail == 0)
2405                 return;
2406         for (i = 0; i < rxq->rx_nb_avail; i++) {
2407                 struct rte_mbuf *mbuf;
2408
2409                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2410                 rte_pktmbuf_free_seg(mbuf);
2411         }
2412         rxq->rx_nb_avail = 0;
2413 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2414 }
2415
2416 void
2417 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2418 {
2419         unsigned i;
2420         uint16_t len;
2421
2422         if (!rxq) {
2423                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2424                 return;
2425         }
2426
2427 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2428         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2429                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2430         else
2431 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2432                 len = rxq->nb_rx_desc;
2433
2434         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2435                 ((volatile char *)rxq->rx_ring)[i] = 0;
2436
2437         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2438         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2439                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2440
2441 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2442         rxq->rx_nb_avail = 0;
2443         rxq->rx_next_avail = 0;
2444         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2445 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2446         rxq->rx_tail = 0;
2447         rxq->nb_rx_hold = 0;
2448         rxq->pkt_first_seg = NULL;
2449         rxq->pkt_last_seg = NULL;
2450
2451         rxq->rxrearm_start = 0;
2452         rxq->rxrearm_nb = 0;
2453 }
2454
2455 void
2456 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2457 {
2458         struct rte_eth_dev *dev;
2459         uint16_t i;
2460
2461         dev = &rte_eth_devices[txq->port_id];
2462
2463         if (!txq || !txq->sw_ring) {
2464                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2465                 return;
2466         }
2467
2468         /**
2469          *  vPMD tx will not set sw_ring's mbuf to NULL after free,
2470          *  so need to free remains more carefully.
2471          */
2472         if (dev->tx_pkt_burst == i40e_xmit_pkts_vec_avx2 ||
2473                         dev->tx_pkt_burst == i40e_xmit_pkts_vec) {
2474                 i = txq->tx_next_dd - txq->tx_rs_thresh + 1;
2475                 if (txq->tx_tail < i) {
2476                         for (; i < txq->nb_tx_desc; i++) {
2477                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2478                                 txq->sw_ring[i].mbuf = NULL;
2479                         }
2480                         i = 0;
2481                 }
2482                 for (; i < txq->tx_tail; i++) {
2483                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2484                         txq->sw_ring[i].mbuf = NULL;
2485                 }
2486         } else {
2487                 for (i = 0; i < txq->nb_tx_desc; i++) {
2488                         if (txq->sw_ring[i].mbuf) {
2489                                 rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2490                                 txq->sw_ring[i].mbuf = NULL;
2491                         }
2492                 }
2493         }
2494 }
2495
2496 void
2497 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2498 {
2499         struct i40e_tx_entry *txe;
2500         uint16_t i, prev, size;
2501
2502         if (!txq) {
2503                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2504                 return;
2505         }
2506
2507         txe = txq->sw_ring;
2508         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2509         for (i = 0; i < size; i++)
2510                 ((volatile char *)txq->tx_ring)[i] = 0;
2511
2512         prev = (uint16_t)(txq->nb_tx_desc - 1);
2513         for (i = 0; i < txq->nb_tx_desc; i++) {
2514                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2515
2516                 txd->cmd_type_offset_bsz =
2517                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2518                 txe[i].mbuf =  NULL;
2519                 txe[i].last_id = i;
2520                 txe[prev].next_id = i;
2521                 prev = i;
2522         }
2523
2524         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2525         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2526
2527         txq->tx_tail = 0;
2528         txq->nb_tx_used = 0;
2529
2530         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2531         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2532 }
2533
2534 /* Init the TX queue in hardware */
2535 int
2536 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2537 {
2538         enum i40e_status_code err = I40E_SUCCESS;
2539         struct i40e_vsi *vsi = txq->vsi;
2540         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2541         uint16_t pf_q = txq->reg_idx;
2542         struct i40e_hmc_obj_txq tx_ctx;
2543         uint32_t qtx_ctl;
2544
2545         /* clear the context structure first */
2546         memset(&tx_ctx, 0, sizeof(tx_ctx));
2547         tx_ctx.new_context = 1;
2548         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2549         tx_ctx.qlen = txq->nb_tx_desc;
2550
2551 #ifdef RTE_LIBRTE_IEEE1588
2552         tx_ctx.timesync_ena = 1;
2553 #endif
2554         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2555         if (vsi->type == I40E_VSI_FDIR)
2556                 tx_ctx.fd_ena = TRUE;
2557
2558         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2559         if (err != I40E_SUCCESS) {
2560                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2561                 return err;
2562         }
2563
2564         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2565         if (err != I40E_SUCCESS) {
2566                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2567                 return err;
2568         }
2569
2570         /* Now associate this queue with this PCI function */
2571         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2572         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2573                                         I40E_QTX_CTL_PF_INDX_MASK);
2574         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2575         I40E_WRITE_FLUSH(hw);
2576
2577         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2578
2579         return err;
2580 }
2581
2582 int
2583 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2584 {
2585         struct i40e_rx_entry *rxe = rxq->sw_ring;
2586         uint64_t dma_addr;
2587         uint16_t i;
2588
2589         for (i = 0; i < rxq->nb_rx_desc; i++) {
2590                 volatile union i40e_rx_desc *rxd;
2591                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2592
2593                 if (unlikely(!mbuf)) {
2594                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2595                         return -ENOMEM;
2596                 }
2597
2598                 rte_mbuf_refcnt_set(mbuf, 1);
2599                 mbuf->next = NULL;
2600                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2601                 mbuf->nb_segs = 1;
2602                 mbuf->port = rxq->port_id;
2603
2604                 dma_addr =
2605                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
2606
2607                 rxd = &rxq->rx_ring[i];
2608                 rxd->read.pkt_addr = dma_addr;
2609                 rxd->read.hdr_addr = 0;
2610 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2611                 rxd->read.rsvd1 = 0;
2612                 rxd->read.rsvd2 = 0;
2613 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2614
2615                 rxe[i].mbuf = mbuf;
2616         }
2617
2618         return 0;
2619 }
2620
2621 /*
2622  * Calculate the buffer length, and check the jumbo frame
2623  * and maximum packet length.
2624  */
2625 static int
2626 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2627 {
2628         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2629         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2630         struct rte_eth_dev_data *data = pf->dev_data;
2631         uint16_t buf_size, len;
2632
2633         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2634                 RTE_PKTMBUF_HEADROOM);
2635
2636         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2637                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2638         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2639                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2640                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2641                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2642                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2643                 rxq->hs_mode = i40e_header_split_enabled;
2644                 break;
2645         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2646         default:
2647                 rxq->rx_hdr_len = 0;
2648                 rxq->rx_buf_len = RTE_ALIGN_FLOOR(buf_size,
2649                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2650                 rxq->hs_mode = i40e_header_split_none;
2651                 break;
2652         }
2653
2654         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2655         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2656         if (data->dev_conf.rxmode.offloads & DEV_RX_OFFLOAD_JUMBO_FRAME) {
2657                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2658                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2659                         PMD_DRV_LOG(ERR, "maximum packet length must "
2660                                     "be larger than %u and smaller than %u,"
2661                                     "as jumbo frame is enabled",
2662                                     (uint32_t)ETHER_MAX_LEN,
2663                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2664                         return I40E_ERR_CONFIG;
2665                 }
2666         } else {
2667                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2668                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2669                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2670                                     "larger than %u and smaller than %u, "
2671                                     "as jumbo frame is disabled",
2672                                     (uint32_t)ETHER_MIN_LEN,
2673                                     (uint32_t)ETHER_MAX_LEN);
2674                         return I40E_ERR_CONFIG;
2675                 }
2676         }
2677
2678         return 0;
2679 }
2680
2681 /* Init the RX queue in hardware */
2682 int
2683 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2684 {
2685         int err = I40E_SUCCESS;
2686         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2687         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2688         uint16_t pf_q = rxq->reg_idx;
2689         uint16_t buf_size;
2690         struct i40e_hmc_obj_rxq rx_ctx;
2691
2692         err = i40e_rx_queue_config(rxq);
2693         if (err < 0) {
2694                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2695                 return err;
2696         }
2697
2698         /* Clear the context structure first */
2699         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2700         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2701         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2702
2703         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2704         rx_ctx.qlen = rxq->nb_rx_desc;
2705 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2706         rx_ctx.dsize = 1;
2707 #endif
2708         rx_ctx.dtype = rxq->hs_mode;
2709         if (rxq->hs_mode)
2710                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2711         else
2712                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2713         rx_ctx.rxmax = rxq->max_pkt_len;
2714         rx_ctx.tphrdesc_ena = 1;
2715         rx_ctx.tphwdesc_ena = 1;
2716         rx_ctx.tphdata_ena = 1;
2717         rx_ctx.tphhead_ena = 1;
2718         rx_ctx.lrxqthresh = 2;
2719         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2720         rx_ctx.l2tsel = 1;
2721         /* showiv indicates if inner VLAN is stripped inside of tunnel
2722          * packet. When set it to 1, vlan information is stripped from
2723          * the inner header, but the hardware does not put it in the
2724          * descriptor. So set it zero by default.
2725          */
2726         rx_ctx.showiv = 0;
2727         rx_ctx.prefena = 1;
2728
2729         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2730         if (err != I40E_SUCCESS) {
2731                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2732                 return err;
2733         }
2734         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2735         if (err != I40E_SUCCESS) {
2736                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2737                 return err;
2738         }
2739
2740         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2741
2742         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2743                 RTE_PKTMBUF_HEADROOM);
2744
2745         /* Check if scattered RX needs to be used. */
2746         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2747                 dev_data->scattered_rx = 1;
2748         }
2749
2750         /* Init the RX tail regieter. */
2751         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2752
2753         return 0;
2754 }
2755
2756 void
2757 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2758 {
2759         uint16_t i;
2760
2761         PMD_INIT_FUNC_TRACE();
2762
2763         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2764                 if (!dev->data->tx_queues[i])
2765                         continue;
2766                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2767                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2768         }
2769
2770         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2771                 if (!dev->data->rx_queues[i])
2772                         continue;
2773                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2774                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2775         }
2776 }
2777
2778 void
2779 i40e_dev_free_queues(struct rte_eth_dev *dev)
2780 {
2781         uint16_t i;
2782
2783         PMD_INIT_FUNC_TRACE();
2784
2785         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2786                 if (!dev->data->rx_queues[i])
2787                         continue;
2788                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2789                 dev->data->rx_queues[i] = NULL;
2790         }
2791         dev->data->nb_rx_queues = 0;
2792
2793         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2794                 if (!dev->data->tx_queues[i])
2795                         continue;
2796                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2797                 dev->data->tx_queues[i] = NULL;
2798         }
2799         dev->data->nb_tx_queues = 0;
2800 }
2801
2802 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2803 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2804
2805 enum i40e_status_code
2806 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2807 {
2808         struct i40e_tx_queue *txq;
2809         const struct rte_memzone *tz = NULL;
2810         uint32_t ring_size;
2811         struct rte_eth_dev *dev;
2812
2813         if (!pf) {
2814                 PMD_DRV_LOG(ERR, "PF is not available");
2815                 return I40E_ERR_BAD_PTR;
2816         }
2817
2818         dev = pf->adapter->eth_dev;
2819
2820         /* Allocate the TX queue data structure. */
2821         txq = rte_zmalloc_socket("i40e fdir tx queue",
2822                                   sizeof(struct i40e_tx_queue),
2823                                   RTE_CACHE_LINE_SIZE,
2824                                   SOCKET_ID_ANY);
2825         if (!txq) {
2826                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2827                                         "tx queue structure.");
2828                 return I40E_ERR_NO_MEMORY;
2829         }
2830
2831         /* Allocate TX hardware ring descriptors. */
2832         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2833         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2834
2835         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2836                                       I40E_FDIR_QUEUE_ID, ring_size,
2837                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2838         if (!tz) {
2839                 i40e_dev_tx_queue_release(txq);
2840                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2841                 return I40E_ERR_NO_MEMORY;
2842         }
2843
2844         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2845         txq->queue_id = I40E_FDIR_QUEUE_ID;
2846         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2847         txq->vsi = pf->fdir.fdir_vsi;
2848
2849         txq->tx_ring_phys_addr = tz->iova;
2850         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2851         /*
2852          * don't need to allocate software ring and reset for the fdir
2853          * program queue just set the queue has been configured.
2854          */
2855         txq->q_set = TRUE;
2856         pf->fdir.txq = txq;
2857
2858         return I40E_SUCCESS;
2859 }
2860
2861 enum i40e_status_code
2862 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2863 {
2864         struct i40e_rx_queue *rxq;
2865         const struct rte_memzone *rz = NULL;
2866         uint32_t ring_size;
2867         struct rte_eth_dev *dev;
2868
2869         if (!pf) {
2870                 PMD_DRV_LOG(ERR, "PF is not available");
2871                 return I40E_ERR_BAD_PTR;
2872         }
2873
2874         dev = pf->adapter->eth_dev;
2875
2876         /* Allocate the RX queue data structure. */
2877         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2878                                   sizeof(struct i40e_rx_queue),
2879                                   RTE_CACHE_LINE_SIZE,
2880                                   SOCKET_ID_ANY);
2881         if (!rxq) {
2882                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2883                                         "rx queue structure.");
2884                 return I40E_ERR_NO_MEMORY;
2885         }
2886
2887         /* Allocate RX hardware ring descriptors. */
2888         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2889         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2890
2891         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2892                                       I40E_FDIR_QUEUE_ID, ring_size,
2893                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2894         if (!rz) {
2895                 i40e_dev_rx_queue_release(rxq);
2896                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2897                 return I40E_ERR_NO_MEMORY;
2898         }
2899
2900         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2901         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2902         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2903         rxq->vsi = pf->fdir.fdir_vsi;
2904
2905         rxq->rx_ring_phys_addr = rz->iova;
2906         memset(rz->addr, 0, I40E_FDIR_NUM_RX_DESC * sizeof(union i40e_rx_desc));
2907         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2908
2909         /*
2910          * Don't need to allocate software ring and reset for the fdir
2911          * rx queue, just set the queue has been configured.
2912          */
2913         rxq->q_set = TRUE;
2914         pf->fdir.rxq = rxq;
2915
2916         return I40E_SUCCESS;
2917 }
2918
2919 void
2920 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2921         struct rte_eth_rxq_info *qinfo)
2922 {
2923         struct i40e_rx_queue *rxq;
2924
2925         rxq = dev->data->rx_queues[queue_id];
2926
2927         qinfo->mp = rxq->mp;
2928         qinfo->scattered_rx = dev->data->scattered_rx;
2929         qinfo->nb_desc = rxq->nb_rx_desc;
2930
2931         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2932         qinfo->conf.rx_drop_en = rxq->drop_en;
2933         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2934         qinfo->conf.offloads = rxq->offloads;
2935 }
2936
2937 void
2938 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2939         struct rte_eth_txq_info *qinfo)
2940 {
2941         struct i40e_tx_queue *txq;
2942
2943         txq = dev->data->tx_queues[queue_id];
2944
2945         qinfo->nb_desc = txq->nb_tx_desc;
2946
2947         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2948         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2949         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2950
2951         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2952         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2953         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2954         qinfo->conf.offloads = txq->offloads;
2955 }
2956
2957 void __attribute__((cold))
2958 i40e_set_rx_function(struct rte_eth_dev *dev)
2959 {
2960         struct i40e_adapter *ad =
2961                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2962         uint16_t rx_using_sse, i;
2963         /* In order to allow Vector Rx there are a few configuration
2964          * conditions to be met and Rx Bulk Allocation should be allowed.
2965          */
2966         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2967                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2968                     !ad->rx_bulk_alloc_allowed) {
2969                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2970                                      " Vector Rx preconditions",
2971                                      dev->data->port_id);
2972
2973                         ad->rx_vec_allowed = false;
2974                 }
2975                 if (ad->rx_vec_allowed) {
2976                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2977                                 struct i40e_rx_queue *rxq =
2978                                         dev->data->rx_queues[i];
2979
2980                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2981                                         ad->rx_vec_allowed = false;
2982                                         break;
2983                                 }
2984                         }
2985                 }
2986         }
2987
2988         if (dev->data->scattered_rx) {
2989                 /* Set the non-LRO scattered callback: there are Vector and
2990                  * single allocation versions.
2991                  */
2992                 if (ad->rx_vec_allowed) {
2993                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2994                                             "callback (port=%d).",
2995                                      dev->data->port_id);
2996
2997                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2998 #ifdef RTE_ARCH_X86
2999                         /*
3000                          * since AVX frequency can be different to base
3001                          * frequency, limit use of AVX2 version to later
3002                          * plaforms, not all those that could theoretically
3003                          * run it.
3004                          */
3005                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3006                                 dev->rx_pkt_burst =
3007                                         i40e_recv_scattered_pkts_vec_avx2;
3008 #endif
3009                 } else {
3010                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
3011                                            "allocation callback (port=%d).",
3012                                      dev->data->port_id);
3013                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
3014                 }
3015         /* If parameters allow we are going to choose between the following
3016          * callbacks:
3017          *    - Vector
3018          *    - Bulk Allocation
3019          *    - Single buffer allocation (the simplest one)
3020          */
3021         } else if (ad->rx_vec_allowed) {
3022                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
3023                                     "burst size no less than %d (port=%d).",
3024                              RTE_I40E_DESCS_PER_LOOP,
3025                              dev->data->port_id);
3026
3027                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
3028 #ifdef RTE_ARCH_X86
3029                 /*
3030                  * since AVX frequency can be different to base
3031                  * frequency, limit use of AVX2 version to later
3032                  * plaforms, not all those that could theoretically
3033                  * run it.
3034                  */
3035                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3036                         dev->rx_pkt_burst = i40e_recv_pkts_vec_avx2;
3037 #endif
3038         } else if (ad->rx_bulk_alloc_allowed) {
3039                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
3040                                     "satisfied. Rx Burst Bulk Alloc function "
3041                                     "will be used on port=%d.",
3042                              dev->data->port_id);
3043
3044                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
3045         } else {
3046                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
3047                                     "satisfied, or Scattered Rx is requested "
3048                                     "(port=%d).",
3049                              dev->data->port_id);
3050
3051                 dev->rx_pkt_burst = i40e_recv_pkts;
3052         }
3053
3054         /* Propagate information about RX function choice through all queues. */
3055         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3056                 rx_using_sse =
3057                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
3058                          dev->rx_pkt_burst == i40e_recv_pkts_vec ||
3059                          dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec_avx2 ||
3060                          dev->rx_pkt_burst == i40e_recv_pkts_vec_avx2);
3061
3062                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
3063                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
3064
3065                         if (rxq)
3066                                 rxq->rx_using_sse = rx_using_sse;
3067                 }
3068         }
3069 }
3070
3071 void __attribute__((cold))
3072 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
3073 {
3074         struct i40e_adapter *ad =
3075                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3076
3077         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
3078         ad->tx_simple_allowed = (txq->offloads == 0 &&
3079                         txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST);
3080         ad->tx_vec_allowed = (ad->tx_simple_allowed &&
3081                         txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ);
3082
3083         if (ad->tx_vec_allowed)
3084                 PMD_INIT_LOG(DEBUG, "Vector Tx can be enabled on Tx queue %u.",
3085                                 txq->queue_id);
3086         else if (ad->tx_simple_allowed)
3087                 PMD_INIT_LOG(DEBUG, "Simple Tx can be enabled on Tx queue %u.",
3088                                 txq->queue_id);
3089         else
3090                 PMD_INIT_LOG(DEBUG,
3091                                 "Neither simple nor vector Tx enabled on Tx queue %u\n",
3092                                 txq->queue_id);
3093 }
3094
3095 void __attribute__((cold))
3096 i40e_set_tx_function(struct rte_eth_dev *dev)
3097 {
3098         struct i40e_adapter *ad =
3099                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3100         int i;
3101
3102         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
3103                 if (ad->tx_vec_allowed) {
3104                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
3105                                 struct i40e_tx_queue *txq =
3106                                         dev->data->tx_queues[i];
3107
3108                                 if (txq && i40e_txq_vec_setup(txq)) {
3109                                         ad->tx_vec_allowed = false;
3110                                         break;
3111                                 }
3112                         }
3113                 }
3114         }
3115
3116         if (ad->tx_simple_allowed) {
3117                 if (ad->tx_vec_allowed) {
3118                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
3119                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
3120 #ifdef RTE_ARCH_X86
3121                         /*
3122                          * since AVX frequency can be different to base
3123                          * frequency, limit use of AVX2 version to later
3124                          * plaforms, not all those that could theoretically
3125                          * run it.
3126                          */
3127                         if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F))
3128                                 dev->tx_pkt_burst = i40e_xmit_pkts_vec_avx2;
3129 #endif
3130                 } else {
3131                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
3132                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
3133                 }
3134                 dev->tx_pkt_prepare = NULL;
3135         } else {
3136                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
3137                 dev->tx_pkt_burst = i40e_xmit_pkts;
3138                 dev->tx_pkt_prepare = i40e_prep_pkts;
3139         }
3140 }
3141
3142 void __attribute__((cold))
3143 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
3144 {
3145         struct i40e_adapter *ad =
3146                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3147         int i;
3148
3149         for (i = 0; i < I40E_MAX_PKT_TYPE; i++)
3150                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
3151 }
3152
3153 void __attribute__((cold))
3154 i40e_set_default_pctype_table(struct rte_eth_dev *dev)
3155 {
3156         struct i40e_adapter *ad =
3157                         I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3158         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3159         int i;
3160
3161         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++)
3162                 ad->pctypes_tbl[i] = 0ULL;
3163         ad->flow_types_mask = 0ULL;
3164         ad->pctypes_mask = 0ULL;
3165
3166         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV4] =
3167                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV4);
3168         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] =
3169                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_UDP);
3170         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] =
3171                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP);
3172         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_SCTP] =
3173                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_SCTP);
3174         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_OTHER] =
3175                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_OTHER);
3176         ad->pctypes_tbl[RTE_ETH_FLOW_FRAG_IPV6] =
3177                                 (1ULL << I40E_FILTER_PCTYPE_FRAG_IPV6);
3178         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] =
3179                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_UDP);
3180         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] =
3181                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP);
3182         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_SCTP] =
3183                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_SCTP);
3184         ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_OTHER] =
3185                                 (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_OTHER);
3186         ad->pctypes_tbl[RTE_ETH_FLOW_L2_PAYLOAD] =
3187                                 (1ULL << I40E_FILTER_PCTYPE_L2_PAYLOAD);
3188
3189         if (hw->mac.type == I40E_MAC_X722) {
3190                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3191                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP);
3192                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_UDP] |=
3193                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP);
3194                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV4_TCP] |=
3195                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK);
3196                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3197                         (1ULL << I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP);
3198                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_UDP] |=
3199                         (1ULL << I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP);
3200                 ad->pctypes_tbl[RTE_ETH_FLOW_NONFRAG_IPV6_TCP] |=
3201                         (1ULL << I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK);
3202         }
3203
3204         for (i = 0; i < I40E_FLOW_TYPE_MAX; i++) {
3205                 if (ad->pctypes_tbl[i])
3206                         ad->flow_types_mask |= (1ULL << i);
3207                 ad->pctypes_mask |= ad->pctypes_tbl[i];
3208         }
3209 }
3210
3211 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
3212 int __attribute__((weak))
3213 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
3214 {
3215         return -1;
3216 }
3217
3218 uint16_t __attribute__((weak))
3219 i40e_recv_pkts_vec(
3220         void __rte_unused *rx_queue,
3221         struct rte_mbuf __rte_unused **rx_pkts,
3222         uint16_t __rte_unused nb_pkts)
3223 {
3224         return 0;
3225 }
3226
3227 uint16_t __attribute__((weak))
3228 i40e_recv_scattered_pkts_vec(
3229         void __rte_unused *rx_queue,
3230         struct rte_mbuf __rte_unused **rx_pkts,
3231         uint16_t __rte_unused nb_pkts)
3232 {
3233         return 0;
3234 }
3235
3236 uint16_t __attribute__((weak))
3237 i40e_recv_pkts_vec_avx2(void __rte_unused *rx_queue,
3238                         struct rte_mbuf __rte_unused **rx_pkts,
3239                         uint16_t __rte_unused nb_pkts)
3240 {
3241         return 0;
3242 }
3243
3244 uint16_t __attribute__((weak))
3245 i40e_recv_scattered_pkts_vec_avx2(void __rte_unused *rx_queue,
3246                         struct rte_mbuf __rte_unused **rx_pkts,
3247                         uint16_t __rte_unused nb_pkts)
3248 {
3249         return 0;
3250 }
3251
3252 int __attribute__((weak))
3253 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
3254 {
3255         return -1;
3256 }
3257
3258 int __attribute__((weak))
3259 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
3260 {
3261         return -1;
3262 }
3263
3264 void __attribute__((weak))
3265 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
3266 {
3267         return;
3268 }
3269
3270 uint16_t __attribute__((weak))
3271 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
3272                           struct rte_mbuf __rte_unused **tx_pkts,
3273                           uint16_t __rte_unused nb_pkts)
3274 {
3275         return 0;
3276 }
3277
3278 uint16_t __attribute__((weak))
3279 i40e_xmit_pkts_vec_avx2(void __rte_unused * tx_queue,
3280                           struct rte_mbuf __rte_unused **tx_pkts,
3281                           uint16_t __rte_unused nb_pkts)
3282 {
3283         return 0;
3284 }