drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_TX_MAX_BURST  32
  68
  69 #define I40E_DMA_MEM_ALIGN 4096
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  82         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  83
  84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  85         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  86
  87 static const struct rte_memzone *
  88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  89                            const char *ring_name,
  90                            uint16_t queue_id,
  91                            uint32_t ring_size,
  92                            int socket_id);
  93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  94                                       struct rte_mbuf **tx_pkts,
  95                                       uint16_t nb_pkts);
  96
  97 static inline void
  98 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  99 {
 100         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 101                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_VLAN_PKT;
 103                 mb->vlan_tci =
 104                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 107         } else {
 108                 mb->vlan_tci = 0;
 109         }
 110 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 111         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 112                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 113                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 114                 mb->vlan_tci_outer = mb->vlan_tci;
 115                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 116                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 117                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 118                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 119         } else {
 120                 mb->vlan_tci_outer = 0;
 121         }
 122 #endif
 123         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 124                    mb->vlan_tci, mb->vlan_tci_outer);
 125 }
 126
 127 /* Translate the rx descriptor status to pkt flags */
 128 static inline uint64_t
 129 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 130 {
 131         uint64_t flags;
 132
 133         /* Check if RSS_HASH */
 134         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 135                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 136                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 137
 138         /* Check if FDIR Match */
 139         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 140                                                         PKT_RX_FDIR : 0);
 141
 142         return flags;
 143 }
 144
 145 static inline uint64_t
 146 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 147 {
 148         uint64_t flags = 0;
 149         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 150
 151 #define I40E_RX_ERR_BITS 0x3f
 152         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 153                 return flags;
 154         /* If RXE bit set, all other status bits are meaningless */
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 156                 flags |= PKT_RX_MAC_ERR;
 157                 return flags;
 158         }
 159
 160         /* If RECIPE bit set, all other status indications should be ignored */
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 162                 flags |= PKT_RX_RECIP_ERR;
 163                 return flags;
 164         }
 165         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 166                 flags |= PKT_RX_HBUF_OVERFLOW;
 167         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 168                 flags |= PKT_RX_IP_CKSUM_BAD;
 169         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 170                 flags |= PKT_RX_L4_CKSUM_BAD;
 171         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 172                 flags |= PKT_RX_EIP_CKSUM_BAD;
 173         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 174                 flags |= PKT_RX_OVERSIZE;
 175
 176         return flags;
 177 }
 178
 179 /* Translate pkt types to pkt flags */
 180 static inline uint64_t
 181 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 182 {
 183         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 184                                         I40E_RXD_QW1_PTYPE_SHIFT);
 185         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 186                 0, /* PTYPE 0 */
 187                 0, /* PTYPE 1 */
 188                 PKT_RX_IEEE1588_PTP, /* PTYPE 2 */
 189                 0, /* PTYPE 3 */
 190                 0, /* PTYPE 4 */
 191                 0, /* PTYPE 5 */
 192                 0, /* PTYPE 6 */
 193                 0, /* PTYPE 7 */
 194                 0, /* PTYPE 8 */
 195                 0, /* PTYPE 9 */
 196                 0, /* PTYPE 10 */
 197                 0, /* PTYPE 11 */
 198                 0, /* PTYPE 12 */
 199                 0, /* PTYPE 13 */
 200                 0, /* PTYPE 14 */
 201                 0, /* PTYPE 15 */
 202                 0, /* PTYPE 16 */
 203                 0, /* PTYPE 17 */
 204                 0, /* PTYPE 18 */
 205                 0, /* PTYPE 19 */
 206                 0, /* PTYPE 20 */
 207                 0, /* PTYPE 21 */
 208                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 209                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 210                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 211                 0, /* PTYPE 25 */
 212                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 213                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 214                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 215                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 216                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 217                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 218                 0, /* PTYPE 32 */
 219                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 220                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 221                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 222                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 223                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 224                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 225                 0, /* PTYPE 39 */
 226                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 227                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 228                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 229                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 230                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 231                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 232                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 233                 0, /* PTYPE 47 */
 234                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 235                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 236                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 237                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 238                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 239                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 240                 0, /* PTYPE 54 */
 241                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 242                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 243                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 244                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 245                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 246                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 247                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 248                 0, /* PTYPE 62 */
 249                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 250                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 251                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 252                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 253                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 254                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 255                 0, /* PTYPE 69 */
 256                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 257                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 258                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 259                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 260                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 261                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 262                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 263                 0, /* PTYPE 77 */
 264                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 265                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 266                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 267                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 268                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 269                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 270                 0, /* PTYPE 84 */
 271                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 272                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 273                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 274                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 275                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 276                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 277                 0, /* PTYPE 91 */
 278                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 279                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 280                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 281                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 282                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 283                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 284                 0, /* PTYPE 98 */
 285                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 286                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 287                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 288                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 289                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 290                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 291                 0, /* PTYPE 105 */
 292                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 293                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 294                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 295                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 296                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 297                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 298                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 299                 0, /* PTYPE 113 */
 300                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 301                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 302                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 303                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 304                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 305                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 306                 0, /* PTYPE 120 */
 307                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 308                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 309                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 310                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 311                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 312                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 313                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 314                 0, /* PTYPE 128 */
 315                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 316                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 317                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 318                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 319                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 320                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 321                 0, /* PTYPE 135 */
 322                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 323                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 324                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 325                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 326                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 327                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 328                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 329                 0, /* PTYPE 143 */
 330                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 331                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 332                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 333                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 334                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 335                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 336                 0, /* PTYPE 150 */
 337                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 338                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 339                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 340                 0, /* PTYPE 154 */
 341                 0, /* PTYPE 155 */
 342                 0, /* PTYPE 156 */
 343                 0, /* PTYPE 157 */
 344                 0, /* PTYPE 158 */
 345                 0, /* PTYPE 159 */
 346                 0, /* PTYPE 160 */
 347                 0, /* PTYPE 161 */
 348                 0, /* PTYPE 162 */
 349                 0, /* PTYPE 163 */
 350                 0, /* PTYPE 164 */
 351                 0, /* PTYPE 165 */
 352                 0, /* PTYPE 166 */
 353                 0, /* PTYPE 167 */
 354                 0, /* PTYPE 168 */
 355                 0, /* PTYPE 169 */
 356                 0, /* PTYPE 170 */
 357                 0, /* PTYPE 171 */
 358                 0, /* PTYPE 172 */
 359                 0, /* PTYPE 173 */
 360                 0, /* PTYPE 174 */
 361                 0, /* PTYPE 175 */
 362                 0, /* PTYPE 176 */
 363                 0, /* PTYPE 177 */
 364                 0, /* PTYPE 178 */
 365                 0, /* PTYPE 179 */
 366                 0, /* PTYPE 180 */
 367                 0, /* PTYPE 181 */
 368                 0, /* PTYPE 182 */
 369                 0, /* PTYPE 183 */
 370                 0, /* PTYPE 184 */
 371                 0, /* PTYPE 185 */
 372                 0, /* PTYPE 186 */
 373                 0, /* PTYPE 187 */
 374                 0, /* PTYPE 188 */
 375                 0, /* PTYPE 189 */
 376                 0, /* PTYPE 190 */
 377                 0, /* PTYPE 191 */
 378                 0, /* PTYPE 192 */
 379                 0, /* PTYPE 193 */
 380                 0, /* PTYPE 194 */
 381                 0, /* PTYPE 195 */
 382                 0, /* PTYPE 196 */
 383                 0, /* PTYPE 197 */
 384                 0, /* PTYPE 198 */
 385                 0, /* PTYPE 199 */
 386                 0, /* PTYPE 200 */
 387                 0, /* PTYPE 201 */
 388                 0, /* PTYPE 202 */
 389                 0, /* PTYPE 203 */
 390                 0, /* PTYPE 204 */
 391                 0, /* PTYPE 205 */
 392                 0, /* PTYPE 206 */
 393                 0, /* PTYPE 207 */
 394                 0, /* PTYPE 208 */
 395                 0, /* PTYPE 209 */
 396                 0, /* PTYPE 210 */
 397                 0, /* PTYPE 211 */
 398                 0, /* PTYPE 212 */
 399                 0, /* PTYPE 213 */
 400                 0, /* PTYPE 214 */
 401                 0, /* PTYPE 215 */
 402                 0, /* PTYPE 216 */
 403                 0, /* PTYPE 217 */
 404                 0, /* PTYPE 218 */
 405                 0, /* PTYPE 219 */
 406                 0, /* PTYPE 220 */
 407                 0, /* PTYPE 221 */
 408                 0, /* PTYPE 222 */
 409                 0, /* PTYPE 223 */
 410                 0, /* PTYPE 224 */
 411                 0, /* PTYPE 225 */
 412                 0, /* PTYPE 226 */
 413                 0, /* PTYPE 227 */
 414                 0, /* PTYPE 228 */
 415                 0, /* PTYPE 229 */
 416                 0, /* PTYPE 230 */
 417                 0, /* PTYPE 231 */
 418                 0, /* PTYPE 232 */
 419                 0, /* PTYPE 233 */
 420                 0, /* PTYPE 234 */
 421                 0, /* PTYPE 235 */
 422                 0, /* PTYPE 236 */
 423                 0, /* PTYPE 237 */
 424                 0, /* PTYPE 238 */
 425                 0, /* PTYPE 239 */
 426                 0, /* PTYPE 240 */
 427                 0, /* PTYPE 241 */
 428                 0, /* PTYPE 242 */
 429                 0, /* PTYPE 243 */
 430                 0, /* PTYPE 244 */
 431                 0, /* PTYPE 245 */
 432                 0, /* PTYPE 246 */
 433                 0, /* PTYPE 247 */
 434                 0, /* PTYPE 248 */
 435                 0, /* PTYPE 249 */
 436                 0, /* PTYPE 250 */
 437                 0, /* PTYPE 251 */
 438                 0, /* PTYPE 252 */
 439                 0, /* PTYPE 253 */
 440                 0, /* PTYPE 254 */
 441                 0, /* PTYPE 255 */
 442         };
 443
 444         return ip_ptype_map[ptype];
 445 }
 446
 447 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 448 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 449 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 450 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 451 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 452
 453 static inline uint64_t
 454 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 455 {
 456         uint64_t flags = 0;
 457 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 458         uint16_t flexbh, flexbl;
 459
 460         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 461                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 462                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 463         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 464                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 465                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 466
 467
 468         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 469                 mb->hash.fdir.hi =
 470                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 471                 flags |= PKT_RX_FDIR_ID;
 472         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 473                 mb->hash.fdir.hi =
 474                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 475                 flags |= PKT_RX_FDIR_FLX;
 476         }
 477         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 478                 mb->hash.fdir.lo =
 479                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 480                 flags |= PKT_RX_FDIR_FLX;
 481         }
 482 #else
 483         mb->hash.fdir.hi =
 484                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 485         flags |= PKT_RX_FDIR_ID;
 486 #endif
 487         return flags;
 488 }
 489 static inline void
 490 i40e_txd_enable_checksum(uint64_t ol_flags,
 491                         uint32_t *td_cmd,
 492                         uint32_t *td_offset,
 493                         union i40e_tx_offload tx_offload,
 494                         uint32_t *cd_tunneling)
 495 {
 496         /* UDP tunneling packet TX checksum offload */
 497         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 498
 499                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 500                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 501
 502                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 503                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 504                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 505                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 506                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 507                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 508
 509                 /* Now set the ctx descriptor fields */
 510                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 511                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 512                                 (tx_offload.l2_len >> 1) <<
 513                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 514
 515         } else
 516                 *td_offset |= (tx_offload.l2_len >> 1)
 517                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 518
 519         /* Enable L3 checksum offloads */
 520         if (ol_flags & PKT_TX_IP_CKSUM) {
 521                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 522                 *td_offset |= (tx_offload.l3_len >> 2)
 523                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 524         } else if (ol_flags & PKT_TX_IPV4) {
 525                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 526                 *td_offset |= (tx_offload.l3_len >> 2)
 527                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 528         } else if (ol_flags & PKT_TX_IPV6) {
 529                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 530                 *td_offset |= (tx_offload.l3_len >> 2)
 531                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 532         }
 533
 534         if (ol_flags & PKT_TX_TCP_SEG) {
 535                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 536                 *td_offset |= (tx_offload.l4_len >> 2)
 537                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 538                 return;
 539         }
 540
 541         /* Enable L4 checksum offloads */
 542         switch (ol_flags & PKT_TX_L4_MASK) {
 543         case PKT_TX_TCP_CKSUM:
 544                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 545                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 546                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 547                 break;
 548         case PKT_TX_SCTP_CKSUM:
 549                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 550                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 551                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 552                 break;
 553         case PKT_TX_UDP_CKSUM:
 554                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 555                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 556                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 557                 break;
 558         default:
 559                 break;
 560         }
 561 }
 562
 563 static inline struct rte_mbuf *
 564 rte_rxmbuf_alloc(struct rte_mempool *mp)
 565 {
 566         struct rte_mbuf *m;
 567
 568         m = __rte_mbuf_raw_alloc(mp);
 569         __rte_mbuf_sanity_check_raw(m, 0);
 570
 571         return m;
 572 }
 573
 574 /* Construct the tx flags */
 575 static inline uint64_t
 576 i40e_build_ctob(uint32_t td_cmd,
 577                 uint32_t td_offset,
 578                 unsigned int size,
 579                 uint32_t td_tag)
 580 {
 581         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 582                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 583                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 584                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 585                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 586 }
 587
 588 static inline int
 589 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 590 {
 591         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 592         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 593         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 594         uint16_t nb_tx_desc = txq->nb_tx_desc;
 595         uint16_t desc_to_clean_to;
 596         uint16_t nb_tx_to_clean;
 597
 598         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 599         if (desc_to_clean_to >= nb_tx_desc)
 600                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 601
 602         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 603         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 604                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 605                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 606                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 607                         "(port=%d queue=%d)", desc_to_clean_to,
 608                                 txq->port_id, txq->queue_id);
 609                 return -1;
 610         }
 611
 612         if (last_desc_cleaned > desc_to_clean_to)
 613                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 614                                                         desc_to_clean_to);
 615         else
 616                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 617                                         last_desc_cleaned);
 618
 619         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 620
 621         txq->last_desc_cleaned = desc_to_clean_to;
 622         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 623
 624         return 0;
 625 }
 626
 627 static inline int
 628 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 629 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 630 #else
 631 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 632 #endif
 633 {
 634         int ret = 0;
 635
 636 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 637         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 638                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 639                              "rxq->rx_free_thresh=%d, "
 640                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 641                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 642                 ret = -EINVAL;
 643         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 644                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 645                              "rxq->rx_free_thresh=%d, "
 646                              "rxq->nb_rx_desc=%d",
 647                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 648                 ret = -EINVAL;
 649         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 650                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 651                              "rxq->nb_rx_desc=%d, "
 652                              "rxq->rx_free_thresh=%d",
 653                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 654                 ret = -EINVAL;
 655         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 656                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 657                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 658                              "rxq->nb_rx_desc=%d, "
 659                              "I40E_MAX_RING_DESC=%d, "
 660                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 661                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 662                              RTE_PMD_I40E_RX_MAX_BURST);
 663                 ret = -EINVAL;
 664         }
 665 #else
 666         ret = -EINVAL;
 667 #endif
 668
 669         return ret;
 670 }
 671
 672 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 673 #define I40E_LOOK_AHEAD 8
 674 #if (I40E_LOOK_AHEAD != 8)
 675 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 676 #endif
 677 static inline int
 678 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 679 {
 680         volatile union i40e_rx_desc *rxdp;
 681         struct i40e_rx_entry *rxep;
 682         struct rte_mbuf *mb;
 683         uint16_t pkt_len;
 684         uint64_t qword1;
 685         uint32_t rx_status;
 686         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 687         int32_t i, j, nb_rx = 0;
 688         uint64_t pkt_flags;
 689
 690         rxdp = &rxq->rx_ring[rxq->rx_tail];
 691         rxep = &rxq->sw_ring[rxq->rx_tail];
 692
 693         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 694         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 695                                 I40E_RXD_QW1_STATUS_SHIFT;
 696
 697         /* Make sure there is at least 1 packet to receive */
 698         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 699                 return 0;
 700
 701         /**
 702          * Scan LOOK_AHEAD descriptors at a time to determine which
 703          * descriptors reference packets that are ready to be received.
 704          */
 705         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 706                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 707                 /* Read desc statuses backwards to avoid race condition */
 708                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 709                         qword1 = rte_le_to_cpu_64(\
 710                                 rxdp[j].wb.qword1.status_error_len);
 711                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 712                                         I40E_RXD_QW1_STATUS_SHIFT;
 713                 }
 714
 715                 /* Compute how many status bits were set */
 716                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 717                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 718
 719                 nb_rx += nb_dd;
 720
 721                 /* Translate descriptor info to mbuf parameters */
 722                 for (j = 0; j < nb_dd; j++) {
 723                         mb = rxep[j].mbuf;
 724                         qword1 = rte_le_to_cpu_64(\
 725                                 rxdp[j].wb.qword1.status_error_len);
 726                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 727                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 728                         mb->data_len = pkt_len;
 729                         mb->pkt_len = pkt_len;
 730                         mb->ol_flags = 0;
 731                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 732                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 733                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 734                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 735
 736                         mb->packet_type = (uint16_t)((qword1 &
 737                                         I40E_RXD_QW1_PTYPE_MASK) >>
 738                                         I40E_RXD_QW1_PTYPE_SHIFT);
 739                         if (pkt_flags & PKT_RX_RSS_HASH)
 740                                 mb->hash.rss = rte_le_to_cpu_32(\
 741                                         rxdp[j].wb.qword0.hi_dword.rss);
 742                         if (pkt_flags & PKT_RX_FDIR)
 743                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 744
 745 #ifdef RTE_LIBRTE_IEEE1588
 746                         uint16_t tsyn = (qword1
 747                                          & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 748                                            | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 749                                          >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 750
 751                         if (tsyn & 0x04)
 752                                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 753
 754                         mb->timesync = tsyn & 0x03;
 755 #endif
 756                         mb->ol_flags |= pkt_flags;
 757
 758                 }
 759
 760                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 761                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 762
 763                 if (nb_dd != I40E_LOOK_AHEAD)
 764                         break;
 765         }
 766
 767         /* Clear software ring entries */
 768         for (i = 0; i < nb_rx; i++)
 769                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 770
 771         return nb_rx;
 772 }
 773
 774 static inline uint16_t
 775 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 776                         struct rte_mbuf **rx_pkts,
 777                         uint16_t nb_pkts)
 778 {
 779         uint16_t i;
 780         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 781
 782         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 783
 784         for (i = 0; i < nb_pkts; i++)
 785                 rx_pkts[i] = stage[i];
 786
 787         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 788         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 789
 790         return nb_pkts;
 791 }
 792
 793 static inline int
 794 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 795 {
 796         volatile union i40e_rx_desc *rxdp;
 797         struct i40e_rx_entry *rxep;
 798         struct rte_mbuf *mb;
 799         uint16_t alloc_idx, i;
 800         uint64_t dma_addr;
 801         int diag;
 802
 803         /* Allocate buffers in bulk */
 804         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 805                                 (rxq->rx_free_thresh - 1));
 806         rxep = &(rxq->sw_ring[alloc_idx]);
 807         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 808                                         rxq->rx_free_thresh);
 809         if (unlikely(diag != 0)) {
 810                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 811                 return -ENOMEM;
 812         }
 813
 814         rxdp = &rxq->rx_ring[alloc_idx];
 815         for (i = 0; i < rxq->rx_free_thresh; i++) {
 816                 if (likely(i < (rxq->rx_free_thresh - 1)))
 817                         /* Prefetch next mbuf */
 818                         rte_prefetch0(rxep[i + 1].mbuf);
 819
 820                 mb = rxep[i].mbuf;
 821                 rte_mbuf_refcnt_set(mb, 1);
 822                 mb->next = NULL;
 823                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 824                 mb->nb_segs = 1;
 825                 mb->port = rxq->port_id;
 826                 dma_addr = rte_cpu_to_le_64(\
 827                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
 828                 rxdp[i].read.hdr_addr = dma_addr;
 829                 rxdp[i].read.pkt_addr = dma_addr;
 830         }
 831
 832         /* Update rx tail regsiter */
 833         rte_wmb();
 834         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 835
 836         rxq->rx_free_trigger =
 837                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 838         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 839                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 840
 841         return 0;
 842 }
 843
 844 static inline uint16_t
 845 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 846 {
 847         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 848         uint16_t nb_rx = 0;
 849
 850         if (!nb_pkts)
 851                 return 0;
 852
 853         if (rxq->rx_nb_avail)
 854                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 855
 856         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 857         rxq->rx_next_avail = 0;
 858         rxq->rx_nb_avail = nb_rx;
 859         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 860
 861         if (rxq->rx_tail > rxq->rx_free_trigger) {
 862                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 863                         uint16_t i, j;
 864
 865                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 866                                    "port_id=%u, queue_id=%u",
 867                                    rxq->port_id, rxq->queue_id);
 868                         rxq->rx_nb_avail = 0;
 869                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 870                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 871                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 872
 873                         return 0;
 874                 }
 875         }
 876
 877         if (rxq->rx_tail >= rxq->nb_rx_desc)
 878                 rxq->rx_tail = 0;
 879
 880         if (rxq->rx_nb_avail)
 881                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 882
 883         return 0;
 884 }
 885
 886 static uint16_t
 887 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 888                           struct rte_mbuf **rx_pkts,
 889                           uint16_t nb_pkts)
 890 {
 891         uint16_t nb_rx = 0, n, count;
 892
 893         if (unlikely(nb_pkts == 0))
 894                 return 0;
 895
 896         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 897                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 898
 899         while (nb_pkts) {
 900                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 901                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 902                 nb_rx = (uint16_t)(nb_rx + count);
 903                 nb_pkts = (uint16_t)(nb_pkts - count);
 904                 if (count < n)
 905                         break;
 906         }
 907
 908         return nb_rx;
 909 }
 910 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 911
 912 uint16_t
 913 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 914 {
 915         struct i40e_rx_queue *rxq;
 916         volatile union i40e_rx_desc *rx_ring;
 917         volatile union i40e_rx_desc *rxdp;
 918         union i40e_rx_desc rxd;
 919         struct i40e_rx_entry *sw_ring;
 920         struct i40e_rx_entry *rxe;
 921         struct rte_mbuf *rxm;
 922         struct rte_mbuf *nmb;
 923         uint16_t nb_rx;
 924         uint32_t rx_status;
 925         uint64_t qword1;
 926         uint16_t rx_packet_len;
 927         uint16_t rx_id, nb_hold;
 928         uint64_t dma_addr;
 929         uint64_t pkt_flags;
 930
 931         nb_rx = 0;
 932         nb_hold = 0;
 933         rxq = rx_queue;
 934         rx_id = rxq->rx_tail;
 935         rx_ring = rxq->rx_ring;
 936         sw_ring = rxq->sw_ring;
 937
 938         while (nb_rx < nb_pkts) {
 939                 rxdp = &rx_ring[rx_id];
 940                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 941                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 942                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 943
 944                 /* Check the DD bit first */
 945                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 946                         break;
 947
 948                 nmb = rte_rxmbuf_alloc(rxq->mp);
 949                 if (unlikely(!nmb))
 950                         break;
 951                 rxd = *rxdp;
 952
 953                 nb_hold++;
 954                 rxe = &sw_ring[rx_id];
 955                 rx_id++;
 956                 if (unlikely(rx_id == rxq->nb_rx_desc))
 957                         rx_id = 0;
 958
 959                 /* Prefetch next mbuf */
 960                 rte_prefetch0(sw_ring[rx_id].mbuf);
 961
 962                 /**
 963                  * When next RX descriptor is on a cache line boundary,
 964                  * prefetch the next 4 RX descriptors and next 8 pointers
 965                  * to mbufs.
 966                  */
 967                 if ((rx_id & 0x3) == 0) {
 968                         rte_prefetch0(&rx_ring[rx_id]);
 969                         rte_prefetch0(&sw_ring[rx_id]);
 970                 }
 971                 rxm = rxe->mbuf;
 972                 rxe->mbuf = nmb;
 973                 dma_addr =
 974                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 975                 rxdp->read.hdr_addr = dma_addr;
 976                 rxdp->read.pkt_addr = dma_addr;
 977
 978                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 979                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 980
 981                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 982                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 983                 rxm->nb_segs = 1;
 984                 rxm->next = NULL;
 985                 rxm->pkt_len = rx_packet_len;
 986                 rxm->data_len = rx_packet_len;
 987                 rxm->port = rxq->port_id;
 988                 rxm->ol_flags = 0;
 989                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 990                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 991                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 992                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 993                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
 994                                 I40E_RXD_QW1_PTYPE_SHIFT);
 995                 if (pkt_flags & PKT_RX_RSS_HASH)
 996                         rxm->hash.rss =
 997                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 998                 if (pkt_flags & PKT_RX_FDIR)
 999                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1000
1001 #ifdef RTE_LIBRTE_IEEE1588
1002                 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
1003                                         | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1004                                         >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1005
1006                 if (tsyn & 0x04)
1007                         pkt_flags |= PKT_RX_IEEE1588_TMST;
1008
1009                 rxm->timesync = tsyn & 0x03;
1010 #endif
1011                 rxm->ol_flags |= pkt_flags;
1012
1013                 rx_pkts[nb_rx++] = rxm;
1014         }
1015         rxq->rx_tail = rx_id;
1016
1017         /**
1018          * If the number of free RX descriptors is greater than the RX free
1019          * threshold of the queue, advance the receive tail register of queue.
1020          * Update that register with the value of the last processed RX
1021          * descriptor minus 1.
1022          */
1023         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1024         if (nb_hold > rxq->rx_free_thresh) {
1025                 rx_id = (uint16_t) ((rx_id == 0) ?
1026                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1027                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1028                 nb_hold = 0;
1029         }
1030         rxq->nb_rx_hold = nb_hold;
1031
1032         return nb_rx;
1033 }
1034
1035 uint16_t
1036 i40e_recv_scattered_pkts(void *rx_queue,
1037                          struct rte_mbuf **rx_pkts,
1038                          uint16_t nb_pkts)
1039 {
1040         struct i40e_rx_queue *rxq = rx_queue;
1041         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1042         volatile union i40e_rx_desc *rxdp;
1043         union i40e_rx_desc rxd;
1044         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1045         struct i40e_rx_entry *rxe;
1046         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1047         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1048         struct rte_mbuf *nmb, *rxm;
1049         uint16_t rx_id = rxq->rx_tail;
1050         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1051         uint32_t rx_status;
1052         uint64_t qword1;
1053         uint64_t dma_addr;
1054         uint64_t pkt_flags;
1055
1056         while (nb_rx < nb_pkts) {
1057                 rxdp = &rx_ring[rx_id];
1058                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1059                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1060                                         I40E_RXD_QW1_STATUS_SHIFT;
1061
1062                 /* Check the DD bit */
1063                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1064                         break;
1065
1066                 nmb = rte_rxmbuf_alloc(rxq->mp);
1067                 if (unlikely(!nmb))
1068                         break;
1069                 rxd = *rxdp;
1070                 nb_hold++;
1071                 rxe = &sw_ring[rx_id];
1072                 rx_id++;
1073                 if (rx_id == rxq->nb_rx_desc)
1074                         rx_id = 0;
1075
1076                 /* Prefetch next mbuf */
1077                 rte_prefetch0(sw_ring[rx_id].mbuf);
1078
1079                 /**
1080                  * When next RX descriptor is on a cache line boundary,
1081                  * prefetch the next 4 RX descriptors and next 8 pointers
1082                  * to mbufs.
1083                  */
1084                 if ((rx_id & 0x3) == 0) {
1085                         rte_prefetch0(&rx_ring[rx_id]);
1086                         rte_prefetch0(&sw_ring[rx_id]);
1087                 }
1088
1089                 rxm = rxe->mbuf;
1090                 rxe->mbuf = nmb;
1091                 dma_addr =
1092                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1093
1094                 /* Set data buffer address and data length of the mbuf */
1095                 rxdp->read.hdr_addr = dma_addr;
1096                 rxdp->read.pkt_addr = dma_addr;
1097                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1098                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1099                 rxm->data_len = rx_packet_len;
1100                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1101
1102                 /**
1103                  * If this is the first buffer of the received packet, set the
1104                  * pointer to the first mbuf of the packet and initialize its
1105                  * context. Otherwise, update the total length and the number
1106                  * of segments of the current scattered packet, and update the
1107                  * pointer to the last mbuf of the current packet.
1108                  */
1109                 if (!first_seg) {
1110                         first_seg = rxm;
1111                         first_seg->nb_segs = 1;
1112                         first_seg->pkt_len = rx_packet_len;
1113                 } else {
1114                         first_seg->pkt_len =
1115                                 (uint16_t)(first_seg->pkt_len +
1116                                                 rx_packet_len);
1117                         first_seg->nb_segs++;
1118                         last_seg->next = rxm;
1119                 }
1120
1121                 /**
1122                  * If this is not the last buffer of the received packet,
1123                  * update the pointer to the last mbuf of the current scattered
1124                  * packet and continue to parse the RX ring.
1125                  */
1126                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1127                         last_seg = rxm;
1128                         continue;
1129                 }
1130
1131                 /**
1132                  * This is the last buffer of the received packet. If the CRC
1133                  * is not stripped by the hardware:
1134                  *  - Subtract the CRC length from the total packet length.
1135                  *  - If the last buffer only contains the whole CRC or a part
1136                  *  of it, free the mbuf associated to the last buffer. If part
1137                  *  of the CRC is also contained in the previous mbuf, subtract
1138                  *  the length of that CRC part from the data length of the
1139                  *  previous mbuf.
1140                  */
1141                 rxm->next = NULL;
1142                 if (unlikely(rxq->crc_len > 0)) {
1143                         first_seg->pkt_len -= ETHER_CRC_LEN;
1144                         if (rx_packet_len <= ETHER_CRC_LEN) {
1145                                 rte_pktmbuf_free_seg(rxm);
1146                                 first_seg->nb_segs--;
1147                                 last_seg->data_len =
1148                                         (uint16_t)(last_seg->data_len -
1149                                         (ETHER_CRC_LEN - rx_packet_len));
1150                                 last_seg->next = NULL;
1151                         } else
1152                                 rxm->data_len = (uint16_t)(rx_packet_len -
1153                                                                 ETHER_CRC_LEN);
1154                 }
1155
1156                 first_seg->port = rxq->port_id;
1157                 first_seg->ol_flags = 0;
1158                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1159                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1160                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1161                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1162                 first_seg->packet_type = (uint16_t)((qword1 &
1163                                         I40E_RXD_QW1_PTYPE_MASK) >>
1164                                         I40E_RXD_QW1_PTYPE_SHIFT);
1165                 if (pkt_flags & PKT_RX_RSS_HASH)
1166                         rxm->hash.rss =
1167                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1168                 if (pkt_flags & PKT_RX_FDIR)
1169                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1170
1171 #ifdef RTE_LIBRTE_IEEE1588
1172                 uint16_t tsyn = (qword1 & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
1173                                         | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
1174                                         >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
1175
1176                 if (tsyn & 0x04)
1177                         pkt_flags |= PKT_RX_IEEE1588_TMST;
1178
1179                 first_seg->timesync = tsyn & 0x03;
1180 #endif
1181                 first_seg->ol_flags |= pkt_flags;
1182
1183                 /* Prefetch data of first segment, if configured to do so. */
1184                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1185                         first_seg->data_off));
1186                 rx_pkts[nb_rx++] = first_seg;
1187                 first_seg = NULL;
1188         }
1189
1190         /* Record index of the next RX descriptor to probe. */
1191         rxq->rx_tail = rx_id;
1192         rxq->pkt_first_seg = first_seg;
1193         rxq->pkt_last_seg = last_seg;
1194
1195         /**
1196          * If the number of free RX descriptors is greater than the RX free
1197          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1198          * register. Update the RDT with the value of the last processed RX
1199          * descriptor minus 1, to guarantee that the RDT register is never
1200          * equal to the RDH register, which creates a "full" ring situtation
1201          * from the hardware point of view.
1202          */
1203         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1204         if (nb_hold > rxq->rx_free_thresh) {
1205                 rx_id = (uint16_t)(rx_id == 0 ?
1206                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1207                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1208                 nb_hold = 0;
1209         }
1210         rxq->nb_rx_hold = nb_hold;
1211
1212         return nb_rx;
1213 }
1214
1215 /* Check if the context descriptor is needed for TX offloading */
1216 static inline uint16_t
1217 i40e_calc_context_desc(uint64_t flags)
1218 {
1219         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1220                 PKT_TX_TCP_SEG |
1221                 PKT_TX_QINQ_PKT;
1222
1223 #ifdef RTE_LIBRTE_IEEE1588
1224         mask |= PKT_TX_IEEE1588_TMST;
1225 #endif
1226
1227         return ((flags & mask) ? 1 : 0);
1228 }
1229
1230 /* set i40e TSO context descriptor */
1231 static inline uint64_t
1232 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1233 {
1234         uint64_t ctx_desc = 0;
1235         uint32_t cd_cmd, hdr_len, cd_tso_len;
1236
1237         if (!tx_offload.l4_len) {
1238                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1239                 return ctx_desc;
1240         }
1241
1242         /**
1243          * in case of tunneling packet, the outer_l2_len and
1244          * outer_l3_len must be 0.
1245          */
1246         hdr_len = tx_offload.outer_l2_len +
1247                 tx_offload.outer_l3_len +
1248                 tx_offload.l2_len +
1249                 tx_offload.l3_len +
1250                 tx_offload.l4_len;
1251
1252         cd_cmd = I40E_TX_CTX_DESC_TSO;
1253         cd_tso_len = mbuf->pkt_len - hdr_len;
1254         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1255                 ((uint64_t)cd_tso_len <<
1256                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1257                 ((uint64_t)mbuf->tso_segsz <<
1258                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1259
1260         return ctx_desc;
1261 }
1262
1263 uint16_t
1264 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1265 {
1266         struct i40e_tx_queue *txq;
1267         struct i40e_tx_entry *sw_ring;
1268         struct i40e_tx_entry *txe, *txn;
1269         volatile struct i40e_tx_desc *txd;
1270         volatile struct i40e_tx_desc *txr;
1271         struct rte_mbuf *tx_pkt;
1272         struct rte_mbuf *m_seg;
1273         uint32_t cd_tunneling_params;
1274         uint16_t tx_id;
1275         uint16_t nb_tx;
1276         uint32_t td_cmd;
1277         uint32_t td_offset;
1278         uint32_t tx_flags;
1279         uint32_t td_tag;
1280         uint64_t ol_flags;
1281         uint16_t nb_used;
1282         uint16_t nb_ctx;
1283         uint16_t tx_last;
1284         uint16_t slen;
1285         uint64_t buf_dma_addr;
1286         union i40e_tx_offload tx_offload = {0};
1287
1288         txq = tx_queue;
1289         sw_ring = txq->sw_ring;
1290         txr = txq->tx_ring;
1291         tx_id = txq->tx_tail;
1292         txe = &sw_ring[tx_id];
1293
1294         /* Check if the descriptor ring needs to be cleaned. */
1295         if (txq->nb_tx_free < txq->tx_free_thresh)
1296                 i40e_xmit_cleanup(txq);
1297
1298         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1299                 td_cmd = 0;
1300                 td_tag = 0;
1301                 td_offset = 0;
1302                 tx_flags = 0;
1303
1304                 tx_pkt = *tx_pkts++;
1305                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1306
1307                 ol_flags = tx_pkt->ol_flags;
1308                 tx_offload.l2_len = tx_pkt->l2_len;
1309                 tx_offload.l3_len = tx_pkt->l3_len;
1310                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1311                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1312                 tx_offload.l4_len = tx_pkt->l4_len;
1313                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1314
1315                 /* Calculate the number of context descriptors needed. */
1316                 nb_ctx = i40e_calc_context_desc(ol_flags);
1317
1318                 /**
1319                  * The number of descriptors that must be allocated for
1320                  * a packet equals to the number of the segments of that
1321                  * packet plus 1 context descriptor if needed.
1322                  */
1323                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1324                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1325
1326                 /* Circular ring */
1327                 if (tx_last >= txq->nb_tx_desc)
1328                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1329
1330                 if (nb_used > txq->nb_tx_free) {
1331                         if (i40e_xmit_cleanup(txq) != 0) {
1332                                 if (nb_tx == 0)
1333                                         return 0;
1334                                 goto end_of_tx;
1335                         }
1336                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1337                                 while (nb_used > txq->nb_tx_free) {
1338                                         if (i40e_xmit_cleanup(txq) != 0) {
1339                                                 if (nb_tx == 0)
1340                                                         return 0;
1341                                                 goto end_of_tx;
1342                                         }
1343                                 }
1344                         }
1345                 }
1346
1347                 /* Descriptor based VLAN insertion */
1348                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1349                         tx_flags |= tx_pkt->vlan_tci <<
1350                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1351                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1352                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1353                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1354                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1355                 }
1356
1357                 /* Always enable CRC offload insertion */
1358                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1359
1360                 /* Enable checksum offloading */
1361                 cd_tunneling_params = 0;
1362                 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1363                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1364                                 tx_offload, &cd_tunneling_params);
1365                 }
1366
1367                 if (unlikely(nb_ctx)) {
1368                         /* Setup TX context descriptor if required */
1369                         volatile struct i40e_tx_context_desc *ctx_txd =
1370                                 (volatile struct i40e_tx_context_desc *)\
1371                                                         &txr[tx_id];
1372                         uint16_t cd_l2tag2 = 0;
1373                         uint64_t cd_type_cmd_tso_mss =
1374                                 I40E_TX_DESC_DTYPE_CONTEXT;
1375
1376                         txn = &sw_ring[txe->next_id];
1377                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1378                         if (txe->mbuf != NULL) {
1379                                 rte_pktmbuf_free_seg(txe->mbuf);
1380                                 txe->mbuf = NULL;
1381                         }
1382
1383                         /* TSO enabled means no timestamp */
1384                         if (ol_flags & PKT_TX_TCP_SEG)
1385                                 cd_type_cmd_tso_mss |=
1386                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1387                         else {
1388 #ifdef RTE_LIBRTE_IEEE1588
1389                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1390                                         cd_type_cmd_tso_mss |=
1391                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1392                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1393 #endif
1394                         }
1395
1396                         ctx_txd->tunneling_params =
1397                                 rte_cpu_to_le_32(cd_tunneling_params);
1398                         if (ol_flags & PKT_TX_QINQ_PKT) {
1399                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1400                                 cd_type_cmd_tso_mss |=
1401                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1402                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1403                         }
1404                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1405                         ctx_txd->type_cmd_tso_mss =
1406                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1407
1408                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1409                                 "tunneling_params: %#x;\n"
1410                                 "l2tag2: %#hx;\n"
1411                                 "rsvd: %#hx;\n"
1412                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1413                                 tx_pkt, tx_id,
1414                                 ctx_txd->tunneling_params,
1415                                 ctx_txd->l2tag2,
1416                                 ctx_txd->rsvd,
1417                                 ctx_txd->type_cmd_tso_mss);
1418
1419                         txe->last_id = tx_last;
1420                         tx_id = txe->next_id;
1421                         txe = txn;
1422                 }
1423
1424                 m_seg = tx_pkt;
1425                 do {
1426                         txd = &txr[tx_id];
1427                         txn = &sw_ring[txe->next_id];
1428
1429                         if (txe->mbuf)
1430                                 rte_pktmbuf_free_seg(txe->mbuf);
1431                         txe->mbuf = m_seg;
1432
1433                         /* Setup TX Descriptor */
1434                         slen = m_seg->data_len;
1435                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1436
1437                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1438                                 "buf_dma_addr: %#"PRIx64";\n"
1439                                 "td_cmd: %#x;\n"
1440                                 "td_offset: %#x;\n"
1441                                 "td_len: %u;\n"
1442                                 "td_tag: %#x;\n",
1443                                 tx_pkt, tx_id, buf_dma_addr,
1444                                 td_cmd, td_offset, slen, td_tag);
1445
1446                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1447                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1448                                                 td_offset, slen, td_tag);
1449                         txe->last_id = tx_last;
1450                         tx_id = txe->next_id;
1451                         txe = txn;
1452                         m_seg = m_seg->next;
1453                 } while (m_seg != NULL);
1454
1455                 /* The last packet data descriptor needs End Of Packet (EOP) */
1456                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1457                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1458                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1459
1460                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1461                         PMD_TX_FREE_LOG(DEBUG,
1462                                         "Setting RS bit on TXD id="
1463                                         "%4u (port=%d queue=%d)",
1464                                         tx_last, txq->port_id, txq->queue_id);
1465
1466                         td_cmd |= I40E_TX_DESC_CMD_RS;
1467
1468                         /* Update txq RS bit counters */
1469                         txq->nb_tx_used = 0;
1470                 }
1471
1472                 txd->cmd_type_offset_bsz |=
1473                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1474                                         I40E_TXD_QW1_CMD_SHIFT);
1475         }
1476
1477 end_of_tx:
1478         rte_wmb();
1479
1480         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1481                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1482                    (unsigned) tx_id, (unsigned) nb_tx);
1483
1484         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1485         txq->tx_tail = tx_id;
1486
1487         return nb_tx;
1488 }
1489
1490 static inline int __attribute__((always_inline))
1491 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1492 {
1493         struct i40e_tx_entry *txep;
1494         uint16_t i;
1495
1496         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1497                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1498                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1499                 return 0;
1500
1501         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1502
1503         for (i = 0; i < txq->tx_rs_thresh; i++)
1504                 rte_prefetch0((txep + i)->mbuf);
1505
1506         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1507                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1508                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1509                         txep->mbuf = NULL;
1510                 }
1511         } else {
1512                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1513                         rte_pktmbuf_free_seg(txep->mbuf);
1514                         txep->mbuf = NULL;
1515                 }
1516         }
1517
1518         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1519         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1520         if (txq->tx_next_dd >= txq->nb_tx_desc)
1521                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1522
1523         return txq->tx_rs_thresh;
1524 }
1525
1526 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1527                      I40E_TX_DESC_CMD_EOP)
1528
1529 /* Populate 4 descriptors with data from 4 mbufs */
1530 static inline void
1531 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1532 {
1533         uint64_t dma_addr;
1534         uint32_t i;
1535
1536         for (i = 0; i < 4; i++, txdp++, pkts++) {
1537                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1538                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1539                 txdp->cmd_type_offset_bsz =
1540                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1541                                         (*pkts)->data_len, 0);
1542         }
1543 }
1544
1545 /* Populate 1 descriptor with data from 1 mbuf */
1546 static inline void
1547 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1548 {
1549         uint64_t dma_addr;
1550
1551         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1552         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1553         txdp->cmd_type_offset_bsz =
1554                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1555                                 (*pkts)->data_len, 0);
1556 }
1557
1558 /* Fill hardware descriptor ring with mbuf data */
1559 static inline void
1560 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1561                      struct rte_mbuf **pkts,
1562                      uint16_t nb_pkts)
1563 {
1564         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1565         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1566         const int N_PER_LOOP = 4;
1567         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1568         int mainpart, leftover;
1569         int i, j;
1570
1571         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1572         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1573         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1574                 for (j = 0; j < N_PER_LOOP; ++j) {
1575                         (txep + i + j)->mbuf = *(pkts + i + j);
1576                 }
1577                 tx4(txdp + i, pkts + i);
1578         }
1579         if (unlikely(leftover > 0)) {
1580                 for (i = 0; i < leftover; ++i) {
1581                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1582                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1583                 }
1584         }
1585 }
1586
1587 static inline uint16_t
1588 tx_xmit_pkts(struct i40e_tx_queue *txq,
1589              struct rte_mbuf **tx_pkts,
1590              uint16_t nb_pkts)
1591 {
1592         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1593         uint16_t n = 0;
1594
1595         /**
1596          * Begin scanning the H/W ring for done descriptors when the number
1597          * of available descriptors drops below tx_free_thresh. For each done
1598          * descriptor, free the associated buffer.
1599          */
1600         if (txq->nb_tx_free < txq->tx_free_thresh)
1601                 i40e_tx_free_bufs(txq);
1602
1603         /* Use available descriptor only */
1604         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1605         if (unlikely(!nb_pkts))
1606                 return 0;
1607
1608         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1609         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1610                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1611                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1612                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1613                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1614                                                 I40E_TXD_QW1_CMD_SHIFT);
1615                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1616                 txq->tx_tail = 0;
1617         }
1618
1619         /* Fill hardware descriptor ring with mbuf data */
1620         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1621         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1622
1623         /* Determin if RS bit needs to be set */
1624         if (txq->tx_tail > txq->tx_next_rs) {
1625                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1626                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1627                                                 I40E_TXD_QW1_CMD_SHIFT);
1628                 txq->tx_next_rs =
1629                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1630                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1631                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1632         }
1633
1634         if (txq->tx_tail >= txq->nb_tx_desc)
1635                 txq->tx_tail = 0;
1636
1637         /* Update the tx tail register */
1638         rte_wmb();
1639         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1640
1641         return nb_pkts;
1642 }
1643
1644 static uint16_t
1645 i40e_xmit_pkts_simple(void *tx_queue,
1646                       struct rte_mbuf **tx_pkts,
1647                       uint16_t nb_pkts)
1648 {
1649         uint16_t nb_tx = 0;
1650
1651         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1652                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1653                                                 tx_pkts, nb_pkts);
1654
1655         while (nb_pkts) {
1656                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1657                                                 I40E_TX_MAX_BURST);
1658
1659                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1660                                                 &tx_pkts[nb_tx], num);
1661                 nb_tx = (uint16_t)(nb_tx + ret);
1662                 nb_pkts = (uint16_t)(nb_pkts - ret);
1663                 if (ret < num)
1664                         break;
1665         }
1666
1667         return nb_tx;
1668 }
1669
1670 /*
1671  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1672  * application used, which assume having sequential ones. But from driver's
1673  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1674  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1675  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1676  * use queue_idx from 0 to 95 to access queues, while real queue would be
1677  * different. This function will do a queue mapping to find VSI the queue
1678  * belongs to.
1679  */
1680 static struct i40e_vsi*
1681 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1682 {
1683         /* the queue in MAIN VSI range */
1684         if (queue_idx < pf->main_vsi->nb_qps)
1685                 return pf->main_vsi;
1686
1687         queue_idx -= pf->main_vsi->nb_qps;
1688
1689         /* queue_idx is greater than VMDQ VSIs range */
1690         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1691                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1692                 return NULL;
1693         }
1694
1695         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1696 }
1697
1698 static uint16_t
1699 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1700 {
1701         /* the queue in MAIN VSI range */
1702         if (queue_idx < pf->main_vsi->nb_qps)
1703                 return queue_idx;
1704
1705         /* It's VMDQ queues */
1706         queue_idx -= pf->main_vsi->nb_qps;
1707
1708         if (pf->nb_cfg_vmdq_vsi)
1709                 return queue_idx % pf->vmdq_nb_qps;
1710         else {
1711                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1712                 return (uint16_t)(-1);
1713         }
1714 }
1715
1716 int
1717 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1718 {
1719         struct i40e_rx_queue *rxq;
1720         int err = -1;
1721         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1722
1723         PMD_INIT_FUNC_TRACE();
1724
1725         if (rx_queue_id < dev->data->nb_rx_queues) {
1726                 rxq = dev->data->rx_queues[rx_queue_id];
1727
1728                 err = i40e_alloc_rx_queue_mbufs(rxq);
1729                 if (err) {
1730                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1731                         return err;
1732                 }
1733
1734                 rte_wmb();
1735
1736                 /* Init the RX tail regieter. */
1737                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1738
1739                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1740
1741                 if (err) {
1742                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1743                                     rx_queue_id);
1744
1745                         i40e_rx_queue_release_mbufs(rxq);
1746                         i40e_reset_rx_queue(rxq);
1747                 }
1748         }
1749
1750         return err;
1751 }
1752
1753 int
1754 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1755 {
1756         struct i40e_rx_queue *rxq;
1757         int err;
1758         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1759
1760         if (rx_queue_id < dev->data->nb_rx_queues) {
1761                 rxq = dev->data->rx_queues[rx_queue_id];
1762
1763                 /*
1764                 * rx_queue_id is queue id aplication refers to, while
1765                 * rxq->reg_idx is the real queue index.
1766                 */
1767                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1768
1769                 if (err) {
1770                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1771                                     rx_queue_id);
1772                         return err;
1773                 }
1774                 i40e_rx_queue_release_mbufs(rxq);
1775                 i40e_reset_rx_queue(rxq);
1776         }
1777
1778         return 0;
1779 }
1780
1781 int
1782 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1783 {
1784         int err = -1;
1785         struct i40e_tx_queue *txq;
1786         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1787
1788         PMD_INIT_FUNC_TRACE();
1789
1790         if (tx_queue_id < dev->data->nb_tx_queues) {
1791                 txq = dev->data->tx_queues[tx_queue_id];
1792
1793                 /*
1794                 * tx_queue_id is queue id aplication refers to, while
1795                 * rxq->reg_idx is the real queue index.
1796                 */
1797                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1798                 if (err)
1799                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1800                                     tx_queue_id);
1801         }
1802
1803         return err;
1804 }
1805
1806 int
1807 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1808 {
1809         struct i40e_tx_queue *txq;
1810         int err;
1811         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1812
1813         if (tx_queue_id < dev->data->nb_tx_queues) {
1814                 txq = dev->data->tx_queues[tx_queue_id];
1815
1816                 /*
1817                 * tx_queue_id is queue id aplication refers to, while
1818                 * txq->reg_idx is the real queue index.
1819                 */
1820                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1821
1822                 if (err) {
1823                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1824                                     tx_queue_id);
1825                         return err;
1826                 }
1827
1828                 i40e_tx_queue_release_mbufs(txq);
1829                 i40e_reset_tx_queue(txq);
1830         }
1831
1832         return 0;
1833 }
1834
1835 int
1836 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1837                         uint16_t queue_idx,
1838                         uint16_t nb_desc,
1839                         unsigned int socket_id,
1840                         const struct rte_eth_rxconf *rx_conf,
1841                         struct rte_mempool *mp)
1842 {
1843         struct i40e_vsi *vsi;
1844         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1845         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1846         struct i40e_rx_queue *rxq;
1847         const struct rte_memzone *rz;
1848         uint32_t ring_size;
1849         uint16_t len;
1850         int use_def_burst_func = 1;
1851
1852         if (hw->mac.type == I40E_MAC_VF) {
1853                 struct i40e_vf *vf =
1854                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1855                 vsi = &vf->vsi;
1856         } else
1857                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1858
1859         if (vsi == NULL) {
1860                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1861                             "index exceeds the maximum");
1862                 return I40E_ERR_PARAM;
1863         }
1864         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1865                                         (nb_desc > I40E_MAX_RING_DESC) ||
1866                                         (nb_desc < I40E_MIN_RING_DESC)) {
1867                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1868                             "invalid", nb_desc);
1869                 return I40E_ERR_PARAM;
1870         }
1871
1872         /* Free memory if needed */
1873         if (dev->data->rx_queues[queue_idx]) {
1874                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1875                 dev->data->rx_queues[queue_idx] = NULL;
1876         }
1877
1878         /* Allocate the rx queue data structure */
1879         rxq = rte_zmalloc_socket("i40e rx queue",
1880                                  sizeof(struct i40e_rx_queue),
1881                                  RTE_CACHE_LINE_SIZE,
1882                                  socket_id);
1883         if (!rxq) {
1884                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1885                             "rx queue data structure");
1886                 return (-ENOMEM);
1887         }
1888         rxq->mp = mp;
1889         rxq->nb_rx_desc = nb_desc;
1890         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1891         rxq->queue_id = queue_idx;
1892         if (hw->mac.type == I40E_MAC_VF)
1893                 rxq->reg_idx = queue_idx;
1894         else /* PF device */
1895                 rxq->reg_idx = vsi->base_queue +
1896                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1897
1898         rxq->port_id = dev->data->port_id;
1899         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1900                                                         0 : ETHER_CRC_LEN);
1901         rxq->drop_en = rx_conf->rx_drop_en;
1902         rxq->vsi = vsi;
1903         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1904
1905         /* Allocate the maximun number of RX ring hardware descriptor. */
1906         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1907         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1908         rz = i40e_ring_dma_zone_reserve(dev,
1909                                         "rx_ring",
1910                                         queue_idx,
1911                                         ring_size,
1912                                         socket_id);
1913         if (!rz) {
1914                 i40e_dev_rx_queue_release(rxq);
1915                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1916                 return (-ENOMEM);
1917         }
1918
1919         /* Zero all the descriptors in the ring. */
1920         memset(rz->addr, 0, ring_size);
1921
1922 #ifdef RTE_LIBRTE_XEN_DOM0
1923         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1924 #else
1925         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1926 #endif
1927
1928         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1929
1930 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1931         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1932 #else
1933         len = nb_desc;
1934 #endif
1935
1936         /* Allocate the software ring. */
1937         rxq->sw_ring =
1938                 rte_zmalloc_socket("i40e rx sw ring",
1939                                    sizeof(struct i40e_rx_entry) * len,
1940                                    RTE_CACHE_LINE_SIZE,
1941                                    socket_id);
1942         if (!rxq->sw_ring) {
1943                 i40e_dev_rx_queue_release(rxq);
1944                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1945                 return (-ENOMEM);
1946         }
1947
1948         i40e_reset_rx_queue(rxq);
1949         rxq->q_set = TRUE;
1950         dev->data->rx_queues[queue_idx] = rxq;
1951
1952         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1953
1954         if (!use_def_burst_func && !dev->data->scattered_rx) {
1955 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1956                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1957                              "satisfied. Rx Burst Bulk Alloc function will be "
1958                              "used on port=%d, queue=%d.",
1959                              rxq->port_id, rxq->queue_id);
1960                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1961 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1962         } else {
1963                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1964                              "not satisfied, Scattered Rx is requested, "
1965                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1966                              "not enabled on port=%d, queue=%d.",
1967                              rxq->port_id, rxq->queue_id);
1968         }
1969
1970         return 0;
1971 }
1972
1973 void
1974 i40e_dev_rx_queue_release(void *rxq)
1975 {
1976         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1977
1978         if (!q) {
1979                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1980                 return;
1981         }
1982
1983         i40e_rx_queue_release_mbufs(q);
1984         rte_free(q->sw_ring);
1985         rte_free(q);
1986 }
1987
1988 uint32_t
1989 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1990 {
1991 #define I40E_RXQ_SCAN_INTERVAL 4
1992         volatile union i40e_rx_desc *rxdp;
1993         struct i40e_rx_queue *rxq;
1994         uint16_t desc = 0;
1995
1996         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1997                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1998                 return 0;
1999         }
2000
2001         rxq = dev->data->rx_queues[rx_queue_id];
2002         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
2003         while ((desc < rxq->nb_rx_desc) &&
2004                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2005                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2006                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
2007                 /**
2008                  * Check the DD bit of a rx descriptor of each 4 in a group,
2009                  * to avoid checking too frequently and downgrading performance
2010                  * too much.
2011                  */
2012                 desc += I40E_RXQ_SCAN_INTERVAL;
2013                 rxdp += I40E_RXQ_SCAN_INTERVAL;
2014                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2015                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2016                                         desc - rxq->nb_rx_desc]);
2017         }
2018
2019         return desc;
2020 }
2021
2022 int
2023 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
2024 {
2025         volatile union i40e_rx_desc *rxdp;
2026         struct i40e_rx_queue *rxq = rx_queue;
2027         uint16_t desc;
2028         int ret;
2029
2030         if (unlikely(offset >= rxq->nb_rx_desc)) {
2031                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
2032                 return 0;
2033         }
2034
2035         desc = rxq->rx_tail + offset;
2036         if (desc >= rxq->nb_rx_desc)
2037                 desc -= rxq->nb_rx_desc;
2038
2039         rxdp = &(rxq->rx_ring[desc]);
2040
2041         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2042                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2043                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2044
2045         return ret;
2046 }
2047
2048 int
2049 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2050                         uint16_t queue_idx,
2051                         uint16_t nb_desc,
2052                         unsigned int socket_id,
2053                         const struct rte_eth_txconf *tx_conf)
2054 {
2055         struct i40e_vsi *vsi;
2056         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2057         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2058         struct i40e_tx_queue *txq;
2059         const struct rte_memzone *tz;
2060         uint32_t ring_size;
2061         uint16_t tx_rs_thresh, tx_free_thresh;
2062
2063         if (hw->mac.type == I40E_MAC_VF) {
2064                 struct i40e_vf *vf =
2065                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2066                 vsi = &vf->vsi;
2067         } else
2068                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2069
2070         if (vsi == NULL) {
2071                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2072                             "exceeds the maximum", queue_idx);
2073                 return I40E_ERR_PARAM;
2074         }
2075
2076         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2077                                         (nb_desc > I40E_MAX_RING_DESC) ||
2078                                         (nb_desc < I40E_MIN_RING_DESC)) {
2079                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2080                             "invalid", nb_desc);
2081                 return I40E_ERR_PARAM;
2082         }
2083
2084         /**
2085          * The following two parameters control the setting of the RS bit on
2086          * transmit descriptors. TX descriptors will have their RS bit set
2087          * after txq->tx_rs_thresh descriptors have been used. The TX
2088          * descriptor ring will be cleaned after txq->tx_free_thresh
2089          * descriptors are used or if the number of descriptors required to
2090          * transmit a packet is greater than the number of free TX descriptors.
2091          *
2092          * The following constraints must be satisfied:
2093          *  - tx_rs_thresh must be greater than 0.
2094          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2095          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2096          *  - tx_rs_thresh must be a divisor of the ring size.
2097          *  - tx_free_thresh must be greater than 0.
2098          *  - tx_free_thresh must be less than the size of the ring minus 3.
2099          *
2100          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2101          * race condition, hence the maximum threshold constraints. When set
2102          * to zero use default values.
2103          */
2104         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2105                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2106         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2107                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2108         if (tx_rs_thresh >= (nb_desc - 2)) {
2109                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2110                              "number of TX descriptors minus 2. "
2111                              "(tx_rs_thresh=%u port=%d queue=%d)",
2112                              (unsigned int)tx_rs_thresh,
2113                              (int)dev->data->port_id,
2114                              (int)queue_idx);
2115                 return I40E_ERR_PARAM;
2116         }
2117         if (tx_free_thresh >= (nb_desc - 3)) {
2118                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2119                              "tx_free_thresh must be less than the "
2120                              "number of TX descriptors minus 3. "
2121                              "(tx_free_thresh=%u port=%d queue=%d)",
2122                              (unsigned int)tx_free_thresh,
2123                              (int)dev->data->port_id,
2124                              (int)queue_idx);
2125                 return I40E_ERR_PARAM;
2126         }
2127         if (tx_rs_thresh > tx_free_thresh) {
2128                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2129                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2130                              " tx_rs_thresh=%u port=%d queue=%d)",
2131                              (unsigned int)tx_free_thresh,
2132                              (unsigned int)tx_rs_thresh,
2133                              (int)dev->data->port_id,
2134                              (int)queue_idx);
2135                 return I40E_ERR_PARAM;
2136         }
2137         if ((nb_desc % tx_rs_thresh) != 0) {
2138                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2139                              "number of TX descriptors. (tx_rs_thresh=%u"
2140                              " port=%d queue=%d)",
2141                              (unsigned int)tx_rs_thresh,
2142                              (int)dev->data->port_id,
2143                              (int)queue_idx);
2144                 return I40E_ERR_PARAM;
2145         }
2146         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2147                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2148                              "tx_rs_thresh is greater than 1. "
2149                              "(tx_rs_thresh=%u port=%d queue=%d)",
2150                              (unsigned int)tx_rs_thresh,
2151                              (int)dev->data->port_id,
2152                              (int)queue_idx);
2153                 return I40E_ERR_PARAM;
2154         }
2155
2156         /* Free memory if needed. */
2157         if (dev->data->tx_queues[queue_idx]) {
2158                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2159                 dev->data->tx_queues[queue_idx] = NULL;
2160         }
2161
2162         /* Allocate the TX queue data structure. */
2163         txq = rte_zmalloc_socket("i40e tx queue",
2164                                   sizeof(struct i40e_tx_queue),
2165                                   RTE_CACHE_LINE_SIZE,
2166                                   socket_id);
2167         if (!txq) {
2168                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2169                             "tx queue structure");
2170                 return (-ENOMEM);
2171         }
2172
2173         /* Allocate TX hardware ring descriptors. */
2174         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2175         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2176         tz = i40e_ring_dma_zone_reserve(dev,
2177                                         "tx_ring",
2178                                         queue_idx,
2179                                         ring_size,
2180                                         socket_id);
2181         if (!tz) {
2182                 i40e_dev_tx_queue_release(txq);
2183                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2184                 return (-ENOMEM);
2185         }
2186
2187         txq->nb_tx_desc = nb_desc;
2188         txq->tx_rs_thresh = tx_rs_thresh;
2189         txq->tx_free_thresh = tx_free_thresh;
2190         txq->pthresh = tx_conf->tx_thresh.pthresh;
2191         txq->hthresh = tx_conf->tx_thresh.hthresh;
2192         txq->wthresh = tx_conf->tx_thresh.wthresh;
2193         txq->queue_id = queue_idx;
2194         if (hw->mac.type == I40E_MAC_VF)
2195                 txq->reg_idx = queue_idx;
2196         else /* PF device */
2197                 txq->reg_idx = vsi->base_queue +
2198                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2199
2200         txq->port_id = dev->data->port_id;
2201         txq->txq_flags = tx_conf->txq_flags;
2202         txq->vsi = vsi;
2203         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2204
2205 #ifdef RTE_LIBRTE_XEN_DOM0
2206         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2207 #else
2208         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2209 #endif
2210         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2211
2212         /* Allocate software ring */
2213         txq->sw_ring =
2214                 rte_zmalloc_socket("i40e tx sw ring",
2215                                    sizeof(struct i40e_tx_entry) * nb_desc,
2216                                    RTE_CACHE_LINE_SIZE,
2217                                    socket_id);
2218         if (!txq->sw_ring) {
2219                 i40e_dev_tx_queue_release(txq);
2220                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2221                 return (-ENOMEM);
2222         }
2223
2224         i40e_reset_tx_queue(txq);
2225         txq->q_set = TRUE;
2226         dev->data->tx_queues[queue_idx] = txq;
2227
2228         /* Use a simple TX queue without offloads or multi segs if possible */
2229         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2230                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2231                 PMD_INIT_LOG(INFO, "Using simple tx path");
2232                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2233         } else {
2234                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2235                 dev->tx_pkt_burst = i40e_xmit_pkts;
2236         }
2237
2238         return 0;
2239 }
2240
2241 void
2242 i40e_dev_tx_queue_release(void *txq)
2243 {
2244         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2245
2246         if (!q) {
2247                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2248                 return;
2249         }
2250
2251         i40e_tx_queue_release_mbufs(q);
2252         rte_free(q->sw_ring);
2253         rte_free(q);
2254 }
2255
2256 static const struct rte_memzone *
2257 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2258                            const char *ring_name,
2259                            uint16_t queue_id,
2260                            uint32_t ring_size,
2261                            int socket_id)
2262 {
2263         char z_name[RTE_MEMZONE_NAMESIZE];
2264         const struct rte_memzone *mz;
2265
2266         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2267                         dev->driver->pci_drv.name, ring_name,
2268                                 dev->data->port_id, queue_id);
2269         mz = rte_memzone_lookup(z_name);
2270         if (mz)
2271                 return mz;
2272
2273 #ifdef RTE_LIBRTE_XEN_DOM0
2274         return rte_memzone_reserve_bounded(z_name, ring_size,
2275                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2276 #else
2277         return rte_memzone_reserve_aligned(z_name, ring_size,
2278                                 socket_id, 0, I40E_ALIGN);
2279 #endif
2280 }
2281
2282 const struct rte_memzone *
2283 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2284 {
2285         const struct rte_memzone *mz = NULL;
2286
2287         mz = rte_memzone_lookup(name);
2288         if (mz)
2289                 return mz;
2290 #ifdef RTE_LIBRTE_XEN_DOM0
2291         mz = rte_memzone_reserve_bounded(name, len,
2292                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2293 #else
2294         mz = rte_memzone_reserve_aligned(name, len,
2295                                 socket_id, 0, I40E_ALIGN);
2296 #endif
2297         return mz;
2298 }
2299
2300 void
2301 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2302 {
2303         uint16_t i;
2304
2305         if (!rxq || !rxq->sw_ring) {
2306                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2307                 return;
2308         }
2309
2310         for (i = 0; i < rxq->nb_rx_desc; i++) {
2311                 if (rxq->sw_ring[i].mbuf) {
2312                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2313                         rxq->sw_ring[i].mbuf = NULL;
2314                 }
2315         }
2316 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2317         if (rxq->rx_nb_avail == 0)
2318                 return;
2319         for (i = 0; i < rxq->rx_nb_avail; i++) {
2320                 struct rte_mbuf *mbuf;
2321
2322                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2323                 rte_pktmbuf_free_seg(mbuf);
2324         }
2325         rxq->rx_nb_avail = 0;
2326 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2327 }
2328
2329 void
2330 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2331 {
2332         unsigned i;
2333         uint16_t len;
2334
2335 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2336         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2337                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2338         else
2339 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2340                 len = rxq->nb_rx_desc;
2341
2342         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2343                 ((volatile char *)rxq->rx_ring)[i] = 0;
2344
2345 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2346         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2347         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2348                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2349
2350         rxq->rx_nb_avail = 0;
2351         rxq->rx_next_avail = 0;
2352         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2353 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2354         rxq->rx_tail = 0;
2355         rxq->nb_rx_hold = 0;
2356         rxq->pkt_first_seg = NULL;
2357         rxq->pkt_last_seg = NULL;
2358 }
2359
2360 void
2361 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2362 {
2363         uint16_t i;
2364
2365         if (!txq || !txq->sw_ring) {
2366                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2367                 return;
2368         }
2369
2370         for (i = 0; i < txq->nb_tx_desc; i++) {
2371                 if (txq->sw_ring[i].mbuf) {
2372                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2373                         txq->sw_ring[i].mbuf = NULL;
2374                 }
2375         }
2376 }
2377
2378 void
2379 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2380 {
2381         struct i40e_tx_entry *txe;
2382         uint16_t i, prev, size;
2383
2384         if (!txq) {
2385                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2386                 return;
2387         }
2388
2389         txe = txq->sw_ring;
2390         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2391         for (i = 0; i < size; i++)
2392                 ((volatile char *)txq->tx_ring)[i] = 0;
2393
2394         prev = (uint16_t)(txq->nb_tx_desc - 1);
2395         for (i = 0; i < txq->nb_tx_desc; i++) {
2396                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2397
2398                 txd->cmd_type_offset_bsz =
2399                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2400                 txe[i].mbuf =  NULL;
2401                 txe[i].last_id = i;
2402                 txe[prev].next_id = i;
2403                 prev = i;
2404         }
2405
2406         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2407         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2408
2409         txq->tx_tail = 0;
2410         txq->nb_tx_used = 0;
2411
2412         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2413         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2414 }
2415
2416 /* Init the TX queue in hardware */
2417 int
2418 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2419 {
2420         enum i40e_status_code err = I40E_SUCCESS;
2421         struct i40e_vsi *vsi = txq->vsi;
2422         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2423         uint16_t pf_q = txq->reg_idx;
2424         struct i40e_hmc_obj_txq tx_ctx;
2425         uint32_t qtx_ctl;
2426
2427         /* clear the context structure first */
2428         memset(&tx_ctx, 0, sizeof(tx_ctx));
2429         tx_ctx.new_context = 1;
2430         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2431         tx_ctx.qlen = txq->nb_tx_desc;
2432
2433 #ifdef RTE_LIBRTE_IEEE1588
2434         tx_ctx.timesync_ena = 1;
2435 #endif
2436         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2437         if (vsi->type == I40E_VSI_FDIR)
2438                 tx_ctx.fd_ena = TRUE;
2439
2440         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2441         if (err != I40E_SUCCESS) {
2442                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2443                 return err;
2444         }
2445
2446         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2447         if (err != I40E_SUCCESS) {
2448                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2449                 return err;
2450         }
2451
2452         /* Now associate this queue with this PCI function */
2453         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2454         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2455                                         I40E_QTX_CTL_PF_INDX_MASK);
2456         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2457         I40E_WRITE_FLUSH(hw);
2458
2459         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2460
2461         return err;
2462 }
2463
2464 int
2465 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2466 {
2467         struct i40e_rx_entry *rxe = rxq->sw_ring;
2468         uint64_t dma_addr;
2469         uint16_t i;
2470
2471         for (i = 0; i < rxq->nb_rx_desc; i++) {
2472                 volatile union i40e_rx_desc *rxd;
2473                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2474
2475                 if (unlikely(!mbuf)) {
2476                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2477                         return -ENOMEM;
2478                 }
2479
2480                 rte_mbuf_refcnt_set(mbuf, 1);
2481                 mbuf->next = NULL;
2482                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2483                 mbuf->nb_segs = 1;
2484                 mbuf->port = rxq->port_id;
2485
2486                 dma_addr =
2487                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2488
2489                 rxd = &rxq->rx_ring[i];
2490                 rxd->read.pkt_addr = dma_addr;
2491                 rxd->read.hdr_addr = dma_addr;
2492 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2493                 rxd->read.rsvd1 = 0;
2494                 rxd->read.rsvd2 = 0;
2495 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2496
2497                 rxe[i].mbuf = mbuf;
2498         }
2499
2500         return 0;
2501 }
2502
2503 /*
2504  * Calculate the buffer length, and check the jumbo frame
2505  * and maximum packet length.
2506  */
2507 static int
2508 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2509 {
2510         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2511         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2512         struct rte_eth_dev_data *data = pf->dev_data;
2513         uint16_t buf_size, len;
2514
2515         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2516                 RTE_PKTMBUF_HEADROOM);
2517
2518         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2519                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2520         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2521                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2522                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2523                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2524                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2525                 rxq->hs_mode = i40e_header_split_enabled;
2526                 break;
2527         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2528         default:
2529                 rxq->rx_hdr_len = 0;
2530                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2531                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2532                 rxq->hs_mode = i40e_header_split_none;
2533                 break;
2534         }
2535
2536         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2537         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2538         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2539                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2540                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2541                         PMD_DRV_LOG(ERR, "maximum packet length must "
2542                                     "be larger than %u and smaller than %u,"
2543                                     "as jumbo frame is enabled",
2544                                     (uint32_t)ETHER_MAX_LEN,
2545                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2546                         return I40E_ERR_CONFIG;
2547                 }
2548         } else {
2549                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2550                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2551                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2552                                     "larger than %u and smaller than %u, "
2553                                     "as jumbo frame is disabled",
2554                                     (uint32_t)ETHER_MIN_LEN,
2555                                     (uint32_t)ETHER_MAX_LEN);
2556                         return I40E_ERR_CONFIG;
2557                 }
2558         }
2559
2560         return 0;
2561 }
2562
2563 /* Init the RX queue in hardware */
2564 int
2565 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2566 {
2567         int err = I40E_SUCCESS;
2568         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2569         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2570         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2571         uint16_t pf_q = rxq->reg_idx;
2572         uint16_t buf_size;
2573         struct i40e_hmc_obj_rxq rx_ctx;
2574
2575         err = i40e_rx_queue_config(rxq);
2576         if (err < 0) {
2577                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2578                 return err;
2579         }
2580
2581         /* Clear the context structure first */
2582         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2583         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2584         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2585
2586         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2587         rx_ctx.qlen = rxq->nb_rx_desc;
2588 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2589         rx_ctx.dsize = 1;
2590 #endif
2591         rx_ctx.dtype = rxq->hs_mode;
2592         if (rxq->hs_mode)
2593                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2594         else
2595                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2596         rx_ctx.rxmax = rxq->max_pkt_len;
2597         rx_ctx.tphrdesc_ena = 1;
2598         rx_ctx.tphwdesc_ena = 1;
2599         rx_ctx.tphdata_ena = 1;
2600         rx_ctx.tphhead_ena = 1;
2601         rx_ctx.lrxqthresh = 2;
2602         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2603         rx_ctx.l2tsel = 1;
2604         rx_ctx.showiv = 1;
2605         rx_ctx.prefena = 1;
2606
2607         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2608         if (err != I40E_SUCCESS) {
2609                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2610                 return err;
2611         }
2612         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2613         if (err != I40E_SUCCESS) {
2614                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2615                 return err;
2616         }
2617
2618         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2619
2620         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2621                 RTE_PKTMBUF_HEADROOM);
2622
2623         /* Check if scattered RX needs to be used. */
2624         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2625                 dev_data->scattered_rx = 1;
2626                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2627         }
2628
2629         /* Init the RX tail regieter. */
2630         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2631
2632         return 0;
2633 }
2634
2635 void
2636 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2637 {
2638         uint16_t i;
2639
2640         PMD_INIT_FUNC_TRACE();
2641
2642         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2643                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2644                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2645         }
2646
2647         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2648                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2649                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2650         }
2651 }
2652
2653 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2654 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2655
2656 enum i40e_status_code
2657 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2658 {
2659         struct i40e_tx_queue *txq;
2660         const struct rte_memzone *tz = NULL;
2661         uint32_t ring_size;
2662         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2663
2664         if (!pf) {
2665                 PMD_DRV_LOG(ERR, "PF is not available");
2666                 return I40E_ERR_BAD_PTR;
2667         }
2668
2669         /* Allocate the TX queue data structure. */
2670         txq = rte_zmalloc_socket("i40e fdir tx queue",
2671                                   sizeof(struct i40e_tx_queue),
2672                                   RTE_CACHE_LINE_SIZE,
2673                                   SOCKET_ID_ANY);
2674         if (!txq) {
2675                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2676                                         "tx queue structure.");
2677                 return I40E_ERR_NO_MEMORY;
2678         }
2679
2680         /* Allocate TX hardware ring descriptors. */
2681         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2682         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2683
2684         tz = i40e_ring_dma_zone_reserve(dev,
2685                                         "fdir_tx_ring",
2686                                         I40E_FDIR_QUEUE_ID,
2687                                         ring_size,
2688                                         SOCKET_ID_ANY);
2689         if (!tz) {
2690                 i40e_dev_tx_queue_release(txq);
2691                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2692                 return I40E_ERR_NO_MEMORY;
2693         }
2694
2695         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2696         txq->queue_id = I40E_FDIR_QUEUE_ID;
2697         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2698         txq->vsi = pf->fdir.fdir_vsi;
2699
2700 #ifdef RTE_LIBRTE_XEN_DOM0
2701         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2702 #else
2703         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2704 #endif
2705         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2706         /*
2707          * don't need to allocate software ring and reset for the fdir
2708          * program queue just set the queue has been configured.
2709          */
2710         txq->q_set = TRUE;
2711         pf->fdir.txq = txq;
2712
2713         return I40E_SUCCESS;
2714 }
2715
2716 enum i40e_status_code
2717 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2718 {
2719         struct i40e_rx_queue *rxq;
2720         const struct rte_memzone *rz = NULL;
2721         uint32_t ring_size;
2722         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2723
2724         if (!pf) {
2725                 PMD_DRV_LOG(ERR, "PF is not available");
2726                 return I40E_ERR_BAD_PTR;
2727         }
2728
2729         /* Allocate the RX queue data structure. */
2730         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2731                                   sizeof(struct i40e_rx_queue),
2732                                   RTE_CACHE_LINE_SIZE,
2733                                   SOCKET_ID_ANY);
2734         if (!rxq) {
2735                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2736                                         "rx queue structure.");
2737                 return I40E_ERR_NO_MEMORY;
2738         }
2739
2740         /* Allocate RX hardware ring descriptors. */
2741         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2742         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2743
2744         rz = i40e_ring_dma_zone_reserve(dev,
2745                                         "fdir_rx_ring",
2746                                         I40E_FDIR_QUEUE_ID,
2747                                         ring_size,
2748                                         SOCKET_ID_ANY);
2749         if (!rz) {
2750                 i40e_dev_rx_queue_release(rxq);
2751                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2752                 return I40E_ERR_NO_MEMORY;
2753         }
2754
2755         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2756         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2757         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2758         rxq->vsi = pf->fdir.fdir_vsi;
2759
2760 #ifdef RTE_LIBRTE_XEN_DOM0
2761         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2762 #else
2763         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2764 #endif
2765         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2766
2767         /*
2768          * Don't need to allocate software ring and reset for the fdir
2769          * rx queue, just set the queue has been configured.
2770          */
2771         rxq->q_set = TRUE;
2772         pf->fdir.rxq = rxq;
2773
2774         return I40E_SUCCESS;
2775 }