drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2016 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53 #include <rte_ip.h>
  54 #include <rte_net.h>
  55
  56 #include "i40e_logs.h"
  57 #include "base/i40e_prototype.h"
  58 #include "base/i40e_type.h"
  59 #include "i40e_ethdev.h"
  60 #include "i40e_rxtx.h"
  61
  62 #define DEFAULT_TX_RS_THRESH   32
  63 #define DEFAULT_TX_FREE_THRESH 32
  64
  65 #define I40E_TX_MAX_BURST  32
  66
  67 #define I40E_DMA_MEM_ALIGN 4096
  68
  69 /* Base address of the HW descriptor ring should be 128B aligned. */
  70 #define I40E_RING_BASE_ALIGN    128
  71
  72 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  73                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  74
  75 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  76
  77 #ifdef RTE_LIBRTE_IEEE1588
  78 #define I40E_TX_IEEE1588_TMST PKT_TX_IEEE1588_TMST
  79 #else
  80 #define I40E_TX_IEEE1588_TMST 0
  81 #endif
  82
  83 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  84                 PKT_TX_IP_CKSUM |                \
  85                 PKT_TX_L4_MASK |                 \
  86                 PKT_TX_TCP_SEG |                 \
  87                 PKT_TX_OUTER_IP_CKSUM)
  88
  89 #define I40E_TX_OFFLOAD_MASK (  \
  90                 PKT_TX_IP_CKSUM |       \
  91                 PKT_TX_L4_MASK |        \
  92                 PKT_TX_OUTER_IP_CKSUM | \
  93                 PKT_TX_TCP_SEG |        \
  94                 PKT_TX_QINQ_PKT |       \
  95                 PKT_TX_VLAN_PKT |       \
  96                 PKT_TX_TUNNEL_MASK |    \
  97                 I40E_TX_IEEE1588_TMST)
  98
  99 #define I40E_TX_OFFLOAD_NOTSUP_MASK \
 100                 (PKT_TX_OFFLOAD_MASK ^ I40E_TX_OFFLOAD_MASK)
 101
 102 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
 103                                       struct rte_mbuf **tx_pkts,
 104                                       uint16_t nb_pkts);
 105
 106 static inline void
 107 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
 108 {
 109         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 110                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 111                 mb->ol_flags |= PKT_RX_VLAN_PKT | PKT_RX_VLAN_STRIPPED;
 112                 mb->vlan_tci =
 113                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 114                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 115                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 116         } else {
 117                 mb->vlan_tci = 0;
 118         }
 119 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 120         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 121                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 122                 mb->ol_flags |= PKT_RX_QINQ_STRIPPED;
 123                 mb->vlan_tci_outer = mb->vlan_tci;
 124                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 125                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 126                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 127                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 128         } else {
 129                 mb->vlan_tci_outer = 0;
 130         }
 131 #endif
 132         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 133                    mb->vlan_tci, mb->vlan_tci_outer);
 134 }
 135
 136 /* Translate the rx descriptor status to pkt flags */
 137 static inline uint64_t
 138 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 139 {
 140         uint64_t flags;
 141
 142         /* Check if RSS_HASH */
 143         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 144                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 145                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 146
 147         /* Check if FDIR Match */
 148         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 149                                                         PKT_RX_FDIR : 0);
 150
 151         return flags;
 152 }
 153
 154 static inline uint64_t
 155 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 156 {
 157         uint64_t flags = 0;
 158         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 159
 160 #define I40E_RX_ERR_BITS 0x3f
 161         if (likely((error_bits & I40E_RX_ERR_BITS) == 0)) {
 162                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 163                 return flags;
 164         }
 165
 166         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 167                 flags |= PKT_RX_IP_CKSUM_BAD;
 168         else
 169                 flags |= PKT_RX_IP_CKSUM_GOOD;
 170
 171         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 172                 flags |= PKT_RX_L4_CKSUM_BAD;
 173         else
 174                 flags |= PKT_RX_L4_CKSUM_GOOD;
 175
 176         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 177                 flags |= PKT_RX_EIP_CKSUM_BAD;
 178
 179         return flags;
 180 }
 181
 182 /* Function to check and set the ieee1588 timesync index and get the
 183  * appropriate flags.
 184  */
 185 #ifdef RTE_LIBRTE_IEEE1588
 186 static inline uint64_t
 187 i40e_get_iee15888_flags(struct rte_mbuf *mb, uint64_t qword)
 188 {
 189         uint64_t pkt_flags = 0;
 190         uint16_t tsyn = (qword & (I40E_RXD_QW1_STATUS_TSYNVALID_MASK
 191                                   | I40E_RXD_QW1_STATUS_TSYNINDX_MASK))
 192                                     >> I40E_RX_DESC_STATUS_TSYNINDX_SHIFT;
 193
 194         if ((mb->packet_type & RTE_PTYPE_L2_MASK)
 195                         == RTE_PTYPE_L2_ETHER_TIMESYNC)
 196                 pkt_flags = PKT_RX_IEEE1588_PTP;
 197         if (tsyn & 0x04) {
 198                 pkt_flags |= PKT_RX_IEEE1588_TMST;
 199                 mb->timesync = tsyn & 0x03;
 200         }
 201
 202         return pkt_flags;
 203 }
 204 #endif
 205
 206 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 207 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 208 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 209 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 210 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 211
 212 static inline uint64_t
 213 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 214 {
 215         uint64_t flags = 0;
 216 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 217         uint16_t flexbh, flexbl;
 218
 219         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 220                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 221                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 222         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 223                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 224                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 225
 226
 227         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 228                 mb->hash.fdir.hi =
 229                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 230                 flags |= PKT_RX_FDIR_ID;
 231         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 232                 mb->hash.fdir.hi =
 233                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 234                 flags |= PKT_RX_FDIR_FLX;
 235         }
 236         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 237                 mb->hash.fdir.lo =
 238                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 239                 flags |= PKT_RX_FDIR_FLX;
 240         }
 241 #else
 242         mb->hash.fdir.hi =
 243                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 244         flags |= PKT_RX_FDIR_ID;
 245 #endif
 246         return flags;
 247 }
 248
 249 static inline void
 250 i40e_parse_tunneling_params(uint64_t ol_flags,
 251                             union i40e_tx_offload tx_offload,
 252                             uint32_t *cd_tunneling)
 253 {
 254         /* EIPT: External (outer) IP header type */
 255         if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 256                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 257         else if (ol_flags & PKT_TX_OUTER_IPV4)
 258                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 259         else if (ol_flags & PKT_TX_OUTER_IPV6)
 260                 *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 261
 262         /* EIPLEN: External (outer) IP header length, in DWords */
 263         *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 264                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT;
 265
 266         /* L4TUNT: L4 Tunneling Type */
 267         switch (ol_flags & PKT_TX_TUNNEL_MASK) {
 268         case PKT_TX_TUNNEL_IPIP:
 269                 /* for non UDP / GRE tunneling, set to 00b */
 270                 break;
 271         case PKT_TX_TUNNEL_VXLAN:
 272         case PKT_TX_TUNNEL_GENEVE:
 273                 *cd_tunneling |= I40E_TXD_CTX_UDP_TUNNELING;
 274                 break;
 275         case PKT_TX_TUNNEL_GRE:
 276                 *cd_tunneling |= I40E_TXD_CTX_GRE_TUNNELING;
 277                 break;
 278         default:
 279                 PMD_TX_LOG(ERR, "Tunnel type not supported");
 280                 return;
 281         }
 282
 283         /* L4TUNLEN: L4 Tunneling Length, in Words
 284          *
 285          * We depend on app to set rte_mbuf.l2_len correctly.
 286          * For IP in GRE it should be set to the length of the GRE
 287          * header;
 288          * for MAC in GRE or MAC in UDP it should be set to the length
 289          * of the GRE or UDP headers plus the inner MAC up to including
 290          * its last Ethertype.
 291          */
 292         *cd_tunneling |= (tx_offload.l2_len >> 1) <<
 293                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 294 }
 295
 296 static inline void
 297 i40e_txd_enable_checksum(uint64_t ol_flags,
 298                         uint32_t *td_cmd,
 299                         uint32_t *td_offset,
 300                         union i40e_tx_offload tx_offload)
 301 {
 302         /* Set MACLEN */
 303         if (ol_flags & PKT_TX_TUNNEL_MASK)
 304                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 305                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 306         else
 307                 *td_offset |= (tx_offload.l2_len >> 1)
 308                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 309
 310         /* Enable L3 checksum offloads */
 311         if (ol_flags & PKT_TX_IP_CKSUM) {
 312                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 313                 *td_offset |= (tx_offload.l3_len >> 2)
 314                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 315         } else if (ol_flags & PKT_TX_IPV4) {
 316                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 317                 *td_offset |= (tx_offload.l3_len >> 2)
 318                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 319         } else if (ol_flags & PKT_TX_IPV6) {
 320                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 321                 *td_offset |= (tx_offload.l3_len >> 2)
 322                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 323         }
 324
 325         if (ol_flags & PKT_TX_TCP_SEG) {
 326                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 327                 *td_offset |= (tx_offload.l4_len >> 2)
 328                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 329                 return;
 330         }
 331
 332         /* Enable L4 checksum offloads */
 333         switch (ol_flags & PKT_TX_L4_MASK) {
 334         case PKT_TX_TCP_CKSUM:
 335                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 336                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 337                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 338                 break;
 339         case PKT_TX_SCTP_CKSUM:
 340                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 341                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 342                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 343                 break;
 344         case PKT_TX_UDP_CKSUM:
 345                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 346                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 347                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 348                 break;
 349         default:
 350                 break;
 351         }
 352 }
 353
 354 /* Construct the tx flags */
 355 static inline uint64_t
 356 i40e_build_ctob(uint32_t td_cmd,
 357                 uint32_t td_offset,
 358                 unsigned int size,
 359                 uint32_t td_tag)
 360 {
 361         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 362                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 363                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 364                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 365                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 366 }
 367
 368 static inline int
 369 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 370 {
 371         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 372         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 373         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 374         uint16_t nb_tx_desc = txq->nb_tx_desc;
 375         uint16_t desc_to_clean_to;
 376         uint16_t nb_tx_to_clean;
 377
 378         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 379         if (desc_to_clean_to >= nb_tx_desc)
 380                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 381
 382         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 383         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
 384                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
 385                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)) {
 386                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 387                         "(port=%d queue=%d)", desc_to_clean_to,
 388                                 txq->port_id, txq->queue_id);
 389                 return -1;
 390         }
 391
 392         if (last_desc_cleaned > desc_to_clean_to)
 393                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 394                                                         desc_to_clean_to);
 395         else
 396                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 397                                         last_desc_cleaned);
 398
 399         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 400
 401         txq->last_desc_cleaned = desc_to_clean_to;
 402         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 403
 404         return 0;
 405 }
 406
 407 static inline int
 408 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 409 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 410 #else
 411 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 412 #endif
 413 {
 414         int ret = 0;
 415
 416 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 417         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 418                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 419                              "rxq->rx_free_thresh=%d, "
 420                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 421                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 422                 ret = -EINVAL;
 423         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 424                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 425                              "rxq->rx_free_thresh=%d, "
 426                              "rxq->nb_rx_desc=%d",
 427                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 428                 ret = -EINVAL;
 429         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 430                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 431                              "rxq->nb_rx_desc=%d, "
 432                              "rxq->rx_free_thresh=%d",
 433                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 434                 ret = -EINVAL;
 435         }
 436 #else
 437         ret = -EINVAL;
 438 #endif
 439
 440         return ret;
 441 }
 442
 443 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 444 #define I40E_LOOK_AHEAD 8
 445 #if (I40E_LOOK_AHEAD != 8)
 446 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 447 #endif
 448 static inline int
 449 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 450 {
 451         volatile union i40e_rx_desc *rxdp;
 452         struct i40e_rx_entry *rxep;
 453         struct rte_mbuf *mb;
 454         uint16_t pkt_len;
 455         uint64_t qword1;
 456         uint32_t rx_status;
 457         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 458         int32_t i, j, nb_rx = 0;
 459         uint64_t pkt_flags;
 460         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 461
 462         rxdp = &rxq->rx_ring[rxq->rx_tail];
 463         rxep = &rxq->sw_ring[rxq->rx_tail];
 464
 465         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 466         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 467                                 I40E_RXD_QW1_STATUS_SHIFT;
 468
 469         /* Make sure there is at least 1 packet to receive */
 470         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 471                 return 0;
 472
 473         /**
 474          * Scan LOOK_AHEAD descriptors at a time to determine which
 475          * descriptors reference packets that are ready to be received.
 476          */
 477         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 478                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 479                 /* Read desc statuses backwards to avoid race condition */
 480                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 481                         qword1 = rte_le_to_cpu_64(\
 482                                 rxdp[j].wb.qword1.status_error_len);
 483                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 484                                         I40E_RXD_QW1_STATUS_SHIFT;
 485                 }
 486
 487                 rte_smp_rmb();
 488
 489                 /* Compute how many status bits were set */
 490                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 491                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 492
 493                 nb_rx += nb_dd;
 494
 495                 /* Translate descriptor info to mbuf parameters */
 496                 for (j = 0; j < nb_dd; j++) {
 497                         mb = rxep[j].mbuf;
 498                         qword1 = rte_le_to_cpu_64(\
 499                                 rxdp[j].wb.qword1.status_error_len);
 500                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 501                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 502                         mb->data_len = pkt_len;
 503                         mb->pkt_len = pkt_len;
 504                         mb->ol_flags = 0;
 505                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 506                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 507                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 508                         mb->packet_type =
 509                                 ptype_tbl[(uint8_t)((qword1 &
 510                                 I40E_RXD_QW1_PTYPE_MASK) >>
 511                                 I40E_RXD_QW1_PTYPE_SHIFT)];
 512                         if (pkt_flags & PKT_RX_RSS_HASH)
 513                                 mb->hash.rss = rte_le_to_cpu_32(\
 514                                         rxdp[j].wb.qword0.hi_dword.rss);
 515                         if (pkt_flags & PKT_RX_FDIR)
 516                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 517
 518 #ifdef RTE_LIBRTE_IEEE1588
 519                         pkt_flags |= i40e_get_iee15888_flags(mb, qword1);
 520 #endif
 521                         mb->ol_flags |= pkt_flags;
 522
 523                 }
 524
 525                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 526                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 527
 528                 if (nb_dd != I40E_LOOK_AHEAD)
 529                         break;
 530         }
 531
 532         /* Clear software ring entries */
 533         for (i = 0; i < nb_rx; i++)
 534                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 535
 536         return nb_rx;
 537 }
 538
 539 static inline uint16_t
 540 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 541                         struct rte_mbuf **rx_pkts,
 542                         uint16_t nb_pkts)
 543 {
 544         uint16_t i;
 545         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 546
 547         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 548
 549         for (i = 0; i < nb_pkts; i++)
 550                 rx_pkts[i] = stage[i];
 551
 552         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 553         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 554
 555         return nb_pkts;
 556 }
 557
 558 static inline int
 559 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 560 {
 561         volatile union i40e_rx_desc *rxdp;
 562         struct i40e_rx_entry *rxep;
 563         struct rte_mbuf *mb;
 564         uint16_t alloc_idx, i;
 565         uint64_t dma_addr;
 566         int diag;
 567
 568         /* Allocate buffers in bulk */
 569         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 570                                 (rxq->rx_free_thresh - 1));
 571         rxep = &(rxq->sw_ring[alloc_idx]);
 572         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 573                                         rxq->rx_free_thresh);
 574         if (unlikely(diag != 0)) {
 575                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 576                 return -ENOMEM;
 577         }
 578
 579         rxdp = &rxq->rx_ring[alloc_idx];
 580         for (i = 0; i < rxq->rx_free_thresh; i++) {
 581                 if (likely(i < (rxq->rx_free_thresh - 1)))
 582                         /* Prefetch next mbuf */
 583                         rte_prefetch0(rxep[i + 1].mbuf);
 584
 585                 mb = rxep[i].mbuf;
 586                 rte_mbuf_refcnt_set(mb, 1);
 587                 mb->next = NULL;
 588                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 589                 mb->nb_segs = 1;
 590                 mb->port = rxq->port_id;
 591                 dma_addr = rte_cpu_to_le_64(\
 592                         rte_mbuf_data_dma_addr_default(mb));
 593                 rxdp[i].read.hdr_addr = 0;
 594                 rxdp[i].read.pkt_addr = dma_addr;
 595         }
 596
 597         /* Update rx tail regsiter */
 598         rte_wmb();
 599         I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
 600
 601         rxq->rx_free_trigger =
 602                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 603         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 604                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 605
 606         return 0;
 607 }
 608
 609 static inline uint16_t
 610 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 611 {
 612         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 613         uint16_t nb_rx = 0;
 614
 615         if (!nb_pkts)
 616                 return 0;
 617
 618         if (rxq->rx_nb_avail)
 619                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 620
 621         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 622         rxq->rx_next_avail = 0;
 623         rxq->rx_nb_avail = nb_rx;
 624         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 625
 626         if (rxq->rx_tail > rxq->rx_free_trigger) {
 627                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 628                         uint16_t i, j;
 629
 630                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 631                                    "port_id=%u, queue_id=%u",
 632                                    rxq->port_id, rxq->queue_id);
 633                         rxq->rx_nb_avail = 0;
 634                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 635                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 636                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 637
 638                         return 0;
 639                 }
 640         }
 641
 642         if (rxq->rx_tail >= rxq->nb_rx_desc)
 643                 rxq->rx_tail = 0;
 644
 645         if (rxq->rx_nb_avail)
 646                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 647
 648         return 0;
 649 }
 650
 651 static uint16_t
 652 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 653                           struct rte_mbuf **rx_pkts,
 654                           uint16_t nb_pkts)
 655 {
 656         uint16_t nb_rx = 0, n, count;
 657
 658         if (unlikely(nb_pkts == 0))
 659                 return 0;
 660
 661         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 662                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 663
 664         while (nb_pkts) {
 665                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 666                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 667                 nb_rx = (uint16_t)(nb_rx + count);
 668                 nb_pkts = (uint16_t)(nb_pkts - count);
 669                 if (count < n)
 670                         break;
 671         }
 672
 673         return nb_rx;
 674 }
 675 #else
 676 static uint16_t
 677 i40e_recv_pkts_bulk_alloc(void __rte_unused *rx_queue,
 678                           struct rte_mbuf __rte_unused **rx_pkts,
 679                           uint16_t __rte_unused nb_pkts)
 680 {
 681         return 0;
 682 }
 683 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 684
 685 uint16_t
 686 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 687 {
 688         struct i40e_rx_queue *rxq;
 689         volatile union i40e_rx_desc *rx_ring;
 690         volatile union i40e_rx_desc *rxdp;
 691         union i40e_rx_desc rxd;
 692         struct i40e_rx_entry *sw_ring;
 693         struct i40e_rx_entry *rxe;
 694         struct rte_mbuf *rxm;
 695         struct rte_mbuf *nmb;
 696         uint16_t nb_rx;
 697         uint32_t rx_status;
 698         uint64_t qword1;
 699         uint16_t rx_packet_len;
 700         uint16_t rx_id, nb_hold;
 701         uint64_t dma_addr;
 702         uint64_t pkt_flags;
 703         uint32_t *ptype_tbl;
 704
 705         nb_rx = 0;
 706         nb_hold = 0;
 707         rxq = rx_queue;
 708         rx_id = rxq->rx_tail;
 709         rx_ring = rxq->rx_ring;
 710         sw_ring = rxq->sw_ring;
 711         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 712
 713         while (nb_rx < nb_pkts) {
 714                 rxdp = &rx_ring[rx_id];
 715                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 716                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 717                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 718
 719                 /* Check the DD bit first */
 720                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 721                         break;
 722
 723                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 724                 if (unlikely(!nmb))
 725                         break;
 726                 rxd = *rxdp;
 727
 728                 nb_hold++;
 729                 rxe = &sw_ring[rx_id];
 730                 rx_id++;
 731                 if (unlikely(rx_id == rxq->nb_rx_desc))
 732                         rx_id = 0;
 733
 734                 /* Prefetch next mbuf */
 735                 rte_prefetch0(sw_ring[rx_id].mbuf);
 736
 737                 /**
 738                  * When next RX descriptor is on a cache line boundary,
 739                  * prefetch the next 4 RX descriptors and next 8 pointers
 740                  * to mbufs.
 741                  */
 742                 if ((rx_id & 0x3) == 0) {
 743                         rte_prefetch0(&rx_ring[rx_id]);
 744                         rte_prefetch0(&sw_ring[rx_id]);
 745                 }
 746                 rxm = rxe->mbuf;
 747                 rxe->mbuf = nmb;
 748                 dma_addr =
 749                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 750                 rxdp->read.hdr_addr = 0;
 751                 rxdp->read.pkt_addr = dma_addr;
 752
 753                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 754                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 755
 756                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 757                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 758                 rxm->nb_segs = 1;
 759                 rxm->next = NULL;
 760                 rxm->pkt_len = rx_packet_len;
 761                 rxm->data_len = rx_packet_len;
 762                 rxm->port = rxq->port_id;
 763                 rxm->ol_flags = 0;
 764                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 765                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 766                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 767                 rxm->packet_type =
 768                         ptype_tbl[(uint8_t)((qword1 &
 769                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 770                 if (pkt_flags & PKT_RX_RSS_HASH)
 771                         rxm->hash.rss =
 772                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 773                 if (pkt_flags & PKT_RX_FDIR)
 774                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 775
 776 #ifdef RTE_LIBRTE_IEEE1588
 777                 pkt_flags |= i40e_get_iee15888_flags(rxm, qword1);
 778 #endif
 779                 rxm->ol_flags |= pkt_flags;
 780
 781                 rx_pkts[nb_rx++] = rxm;
 782         }
 783         rxq->rx_tail = rx_id;
 784
 785         /**
 786          * If the number of free RX descriptors is greater than the RX free
 787          * threshold of the queue, advance the receive tail register of queue.
 788          * Update that register with the value of the last processed RX
 789          * descriptor minus 1.
 790          */
 791         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 792         if (nb_hold > rxq->rx_free_thresh) {
 793                 rx_id = (uint16_t) ((rx_id == 0) ?
 794                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 795                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 796                 nb_hold = 0;
 797         }
 798         rxq->nb_rx_hold = nb_hold;
 799
 800         return nb_rx;
 801 }
 802
 803 uint16_t
 804 i40e_recv_scattered_pkts(void *rx_queue,
 805                          struct rte_mbuf **rx_pkts,
 806                          uint16_t nb_pkts)
 807 {
 808         struct i40e_rx_queue *rxq = rx_queue;
 809         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 810         volatile union i40e_rx_desc *rxdp;
 811         union i40e_rx_desc rxd;
 812         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 813         struct i40e_rx_entry *rxe;
 814         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 815         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
 816         struct rte_mbuf *nmb, *rxm;
 817         uint16_t rx_id = rxq->rx_tail;
 818         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
 819         uint32_t rx_status;
 820         uint64_t qword1;
 821         uint64_t dma_addr;
 822         uint64_t pkt_flags;
 823         uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 824
 825         while (nb_rx < nb_pkts) {
 826                 rxdp = &rx_ring[rx_id];
 827                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 828                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 829                                         I40E_RXD_QW1_STATUS_SHIFT;
 830
 831                 /* Check the DD bit */
 832                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 833                         break;
 834
 835                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 836                 if (unlikely(!nmb))
 837                         break;
 838                 rxd = *rxdp;
 839                 nb_hold++;
 840                 rxe = &sw_ring[rx_id];
 841                 rx_id++;
 842                 if (rx_id == rxq->nb_rx_desc)
 843                         rx_id = 0;
 844
 845                 /* Prefetch next mbuf */
 846                 rte_prefetch0(sw_ring[rx_id].mbuf);
 847
 848                 /**
 849                  * When next RX descriptor is on a cache line boundary,
 850                  * prefetch the next 4 RX descriptors and next 8 pointers
 851                  * to mbufs.
 852                  */
 853                 if ((rx_id & 0x3) == 0) {
 854                         rte_prefetch0(&rx_ring[rx_id]);
 855                         rte_prefetch0(&sw_ring[rx_id]);
 856                 }
 857
 858                 rxm = rxe->mbuf;
 859                 rxe->mbuf = nmb;
 860                 dma_addr =
 861                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(nmb));
 862
 863                 /* Set data buffer address and data length of the mbuf */
 864                 rxdp->read.hdr_addr = 0;
 865                 rxdp->read.pkt_addr = dma_addr;
 866                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 867                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
 868                 rxm->data_len = rx_packet_len;
 869                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 870
 871                 /**
 872                  * If this is the first buffer of the received packet, set the
 873                  * pointer to the first mbuf of the packet and initialize its
 874                  * context. Otherwise, update the total length and the number
 875                  * of segments of the current scattered packet, and update the
 876                  * pointer to the last mbuf of the current packet.
 877                  */
 878                 if (!first_seg) {
 879                         first_seg = rxm;
 880                         first_seg->nb_segs = 1;
 881                         first_seg->pkt_len = rx_packet_len;
 882                 } else {
 883                         first_seg->pkt_len =
 884                                 (uint16_t)(first_seg->pkt_len +
 885                                                 rx_packet_len);
 886                         first_seg->nb_segs++;
 887                         last_seg->next = rxm;
 888                 }
 889
 890                 /**
 891                  * If this is not the last buffer of the received packet,
 892                  * update the pointer to the last mbuf of the current scattered
 893                  * packet and continue to parse the RX ring.
 894                  */
 895                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
 896                         last_seg = rxm;
 897                         continue;
 898                 }
 899
 900                 /**
 901                  * This is the last buffer of the received packet. If the CRC
 902                  * is not stripped by the hardware:
 903                  *  - Subtract the CRC length from the total packet length.
 904                  *  - If the last buffer only contains the whole CRC or a part
 905                  *  of it, free the mbuf associated to the last buffer. If part
 906                  *  of the CRC is also contained in the previous mbuf, subtract
 907                  *  the length of that CRC part from the data length of the
 908                  *  previous mbuf.
 909                  */
 910                 rxm->next = NULL;
 911                 if (unlikely(rxq->crc_len > 0)) {
 912                         first_seg->pkt_len -= ETHER_CRC_LEN;
 913                         if (rx_packet_len <= ETHER_CRC_LEN) {
 914                                 rte_pktmbuf_free_seg(rxm);
 915                                 first_seg->nb_segs--;
 916                                 last_seg->data_len =
 917                                         (uint16_t)(last_seg->data_len -
 918                                         (ETHER_CRC_LEN - rx_packet_len));
 919                                 last_seg->next = NULL;
 920                         } else
 921                                 rxm->data_len = (uint16_t)(rx_packet_len -
 922                                                                 ETHER_CRC_LEN);
 923                 }
 924
 925                 first_seg->port = rxq->port_id;
 926                 first_seg->ol_flags = 0;
 927                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
 928                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 929                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 930                 first_seg->packet_type =
 931                         ptype_tbl[(uint8_t)((qword1 &
 932                         I40E_RXD_QW1_PTYPE_MASK) >> I40E_RXD_QW1_PTYPE_SHIFT)];
 933                 if (pkt_flags & PKT_RX_RSS_HASH)
 934                         first_seg->hash.rss =
 935                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 936                 if (pkt_flags & PKT_RX_FDIR)
 937                         pkt_flags |= i40e_rxd_build_fdir(&rxd, first_seg);
 938
 939 #ifdef RTE_LIBRTE_IEEE1588
 940                 pkt_flags |= i40e_get_iee15888_flags(first_seg, qword1);
 941 #endif
 942                 first_seg->ol_flags |= pkt_flags;
 943
 944                 /* Prefetch data of first segment, if configured to do so. */
 945                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
 946                         first_seg->data_off));
 947                 rx_pkts[nb_rx++] = first_seg;
 948                 first_seg = NULL;
 949         }
 950
 951         /* Record index of the next RX descriptor to probe. */
 952         rxq->rx_tail = rx_id;
 953         rxq->pkt_first_seg = first_seg;
 954         rxq->pkt_last_seg = last_seg;
 955
 956         /**
 957          * If the number of free RX descriptors is greater than the RX free
 958          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 959          * register. Update the RDT with the value of the last processed RX
 960          * descriptor minus 1, to guarantee that the RDT register is never
 961          * equal to the RDH register, which creates a "full" ring situtation
 962          * from the hardware point of view.
 963          */
 964         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 965         if (nb_hold > rxq->rx_free_thresh) {
 966                 rx_id = (uint16_t)(rx_id == 0 ?
 967                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 968                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 969                 nb_hold = 0;
 970         }
 971         rxq->nb_rx_hold = nb_hold;
 972
 973         return nb_rx;
 974 }
 975
 976 /* Check if the context descriptor is needed for TX offloading */
 977 static inline uint16_t
 978 i40e_calc_context_desc(uint64_t flags)
 979 {
 980         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
 981                 PKT_TX_TCP_SEG |
 982                 PKT_TX_QINQ_PKT |
 983                 PKT_TX_TUNNEL_MASK;
 984
 985 #ifdef RTE_LIBRTE_IEEE1588
 986         mask |= PKT_TX_IEEE1588_TMST;
 987 #endif
 988
 989         return (flags & mask) ? 1 : 0;
 990 }
 991
 992 /* set i40e TSO context descriptor */
 993 static inline uint64_t
 994 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
 995 {
 996         uint64_t ctx_desc = 0;
 997         uint32_t cd_cmd, hdr_len, cd_tso_len;
 998
 999         if (!tx_offload.l4_len) {
1000                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1001                 return ctx_desc;
1002         }
1003
1004         /**
1005          * in case of non tunneling packet, the outer_l2_len and
1006          * outer_l3_len must be 0.
1007          */
1008         hdr_len = tx_offload.outer_l2_len +
1009                 tx_offload.outer_l3_len +
1010                 tx_offload.l2_len +
1011                 tx_offload.l3_len +
1012                 tx_offload.l4_len;
1013
1014         cd_cmd = I40E_TX_CTX_DESC_TSO;
1015         cd_tso_len = mbuf->pkt_len - hdr_len;
1016         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1017                 ((uint64_t)cd_tso_len <<
1018                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1019                 ((uint64_t)mbuf->tso_segsz <<
1020                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1021
1022         return ctx_desc;
1023 }
1024
1025 uint16_t
1026 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1027 {
1028         struct i40e_tx_queue *txq;
1029         struct i40e_tx_entry *sw_ring;
1030         struct i40e_tx_entry *txe, *txn;
1031         volatile struct i40e_tx_desc *txd;
1032         volatile struct i40e_tx_desc *txr;
1033         struct rte_mbuf *tx_pkt;
1034         struct rte_mbuf *m_seg;
1035         uint32_t cd_tunneling_params;
1036         uint16_t tx_id;
1037         uint16_t nb_tx;
1038         uint32_t td_cmd;
1039         uint32_t td_offset;
1040         uint32_t td_tag;
1041         uint64_t ol_flags;
1042         uint16_t nb_used;
1043         uint16_t nb_ctx;
1044         uint16_t tx_last;
1045         uint16_t slen;
1046         uint64_t buf_dma_addr;
1047         union i40e_tx_offload tx_offload = {0};
1048
1049         txq = tx_queue;
1050         sw_ring = txq->sw_ring;
1051         txr = txq->tx_ring;
1052         tx_id = txq->tx_tail;
1053         txe = &sw_ring[tx_id];
1054
1055         /* Check if the descriptor ring needs to be cleaned. */
1056         if (txq->nb_tx_free < txq->tx_free_thresh)
1057                 i40e_xmit_cleanup(txq);
1058
1059         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1060                 td_cmd = 0;
1061                 td_tag = 0;
1062                 td_offset = 0;
1063
1064                 tx_pkt = *tx_pkts++;
1065                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1066
1067                 ol_flags = tx_pkt->ol_flags;
1068                 tx_offload.l2_len = tx_pkt->l2_len;
1069                 tx_offload.l3_len = tx_pkt->l3_len;
1070                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1071                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1072                 tx_offload.l4_len = tx_pkt->l4_len;
1073                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1074
1075                 /* Calculate the number of context descriptors needed. */
1076                 nb_ctx = i40e_calc_context_desc(ol_flags);
1077
1078                 /**
1079                  * The number of descriptors that must be allocated for
1080                  * a packet equals to the number of the segments of that
1081                  * packet plus 1 context descriptor if needed.
1082                  */
1083                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1084                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1085
1086                 /* Circular ring */
1087                 if (tx_last >= txq->nb_tx_desc)
1088                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1089
1090                 if (nb_used > txq->nb_tx_free) {
1091                         if (i40e_xmit_cleanup(txq) != 0) {
1092                                 if (nb_tx == 0)
1093                                         return 0;
1094                                 goto end_of_tx;
1095                         }
1096                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1097                                 while (nb_used > txq->nb_tx_free) {
1098                                         if (i40e_xmit_cleanup(txq) != 0) {
1099                                                 if (nb_tx == 0)
1100                                                         return 0;
1101                                                 goto end_of_tx;
1102                                         }
1103                                 }
1104                         }
1105                 }
1106
1107                 /* Descriptor based VLAN insertion */
1108                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1109                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1110                         td_tag = tx_pkt->vlan_tci;
1111                 }
1112
1113                 /* Always enable CRC offload insertion */
1114                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1115
1116                 /* Fill in tunneling parameters if necessary */
1117                 cd_tunneling_params = 0;
1118                 if (ol_flags & PKT_TX_TUNNEL_MASK)
1119                         i40e_parse_tunneling_params(ol_flags, tx_offload,
1120                                                     &cd_tunneling_params);
1121                 /* Enable checksum offloading */
1122                 if (ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)
1123                         i40e_txd_enable_checksum(ol_flags, &td_cmd,
1124                                                  &td_offset, tx_offload);
1125
1126                 if (nb_ctx) {
1127                         /* Setup TX context descriptor if required */
1128                         volatile struct i40e_tx_context_desc *ctx_txd =
1129                                 (volatile struct i40e_tx_context_desc *)\
1130                                                         &txr[tx_id];
1131                         uint16_t cd_l2tag2 = 0;
1132                         uint64_t cd_type_cmd_tso_mss =
1133                                 I40E_TX_DESC_DTYPE_CONTEXT;
1134
1135                         txn = &sw_ring[txe->next_id];
1136                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1137                         if (txe->mbuf != NULL) {
1138                                 rte_pktmbuf_free_seg(txe->mbuf);
1139                                 txe->mbuf = NULL;
1140                         }
1141
1142                         /* TSO enabled means no timestamp */
1143                         if (ol_flags & PKT_TX_TCP_SEG)
1144                                 cd_type_cmd_tso_mss |=
1145                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1146                         else {
1147 #ifdef RTE_LIBRTE_IEEE1588
1148                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1149                                         cd_type_cmd_tso_mss |=
1150                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1151                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1152 #endif
1153                         }
1154
1155                         ctx_txd->tunneling_params =
1156                                 rte_cpu_to_le_32(cd_tunneling_params);
1157                         if (ol_flags & PKT_TX_QINQ_PKT) {
1158                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1159                                 cd_type_cmd_tso_mss |=
1160                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1161                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1162                         }
1163                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1164                         ctx_txd->type_cmd_tso_mss =
1165                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1166
1167                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1168                                 "tunneling_params: %#x;\n"
1169                                 "l2tag2: %#hx;\n"
1170                                 "rsvd: %#hx;\n"
1171                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1172                                 tx_pkt, tx_id,
1173                                 ctx_txd->tunneling_params,
1174                                 ctx_txd->l2tag2,
1175                                 ctx_txd->rsvd,
1176                                 ctx_txd->type_cmd_tso_mss);
1177
1178                         txe->last_id = tx_last;
1179                         tx_id = txe->next_id;
1180                         txe = txn;
1181                 }
1182
1183                 m_seg = tx_pkt;
1184                 do {
1185                         txd = &txr[tx_id];
1186                         txn = &sw_ring[txe->next_id];
1187
1188                         if (txe->mbuf)
1189                                 rte_pktmbuf_free_seg(txe->mbuf);
1190                         txe->mbuf = m_seg;
1191
1192                         /* Setup TX Descriptor */
1193                         slen = m_seg->data_len;
1194                         buf_dma_addr = rte_mbuf_data_dma_addr(m_seg);
1195
1196                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1197                                 "buf_dma_addr: %#"PRIx64";\n"
1198                                 "td_cmd: %#x;\n"
1199                                 "td_offset: %#x;\n"
1200                                 "td_len: %u;\n"
1201                                 "td_tag: %#x;\n",
1202                                 tx_pkt, tx_id, buf_dma_addr,
1203                                 td_cmd, td_offset, slen, td_tag);
1204
1205                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1206                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1207                                                 td_offset, slen, td_tag);
1208                         txe->last_id = tx_last;
1209                         tx_id = txe->next_id;
1210                         txe = txn;
1211                         m_seg = m_seg->next;
1212                 } while (m_seg != NULL);
1213
1214                 /* The last packet data descriptor needs End Of Packet (EOP) */
1215                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1216                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1217                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1218
1219                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1220                         PMD_TX_FREE_LOG(DEBUG,
1221                                         "Setting RS bit on TXD id="
1222                                         "%4u (port=%d queue=%d)",
1223                                         tx_last, txq->port_id, txq->queue_id);
1224
1225                         td_cmd |= I40E_TX_DESC_CMD_RS;
1226
1227                         /* Update txq RS bit counters */
1228                         txq->nb_tx_used = 0;
1229                 }
1230
1231                 txd->cmd_type_offset_bsz |=
1232                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1233                                         I40E_TXD_QW1_CMD_SHIFT);
1234         }
1235
1236 end_of_tx:
1237         rte_wmb();
1238
1239         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1240                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1241                    (unsigned) tx_id, (unsigned) nb_tx);
1242
1243         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
1244         txq->tx_tail = tx_id;
1245
1246         return nb_tx;
1247 }
1248
1249 static inline int __attribute__((always_inline))
1250 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1251 {
1252         struct i40e_tx_entry *txep;
1253         uint16_t i;
1254
1255         if ((txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1256                         rte_cpu_to_le_64(I40E_TXD_QW1_DTYPE_MASK)) !=
1257                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))
1258                 return 0;
1259
1260         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1261
1262         for (i = 0; i < txq->tx_rs_thresh; i++)
1263                 rte_prefetch0((txep + i)->mbuf);
1264
1265         if (txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT) {
1266                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1267                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1268                         txep->mbuf = NULL;
1269                 }
1270         } else {
1271                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1272                         rte_pktmbuf_free_seg(txep->mbuf);
1273                         txep->mbuf = NULL;
1274                 }
1275         }
1276
1277         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1278         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1279         if (txq->tx_next_dd >= txq->nb_tx_desc)
1280                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1281
1282         return txq->tx_rs_thresh;
1283 }
1284
1285 /* Populate 4 descriptors with data from 4 mbufs */
1286 static inline void
1287 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1288 {
1289         uint64_t dma_addr;
1290         uint32_t i;
1291
1292         for (i = 0; i < 4; i++, txdp++, pkts++) {
1293                 dma_addr = rte_mbuf_data_dma_addr(*pkts);
1294                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1295                 txdp->cmd_type_offset_bsz =
1296                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1297                                         (*pkts)->data_len, 0);
1298         }
1299 }
1300
1301 /* Populate 1 descriptor with data from 1 mbuf */
1302 static inline void
1303 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1304 {
1305         uint64_t dma_addr;
1306
1307         dma_addr = rte_mbuf_data_dma_addr(*pkts);
1308         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1309         txdp->cmd_type_offset_bsz =
1310                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1311                                 (*pkts)->data_len, 0);
1312 }
1313
1314 /* Fill hardware descriptor ring with mbuf data */
1315 static inline void
1316 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1317                      struct rte_mbuf **pkts,
1318                      uint16_t nb_pkts)
1319 {
1320         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1321         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1322         const int N_PER_LOOP = 4;
1323         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1324         int mainpart, leftover;
1325         int i, j;
1326
1327         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1328         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1329         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1330                 for (j = 0; j < N_PER_LOOP; ++j) {
1331                         (txep + i + j)->mbuf = *(pkts + i + j);
1332                 }
1333                 tx4(txdp + i, pkts + i);
1334         }
1335         if (unlikely(leftover > 0)) {
1336                 for (i = 0; i < leftover; ++i) {
1337                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1338                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1339                 }
1340         }
1341 }
1342
1343 static inline uint16_t
1344 tx_xmit_pkts(struct i40e_tx_queue *txq,
1345              struct rte_mbuf **tx_pkts,
1346              uint16_t nb_pkts)
1347 {
1348         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1349         uint16_t n = 0;
1350
1351         /**
1352          * Begin scanning the H/W ring for done descriptors when the number
1353          * of available descriptors drops below tx_free_thresh. For each done
1354          * descriptor, free the associated buffer.
1355          */
1356         if (txq->nb_tx_free < txq->tx_free_thresh)
1357                 i40e_tx_free_bufs(txq);
1358
1359         /* Use available descriptor only */
1360         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1361         if (unlikely(!nb_pkts))
1362                 return 0;
1363
1364         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1365         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1366                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1367                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1368                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1369                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1370                                                 I40E_TXD_QW1_CMD_SHIFT);
1371                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1372                 txq->tx_tail = 0;
1373         }
1374
1375         /* Fill hardware descriptor ring with mbuf data */
1376         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1377         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1378
1379         /* Determin if RS bit needs to be set */
1380         if (txq->tx_tail > txq->tx_next_rs) {
1381                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1382                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1383                                                 I40E_TXD_QW1_CMD_SHIFT);
1384                 txq->tx_next_rs =
1385                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1386                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1387                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1388         }
1389
1390         if (txq->tx_tail >= txq->nb_tx_desc)
1391                 txq->tx_tail = 0;
1392
1393         /* Update the tx tail register */
1394         rte_wmb();
1395         I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, txq->tx_tail);
1396
1397         return nb_pkts;
1398 }
1399
1400 static uint16_t
1401 i40e_xmit_pkts_simple(void *tx_queue,
1402                       struct rte_mbuf **tx_pkts,
1403                       uint16_t nb_pkts)
1404 {
1405         uint16_t nb_tx = 0;
1406
1407         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1408                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1409                                                 tx_pkts, nb_pkts);
1410
1411         while (nb_pkts) {
1412                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1413                                                 I40E_TX_MAX_BURST);
1414
1415                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1416                                                 &tx_pkts[nb_tx], num);
1417                 nb_tx = (uint16_t)(nb_tx + ret);
1418                 nb_pkts = (uint16_t)(nb_pkts - ret);
1419                 if (ret < num)
1420                         break;
1421         }
1422
1423         return nb_tx;
1424 }
1425
1426 static uint16_t
1427 i40e_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1428                    uint16_t nb_pkts)
1429 {
1430         uint16_t nb_tx = 0;
1431         struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
1432
1433         while (nb_pkts) {
1434                 uint16_t ret, num;
1435
1436                 num = (uint16_t)RTE_MIN(nb_pkts, txq->tx_rs_thresh);
1437                 ret = i40e_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx],
1438                                                 num);
1439                 nb_tx += ret;
1440                 nb_pkts -= ret;
1441                 if (ret < num)
1442                         break;
1443         }
1444
1445         return nb_tx;
1446 }
1447
1448 /*********************************************************************
1449  *
1450  *  TX prep functions
1451  *
1452  **********************************************************************/
1453 uint16_t
1454 i40e_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
1455                 uint16_t nb_pkts)
1456 {
1457         int i, ret;
1458         uint64_t ol_flags;
1459         struct rte_mbuf *m;
1460
1461         for (i = 0; i < nb_pkts; i++) {
1462                 m = tx_pkts[i];
1463                 ol_flags = m->ol_flags;
1464
1465                 /**
1466                  * m->nb_segs is uint8_t, so nb_segs is always less than
1467                  * I40E_TX_MAX_SEG.
1468                  * We check only a condition for nb_segs > I40E_TX_MAX_MTU_SEG.
1469                  */
1470                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
1471                         if (m->nb_segs > I40E_TX_MAX_MTU_SEG) {
1472                                 rte_errno = -EINVAL;
1473                                 return i;
1474                         }
1475                 } else if ((m->tso_segsz < I40E_MIN_TSO_MSS) ||
1476                                 (m->tso_segsz > I40E_MAX_TSO_MSS)) {
1477                         /* MSS outside the range (256B - 9674B) are considered
1478                          * malicious
1479                          */
1480                         rte_errno = -EINVAL;
1481                         return i;
1482                 }
1483
1484                 if (ol_flags & I40E_TX_OFFLOAD_NOTSUP_MASK) {
1485                         rte_errno = -ENOTSUP;
1486                         return i;
1487                 }
1488
1489 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
1490                 ret = rte_validate_tx_offload(m);
1491                 if (ret != 0) {
1492                         rte_errno = ret;
1493                         return i;
1494                 }
1495 #endif
1496                 ret = rte_net_intel_cksum_prepare(m);
1497                 if (ret != 0) {
1498                         rte_errno = ret;
1499                         return i;
1500                 }
1501         }
1502         return i;
1503 }
1504
1505 /*
1506  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1507  * application used, which assume having sequential ones. But from driver's
1508  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1509  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1510  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1511  * use queue_idx from 0 to 95 to access queues, while real queue would be
1512  * different. This function will do a queue mapping to find VSI the queue
1513  * belongs to.
1514  */
1515 static struct i40e_vsi*
1516 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1517 {
1518         /* the queue in MAIN VSI range */
1519         if (queue_idx < pf->main_vsi->nb_qps)
1520                 return pf->main_vsi;
1521
1522         queue_idx -= pf->main_vsi->nb_qps;
1523
1524         /* queue_idx is greater than VMDQ VSIs range */
1525         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1526                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1527                 return NULL;
1528         }
1529
1530         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1531 }
1532
1533 static uint16_t
1534 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1535 {
1536         /* the queue in MAIN VSI range */
1537         if (queue_idx < pf->main_vsi->nb_qps)
1538                 return queue_idx;
1539
1540         /* It's VMDQ queues */
1541         queue_idx -= pf->main_vsi->nb_qps;
1542
1543         if (pf->nb_cfg_vmdq_vsi)
1544                 return queue_idx % pf->vmdq_nb_qps;
1545         else {
1546                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1547                 return (uint16_t)(-1);
1548         }
1549 }
1550
1551 int
1552 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1553 {
1554         struct i40e_rx_queue *rxq;
1555         int err = -1;
1556         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1557
1558         PMD_INIT_FUNC_TRACE();
1559
1560         if (rx_queue_id < dev->data->nb_rx_queues) {
1561                 rxq = dev->data->rx_queues[rx_queue_id];
1562
1563                 err = i40e_alloc_rx_queue_mbufs(rxq);
1564                 if (err) {
1565                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1566                         return err;
1567                 }
1568
1569                 rte_wmb();
1570
1571                 /* Init the RX tail regieter. */
1572                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1573
1574                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1575
1576                 if (err) {
1577                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1578                                     rx_queue_id);
1579
1580                         i40e_rx_queue_release_mbufs(rxq);
1581                         i40e_reset_rx_queue(rxq);
1582                 } else
1583                         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1584         }
1585
1586         return err;
1587 }
1588
1589 int
1590 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1591 {
1592         struct i40e_rx_queue *rxq;
1593         int err;
1594         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1595
1596         if (rx_queue_id < dev->data->nb_rx_queues) {
1597                 rxq = dev->data->rx_queues[rx_queue_id];
1598
1599                 /*
1600                 * rx_queue_id is queue id aplication refers to, while
1601                 * rxq->reg_idx is the real queue index.
1602                 */
1603                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1604
1605                 if (err) {
1606                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1607                                     rx_queue_id);
1608                         return err;
1609                 }
1610                 i40e_rx_queue_release_mbufs(rxq);
1611                 i40e_reset_rx_queue(rxq);
1612                 dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1613         }
1614
1615         return 0;
1616 }
1617
1618 int
1619 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1620 {
1621         int err = -1;
1622         struct i40e_tx_queue *txq;
1623         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1624
1625         PMD_INIT_FUNC_TRACE();
1626
1627         if (tx_queue_id < dev->data->nb_tx_queues) {
1628                 txq = dev->data->tx_queues[tx_queue_id];
1629
1630                 /*
1631                 * tx_queue_id is queue id aplication refers to, while
1632                 * rxq->reg_idx is the real queue index.
1633                 */
1634                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1635                 if (err)
1636                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1637                                     tx_queue_id);
1638                 else
1639                         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STARTED;
1640         }
1641
1642         return err;
1643 }
1644
1645 int
1646 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1647 {
1648         struct i40e_tx_queue *txq;
1649         int err;
1650         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1651
1652         if (tx_queue_id < dev->data->nb_tx_queues) {
1653                 txq = dev->data->tx_queues[tx_queue_id];
1654
1655                 /*
1656                 * tx_queue_id is queue id aplication refers to, while
1657                 * txq->reg_idx is the real queue index.
1658                 */
1659                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1660
1661                 if (err) {
1662                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1663                                     tx_queue_id);
1664                         return err;
1665                 }
1666
1667                 i40e_tx_queue_release_mbufs(txq);
1668                 i40e_reset_tx_queue(txq);
1669                 dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
1670         }
1671
1672         return 0;
1673 }
1674
1675 const uint32_t *
1676 i40e_dev_supported_ptypes_get(struct rte_eth_dev *dev)
1677 {
1678         static const uint32_t ptypes[] = {
1679                 /* refers to i40e_rxd_pkt_type_mapping() */
1680                 RTE_PTYPE_L2_ETHER,
1681                 RTE_PTYPE_L2_ETHER_TIMESYNC,
1682                 RTE_PTYPE_L2_ETHER_LLDP,
1683                 RTE_PTYPE_L2_ETHER_ARP,
1684                 RTE_PTYPE_L3_IPV4_EXT_UNKNOWN,
1685                 RTE_PTYPE_L3_IPV6_EXT_UNKNOWN,
1686                 RTE_PTYPE_L4_FRAG,
1687                 RTE_PTYPE_L4_ICMP,
1688                 RTE_PTYPE_L4_NONFRAG,
1689                 RTE_PTYPE_L4_SCTP,
1690                 RTE_PTYPE_L4_TCP,
1691                 RTE_PTYPE_L4_UDP,
1692                 RTE_PTYPE_TUNNEL_GRENAT,
1693                 RTE_PTYPE_TUNNEL_IP,
1694                 RTE_PTYPE_INNER_L2_ETHER,
1695                 RTE_PTYPE_INNER_L2_ETHER_VLAN,
1696                 RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN,
1697                 RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN,
1698                 RTE_PTYPE_INNER_L4_FRAG,
1699                 RTE_PTYPE_INNER_L4_ICMP,
1700                 RTE_PTYPE_INNER_L4_NONFRAG,
1701                 RTE_PTYPE_INNER_L4_SCTP,
1702                 RTE_PTYPE_INNER_L4_TCP,
1703                 RTE_PTYPE_INNER_L4_UDP,
1704                 RTE_PTYPE_UNKNOWN
1705         };
1706
1707         if (dev->rx_pkt_burst == i40e_recv_pkts ||
1708 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1709             dev->rx_pkt_burst == i40e_recv_pkts_bulk_alloc ||
1710 #endif
1711             dev->rx_pkt_burst == i40e_recv_scattered_pkts ||
1712             dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
1713             dev->rx_pkt_burst == i40e_recv_pkts_vec)
1714                 return ptypes;
1715         return NULL;
1716 }
1717
1718 int
1719 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1720                         uint16_t queue_idx,
1721                         uint16_t nb_desc,
1722                         unsigned int socket_id,
1723                         const struct rte_eth_rxconf *rx_conf,
1724                         struct rte_mempool *mp)
1725 {
1726         struct i40e_vsi *vsi;
1727         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1728         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1729         struct i40e_adapter *ad =
1730                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1731         struct i40e_rx_queue *rxq;
1732         const struct rte_memzone *rz;
1733         uint32_t ring_size;
1734         uint16_t len, i;
1735         uint16_t base, bsf, tc_mapping;
1736         int use_def_burst_func = 1;
1737
1738         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
1739                 struct i40e_vf *vf =
1740                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1741                 vsi = &vf->vsi;
1742         } else
1743                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1744
1745         if (vsi == NULL) {
1746                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1747                             "index exceeds the maximum");
1748                 return I40E_ERR_PARAM;
1749         }
1750         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
1751                         (nb_desc > I40E_MAX_RING_DESC) ||
1752                         (nb_desc < I40E_MIN_RING_DESC)) {
1753                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1754                             "invalid", nb_desc);
1755                 return I40E_ERR_PARAM;
1756         }
1757
1758         /* Free memory if needed */
1759         if (dev->data->rx_queues[queue_idx]) {
1760                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1761                 dev->data->rx_queues[queue_idx] = NULL;
1762         }
1763
1764         /* Allocate the rx queue data structure */
1765         rxq = rte_zmalloc_socket("i40e rx queue",
1766                                  sizeof(struct i40e_rx_queue),
1767                                  RTE_CACHE_LINE_SIZE,
1768                                  socket_id);
1769         if (!rxq) {
1770                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1771                             "rx queue data structure");
1772                 return -ENOMEM;
1773         }
1774         rxq->mp = mp;
1775         rxq->nb_rx_desc = nb_desc;
1776         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1777         rxq->queue_id = queue_idx;
1778         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
1779                 rxq->reg_idx = queue_idx;
1780         else /* PF device */
1781                 rxq->reg_idx = vsi->base_queue +
1782                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1783
1784         rxq->port_id = dev->data->port_id;
1785         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1786                                                         0 : ETHER_CRC_LEN);
1787         rxq->drop_en = rx_conf->rx_drop_en;
1788         rxq->vsi = vsi;
1789         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1790
1791         /* Allocate the maximun number of RX ring hardware descriptor. */
1792         len = I40E_MAX_RING_DESC;
1793
1794         /**
1795          * Allocating a little more memory because vectorized/bulk_alloc Rx
1796          * functions doesn't check boundaries each time.
1797          */
1798         len += RTE_PMD_I40E_RX_MAX_BURST;
1799
1800         ring_size = RTE_ALIGN(len * sizeof(union i40e_rx_desc),
1801                               I40E_DMA_MEM_ALIGN);
1802
1803         rz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
1804                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
1805         if (!rz) {
1806                 i40e_dev_rx_queue_release(rxq);
1807                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1808                 return -ENOMEM;
1809         }
1810
1811         /* Zero all the descriptors in the ring. */
1812         memset(rz->addr, 0, ring_size);
1813
1814         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1815         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1816
1817         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1818
1819         /* Allocate the software ring. */
1820         rxq->sw_ring =
1821                 rte_zmalloc_socket("i40e rx sw ring",
1822                                    sizeof(struct i40e_rx_entry) * len,
1823                                    RTE_CACHE_LINE_SIZE,
1824                                    socket_id);
1825         if (!rxq->sw_ring) {
1826                 i40e_dev_rx_queue_release(rxq);
1827                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1828                 return -ENOMEM;
1829         }
1830
1831         i40e_reset_rx_queue(rxq);
1832         rxq->q_set = TRUE;
1833         dev->data->rx_queues[queue_idx] = rxq;
1834
1835         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1836
1837         if (!use_def_burst_func) {
1838 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1839                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1840                              "satisfied. Rx Burst Bulk Alloc function will be "
1841                              "used on port=%d, queue=%d.",
1842                              rxq->port_id, rxq->queue_id);
1843 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1844         } else {
1845                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1846                              "not satisfied, Scattered Rx is requested, "
1847                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1848                              "not enabled on port=%d, queue=%d.",
1849                              rxq->port_id, rxq->queue_id);
1850                 ad->rx_bulk_alloc_allowed = false;
1851         }
1852
1853         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1854                 if (!(vsi->enabled_tc & (1 << i)))
1855                         continue;
1856                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
1857                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
1858                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
1859                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
1860                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
1861
1862                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
1863                         rxq->dcb_tc = i;
1864         }
1865
1866         return 0;
1867 }
1868
1869 void
1870 i40e_dev_rx_queue_release(void *rxq)
1871 {
1872         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1873
1874         if (!q) {
1875                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1876                 return;
1877         }
1878
1879         i40e_rx_queue_release_mbufs(q);
1880         rte_free(q->sw_ring);
1881         rte_free(q);
1882 }
1883
1884 uint32_t
1885 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1886 {
1887 #define I40E_RXQ_SCAN_INTERVAL 4
1888         volatile union i40e_rx_desc *rxdp;
1889         struct i40e_rx_queue *rxq;
1890         uint16_t desc = 0;
1891
1892         rxq = dev->data->rx_queues[rx_queue_id];
1893         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1894         while ((desc < rxq->nb_rx_desc) &&
1895                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1896                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1897                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1898                 /**
1899                  * Check the DD bit of a rx descriptor of each 4 in a group,
1900                  * to avoid checking too frequently and downgrading performance
1901                  * too much.
1902                  */
1903                 desc += I40E_RXQ_SCAN_INTERVAL;
1904                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1905                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1906                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1907                                         desc - rxq->nb_rx_desc]);
1908         }
1909
1910         return desc;
1911 }
1912
1913 int
1914 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1915 {
1916         volatile union i40e_rx_desc *rxdp;
1917         struct i40e_rx_queue *rxq = rx_queue;
1918         uint16_t desc;
1919         int ret;
1920
1921         if (unlikely(offset >= rxq->nb_rx_desc)) {
1922                 PMD_DRV_LOG(ERR, "Invalid RX descriptor id %u", offset);
1923                 return 0;
1924         }
1925
1926         desc = rxq->rx_tail + offset;
1927         if (desc >= rxq->nb_rx_desc)
1928                 desc -= rxq->nb_rx_desc;
1929
1930         rxdp = &(rxq->rx_ring[desc]);
1931
1932         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1933                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1934                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1935
1936         return ret;
1937 }
1938
1939 int
1940 i40e_dev_rx_descriptor_status(void *rx_queue, uint16_t offset)
1941 {
1942         struct i40e_rx_queue *rxq = rx_queue;
1943         volatile uint64_t *status;
1944         uint64_t mask;
1945         uint32_t desc;
1946
1947         if (unlikely(offset >= rxq->nb_rx_desc))
1948                 return -EINVAL;
1949
1950         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
1951                 return RTE_ETH_RX_DESC_UNAVAIL;
1952
1953         desc = rxq->rx_tail + offset;
1954         if (desc >= rxq->nb_rx_desc)
1955                 desc -= rxq->nb_rx_desc;
1956
1957         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
1958         mask = rte_le_to_cpu_64((1ULL << I40E_RX_DESC_STATUS_DD_SHIFT)
1959                 << I40E_RXD_QW1_STATUS_SHIFT);
1960         if (*status & mask)
1961                 return RTE_ETH_RX_DESC_DONE;
1962
1963         return RTE_ETH_RX_DESC_AVAIL;
1964 }
1965
1966 int
1967 i40e_dev_tx_descriptor_status(void *tx_queue, uint16_t offset)
1968 {
1969         struct i40e_tx_queue *txq = tx_queue;
1970         volatile uint64_t *status;
1971         uint64_t mask, expect;
1972         uint32_t desc;
1973
1974         if (unlikely(offset >= txq->nb_tx_desc))
1975                 return -EINVAL;
1976
1977         desc = txq->tx_tail + offset;
1978         /* go to next desc that has the RS bit */
1979         desc = ((desc + txq->tx_rs_thresh - 1) / txq->tx_rs_thresh) *
1980                 txq->tx_rs_thresh;
1981         if (desc >= txq->nb_tx_desc) {
1982                 desc -= txq->nb_tx_desc;
1983                 if (desc >= txq->nb_tx_desc)
1984                         desc -= txq->nb_tx_desc;
1985         }
1986
1987         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
1988         mask = rte_le_to_cpu_64(I40E_TXD_QW1_DTYPE_MASK);
1989         expect = rte_cpu_to_le_64(
1990                 I40E_TX_DESC_DTYPE_DESC_DONE << I40E_TXD_QW1_DTYPE_SHIFT);
1991         if ((*status & mask) == expect)
1992                 return RTE_ETH_TX_DESC_DONE;
1993
1994         return RTE_ETH_TX_DESC_FULL;
1995 }
1996
1997 int
1998 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1999                         uint16_t queue_idx,
2000                         uint16_t nb_desc,
2001                         unsigned int socket_id,
2002                         const struct rte_eth_txconf *tx_conf)
2003 {
2004         struct i40e_vsi *vsi;
2005         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2006         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2007         struct i40e_tx_queue *txq;
2008         const struct rte_memzone *tz;
2009         uint32_t ring_size;
2010         uint16_t tx_rs_thresh, tx_free_thresh;
2011         uint16_t i, base, bsf, tc_mapping;
2012
2013         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF) {
2014                 struct i40e_vf *vf =
2015                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2016                 vsi = &vf->vsi;
2017         } else
2018                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2019
2020         if (vsi == NULL) {
2021                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2022                             "exceeds the maximum", queue_idx);
2023                 return I40E_ERR_PARAM;
2024         }
2025
2026         if (nb_desc % I40E_ALIGN_RING_DESC != 0 ||
2027                         (nb_desc > I40E_MAX_RING_DESC) ||
2028                         (nb_desc < I40E_MIN_RING_DESC)) {
2029                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2030                             "invalid", nb_desc);
2031                 return I40E_ERR_PARAM;
2032         }
2033
2034         /**
2035          * The following two parameters control the setting of the RS bit on
2036          * transmit descriptors. TX descriptors will have their RS bit set
2037          * after txq->tx_rs_thresh descriptors have been used. The TX
2038          * descriptor ring will be cleaned after txq->tx_free_thresh
2039          * descriptors are used or if the number of descriptors required to
2040          * transmit a packet is greater than the number of free TX descriptors.
2041          *
2042          * The following constraints must be satisfied:
2043          *  - tx_rs_thresh must be greater than 0.
2044          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2045          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2046          *  - tx_rs_thresh must be a divisor of the ring size.
2047          *  - tx_free_thresh must be greater than 0.
2048          *  - tx_free_thresh must be less than the size of the ring minus 3.
2049          *
2050          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2051          * race condition, hence the maximum threshold constraints. When set
2052          * to zero use default values.
2053          */
2054         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2055                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2056         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2057                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2058         if (tx_rs_thresh >= (nb_desc - 2)) {
2059                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2060                              "number of TX descriptors minus 2. "
2061                              "(tx_rs_thresh=%u port=%d queue=%d)",
2062                              (unsigned int)tx_rs_thresh,
2063                              (int)dev->data->port_id,
2064                              (int)queue_idx);
2065                 return I40E_ERR_PARAM;
2066         }
2067         if (tx_free_thresh >= (nb_desc - 3)) {
2068                 PMD_INIT_LOG(ERR, "tx_free_thresh must be less than the "
2069                              "number of TX descriptors minus 3. "
2070                              "(tx_free_thresh=%u port=%d queue=%d)",
2071                              (unsigned int)tx_free_thresh,
2072                              (int)dev->data->port_id,
2073                              (int)queue_idx);
2074                 return I40E_ERR_PARAM;
2075         }
2076         if (tx_rs_thresh > tx_free_thresh) {
2077                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2078                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2079                              " tx_rs_thresh=%u port=%d queue=%d)",
2080                              (unsigned int)tx_free_thresh,
2081                              (unsigned int)tx_rs_thresh,
2082                              (int)dev->data->port_id,
2083                              (int)queue_idx);
2084                 return I40E_ERR_PARAM;
2085         }
2086         if ((nb_desc % tx_rs_thresh) != 0) {
2087                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2088                              "number of TX descriptors. (tx_rs_thresh=%u"
2089                              " port=%d queue=%d)",
2090                              (unsigned int)tx_rs_thresh,
2091                              (int)dev->data->port_id,
2092                              (int)queue_idx);
2093                 return I40E_ERR_PARAM;
2094         }
2095         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2096                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2097                              "tx_rs_thresh is greater than 1. "
2098                              "(tx_rs_thresh=%u port=%d queue=%d)",
2099                              (unsigned int)tx_rs_thresh,
2100                              (int)dev->data->port_id,
2101                              (int)queue_idx);
2102                 return I40E_ERR_PARAM;
2103         }
2104
2105         /* Free memory if needed. */
2106         if (dev->data->tx_queues[queue_idx]) {
2107                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2108                 dev->data->tx_queues[queue_idx] = NULL;
2109         }
2110
2111         /* Allocate the TX queue data structure. */
2112         txq = rte_zmalloc_socket("i40e tx queue",
2113                                   sizeof(struct i40e_tx_queue),
2114                                   RTE_CACHE_LINE_SIZE,
2115                                   socket_id);
2116         if (!txq) {
2117                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2118                             "tx queue structure");
2119                 return -ENOMEM;
2120         }
2121
2122         /* Allocate TX hardware ring descriptors. */
2123         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2124         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2125         tz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
2126                               ring_size, I40E_RING_BASE_ALIGN, socket_id);
2127         if (!tz) {
2128                 i40e_dev_tx_queue_release(txq);
2129                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2130                 return -ENOMEM;
2131         }
2132
2133         txq->nb_tx_desc = nb_desc;
2134         txq->tx_rs_thresh = tx_rs_thresh;
2135         txq->tx_free_thresh = tx_free_thresh;
2136         txq->pthresh = tx_conf->tx_thresh.pthresh;
2137         txq->hthresh = tx_conf->tx_thresh.hthresh;
2138         txq->wthresh = tx_conf->tx_thresh.wthresh;
2139         txq->queue_id = queue_idx;
2140         if (hw->mac.type == I40E_MAC_VF || hw->mac.type == I40E_MAC_X722_VF)
2141                 txq->reg_idx = queue_idx;
2142         else /* PF device */
2143                 txq->reg_idx = vsi->base_queue +
2144                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2145
2146         txq->port_id = dev->data->port_id;
2147         txq->txq_flags = tx_conf->txq_flags;
2148         txq->vsi = vsi;
2149         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2150
2151         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2152         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2153
2154         /* Allocate software ring */
2155         txq->sw_ring =
2156                 rte_zmalloc_socket("i40e tx sw ring",
2157                                    sizeof(struct i40e_tx_entry) * nb_desc,
2158                                    RTE_CACHE_LINE_SIZE,
2159                                    socket_id);
2160         if (!txq->sw_ring) {
2161                 i40e_dev_tx_queue_release(txq);
2162                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2163                 return -ENOMEM;
2164         }
2165
2166         i40e_reset_tx_queue(txq);
2167         txq->q_set = TRUE;
2168         dev->data->tx_queues[queue_idx] = txq;
2169
2170         /* Use a simple TX queue without offloads or multi segs if possible */
2171         i40e_set_tx_function_flag(dev, txq);
2172
2173         for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
2174                 if (!(vsi->enabled_tc & (1 << i)))
2175                         continue;
2176                 tc_mapping = rte_le_to_cpu_16(vsi->info.tc_mapping[i]);
2177                 base = (tc_mapping & I40E_AQ_VSI_TC_QUE_OFFSET_MASK) >>
2178                         I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT;
2179                 bsf = (tc_mapping & I40E_AQ_VSI_TC_QUE_NUMBER_MASK) >>
2180                         I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT;
2181
2182                 if (queue_idx >= base && queue_idx < (base + BIT(bsf)))
2183                         txq->dcb_tc = i;
2184         }
2185
2186         return 0;
2187 }
2188
2189 void
2190 i40e_dev_tx_queue_release(void *txq)
2191 {
2192         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2193
2194         if (!q) {
2195                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2196                 return;
2197         }
2198
2199         i40e_tx_queue_release_mbufs(q);
2200         rte_free(q->sw_ring);
2201         rte_free(q);
2202 }
2203
2204 const struct rte_memzone *
2205 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2206 {
2207         const struct rte_memzone *mz;
2208
2209         mz = rte_memzone_lookup(name);
2210         if (mz)
2211                 return mz;
2212
2213         if (rte_xen_dom0_supported())
2214                 mz = rte_memzone_reserve_bounded(name, len,
2215                                 socket_id, 0, I40E_RING_BASE_ALIGN, RTE_PGSIZE_2M);
2216         else
2217                 mz = rte_memzone_reserve_aligned(name, len,
2218                                 socket_id, 0, I40E_RING_BASE_ALIGN);
2219         return mz;
2220 }
2221
2222 void
2223 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2224 {
2225         uint16_t i;
2226
2227         /* SSE Vector driver has a different way of releasing mbufs. */
2228         if (rxq->rx_using_sse) {
2229                 i40e_rx_queue_release_mbufs_vec(rxq);
2230                 return;
2231         }
2232
2233         if (!rxq->sw_ring) {
2234                 PMD_DRV_LOG(DEBUG, "Pointer to sw_ring is NULL");
2235                 return;
2236         }
2237
2238         for (i = 0; i < rxq->nb_rx_desc; i++) {
2239                 if (rxq->sw_ring[i].mbuf) {
2240                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2241                         rxq->sw_ring[i].mbuf = NULL;
2242                 }
2243         }
2244 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2245         if (rxq->rx_nb_avail == 0)
2246                 return;
2247         for (i = 0; i < rxq->rx_nb_avail; i++) {
2248                 struct rte_mbuf *mbuf;
2249
2250                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2251                 rte_pktmbuf_free_seg(mbuf);
2252         }
2253         rxq->rx_nb_avail = 0;
2254 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2255 }
2256
2257 void
2258 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2259 {
2260         unsigned i;
2261         uint16_t len;
2262
2263         if (!rxq) {
2264                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
2265                 return;
2266         }
2267
2268 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2269         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2270                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2271         else
2272 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2273                 len = rxq->nb_rx_desc;
2274
2275         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2276                 ((volatile char *)rxq->rx_ring)[i] = 0;
2277
2278         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2279         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2280                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2281
2282 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2283         rxq->rx_nb_avail = 0;
2284         rxq->rx_next_avail = 0;
2285         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2286 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2287         rxq->rx_tail = 0;
2288         rxq->nb_rx_hold = 0;
2289         rxq->pkt_first_seg = NULL;
2290         rxq->pkt_last_seg = NULL;
2291
2292         rxq->rxrearm_start = 0;
2293         rxq->rxrearm_nb = 0;
2294 }
2295
2296 void
2297 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2298 {
2299         uint16_t i;
2300
2301         if (!txq || !txq->sw_ring) {
2302                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2303                 return;
2304         }
2305
2306         for (i = 0; i < txq->nb_tx_desc; i++) {
2307                 if (txq->sw_ring[i].mbuf) {
2308                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2309                         txq->sw_ring[i].mbuf = NULL;
2310                 }
2311         }
2312 }
2313
2314 void
2315 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2316 {
2317         struct i40e_tx_entry *txe;
2318         uint16_t i, prev, size;
2319
2320         if (!txq) {
2321                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2322                 return;
2323         }
2324
2325         txe = txq->sw_ring;
2326         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2327         for (i = 0; i < size; i++)
2328                 ((volatile char *)txq->tx_ring)[i] = 0;
2329
2330         prev = (uint16_t)(txq->nb_tx_desc - 1);
2331         for (i = 0; i < txq->nb_tx_desc; i++) {
2332                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2333
2334                 txd->cmd_type_offset_bsz =
2335                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2336                 txe[i].mbuf =  NULL;
2337                 txe[i].last_id = i;
2338                 txe[prev].next_id = i;
2339                 prev = i;
2340         }
2341
2342         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2343         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2344
2345         txq->tx_tail = 0;
2346         txq->nb_tx_used = 0;
2347
2348         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2349         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2350 }
2351
2352 /* Init the TX queue in hardware */
2353 int
2354 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2355 {
2356         enum i40e_status_code err = I40E_SUCCESS;
2357         struct i40e_vsi *vsi = txq->vsi;
2358         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2359         uint16_t pf_q = txq->reg_idx;
2360         struct i40e_hmc_obj_txq tx_ctx;
2361         uint32_t qtx_ctl;
2362
2363         /* clear the context structure first */
2364         memset(&tx_ctx, 0, sizeof(tx_ctx));
2365         tx_ctx.new_context = 1;
2366         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2367         tx_ctx.qlen = txq->nb_tx_desc;
2368
2369 #ifdef RTE_LIBRTE_IEEE1588
2370         tx_ctx.timesync_ena = 1;
2371 #endif
2372         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[txq->dcb_tc]);
2373         if (vsi->type == I40E_VSI_FDIR)
2374                 tx_ctx.fd_ena = TRUE;
2375
2376         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2377         if (err != I40E_SUCCESS) {
2378                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2379                 return err;
2380         }
2381
2382         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2383         if (err != I40E_SUCCESS) {
2384                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2385                 return err;
2386         }
2387
2388         /* Now associate this queue with this PCI function */
2389         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2390         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2391                                         I40E_QTX_CTL_PF_INDX_MASK);
2392         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2393         I40E_WRITE_FLUSH(hw);
2394
2395         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2396
2397         return err;
2398 }
2399
2400 int
2401 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2402 {
2403         struct i40e_rx_entry *rxe = rxq->sw_ring;
2404         uint64_t dma_addr;
2405         uint16_t i;
2406
2407         for (i = 0; i < rxq->nb_rx_desc; i++) {
2408                 volatile union i40e_rx_desc *rxd;
2409                 struct rte_mbuf *mbuf = rte_mbuf_raw_alloc(rxq->mp);
2410
2411                 if (unlikely(!mbuf)) {
2412                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2413                         return -ENOMEM;
2414                 }
2415
2416                 rte_mbuf_refcnt_set(mbuf, 1);
2417                 mbuf->next = NULL;
2418                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2419                 mbuf->nb_segs = 1;
2420                 mbuf->port = rxq->port_id;
2421
2422                 dma_addr =
2423                         rte_cpu_to_le_64(rte_mbuf_data_dma_addr_default(mbuf));
2424
2425                 rxd = &rxq->rx_ring[i];
2426                 rxd->read.pkt_addr = dma_addr;
2427                 rxd->read.hdr_addr = 0;
2428 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2429                 rxd->read.rsvd1 = 0;
2430                 rxd->read.rsvd2 = 0;
2431 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2432
2433                 rxe[i].mbuf = mbuf;
2434         }
2435
2436         return 0;
2437 }
2438
2439 /*
2440  * Calculate the buffer length, and check the jumbo frame
2441  * and maximum packet length.
2442  */
2443 static int
2444 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2445 {
2446         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2447         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2448         struct rte_eth_dev_data *data = pf->dev_data;
2449         uint16_t buf_size, len;
2450
2451         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2452                 RTE_PKTMBUF_HEADROOM);
2453
2454         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2455                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2456         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2457                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2458                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2459                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2460                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2461                 rxq->hs_mode = i40e_header_split_enabled;
2462                 break;
2463         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2464         default:
2465                 rxq->rx_hdr_len = 0;
2466                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2467                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2468                 rxq->hs_mode = i40e_header_split_none;
2469                 break;
2470         }
2471
2472         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2473         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2474         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2475                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2476                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2477                         PMD_DRV_LOG(ERR, "maximum packet length must "
2478                                     "be larger than %u and smaller than %u,"
2479                                     "as jumbo frame is enabled",
2480                                     (uint32_t)ETHER_MAX_LEN,
2481                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2482                         return I40E_ERR_CONFIG;
2483                 }
2484         } else {
2485                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2486                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2487                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2488                                     "larger than %u and smaller than %u, "
2489                                     "as jumbo frame is disabled",
2490                                     (uint32_t)ETHER_MIN_LEN,
2491                                     (uint32_t)ETHER_MAX_LEN);
2492                         return I40E_ERR_CONFIG;
2493                 }
2494         }
2495
2496         return 0;
2497 }
2498
2499 /* Init the RX queue in hardware */
2500 int
2501 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2502 {
2503         int err = I40E_SUCCESS;
2504         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2505         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2506         uint16_t pf_q = rxq->reg_idx;
2507         uint16_t buf_size;
2508         struct i40e_hmc_obj_rxq rx_ctx;
2509
2510         err = i40e_rx_queue_config(rxq);
2511         if (err < 0) {
2512                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2513                 return err;
2514         }
2515
2516         /* Clear the context structure first */
2517         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2518         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2519         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2520
2521         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2522         rx_ctx.qlen = rxq->nb_rx_desc;
2523 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2524         rx_ctx.dsize = 1;
2525 #endif
2526         rx_ctx.dtype = rxq->hs_mode;
2527         if (rxq->hs_mode)
2528                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2529         else
2530                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2531         rx_ctx.rxmax = rxq->max_pkt_len;
2532         rx_ctx.tphrdesc_ena = 1;
2533         rx_ctx.tphwdesc_ena = 1;
2534         rx_ctx.tphdata_ena = 1;
2535         rx_ctx.tphhead_ena = 1;
2536         rx_ctx.lrxqthresh = 2;
2537         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2538         rx_ctx.l2tsel = 1;
2539         /* showiv indicates if inner VLAN is stripped inside of tunnel
2540          * packet. When set it to 1, vlan information is stripped from
2541          * the inner header, but the hardware does not put it in the
2542          * descriptor. So set it zero by default.
2543          */
2544         rx_ctx.showiv = 0;
2545         rx_ctx.prefena = 1;
2546
2547         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2548         if (err != I40E_SUCCESS) {
2549                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2550                 return err;
2551         }
2552         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2553         if (err != I40E_SUCCESS) {
2554                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2555                 return err;
2556         }
2557
2558         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2559
2560         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2561                 RTE_PKTMBUF_HEADROOM);
2562
2563         /* Check if scattered RX needs to be used. */
2564         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2565                 dev_data->scattered_rx = 1;
2566         }
2567
2568         /* Init the RX tail regieter. */
2569         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2570
2571         return 0;
2572 }
2573
2574 void
2575 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2576 {
2577         uint16_t i;
2578
2579         PMD_INIT_FUNC_TRACE();
2580
2581         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2582                 if (!dev->data->tx_queues[i])
2583                         continue;
2584                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2585                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2586         }
2587
2588         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2589                 if (!dev->data->rx_queues[i])
2590                         continue;
2591                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2592                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2593         }
2594 }
2595
2596 void
2597 i40e_dev_free_queues(struct rte_eth_dev *dev)
2598 {
2599         uint16_t i;
2600
2601         PMD_INIT_FUNC_TRACE();
2602
2603         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2604                 if (!dev->data->rx_queues[i])
2605                         continue;
2606                 i40e_dev_rx_queue_release(dev->data->rx_queues[i]);
2607                 dev->data->rx_queues[i] = NULL;
2608         }
2609         dev->data->nb_rx_queues = 0;
2610
2611         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2612                 if (!dev->data->tx_queues[i])
2613                         continue;
2614                 i40e_dev_tx_queue_release(dev->data->tx_queues[i]);
2615                 dev->data->tx_queues[i] = NULL;
2616         }
2617         dev->data->nb_tx_queues = 0;
2618 }
2619
2620 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2621 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2622
2623 enum i40e_status_code
2624 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2625 {
2626         struct i40e_tx_queue *txq;
2627         const struct rte_memzone *tz = NULL;
2628         uint32_t ring_size;
2629         struct rte_eth_dev *dev;
2630
2631         if (!pf) {
2632                 PMD_DRV_LOG(ERR, "PF is not available");
2633                 return I40E_ERR_BAD_PTR;
2634         }
2635
2636         dev = pf->adapter->eth_dev;
2637
2638         /* Allocate the TX queue data structure. */
2639         txq = rte_zmalloc_socket("i40e fdir tx queue",
2640                                   sizeof(struct i40e_tx_queue),
2641                                   RTE_CACHE_LINE_SIZE,
2642                                   SOCKET_ID_ANY);
2643         if (!txq) {
2644                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2645                                         "tx queue structure.");
2646                 return I40E_ERR_NO_MEMORY;
2647         }
2648
2649         /* Allocate TX hardware ring descriptors. */
2650         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2651         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2652
2653         tz = rte_eth_dma_zone_reserve(dev, "fdir_tx_ring",
2654                                       I40E_FDIR_QUEUE_ID, ring_size,
2655                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2656         if (!tz) {
2657                 i40e_dev_tx_queue_release(txq);
2658                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2659                 return I40E_ERR_NO_MEMORY;
2660         }
2661
2662         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2663         txq->queue_id = I40E_FDIR_QUEUE_ID;
2664         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2665         txq->vsi = pf->fdir.fdir_vsi;
2666
2667         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2668         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2669         /*
2670          * don't need to allocate software ring and reset for the fdir
2671          * program queue just set the queue has been configured.
2672          */
2673         txq->q_set = TRUE;
2674         pf->fdir.txq = txq;
2675
2676         return I40E_SUCCESS;
2677 }
2678
2679 enum i40e_status_code
2680 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2681 {
2682         struct i40e_rx_queue *rxq;
2683         const struct rte_memzone *rz = NULL;
2684         uint32_t ring_size;
2685         struct rte_eth_dev *dev;
2686
2687         if (!pf) {
2688                 PMD_DRV_LOG(ERR, "PF is not available");
2689                 return I40E_ERR_BAD_PTR;
2690         }
2691
2692         dev = pf->adapter->eth_dev;
2693
2694         /* Allocate the RX queue data structure. */
2695         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2696                                   sizeof(struct i40e_rx_queue),
2697                                   RTE_CACHE_LINE_SIZE,
2698                                   SOCKET_ID_ANY);
2699         if (!rxq) {
2700                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2701                                         "rx queue structure.");
2702                 return I40E_ERR_NO_MEMORY;
2703         }
2704
2705         /* Allocate RX hardware ring descriptors. */
2706         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2707         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2708
2709         rz = rte_eth_dma_zone_reserve(dev, "fdir_rx_ring",
2710                                       I40E_FDIR_QUEUE_ID, ring_size,
2711                                       I40E_RING_BASE_ALIGN, SOCKET_ID_ANY);
2712         if (!rz) {
2713                 i40e_dev_rx_queue_release(rxq);
2714                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2715                 return I40E_ERR_NO_MEMORY;
2716         }
2717
2718         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2719         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2720         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2721         rxq->vsi = pf->fdir.fdir_vsi;
2722
2723         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2724         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2725
2726         /*
2727          * Don't need to allocate software ring and reset for the fdir
2728          * rx queue, just set the queue has been configured.
2729          */
2730         rxq->q_set = TRUE;
2731         pf->fdir.rxq = rxq;
2732
2733         return I40E_SUCCESS;
2734 }
2735
2736 void
2737 i40e_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2738         struct rte_eth_rxq_info *qinfo)
2739 {
2740         struct i40e_rx_queue *rxq;
2741
2742         rxq = dev->data->rx_queues[queue_id];
2743
2744         qinfo->mp = rxq->mp;
2745         qinfo->scattered_rx = dev->data->scattered_rx;
2746         qinfo->nb_desc = rxq->nb_rx_desc;
2747
2748         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2749         qinfo->conf.rx_drop_en = rxq->drop_en;
2750         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2751 }
2752
2753 void
2754 i40e_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2755         struct rte_eth_txq_info *qinfo)
2756 {
2757         struct i40e_tx_queue *txq;
2758
2759         txq = dev->data->tx_queues[queue_id];
2760
2761         qinfo->nb_desc = txq->nb_tx_desc;
2762
2763         qinfo->conf.tx_thresh.pthresh = txq->pthresh;
2764         qinfo->conf.tx_thresh.hthresh = txq->hthresh;
2765         qinfo->conf.tx_thresh.wthresh = txq->wthresh;
2766
2767         qinfo->conf.tx_free_thresh = txq->tx_free_thresh;
2768         qinfo->conf.tx_rs_thresh = txq->tx_rs_thresh;
2769         qinfo->conf.txq_flags = txq->txq_flags;
2770         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2771 }
2772
2773 void __attribute__((cold))
2774 i40e_set_rx_function(struct rte_eth_dev *dev)
2775 {
2776         struct i40e_adapter *ad =
2777                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2778         uint16_t rx_using_sse, i;
2779         /* In order to allow Vector Rx there are a few configuration
2780          * conditions to be met and Rx Bulk Allocation should be allowed.
2781          */
2782         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2783                 if (i40e_rx_vec_dev_conf_condition_check(dev) ||
2784                     !ad->rx_bulk_alloc_allowed) {
2785                         PMD_INIT_LOG(DEBUG, "Port[%d] doesn't meet"
2786                                      " Vector Rx preconditions",
2787                                      dev->data->port_id);
2788
2789                         ad->rx_vec_allowed = false;
2790                 }
2791                 if (ad->rx_vec_allowed) {
2792                         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2793                                 struct i40e_rx_queue *rxq =
2794                                         dev->data->rx_queues[i];
2795
2796                                 if (rxq && i40e_rxq_vec_setup(rxq)) {
2797                                         ad->rx_vec_allowed = false;
2798                                         break;
2799                                 }
2800                         }
2801                 }
2802         }
2803
2804         if (dev->data->scattered_rx) {
2805                 /* Set the non-LRO scattered callback: there are Vector and
2806                  * single allocation versions.
2807                  */
2808                 if (ad->rx_vec_allowed) {
2809                         PMD_INIT_LOG(DEBUG, "Using Vector Scattered Rx "
2810                                             "callback (port=%d).",
2811                                      dev->data->port_id);
2812
2813                         dev->rx_pkt_burst = i40e_recv_scattered_pkts_vec;
2814                 } else {
2815                         PMD_INIT_LOG(DEBUG, "Using a Scattered with bulk "
2816                                            "allocation callback (port=%d).",
2817                                      dev->data->port_id);
2818                         dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2819                 }
2820         /* If parameters allow we are going to choose between the following
2821          * callbacks:
2822          *    - Vector
2823          *    - Bulk Allocation
2824          *    - Single buffer allocation (the simplest one)
2825          */
2826         } else if (ad->rx_vec_allowed) {
2827                 PMD_INIT_LOG(DEBUG, "Vector rx enabled, please make sure RX "
2828                                     "burst size no less than %d (port=%d).",
2829                              RTE_I40E_DESCS_PER_LOOP,
2830                              dev->data->port_id);
2831
2832                 dev->rx_pkt_burst = i40e_recv_pkts_vec;
2833         } else if (ad->rx_bulk_alloc_allowed) {
2834                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
2835                                     "satisfied. Rx Burst Bulk Alloc function "
2836                                     "will be used on port=%d.",
2837                              dev->data->port_id);
2838
2839                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
2840         } else {
2841                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are not "
2842                                     "satisfied, or Scattered Rx is requested "
2843                                     "(port=%d).",
2844                              dev->data->port_id);
2845
2846                 dev->rx_pkt_burst = i40e_recv_pkts;
2847         }
2848
2849         /* Propagate information about RX function choice through all queues. */
2850         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2851                 rx_using_sse =
2852                         (dev->rx_pkt_burst == i40e_recv_scattered_pkts_vec ||
2853                          dev->rx_pkt_burst == i40e_recv_pkts_vec);
2854
2855                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2856                         struct i40e_rx_queue *rxq = dev->data->rx_queues[i];
2857
2858                         if (rxq)
2859                                 rxq->rx_using_sse = rx_using_sse;
2860                 }
2861         }
2862 }
2863
2864 void __attribute__((cold))
2865 i40e_set_tx_function_flag(struct rte_eth_dev *dev, struct i40e_tx_queue *txq)
2866 {
2867         struct i40e_adapter *ad =
2868                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2869
2870         /* Use a simple Tx queue (no offloads, no multi segs) if possible */
2871         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS)
2872                         && (txq->tx_rs_thresh >= RTE_PMD_I40E_TX_MAX_BURST)) {
2873                 if (txq->tx_rs_thresh <= RTE_I40E_TX_MAX_FREE_BUF_SZ) {
2874                         PMD_INIT_LOG(DEBUG, "Vector tx"
2875                                      " can be enabled on this txq.");
2876
2877                 } else {
2878                         ad->tx_vec_allowed = false;
2879                 }
2880         } else {
2881                 ad->tx_simple_allowed = false;
2882         }
2883 }
2884
2885 void __attribute__((cold))
2886 i40e_set_tx_function(struct rte_eth_dev *dev)
2887 {
2888         struct i40e_adapter *ad =
2889                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2890         int i;
2891
2892         if (rte_eal_process_type() == RTE_PROC_PRIMARY) {
2893                 if (ad->tx_vec_allowed) {
2894                         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2895                                 struct i40e_tx_queue *txq =
2896                                         dev->data->tx_queues[i];
2897
2898                                 if (txq && i40e_txq_vec_setup(txq)) {
2899                                         ad->tx_vec_allowed = false;
2900                                         break;
2901                                 }
2902                         }
2903                 }
2904         }
2905
2906         if (ad->tx_simple_allowed) {
2907                 if (ad->tx_vec_allowed) {
2908                         PMD_INIT_LOG(DEBUG, "Vector tx finally be used.");
2909                         dev->tx_pkt_burst = i40e_xmit_pkts_vec;
2910                 } else {
2911                         PMD_INIT_LOG(DEBUG, "Simple tx finally be used.");
2912                         dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2913                 }
2914                 dev->tx_pkt_prepare = NULL;
2915         } else {
2916                 PMD_INIT_LOG(DEBUG, "Xmit tx finally be used.");
2917                 dev->tx_pkt_burst = i40e_xmit_pkts;
2918                 dev->tx_pkt_prepare = i40e_prep_pkts;
2919         }
2920 }
2921
2922 void __attribute__((cold))
2923 i40e_set_default_ptype_table(struct rte_eth_dev *dev)
2924 {
2925         struct i40e_adapter *ad =
2926                 I40E_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2927         int i;
2928
2929         for (i = 0; i <= I40E_MAX_PKT_TYPE; i++)
2930                 ad->ptype_tbl[i] = i40e_get_default_pkt_type(i);
2931 }
2932
2933 /* Stubs needed for linkage when CONFIG_RTE_I40E_INC_VECTOR is set to 'n' */
2934 int __attribute__((weak))
2935 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev __rte_unused *dev)
2936 {
2937         return -1;
2938 }
2939
2940 uint16_t __attribute__((weak))
2941 i40e_recv_pkts_vec(
2942         void __rte_unused *rx_queue,
2943         struct rte_mbuf __rte_unused **rx_pkts,
2944         uint16_t __rte_unused nb_pkts)
2945 {
2946         return 0;
2947 }
2948
2949 uint16_t __attribute__((weak))
2950 i40e_recv_scattered_pkts_vec(
2951         void __rte_unused *rx_queue,
2952         struct rte_mbuf __rte_unused **rx_pkts,
2953         uint16_t __rte_unused nb_pkts)
2954 {
2955         return 0;
2956 }
2957
2958 int __attribute__((weak))
2959 i40e_rxq_vec_setup(struct i40e_rx_queue __rte_unused *rxq)
2960 {
2961         return -1;
2962 }
2963
2964 int __attribute__((weak))
2965 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
2966 {
2967         return -1;
2968 }
2969
2970 void __attribute__((weak))
2971 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue __rte_unused*rxq)
2972 {
2973         return;
2974 }
2975
2976 uint16_t __attribute__((weak))
2977 i40e_xmit_fixed_burst_vec(void __rte_unused * tx_queue,
2978                           struct rte_mbuf __rte_unused **tx_pkts,
2979                           uint16_t __rte_unused nb_pkts)
2980 {
2981         return 0;
2982 }