drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_TX_MAX_BURST  32
  68
  69 #define I40E_DMA_MEM_ALIGN 4096
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  82         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  83
  84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  85         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  86
  87 static const struct rte_memzone *
  88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  89                            const char *ring_name,
  90                            uint16_t queue_id,
  91                            uint32_t ring_size,
  92                            int socket_id);
  93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  94                                       struct rte_mbuf **tx_pkts,
  95                                       uint16_t nb_pkts);
  96
  97 /* Translate the rx descriptor status to pkt flags */
  98 static inline uint64_t
  99 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 100 {
 101         uint64_t flags;
 102
 103         /* Check if VLAN packet */
 104         flags = qword & (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 105                                                         PKT_RX_VLAN_PKT : 0;
 106
 107         /* Check if RSS_HASH */
 108         flags |= (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 109                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 110                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 111
 112         /* Check if FDIR Match */
 113         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 114                                                         PKT_RX_FDIR : 0);
 115
 116         return flags;
 117 }
 118
 119 static inline uint64_t
 120 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 121 {
 122         uint64_t flags = 0;
 123         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 124
 125 #define I40E_RX_ERR_BITS 0x3f
 126         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 127                 return flags;
 128         /* If RXE bit set, all other status bits are meaningless */
 129         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 130                 flags |= PKT_RX_MAC_ERR;
 131                 return flags;
 132         }
 133
 134         /* If RECIPE bit set, all other status indications should be ignored */
 135         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 136                 flags |= PKT_RX_RECIP_ERR;
 137                 return flags;
 138         }
 139         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 140                 flags |= PKT_RX_HBUF_OVERFLOW;
 141         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 142                 flags |= PKT_RX_IP_CKSUM_BAD;
 143         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 144                 flags |= PKT_RX_L4_CKSUM_BAD;
 145         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 146                 flags |= PKT_RX_EIP_CKSUM_BAD;
 147         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 148                 flags |= PKT_RX_OVERSIZE;
 149
 150         return flags;
 151 }
 152
 153 /* Translate pkt types to pkt flags */
 154 static inline uint64_t
 155 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 156 {
 157         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 158                                         I40E_RXD_QW1_PTYPE_SHIFT);
 159         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 160                 0, /* PTYPE 0 */
 161                 0, /* PTYPE 1 */
 162                 0, /* PTYPE 2 */
 163                 0, /* PTYPE 3 */
 164                 0, /* PTYPE 4 */
 165                 0, /* PTYPE 5 */
 166                 0, /* PTYPE 6 */
 167                 0, /* PTYPE 7 */
 168                 0, /* PTYPE 8 */
 169                 0, /* PTYPE 9 */
 170                 0, /* PTYPE 10 */
 171                 0, /* PTYPE 11 */
 172                 0, /* PTYPE 12 */
 173                 0, /* PTYPE 13 */
 174                 0, /* PTYPE 14 */
 175                 0, /* PTYPE 15 */
 176                 0, /* PTYPE 16 */
 177                 0, /* PTYPE 17 */
 178                 0, /* PTYPE 18 */
 179                 0, /* PTYPE 19 */
 180                 0, /* PTYPE 20 */
 181                 0, /* PTYPE 21 */
 182                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 183                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 184                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 185                 0, /* PTYPE 25 */
 186                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 187                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 188                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 189                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 190                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 191                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 192                 0, /* PTYPE 32 */
 193                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 194                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 195                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 196                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 197                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 198                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 199                 0, /* PTYPE 39 */
 200                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 201                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 202                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 203                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 204                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 205                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 206                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 207                 0, /* PTYPE 47 */
 208                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 209                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 210                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 211                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 212                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 213                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 214                 0, /* PTYPE 54 */
 215                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 216                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 217                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 218                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 219                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 220                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 221                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 222                 0, /* PTYPE 62 */
 223                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 224                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 225                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 226                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 227                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 228                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 229                 0, /* PTYPE 69 */
 230                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 231                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 232                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 233                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 234                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 235                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 236                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 237                 0, /* PTYPE 77 */
 238                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 239                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 240                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 241                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 242                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 243                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 244                 0, /* PTYPE 84 */
 245                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 246                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 247                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 248                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 249                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 250                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 251                 0, /* PTYPE 91 */
 252                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 253                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 254                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 255                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 256                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 257                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 258                 0, /* PTYPE 98 */
 259                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 260                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 261                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 262                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 263                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 264                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 265                 0, /* PTYPE 105 */
 266                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 267                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 268                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 269                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 270                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 271                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 272                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 273                 0, /* PTYPE 113 */
 274                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 275                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 276                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 277                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 278                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 279                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 280                 0, /* PTYPE 120 */
 281                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 282                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 283                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 284                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 285                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 286                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 287                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 288                 0, /* PTYPE 128 */
 289                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 290                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 291                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 292                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 293                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 294                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 295                 0, /* PTYPE 135 */
 296                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 297                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 298                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 299                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 300                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 301                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 302                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 303                 0, /* PTYPE 143 */
 304                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 305                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 306                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 307                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 308                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 309                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 310                 0, /* PTYPE 150 */
 311                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 312                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 313                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 314                 0, /* PTYPE 154 */
 315                 0, /* PTYPE 155 */
 316                 0, /* PTYPE 156 */
 317                 0, /* PTYPE 157 */
 318                 0, /* PTYPE 158 */
 319                 0, /* PTYPE 159 */
 320                 0, /* PTYPE 160 */
 321                 0, /* PTYPE 161 */
 322                 0, /* PTYPE 162 */
 323                 0, /* PTYPE 163 */
 324                 0, /* PTYPE 164 */
 325                 0, /* PTYPE 165 */
 326                 0, /* PTYPE 166 */
 327                 0, /* PTYPE 167 */
 328                 0, /* PTYPE 168 */
 329                 0, /* PTYPE 169 */
 330                 0, /* PTYPE 170 */
 331                 0, /* PTYPE 171 */
 332                 0, /* PTYPE 172 */
 333                 0, /* PTYPE 173 */
 334                 0, /* PTYPE 174 */
 335                 0, /* PTYPE 175 */
 336                 0, /* PTYPE 176 */
 337                 0, /* PTYPE 177 */
 338                 0, /* PTYPE 178 */
 339                 0, /* PTYPE 179 */
 340                 0, /* PTYPE 180 */
 341                 0, /* PTYPE 181 */
 342                 0, /* PTYPE 182 */
 343                 0, /* PTYPE 183 */
 344                 0, /* PTYPE 184 */
 345                 0, /* PTYPE 185 */
 346                 0, /* PTYPE 186 */
 347                 0, /* PTYPE 187 */
 348                 0, /* PTYPE 188 */
 349                 0, /* PTYPE 189 */
 350                 0, /* PTYPE 190 */
 351                 0, /* PTYPE 191 */
 352                 0, /* PTYPE 192 */
 353                 0, /* PTYPE 193 */
 354                 0, /* PTYPE 194 */
 355                 0, /* PTYPE 195 */
 356                 0, /* PTYPE 196 */
 357                 0, /* PTYPE 197 */
 358                 0, /* PTYPE 198 */
 359                 0, /* PTYPE 199 */
 360                 0, /* PTYPE 200 */
 361                 0, /* PTYPE 201 */
 362                 0, /* PTYPE 202 */
 363                 0, /* PTYPE 203 */
 364                 0, /* PTYPE 204 */
 365                 0, /* PTYPE 205 */
 366                 0, /* PTYPE 206 */
 367                 0, /* PTYPE 207 */
 368                 0, /* PTYPE 208 */
 369                 0, /* PTYPE 209 */
 370                 0, /* PTYPE 210 */
 371                 0, /* PTYPE 211 */
 372                 0, /* PTYPE 212 */
 373                 0, /* PTYPE 213 */
 374                 0, /* PTYPE 214 */
 375                 0, /* PTYPE 215 */
 376                 0, /* PTYPE 216 */
 377                 0, /* PTYPE 217 */
 378                 0, /* PTYPE 218 */
 379                 0, /* PTYPE 219 */
 380                 0, /* PTYPE 220 */
 381                 0, /* PTYPE 221 */
 382                 0, /* PTYPE 222 */
 383                 0, /* PTYPE 223 */
 384                 0, /* PTYPE 224 */
 385                 0, /* PTYPE 225 */
 386                 0, /* PTYPE 226 */
 387                 0, /* PTYPE 227 */
 388                 0, /* PTYPE 228 */
 389                 0, /* PTYPE 229 */
 390                 0, /* PTYPE 230 */
 391                 0, /* PTYPE 231 */
 392                 0, /* PTYPE 232 */
 393                 0, /* PTYPE 233 */
 394                 0, /* PTYPE 234 */
 395                 0, /* PTYPE 235 */
 396                 0, /* PTYPE 236 */
 397                 0, /* PTYPE 237 */
 398                 0, /* PTYPE 238 */
 399                 0, /* PTYPE 239 */
 400                 0, /* PTYPE 240 */
 401                 0, /* PTYPE 241 */
 402                 0, /* PTYPE 242 */
 403                 0, /* PTYPE 243 */
 404                 0, /* PTYPE 244 */
 405                 0, /* PTYPE 245 */
 406                 0, /* PTYPE 246 */
 407                 0, /* PTYPE 247 */
 408                 0, /* PTYPE 248 */
 409                 0, /* PTYPE 249 */
 410                 0, /* PTYPE 250 */
 411                 0, /* PTYPE 251 */
 412                 0, /* PTYPE 252 */
 413                 0, /* PTYPE 253 */
 414                 0, /* PTYPE 254 */
 415                 0, /* PTYPE 255 */
 416         };
 417
 418         return ip_ptype_map[ptype];
 419 }
 420
 421 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 422 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 423 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 424 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 425 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 426
 427 static inline uint64_t
 428 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 429 {
 430         uint64_t flags = 0;
 431 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 432         uint16_t flexbh, flexbl;
 433
 434         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 435                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 436                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 437         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 438                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 439                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 440
 441
 442         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 443                 mb->hash.fdir.hi =
 444                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 445                 flags |= PKT_RX_FDIR_ID;
 446         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 447                 mb->hash.fdir.hi =
 448                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 449                 flags |= PKT_RX_FDIR_FLX;
 450         }
 451         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 452                 mb->hash.fdir.lo =
 453                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 454                 flags |= PKT_RX_FDIR_FLX;
 455         }
 456 #else
 457         mb->hash.fdir.hi =
 458                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 459         flags |= PKT_RX_FDIR_ID;
 460 #endif
 461         return flags;
 462 }
 463 static inline void
 464 i40e_txd_enable_checksum(uint64_t ol_flags,
 465                         uint32_t *td_cmd,
 466                         uint32_t *td_offset,
 467                         union i40e_tx_offload tx_offload,
 468                         uint32_t *cd_tunneling)
 469 {
 470         /* UDP tunneling packet TX checksum offload */
 471         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 472
 473                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 474                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 475
 476                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 477                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 478                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 479                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 480                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 481                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 482
 483                 /* Now set the ctx descriptor fields */
 484                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 485                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 486                                 (tx_offload.l2_len >> 1) <<
 487                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 488
 489         } else
 490                 *td_offset |= (tx_offload.l2_len >> 1)
 491                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 492
 493         /* Enable L3 checksum offloads */
 494         if (ol_flags & PKT_TX_IP_CKSUM) {
 495                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 496                 *td_offset |= (tx_offload.l3_len >> 2)
 497                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 498         } else if (ol_flags & PKT_TX_IPV4) {
 499                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 500                 *td_offset |= (tx_offload.l3_len >> 2)
 501                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 502         } else if (ol_flags & PKT_TX_IPV6) {
 503                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 504                 *td_offset |= (tx_offload.l3_len >> 2)
 505                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 506         }
 507
 508         if (ol_flags & PKT_TX_TCP_SEG) {
 509                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 510                 *td_offset |= (tx_offload.l4_len >> 2)
 511                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 512                 return;
 513         }
 514
 515         /* Enable L4 checksum offloads */
 516         switch (ol_flags & PKT_TX_L4_MASK) {
 517         case PKT_TX_TCP_CKSUM:
 518                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 519                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 520                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 521                 break;
 522         case PKT_TX_SCTP_CKSUM:
 523                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 524                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 525                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 526                 break;
 527         case PKT_TX_UDP_CKSUM:
 528                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 529                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 530                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 531                 break;
 532         default:
 533                 break;
 534         }
 535 }
 536
 537 static inline struct rte_mbuf *
 538 rte_rxmbuf_alloc(struct rte_mempool *mp)
 539 {
 540         struct rte_mbuf *m;
 541
 542         m = __rte_mbuf_raw_alloc(mp);
 543         __rte_mbuf_sanity_check_raw(m, 0);
 544
 545         return m;
 546 }
 547
 548 /* Construct the tx flags */
 549 static inline uint64_t
 550 i40e_build_ctob(uint32_t td_cmd,
 551                 uint32_t td_offset,
 552                 unsigned int size,
 553                 uint32_t td_tag)
 554 {
 555         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 556                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 557                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 558                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 559                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 560 }
 561
 562 static inline int
 563 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 564 {
 565         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 566         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 567         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 568         uint16_t nb_tx_desc = txq->nb_tx_desc;
 569         uint16_t desc_to_clean_to;
 570         uint16_t nb_tx_to_clean;
 571
 572         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 573         if (desc_to_clean_to >= nb_tx_desc)
 574                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 575
 576         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 577         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
 578                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
 579                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 580                         "(port=%d queue=%d)", desc_to_clean_to,
 581                                 txq->port_id, txq->queue_id);
 582                 return -1;
 583         }
 584
 585         if (last_desc_cleaned > desc_to_clean_to)
 586                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 587                                                         desc_to_clean_to);
 588         else
 589                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 590                                         last_desc_cleaned);
 591
 592         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 593
 594         txq->last_desc_cleaned = desc_to_clean_to;
 595         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 596
 597         return 0;
 598 }
 599
 600 static inline int
 601 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 602 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 603 #else
 604 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 605 #endif
 606 {
 607         int ret = 0;
 608
 609 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 610         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 611                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 612                              "rxq->rx_free_thresh=%d, "
 613                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 614                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 615                 ret = -EINVAL;
 616         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 617                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 618                              "rxq->rx_free_thresh=%d, "
 619                              "rxq->nb_rx_desc=%d",
 620                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 621                 ret = -EINVAL;
 622         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 623                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 624                              "rxq->nb_rx_desc=%d, "
 625                              "rxq->rx_free_thresh=%d",
 626                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 627                 ret = -EINVAL;
 628         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 629                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 630                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 631                              "rxq->nb_rx_desc=%d, "
 632                              "I40E_MAX_RING_DESC=%d, "
 633                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 634                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 635                              RTE_PMD_I40E_RX_MAX_BURST);
 636                 ret = -EINVAL;
 637         }
 638 #else
 639         ret = -EINVAL;
 640 #endif
 641
 642         return ret;
 643 }
 644
 645 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 646 #define I40E_LOOK_AHEAD 8
 647 #if (I40E_LOOK_AHEAD != 8)
 648 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 649 #endif
 650 static inline int
 651 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 652 {
 653         volatile union i40e_rx_desc *rxdp;
 654         struct i40e_rx_entry *rxep;
 655         struct rte_mbuf *mb;
 656         uint16_t pkt_len;
 657         uint64_t qword1;
 658         uint32_t rx_status;
 659         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 660         int32_t i, j, nb_rx = 0;
 661         uint64_t pkt_flags;
 662
 663         rxdp = &rxq->rx_ring[rxq->rx_tail];
 664         rxep = &rxq->sw_ring[rxq->rx_tail];
 665
 666         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 667         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 668                                 I40E_RXD_QW1_STATUS_SHIFT;
 669
 670         /* Make sure there is at least 1 packet to receive */
 671         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 672                 return 0;
 673
 674         /**
 675          * Scan LOOK_AHEAD descriptors at a time to determine which
 676          * descriptors reference packets that are ready to be received.
 677          */
 678         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 679                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 680                 /* Read desc statuses backwards to avoid race condition */
 681                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 682                         qword1 = rte_le_to_cpu_64(\
 683                                 rxdp[j].wb.qword1.status_error_len);
 684                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 685                                         I40E_RXD_QW1_STATUS_SHIFT;
 686                 }
 687
 688                 /* Compute how many status bits were set */
 689                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 690                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 691
 692                 nb_rx += nb_dd;
 693
 694                 /* Translate descriptor info to mbuf parameters */
 695                 for (j = 0; j < nb_dd; j++) {
 696                         mb = rxep[j].mbuf;
 697                         qword1 = rte_le_to_cpu_64(\
 698                                 rxdp[j].wb.qword1.status_error_len);
 699                         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 700                                                 I40E_RXD_QW1_STATUS_SHIFT;
 701                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 702                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 703                         mb->data_len = pkt_len;
 704                         mb->pkt_len = pkt_len;
 705                         mb->vlan_tci = rx_status &
 706                                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 707                         rte_le_to_cpu_16(\
 708                                 rxdp[j].wb.qword0.lo_dword.l2tag1) : 0;
 709                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 710                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 711                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 712
 713                         mb->packet_type = (uint16_t)((qword1 &
 714                                         I40E_RXD_QW1_PTYPE_MASK) >>
 715                                         I40E_RXD_QW1_PTYPE_SHIFT);
 716                         if (pkt_flags & PKT_RX_RSS_HASH)
 717                                 mb->hash.rss = rte_le_to_cpu_32(\
 718                                         rxdp[j].wb.qword0.hi_dword.rss);
 719                         if (pkt_flags & PKT_RX_FDIR)
 720                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 721
 722                         mb->ol_flags = pkt_flags;
 723                 }
 724
 725                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 726                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 727
 728                 if (nb_dd != I40E_LOOK_AHEAD)
 729                         break;
 730         }
 731
 732         /* Clear software ring entries */
 733         for (i = 0; i < nb_rx; i++)
 734                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 735
 736         return nb_rx;
 737 }
 738
 739 static inline uint16_t
 740 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 741                         struct rte_mbuf **rx_pkts,
 742                         uint16_t nb_pkts)
 743 {
 744         uint16_t i;
 745         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 746
 747         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 748
 749         for (i = 0; i < nb_pkts; i++)
 750                 rx_pkts[i] = stage[i];
 751
 752         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 753         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 754
 755         return nb_pkts;
 756 }
 757
 758 static inline int
 759 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 760 {
 761         volatile union i40e_rx_desc *rxdp;
 762         struct i40e_rx_entry *rxep;
 763         struct rte_mbuf *mb;
 764         uint16_t alloc_idx, i;
 765         uint64_t dma_addr;
 766         int diag;
 767
 768         /* Allocate buffers in bulk */
 769         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 770                                 (rxq->rx_free_thresh - 1));
 771         rxep = &(rxq->sw_ring[alloc_idx]);
 772         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 773                                         rxq->rx_free_thresh);
 774         if (unlikely(diag != 0)) {
 775                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 776                 return -ENOMEM;
 777         }
 778
 779         rxdp = &rxq->rx_ring[alloc_idx];
 780         for (i = 0; i < rxq->rx_free_thresh; i++) {
 781                 mb = rxep[i].mbuf;
 782                 rte_mbuf_refcnt_set(mb, 1);
 783                 mb->next = NULL;
 784                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 785                 mb->nb_segs = 1;
 786                 mb->port = rxq->port_id;
 787                 dma_addr = rte_cpu_to_le_64(\
 788                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
 789                 rxdp[i].read.hdr_addr = dma_addr;
 790                 rxdp[i].read.pkt_addr = dma_addr;
 791         }
 792
 793         /* Update rx tail regsiter */
 794         rte_wmb();
 795         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 796
 797         rxq->rx_free_trigger =
 798                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 799         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 800                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 801
 802         return 0;
 803 }
 804
 805 static inline uint16_t
 806 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 807 {
 808         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 809         uint16_t nb_rx = 0;
 810
 811         if (!nb_pkts)
 812                 return 0;
 813
 814         if (rxq->rx_nb_avail)
 815                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 816
 817         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 818         rxq->rx_next_avail = 0;
 819         rxq->rx_nb_avail = nb_rx;
 820         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 821
 822         if (rxq->rx_tail > rxq->rx_free_trigger) {
 823                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 824                         uint16_t i, j;
 825
 826                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 827                                    "port_id=%u, queue_id=%u",
 828                                    rxq->port_id, rxq->queue_id);
 829                         rxq->rx_nb_avail = 0;
 830                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 831                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 832                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 833
 834                         return 0;
 835                 }
 836         }
 837
 838         if (rxq->rx_tail >= rxq->nb_rx_desc)
 839                 rxq->rx_tail = 0;
 840
 841         if (rxq->rx_nb_avail)
 842                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 843
 844         return 0;
 845 }
 846
 847 static uint16_t
 848 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 849                           struct rte_mbuf **rx_pkts,
 850                           uint16_t nb_pkts)
 851 {
 852         uint16_t nb_rx = 0, n, count;
 853
 854         if (unlikely(nb_pkts == 0))
 855                 return 0;
 856
 857         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 858                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 859
 860         while (nb_pkts) {
 861                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 862                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 863                 nb_rx = (uint16_t)(nb_rx + count);
 864                 nb_pkts = (uint16_t)(nb_pkts - count);
 865                 if (count < n)
 866                         break;
 867         }
 868
 869         return nb_rx;
 870 }
 871 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 872
 873 uint16_t
 874 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 875 {
 876         struct i40e_rx_queue *rxq;
 877         volatile union i40e_rx_desc *rx_ring;
 878         volatile union i40e_rx_desc *rxdp;
 879         union i40e_rx_desc rxd;
 880         struct i40e_rx_entry *sw_ring;
 881         struct i40e_rx_entry *rxe;
 882         struct rte_mbuf *rxm;
 883         struct rte_mbuf *nmb;
 884         uint16_t nb_rx;
 885         uint32_t rx_status;
 886         uint64_t qword1;
 887         uint16_t rx_packet_len;
 888         uint16_t rx_id, nb_hold;
 889         uint64_t dma_addr;
 890         uint64_t pkt_flags;
 891
 892         nb_rx = 0;
 893         nb_hold = 0;
 894         rxq = rx_queue;
 895         rx_id = rxq->rx_tail;
 896         rx_ring = rxq->rx_ring;
 897         sw_ring = rxq->sw_ring;
 898
 899         while (nb_rx < nb_pkts) {
 900                 rxdp = &rx_ring[rx_id];
 901                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 902                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 903                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 904                 /* Check the DD bit first */
 905                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 906                         break;
 907
 908                 nmb = rte_rxmbuf_alloc(rxq->mp);
 909                 if (unlikely(!nmb))
 910                         break;
 911                 rxd = *rxdp;
 912
 913                 nb_hold++;
 914                 rxe = &sw_ring[rx_id];
 915                 rx_id++;
 916                 if (unlikely(rx_id == rxq->nb_rx_desc))
 917                         rx_id = 0;
 918
 919                 /* Prefetch next mbuf */
 920                 rte_prefetch0(sw_ring[rx_id].mbuf);
 921
 922                 /**
 923                  * When next RX descriptor is on a cache line boundary,
 924                  * prefetch the next 4 RX descriptors and next 8 pointers
 925                  * to mbufs.
 926                  */
 927                 if ((rx_id & 0x3) == 0) {
 928                         rte_prefetch0(&rx_ring[rx_id]);
 929                         rte_prefetch0(&sw_ring[rx_id]);
 930                 }
 931                 rxm = rxe->mbuf;
 932                 rxe->mbuf = nmb;
 933                 dma_addr =
 934                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 935                 rxdp->read.hdr_addr = dma_addr;
 936                 rxdp->read.pkt_addr = dma_addr;
 937
 938                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 939                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 940
 941                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 942                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 943                 rxm->nb_segs = 1;
 944                 rxm->next = NULL;
 945                 rxm->pkt_len = rx_packet_len;
 946                 rxm->data_len = rx_packet_len;
 947                 rxm->port = rxq->port_id;
 948
 949                 rxm->vlan_tci = rx_status &
 950                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT) ?
 951                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
 952                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 953                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 954                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 955                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
 956                                 I40E_RXD_QW1_PTYPE_SHIFT);
 957                 if (pkt_flags & PKT_RX_RSS_HASH)
 958                         rxm->hash.rss =
 959                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 960                 if (pkt_flags & PKT_RX_FDIR)
 961                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 962
 963                 rxm->ol_flags = pkt_flags;
 964
 965                 rx_pkts[nb_rx++] = rxm;
 966         }
 967         rxq->rx_tail = rx_id;
 968
 969         /**
 970          * If the number of free RX descriptors is greater than the RX free
 971          * threshold of the queue, advance the receive tail register of queue.
 972          * Update that register with the value of the last processed RX
 973          * descriptor minus 1.
 974          */
 975         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 976         if (nb_hold > rxq->rx_free_thresh) {
 977                 rx_id = (uint16_t) ((rx_id == 0) ?
 978                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 979                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 980                 nb_hold = 0;
 981         }
 982         rxq->nb_rx_hold = nb_hold;
 983
 984         return nb_rx;
 985 }
 986
 987 uint16_t
 988 i40e_recv_scattered_pkts(void *rx_queue,
 989                          struct rte_mbuf **rx_pkts,
 990                          uint16_t nb_pkts)
 991 {
 992         struct i40e_rx_queue *rxq = rx_queue;
 993         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
 994         volatile union i40e_rx_desc *rxdp;
 995         union i40e_rx_desc rxd;
 996         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
 997         struct i40e_rx_entry *rxe;
 998         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
 999         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1000         struct rte_mbuf *nmb, *rxm;
1001         uint16_t rx_id = rxq->rx_tail;
1002         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1003         uint32_t rx_status;
1004         uint64_t qword1;
1005         uint64_t dma_addr;
1006         uint64_t pkt_flags;
1007
1008         while (nb_rx < nb_pkts) {
1009                 rxdp = &rx_ring[rx_id];
1010                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1011                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1012                                         I40E_RXD_QW1_STATUS_SHIFT;
1013                 /* Check the DD bit */
1014                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1015                         break;
1016
1017                 nmb = rte_rxmbuf_alloc(rxq->mp);
1018                 if (unlikely(!nmb))
1019                         break;
1020                 rxd = *rxdp;
1021                 nb_hold++;
1022                 rxe = &sw_ring[rx_id];
1023                 rx_id++;
1024                 if (rx_id == rxq->nb_rx_desc)
1025                         rx_id = 0;
1026
1027                 /* Prefetch next mbuf */
1028                 rte_prefetch0(sw_ring[rx_id].mbuf);
1029
1030                 /**
1031                  * When next RX descriptor is on a cache line boundary,
1032                  * prefetch the next 4 RX descriptors and next 8 pointers
1033                  * to mbufs.
1034                  */
1035                 if ((rx_id & 0x3) == 0) {
1036                         rte_prefetch0(&rx_ring[rx_id]);
1037                         rte_prefetch0(&sw_ring[rx_id]);
1038                 }
1039
1040                 rxm = rxe->mbuf;
1041                 rxe->mbuf = nmb;
1042                 dma_addr =
1043                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1044
1045                 /* Set data buffer address and data length of the mbuf */
1046                 rxdp->read.hdr_addr = dma_addr;
1047                 rxdp->read.pkt_addr = dma_addr;
1048                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1049                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1050                 rxm->data_len = rx_packet_len;
1051                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1052
1053                 /**
1054                  * If this is the first buffer of the received packet, set the
1055                  * pointer to the first mbuf of the packet and initialize its
1056                  * context. Otherwise, update the total length and the number
1057                  * of segments of the current scattered packet, and update the
1058                  * pointer to the last mbuf of the current packet.
1059                  */
1060                 if (!first_seg) {
1061                         first_seg = rxm;
1062                         first_seg->nb_segs = 1;
1063                         first_seg->pkt_len = rx_packet_len;
1064                 } else {
1065                         first_seg->pkt_len =
1066                                 (uint16_t)(first_seg->pkt_len +
1067                                                 rx_packet_len);
1068                         first_seg->nb_segs++;
1069                         last_seg->next = rxm;
1070                 }
1071
1072                 /**
1073                  * If this is not the last buffer of the received packet,
1074                  * update the pointer to the last mbuf of the current scattered
1075                  * packet and continue to parse the RX ring.
1076                  */
1077                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1078                         last_seg = rxm;
1079                         continue;
1080                 }
1081
1082                 /**
1083                  * This is the last buffer of the received packet. If the CRC
1084                  * is not stripped by the hardware:
1085                  *  - Subtract the CRC length from the total packet length.
1086                  *  - If the last buffer only contains the whole CRC or a part
1087                  *  of it, free the mbuf associated to the last buffer. If part
1088                  *  of the CRC is also contained in the previous mbuf, subtract
1089                  *  the length of that CRC part from the data length of the
1090                  *  previous mbuf.
1091                  */
1092                 rxm->next = NULL;
1093                 if (unlikely(rxq->crc_len > 0)) {
1094                         first_seg->pkt_len -= ETHER_CRC_LEN;
1095                         if (rx_packet_len <= ETHER_CRC_LEN) {
1096                                 rte_pktmbuf_free_seg(rxm);
1097                                 first_seg->nb_segs--;
1098                                 last_seg->data_len =
1099                                         (uint16_t)(last_seg->data_len -
1100                                         (ETHER_CRC_LEN - rx_packet_len));
1101                                 last_seg->next = NULL;
1102                         } else
1103                                 rxm->data_len = (uint16_t)(rx_packet_len -
1104                                                                 ETHER_CRC_LEN);
1105                 }
1106
1107                 first_seg->port = rxq->port_id;
1108                 first_seg->vlan_tci = (rx_status &
1109                         (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) ?
1110                         rte_le_to_cpu_16(rxd.wb.qword0.lo_dword.l2tag1) : 0;
1111                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1112                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1113                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1114                 first_seg->packet_type = (uint16_t)((qword1 &
1115                                         I40E_RXD_QW1_PTYPE_MASK) >>
1116                                         I40E_RXD_QW1_PTYPE_SHIFT);
1117                 if (pkt_flags & PKT_RX_RSS_HASH)
1118                         rxm->hash.rss =
1119                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1120                 if (pkt_flags & PKT_RX_FDIR)
1121                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1122
1123                 first_seg->ol_flags = pkt_flags;
1124
1125                 /* Prefetch data of first segment, if configured to do so. */
1126                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1127                         first_seg->data_off));
1128                 rx_pkts[nb_rx++] = first_seg;
1129                 first_seg = NULL;
1130         }
1131
1132         /* Record index of the next RX descriptor to probe. */
1133         rxq->rx_tail = rx_id;
1134         rxq->pkt_first_seg = first_seg;
1135         rxq->pkt_last_seg = last_seg;
1136
1137         /**
1138          * If the number of free RX descriptors is greater than the RX free
1139          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1140          * register. Update the RDT with the value of the last processed RX
1141          * descriptor minus 1, to guarantee that the RDT register is never
1142          * equal to the RDH register, which creates a "full" ring situtation
1143          * from the hardware point of view.
1144          */
1145         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1146         if (nb_hold > rxq->rx_free_thresh) {
1147                 rx_id = (uint16_t)(rx_id == 0 ?
1148                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1149                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1150                 nb_hold = 0;
1151         }
1152         rxq->nb_rx_hold = nb_hold;
1153
1154         return nb_rx;
1155 }
1156
1157 /* Check if the context descriptor is needed for TX offloading */
1158 static inline uint16_t
1159 i40e_calc_context_desc(uint64_t flags)
1160 {
1161         uint64_t mask = 0ULL;
1162
1163         mask |= (PKT_TX_OUTER_IP_CKSUM | PKT_TX_TCP_SEG);
1164
1165 #ifdef RTE_LIBRTE_IEEE1588
1166         mask |= PKT_TX_IEEE1588_TMST;
1167 #endif
1168         if (flags & mask)
1169                 return 1;
1170
1171         return 0;
1172 }
1173
1174 /* set i40e TSO context descriptor */
1175 static inline uint64_t
1176 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1177 {
1178         uint64_t ctx_desc = 0;
1179         uint32_t cd_cmd, hdr_len, cd_tso_len;
1180
1181         if (!tx_offload.l4_len) {
1182                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1183                 return ctx_desc;
1184         }
1185
1186         /**
1187          * in case of tunneling packet, the outer_l2_len and
1188          * outer_l3_len must be 0.
1189          */
1190         hdr_len = tx_offload.outer_l2_len +
1191                 tx_offload.outer_l3_len +
1192                 tx_offload.l2_len +
1193                 tx_offload.l3_len +
1194                 tx_offload.l4_len;
1195
1196         cd_cmd = I40E_TX_CTX_DESC_TSO;
1197         cd_tso_len = mbuf->pkt_len - hdr_len;
1198         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1199                 ((uint64_t)cd_tso_len <<
1200                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1201                 ((uint64_t)mbuf->tso_segsz <<
1202                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1203
1204         return ctx_desc;
1205 }
1206
1207 uint16_t
1208 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1209 {
1210         struct i40e_tx_queue *txq;
1211         struct i40e_tx_entry *sw_ring;
1212         struct i40e_tx_entry *txe, *txn;
1213         volatile struct i40e_tx_desc *txd;
1214         volatile struct i40e_tx_desc *txr;
1215         struct rte_mbuf *tx_pkt;
1216         struct rte_mbuf *m_seg;
1217         uint32_t cd_tunneling_params;
1218         uint16_t tx_id;
1219         uint16_t nb_tx;
1220         uint32_t td_cmd;
1221         uint32_t td_offset;
1222         uint32_t tx_flags;
1223         uint32_t td_tag;
1224         uint64_t ol_flags;
1225         uint16_t nb_used;
1226         uint16_t nb_ctx;
1227         uint16_t tx_last;
1228         uint16_t slen;
1229         uint64_t buf_dma_addr;
1230         union i40e_tx_offload tx_offload = {0};
1231
1232         txq = tx_queue;
1233         sw_ring = txq->sw_ring;
1234         txr = txq->tx_ring;
1235         tx_id = txq->tx_tail;
1236         txe = &sw_ring[tx_id];
1237
1238         /* Check if the descriptor ring needs to be cleaned. */
1239         if ((txq->nb_tx_desc - txq->nb_tx_free) > txq->tx_free_thresh)
1240                 i40e_xmit_cleanup(txq);
1241
1242         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1243                 td_cmd = 0;
1244                 td_tag = 0;
1245                 td_offset = 0;
1246                 tx_flags = 0;
1247
1248                 tx_pkt = *tx_pkts++;
1249                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1250
1251                 ol_flags = tx_pkt->ol_flags;
1252                 tx_offload.l2_len = tx_pkt->l2_len;
1253                 tx_offload.l3_len = tx_pkt->l3_len;
1254                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1255                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1256                 tx_offload.l4_len = tx_pkt->l4_len;
1257                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1258
1259                 /* Calculate the number of context descriptors needed. */
1260                 nb_ctx = i40e_calc_context_desc(ol_flags);
1261
1262                 /**
1263                  * The number of descriptors that must be allocated for
1264                  * a packet equals to the number of the segments of that
1265                  * packet plus 1 context descriptor if needed.
1266                  */
1267                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1268                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1269
1270                 /* Circular ring */
1271                 if (tx_last >= txq->nb_tx_desc)
1272                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1273
1274                 if (nb_used > txq->nb_tx_free) {
1275                         if (i40e_xmit_cleanup(txq) != 0) {
1276                                 if (nb_tx == 0)
1277                                         return 0;
1278                                 goto end_of_tx;
1279                         }
1280                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1281                                 while (nb_used > txq->nb_tx_free) {
1282                                         if (i40e_xmit_cleanup(txq) != 0) {
1283                                                 if (nb_tx == 0)
1284                                                         return 0;
1285                                                 goto end_of_tx;
1286                                         }
1287                                 }
1288                         }
1289                 }
1290
1291                 /* Descriptor based VLAN insertion */
1292                 if (ol_flags & PKT_TX_VLAN_PKT) {
1293                         tx_flags |= tx_pkt->vlan_tci <<
1294                                         I40E_TX_FLAG_L2TAG1_SHIFT;
1295                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1296                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1297                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1298                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1299                 }
1300
1301                 /* Always enable CRC offload insertion */
1302                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1303
1304                 /* Enable checksum offloading */
1305                 cd_tunneling_params = 0;
1306                 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1307                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1308                                 tx_offload, &cd_tunneling_params);
1309                 }
1310
1311                 if (unlikely(nb_ctx)) {
1312                         /* Setup TX context descriptor if required */
1313                         volatile struct i40e_tx_context_desc *ctx_txd =
1314                                 (volatile struct i40e_tx_context_desc *)\
1315                                                         &txr[tx_id];
1316                         uint16_t cd_l2tag2 = 0;
1317                         uint64_t cd_type_cmd_tso_mss =
1318                                 I40E_TX_DESC_DTYPE_CONTEXT;
1319
1320                         txn = &sw_ring[txe->next_id];
1321                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1322                         if (txe->mbuf != NULL) {
1323                                 rte_pktmbuf_free_seg(txe->mbuf);
1324                                 txe->mbuf = NULL;
1325                         }
1326
1327                         /* TSO enabled means no timestamp */
1328                         if (ol_flags & PKT_TX_TCP_SEG)
1329                                 cd_type_cmd_tso_mss |=
1330                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1331                         else {
1332 #ifdef RTE_LIBRTE_IEEE1588
1333                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1334                                         cd_type_cmd_tso_mss |=
1335                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1336                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1337 #endif
1338                         }
1339
1340                         ctx_txd->tunneling_params =
1341                                 rte_cpu_to_le_32(cd_tunneling_params);
1342                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1343                         ctx_txd->type_cmd_tso_mss =
1344                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1345
1346                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1347                                 "tunneling_params: %#x;\n"
1348                                 "l2tag2: %#hx;\n"
1349                                 "rsvd: %#hx;\n"
1350                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1351                                 tx_pkt, tx_id,
1352                                 ctx_txd->tunneling_params,
1353                                 ctx_txd->l2tag2,
1354                                 ctx_txd->rsvd,
1355                                 ctx_txd->type_cmd_tso_mss);
1356
1357                         txe->last_id = tx_last;
1358                         tx_id = txe->next_id;
1359                         txe = txn;
1360                 }
1361
1362                 m_seg = tx_pkt;
1363                 do {
1364                         txd = &txr[tx_id];
1365                         txn = &sw_ring[txe->next_id];
1366
1367                         if (txe->mbuf)
1368                                 rte_pktmbuf_free_seg(txe->mbuf);
1369                         txe->mbuf = m_seg;
1370
1371                         /* Setup TX Descriptor */
1372                         slen = m_seg->data_len;
1373                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1374
1375                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1376                                 "buf_dma_addr: %#"PRIx64";\n"
1377                                 "td_cmd: %#x;\n"
1378                                 "td_offset: %#x;\n"
1379                                 "td_len: %u;\n"
1380                                 "td_tag: %#x;\n",
1381                                 tx_pkt, tx_id, buf_dma_addr,
1382                                 td_cmd, td_offset, slen, td_tag);
1383
1384                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1385                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1386                                                 td_offset, slen, td_tag);
1387                         txe->last_id = tx_last;
1388                         tx_id = txe->next_id;
1389                         txe = txn;
1390                         m_seg = m_seg->next;
1391                 } while (m_seg != NULL);
1392
1393                 /* The last packet data descriptor needs End Of Packet (EOP) */
1394                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1395                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1396                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1397
1398                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1399                         PMD_TX_FREE_LOG(DEBUG,
1400                                         "Setting RS bit on TXD id="
1401                                         "%4u (port=%d queue=%d)",
1402                                         tx_last, txq->port_id, txq->queue_id);
1403
1404                         td_cmd |= I40E_TX_DESC_CMD_RS;
1405
1406                         /* Update txq RS bit counters */
1407                         txq->nb_tx_used = 0;
1408                 }
1409
1410                 txd->cmd_type_offset_bsz |=
1411                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1412                                         I40E_TXD_QW1_CMD_SHIFT);
1413         }
1414
1415 end_of_tx:
1416         rte_wmb();
1417
1418         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1419                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1420                    (unsigned) tx_id, (unsigned) nb_tx);
1421
1422         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1423         txq->tx_tail = tx_id;
1424
1425         return nb_tx;
1426 }
1427
1428 static inline int __attribute__((always_inline))
1429 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1430 {
1431         struct i40e_tx_entry *txep;
1432         uint16_t i;
1433
1434         if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1435                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1436                 return 0;
1437
1438         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1439
1440         for (i = 0; i < txq->tx_rs_thresh; i++)
1441                 rte_prefetch0((txep + i)->mbuf);
1442
1443         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1444                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1445                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1446                         txep->mbuf = NULL;
1447                 }
1448         } else {
1449                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1450                         rte_pktmbuf_free_seg(txep->mbuf);
1451                         txep->mbuf = NULL;
1452                 }
1453         }
1454
1455         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1456         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1457         if (txq->tx_next_dd >= txq->nb_tx_desc)
1458                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1459
1460         return txq->tx_rs_thresh;
1461 }
1462
1463 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1464                      I40E_TX_DESC_CMD_EOP)
1465
1466 /* Populate 4 descriptors with data from 4 mbufs */
1467 static inline void
1468 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1469 {
1470         uint64_t dma_addr;
1471         uint32_t i;
1472
1473         for (i = 0; i < 4; i++, txdp++, pkts++) {
1474                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1475                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1476                 txdp->cmd_type_offset_bsz =
1477                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1478                                         (*pkts)->data_len, 0);
1479         }
1480 }
1481
1482 /* Populate 1 descriptor with data from 1 mbuf */
1483 static inline void
1484 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1485 {
1486         uint64_t dma_addr;
1487
1488         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1489         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1490         txdp->cmd_type_offset_bsz =
1491                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1492                                 (*pkts)->data_len, 0);
1493 }
1494
1495 /* Fill hardware descriptor ring with mbuf data */
1496 static inline void
1497 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1498                      struct rte_mbuf **pkts,
1499                      uint16_t nb_pkts)
1500 {
1501         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1502         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1503         const int N_PER_LOOP = 4;
1504         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1505         int mainpart, leftover;
1506         int i, j;
1507
1508         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1509         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1510         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1511                 for (j = 0; j < N_PER_LOOP; ++j) {
1512                         (txep + i + j)->mbuf = *(pkts + i + j);
1513                 }
1514                 tx4(txdp + i, pkts + i);
1515         }
1516         if (unlikely(leftover > 0)) {
1517                 for (i = 0; i < leftover; ++i) {
1518                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1519                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1520                 }
1521         }
1522 }
1523
1524 static inline uint16_t
1525 tx_xmit_pkts(struct i40e_tx_queue *txq,
1526              struct rte_mbuf **tx_pkts,
1527              uint16_t nb_pkts)
1528 {
1529         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1530         uint16_t n = 0;
1531
1532         /**
1533          * Begin scanning the H/W ring for done descriptors when the number
1534          * of available descriptors drops below tx_free_thresh. For each done
1535          * descriptor, free the associated buffer.
1536          */
1537         if (txq->nb_tx_free < txq->tx_free_thresh)
1538                 i40e_tx_free_bufs(txq);
1539
1540         /* Use available descriptor only */
1541         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1542         if (unlikely(!nb_pkts))
1543                 return 0;
1544
1545         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1546         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1547                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1548                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1549                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1550                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1551                                                 I40E_TXD_QW1_CMD_SHIFT);
1552                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1553                 txq->tx_tail = 0;
1554         }
1555
1556         /* Fill hardware descriptor ring with mbuf data */
1557         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1558         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1559
1560         /* Determin if RS bit needs to be set */
1561         if (txq->tx_tail > txq->tx_next_rs) {
1562                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1563                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1564                                                 I40E_TXD_QW1_CMD_SHIFT);
1565                 txq->tx_next_rs =
1566                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1567                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1568                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1569         }
1570
1571         if (txq->tx_tail >= txq->nb_tx_desc)
1572                 txq->tx_tail = 0;
1573
1574         /* Update the tx tail register */
1575         rte_wmb();
1576         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1577
1578         return nb_pkts;
1579 }
1580
1581 static uint16_t
1582 i40e_xmit_pkts_simple(void *tx_queue,
1583                       struct rte_mbuf **tx_pkts,
1584                       uint16_t nb_pkts)
1585 {
1586         uint16_t nb_tx = 0;
1587
1588         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1589                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1590                                                 tx_pkts, nb_pkts);
1591
1592         while (nb_pkts) {
1593                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1594                                                 I40E_TX_MAX_BURST);
1595
1596                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1597                                                 &tx_pkts[nb_tx], num);
1598                 nb_tx = (uint16_t)(nb_tx + ret);
1599                 nb_pkts = (uint16_t)(nb_pkts - ret);
1600                 if (ret < num)
1601                         break;
1602         }
1603
1604         return nb_tx;
1605 }
1606
1607 /*
1608  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1609  * application used, which assume having sequential ones. But from driver's
1610  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1611  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1612  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1613  * use queue_idx from 0 to 95 to access queues, while real queue would be
1614  * different. This function will do a queue mapping to find VSI the queue
1615  * belongs to.
1616  */
1617 static struct i40e_vsi*
1618 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1619 {
1620         /* the queue in MAIN VSI range */
1621         if (queue_idx < pf->main_vsi->nb_qps)
1622                 return pf->main_vsi;
1623
1624         queue_idx -= pf->main_vsi->nb_qps;
1625
1626         /* queue_idx is greater than VMDQ VSIs range */
1627         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1628                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1629                 return NULL;
1630         }
1631
1632         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1633 }
1634
1635 static uint16_t
1636 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1637 {
1638         /* the queue in MAIN VSI range */
1639         if (queue_idx < pf->main_vsi->nb_qps)
1640                 return queue_idx;
1641
1642         /* It's VMDQ queues */
1643         queue_idx -= pf->main_vsi->nb_qps;
1644
1645         if (pf->nb_cfg_vmdq_vsi)
1646                 return queue_idx % pf->vmdq_nb_qps;
1647         else {
1648                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1649                 return (uint16_t)(-1);
1650         }
1651 }
1652
1653 int
1654 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1655 {
1656         struct i40e_rx_queue *rxq;
1657         int err = -1;
1658         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1659
1660         PMD_INIT_FUNC_TRACE();
1661
1662         if (rx_queue_id < dev->data->nb_rx_queues) {
1663                 rxq = dev->data->rx_queues[rx_queue_id];
1664
1665                 err = i40e_alloc_rx_queue_mbufs(rxq);
1666                 if (err) {
1667                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1668                         return err;
1669                 }
1670
1671                 rte_wmb();
1672
1673                 /* Init the RX tail regieter. */
1674                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1675
1676                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1677
1678                 if (err) {
1679                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1680                                     rx_queue_id);
1681
1682                         i40e_rx_queue_release_mbufs(rxq);
1683                         i40e_reset_rx_queue(rxq);
1684                 }
1685         }
1686
1687         return err;
1688 }
1689
1690 int
1691 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1692 {
1693         struct i40e_rx_queue *rxq;
1694         int err;
1695         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1696
1697         if (rx_queue_id < dev->data->nb_rx_queues) {
1698                 rxq = dev->data->rx_queues[rx_queue_id];
1699
1700                 /*
1701                 * rx_queue_id is queue id aplication refers to, while
1702                 * rxq->reg_idx is the real queue index.
1703                 */
1704                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1705
1706                 if (err) {
1707                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1708                                     rx_queue_id);
1709                         return err;
1710                 }
1711                 i40e_rx_queue_release_mbufs(rxq);
1712                 i40e_reset_rx_queue(rxq);
1713         }
1714
1715         return 0;
1716 }
1717
1718 int
1719 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1720 {
1721         int err = -1;
1722         struct i40e_tx_queue *txq;
1723         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1724
1725         PMD_INIT_FUNC_TRACE();
1726
1727         if (tx_queue_id < dev->data->nb_tx_queues) {
1728                 txq = dev->data->tx_queues[tx_queue_id];
1729
1730                 /*
1731                 * tx_queue_id is queue id aplication refers to, while
1732                 * rxq->reg_idx is the real queue index.
1733                 */
1734                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1735                 if (err)
1736                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1737                                     tx_queue_id);
1738         }
1739
1740         return err;
1741 }
1742
1743 int
1744 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1745 {
1746         struct i40e_tx_queue *txq;
1747         int err;
1748         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1749
1750         if (tx_queue_id < dev->data->nb_tx_queues) {
1751                 txq = dev->data->tx_queues[tx_queue_id];
1752
1753                 /*
1754                 * tx_queue_id is queue id aplication refers to, while
1755                 * txq->reg_idx is the real queue index.
1756                 */
1757                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1758
1759                 if (err) {
1760                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1761                                     tx_queue_id);
1762                         return err;
1763                 }
1764
1765                 i40e_tx_queue_release_mbufs(txq);
1766                 i40e_reset_tx_queue(txq);
1767         }
1768
1769         return 0;
1770 }
1771
1772 int
1773 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1774                         uint16_t queue_idx,
1775                         uint16_t nb_desc,
1776                         unsigned int socket_id,
1777                         const struct rte_eth_rxconf *rx_conf,
1778                         struct rte_mempool *mp)
1779 {
1780         struct i40e_vsi *vsi;
1781         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1782         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1783         struct i40e_rx_queue *rxq;
1784         const struct rte_memzone *rz;
1785         uint32_t ring_size;
1786         uint16_t len;
1787         int use_def_burst_func = 1;
1788
1789         if (hw->mac.type == I40E_MAC_VF) {
1790                 struct i40e_vf *vf =
1791                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1792                 vsi = &vf->vsi;
1793         } else
1794                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1795
1796         if (vsi == NULL) {
1797                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1798                             "index exceeds the maximum");
1799                 return I40E_ERR_PARAM;
1800         }
1801         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1802                                         (nb_desc > I40E_MAX_RING_DESC) ||
1803                                         (nb_desc < I40E_MIN_RING_DESC)) {
1804                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1805                             "invalid", nb_desc);
1806                 return I40E_ERR_PARAM;
1807         }
1808
1809         /* Free memory if needed */
1810         if (dev->data->rx_queues[queue_idx]) {
1811                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1812                 dev->data->rx_queues[queue_idx] = NULL;
1813         }
1814
1815         /* Allocate the rx queue data structure */
1816         rxq = rte_zmalloc_socket("i40e rx queue",
1817                                  sizeof(struct i40e_rx_queue),
1818                                  RTE_CACHE_LINE_SIZE,
1819                                  socket_id);
1820         if (!rxq) {
1821                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1822                             "rx queue data structure");
1823                 return (-ENOMEM);
1824         }
1825         rxq->mp = mp;
1826         rxq->nb_rx_desc = nb_desc;
1827         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1828         rxq->queue_id = queue_idx;
1829         if (hw->mac.type == I40E_MAC_VF)
1830                 rxq->reg_idx = queue_idx;
1831         else /* PF device */
1832                 rxq->reg_idx = vsi->base_queue +
1833                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1834
1835         rxq->port_id = dev->data->port_id;
1836         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1837                                                         0 : ETHER_CRC_LEN);
1838         rxq->drop_en = rx_conf->rx_drop_en;
1839         rxq->vsi = vsi;
1840         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1841
1842         /* Allocate the maximun number of RX ring hardware descriptor. */
1843         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1844         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1845         rz = i40e_ring_dma_zone_reserve(dev,
1846                                         "rx_ring",
1847                                         queue_idx,
1848                                         ring_size,
1849                                         socket_id);
1850         if (!rz) {
1851                 i40e_dev_rx_queue_release(rxq);
1852                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1853                 return (-ENOMEM);
1854         }
1855
1856         /* Zero all the descriptors in the ring. */
1857         memset(rz->addr, 0, ring_size);
1858
1859 #ifdef RTE_LIBRTE_XEN_DOM0
1860         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1861 #else
1862         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1863 #endif
1864
1865         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1866
1867 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1868         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1869 #else
1870         len = nb_desc;
1871 #endif
1872
1873         /* Allocate the software ring. */
1874         rxq->sw_ring =
1875                 rte_zmalloc_socket("i40e rx sw ring",
1876                                    sizeof(struct i40e_rx_entry) * len,
1877                                    RTE_CACHE_LINE_SIZE,
1878                                    socket_id);
1879         if (!rxq->sw_ring) {
1880                 i40e_dev_rx_queue_release(rxq);
1881                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1882                 return (-ENOMEM);
1883         }
1884
1885         i40e_reset_rx_queue(rxq);
1886         rxq->q_set = TRUE;
1887         dev->data->rx_queues[queue_idx] = rxq;
1888
1889         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1890
1891         if (!use_def_burst_func && !dev->data->scattered_rx) {
1892 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1893                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1894                              "satisfied. Rx Burst Bulk Alloc function will be "
1895                              "used on port=%d, queue=%d.",
1896                              rxq->port_id, rxq->queue_id);
1897                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1898 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1899         } else {
1900                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1901                              "not satisfied, Scattered Rx is requested, "
1902                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1903                              "not enabled on port=%d, queue=%d.",
1904                              rxq->port_id, rxq->queue_id);
1905         }
1906
1907         return 0;
1908 }
1909
1910 void
1911 i40e_dev_rx_queue_release(void *rxq)
1912 {
1913         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1914
1915         if (!q) {
1916                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1917                 return;
1918         }
1919
1920         i40e_rx_queue_release_mbufs(q);
1921         rte_free(q->sw_ring);
1922         rte_free(q);
1923 }
1924
1925 uint32_t
1926 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1927 {
1928 #define I40E_RXQ_SCAN_INTERVAL 4
1929         volatile union i40e_rx_desc *rxdp;
1930         struct i40e_rx_queue *rxq;
1931         uint16_t desc = 0;
1932
1933         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1934                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1935                 return 0;
1936         }
1937
1938         rxq = dev->data->rx_queues[rx_queue_id];
1939         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1940         while ((desc < rxq->nb_rx_desc) &&
1941                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1942                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1943                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1944                 /**
1945                  * Check the DD bit of a rx descriptor of each 4 in a group,
1946                  * to avoid checking too frequently and downgrading performance
1947                  * too much.
1948                  */
1949                 desc += I40E_RXQ_SCAN_INTERVAL;
1950                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1951                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1952                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1953                                         desc - rxq->nb_rx_desc]);
1954         }
1955
1956         return desc;
1957 }
1958
1959 int
1960 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1961 {
1962         volatile union i40e_rx_desc *rxdp;
1963         struct i40e_rx_queue *rxq = rx_queue;
1964         uint16_t desc;
1965         int ret;
1966
1967         if (unlikely(offset >= rxq->nb_rx_desc)) {
1968                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1969                 return 0;
1970         }
1971
1972         desc = rxq->rx_tail + offset;
1973         if (desc >= rxq->nb_rx_desc)
1974                 desc -= rxq->nb_rx_desc;
1975
1976         rxdp = &(rxq->rx_ring[desc]);
1977
1978         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1979                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1980                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
1981
1982         return ret;
1983 }
1984
1985 int
1986 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
1987                         uint16_t queue_idx,
1988                         uint16_t nb_desc,
1989                         unsigned int socket_id,
1990                         const struct rte_eth_txconf *tx_conf)
1991 {
1992         struct i40e_vsi *vsi;
1993         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1994         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1995         struct i40e_tx_queue *txq;
1996         const struct rte_memzone *tz;
1997         uint32_t ring_size;
1998         uint16_t tx_rs_thresh, tx_free_thresh;
1999
2000         if (hw->mac.type == I40E_MAC_VF) {
2001                 struct i40e_vf *vf =
2002                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2003                 vsi = &vf->vsi;
2004         } else
2005                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2006
2007         if (vsi == NULL) {
2008                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2009                             "exceeds the maximum", queue_idx);
2010                 return I40E_ERR_PARAM;
2011         }
2012
2013         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2014                                         (nb_desc > I40E_MAX_RING_DESC) ||
2015                                         (nb_desc < I40E_MIN_RING_DESC)) {
2016                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2017                             "invalid", nb_desc);
2018                 return I40E_ERR_PARAM;
2019         }
2020
2021         /**
2022          * The following two parameters control the setting of the RS bit on
2023          * transmit descriptors. TX descriptors will have their RS bit set
2024          * after txq->tx_rs_thresh descriptors have been used. The TX
2025          * descriptor ring will be cleaned after txq->tx_free_thresh
2026          * descriptors are used or if the number of descriptors required to
2027          * transmit a packet is greater than the number of free TX descriptors.
2028          *
2029          * The following constraints must be satisfied:
2030          *  - tx_rs_thresh must be greater than 0.
2031          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2032          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2033          *  - tx_rs_thresh must be a divisor of the ring size.
2034          *  - tx_free_thresh must be greater than 0.
2035          *  - tx_free_thresh must be less than the size of the ring minus 3.
2036          *
2037          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2038          * race condition, hence the maximum threshold constraints. When set
2039          * to zero use default values.
2040          */
2041         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2042                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2043         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2044                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2045         if (tx_rs_thresh >= (nb_desc - 2)) {
2046                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2047                              "number of TX descriptors minus 2. "
2048                              "(tx_rs_thresh=%u port=%d queue=%d)",
2049                              (unsigned int)tx_rs_thresh,
2050                              (int)dev->data->port_id,
2051                              (int)queue_idx);
2052                 return I40E_ERR_PARAM;
2053         }
2054         if (tx_free_thresh >= (nb_desc - 3)) {
2055                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2056                              "tx_free_thresh must be less than the "
2057                              "number of TX descriptors minus 3. "
2058                              "(tx_free_thresh=%u port=%d queue=%d)",
2059                              (unsigned int)tx_free_thresh,
2060                              (int)dev->data->port_id,
2061                              (int)queue_idx);
2062                 return I40E_ERR_PARAM;
2063         }
2064         if (tx_rs_thresh > tx_free_thresh) {
2065                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2066                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2067                              " tx_rs_thresh=%u port=%d queue=%d)",
2068                              (unsigned int)tx_free_thresh,
2069                              (unsigned int)tx_rs_thresh,
2070                              (int)dev->data->port_id,
2071                              (int)queue_idx);
2072                 return I40E_ERR_PARAM;
2073         }
2074         if ((nb_desc % tx_rs_thresh) != 0) {
2075                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2076                              "number of TX descriptors. (tx_rs_thresh=%u"
2077                              " port=%d queue=%d)",
2078                              (unsigned int)tx_rs_thresh,
2079                              (int)dev->data->port_id,
2080                              (int)queue_idx);
2081                 return I40E_ERR_PARAM;
2082         }
2083         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2084                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2085                              "tx_rs_thresh is greater than 1. "
2086                              "(tx_rs_thresh=%u port=%d queue=%d)",
2087                              (unsigned int)tx_rs_thresh,
2088                              (int)dev->data->port_id,
2089                              (int)queue_idx);
2090                 return I40E_ERR_PARAM;
2091         }
2092
2093         /* Free memory if needed. */
2094         if (dev->data->tx_queues[queue_idx]) {
2095                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2096                 dev->data->tx_queues[queue_idx] = NULL;
2097         }
2098
2099         /* Allocate the TX queue data structure. */
2100         txq = rte_zmalloc_socket("i40e tx queue",
2101                                   sizeof(struct i40e_tx_queue),
2102                                   RTE_CACHE_LINE_SIZE,
2103                                   socket_id);
2104         if (!txq) {
2105                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2106                             "tx queue structure");
2107                 return (-ENOMEM);
2108         }
2109
2110         /* Allocate TX hardware ring descriptors. */
2111         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2112         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2113         tz = i40e_ring_dma_zone_reserve(dev,
2114                                         "tx_ring",
2115                                         queue_idx,
2116                                         ring_size,
2117                                         socket_id);
2118         if (!tz) {
2119                 i40e_dev_tx_queue_release(txq);
2120                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2121                 return (-ENOMEM);
2122         }
2123
2124         txq->nb_tx_desc = nb_desc;
2125         txq->tx_rs_thresh = tx_rs_thresh;
2126         txq->tx_free_thresh = tx_free_thresh;
2127         txq->pthresh = tx_conf->tx_thresh.pthresh;
2128         txq->hthresh = tx_conf->tx_thresh.hthresh;
2129         txq->wthresh = tx_conf->tx_thresh.wthresh;
2130         txq->queue_id = queue_idx;
2131         if (hw->mac.type == I40E_MAC_VF)
2132                 txq->reg_idx = queue_idx;
2133         else /* PF device */
2134                 txq->reg_idx = vsi->base_queue +
2135                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2136
2137         txq->port_id = dev->data->port_id;
2138         txq->txq_flags = tx_conf->txq_flags;
2139         txq->vsi = vsi;
2140         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2141
2142 #ifdef RTE_LIBRTE_XEN_DOM0
2143         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2144 #else
2145         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2146 #endif
2147         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2148
2149         /* Allocate software ring */
2150         txq->sw_ring =
2151                 rte_zmalloc_socket("i40e tx sw ring",
2152                                    sizeof(struct i40e_tx_entry) * nb_desc,
2153                                    RTE_CACHE_LINE_SIZE,
2154                                    socket_id);
2155         if (!txq->sw_ring) {
2156                 i40e_dev_tx_queue_release(txq);
2157                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2158                 return (-ENOMEM);
2159         }
2160
2161         i40e_reset_tx_queue(txq);
2162         txq->q_set = TRUE;
2163         dev->data->tx_queues[queue_idx] = txq;
2164
2165         /* Use a simple TX queue without offloads or multi segs if possible */
2166         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2167                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2168                 PMD_INIT_LOG(INFO, "Using simple tx path");
2169                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2170         } else {
2171                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2172                 dev->tx_pkt_burst = i40e_xmit_pkts;
2173         }
2174
2175         return 0;
2176 }
2177
2178 void
2179 i40e_dev_tx_queue_release(void *txq)
2180 {
2181         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2182
2183         if (!q) {
2184                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2185                 return;
2186         }
2187
2188         i40e_tx_queue_release_mbufs(q);
2189         rte_free(q->sw_ring);
2190         rte_free(q);
2191 }
2192
2193 static const struct rte_memzone *
2194 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2195                            const char *ring_name,
2196                            uint16_t queue_id,
2197                            uint32_t ring_size,
2198                            int socket_id)
2199 {
2200         char z_name[RTE_MEMZONE_NAMESIZE];
2201         const struct rte_memzone *mz;
2202
2203         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2204                         dev->driver->pci_drv.name, ring_name,
2205                                 dev->data->port_id, queue_id);
2206         mz = rte_memzone_lookup(z_name);
2207         if (mz)
2208                 return mz;
2209
2210 #ifdef RTE_LIBRTE_XEN_DOM0
2211         return rte_memzone_reserve_bounded(z_name, ring_size,
2212                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2213 #else
2214         return rte_memzone_reserve_aligned(z_name, ring_size,
2215                                 socket_id, 0, I40E_ALIGN);
2216 #endif
2217 }
2218
2219 const struct rte_memzone *
2220 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2221 {
2222         const struct rte_memzone *mz = NULL;
2223
2224         mz = rte_memzone_lookup(name);
2225         if (mz)
2226                 return mz;
2227 #ifdef RTE_LIBRTE_XEN_DOM0
2228         mz = rte_memzone_reserve_bounded(name, len,
2229                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2230 #else
2231         mz = rte_memzone_reserve_aligned(name, len,
2232                                 socket_id, 0, I40E_ALIGN);
2233 #endif
2234         return mz;
2235 }
2236
2237 void
2238 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2239 {
2240         uint16_t i;
2241
2242         if (!rxq || !rxq->sw_ring) {
2243                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2244                 return;
2245         }
2246
2247         for (i = 0; i < rxq->nb_rx_desc; i++) {
2248                 if (rxq->sw_ring[i].mbuf) {
2249                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2250                         rxq->sw_ring[i].mbuf = NULL;
2251                 }
2252         }
2253 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2254         if (rxq->rx_nb_avail == 0)
2255                 return;
2256         for (i = 0; i < rxq->rx_nb_avail; i++) {
2257                 struct rte_mbuf *mbuf;
2258
2259                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2260                 rte_pktmbuf_free_seg(mbuf);
2261         }
2262         rxq->rx_nb_avail = 0;
2263 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2264 }
2265
2266 void
2267 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2268 {
2269         unsigned i;
2270         uint16_t len;
2271
2272 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2273         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2274                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2275         else
2276 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2277                 len = rxq->nb_rx_desc;
2278
2279         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2280                 ((volatile char *)rxq->rx_ring)[i] = 0;
2281
2282 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2283         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2284         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2285                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2286
2287         rxq->rx_nb_avail = 0;
2288         rxq->rx_next_avail = 0;
2289         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2290 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2291         rxq->rx_tail = 0;
2292         rxq->nb_rx_hold = 0;
2293         rxq->pkt_first_seg = NULL;
2294         rxq->pkt_last_seg = NULL;
2295 }
2296
2297 void
2298 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2299 {
2300         uint16_t i;
2301
2302         if (!txq || !txq->sw_ring) {
2303                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2304                 return;
2305         }
2306
2307         for (i = 0; i < txq->nb_tx_desc; i++) {
2308                 if (txq->sw_ring[i].mbuf) {
2309                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2310                         txq->sw_ring[i].mbuf = NULL;
2311                 }
2312         }
2313 }
2314
2315 void
2316 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2317 {
2318         struct i40e_tx_entry *txe;
2319         uint16_t i, prev, size;
2320
2321         if (!txq) {
2322                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2323                 return;
2324         }
2325
2326         txe = txq->sw_ring;
2327         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2328         for (i = 0; i < size; i++)
2329                 ((volatile char *)txq->tx_ring)[i] = 0;
2330
2331         prev = (uint16_t)(txq->nb_tx_desc - 1);
2332         for (i = 0; i < txq->nb_tx_desc; i++) {
2333                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2334
2335                 txd->cmd_type_offset_bsz =
2336                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2337                 txe[i].mbuf =  NULL;
2338                 txe[i].last_id = i;
2339                 txe[prev].next_id = i;
2340                 prev = i;
2341         }
2342
2343         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2344         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2345
2346         txq->tx_tail = 0;
2347         txq->nb_tx_used = 0;
2348
2349         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2350         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2351 }
2352
2353 /* Init the TX queue in hardware */
2354 int
2355 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2356 {
2357         enum i40e_status_code err = I40E_SUCCESS;
2358         struct i40e_vsi *vsi = txq->vsi;
2359         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2360         uint16_t pf_q = txq->reg_idx;
2361         struct i40e_hmc_obj_txq tx_ctx;
2362         uint32_t qtx_ctl;
2363
2364         /* clear the context structure first */
2365         memset(&tx_ctx, 0, sizeof(tx_ctx));
2366         tx_ctx.new_context = 1;
2367         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2368         tx_ctx.qlen = txq->nb_tx_desc;
2369         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2370         if (vsi->type == I40E_VSI_FDIR)
2371                 tx_ctx.fd_ena = TRUE;
2372
2373         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2374         if (err != I40E_SUCCESS) {
2375                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2376                 return err;
2377         }
2378
2379         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2380         if (err != I40E_SUCCESS) {
2381                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2382                 return err;
2383         }
2384
2385         /* Now associate this queue with this PCI function */
2386         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2387         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2388                                         I40E_QTX_CTL_PF_INDX_MASK);
2389         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2390         I40E_WRITE_FLUSH(hw);
2391
2392         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2393
2394         return err;
2395 }
2396
2397 int
2398 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2399 {
2400         struct i40e_rx_entry *rxe = rxq->sw_ring;
2401         uint64_t dma_addr;
2402         uint16_t i;
2403
2404         for (i = 0; i < rxq->nb_rx_desc; i++) {
2405                 volatile union i40e_rx_desc *rxd;
2406                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2407
2408                 if (unlikely(!mbuf)) {
2409                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2410                         return -ENOMEM;
2411                 }
2412
2413                 rte_mbuf_refcnt_set(mbuf, 1);
2414                 mbuf->next = NULL;
2415                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2416                 mbuf->nb_segs = 1;
2417                 mbuf->port = rxq->port_id;
2418
2419                 dma_addr =
2420                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2421
2422                 rxd = &rxq->rx_ring[i];
2423                 rxd->read.pkt_addr = dma_addr;
2424                 rxd->read.hdr_addr = dma_addr;
2425 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2426                 rxd->read.rsvd1 = 0;
2427                 rxd->read.rsvd2 = 0;
2428 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2429
2430                 rxe[i].mbuf = mbuf;
2431         }
2432
2433         return 0;
2434 }
2435
2436 /*
2437  * Calculate the buffer length, and check the jumbo frame
2438  * and maximum packet length.
2439  */
2440 static int
2441 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2442 {
2443         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2444         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2445         struct rte_eth_dev_data *data = pf->dev_data;
2446         uint16_t buf_size, len;
2447
2448         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2449                 RTE_PKTMBUF_HEADROOM);
2450
2451         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2452                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2453         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2454                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2455                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2456                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2457                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2458                 rxq->hs_mode = i40e_header_split_enabled;
2459                 break;
2460         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2461         default:
2462                 rxq->rx_hdr_len = 0;
2463                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2464                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2465                 rxq->hs_mode = i40e_header_split_none;
2466                 break;
2467         }
2468
2469         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2470         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2471         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2472                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2473                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2474                         PMD_DRV_LOG(ERR, "maximum packet length must "
2475                                     "be larger than %u and smaller than %u,"
2476                                     "as jumbo frame is enabled",
2477                                     (uint32_t)ETHER_MAX_LEN,
2478                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2479                         return I40E_ERR_CONFIG;
2480                 }
2481         } else {
2482                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2483                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2484                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2485                                     "larger than %u and smaller than %u, "
2486                                     "as jumbo frame is disabled",
2487                                     (uint32_t)ETHER_MIN_LEN,
2488                                     (uint32_t)ETHER_MAX_LEN);
2489                         return I40E_ERR_CONFIG;
2490                 }
2491         }
2492
2493         return 0;
2494 }
2495
2496 /* Init the RX queue in hardware */
2497 int
2498 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2499 {
2500         int err = I40E_SUCCESS;
2501         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2502         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2503         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2504         uint16_t pf_q = rxq->reg_idx;
2505         uint16_t buf_size;
2506         struct i40e_hmc_obj_rxq rx_ctx;
2507
2508         err = i40e_rx_queue_config(rxq);
2509         if (err < 0) {
2510                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2511                 return err;
2512         }
2513
2514         /* Clear the context structure first */
2515         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2516         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2517         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2518
2519         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2520         rx_ctx.qlen = rxq->nb_rx_desc;
2521 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2522         rx_ctx.dsize = 1;
2523 #endif
2524         rx_ctx.dtype = rxq->hs_mode;
2525         if (rxq->hs_mode)
2526                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2527         else
2528                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2529         rx_ctx.rxmax = rxq->max_pkt_len;
2530         rx_ctx.tphrdesc_ena = 1;
2531         rx_ctx.tphwdesc_ena = 1;
2532         rx_ctx.tphdata_ena = 1;
2533         rx_ctx.tphhead_ena = 1;
2534         rx_ctx.lrxqthresh = 2;
2535         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2536         rx_ctx.l2tsel = 1;
2537         rx_ctx.showiv = 1;
2538         rx_ctx.prefena = 1;
2539
2540         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2541         if (err != I40E_SUCCESS) {
2542                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2543                 return err;
2544         }
2545         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2546         if (err != I40E_SUCCESS) {
2547                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2548                 return err;
2549         }
2550
2551         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2552
2553         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2554                 RTE_PKTMBUF_HEADROOM);
2555
2556         /* Check if scattered RX needs to be used. */
2557         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2558                 dev_data->scattered_rx = 1;
2559                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2560         }
2561
2562         /* Init the RX tail regieter. */
2563         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2564
2565         return 0;
2566 }
2567
2568 void
2569 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2570 {
2571         uint16_t i;
2572
2573         PMD_INIT_FUNC_TRACE();
2574
2575         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2576                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2577                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2578         }
2579
2580         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2581                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2582                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2583         }
2584 }
2585
2586 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2587 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2588
2589 enum i40e_status_code
2590 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2591 {
2592         struct i40e_tx_queue *txq;
2593         const struct rte_memzone *tz = NULL;
2594         uint32_t ring_size;
2595         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2596
2597         if (!pf) {
2598                 PMD_DRV_LOG(ERR, "PF is not available");
2599                 return I40E_ERR_BAD_PTR;
2600         }
2601
2602         /* Allocate the TX queue data structure. */
2603         txq = rte_zmalloc_socket("i40e fdir tx queue",
2604                                   sizeof(struct i40e_tx_queue),
2605                                   RTE_CACHE_LINE_SIZE,
2606                                   SOCKET_ID_ANY);
2607         if (!txq) {
2608                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2609                                         "tx queue structure.");
2610                 return I40E_ERR_NO_MEMORY;
2611         }
2612
2613         /* Allocate TX hardware ring descriptors. */
2614         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2615         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2616
2617         tz = i40e_ring_dma_zone_reserve(dev,
2618                                         "fdir_tx_ring",
2619                                         I40E_FDIR_QUEUE_ID,
2620                                         ring_size,
2621                                         SOCKET_ID_ANY);
2622         if (!tz) {
2623                 i40e_dev_tx_queue_release(txq);
2624                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2625                 return I40E_ERR_NO_MEMORY;
2626         }
2627
2628         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2629         txq->queue_id = I40E_FDIR_QUEUE_ID;
2630         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2631         txq->vsi = pf->fdir.fdir_vsi;
2632
2633 #ifdef RTE_LIBRTE_XEN_DOM0
2634         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2635 #else
2636         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2637 #endif
2638         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2639         /*
2640          * don't need to allocate software ring and reset for the fdir
2641          * program queue just set the queue has been configured.
2642          */
2643         txq->q_set = TRUE;
2644         pf->fdir.txq = txq;
2645
2646         return I40E_SUCCESS;
2647 }
2648
2649 enum i40e_status_code
2650 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2651 {
2652         struct i40e_rx_queue *rxq;
2653         const struct rte_memzone *rz = NULL;
2654         uint32_t ring_size;
2655         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2656
2657         if (!pf) {
2658                 PMD_DRV_LOG(ERR, "PF is not available");
2659                 return I40E_ERR_BAD_PTR;
2660         }
2661
2662         /* Allocate the RX queue data structure. */
2663         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2664                                   sizeof(struct i40e_rx_queue),
2665                                   RTE_CACHE_LINE_SIZE,
2666                                   SOCKET_ID_ANY);
2667         if (!rxq) {
2668                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2669                                         "rx queue structure.");
2670                 return I40E_ERR_NO_MEMORY;
2671         }
2672
2673         /* Allocate RX hardware ring descriptors. */
2674         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2675         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2676
2677         rz = i40e_ring_dma_zone_reserve(dev,
2678                                         "fdir_rx_ring",
2679                                         I40E_FDIR_QUEUE_ID,
2680                                         ring_size,
2681                                         SOCKET_ID_ANY);
2682         if (!rz) {
2683                 i40e_dev_rx_queue_release(rxq);
2684                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2685                 return I40E_ERR_NO_MEMORY;
2686         }
2687
2688         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2689         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2690         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2691         rxq->vsi = pf->fdir.fdir_vsi;
2692
2693 #ifdef RTE_LIBRTE_XEN_DOM0
2694         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2695 #else
2696         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2697 #endif
2698         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2699
2700         /*
2701          * Don't need to allocate software ring and reset for the fdir
2702          * rx queue, just set the queue has been configured.
2703          */
2704         rxq->q_set = TRUE;
2705         pf->fdir.rxq = rxq;
2706
2707         return I40E_SUCCESS;
2708 }