drivers/net/i40e/i40e_rxtx.c

   1 /*-
   2  *   BSD LICENSE
   3  *
   4  *   Copyright(c) 2010-2015 Intel Corporation. All rights reserved.
   5  *   All rights reserved.
   6  *
   7  *   Redistribution and use in source and binary forms, with or without
   8  *   modification, are permitted provided that the following conditions
   9  *   are met:
  10  *
  11  *     * Redistributions of source code must retain the above copyright
  12  *       notice, this list of conditions and the following disclaimer.
  13  *     * Redistributions in binary form must reproduce the above copyright
  14  *       notice, this list of conditions and the following disclaimer in
  15  *       the documentation and/or other materials provided with the
  16  *       distribution.
  17  *     * Neither the name of Intel Corporation nor the names of its
  18  *       contributors may be used to endorse or promote products derived
  19  *       from this software without specific prior written permission.
  20  *
  21  *   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  22  *   "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  23  *   LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  24  *   A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  25  *   OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  26  *   SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  27  *   LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  28  *   DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  29  *   THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30  *   (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31  *   OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32  */
  33
  34 #include <stdio.h>
  35 #include <stdlib.h>
  36 #include <string.h>
  37 #include <errno.h>
  38 #include <stdint.h>
  39 #include <stdarg.h>
  40 #include <unistd.h>
  41 #include <inttypes.h>
  42 #include <sys/queue.h>
  43
  44 #include <rte_string_fns.h>
  45 #include <rte_memzone.h>
  46 #include <rte_mbuf.h>
  47 #include <rte_malloc.h>
  48 #include <rte_ether.h>
  49 #include <rte_ethdev.h>
  50 #include <rte_tcp.h>
  51 #include <rte_sctp.h>
  52 #include <rte_udp.h>
  53
  54 #include "i40e_logs.h"
  55 #include "base/i40e_prototype.h"
  56 #include "base/i40e_type.h"
  57 #include "i40e_ethdev.h"
  58 #include "i40e_rxtx.h"
  59
  60 #define I40E_MIN_RING_DESC     64
  61 #define I40E_MAX_RING_DESC     4096
  62 #define I40E_ALIGN             128
  63 #define DEFAULT_TX_RS_THRESH   32
  64 #define DEFAULT_TX_FREE_THRESH 32
  65 #define I40E_MAX_PKT_TYPE      256
  66
  67 #define I40E_TX_MAX_BURST  32
  68
  69 #define I40E_DMA_MEM_ALIGN 4096
  70
  71 #define I40E_SIMPLE_FLAGS ((uint32_t)ETH_TXQ_FLAGS_NOMULTSEGS | \
  72                                         ETH_TXQ_FLAGS_NOOFFLOADS)
  73
  74 #define I40E_TXD_CMD (I40E_TX_DESC_CMD_EOP | I40E_TX_DESC_CMD_RS)
  75
  76 #define I40E_TX_CKSUM_OFFLOAD_MASK (             \
  77                 PKT_TX_IP_CKSUM |                \
  78                 PKT_TX_L4_MASK |                 \
  79                 PKT_TX_OUTER_IP_CKSUM)
  80
  81 #define RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb) \
  82         (uint64_t) ((mb)->buf_physaddr + RTE_PKTMBUF_HEADROOM)
  83
  84 #define RTE_MBUF_DATA_DMA_ADDR(mb) \
  85         ((uint64_t)((mb)->buf_physaddr + (mb)->data_off))
  86
  87 static const struct rte_memzone *
  88 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
  89                            const char *ring_name,
  90                            uint16_t queue_id,
  91                            uint32_t ring_size,
  92                            int socket_id);
  93 static uint16_t i40e_xmit_pkts_simple(void *tx_queue,
  94                                       struct rte_mbuf **tx_pkts,
  95                                       uint16_t nb_pkts);
  96
  97 static inline void
  98 i40e_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union i40e_rx_desc *rxdp)
  99 {
 100         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 101                 (1 << I40E_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 102                 mb->ol_flags |= PKT_RX_VLAN_PKT;
 103                 mb->vlan_tci =
 104                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 105                 PMD_RX_LOG(DEBUG, "Descriptor l2tag1: %u",
 106                            rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1));
 107         } else {
 108                 mb->vlan_tci = 0;
 109         }
 110 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 111         if (rte_le_to_cpu_16(rxdp->wb.qword2.ext_status) &
 112                 (1 << I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT)) {
 113                 mb->ol_flags |= PKT_RX_QINQ_PKT;
 114                 mb->vlan_tci_outer = mb->vlan_tci;
 115                 mb->vlan_tci = rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2);
 116                 PMD_RX_LOG(DEBUG, "Descriptor l2tag2_1: %u, l2tag2_2: %u",
 117                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_1),
 118                            rte_le_to_cpu_16(rxdp->wb.qword2.l2tag2_2));
 119         } else {
 120                 mb->vlan_tci_outer = 0;
 121         }
 122 #endif
 123         PMD_RX_LOG(DEBUG, "Mbuf vlan_tci: %u, vlan_tci_outer: %u",
 124                    mb->vlan_tci, mb->vlan_tci_outer);
 125 }
 126
 127 /* Translate the rx descriptor status to pkt flags */
 128 static inline uint64_t
 129 i40e_rxd_status_to_pkt_flags(uint64_t qword)
 130 {
 131         uint64_t flags;
 132
 133         /* Check if RSS_HASH */
 134         flags = (((qword >> I40E_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 135                                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ==
 136                         I40E_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 137
 138         /* Check if FDIR Match */
 139         flags |= (qword & (1 << I40E_RX_DESC_STATUS_FLM_SHIFT) ?
 140                                                         PKT_RX_FDIR : 0);
 141
 142         return flags;
 143 }
 144
 145 static inline uint64_t
 146 i40e_rxd_error_to_pkt_flags(uint64_t qword)
 147 {
 148         uint64_t flags = 0;
 149         uint64_t error_bits = (qword >> I40E_RXD_QW1_ERROR_SHIFT);
 150
 151 #define I40E_RX_ERR_BITS 0x3f
 152         if (likely((error_bits & I40E_RX_ERR_BITS) == 0))
 153                 return flags;
 154         /* If RXE bit set, all other status bits are meaningless */
 155         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RXE_SHIFT))) {
 156                 flags |= PKT_RX_MAC_ERR;
 157                 return flags;
 158         }
 159
 160         /* If RECIPE bit set, all other status indications should be ignored */
 161         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_RECIPE_SHIFT))) {
 162                 flags |= PKT_RX_RECIP_ERR;
 163                 return flags;
 164         }
 165         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_HBO_SHIFT)))
 166                 flags |= PKT_RX_HBUF_OVERFLOW;
 167         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_IPE_SHIFT)))
 168                 flags |= PKT_RX_IP_CKSUM_BAD;
 169         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_L4E_SHIFT)))
 170                 flags |= PKT_RX_L4_CKSUM_BAD;
 171         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_EIPE_SHIFT)))
 172                 flags |= PKT_RX_EIP_CKSUM_BAD;
 173         if (unlikely(error_bits & (1 << I40E_RX_DESC_ERROR_OVERSIZE_SHIFT)))
 174                 flags |= PKT_RX_OVERSIZE;
 175
 176         return flags;
 177 }
 178
 179 /* Translate pkt types to pkt flags */
 180 static inline uint64_t
 181 i40e_rxd_ptype_to_pkt_flags(uint64_t qword)
 182 {
 183         uint8_t ptype = (uint8_t)((qword & I40E_RXD_QW1_PTYPE_MASK) >>
 184                                         I40E_RXD_QW1_PTYPE_SHIFT);
 185         static const uint64_t ip_ptype_map[I40E_MAX_PKT_TYPE] = {
 186                 0, /* PTYPE 0 */
 187                 0, /* PTYPE 1 */
 188                 0, /* PTYPE 2 */
 189                 0, /* PTYPE 3 */
 190                 0, /* PTYPE 4 */
 191                 0, /* PTYPE 5 */
 192                 0, /* PTYPE 6 */
 193                 0, /* PTYPE 7 */
 194                 0, /* PTYPE 8 */
 195                 0, /* PTYPE 9 */
 196                 0, /* PTYPE 10 */
 197                 0, /* PTYPE 11 */
 198                 0, /* PTYPE 12 */
 199                 0, /* PTYPE 13 */
 200                 0, /* PTYPE 14 */
 201                 0, /* PTYPE 15 */
 202                 0, /* PTYPE 16 */
 203                 0, /* PTYPE 17 */
 204                 0, /* PTYPE 18 */
 205                 0, /* PTYPE 19 */
 206                 0, /* PTYPE 20 */
 207                 0, /* PTYPE 21 */
 208                 PKT_RX_IPV4_HDR, /* PTYPE 22 */
 209                 PKT_RX_IPV4_HDR, /* PTYPE 23 */
 210                 PKT_RX_IPV4_HDR, /* PTYPE 24 */
 211                 0, /* PTYPE 25 */
 212                 PKT_RX_IPV4_HDR, /* PTYPE 26 */
 213                 PKT_RX_IPV4_HDR, /* PTYPE 27 */
 214                 PKT_RX_IPV4_HDR, /* PTYPE 28 */
 215                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 29 */
 216                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 30 */
 217                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 31 */
 218                 0, /* PTYPE 32 */
 219                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 33 */
 220                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 34 */
 221                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 35 */
 222                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 36 */
 223                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 37 */
 224                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 38 */
 225                 0, /* PTYPE 39 */
 226                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 40 */
 227                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 41 */
 228                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 42 */
 229                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 43 */
 230                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 44 */
 231                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 45 */
 232                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 46 */
 233                 0, /* PTYPE 47 */
 234                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 48 */
 235                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 49 */
 236                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 50 */
 237                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 51 */
 238                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 52 */
 239                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 53 */
 240                 0, /* PTYPE 54 */
 241                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 55 */
 242                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 56 */
 243                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 57 */
 244                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 58 */
 245                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 59 */
 246                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 60 */
 247                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 61 */
 248                 0, /* PTYPE 62 */
 249                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 63 */
 250                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 64 */
 251                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 65 */
 252                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 66 */
 253                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 67 */
 254                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 68 */
 255                 0, /* PTYPE 69 */
 256                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 70 */
 257                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 71 */
 258                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 72 */
 259                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 73 */
 260                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 74 */
 261                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 75 */
 262                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 76 */
 263                 0, /* PTYPE 77 */
 264                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 78 */
 265                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 79 */
 266                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 80 */
 267                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 81 */
 268                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 82 */
 269                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 83 */
 270                 0, /* PTYPE 84 */
 271                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 85 */
 272                 PKT_RX_TUNNEL_IPV4_HDR, /* PTYPE 86 */
 273                 PKT_RX_IPV4_HDR_EXT, /* PTYPE 87 */
 274                 PKT_RX_IPV6_HDR, /* PTYPE 88 */
 275                 PKT_RX_IPV6_HDR, /* PTYPE 89 */
 276                 PKT_RX_IPV6_HDR, /* PTYPE 90 */
 277                 0, /* PTYPE 91 */
 278                 PKT_RX_IPV6_HDR, /* PTYPE 92 */
 279                 PKT_RX_IPV6_HDR, /* PTYPE 93 */
 280                 PKT_RX_IPV6_HDR, /* PTYPE 94 */
 281                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 95 */
 282                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 96 */
 283                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 97 */
 284                 0, /* PTYPE 98 */
 285                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 99 */
 286                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 100 */
 287                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 101 */
 288                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 102 */
 289                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 103 */
 290                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 104 */
 291                 0, /* PTYPE 105 */
 292                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 106 */
 293                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 107 */
 294                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 108 */
 295                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 109 */
 296                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 110 */
 297                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 111 */
 298                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 112 */
 299                 0, /* PTYPE 113 */
 300                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 114 */
 301                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 115 */
 302                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 116 */
 303                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 117 */
 304                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 118 */
 305                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 119 */
 306                 0, /* PTYPE 120 */
 307                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 121 */
 308                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 122 */
 309                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 123 */
 310                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 124 */
 311                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 125 */
 312                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 126 */
 313                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 127 */
 314                 0, /* PTYPE 128 */
 315                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 129 */
 316                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 130 */
 317                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 131 */
 318                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 132 */
 319                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 133 */
 320                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 134 */
 321                 0, /* PTYPE 135 */
 322                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 136 */
 323                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 137 */
 324                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 138 */
 325                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 139 */
 326                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 140 */
 327                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 141 */
 328                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 142 */
 329                 0, /* PTYPE 143 */
 330                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 144 */
 331                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 145 */
 332                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 146 */
 333                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 147 */
 334                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 148 */
 335                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 149 */
 336                 0, /* PTYPE 150 */
 337                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 151 */
 338                 PKT_RX_TUNNEL_IPV6_HDR, /* PTYPE 152 */
 339                 PKT_RX_IPV6_HDR_EXT, /* PTYPE 153 */
 340                 0, /* PTYPE 154 */
 341                 0, /* PTYPE 155 */
 342                 0, /* PTYPE 156 */
 343                 0, /* PTYPE 157 */
 344                 0, /* PTYPE 158 */
 345                 0, /* PTYPE 159 */
 346                 0, /* PTYPE 160 */
 347                 0, /* PTYPE 161 */
 348                 0, /* PTYPE 162 */
 349                 0, /* PTYPE 163 */
 350                 0, /* PTYPE 164 */
 351                 0, /* PTYPE 165 */
 352                 0, /* PTYPE 166 */
 353                 0, /* PTYPE 167 */
 354                 0, /* PTYPE 168 */
 355                 0, /* PTYPE 169 */
 356                 0, /* PTYPE 170 */
 357                 0, /* PTYPE 171 */
 358                 0, /* PTYPE 172 */
 359                 0, /* PTYPE 173 */
 360                 0, /* PTYPE 174 */
 361                 0, /* PTYPE 175 */
 362                 0, /* PTYPE 176 */
 363                 0, /* PTYPE 177 */
 364                 0, /* PTYPE 178 */
 365                 0, /* PTYPE 179 */
 366                 0, /* PTYPE 180 */
 367                 0, /* PTYPE 181 */
 368                 0, /* PTYPE 182 */
 369                 0, /* PTYPE 183 */
 370                 0, /* PTYPE 184 */
 371                 0, /* PTYPE 185 */
 372                 0, /* PTYPE 186 */
 373                 0, /* PTYPE 187 */
 374                 0, /* PTYPE 188 */
 375                 0, /* PTYPE 189 */
 376                 0, /* PTYPE 190 */
 377                 0, /* PTYPE 191 */
 378                 0, /* PTYPE 192 */
 379                 0, /* PTYPE 193 */
 380                 0, /* PTYPE 194 */
 381                 0, /* PTYPE 195 */
 382                 0, /* PTYPE 196 */
 383                 0, /* PTYPE 197 */
 384                 0, /* PTYPE 198 */
 385                 0, /* PTYPE 199 */
 386                 0, /* PTYPE 200 */
 387                 0, /* PTYPE 201 */
 388                 0, /* PTYPE 202 */
 389                 0, /* PTYPE 203 */
 390                 0, /* PTYPE 204 */
 391                 0, /* PTYPE 205 */
 392                 0, /* PTYPE 206 */
 393                 0, /* PTYPE 207 */
 394                 0, /* PTYPE 208 */
 395                 0, /* PTYPE 209 */
 396                 0, /* PTYPE 210 */
 397                 0, /* PTYPE 211 */
 398                 0, /* PTYPE 212 */
 399                 0, /* PTYPE 213 */
 400                 0, /* PTYPE 214 */
 401                 0, /* PTYPE 215 */
 402                 0, /* PTYPE 216 */
 403                 0, /* PTYPE 217 */
 404                 0, /* PTYPE 218 */
 405                 0, /* PTYPE 219 */
 406                 0, /* PTYPE 220 */
 407                 0, /* PTYPE 221 */
 408                 0, /* PTYPE 222 */
 409                 0, /* PTYPE 223 */
 410                 0, /* PTYPE 224 */
 411                 0, /* PTYPE 225 */
 412                 0, /* PTYPE 226 */
 413                 0, /* PTYPE 227 */
 414                 0, /* PTYPE 228 */
 415                 0, /* PTYPE 229 */
 416                 0, /* PTYPE 230 */
 417                 0, /* PTYPE 231 */
 418                 0, /* PTYPE 232 */
 419                 0, /* PTYPE 233 */
 420                 0, /* PTYPE 234 */
 421                 0, /* PTYPE 235 */
 422                 0, /* PTYPE 236 */
 423                 0, /* PTYPE 237 */
 424                 0, /* PTYPE 238 */
 425                 0, /* PTYPE 239 */
 426                 0, /* PTYPE 240 */
 427                 0, /* PTYPE 241 */
 428                 0, /* PTYPE 242 */
 429                 0, /* PTYPE 243 */
 430                 0, /* PTYPE 244 */
 431                 0, /* PTYPE 245 */
 432                 0, /* PTYPE 246 */
 433                 0, /* PTYPE 247 */
 434                 0, /* PTYPE 248 */
 435                 0, /* PTYPE 249 */
 436                 0, /* PTYPE 250 */
 437                 0, /* PTYPE 251 */
 438                 0, /* PTYPE 252 */
 439                 0, /* PTYPE 253 */
 440                 0, /* PTYPE 254 */
 441                 0, /* PTYPE 255 */
 442         };
 443
 444         return ip_ptype_map[ptype];
 445 }
 446
 447 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK   0x03
 448 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID  0x01
 449 #define I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX   0x02
 450 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK   0x03
 451 #define I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX   0x01
 452
 453 static inline uint64_t
 454 i40e_rxd_build_fdir(volatile union i40e_rx_desc *rxdp, struct rte_mbuf *mb)
 455 {
 456         uint64_t flags = 0;
 457 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
 458         uint16_t flexbh, flexbl;
 459
 460         flexbh = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 461                 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT) &
 462                 I40E_RX_DESC_EXT_STATUS_FLEXBH_MASK;
 463         flexbl = (rte_le_to_cpu_32(rxdp->wb.qword2.ext_status) >>
 464                 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT) &
 465                 I40E_RX_DESC_EXT_STATUS_FLEXBL_MASK;
 466
 467
 468         if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FD_ID) {
 469                 mb->hash.fdir.hi =
 470                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.fd_id);
 471                 flags |= PKT_RX_FDIR_ID;
 472         } else if (flexbh == I40E_RX_DESC_EXT_STATUS_FLEXBH_FLEX) {
 473                 mb->hash.fdir.hi =
 474                         rte_le_to_cpu_32(rxdp->wb.qword3.hi_dword.flex_bytes_hi);
 475                 flags |= PKT_RX_FDIR_FLX;
 476         }
 477         if (flexbl == I40E_RX_DESC_EXT_STATUS_FLEXBL_FLEX) {
 478                 mb->hash.fdir.lo =
 479                         rte_le_to_cpu_32(rxdp->wb.qword3.lo_dword.flex_bytes_lo);
 480                 flags |= PKT_RX_FDIR_FLX;
 481         }
 482 #else
 483         mb->hash.fdir.hi =
 484                 rte_le_to_cpu_32(rxdp->wb.qword0.hi_dword.fd_id);
 485         flags |= PKT_RX_FDIR_ID;
 486 #endif
 487         return flags;
 488 }
 489 static inline void
 490 i40e_txd_enable_checksum(uint64_t ol_flags,
 491                         uint32_t *td_cmd,
 492                         uint32_t *td_offset,
 493                         union i40e_tx_offload tx_offload,
 494                         uint32_t *cd_tunneling)
 495 {
 496         /* UDP tunneling packet TX checksum offload */
 497         if (ol_flags & PKT_TX_OUTER_IP_CKSUM) {
 498
 499                 *td_offset |= (tx_offload.outer_l2_len >> 1)
 500                                 << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 501
 502                 if (ol_flags & PKT_TX_OUTER_IP_CKSUM)
 503                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4;
 504                 else if (ol_flags & PKT_TX_OUTER_IPV4)
 505                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM;
 506                 else if (ol_flags & PKT_TX_OUTER_IPV6)
 507                         *cd_tunneling |= I40E_TX_CTX_EXT_IP_IPV6;
 508
 509                 /* Now set the ctx descriptor fields */
 510                 *cd_tunneling |= (tx_offload.outer_l3_len >> 2) <<
 511                                 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT |
 512                                 (tx_offload.l2_len >> 1) <<
 513                                 I40E_TXD_CTX_QW0_NATLEN_SHIFT;
 514
 515         } else
 516                 *td_offset |= (tx_offload.l2_len >> 1)
 517                         << I40E_TX_DESC_LENGTH_MACLEN_SHIFT;
 518
 519         /* Enable L3 checksum offloads */
 520         if (ol_flags & PKT_TX_IP_CKSUM) {
 521                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4_CSUM;
 522                 *td_offset |= (tx_offload.l3_len >> 2)
 523                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 524         } else if (ol_flags & PKT_TX_IPV4) {
 525                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV4;
 526                 *td_offset |= (tx_offload.l3_len >> 2)
 527                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 528         } else if (ol_flags & PKT_TX_IPV6) {
 529                 *td_cmd |= I40E_TX_DESC_CMD_IIPT_IPV6;
 530                 *td_offset |= (tx_offload.l3_len >> 2)
 531                                 << I40E_TX_DESC_LENGTH_IPLEN_SHIFT;
 532         }
 533
 534         if (ol_flags & PKT_TX_TCP_SEG) {
 535                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 536                 *td_offset |= (tx_offload.l4_len >> 2)
 537                         << I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 538                 return;
 539         }
 540
 541         /* Enable L4 checksum offloads */
 542         switch (ol_flags & PKT_TX_L4_MASK) {
 543         case PKT_TX_TCP_CKSUM:
 544                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_TCP;
 545                 *td_offset |= (sizeof(struct tcp_hdr) >> 2) <<
 546                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 547                 break;
 548         case PKT_TX_SCTP_CKSUM:
 549                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_SCTP;
 550                 *td_offset |= (sizeof(struct sctp_hdr) >> 2) <<
 551                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 552                 break;
 553         case PKT_TX_UDP_CKSUM:
 554                 *td_cmd |= I40E_TX_DESC_CMD_L4T_EOFT_UDP;
 555                 *td_offset |= (sizeof(struct udp_hdr) >> 2) <<
 556                                 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
 557                 break;
 558         default:
 559                 break;
 560         }
 561 }
 562
 563 static inline struct rte_mbuf *
 564 rte_rxmbuf_alloc(struct rte_mempool *mp)
 565 {
 566         struct rte_mbuf *m;
 567
 568         m = __rte_mbuf_raw_alloc(mp);
 569         __rte_mbuf_sanity_check_raw(m, 0);
 570
 571         return m;
 572 }
 573
 574 /* Construct the tx flags */
 575 static inline uint64_t
 576 i40e_build_ctob(uint32_t td_cmd,
 577                 uint32_t td_offset,
 578                 unsigned int size,
 579                 uint32_t td_tag)
 580 {
 581         return rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DATA |
 582                         ((uint64_t)td_cmd  << I40E_TXD_QW1_CMD_SHIFT) |
 583                         ((uint64_t)td_offset << I40E_TXD_QW1_OFFSET_SHIFT) |
 584                         ((uint64_t)size  << I40E_TXD_QW1_TX_BUF_SZ_SHIFT) |
 585                         ((uint64_t)td_tag  << I40E_TXD_QW1_L2TAG1_SHIFT));
 586 }
 587
 588 static inline int
 589 i40e_xmit_cleanup(struct i40e_tx_queue *txq)
 590 {
 591         struct i40e_tx_entry *sw_ring = txq->sw_ring;
 592         volatile struct i40e_tx_desc *txd = txq->tx_ring;
 593         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
 594         uint16_t nb_tx_desc = txq->nb_tx_desc;
 595         uint16_t desc_to_clean_to;
 596         uint16_t nb_tx_to_clean;
 597
 598         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->tx_rs_thresh);
 599         if (desc_to_clean_to >= nb_tx_desc)
 600                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
 601
 602         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
 603         if (!(txd[desc_to_clean_to].cmd_type_offset_bsz &
 604                 rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE))) {
 605                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
 606                         "(port=%d queue=%d)", desc_to_clean_to,
 607                                 txq->port_id, txq->queue_id);
 608                 return -1;
 609         }
 610
 611         if (last_desc_cleaned > desc_to_clean_to)
 612                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
 613                                                         desc_to_clean_to);
 614         else
 615                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
 616                                         last_desc_cleaned);
 617
 618         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
 619
 620         txq->last_desc_cleaned = desc_to_clean_to;
 621         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + nb_tx_to_clean);
 622
 623         return 0;
 624 }
 625
 626 static inline int
 627 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 628 check_rx_burst_bulk_alloc_preconditions(struct i40e_rx_queue *rxq)
 629 #else
 630 check_rx_burst_bulk_alloc_preconditions(__rte_unused struct i40e_rx_queue *rxq)
 631 #endif
 632 {
 633         int ret = 0;
 634
 635 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 636         if (!(rxq->rx_free_thresh >= RTE_PMD_I40E_RX_MAX_BURST)) {
 637                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 638                              "rxq->rx_free_thresh=%d, "
 639                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 640                              rxq->rx_free_thresh, RTE_PMD_I40E_RX_MAX_BURST);
 641                 ret = -EINVAL;
 642         } else if (!(rxq->rx_free_thresh < rxq->nb_rx_desc)) {
 643                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 644                              "rxq->rx_free_thresh=%d, "
 645                              "rxq->nb_rx_desc=%d",
 646                              rxq->rx_free_thresh, rxq->nb_rx_desc);
 647                 ret = -EINVAL;
 648         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 649                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 650                              "rxq->nb_rx_desc=%d, "
 651                              "rxq->rx_free_thresh=%d",
 652                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 653                 ret = -EINVAL;
 654         } else if (!(rxq->nb_rx_desc < (I40E_MAX_RING_DESC -
 655                                 RTE_PMD_I40E_RX_MAX_BURST))) {
 656                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 657                              "rxq->nb_rx_desc=%d, "
 658                              "I40E_MAX_RING_DESC=%d, "
 659                              "RTE_PMD_I40E_RX_MAX_BURST=%d",
 660                              rxq->nb_rx_desc, I40E_MAX_RING_DESC,
 661                              RTE_PMD_I40E_RX_MAX_BURST);
 662                 ret = -EINVAL;
 663         }
 664 #else
 665         ret = -EINVAL;
 666 #endif
 667
 668         return ret;
 669 }
 670
 671 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
 672 #define I40E_LOOK_AHEAD 8
 673 #if (I40E_LOOK_AHEAD != 8)
 674 #error "PMD I40E: I40E_LOOK_AHEAD must be 8\n"
 675 #endif
 676 static inline int
 677 i40e_rx_scan_hw_ring(struct i40e_rx_queue *rxq)
 678 {
 679         volatile union i40e_rx_desc *rxdp;
 680         struct i40e_rx_entry *rxep;
 681         struct rte_mbuf *mb;
 682         uint16_t pkt_len;
 683         uint64_t qword1;
 684         uint32_t rx_status;
 685         int32_t s[I40E_LOOK_AHEAD], nb_dd;
 686         int32_t i, j, nb_rx = 0;
 687         uint64_t pkt_flags;
 688
 689         rxdp = &rxq->rx_ring[rxq->rx_tail];
 690         rxep = &rxq->sw_ring[rxq->rx_tail];
 691
 692         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 693         rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 694                                 I40E_RXD_QW1_STATUS_SHIFT;
 695
 696         /* Make sure there is at least 1 packet to receive */
 697         if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 698                 return 0;
 699
 700         /**
 701          * Scan LOOK_AHEAD descriptors at a time to determine which
 702          * descriptors reference packets that are ready to be received.
 703          */
 704         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; i+=I40E_LOOK_AHEAD,
 705                         rxdp += I40E_LOOK_AHEAD, rxep += I40E_LOOK_AHEAD) {
 706                 /* Read desc statuses backwards to avoid race condition */
 707                 for (j = I40E_LOOK_AHEAD - 1; j >= 0; j--) {
 708                         qword1 = rte_le_to_cpu_64(\
 709                                 rxdp[j].wb.qword1.status_error_len);
 710                         s[j] = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
 711                                         I40E_RXD_QW1_STATUS_SHIFT;
 712                 }
 713
 714                 /* Compute how many status bits were set */
 715                 for (j = 0, nb_dd = 0; j < I40E_LOOK_AHEAD; j++)
 716                         nb_dd += s[j] & (1 << I40E_RX_DESC_STATUS_DD_SHIFT);
 717
 718                 nb_rx += nb_dd;
 719
 720                 /* Translate descriptor info to mbuf parameters */
 721                 for (j = 0; j < nb_dd; j++) {
 722                         mb = rxep[j].mbuf;
 723                         qword1 = rte_le_to_cpu_64(\
 724                                 rxdp[j].wb.qword1.status_error_len);
 725                         pkt_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 726                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 727                         mb->data_len = pkt_len;
 728                         mb->pkt_len = pkt_len;
 729                         mb->ol_flags = 0;
 730                         i40e_rxd_to_vlan_tci(mb, &rxdp[j]);
 731                         pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 732                         pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 733                         pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 734
 735                         mb->packet_type = (uint16_t)((qword1 &
 736                                         I40E_RXD_QW1_PTYPE_MASK) >>
 737                                         I40E_RXD_QW1_PTYPE_SHIFT);
 738                         if (pkt_flags & PKT_RX_RSS_HASH)
 739                                 mb->hash.rss = rte_le_to_cpu_32(\
 740                                         rxdp[j].wb.qword0.hi_dword.rss);
 741                         if (pkt_flags & PKT_RX_FDIR)
 742                                 pkt_flags |= i40e_rxd_build_fdir(&rxdp[j], mb);
 743
 744                         mb->ol_flags |= pkt_flags;
 745                 }
 746
 747                 for (j = 0; j < I40E_LOOK_AHEAD; j++)
 748                         rxq->rx_stage[i + j] = rxep[j].mbuf;
 749
 750                 if (nb_dd != I40E_LOOK_AHEAD)
 751                         break;
 752         }
 753
 754         /* Clear software ring entries */
 755         for (i = 0; i < nb_rx; i++)
 756                 rxq->sw_ring[rxq->rx_tail + i].mbuf = NULL;
 757
 758         return nb_rx;
 759 }
 760
 761 static inline uint16_t
 762 i40e_rx_fill_from_stage(struct i40e_rx_queue *rxq,
 763                         struct rte_mbuf **rx_pkts,
 764                         uint16_t nb_pkts)
 765 {
 766         uint16_t i;
 767         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
 768
 769         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
 770
 771         for (i = 0; i < nb_pkts; i++)
 772                 rx_pkts[i] = stage[i];
 773
 774         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
 775         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
 776
 777         return nb_pkts;
 778 }
 779
 780 static inline int
 781 i40e_rx_alloc_bufs(struct i40e_rx_queue *rxq)
 782 {
 783         volatile union i40e_rx_desc *rxdp;
 784         struct i40e_rx_entry *rxep;
 785         struct rte_mbuf *mb;
 786         uint16_t alloc_idx, i;
 787         uint64_t dma_addr;
 788         int diag;
 789
 790         /* Allocate buffers in bulk */
 791         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
 792                                 (rxq->rx_free_thresh - 1));
 793         rxep = &(rxq->sw_ring[alloc_idx]);
 794         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
 795                                         rxq->rx_free_thresh);
 796         if (unlikely(diag != 0)) {
 797                 PMD_DRV_LOG(ERR, "Failed to get mbufs in bulk");
 798                 return -ENOMEM;
 799         }
 800
 801         rxdp = &rxq->rx_ring[alloc_idx];
 802         for (i = 0; i < rxq->rx_free_thresh; i++) {
 803                 mb = rxep[i].mbuf;
 804                 rte_mbuf_refcnt_set(mb, 1);
 805                 mb->next = NULL;
 806                 mb->data_off = RTE_PKTMBUF_HEADROOM;
 807                 mb->nb_segs = 1;
 808                 mb->port = rxq->port_id;
 809                 dma_addr = rte_cpu_to_le_64(\
 810                         RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mb));
 811                 rxdp[i].read.hdr_addr = dma_addr;
 812                 rxdp[i].read.pkt_addr = dma_addr;
 813         }
 814
 815         /* Update rx tail regsiter */
 816         rte_wmb();
 817         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->rx_free_trigger);
 818
 819         rxq->rx_free_trigger =
 820                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
 821         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
 822                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 823
 824         return 0;
 825 }
 826
 827 static inline uint16_t
 828 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 829 {
 830         struct i40e_rx_queue *rxq = (struct i40e_rx_queue *)rx_queue;
 831         uint16_t nb_rx = 0;
 832
 833         if (!nb_pkts)
 834                 return 0;
 835
 836         if (rxq->rx_nb_avail)
 837                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 838
 839         nb_rx = (uint16_t)i40e_rx_scan_hw_ring(rxq);
 840         rxq->rx_next_avail = 0;
 841         rxq->rx_nb_avail = nb_rx;
 842         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
 843
 844         if (rxq->rx_tail > rxq->rx_free_trigger) {
 845                 if (i40e_rx_alloc_bufs(rxq) != 0) {
 846                         uint16_t i, j;
 847
 848                         PMD_RX_LOG(DEBUG, "Rx mbuf alloc failed for "
 849                                    "port_id=%u, queue_id=%u",
 850                                    rxq->port_id, rxq->queue_id);
 851                         rxq->rx_nb_avail = 0;
 852                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
 853                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
 854                                 rxq->sw_ring[j].mbuf = rxq->rx_stage[i];
 855
 856                         return 0;
 857                 }
 858         }
 859
 860         if (rxq->rx_tail >= rxq->nb_rx_desc)
 861                 rxq->rx_tail = 0;
 862
 863         if (rxq->rx_nb_avail)
 864                 return i40e_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
 865
 866         return 0;
 867 }
 868
 869 static uint16_t
 870 i40e_recv_pkts_bulk_alloc(void *rx_queue,
 871                           struct rte_mbuf **rx_pkts,
 872                           uint16_t nb_pkts)
 873 {
 874         uint16_t nb_rx = 0, n, count;
 875
 876         if (unlikely(nb_pkts == 0))
 877                 return 0;
 878
 879         if (likely(nb_pkts <= RTE_PMD_I40E_RX_MAX_BURST))
 880                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
 881
 882         while (nb_pkts) {
 883                 n = RTE_MIN(nb_pkts, RTE_PMD_I40E_RX_MAX_BURST);
 884                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
 885                 nb_rx = (uint16_t)(nb_rx + count);
 886                 nb_pkts = (uint16_t)(nb_pkts - count);
 887                 if (count < n)
 888                         break;
 889         }
 890
 891         return nb_rx;
 892 }
 893 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
 894
 895 uint16_t
 896 i40e_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 897 {
 898         struct i40e_rx_queue *rxq;
 899         volatile union i40e_rx_desc *rx_ring;
 900         volatile union i40e_rx_desc *rxdp;
 901         union i40e_rx_desc rxd;
 902         struct i40e_rx_entry *sw_ring;
 903         struct i40e_rx_entry *rxe;
 904         struct rte_mbuf *rxm;
 905         struct rte_mbuf *nmb;
 906         uint16_t nb_rx;
 907         uint32_t rx_status;
 908         uint64_t qword1;
 909         uint16_t rx_packet_len;
 910         uint16_t rx_id, nb_hold;
 911         uint64_t dma_addr;
 912         uint64_t pkt_flags;
 913
 914         nb_rx = 0;
 915         nb_hold = 0;
 916         rxq = rx_queue;
 917         rx_id = rxq->rx_tail;
 918         rx_ring = rxq->rx_ring;
 919         sw_ring = rxq->sw_ring;
 920
 921         while (nb_rx < nb_pkts) {
 922                 rxdp = &rx_ring[rx_id];
 923                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 924                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK)
 925                                 >> I40E_RXD_QW1_STATUS_SHIFT;
 926                 /* Check the DD bit first */
 927                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
 928                         break;
 929
 930                 nmb = rte_rxmbuf_alloc(rxq->mp);
 931                 if (unlikely(!nmb))
 932                         break;
 933                 rxd = *rxdp;
 934
 935                 nb_hold++;
 936                 rxe = &sw_ring[rx_id];
 937                 rx_id++;
 938                 if (unlikely(rx_id == rxq->nb_rx_desc))
 939                         rx_id = 0;
 940
 941                 /* Prefetch next mbuf */
 942                 rte_prefetch0(sw_ring[rx_id].mbuf);
 943
 944                 /**
 945                  * When next RX descriptor is on a cache line boundary,
 946                  * prefetch the next 4 RX descriptors and next 8 pointers
 947                  * to mbufs.
 948                  */
 949                 if ((rx_id & 0x3) == 0) {
 950                         rte_prefetch0(&rx_ring[rx_id]);
 951                         rte_prefetch0(&sw_ring[rx_id]);
 952                 }
 953                 rxm = rxe->mbuf;
 954                 rxe->mbuf = nmb;
 955                 dma_addr =
 956                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
 957                 rxdp->read.hdr_addr = dma_addr;
 958                 rxdp->read.pkt_addr = dma_addr;
 959
 960                 rx_packet_len = ((qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
 961                                 I40E_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 962
 963                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 964                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 965                 rxm->nb_segs = 1;
 966                 rxm->next = NULL;
 967                 rxm->pkt_len = rx_packet_len;
 968                 rxm->data_len = rx_packet_len;
 969                 rxm->port = rxq->port_id;
 970                 rxm->ol_flags = 0;
 971                 i40e_rxd_to_vlan_tci(rxm, &rxd);
 972                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
 973                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
 974                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
 975                 rxm->packet_type = (uint16_t)((qword1 & I40E_RXD_QW1_PTYPE_MASK) >>
 976                                 I40E_RXD_QW1_PTYPE_SHIFT);
 977                 if (pkt_flags & PKT_RX_RSS_HASH)
 978                         rxm->hash.rss =
 979                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 980                 if (pkt_flags & PKT_RX_FDIR)
 981                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
 982
 983                 rxm->ol_flags |= pkt_flags;
 984
 985                 rx_pkts[nb_rx++] = rxm;
 986         }
 987         rxq->rx_tail = rx_id;
 988
 989         /**
 990          * If the number of free RX descriptors is greater than the RX free
 991          * threshold of the queue, advance the receive tail register of queue.
 992          * Update that register with the value of the last processed RX
 993          * descriptor minus 1.
 994          */
 995         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 996         if (nb_hold > rxq->rx_free_thresh) {
 997                 rx_id = (uint16_t) ((rx_id == 0) ?
 998                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 999                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1000                 nb_hold = 0;
1001         }
1002         rxq->nb_rx_hold = nb_hold;
1003
1004         return nb_rx;
1005 }
1006
1007 uint16_t
1008 i40e_recv_scattered_pkts(void *rx_queue,
1009                          struct rte_mbuf **rx_pkts,
1010                          uint16_t nb_pkts)
1011 {
1012         struct i40e_rx_queue *rxq = rx_queue;
1013         volatile union i40e_rx_desc *rx_ring = rxq->rx_ring;
1014         volatile union i40e_rx_desc *rxdp;
1015         union i40e_rx_desc rxd;
1016         struct i40e_rx_entry *sw_ring = rxq->sw_ring;
1017         struct i40e_rx_entry *rxe;
1018         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1019         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1020         struct rte_mbuf *nmb, *rxm;
1021         uint16_t rx_id = rxq->rx_tail;
1022         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1023         uint32_t rx_status;
1024         uint64_t qword1;
1025         uint64_t dma_addr;
1026         uint64_t pkt_flags;
1027
1028         while (nb_rx < nb_pkts) {
1029                 rxdp = &rx_ring[rx_id];
1030                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1031                 rx_status = (qword1 & I40E_RXD_QW1_STATUS_MASK) >>
1032                                         I40E_RXD_QW1_STATUS_SHIFT;
1033                 /* Check the DD bit */
1034                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
1035                         break;
1036
1037                 nmb = rte_rxmbuf_alloc(rxq->mp);
1038                 if (unlikely(!nmb))
1039                         break;
1040                 rxd = *rxdp;
1041                 nb_hold++;
1042                 rxe = &sw_ring[rx_id];
1043                 rx_id++;
1044                 if (rx_id == rxq->nb_rx_desc)
1045                         rx_id = 0;
1046
1047                 /* Prefetch next mbuf */
1048                 rte_prefetch0(sw_ring[rx_id].mbuf);
1049
1050                 /**
1051                  * When next RX descriptor is on a cache line boundary,
1052                  * prefetch the next 4 RX descriptors and next 8 pointers
1053                  * to mbufs.
1054                  */
1055                 if ((rx_id & 0x3) == 0) {
1056                         rte_prefetch0(&rx_ring[rx_id]);
1057                         rte_prefetch0(&sw_ring[rx_id]);
1058                 }
1059
1060                 rxm = rxe->mbuf;
1061                 rxe->mbuf = nmb;
1062                 dma_addr =
1063                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(nmb));
1064
1065                 /* Set data buffer address and data length of the mbuf */
1066                 rxdp->read.hdr_addr = dma_addr;
1067                 rxdp->read.pkt_addr = dma_addr;
1068                 rx_packet_len = (qword1 & I40E_RXD_QW1_LENGTH_PBUF_MASK) >>
1069                                         I40E_RXD_QW1_LENGTH_PBUF_SHIFT;
1070                 rxm->data_len = rx_packet_len;
1071                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1072
1073                 /**
1074                  * If this is the first buffer of the received packet, set the
1075                  * pointer to the first mbuf of the packet and initialize its
1076                  * context. Otherwise, update the total length and the number
1077                  * of segments of the current scattered packet, and update the
1078                  * pointer to the last mbuf of the current packet.
1079                  */
1080                 if (!first_seg) {
1081                         first_seg = rxm;
1082                         first_seg->nb_segs = 1;
1083                         first_seg->pkt_len = rx_packet_len;
1084                 } else {
1085                         first_seg->pkt_len =
1086                                 (uint16_t)(first_seg->pkt_len +
1087                                                 rx_packet_len);
1088                         first_seg->nb_segs++;
1089                         last_seg->next = rxm;
1090                 }
1091
1092                 /**
1093                  * If this is not the last buffer of the received packet,
1094                  * update the pointer to the last mbuf of the current scattered
1095                  * packet and continue to parse the RX ring.
1096                  */
1097                 if (!(rx_status & (1 << I40E_RX_DESC_STATUS_EOF_SHIFT))) {
1098                         last_seg = rxm;
1099                         continue;
1100                 }
1101
1102                 /**
1103                  * This is the last buffer of the received packet. If the CRC
1104                  * is not stripped by the hardware:
1105                  *  - Subtract the CRC length from the total packet length.
1106                  *  - If the last buffer only contains the whole CRC or a part
1107                  *  of it, free the mbuf associated to the last buffer. If part
1108                  *  of the CRC is also contained in the previous mbuf, subtract
1109                  *  the length of that CRC part from the data length of the
1110                  *  previous mbuf.
1111                  */
1112                 rxm->next = NULL;
1113                 if (unlikely(rxq->crc_len > 0)) {
1114                         first_seg->pkt_len -= ETHER_CRC_LEN;
1115                         if (rx_packet_len <= ETHER_CRC_LEN) {
1116                                 rte_pktmbuf_free_seg(rxm);
1117                                 first_seg->nb_segs--;
1118                                 last_seg->data_len =
1119                                         (uint16_t)(last_seg->data_len -
1120                                         (ETHER_CRC_LEN - rx_packet_len));
1121                                 last_seg->next = NULL;
1122                         } else
1123                                 rxm->data_len = (uint16_t)(rx_packet_len -
1124                                                                 ETHER_CRC_LEN);
1125                 }
1126
1127                 first_seg->port = rxq->port_id;
1128                 first_seg->ol_flags = 0;
1129                 i40e_rxd_to_vlan_tci(first_seg, &rxd);
1130                 pkt_flags = i40e_rxd_status_to_pkt_flags(qword1);
1131                 pkt_flags |= i40e_rxd_error_to_pkt_flags(qword1);
1132                 pkt_flags |= i40e_rxd_ptype_to_pkt_flags(qword1);
1133                 first_seg->packet_type = (uint16_t)((qword1 &
1134                                         I40E_RXD_QW1_PTYPE_MASK) >>
1135                                         I40E_RXD_QW1_PTYPE_SHIFT);
1136                 if (pkt_flags & PKT_RX_RSS_HASH)
1137                         rxm->hash.rss =
1138                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1139                 if (pkt_flags & PKT_RX_FDIR)
1140                         pkt_flags |= i40e_rxd_build_fdir(&rxd, rxm);
1141
1142                 first_seg->ol_flags |= pkt_flags;
1143
1144                 /* Prefetch data of first segment, if configured to do so. */
1145                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1146                         first_seg->data_off));
1147                 rx_pkts[nb_rx++] = first_seg;
1148                 first_seg = NULL;
1149         }
1150
1151         /* Record index of the next RX descriptor to probe. */
1152         rxq->rx_tail = rx_id;
1153         rxq->pkt_first_seg = first_seg;
1154         rxq->pkt_last_seg = last_seg;
1155
1156         /**
1157          * If the number of free RX descriptors is greater than the RX free
1158          * threshold of the queue, advance the Receive Descriptor Tail (RDT)
1159          * register. Update the RDT with the value of the last processed RX
1160          * descriptor minus 1, to guarantee that the RDT register is never
1161          * equal to the RDH register, which creates a "full" ring situtation
1162          * from the hardware point of view.
1163          */
1164         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
1165         if (nb_hold > rxq->rx_free_thresh) {
1166                 rx_id = (uint16_t)(rx_id == 0 ?
1167                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
1168                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
1169                 nb_hold = 0;
1170         }
1171         rxq->nb_rx_hold = nb_hold;
1172
1173         return nb_rx;
1174 }
1175
1176 /* Check if the context descriptor is needed for TX offloading */
1177 static inline uint16_t
1178 i40e_calc_context_desc(uint64_t flags)
1179 {
1180         static uint64_t mask = PKT_TX_OUTER_IP_CKSUM |
1181                 PKT_TX_TCP_SEG |
1182                 PKT_TX_QINQ_PKT;
1183
1184 #ifdef RTE_LIBRTE_IEEE1588
1185         mask |= PKT_TX_IEEE1588_TMST;
1186 #endif
1187
1188         return ((flags & mask) ? 1 : 0);
1189 }
1190
1191 /* set i40e TSO context descriptor */
1192 static inline uint64_t
1193 i40e_set_tso_ctx(struct rte_mbuf *mbuf, union i40e_tx_offload tx_offload)
1194 {
1195         uint64_t ctx_desc = 0;
1196         uint32_t cd_cmd, hdr_len, cd_tso_len;
1197
1198         if (!tx_offload.l4_len) {
1199                 PMD_DRV_LOG(DEBUG, "L4 length set to 0");
1200                 return ctx_desc;
1201         }
1202
1203         /**
1204          * in case of tunneling packet, the outer_l2_len and
1205          * outer_l3_len must be 0.
1206          */
1207         hdr_len = tx_offload.outer_l2_len +
1208                 tx_offload.outer_l3_len +
1209                 tx_offload.l2_len +
1210                 tx_offload.l3_len +
1211                 tx_offload.l4_len;
1212
1213         cd_cmd = I40E_TX_CTX_DESC_TSO;
1214         cd_tso_len = mbuf->pkt_len - hdr_len;
1215         ctx_desc |= ((uint64_t)cd_cmd << I40E_TXD_CTX_QW1_CMD_SHIFT) |
1216                 ((uint64_t)cd_tso_len <<
1217                  I40E_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1218                 ((uint64_t)mbuf->tso_segsz <<
1219                  I40E_TXD_CTX_QW1_MSS_SHIFT);
1220
1221         return ctx_desc;
1222 }
1223
1224 uint16_t
1225 i40e_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1226 {
1227         struct i40e_tx_queue *txq;
1228         struct i40e_tx_entry *sw_ring;
1229         struct i40e_tx_entry *txe, *txn;
1230         volatile struct i40e_tx_desc *txd;
1231         volatile struct i40e_tx_desc *txr;
1232         struct rte_mbuf *tx_pkt;
1233         struct rte_mbuf *m_seg;
1234         uint32_t cd_tunneling_params;
1235         uint16_t tx_id;
1236         uint16_t nb_tx;
1237         uint32_t td_cmd;
1238         uint32_t td_offset;
1239         uint32_t tx_flags;
1240         uint32_t td_tag;
1241         uint64_t ol_flags;
1242         uint16_t nb_used;
1243         uint16_t nb_ctx;
1244         uint16_t tx_last;
1245         uint16_t slen;
1246         uint64_t buf_dma_addr;
1247         union i40e_tx_offload tx_offload = {0};
1248
1249         txq = tx_queue;
1250         sw_ring = txq->sw_ring;
1251         txr = txq->tx_ring;
1252         tx_id = txq->tx_tail;
1253         txe = &sw_ring[tx_id];
1254
1255         /* Check if the descriptor ring needs to be cleaned. */
1256         if (txq->nb_tx_free < txq->tx_free_thresh)
1257                 i40e_xmit_cleanup(txq);
1258
1259         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1260                 td_cmd = 0;
1261                 td_tag = 0;
1262                 td_offset = 0;
1263                 tx_flags = 0;
1264
1265                 tx_pkt = *tx_pkts++;
1266                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1267
1268                 ol_flags = tx_pkt->ol_flags;
1269                 tx_offload.l2_len = tx_pkt->l2_len;
1270                 tx_offload.l3_len = tx_pkt->l3_len;
1271                 tx_offload.outer_l2_len = tx_pkt->outer_l2_len;
1272                 tx_offload.outer_l3_len = tx_pkt->outer_l3_len;
1273                 tx_offload.l4_len = tx_pkt->l4_len;
1274                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1275
1276                 /* Calculate the number of context descriptors needed. */
1277                 nb_ctx = i40e_calc_context_desc(ol_flags);
1278
1279                 /**
1280                  * The number of descriptors that must be allocated for
1281                  * a packet equals to the number of the segments of that
1282                  * packet plus 1 context descriptor if needed.
1283                  */
1284                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1285                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1286
1287                 /* Circular ring */
1288                 if (tx_last >= txq->nb_tx_desc)
1289                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1290
1291                 if (nb_used > txq->nb_tx_free) {
1292                         if (i40e_xmit_cleanup(txq) != 0) {
1293                                 if (nb_tx == 0)
1294                                         return 0;
1295                                 goto end_of_tx;
1296                         }
1297                         if (unlikely(nb_used > txq->tx_rs_thresh)) {
1298                                 while (nb_used > txq->nb_tx_free) {
1299                                         if (i40e_xmit_cleanup(txq) != 0) {
1300                                                 if (nb_tx == 0)
1301                                                         return 0;
1302                                                 goto end_of_tx;
1303                                         }
1304                                 }
1305                         }
1306                 }
1307
1308                 /* Descriptor based VLAN insertion */
1309                 if (ol_flags & (PKT_TX_VLAN_PKT | PKT_TX_QINQ_PKT)) {
1310                         tx_flags |= tx_pkt->vlan_tci <<
1311                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1312                         tx_flags |= I40E_TX_FLAG_INSERT_VLAN;
1313                         td_cmd |= I40E_TX_DESC_CMD_IL2TAG1;
1314                         td_tag = (tx_flags & I40E_TX_FLAG_L2TAG1_MASK) >>
1315                                                 I40E_TX_FLAG_L2TAG1_SHIFT;
1316                 }
1317
1318                 /* Always enable CRC offload insertion */
1319                 td_cmd |= I40E_TX_DESC_CMD_ICRC;
1320
1321                 /* Enable checksum offloading */
1322                 cd_tunneling_params = 0;
1323                 if (unlikely(ol_flags & I40E_TX_CKSUM_OFFLOAD_MASK)) {
1324                         i40e_txd_enable_checksum(ol_flags, &td_cmd, &td_offset,
1325                                 tx_offload, &cd_tunneling_params);
1326                 }
1327
1328                 if (unlikely(nb_ctx)) {
1329                         /* Setup TX context descriptor if required */
1330                         volatile struct i40e_tx_context_desc *ctx_txd =
1331                                 (volatile struct i40e_tx_context_desc *)\
1332                                                         &txr[tx_id];
1333                         uint16_t cd_l2tag2 = 0;
1334                         uint64_t cd_type_cmd_tso_mss =
1335                                 I40E_TX_DESC_DTYPE_CONTEXT;
1336
1337                         txn = &sw_ring[txe->next_id];
1338                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1339                         if (txe->mbuf != NULL) {
1340                                 rte_pktmbuf_free_seg(txe->mbuf);
1341                                 txe->mbuf = NULL;
1342                         }
1343
1344                         /* TSO enabled means no timestamp */
1345                         if (ol_flags & PKT_TX_TCP_SEG)
1346                                 cd_type_cmd_tso_mss |=
1347                                         i40e_set_tso_ctx(tx_pkt, tx_offload);
1348                         else {
1349 #ifdef RTE_LIBRTE_IEEE1588
1350                                 if (ol_flags & PKT_TX_IEEE1588_TMST)
1351                                         cd_type_cmd_tso_mss |=
1352                                                 ((uint64_t)I40E_TX_CTX_DESC_TSYN <<
1353                                                  I40E_TXD_CTX_QW1_CMD_SHIFT);
1354 #endif
1355                         }
1356
1357                         ctx_txd->tunneling_params =
1358                                 rte_cpu_to_le_32(cd_tunneling_params);
1359                         if (ol_flags & PKT_TX_QINQ_PKT) {
1360                                 cd_l2tag2 = tx_pkt->vlan_tci_outer;
1361                                 cd_type_cmd_tso_mss |=
1362                                         ((uint64_t)I40E_TX_CTX_DESC_IL2TAG2 <<
1363                                                 I40E_TXD_CTX_QW1_CMD_SHIFT);
1364                         }
1365                         ctx_txd->l2tag2 = rte_cpu_to_le_16(cd_l2tag2);
1366                         ctx_txd->type_cmd_tso_mss =
1367                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1368
1369                         PMD_TX_LOG(DEBUG, "mbuf: %p, TCD[%u]:\n"
1370                                 "tunneling_params: %#x;\n"
1371                                 "l2tag2: %#hx;\n"
1372                                 "rsvd: %#hx;\n"
1373                                 "type_cmd_tso_mss: %#"PRIx64";\n",
1374                                 tx_pkt, tx_id,
1375                                 ctx_txd->tunneling_params,
1376                                 ctx_txd->l2tag2,
1377                                 ctx_txd->rsvd,
1378                                 ctx_txd->type_cmd_tso_mss);
1379
1380                         txe->last_id = tx_last;
1381                         tx_id = txe->next_id;
1382                         txe = txn;
1383                 }
1384
1385                 m_seg = tx_pkt;
1386                 do {
1387                         txd = &txr[tx_id];
1388                         txn = &sw_ring[txe->next_id];
1389
1390                         if (txe->mbuf)
1391                                 rte_pktmbuf_free_seg(txe->mbuf);
1392                         txe->mbuf = m_seg;
1393
1394                         /* Setup TX Descriptor */
1395                         slen = m_seg->data_len;
1396                         buf_dma_addr = RTE_MBUF_DATA_DMA_ADDR(m_seg);
1397
1398                         PMD_TX_LOG(DEBUG, "mbuf: %p, TDD[%u]:\n"
1399                                 "buf_dma_addr: %#"PRIx64";\n"
1400                                 "td_cmd: %#x;\n"
1401                                 "td_offset: %#x;\n"
1402                                 "td_len: %u;\n"
1403                                 "td_tag: %#x;\n",
1404                                 tx_pkt, tx_id, buf_dma_addr,
1405                                 td_cmd, td_offset, slen, td_tag);
1406
1407                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1408                         txd->cmd_type_offset_bsz = i40e_build_ctob(td_cmd,
1409                                                 td_offset, slen, td_tag);
1410                         txe->last_id = tx_last;
1411                         tx_id = txe->next_id;
1412                         txe = txn;
1413                         m_seg = m_seg->next;
1414                 } while (m_seg != NULL);
1415
1416                 /* The last packet data descriptor needs End Of Packet (EOP) */
1417                 td_cmd |= I40E_TX_DESC_CMD_EOP;
1418                 txq->nb_tx_used = (uint16_t)(txq->nb_tx_used + nb_used);
1419                 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_used);
1420
1421                 if (txq->nb_tx_used >= txq->tx_rs_thresh) {
1422                         PMD_TX_FREE_LOG(DEBUG,
1423                                         "Setting RS bit on TXD id="
1424                                         "%4u (port=%d queue=%d)",
1425                                         tx_last, txq->port_id, txq->queue_id);
1426
1427                         td_cmd |= I40E_TX_DESC_CMD_RS;
1428
1429                         /* Update txq RS bit counters */
1430                         txq->nb_tx_used = 0;
1431                 }
1432
1433                 txd->cmd_type_offset_bsz |=
1434                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1435                                         I40E_TXD_QW1_CMD_SHIFT);
1436         }
1437
1438 end_of_tx:
1439         rte_wmb();
1440
1441         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
1442                    (unsigned) txq->port_id, (unsigned) txq->queue_id,
1443                    (unsigned) tx_id, (unsigned) nb_tx);
1444
1445         I40E_PCI_REG_WRITE(txq->qtx_tail, tx_id);
1446         txq->tx_tail = tx_id;
1447
1448         return nb_tx;
1449 }
1450
1451 static inline int __attribute__((always_inline))
1452 i40e_tx_free_bufs(struct i40e_tx_queue *txq)
1453 {
1454         struct i40e_tx_entry *txep;
1455         uint16_t i;
1456
1457         if (!(txq->tx_ring[txq->tx_next_dd].cmd_type_offset_bsz &
1458                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE)))
1459                 return 0;
1460
1461         txep = &(txq->sw_ring[txq->tx_next_dd - (txq->tx_rs_thresh - 1)]);
1462
1463         for (i = 0; i < txq->tx_rs_thresh; i++)
1464                 rte_prefetch0((txep + i)->mbuf);
1465
1466         if (!(txq->txq_flags & (uint32_t)ETH_TXQ_FLAGS_NOREFCOUNT)) {
1467                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1468                         rte_mempool_put(txep->mbuf->pool, txep->mbuf);
1469                         txep->mbuf = NULL;
1470                 }
1471         } else {
1472                 for (i = 0; i < txq->tx_rs_thresh; ++i, ++txep) {
1473                         rte_pktmbuf_free_seg(txep->mbuf);
1474                         txep->mbuf = NULL;
1475                 }
1476         }
1477
1478         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free + txq->tx_rs_thresh);
1479         txq->tx_next_dd = (uint16_t)(txq->tx_next_dd + txq->tx_rs_thresh);
1480         if (txq->tx_next_dd >= txq->nb_tx_desc)
1481                 txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
1482
1483         return txq->tx_rs_thresh;
1484 }
1485
1486 #define I40E_TD_CMD (I40E_TX_DESC_CMD_ICRC |\
1487                      I40E_TX_DESC_CMD_EOP)
1488
1489 /* Populate 4 descriptors with data from 4 mbufs */
1490 static inline void
1491 tx4(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1492 {
1493         uint64_t dma_addr;
1494         uint32_t i;
1495
1496         for (i = 0; i < 4; i++, txdp++, pkts++) {
1497                 dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1498                 txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1499                 txdp->cmd_type_offset_bsz =
1500                         i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1501                                         (*pkts)->data_len, 0);
1502         }
1503 }
1504
1505 /* Populate 1 descriptor with data from 1 mbuf */
1506 static inline void
1507 tx1(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkts)
1508 {
1509         uint64_t dma_addr;
1510
1511         dma_addr = RTE_MBUF_DATA_DMA_ADDR(*pkts);
1512         txdp->buffer_addr = rte_cpu_to_le_64(dma_addr);
1513         txdp->cmd_type_offset_bsz =
1514                 i40e_build_ctob((uint32_t)I40E_TD_CMD, 0,
1515                                 (*pkts)->data_len, 0);
1516 }
1517
1518 /* Fill hardware descriptor ring with mbuf data */
1519 static inline void
1520 i40e_tx_fill_hw_ring(struct i40e_tx_queue *txq,
1521                      struct rte_mbuf **pkts,
1522                      uint16_t nb_pkts)
1523 {
1524         volatile struct i40e_tx_desc *txdp = &(txq->tx_ring[txq->tx_tail]);
1525         struct i40e_tx_entry *txep = &(txq->sw_ring[txq->tx_tail]);
1526         const int N_PER_LOOP = 4;
1527         const int N_PER_LOOP_MASK = N_PER_LOOP - 1;
1528         int mainpart, leftover;
1529         int i, j;
1530
1531         mainpart = (nb_pkts & ((uint32_t) ~N_PER_LOOP_MASK));
1532         leftover = (nb_pkts & ((uint32_t)  N_PER_LOOP_MASK));
1533         for (i = 0; i < mainpart; i += N_PER_LOOP) {
1534                 for (j = 0; j < N_PER_LOOP; ++j) {
1535                         (txep + i + j)->mbuf = *(pkts + i + j);
1536                 }
1537                 tx4(txdp + i, pkts + i);
1538         }
1539         if (unlikely(leftover > 0)) {
1540                 for (i = 0; i < leftover; ++i) {
1541                         (txep + mainpart + i)->mbuf = *(pkts + mainpart + i);
1542                         tx1(txdp + mainpart + i, pkts + mainpart + i);
1543                 }
1544         }
1545 }
1546
1547 static inline uint16_t
1548 tx_xmit_pkts(struct i40e_tx_queue *txq,
1549              struct rte_mbuf **tx_pkts,
1550              uint16_t nb_pkts)
1551 {
1552         volatile struct i40e_tx_desc *txr = txq->tx_ring;
1553         uint16_t n = 0;
1554
1555         /**
1556          * Begin scanning the H/W ring for done descriptors when the number
1557          * of available descriptors drops below tx_free_thresh. For each done
1558          * descriptor, free the associated buffer.
1559          */
1560         if (txq->nb_tx_free < txq->tx_free_thresh)
1561                 i40e_tx_free_bufs(txq);
1562
1563         /* Use available descriptor only */
1564         nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
1565         if (unlikely(!nb_pkts))
1566                 return 0;
1567
1568         txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
1569         if ((txq->tx_tail + nb_pkts) > txq->nb_tx_desc) {
1570                 n = (uint16_t)(txq->nb_tx_desc - txq->tx_tail);
1571                 i40e_tx_fill_hw_ring(txq, tx_pkts, n);
1572                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1573                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1574                                                 I40E_TXD_QW1_CMD_SHIFT);
1575                 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1576                 txq->tx_tail = 0;
1577         }
1578
1579         /* Fill hardware descriptor ring with mbuf data */
1580         i40e_tx_fill_hw_ring(txq, tx_pkts + n, (uint16_t)(nb_pkts - n));
1581         txq->tx_tail = (uint16_t)(txq->tx_tail + (nb_pkts - n));
1582
1583         /* Determin if RS bit needs to be set */
1584         if (txq->tx_tail > txq->tx_next_rs) {
1585                 txr[txq->tx_next_rs].cmd_type_offset_bsz |=
1586                         rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
1587                                                 I40E_TXD_QW1_CMD_SHIFT);
1588                 txq->tx_next_rs =
1589                         (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
1590                 if (txq->tx_next_rs >= txq->nb_tx_desc)
1591                         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
1592         }
1593
1594         if (txq->tx_tail >= txq->nb_tx_desc)
1595                 txq->tx_tail = 0;
1596
1597         /* Update the tx tail register */
1598         rte_wmb();
1599         I40E_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1600
1601         return nb_pkts;
1602 }
1603
1604 static uint16_t
1605 i40e_xmit_pkts_simple(void *tx_queue,
1606                       struct rte_mbuf **tx_pkts,
1607                       uint16_t nb_pkts)
1608 {
1609         uint16_t nb_tx = 0;
1610
1611         if (likely(nb_pkts <= I40E_TX_MAX_BURST))
1612                 return tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1613                                                 tx_pkts, nb_pkts);
1614
1615         while (nb_pkts) {
1616                 uint16_t ret, num = (uint16_t)RTE_MIN(nb_pkts,
1617                                                 I40E_TX_MAX_BURST);
1618
1619                 ret = tx_xmit_pkts((struct i40e_tx_queue *)tx_queue,
1620                                                 &tx_pkts[nb_tx], num);
1621                 nb_tx = (uint16_t)(nb_tx + ret);
1622                 nb_pkts = (uint16_t)(nb_pkts - ret);
1623                 if (ret < num)
1624                         break;
1625         }
1626
1627         return nb_tx;
1628 }
1629
1630 /*
1631  * Find the VSI the queue belongs to. 'queue_idx' is the queue index
1632  * application used, which assume having sequential ones. But from driver's
1633  * perspective, it's different. For example, q0 belongs to FDIR VSI, q1-q64
1634  * to MAIN VSI, , q65-96 to SRIOV VSIs, q97-128 to VMDQ VSIs. For application
1635  * running on host, q1-64 and q97-128 can be used, total 96 queues. They can
1636  * use queue_idx from 0 to 95 to access queues, while real queue would be
1637  * different. This function will do a queue mapping to find VSI the queue
1638  * belongs to.
1639  */
1640 static struct i40e_vsi*
1641 i40e_pf_get_vsi_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1642 {
1643         /* the queue in MAIN VSI range */
1644         if (queue_idx < pf->main_vsi->nb_qps)
1645                 return pf->main_vsi;
1646
1647         queue_idx -= pf->main_vsi->nb_qps;
1648
1649         /* queue_idx is greater than VMDQ VSIs range */
1650         if (queue_idx > pf->nb_cfg_vmdq_vsi * pf->vmdq_nb_qps - 1) {
1651                 PMD_INIT_LOG(ERR, "queue_idx out of range. VMDQ configured?");
1652                 return NULL;
1653         }
1654
1655         return pf->vmdq[queue_idx / pf->vmdq_nb_qps].vsi;
1656 }
1657
1658 static uint16_t
1659 i40e_get_queue_offset_by_qindex(struct i40e_pf *pf, uint16_t queue_idx)
1660 {
1661         /* the queue in MAIN VSI range */
1662         if (queue_idx < pf->main_vsi->nb_qps)
1663                 return queue_idx;
1664
1665         /* It's VMDQ queues */
1666         queue_idx -= pf->main_vsi->nb_qps;
1667
1668         if (pf->nb_cfg_vmdq_vsi)
1669                 return queue_idx % pf->vmdq_nb_qps;
1670         else {
1671                 PMD_INIT_LOG(ERR, "Fail to get queue offset");
1672                 return (uint16_t)(-1);
1673         }
1674 }
1675
1676 int
1677 i40e_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1678 {
1679         struct i40e_rx_queue *rxq;
1680         int err = -1;
1681         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1682
1683         PMD_INIT_FUNC_TRACE();
1684
1685         if (rx_queue_id < dev->data->nb_rx_queues) {
1686                 rxq = dev->data->rx_queues[rx_queue_id];
1687
1688                 err = i40e_alloc_rx_queue_mbufs(rxq);
1689                 if (err) {
1690                         PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
1691                         return err;
1692                 }
1693
1694                 rte_wmb();
1695
1696                 /* Init the RX tail regieter. */
1697                 I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
1698
1699                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, TRUE);
1700
1701                 if (err) {
1702                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
1703                                     rx_queue_id);
1704
1705                         i40e_rx_queue_release_mbufs(rxq);
1706                         i40e_reset_rx_queue(rxq);
1707                 }
1708         }
1709
1710         return err;
1711 }
1712
1713 int
1714 i40e_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1715 {
1716         struct i40e_rx_queue *rxq;
1717         int err;
1718         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1719
1720         if (rx_queue_id < dev->data->nb_rx_queues) {
1721                 rxq = dev->data->rx_queues[rx_queue_id];
1722
1723                 /*
1724                 * rx_queue_id is queue id aplication refers to, while
1725                 * rxq->reg_idx is the real queue index.
1726                 */
1727                 err = i40e_switch_rx_queue(hw, rxq->reg_idx, FALSE);
1728
1729                 if (err) {
1730                         PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
1731                                     rx_queue_id);
1732                         return err;
1733                 }
1734                 i40e_rx_queue_release_mbufs(rxq);
1735                 i40e_reset_rx_queue(rxq);
1736         }
1737
1738         return 0;
1739 }
1740
1741 int
1742 i40e_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1743 {
1744         int err = -1;
1745         struct i40e_tx_queue *txq;
1746         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1747
1748         PMD_INIT_FUNC_TRACE();
1749
1750         if (tx_queue_id < dev->data->nb_tx_queues) {
1751                 txq = dev->data->tx_queues[tx_queue_id];
1752
1753                 /*
1754                 * tx_queue_id is queue id aplication refers to, while
1755                 * rxq->reg_idx is the real queue index.
1756                 */
1757                 err = i40e_switch_tx_queue(hw, txq->reg_idx, TRUE);
1758                 if (err)
1759                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
1760                                     tx_queue_id);
1761         }
1762
1763         return err;
1764 }
1765
1766 int
1767 i40e_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
1768 {
1769         struct i40e_tx_queue *txq;
1770         int err;
1771         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1772
1773         if (tx_queue_id < dev->data->nb_tx_queues) {
1774                 txq = dev->data->tx_queues[tx_queue_id];
1775
1776                 /*
1777                 * tx_queue_id is queue id aplication refers to, while
1778                 * txq->reg_idx is the real queue index.
1779                 */
1780                 err = i40e_switch_tx_queue(hw, txq->reg_idx, FALSE);
1781
1782                 if (err) {
1783                         PMD_DRV_LOG(ERR, "Failed to switch TX queue %u of",
1784                                     tx_queue_id);
1785                         return err;
1786                 }
1787
1788                 i40e_tx_queue_release_mbufs(txq);
1789                 i40e_reset_tx_queue(txq);
1790         }
1791
1792         return 0;
1793 }
1794
1795 int
1796 i40e_dev_rx_queue_setup(struct rte_eth_dev *dev,
1797                         uint16_t queue_idx,
1798                         uint16_t nb_desc,
1799                         unsigned int socket_id,
1800                         const struct rte_eth_rxconf *rx_conf,
1801                         struct rte_mempool *mp)
1802 {
1803         struct i40e_vsi *vsi;
1804         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1805         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1806         struct i40e_rx_queue *rxq;
1807         const struct rte_memzone *rz;
1808         uint32_t ring_size;
1809         uint16_t len;
1810         int use_def_burst_func = 1;
1811
1812         if (hw->mac.type == I40E_MAC_VF) {
1813                 struct i40e_vf *vf =
1814                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
1815                 vsi = &vf->vsi;
1816         } else
1817                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
1818
1819         if (vsi == NULL) {
1820                 PMD_DRV_LOG(ERR, "VSI not available or queue "
1821                             "index exceeds the maximum");
1822                 return I40E_ERR_PARAM;
1823         }
1824         if (((nb_desc * sizeof(union i40e_rx_desc)) % I40E_ALIGN) != 0 ||
1825                                         (nb_desc > I40E_MAX_RING_DESC) ||
1826                                         (nb_desc < I40E_MIN_RING_DESC)) {
1827                 PMD_DRV_LOG(ERR, "Number (%u) of receive descriptors is "
1828                             "invalid", nb_desc);
1829                 return I40E_ERR_PARAM;
1830         }
1831
1832         /* Free memory if needed */
1833         if (dev->data->rx_queues[queue_idx]) {
1834                 i40e_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
1835                 dev->data->rx_queues[queue_idx] = NULL;
1836         }
1837
1838         /* Allocate the rx queue data structure */
1839         rxq = rte_zmalloc_socket("i40e rx queue",
1840                                  sizeof(struct i40e_rx_queue),
1841                                  RTE_CACHE_LINE_SIZE,
1842                                  socket_id);
1843         if (!rxq) {
1844                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
1845                             "rx queue data structure");
1846                 return (-ENOMEM);
1847         }
1848         rxq->mp = mp;
1849         rxq->nb_rx_desc = nb_desc;
1850         rxq->rx_free_thresh = rx_conf->rx_free_thresh;
1851         rxq->queue_id = queue_idx;
1852         if (hw->mac.type == I40E_MAC_VF)
1853                 rxq->reg_idx = queue_idx;
1854         else /* PF device */
1855                 rxq->reg_idx = vsi->base_queue +
1856                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
1857
1858         rxq->port_id = dev->data->port_id;
1859         rxq->crc_len = (uint8_t) ((dev->data->dev_conf.rxmode.hw_strip_crc) ?
1860                                                         0 : ETHER_CRC_LEN);
1861         rxq->drop_en = rx_conf->rx_drop_en;
1862         rxq->vsi = vsi;
1863         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
1864
1865         /* Allocate the maximun number of RX ring hardware descriptor. */
1866         ring_size = sizeof(union i40e_rx_desc) * I40E_MAX_RING_DESC;
1867         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
1868         rz = i40e_ring_dma_zone_reserve(dev,
1869                                         "rx_ring",
1870                                         queue_idx,
1871                                         ring_size,
1872                                         socket_id);
1873         if (!rz) {
1874                 i40e_dev_rx_queue_release(rxq);
1875                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX");
1876                 return (-ENOMEM);
1877         }
1878
1879         /* Zero all the descriptors in the ring. */
1880         memset(rz->addr, 0, ring_size);
1881
1882 #ifdef RTE_LIBRTE_XEN_DOM0
1883         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
1884 #else
1885         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
1886 #endif
1887
1888         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
1889
1890 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1891         len = (uint16_t)(nb_desc + RTE_PMD_I40E_RX_MAX_BURST);
1892 #else
1893         len = nb_desc;
1894 #endif
1895
1896         /* Allocate the software ring. */
1897         rxq->sw_ring =
1898                 rte_zmalloc_socket("i40e rx sw ring",
1899                                    sizeof(struct i40e_rx_entry) * len,
1900                                    RTE_CACHE_LINE_SIZE,
1901                                    socket_id);
1902         if (!rxq->sw_ring) {
1903                 i40e_dev_rx_queue_release(rxq);
1904                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW ring");
1905                 return (-ENOMEM);
1906         }
1907
1908         i40e_reset_rx_queue(rxq);
1909         rxq->q_set = TRUE;
1910         dev->data->rx_queues[queue_idx] = rxq;
1911
1912         use_def_burst_func = check_rx_burst_bulk_alloc_preconditions(rxq);
1913
1914         if (!use_def_burst_func && !dev->data->scattered_rx) {
1915 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
1916                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1917                              "satisfied. Rx Burst Bulk Alloc function will be "
1918                              "used on port=%d, queue=%d.",
1919                              rxq->port_id, rxq->queue_id);
1920                 dev->rx_pkt_burst = i40e_recv_pkts_bulk_alloc;
1921 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
1922         } else {
1923                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
1924                              "not satisfied, Scattered Rx is requested, "
1925                              "or RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC is "
1926                              "not enabled on port=%d, queue=%d.",
1927                              rxq->port_id, rxq->queue_id);
1928         }
1929
1930         return 0;
1931 }
1932
1933 void
1934 i40e_dev_rx_queue_release(void *rxq)
1935 {
1936         struct i40e_rx_queue *q = (struct i40e_rx_queue *)rxq;
1937
1938         if (!q) {
1939                 PMD_DRV_LOG(DEBUG, "Pointer to rxq is NULL");
1940                 return;
1941         }
1942
1943         i40e_rx_queue_release_mbufs(q);
1944         rte_free(q->sw_ring);
1945         rte_free(q);
1946 }
1947
1948 uint32_t
1949 i40e_dev_rx_queue_count(struct rte_eth_dev *dev, uint16_t rx_queue_id)
1950 {
1951 #define I40E_RXQ_SCAN_INTERVAL 4
1952         volatile union i40e_rx_desc *rxdp;
1953         struct i40e_rx_queue *rxq;
1954         uint16_t desc = 0;
1955
1956         if (unlikely(rx_queue_id >= dev->data->nb_rx_queues)) {
1957                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", rx_queue_id);
1958                 return 0;
1959         }
1960
1961         rxq = dev->data->rx_queues[rx_queue_id];
1962         rxdp = &(rxq->rx_ring[rxq->rx_tail]);
1963         while ((desc < rxq->nb_rx_desc) &&
1964                 ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
1965                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
1966                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT)) {
1967                 /**
1968                  * Check the DD bit of a rx descriptor of each 4 in a group,
1969                  * to avoid checking too frequently and downgrading performance
1970                  * too much.
1971                  */
1972                 desc += I40E_RXQ_SCAN_INTERVAL;
1973                 rxdp += I40E_RXQ_SCAN_INTERVAL;
1974                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
1975                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
1976                                         desc - rxq->nb_rx_desc]);
1977         }
1978
1979         return desc;
1980 }
1981
1982 int
1983 i40e_dev_rx_descriptor_done(void *rx_queue, uint16_t offset)
1984 {
1985         volatile union i40e_rx_desc *rxdp;
1986         struct i40e_rx_queue *rxq = rx_queue;
1987         uint16_t desc;
1988         int ret;
1989
1990         if (unlikely(offset >= rxq->nb_rx_desc)) {
1991                 PMD_DRV_LOG(ERR, "Invalid RX queue id %u", offset);
1992                 return 0;
1993         }
1994
1995         desc = rxq->rx_tail + offset;
1996         if (desc >= rxq->nb_rx_desc)
1997                 desc -= rxq->nb_rx_desc;
1998
1999         rxdp = &(rxq->rx_ring[desc]);
2000
2001         ret = !!(((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2002                 I40E_RXD_QW1_STATUS_MASK) >> I40E_RXD_QW1_STATUS_SHIFT) &
2003                                 (1 << I40E_RX_DESC_STATUS_DD_SHIFT));
2004
2005         return ret;
2006 }
2007
2008 int
2009 i40e_dev_tx_queue_setup(struct rte_eth_dev *dev,
2010                         uint16_t queue_idx,
2011                         uint16_t nb_desc,
2012                         unsigned int socket_id,
2013                         const struct rte_eth_txconf *tx_conf)
2014 {
2015         struct i40e_vsi *vsi;
2016         struct i40e_hw *hw = I40E_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2017         struct i40e_pf *pf = I40E_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2018         struct i40e_tx_queue *txq;
2019         const struct rte_memzone *tz;
2020         uint32_t ring_size;
2021         uint16_t tx_rs_thresh, tx_free_thresh;
2022
2023         if (hw->mac.type == I40E_MAC_VF) {
2024                 struct i40e_vf *vf =
2025                         I40EVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2026                 vsi = &vf->vsi;
2027         } else
2028                 vsi = i40e_pf_get_vsi_by_qindex(pf, queue_idx);
2029
2030         if (vsi == NULL) {
2031                 PMD_DRV_LOG(ERR, "VSI is NULL, or queue index (%u) "
2032                             "exceeds the maximum", queue_idx);
2033                 return I40E_ERR_PARAM;
2034         }
2035
2036         if (((nb_desc * sizeof(struct i40e_tx_desc)) % I40E_ALIGN) != 0 ||
2037                                         (nb_desc > I40E_MAX_RING_DESC) ||
2038                                         (nb_desc < I40E_MIN_RING_DESC)) {
2039                 PMD_DRV_LOG(ERR, "Number (%u) of transmit descriptors is "
2040                             "invalid", nb_desc);
2041                 return I40E_ERR_PARAM;
2042         }
2043
2044         /**
2045          * The following two parameters control the setting of the RS bit on
2046          * transmit descriptors. TX descriptors will have their RS bit set
2047          * after txq->tx_rs_thresh descriptors have been used. The TX
2048          * descriptor ring will be cleaned after txq->tx_free_thresh
2049          * descriptors are used or if the number of descriptors required to
2050          * transmit a packet is greater than the number of free TX descriptors.
2051          *
2052          * The following constraints must be satisfied:
2053          *  - tx_rs_thresh must be greater than 0.
2054          *  - tx_rs_thresh must be less than the size of the ring minus 2.
2055          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
2056          *  - tx_rs_thresh must be a divisor of the ring size.
2057          *  - tx_free_thresh must be greater than 0.
2058          *  - tx_free_thresh must be less than the size of the ring minus 3.
2059          *
2060          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
2061          * race condition, hence the maximum threshold constraints. When set
2062          * to zero use default values.
2063          */
2064         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
2065                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
2066         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
2067                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
2068         if (tx_rs_thresh >= (nb_desc - 2)) {
2069                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2070                              "number of TX descriptors minus 2. "
2071                              "(tx_rs_thresh=%u port=%d queue=%d)",
2072                              (unsigned int)tx_rs_thresh,
2073                              (int)dev->data->port_id,
2074                              (int)queue_idx);
2075                 return I40E_ERR_PARAM;
2076         }
2077         if (tx_free_thresh >= (nb_desc - 3)) {
2078                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than the "
2079                              "tx_free_thresh must be less than the "
2080                              "number of TX descriptors minus 3. "
2081                              "(tx_free_thresh=%u port=%d queue=%d)",
2082                              (unsigned int)tx_free_thresh,
2083                              (int)dev->data->port_id,
2084                              (int)queue_idx);
2085                 return I40E_ERR_PARAM;
2086         }
2087         if (tx_rs_thresh > tx_free_thresh) {
2088                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be less than or "
2089                              "equal to tx_free_thresh. (tx_free_thresh=%u"
2090                              " tx_rs_thresh=%u port=%d queue=%d)",
2091                              (unsigned int)tx_free_thresh,
2092                              (unsigned int)tx_rs_thresh,
2093                              (int)dev->data->port_id,
2094                              (int)queue_idx);
2095                 return I40E_ERR_PARAM;
2096         }
2097         if ((nb_desc % tx_rs_thresh) != 0) {
2098                 PMD_INIT_LOG(ERR, "tx_rs_thresh must be a divisor of the "
2099                              "number of TX descriptors. (tx_rs_thresh=%u"
2100                              " port=%d queue=%d)",
2101                              (unsigned int)tx_rs_thresh,
2102                              (int)dev->data->port_id,
2103                              (int)queue_idx);
2104                 return I40E_ERR_PARAM;
2105         }
2106         if ((tx_rs_thresh > 1) && (tx_conf->tx_thresh.wthresh != 0)) {
2107                 PMD_INIT_LOG(ERR, "TX WTHRESH must be set to 0 if "
2108                              "tx_rs_thresh is greater than 1. "
2109                              "(tx_rs_thresh=%u port=%d queue=%d)",
2110                              (unsigned int)tx_rs_thresh,
2111                              (int)dev->data->port_id,
2112                              (int)queue_idx);
2113                 return I40E_ERR_PARAM;
2114         }
2115
2116         /* Free memory if needed. */
2117         if (dev->data->tx_queues[queue_idx]) {
2118                 i40e_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
2119                 dev->data->tx_queues[queue_idx] = NULL;
2120         }
2121
2122         /* Allocate the TX queue data structure. */
2123         txq = rte_zmalloc_socket("i40e tx queue",
2124                                   sizeof(struct i40e_tx_queue),
2125                                   RTE_CACHE_LINE_SIZE,
2126                                   socket_id);
2127         if (!txq) {
2128                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2129                             "tx queue structure");
2130                 return (-ENOMEM);
2131         }
2132
2133         /* Allocate TX hardware ring descriptors. */
2134         ring_size = sizeof(struct i40e_tx_desc) * I40E_MAX_RING_DESC;
2135         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2136         tz = i40e_ring_dma_zone_reserve(dev,
2137                                         "tx_ring",
2138                                         queue_idx,
2139                                         ring_size,
2140                                         socket_id);
2141         if (!tz) {
2142                 i40e_dev_tx_queue_release(txq);
2143                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX");
2144                 return (-ENOMEM);
2145         }
2146
2147         txq->nb_tx_desc = nb_desc;
2148         txq->tx_rs_thresh = tx_rs_thresh;
2149         txq->tx_free_thresh = tx_free_thresh;
2150         txq->pthresh = tx_conf->tx_thresh.pthresh;
2151         txq->hthresh = tx_conf->tx_thresh.hthresh;
2152         txq->wthresh = tx_conf->tx_thresh.wthresh;
2153         txq->queue_id = queue_idx;
2154         if (hw->mac.type == I40E_MAC_VF)
2155                 txq->reg_idx = queue_idx;
2156         else /* PF device */
2157                 txq->reg_idx = vsi->base_queue +
2158                         i40e_get_queue_offset_by_qindex(pf, queue_idx);
2159
2160         txq->port_id = dev->data->port_id;
2161         txq->txq_flags = tx_conf->txq_flags;
2162         txq->vsi = vsi;
2163         txq->tx_deferred_start = tx_conf->tx_deferred_start;
2164
2165 #ifdef RTE_LIBRTE_XEN_DOM0
2166         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2167 #else
2168         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2169 #endif
2170         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2171
2172         /* Allocate software ring */
2173         txq->sw_ring =
2174                 rte_zmalloc_socket("i40e tx sw ring",
2175                                    sizeof(struct i40e_tx_entry) * nb_desc,
2176                                    RTE_CACHE_LINE_SIZE,
2177                                    socket_id);
2178         if (!txq->sw_ring) {
2179                 i40e_dev_tx_queue_release(txq);
2180                 PMD_DRV_LOG(ERR, "Failed to allocate memory for SW TX ring");
2181                 return (-ENOMEM);
2182         }
2183
2184         i40e_reset_tx_queue(txq);
2185         txq->q_set = TRUE;
2186         dev->data->tx_queues[queue_idx] = txq;
2187
2188         /* Use a simple TX queue without offloads or multi segs if possible */
2189         if (((txq->txq_flags & I40E_SIMPLE_FLAGS) == I40E_SIMPLE_FLAGS) &&
2190                                 (txq->tx_rs_thresh >= I40E_TX_MAX_BURST)) {
2191                 PMD_INIT_LOG(INFO, "Using simple tx path");
2192                 dev->tx_pkt_burst = i40e_xmit_pkts_simple;
2193         } else {
2194                 PMD_INIT_LOG(INFO, "Using full-featured tx path");
2195                 dev->tx_pkt_burst = i40e_xmit_pkts;
2196         }
2197
2198         return 0;
2199 }
2200
2201 void
2202 i40e_dev_tx_queue_release(void *txq)
2203 {
2204         struct i40e_tx_queue *q = (struct i40e_tx_queue *)txq;
2205
2206         if (!q) {
2207                 PMD_DRV_LOG(DEBUG, "Pointer to TX queue is NULL");
2208                 return;
2209         }
2210
2211         i40e_tx_queue_release_mbufs(q);
2212         rte_free(q->sw_ring);
2213         rte_free(q);
2214 }
2215
2216 static const struct rte_memzone *
2217 i40e_ring_dma_zone_reserve(struct rte_eth_dev *dev,
2218                            const char *ring_name,
2219                            uint16_t queue_id,
2220                            uint32_t ring_size,
2221                            int socket_id)
2222 {
2223         char z_name[RTE_MEMZONE_NAMESIZE];
2224         const struct rte_memzone *mz;
2225
2226         snprintf(z_name, sizeof(z_name), "%s_%s_%d_%d",
2227                         dev->driver->pci_drv.name, ring_name,
2228                                 dev->data->port_id, queue_id);
2229         mz = rte_memzone_lookup(z_name);
2230         if (mz)
2231                 return mz;
2232
2233 #ifdef RTE_LIBRTE_XEN_DOM0
2234         return rte_memzone_reserve_bounded(z_name, ring_size,
2235                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2236 #else
2237         return rte_memzone_reserve_aligned(z_name, ring_size,
2238                                 socket_id, 0, I40E_ALIGN);
2239 #endif
2240 }
2241
2242 const struct rte_memzone *
2243 i40e_memzone_reserve(const char *name, uint32_t len, int socket_id)
2244 {
2245         const struct rte_memzone *mz = NULL;
2246
2247         mz = rte_memzone_lookup(name);
2248         if (mz)
2249                 return mz;
2250 #ifdef RTE_LIBRTE_XEN_DOM0
2251         mz = rte_memzone_reserve_bounded(name, len,
2252                 socket_id, 0, I40E_ALIGN, RTE_PGSIZE_2M);
2253 #else
2254         mz = rte_memzone_reserve_aligned(name, len,
2255                                 socket_id, 0, I40E_ALIGN);
2256 #endif
2257         return mz;
2258 }
2259
2260 void
2261 i40e_rx_queue_release_mbufs(struct i40e_rx_queue *rxq)
2262 {
2263         uint16_t i;
2264
2265         if (!rxq || !rxq->sw_ring) {
2266                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2267                 return;
2268         }
2269
2270         for (i = 0; i < rxq->nb_rx_desc; i++) {
2271                 if (rxq->sw_ring[i].mbuf) {
2272                         rte_pktmbuf_free_seg(rxq->sw_ring[i].mbuf);
2273                         rxq->sw_ring[i].mbuf = NULL;
2274                 }
2275         }
2276 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2277         if (rxq->rx_nb_avail == 0)
2278                 return;
2279         for (i = 0; i < rxq->rx_nb_avail; i++) {
2280                 struct rte_mbuf *mbuf;
2281
2282                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
2283                 rte_pktmbuf_free_seg(mbuf);
2284         }
2285         rxq->rx_nb_avail = 0;
2286 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2287 }
2288
2289 void
2290 i40e_reset_rx_queue(struct i40e_rx_queue *rxq)
2291 {
2292         unsigned i;
2293         uint16_t len;
2294
2295 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2296         if (check_rx_burst_bulk_alloc_preconditions(rxq) == 0)
2297                 len = (uint16_t)(rxq->nb_rx_desc + RTE_PMD_I40E_RX_MAX_BURST);
2298         else
2299 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2300                 len = rxq->nb_rx_desc;
2301
2302         for (i = 0; i < len * sizeof(union i40e_rx_desc); i++)
2303                 ((volatile char *)rxq->rx_ring)[i] = 0;
2304
2305 #ifdef RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC
2306         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
2307         for (i = 0; i < RTE_PMD_I40E_RX_MAX_BURST; ++i)
2308                 rxq->sw_ring[rxq->nb_rx_desc + i].mbuf = &rxq->fake_mbuf;
2309
2310         rxq->rx_nb_avail = 0;
2311         rxq->rx_next_avail = 0;
2312         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
2313 #endif /* RTE_LIBRTE_I40E_RX_ALLOW_BULK_ALLOC */
2314         rxq->rx_tail = 0;
2315         rxq->nb_rx_hold = 0;
2316         rxq->pkt_first_seg = NULL;
2317         rxq->pkt_last_seg = NULL;
2318 }
2319
2320 void
2321 i40e_tx_queue_release_mbufs(struct i40e_tx_queue *txq)
2322 {
2323         uint16_t i;
2324
2325         if (!txq || !txq->sw_ring) {
2326                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
2327                 return;
2328         }
2329
2330         for (i = 0; i < txq->nb_tx_desc; i++) {
2331                 if (txq->sw_ring[i].mbuf) {
2332                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
2333                         txq->sw_ring[i].mbuf = NULL;
2334                 }
2335         }
2336 }
2337
2338 void
2339 i40e_reset_tx_queue(struct i40e_tx_queue *txq)
2340 {
2341         struct i40e_tx_entry *txe;
2342         uint16_t i, prev, size;
2343
2344         if (!txq) {
2345                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
2346                 return;
2347         }
2348
2349         txe = txq->sw_ring;
2350         size = sizeof(struct i40e_tx_desc) * txq->nb_tx_desc;
2351         for (i = 0; i < size; i++)
2352                 ((volatile char *)txq->tx_ring)[i] = 0;
2353
2354         prev = (uint16_t)(txq->nb_tx_desc - 1);
2355         for (i = 0; i < txq->nb_tx_desc; i++) {
2356                 volatile struct i40e_tx_desc *txd = &txq->tx_ring[i];
2357
2358                 txd->cmd_type_offset_bsz =
2359                         rte_cpu_to_le_64(I40E_TX_DESC_DTYPE_DESC_DONE);
2360                 txe[i].mbuf =  NULL;
2361                 txe[i].last_id = i;
2362                 txe[prev].next_id = i;
2363                 prev = i;
2364         }
2365
2366         txq->tx_next_dd = (uint16_t)(txq->tx_rs_thresh - 1);
2367         txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
2368
2369         txq->tx_tail = 0;
2370         txq->nb_tx_used = 0;
2371
2372         txq->last_desc_cleaned = (uint16_t)(txq->nb_tx_desc - 1);
2373         txq->nb_tx_free = (uint16_t)(txq->nb_tx_desc - 1);
2374 }
2375
2376 /* Init the TX queue in hardware */
2377 int
2378 i40e_tx_queue_init(struct i40e_tx_queue *txq)
2379 {
2380         enum i40e_status_code err = I40E_SUCCESS;
2381         struct i40e_vsi *vsi = txq->vsi;
2382         struct i40e_hw *hw = I40E_VSI_TO_HW(vsi);
2383         uint16_t pf_q = txq->reg_idx;
2384         struct i40e_hmc_obj_txq tx_ctx;
2385         uint32_t qtx_ctl;
2386
2387         /* clear the context structure first */
2388         memset(&tx_ctx, 0, sizeof(tx_ctx));
2389         tx_ctx.new_context = 1;
2390         tx_ctx.base = txq->tx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2391         tx_ctx.qlen = txq->nb_tx_desc;
2392         tx_ctx.rdylist = rte_le_to_cpu_16(vsi->info.qs_handle[0]);
2393         if (vsi->type == I40E_VSI_FDIR)
2394                 tx_ctx.fd_ena = TRUE;
2395
2396         err = i40e_clear_lan_tx_queue_context(hw, pf_q);
2397         if (err != I40E_SUCCESS) {
2398                 PMD_DRV_LOG(ERR, "Failure of clean lan tx queue context");
2399                 return err;
2400         }
2401
2402         err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
2403         if (err != I40E_SUCCESS) {
2404                 PMD_DRV_LOG(ERR, "Failure of set lan tx queue context");
2405                 return err;
2406         }
2407
2408         /* Now associate this queue with this PCI function */
2409         qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
2410         qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
2411                                         I40E_QTX_CTL_PF_INDX_MASK);
2412         I40E_WRITE_REG(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
2413         I40E_WRITE_FLUSH(hw);
2414
2415         txq->qtx_tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
2416
2417         return err;
2418 }
2419
2420 int
2421 i40e_alloc_rx_queue_mbufs(struct i40e_rx_queue *rxq)
2422 {
2423         struct i40e_rx_entry *rxe = rxq->sw_ring;
2424         uint64_t dma_addr;
2425         uint16_t i;
2426
2427         for (i = 0; i < rxq->nb_rx_desc; i++) {
2428                 volatile union i40e_rx_desc *rxd;
2429                 struct rte_mbuf *mbuf = rte_rxmbuf_alloc(rxq->mp);
2430
2431                 if (unlikely(!mbuf)) {
2432                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
2433                         return -ENOMEM;
2434                 }
2435
2436                 rte_mbuf_refcnt_set(mbuf, 1);
2437                 mbuf->next = NULL;
2438                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
2439                 mbuf->nb_segs = 1;
2440                 mbuf->port = rxq->port_id;
2441
2442                 dma_addr =
2443                         rte_cpu_to_le_64(RTE_MBUF_DATA_DMA_ADDR_DEFAULT(mbuf));
2444
2445                 rxd = &rxq->rx_ring[i];
2446                 rxd->read.pkt_addr = dma_addr;
2447                 rxd->read.hdr_addr = dma_addr;
2448 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2449                 rxd->read.rsvd1 = 0;
2450                 rxd->read.rsvd2 = 0;
2451 #endif /* RTE_LIBRTE_I40E_16BYTE_RX_DESC */
2452
2453                 rxe[i].mbuf = mbuf;
2454         }
2455
2456         return 0;
2457 }
2458
2459 /*
2460  * Calculate the buffer length, and check the jumbo frame
2461  * and maximum packet length.
2462  */
2463 static int
2464 i40e_rx_queue_config(struct i40e_rx_queue *rxq)
2465 {
2466         struct i40e_pf *pf = I40E_VSI_TO_PF(rxq->vsi);
2467         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2468         struct rte_eth_dev_data *data = pf->dev_data;
2469         uint16_t buf_size, len;
2470
2471         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2472                 RTE_PKTMBUF_HEADROOM);
2473
2474         switch (pf->flags & (I40E_FLAG_HEADER_SPLIT_DISABLED |
2475                         I40E_FLAG_HEADER_SPLIT_ENABLED)) {
2476         case I40E_FLAG_HEADER_SPLIT_ENABLED: /* Not supported */
2477                 rxq->rx_hdr_len = RTE_ALIGN(I40E_RXBUF_SZ_1024,
2478                                 (1 << I40E_RXQ_CTX_HBUFF_SHIFT));
2479                 rxq->rx_buf_len = RTE_ALIGN(I40E_RXBUF_SZ_2048,
2480                                 (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2481                 rxq->hs_mode = i40e_header_split_enabled;
2482                 break;
2483         case I40E_FLAG_HEADER_SPLIT_DISABLED:
2484         default:
2485                 rxq->rx_hdr_len = 0;
2486                 rxq->rx_buf_len = RTE_ALIGN(buf_size,
2487                         (1 << I40E_RXQ_CTX_DBUFF_SHIFT));
2488                 rxq->hs_mode = i40e_header_split_none;
2489                 break;
2490         }
2491
2492         len = hw->func_caps.rx_buf_chain_len * rxq->rx_buf_len;
2493         rxq->max_pkt_len = RTE_MIN(len, data->dev_conf.rxmode.max_rx_pkt_len);
2494         if (data->dev_conf.rxmode.jumbo_frame == 1) {
2495                 if (rxq->max_pkt_len <= ETHER_MAX_LEN ||
2496                         rxq->max_pkt_len > I40E_FRAME_SIZE_MAX) {
2497                         PMD_DRV_LOG(ERR, "maximum packet length must "
2498                                     "be larger than %u and smaller than %u,"
2499                                     "as jumbo frame is enabled",
2500                                     (uint32_t)ETHER_MAX_LEN,
2501                                     (uint32_t)I40E_FRAME_SIZE_MAX);
2502                         return I40E_ERR_CONFIG;
2503                 }
2504         } else {
2505                 if (rxq->max_pkt_len < ETHER_MIN_LEN ||
2506                         rxq->max_pkt_len > ETHER_MAX_LEN) {
2507                         PMD_DRV_LOG(ERR, "maximum packet length must be "
2508                                     "larger than %u and smaller than %u, "
2509                                     "as jumbo frame is disabled",
2510                                     (uint32_t)ETHER_MIN_LEN,
2511                                     (uint32_t)ETHER_MAX_LEN);
2512                         return I40E_ERR_CONFIG;
2513                 }
2514         }
2515
2516         return 0;
2517 }
2518
2519 /* Init the RX queue in hardware */
2520 int
2521 i40e_rx_queue_init(struct i40e_rx_queue *rxq)
2522 {
2523         int err = I40E_SUCCESS;
2524         struct i40e_hw *hw = I40E_VSI_TO_HW(rxq->vsi);
2525         struct rte_eth_dev_data *dev_data = I40E_VSI_TO_DEV_DATA(rxq->vsi);
2526         struct rte_eth_dev *dev = I40E_VSI_TO_ETH_DEV(rxq->vsi);
2527         uint16_t pf_q = rxq->reg_idx;
2528         uint16_t buf_size;
2529         struct i40e_hmc_obj_rxq rx_ctx;
2530
2531         err = i40e_rx_queue_config(rxq);
2532         if (err < 0) {
2533                 PMD_DRV_LOG(ERR, "Failed to config RX queue");
2534                 return err;
2535         }
2536
2537         /* Clear the context structure first */
2538         memset(&rx_ctx, 0, sizeof(struct i40e_hmc_obj_rxq));
2539         rx_ctx.dbuff = rxq->rx_buf_len >> I40E_RXQ_CTX_DBUFF_SHIFT;
2540         rx_ctx.hbuff = rxq->rx_hdr_len >> I40E_RXQ_CTX_HBUFF_SHIFT;
2541
2542         rx_ctx.base = rxq->rx_ring_phys_addr / I40E_QUEUE_BASE_ADDR_UNIT;
2543         rx_ctx.qlen = rxq->nb_rx_desc;
2544 #ifndef RTE_LIBRTE_I40E_16BYTE_RX_DESC
2545         rx_ctx.dsize = 1;
2546 #endif
2547         rx_ctx.dtype = rxq->hs_mode;
2548         if (rxq->hs_mode)
2549                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_ALL;
2550         else
2551                 rx_ctx.hsplit_0 = I40E_HEADER_SPLIT_NONE;
2552         rx_ctx.rxmax = rxq->max_pkt_len;
2553         rx_ctx.tphrdesc_ena = 1;
2554         rx_ctx.tphwdesc_ena = 1;
2555         rx_ctx.tphdata_ena = 1;
2556         rx_ctx.tphhead_ena = 1;
2557         rx_ctx.lrxqthresh = 2;
2558         rx_ctx.crcstrip = (rxq->crc_len == 0) ? 1 : 0;
2559         rx_ctx.l2tsel = 1;
2560         rx_ctx.showiv = 1;
2561         rx_ctx.prefena = 1;
2562
2563         err = i40e_clear_lan_rx_queue_context(hw, pf_q);
2564         if (err != I40E_SUCCESS) {
2565                 PMD_DRV_LOG(ERR, "Failed to clear LAN RX queue context");
2566                 return err;
2567         }
2568         err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
2569         if (err != I40E_SUCCESS) {
2570                 PMD_DRV_LOG(ERR, "Failed to set LAN RX queue context");
2571                 return err;
2572         }
2573
2574         rxq->qrx_tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
2575
2576         buf_size = (uint16_t)(rte_pktmbuf_data_room_size(rxq->mp) -
2577                 RTE_PKTMBUF_HEADROOM);
2578
2579         /* Check if scattered RX needs to be used. */
2580         if ((rxq->max_pkt_len + 2 * I40E_VLAN_TAG_SIZE) > buf_size) {
2581                 dev_data->scattered_rx = 1;
2582                 dev->rx_pkt_burst = i40e_recv_scattered_pkts;
2583         }
2584
2585         /* Init the RX tail regieter. */
2586         I40E_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
2587
2588         return 0;
2589 }
2590
2591 void
2592 i40e_dev_clear_queues(struct rte_eth_dev *dev)
2593 {
2594         uint16_t i;
2595
2596         PMD_INIT_FUNC_TRACE();
2597
2598         for (i = 0; i < dev->data->nb_tx_queues; i++) {
2599                 i40e_tx_queue_release_mbufs(dev->data->tx_queues[i]);
2600                 i40e_reset_tx_queue(dev->data->tx_queues[i]);
2601         }
2602
2603         for (i = 0; i < dev->data->nb_rx_queues; i++) {
2604                 i40e_rx_queue_release_mbufs(dev->data->rx_queues[i]);
2605                 i40e_reset_rx_queue(dev->data->rx_queues[i]);
2606         }
2607 }
2608
2609 #define I40E_FDIR_NUM_TX_DESC  I40E_MIN_RING_DESC
2610 #define I40E_FDIR_NUM_RX_DESC  I40E_MIN_RING_DESC
2611
2612 enum i40e_status_code
2613 i40e_fdir_setup_tx_resources(struct i40e_pf *pf)
2614 {
2615         struct i40e_tx_queue *txq;
2616         const struct rte_memzone *tz = NULL;
2617         uint32_t ring_size;
2618         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2619
2620         if (!pf) {
2621                 PMD_DRV_LOG(ERR, "PF is not available");
2622                 return I40E_ERR_BAD_PTR;
2623         }
2624
2625         /* Allocate the TX queue data structure. */
2626         txq = rte_zmalloc_socket("i40e fdir tx queue",
2627                                   sizeof(struct i40e_tx_queue),
2628                                   RTE_CACHE_LINE_SIZE,
2629                                   SOCKET_ID_ANY);
2630         if (!txq) {
2631                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2632                                         "tx queue structure.");
2633                 return I40E_ERR_NO_MEMORY;
2634         }
2635
2636         /* Allocate TX hardware ring descriptors. */
2637         ring_size = sizeof(struct i40e_tx_desc) * I40E_FDIR_NUM_TX_DESC;
2638         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2639
2640         tz = i40e_ring_dma_zone_reserve(dev,
2641                                         "fdir_tx_ring",
2642                                         I40E_FDIR_QUEUE_ID,
2643                                         ring_size,
2644                                         SOCKET_ID_ANY);
2645         if (!tz) {
2646                 i40e_dev_tx_queue_release(txq);
2647                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for TX.");
2648                 return I40E_ERR_NO_MEMORY;
2649         }
2650
2651         txq->nb_tx_desc = I40E_FDIR_NUM_TX_DESC;
2652         txq->queue_id = I40E_FDIR_QUEUE_ID;
2653         txq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2654         txq->vsi = pf->fdir.fdir_vsi;
2655
2656 #ifdef RTE_LIBRTE_XEN_DOM0
2657         txq->tx_ring_phys_addr = rte_mem_phy2mch(tz->memseg_id, tz->phys_addr);
2658 #else
2659         txq->tx_ring_phys_addr = (uint64_t)tz->phys_addr;
2660 #endif
2661         txq->tx_ring = (struct i40e_tx_desc *)tz->addr;
2662         /*
2663          * don't need to allocate software ring and reset for the fdir
2664          * program queue just set the queue has been configured.
2665          */
2666         txq->q_set = TRUE;
2667         pf->fdir.txq = txq;
2668
2669         return I40E_SUCCESS;
2670 }
2671
2672 enum i40e_status_code
2673 i40e_fdir_setup_rx_resources(struct i40e_pf *pf)
2674 {
2675         struct i40e_rx_queue *rxq;
2676         const struct rte_memzone *rz = NULL;
2677         uint32_t ring_size;
2678         struct rte_eth_dev *dev = pf->adapter->eth_dev;
2679
2680         if (!pf) {
2681                 PMD_DRV_LOG(ERR, "PF is not available");
2682                 return I40E_ERR_BAD_PTR;
2683         }
2684
2685         /* Allocate the RX queue data structure. */
2686         rxq = rte_zmalloc_socket("i40e fdir rx queue",
2687                                   sizeof(struct i40e_rx_queue),
2688                                   RTE_CACHE_LINE_SIZE,
2689                                   SOCKET_ID_ANY);
2690         if (!rxq) {
2691                 PMD_DRV_LOG(ERR, "Failed to allocate memory for "
2692                                         "rx queue structure.");
2693                 return I40E_ERR_NO_MEMORY;
2694         }
2695
2696         /* Allocate RX hardware ring descriptors. */
2697         ring_size = sizeof(union i40e_rx_desc) * I40E_FDIR_NUM_RX_DESC;
2698         ring_size = RTE_ALIGN(ring_size, I40E_DMA_MEM_ALIGN);
2699
2700         rz = i40e_ring_dma_zone_reserve(dev,
2701                                         "fdir_rx_ring",
2702                                         I40E_FDIR_QUEUE_ID,
2703                                         ring_size,
2704                                         SOCKET_ID_ANY);
2705         if (!rz) {
2706                 i40e_dev_rx_queue_release(rxq);
2707                 PMD_DRV_LOG(ERR, "Failed to reserve DMA memory for RX.");
2708                 return I40E_ERR_NO_MEMORY;
2709         }
2710
2711         rxq->nb_rx_desc = I40E_FDIR_NUM_RX_DESC;
2712         rxq->queue_id = I40E_FDIR_QUEUE_ID;
2713         rxq->reg_idx = pf->fdir.fdir_vsi->base_queue;
2714         rxq->vsi = pf->fdir.fdir_vsi;
2715
2716 #ifdef RTE_LIBRTE_XEN_DOM0
2717         rxq->rx_ring_phys_addr = rte_mem_phy2mch(rz->memseg_id, rz->phys_addr);
2718 #else
2719         rxq->rx_ring_phys_addr = (uint64_t)rz->phys_addr;
2720 #endif
2721         rxq->rx_ring = (union i40e_rx_desc *)rz->addr;
2722
2723         /*
2724          * Don't need to allocate software ring and reset for the fdir
2725          * rx queue, just set the queue has been configured.
2726          */
2727         rxq->q_set = TRUE;
2728         pf->fdir.rxq = rxq;
2729
2730         return I40E_SUCCESS;
2731 }