1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2010-2015 Intel Corporation.
3 * Copyright(c) 2016-2018, Linaro Limited.
7 #include <ethdev_driver.h>
8 #include <rte_malloc.h>
11 #include "base/i40e_prototype.h"
12 #include "base/i40e_type.h"
13 #include "i40e_ethdev.h"
14 #include "i40e_rxtx.h"
15 #include "i40e_rxtx_vec_common.h"
18 #pragma GCC diagnostic ignored "-Wcast-qual"
21 i40e_rxq_rearm(struct i40e_rx_queue *rxq)
25 volatile union i40e_rx_desc *rxdp;
26 struct i40e_rx_entry *rxep = &rxq->sw_ring[rxq->rxrearm_start];
27 struct rte_mbuf *mb0, *mb1;
28 uint64x2_t dma_addr0, dma_addr1;
29 uint64x2_t zero = vdupq_n_u64(0);
32 rxdp = rxq->rx_ring + rxq->rxrearm_start;
34 /* Pull 'n' more MBUFs into the software ring */
35 if (unlikely(rte_mempool_get_bulk(rxq->mp,
37 RTE_I40E_RXQ_REARM_THRESH) < 0)) {
38 if (rxq->rxrearm_nb + RTE_I40E_RXQ_REARM_THRESH >=
40 for (i = 0; i < RTE_I40E_DESCS_PER_LOOP; i++) {
41 rxep[i].mbuf = &rxq->fake_mbuf;
42 vst1q_u64((uint64_t *)&rxdp[i].read, zero);
45 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
46 RTE_I40E_RXQ_REARM_THRESH;
50 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
51 for (i = 0; i < RTE_I40E_RXQ_REARM_THRESH; i += 2, rxep += 2) {
55 paddr = mb0->buf_iova + RTE_PKTMBUF_HEADROOM;
56 dma_addr0 = vdupq_n_u64(paddr);
58 /* flush desc with pa dma_addr */
59 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr0);
61 paddr = mb1->buf_iova + RTE_PKTMBUF_HEADROOM;
62 dma_addr1 = vdupq_n_u64(paddr);
63 vst1q_u64((uint64_t *)&rxdp++->read, dma_addr1);
66 rxq->rxrearm_start += RTE_I40E_RXQ_REARM_THRESH;
67 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
68 rxq->rxrearm_start = 0;
70 rxq->rxrearm_nb -= RTE_I40E_RXQ_REARM_THRESH;
72 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
73 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
76 /* Update the tail pointer on the NIC */
77 I40E_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rx_id);
81 desc_to_olflags_v(struct i40e_rx_queue *rxq, uint64x2_t descs[4],
82 struct rte_mbuf **rx_pkts)
84 uint32x4_t vlan0, vlan1, rss, l3_l4e;
85 const uint64x2_t mbuf_init = {rxq->mbuf_initializer, 0};
86 uint64x2_t rearm0, rearm1, rearm2, rearm3;
88 /* mask everything except RSS, flow director and VLAN flags
89 * bit2 is for VLAN tag, bit11 for flow director indication
90 * bit13:12 for RSS indication.
92 const uint32x4_t rss_vlan_msk = {
93 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804};
95 const uint32x4_t cksum_mask = {
96 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
97 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
98 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
99 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
100 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
101 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
102 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
103 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
104 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD,
105 RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
106 RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
107 RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD};
109 /* map rss and vlan type to rss hash and vlan flag */
110 const uint8x16_t vlan_flags = {
112 RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED, 0,
117 const uint8x16_t rss_flags = {
118 0, RTE_MBUF_F_RX_FDIR, 0, 0,
119 0, 0, RTE_MBUF_F_RX_RSS_HASH,
120 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR,
124 const uint8x16_t l3_l4e_flags = {
125 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
126 RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
127 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
128 (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
129 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
130 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
131 (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
132 RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
133 (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
134 RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
135 0, 0, 0, 0, 0, 0, 0, 0};
137 vlan0 = vzipq_u32(vreinterpretq_u32_u64(descs[0]),
138 vreinterpretq_u32_u64(descs[2])).val[1];
139 vlan1 = vzipq_u32(vreinterpretq_u32_u64(descs[1]),
140 vreinterpretq_u32_u64(descs[3])).val[1];
141 vlan0 = vzipq_u32(vlan0, vlan1).val[0];
143 vlan1 = vandq_u32(vlan0, rss_vlan_msk);
144 vlan0 = vreinterpretq_u32_u8(vqtbl1q_u8(vlan_flags,
145 vreinterpretq_u8_u32(vlan1)));
147 rss = vshrq_n_u32(vlan1, 11);
148 rss = vreinterpretq_u32_u8(vqtbl1q_u8(rss_flags,
149 vreinterpretq_u8_u32(rss)));
151 l3_l4e = vshrq_n_u32(vlan1, 22);
152 l3_l4e = vreinterpretq_u32_u8(vqtbl1q_u8(l3_l4e_flags,
153 vreinterpretq_u8_u32(l3_l4e)));
154 /* then we shift left 1 bit */
155 l3_l4e = vshlq_n_u32(l3_l4e, 1);
156 /* we need to mask out the reduntant bits */
157 l3_l4e = vandq_u32(l3_l4e, cksum_mask);
159 vlan0 = vorrq_u32(vlan0, rss);
160 vlan0 = vorrq_u32(vlan0, l3_l4e);
162 rearm0 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 0), mbuf_init, 1);
163 rearm1 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 1), mbuf_init, 1);
164 rearm2 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 2), mbuf_init, 1);
165 rearm3 = vsetq_lane_u64(vgetq_lane_u32(vlan0, 3), mbuf_init, 1);
167 vst1q_u64((uint64_t *)&rx_pkts[0]->rearm_data, rearm0);
168 vst1q_u64((uint64_t *)&rx_pkts[1]->rearm_data, rearm1);
169 vst1q_u64((uint64_t *)&rx_pkts[2]->rearm_data, rearm2);
170 vst1q_u64((uint64_t *)&rx_pkts[3]->rearm_data, rearm3);
173 #define PKTLEN_SHIFT 10
174 #define I40E_UINT16_BIT (CHAR_BIT * sizeof(uint16_t))
177 desc_to_ptype_v(uint64x2_t descs[4], struct rte_mbuf **__rte_restrict rx_pkts,
178 uint32_t *__rte_restrict ptype_tbl)
184 for (i = 0; i < 4; i++) {
185 tmp = vreinterpretq_u8_u64(vshrq_n_u64(descs[i], 30));
186 ptype = vgetq_lane_u8(tmp, 8);
187 rx_pkts[i]->packet_type = ptype_tbl[ptype];
193 * vPMD raw receive routine, only accept(nb_pkts >= RTE_I40E_DESCS_PER_LOOP)
196 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
197 * - floor align nb_pkts to a RTE_I40E_DESCS_PER_LOOP power-of-two
199 static inline uint16_t
200 _recv_raw_pkts_vec(struct i40e_rx_queue *__rte_restrict rxq,
201 struct rte_mbuf **__rte_restrict rx_pkts,
202 uint16_t nb_pkts, uint8_t *split_packet)
204 volatile union i40e_rx_desc *rxdp;
205 struct i40e_rx_entry *sw_ring;
206 uint16_t nb_pkts_recd;
208 uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
210 /* mask to shuffle from desc. to mbuf */
211 uint8x16_t shuf_msk = {
212 0xFF, 0xFF, /* pkt_type set as unknown */
213 0xFF, 0xFF, /* pkt_type set as unknown */
214 14, 15, /* octet 15~14, low 16 bits pkt_len */
215 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
216 14, 15, /* octet 15~14, 16 bits data_len */
217 2, 3, /* octet 2~3, low 16 bits vlan_macip */
218 4, 5, 6, 7 /* octet 4~7, 32bits rss */
221 uint8x16_t eop_check = {
222 0x02, 0x00, 0x02, 0x00,
223 0x02, 0x00, 0x02, 0x00,
224 0x00, 0x00, 0x00, 0x00,
225 0x00, 0x00, 0x00, 0x00
228 uint16x8_t crc_adjust = {
229 0, 0, /* ignore pkt_type field */
230 rxq->crc_len, /* sub crc on pkt_len */
231 0, /* ignore high-16bits of pkt_len */
232 rxq->crc_len, /* sub crc on data_len */
233 0, 0, 0 /* ignore non-length fields */
236 /* nb_pkts has to be floor-aligned to RTE_I40E_DESCS_PER_LOOP */
237 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, RTE_I40E_DESCS_PER_LOOP);
239 /* Just the act of getting into the function from the application is
240 * going to cost about 7 cycles
242 rxdp = rxq->rx_ring + rxq->rx_tail;
244 rte_prefetch_non_temporal(rxdp);
246 /* See if we need to rearm the RX queue - gives the prefetch a bit
249 if (rxq->rxrearm_nb > RTE_I40E_RXQ_REARM_THRESH)
252 /* Before we start moving massive data around, check to see if
253 * there is actually a packet available
255 if (!(rxdp->wb.qword1.status_error_len &
256 rte_cpu_to_le_32(1 << I40E_RX_DESC_STATUS_DD_SHIFT)))
259 /* Cache is empty -> need to scan the buffer rings, but first move
260 * the next 'n' mbufs into the cache
262 sw_ring = &rxq->sw_ring[rxq->rx_tail];
264 /* A. load 4 packet in one loop
265 * [A*. mask out 4 unused dirty field in desc]
266 * B. copy 4 mbuf point from swring to rx_pkts
267 * C. calc the number of DD bits among the 4 packets
268 * [C*. extract the end-of-packet bit, if requested]
269 * D. fill info. from desc to mbuf
272 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
273 pos += RTE_I40E_DESCS_PER_LOOP,
274 rxdp += RTE_I40E_DESCS_PER_LOOP) {
275 uint64x2_t descs[RTE_I40E_DESCS_PER_LOOP];
276 uint8x16_t pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
277 uint16x8x2_t sterr_tmp1, sterr_tmp2;
278 uint64x2_t mbp1, mbp2;
283 int32x4_t len_shl = {0, 0, 0, PKTLEN_SHIFT};
285 /* B.1 load 1 mbuf point */
286 mbp1 = vld1q_u64((uint64_t *)&sw_ring[pos]);
287 /* Read desc statuses backwards to avoid race condition */
288 /* A.1 load 4 pkts desc */
289 descs[3] = vld1q_u64((uint64_t *)(rxdp + 3));
291 /* B.2 copy 2 mbuf point into rx_pkts */
292 vst1q_u64((uint64_t *)&rx_pkts[pos], mbp1);
294 /* B.1 load 1 mbuf point */
295 mbp2 = vld1q_u64((uint64_t *)&sw_ring[pos + 2]);
297 descs[2] = vld1q_u64((uint64_t *)(rxdp + 2));
298 /* B.1 load 2 mbuf point */
299 descs[1] = vld1q_u64((uint64_t *)(rxdp + 1));
300 descs[0] = vld1q_u64((uint64_t *)(rxdp));
302 /* B.2 copy 2 mbuf point into rx_pkts */
303 vst1q_u64((uint64_t *)&rx_pkts[pos + 2], mbp2);
306 rte_mbuf_prefetch_part2(rx_pkts[pos]);
307 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
308 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
309 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
312 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
313 uint32x4_t len3 = vshlq_u32(vreinterpretq_u32_u64(descs[3]),
315 descs[3] = vreinterpretq_u64_u16(vsetq_lane_u16
316 (vgetq_lane_u16(vreinterpretq_u16_u32(len3), 7),
317 vreinterpretq_u16_u64(descs[3]),
319 uint32x4_t len2 = vshlq_u32(vreinterpretq_u32_u64(descs[2]),
321 descs[2] = vreinterpretq_u64_u16(vsetq_lane_u16
322 (vgetq_lane_u16(vreinterpretq_u16_u32(len2), 7),
323 vreinterpretq_u16_u64(descs[2]),
326 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
327 pkt_mb4 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[3]), shuf_msk);
328 pkt_mb3 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[2]), shuf_msk);
330 /* C.1 4=>2 filter staterr info only */
331 sterr_tmp2 = vzipq_u16(vreinterpretq_u16_u64(descs[1]),
332 vreinterpretq_u16_u64(descs[3]));
333 /* C.1 4=>2 filter staterr info only */
334 sterr_tmp1 = vzipq_u16(vreinterpretq_u16_u64(descs[0]),
335 vreinterpretq_u16_u64(descs[2]));
337 /* C.2 get 4 pkts staterr value */
338 staterr = vzipq_u16(sterr_tmp1.val[1],
339 sterr_tmp2.val[1]).val[0];
341 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
343 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
344 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb4), crc_adjust);
345 pkt_mb4 = vreinterpretq_u8_u16(tmp);
346 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb3), crc_adjust);
347 pkt_mb3 = vreinterpretq_u8_u16(tmp);
349 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
350 uint32x4_t len1 = vshlq_u32(vreinterpretq_u32_u64(descs[1]),
352 descs[1] = vreinterpretq_u64_u16(vsetq_lane_u16
353 (vgetq_lane_u16(vreinterpretq_u16_u32(len1), 7),
354 vreinterpretq_u16_u64(descs[1]),
356 uint32x4_t len0 = vshlq_u32(vreinterpretq_u32_u64(descs[0]),
358 descs[0] = vreinterpretq_u64_u16(vsetq_lane_u16
359 (vgetq_lane_u16(vreinterpretq_u16_u32(len0), 7),
360 vreinterpretq_u16_u64(descs[0]),
363 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
364 pkt_mb2 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[1]), shuf_msk);
365 pkt_mb1 = vqtbl1q_u8(vreinterpretq_u8_u64(descs[0]), shuf_msk);
367 /* D.3 copy final 3,4 data to rx_pkts */
368 vst1q_u8((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
370 vst1q_u8((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
373 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
374 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb2), crc_adjust);
375 pkt_mb2 = vreinterpretq_u8_u16(tmp);
376 tmp = vsubq_u16(vreinterpretq_u16_u8(pkt_mb1), crc_adjust);
377 pkt_mb1 = vreinterpretq_u8_u16(tmp);
379 /* C* extract and record EOP bit */
381 uint8x16_t eop_shuf_mask = {
382 0x00, 0x02, 0x04, 0x06,
383 0xFF, 0xFF, 0xFF, 0xFF,
384 0xFF, 0xFF, 0xFF, 0xFF,
385 0xFF, 0xFF, 0xFF, 0xFF};
388 /* and with mask to extract bits, flipping 1-0 */
389 eop_bits = vmvnq_u8(vreinterpretq_u8_u16(staterr));
390 eop_bits = vandq_u8(eop_bits, eop_check);
391 /* the staterr values are not in order, as the count
392 * count of dd bits doesn't care. However, for end of
393 * packet tracking, we do care, so shuffle. This also
394 * compresses the 32-bit values to 8-bit
396 eop_bits = vqtbl1q_u8(eop_bits, eop_shuf_mask);
398 /* store the resulting 32-bit value */
399 vst1q_lane_u32((uint32_t *)split_packet,
400 vreinterpretq_u32_u8(eop_bits), 0);
401 split_packet += RTE_I40E_DESCS_PER_LOOP;
403 /* zero-out next pointers */
404 rx_pkts[pos]->next = NULL;
405 rx_pkts[pos + 1]->next = NULL;
406 rx_pkts[pos + 2]->next = NULL;
407 rx_pkts[pos + 3]->next = NULL;
410 staterr = vshlq_n_u16(staterr, I40E_UINT16_BIT - 1);
411 staterr = vreinterpretq_u16_s16(
412 vshrq_n_s16(vreinterpretq_s16_u16(staterr),
413 I40E_UINT16_BIT - 1));
414 stat = ~vgetq_lane_u64(vreinterpretq_u64_u16(staterr), 0);
416 rte_prefetch_non_temporal(rxdp + RTE_I40E_DESCS_PER_LOOP);
418 /* D.3 copy final 1,2 data to rx_pkts */
419 vst1q_u8((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
421 vst1q_u8((void *)&rx_pkts[pos]->rx_descriptor_fields1,
423 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
424 /* C.4 calc avaialbe number of desc */
425 if (unlikely(stat == 0)) {
426 nb_pkts_recd += RTE_I40E_DESCS_PER_LOOP;
428 nb_pkts_recd += __builtin_ctzl(stat) / I40E_UINT16_BIT;
433 /* Update our internal tail pointer */
434 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
435 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
436 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
443 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
444 * - nb_pkts > RTE_I40E_VPMD_RX_BURST, only scan RTE_I40E_VPMD_RX_BURST
448 i40e_recv_pkts_vec(void *__rte_restrict rx_queue,
449 struct rte_mbuf **__rte_restrict rx_pkts, uint16_t nb_pkts)
451 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
455 * vPMD receive routine that reassembles single burst of 32 scattered packets
458 * - nb_pkts < RTE_I40E_DESCS_PER_LOOP, just return no packet
461 i40e_recv_scattered_burst_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
465 struct i40e_rx_queue *rxq = rx_queue;
466 uint8_t split_flags[RTE_I40E_VPMD_RX_BURST] = {0};
468 /* get some new buffers */
469 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
474 /* happy day case, full burst + no packets to be joined */
475 const uint64_t *split_fl64 = (uint64_t *)split_flags;
477 if (rxq->pkt_first_seg == NULL &&
478 split_fl64[0] == 0 && split_fl64[1] == 0 &&
479 split_fl64[2] == 0 && split_fl64[3] == 0)
482 /* reassemble any packets that need reassembly*/
485 if (rxq->pkt_first_seg == NULL) {
486 /* find the first split flag, and only reassemble then*/
487 while (i < nb_bufs && !split_flags[i])
491 rxq->pkt_first_seg = rx_pkts[i];
493 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
498 * vPMD receive routine that reassembles scattered packets.
501 i40e_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
506 while (nb_pkts > RTE_I40E_VPMD_RX_BURST) {
509 burst = i40e_recv_scattered_burst_vec(rx_queue,
511 RTE_I40E_VPMD_RX_BURST);
514 if (burst < RTE_I40E_VPMD_RX_BURST)
518 return retval + i40e_recv_scattered_burst_vec(rx_queue,
524 vtx1(volatile struct i40e_tx_desc *txdp,
525 struct rte_mbuf *pkt, uint64_t flags)
527 uint64_t high_qw = (I40E_TX_DESC_DTYPE_DATA |
528 ((uint64_t)flags << I40E_TXD_QW1_CMD_SHIFT) |
529 ((uint64_t)pkt->data_len << I40E_TXD_QW1_TX_BUF_SZ_SHIFT));
531 uint64x2_t descriptor = {pkt->buf_iova + pkt->data_off, high_qw};
532 vst1q_u64((uint64_t *)txdp, descriptor);
536 vtx(volatile struct i40e_tx_desc *txdp, struct rte_mbuf **pkt,
537 uint16_t nb_pkts, uint64_t flags)
541 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
542 vtx1(txdp, *pkt, flags);
546 i40e_xmit_fixed_burst_vec(void *__rte_restrict tx_queue,
547 struct rte_mbuf **__rte_restrict tx_pkts, uint16_t nb_pkts)
549 struct i40e_tx_queue *txq = (struct i40e_tx_queue *)tx_queue;
550 volatile struct i40e_tx_desc *txdp;
551 struct i40e_tx_entry *txep;
552 uint16_t n, nb_commit, tx_id;
553 uint64_t flags = I40E_TD_CMD;
554 uint64_t rs = I40E_TX_DESC_CMD_RS | I40E_TD_CMD;
557 /* cross rx_thresh boundary is not allowed */
558 nb_pkts = RTE_MIN(nb_pkts, txq->tx_rs_thresh);
560 if (txq->nb_tx_free < txq->tx_free_thresh)
561 i40e_tx_free_bufs(txq);
563 nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_tx_free, nb_pkts);
564 if (unlikely(nb_pkts == 0))
567 tx_id = txq->tx_tail;
568 txdp = &txq->tx_ring[tx_id];
569 txep = &txq->sw_ring[tx_id];
571 txq->nb_tx_free = (uint16_t)(txq->nb_tx_free - nb_pkts);
573 n = (uint16_t)(txq->nb_tx_desc - tx_id);
574 if (nb_commit >= n) {
575 tx_backlog_entry(txep, tx_pkts, n);
577 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
578 vtx1(txdp, *tx_pkts, flags);
580 vtx1(txdp, *tx_pkts++, rs);
582 nb_commit = (uint16_t)(nb_commit - n);
585 txq->tx_next_rs = (uint16_t)(txq->tx_rs_thresh - 1);
587 /* avoid reach the end of ring */
588 txdp = &txq->tx_ring[tx_id];
589 txep = &txq->sw_ring[tx_id];
592 tx_backlog_entry(txep, tx_pkts, nb_commit);
594 vtx(txdp, tx_pkts, nb_commit, flags);
596 tx_id = (uint16_t)(tx_id + nb_commit);
597 if (tx_id > txq->tx_next_rs) {
598 txq->tx_ring[txq->tx_next_rs].cmd_type_offset_bsz |=
599 rte_cpu_to_le_64(((uint64_t)I40E_TX_DESC_CMD_RS) <<
600 I40E_TXD_QW1_CMD_SHIFT);
602 (uint16_t)(txq->tx_next_rs + txq->tx_rs_thresh);
605 txq->tx_tail = tx_id;
608 I40E_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
614 i40e_rx_queue_release_mbufs_vec(struct i40e_rx_queue *rxq)
616 _i40e_rx_queue_release_mbufs_vec(rxq);
620 i40e_rxq_vec_setup(struct i40e_rx_queue *rxq)
622 return i40e_rxq_vec_setup_default(rxq);
626 i40e_txq_vec_setup(struct i40e_tx_queue __rte_unused *txq)
632 i40e_rx_vec_dev_conf_condition_check(struct rte_eth_dev *dev)
634 return i40e_rx_vec_dev_conf_condition_check_default(dev);