drivers/net/iavf/base/iavf_adminq_cmd.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _IAVF_ADMINQ_CMD_H_
  35 #define _IAVF_ADMINQ_CMD_H_
  36
  37 /* This header file defines the iavf Admin Queue commands and is shared between
  38  * iavf Firmware and Software.
  39  *
  40  * This file needs to comply with the Linux Kernel coding style.
  41  */
  42
  43
  44 #define IAVF_FW_API_VERSION_MAJOR       0x0001
  45 #define IAVF_FW_API_VERSION_MINOR_X722  0x0005
  46 #define IAVF_FW_API_VERSION_MINOR_X710  0x0007
  47
  48 #define IAVF_FW_MINOR_VERSION(_h) ((_h)->mac.type == IAVF_MAC_XL710 ? \
  49                                         IAVF_FW_API_VERSION_MINOR_X710 : \
  50                                         IAVF_FW_API_VERSION_MINOR_X722)
  51
  52 /* API version 1.7 implements additional link and PHY-specific APIs  */
  53 #define IAVF_MINOR_VER_GET_LINK_INFO_XL710 0x0007
  54
  55 struct iavf_aq_desc {
  56         __le16 flags;
  57         __le16 opcode;
  58         __le16 datalen;
  59         __le16 retval;
  60         __le32 cookie_high;
  61         __le32 cookie_low;
  62         union {
  63                 struct {
  64                         __le32 param0;
  65                         __le32 param1;
  66                         __le32 param2;
  67                         __le32 param3;
  68                 } internal;
  69                 struct {
  70                         __le32 param0;
  71                         __le32 param1;
  72                         __le32 addr_high;
  73                         __le32 addr_low;
  74                 } external;
  75                 u8 raw[16];
  76         } params;
  77 };
  78
  79 /* Flags sub-structure
  80  * |0  |1  |2  |3  |4  |5  |6  |7  |8  |9  |10 |11 |12 |13 |14 |15 |
  81  * |DD |CMP|ERR|VFE| * *  RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE |
  82  */
  83
  84 /* command flags and offsets*/
  85 #define IAVF_AQ_FLAG_DD_SHIFT   0
  86 #define IAVF_AQ_FLAG_CMP_SHIFT  1
  87 #define IAVF_AQ_FLAG_ERR_SHIFT  2
  88 #define IAVF_AQ_FLAG_VFE_SHIFT  3
  89 #define IAVF_AQ_FLAG_LB_SHIFT   9
  90 #define IAVF_AQ_FLAG_RD_SHIFT   10
  91 #define IAVF_AQ_FLAG_VFC_SHIFT  11
  92 #define IAVF_AQ_FLAG_BUF_SHIFT  12
  93 #define IAVF_AQ_FLAG_SI_SHIFT   13
  94 #define IAVF_AQ_FLAG_EI_SHIFT   14
  95 #define IAVF_AQ_FLAG_FE_SHIFT   15
  96
  97 #define IAVF_AQ_FLAG_DD         (1 << IAVF_AQ_FLAG_DD_SHIFT)  /* 0x1    */
  98 #define IAVF_AQ_FLAG_CMP        (1 << IAVF_AQ_FLAG_CMP_SHIFT) /* 0x2    */
  99 #define IAVF_AQ_FLAG_ERR        (1 << IAVF_AQ_FLAG_ERR_SHIFT) /* 0x4    */
 100 #define IAVF_AQ_FLAG_VFE        (1 << IAVF_AQ_FLAG_VFE_SHIFT) /* 0x8    */
 101 #define IAVF_AQ_FLAG_LB         (1 << IAVF_AQ_FLAG_LB_SHIFT)  /* 0x200  */
 102 #define IAVF_AQ_FLAG_RD         (1 << IAVF_AQ_FLAG_RD_SHIFT)  /* 0x400  */
 103 #define IAVF_AQ_FLAG_VFC        (1 << IAVF_AQ_FLAG_VFC_SHIFT) /* 0x800  */
 104 #define IAVF_AQ_FLAG_BUF        (1 << IAVF_AQ_FLAG_BUF_SHIFT) /* 0x1000 */
 105 #define IAVF_AQ_FLAG_SI         (1 << IAVF_AQ_FLAG_SI_SHIFT)  /* 0x2000 */
 106 #define IAVF_AQ_FLAG_EI         (1 << IAVF_AQ_FLAG_EI_SHIFT)  /* 0x4000 */
 107 #define IAVF_AQ_FLAG_FE         (1 << IAVF_AQ_FLAG_FE_SHIFT)  /* 0x8000 */
 108
 109 /* error codes */
 110 enum iavf_admin_queue_err {
 111         IAVF_AQ_RC_OK           = 0,  /* success */
 112         IAVF_AQ_RC_EPERM        = 1,  /* Operation not permitted */
 113         IAVF_AQ_RC_ENOENT       = 2,  /* No such element */
 114         IAVF_AQ_RC_ESRCH        = 3,  /* Bad opcode */
 115         IAVF_AQ_RC_EINTR        = 4,  /* operation interrupted */
 116         IAVF_AQ_RC_EIO          = 5,  /* I/O error */
 117         IAVF_AQ_RC_ENXIO        = 6,  /* No such resource */
 118         IAVF_AQ_RC_E2BIG        = 7,  /* Arg too long */
 119         IAVF_AQ_RC_EAGAIN       = 8,  /* Try again */
 120         IAVF_AQ_RC_ENOMEM       = 9,  /* Out of memory */
 121         IAVF_AQ_RC_EACCES       = 10, /* Permission denied */
 122         IAVF_AQ_RC_EFAULT       = 11, /* Bad address */
 123         IAVF_AQ_RC_EBUSY        = 12, /* Device or resource busy */
 124         IAVF_AQ_RC_EEXIST       = 13, /* object already exists */
 125         IAVF_AQ_RC_EINVAL       = 14, /* Invalid argument */
 126         IAVF_AQ_RC_ENOTTY       = 15, /* Not a typewriter */
 127         IAVF_AQ_RC_ENOSPC       = 16, /* No space left or alloc failure */
 128         IAVF_AQ_RC_ENOSYS       = 17, /* Function not implemented */
 129         IAVF_AQ_RC_ERANGE       = 18, /* Parameter out of range */
 130         IAVF_AQ_RC_EFLUSHED     = 19, /* Cmd flushed due to prev cmd error */
 131         IAVF_AQ_RC_BAD_ADDR     = 20, /* Descriptor contains a bad pointer */
 132         IAVF_AQ_RC_EMODE        = 21, /* Op not allowed in current dev mode */
 133         IAVF_AQ_RC_EFBIG        = 22, /* File too large */
 134 };
 135
 136 /* Admin Queue command opcodes */
 137 enum iavf_admin_queue_opc {
 138         /* aq commands */
 139         iavf_aqc_opc_get_version        = 0x0001,
 140         iavf_aqc_opc_driver_version     = 0x0002,
 141         iavf_aqc_opc_queue_shutdown     = 0x0003,
 142         iavf_aqc_opc_set_pf_context     = 0x0004,
 143
 144         /* resource ownership */
 145         iavf_aqc_opc_request_resource   = 0x0008,
 146         iavf_aqc_opc_release_resource   = 0x0009,
 147
 148         iavf_aqc_opc_list_func_capabilities     = 0x000A,
 149         iavf_aqc_opc_list_dev_capabilities      = 0x000B,
 150
 151         /* Proxy commands */
 152         iavf_aqc_opc_set_proxy_config           = 0x0104,
 153         iavf_aqc_opc_set_ns_proxy_table_entry   = 0x0105,
 154
 155         /* LAA */
 156         iavf_aqc_opc_mac_address_read   = 0x0107,
 157         iavf_aqc_opc_mac_address_write  = 0x0108,
 158
 159         /* PXE */
 160         iavf_aqc_opc_clear_pxe_mode     = 0x0110,
 161
 162         /* WoL commands */
 163         iavf_aqc_opc_set_wol_filter     = 0x0120,
 164         iavf_aqc_opc_get_wake_reason    = 0x0121,
 165         iavf_aqc_opc_clear_all_wol_filters = 0x025E,
 166
 167         /* internal switch commands */
 168         iavf_aqc_opc_get_switch_config          = 0x0200,
 169         iavf_aqc_opc_add_statistics             = 0x0201,
 170         iavf_aqc_opc_remove_statistics          = 0x0202,
 171         iavf_aqc_opc_set_port_parameters        = 0x0203,
 172         iavf_aqc_opc_get_switch_resource_alloc  = 0x0204,
 173         iavf_aqc_opc_set_switch_config          = 0x0205,
 174         iavf_aqc_opc_rx_ctl_reg_read            = 0x0206,
 175         iavf_aqc_opc_rx_ctl_reg_write           = 0x0207,
 176
 177         iavf_aqc_opc_add_vsi                    = 0x0210,
 178         iavf_aqc_opc_update_vsi_parameters      = 0x0211,
 179         iavf_aqc_opc_get_vsi_parameters         = 0x0212,
 180
 181         iavf_aqc_opc_add_pv                     = 0x0220,
 182         iavf_aqc_opc_update_pv_parameters       = 0x0221,
 183         iavf_aqc_opc_get_pv_parameters          = 0x0222,
 184
 185         iavf_aqc_opc_add_veb                    = 0x0230,
 186         iavf_aqc_opc_update_veb_parameters      = 0x0231,
 187         iavf_aqc_opc_get_veb_parameters         = 0x0232,
 188
 189         iavf_aqc_opc_delete_element             = 0x0243,
 190
 191         iavf_aqc_opc_add_macvlan                = 0x0250,
 192         iavf_aqc_opc_remove_macvlan             = 0x0251,
 193         iavf_aqc_opc_add_vlan                   = 0x0252,
 194         iavf_aqc_opc_remove_vlan                = 0x0253,
 195         iavf_aqc_opc_set_vsi_promiscuous_modes  = 0x0254,
 196         iavf_aqc_opc_add_tag                    = 0x0255,
 197         iavf_aqc_opc_remove_tag                 = 0x0256,
 198         iavf_aqc_opc_add_multicast_etag         = 0x0257,
 199         iavf_aqc_opc_remove_multicast_etag      = 0x0258,
 200         iavf_aqc_opc_update_tag                 = 0x0259,
 201         iavf_aqc_opc_add_control_packet_filter  = 0x025A,
 202         iavf_aqc_opc_remove_control_packet_filter       = 0x025B,
 203         iavf_aqc_opc_add_cloud_filters          = 0x025C,
 204         iavf_aqc_opc_remove_cloud_filters       = 0x025D,
 205         iavf_aqc_opc_clear_wol_switch_filters   = 0x025E,
 206         iavf_aqc_opc_replace_cloud_filters      = 0x025F,
 207
 208         iavf_aqc_opc_add_mirror_rule    = 0x0260,
 209         iavf_aqc_opc_delete_mirror_rule = 0x0261,
 210
 211         /* Dynamic Device Personalization */
 212         iavf_aqc_opc_write_personalization_profile      = 0x0270,
 213         iavf_aqc_opc_get_personalization_profile_list   = 0x0271,
 214
 215         /* DCB commands */
 216         iavf_aqc_opc_dcb_ignore_pfc     = 0x0301,
 217         iavf_aqc_opc_dcb_updated        = 0x0302,
 218         iavf_aqc_opc_set_dcb_parameters = 0x0303,
 219
 220         /* TX scheduler */
 221         iavf_aqc_opc_configure_vsi_bw_limit             = 0x0400,
 222         iavf_aqc_opc_configure_vsi_ets_sla_bw_limit     = 0x0406,
 223         iavf_aqc_opc_configure_vsi_tc_bw                = 0x0407,
 224         iavf_aqc_opc_query_vsi_bw_config                = 0x0408,
 225         iavf_aqc_opc_query_vsi_ets_sla_config           = 0x040A,
 226         iavf_aqc_opc_configure_switching_comp_bw_limit  = 0x0410,
 227
 228         iavf_aqc_opc_enable_switching_comp_ets                  = 0x0413,
 229         iavf_aqc_opc_modify_switching_comp_ets                  = 0x0414,
 230         iavf_aqc_opc_disable_switching_comp_ets                 = 0x0415,
 231         iavf_aqc_opc_configure_switching_comp_ets_bw_limit      = 0x0416,
 232         iavf_aqc_opc_configure_switching_comp_bw_config         = 0x0417,
 233         iavf_aqc_opc_query_switching_comp_ets_config            = 0x0418,
 234         iavf_aqc_opc_query_port_ets_config                      = 0x0419,
 235         iavf_aqc_opc_query_switching_comp_bw_config             = 0x041A,
 236         iavf_aqc_opc_suspend_port_tx                            = 0x041B,
 237         iavf_aqc_opc_resume_port_tx                             = 0x041C,
 238         iavf_aqc_opc_configure_partition_bw                     = 0x041D,
 239         /* hmc */
 240         iavf_aqc_opc_query_hmc_resource_profile = 0x0500,
 241         iavf_aqc_opc_set_hmc_resource_profile   = 0x0501,
 242
 243         /* phy commands*/
 244
 245         /* phy commands*/
 246         iavf_aqc_opc_get_phy_abilities          = 0x0600,
 247         iavf_aqc_opc_set_phy_config             = 0x0601,
 248         iavf_aqc_opc_set_mac_config             = 0x0603,
 249         iavf_aqc_opc_set_link_restart_an        = 0x0605,
 250         iavf_aqc_opc_get_link_status            = 0x0607,
 251         iavf_aqc_opc_set_phy_int_mask           = 0x0613,
 252         iavf_aqc_opc_get_local_advt_reg         = 0x0614,
 253         iavf_aqc_opc_set_local_advt_reg         = 0x0615,
 254         iavf_aqc_opc_get_partner_advt           = 0x0616,
 255         iavf_aqc_opc_set_lb_modes               = 0x0618,
 256         iavf_aqc_opc_get_phy_wol_caps           = 0x0621,
 257         iavf_aqc_opc_set_phy_debug              = 0x0622,
 258         iavf_aqc_opc_upload_ext_phy_fm          = 0x0625,
 259         iavf_aqc_opc_run_phy_activity           = 0x0626,
 260         iavf_aqc_opc_set_phy_register           = 0x0628,
 261         iavf_aqc_opc_get_phy_register           = 0x0629,
 262
 263         /* NVM commands */
 264         iavf_aqc_opc_nvm_read                   = 0x0701,
 265         iavf_aqc_opc_nvm_erase                  = 0x0702,
 266         iavf_aqc_opc_nvm_update                 = 0x0703,
 267         iavf_aqc_opc_nvm_config_read            = 0x0704,
 268         iavf_aqc_opc_nvm_config_write           = 0x0705,
 269         iavf_aqc_opc_nvm_progress               = 0x0706,
 270         iavf_aqc_opc_oem_post_update            = 0x0720,
 271         iavf_aqc_opc_thermal_sensor             = 0x0721,
 272
 273         /* virtualization commands */
 274         iavf_aqc_opc_send_msg_to_pf             = 0x0801,
 275         iavf_aqc_opc_send_msg_to_vf             = 0x0802,
 276         iavf_aqc_opc_send_msg_to_peer           = 0x0803,
 277
 278         /* alternate structure */
 279         iavf_aqc_opc_alternate_write            = 0x0900,
 280         iavf_aqc_opc_alternate_write_indirect   = 0x0901,
 281         iavf_aqc_opc_alternate_read             = 0x0902,
 282         iavf_aqc_opc_alternate_read_indirect    = 0x0903,
 283         iavf_aqc_opc_alternate_write_done       = 0x0904,
 284         iavf_aqc_opc_alternate_set_mode         = 0x0905,
 285         iavf_aqc_opc_alternate_clear_port       = 0x0906,
 286
 287         /* LLDP commands */
 288         iavf_aqc_opc_lldp_get_mib       = 0x0A00,
 289         iavf_aqc_opc_lldp_update_mib    = 0x0A01,
 290         iavf_aqc_opc_lldp_add_tlv       = 0x0A02,
 291         iavf_aqc_opc_lldp_update_tlv    = 0x0A03,
 292         iavf_aqc_opc_lldp_delete_tlv    = 0x0A04,
 293         iavf_aqc_opc_lldp_stop          = 0x0A05,
 294         iavf_aqc_opc_lldp_start         = 0x0A06,
 295         iavf_aqc_opc_get_cee_dcb_cfg    = 0x0A07,
 296         iavf_aqc_opc_lldp_set_local_mib = 0x0A08,
 297         iavf_aqc_opc_lldp_stop_start_spec_agent = 0x0A09,
 298
 299         /* Tunnel commands */
 300         iavf_aqc_opc_add_udp_tunnel     = 0x0B00,
 301         iavf_aqc_opc_del_udp_tunnel     = 0x0B01,
 302         iavf_aqc_opc_set_rss_key        = 0x0B02,
 303         iavf_aqc_opc_set_rss_lut        = 0x0B03,
 304         iavf_aqc_opc_get_rss_key        = 0x0B04,
 305         iavf_aqc_opc_get_rss_lut        = 0x0B05,
 306
 307         /* Async Events */
 308         iavf_aqc_opc_event_lan_overflow         = 0x1001,
 309
 310         /* OEM commands */
 311         iavf_aqc_opc_oem_parameter_change       = 0xFE00,
 312         iavf_aqc_opc_oem_device_status_change   = 0xFE01,
 313         iavf_aqc_opc_oem_ocsd_initialize        = 0xFE02,
 314         iavf_aqc_opc_oem_ocbb_initialize        = 0xFE03,
 315
 316         /* debug commands */
 317         iavf_aqc_opc_debug_read_reg             = 0xFF03,
 318         iavf_aqc_opc_debug_write_reg            = 0xFF04,
 319         iavf_aqc_opc_debug_modify_reg           = 0xFF07,
 320         iavf_aqc_opc_debug_dump_internals       = 0xFF08,
 321 };
 322
 323 /* command structures and indirect data structures */
 324
 325 /* Structure naming conventions:
 326  * - no suffix for direct command descriptor structures
 327  * - _data for indirect sent data
 328  * - _resp for indirect return data (data which is both will use _data)
 329  * - _completion for direct return data
 330  * - _element_ for repeated elements (may also be _data or _resp)
 331  *
 332  * Command structures are expected to overlay the params.raw member of the basic
 333  * descriptor, and as such cannot exceed 16 bytes in length.
 334  */
 335
 336 /* This macro is used to generate a compilation error if a structure
 337  * is not exactly the correct length. It gives a divide by zero error if the
 338  * structure is not of the correct size, otherwise it creates an enum that is
 339  * never used.
 340  */
 341 #define IAVF_CHECK_STRUCT_LEN(n, X) enum iavf_static_assert_enum_##X \
 342         { iavf_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) }
 343
 344 /* This macro is used extensively to ensure that command structures are 16
 345  * bytes in length as they have to map to the raw array of that size.
 346  */
 347 #define IAVF_CHECK_CMD_LENGTH(X)        IAVF_CHECK_STRUCT_LEN(16, X)
 348
 349 /* internal (0x00XX) commands */
 350
 351 /* Get version (direct 0x0001) */
 352 struct iavf_aqc_get_version {
 353         __le32 rom_ver;
 354         __le32 fw_build;
 355         __le16 fw_major;
 356         __le16 fw_minor;
 357         __le16 api_major;
 358         __le16 api_minor;
 359 };
 360
 361 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_version);
 362
 363 /* Send driver version (indirect 0x0002) */
 364 struct iavf_aqc_driver_version {
 365         u8      driver_major_ver;
 366         u8      driver_minor_ver;
 367         u8      driver_build_ver;
 368         u8      driver_subbuild_ver;
 369         u8      reserved[4];
 370         __le32  address_high;
 371         __le32  address_low;
 372 };
 373
 374 IAVF_CHECK_CMD_LENGTH(iavf_aqc_driver_version);
 375
 376 /* Queue Shutdown (direct 0x0003) */
 377 struct iavf_aqc_queue_shutdown {
 378         __le32  driver_unloading;
 379 #define IAVF_AQ_DRIVER_UNLOADING        0x1
 380         u8      reserved[12];
 381 };
 382
 383 IAVF_CHECK_CMD_LENGTH(iavf_aqc_queue_shutdown);
 384
 385 /* Set PF context (0x0004, direct) */
 386 struct iavf_aqc_set_pf_context {
 387         u8      pf_id;
 388         u8      reserved[15];
 389 };
 390
 391 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_pf_context);
 392
 393 /* Request resource ownership (direct 0x0008)
 394  * Release resource ownership (direct 0x0009)
 395  */
 396 #define IAVF_AQ_RESOURCE_NVM                    1
 397 #define IAVF_AQ_RESOURCE_SDP                    2
 398 #define IAVF_AQ_RESOURCE_ACCESS_READ            1
 399 #define IAVF_AQ_RESOURCE_ACCESS_WRITE           2
 400 #define IAVF_AQ_RESOURCE_NVM_READ_TIMEOUT       3000
 401 #define IAVF_AQ_RESOURCE_NVM_WRITE_TIMEOUT      180000
 402
 403 struct iavf_aqc_request_resource {
 404         __le16  resource_id;
 405         __le16  access_type;
 406         __le32  timeout;
 407         __le32  resource_number;
 408         u8      reserved[4];
 409 };
 410
 411 IAVF_CHECK_CMD_LENGTH(iavf_aqc_request_resource);
 412
 413 /* Get function capabilities (indirect 0x000A)
 414  * Get device capabilities (indirect 0x000B)
 415  */
 416 struct iavf_aqc_list_capabilites {
 417         u8 command_flags;
 418 #define IAVF_AQ_LIST_CAP_PF_INDEX_EN    1
 419         u8 pf_index;
 420         u8 reserved[2];
 421         __le32 count;
 422         __le32 addr_high;
 423         __le32 addr_low;
 424 };
 425
 426 IAVF_CHECK_CMD_LENGTH(iavf_aqc_list_capabilites);
 427
 428 struct iavf_aqc_list_capabilities_element_resp {
 429         __le16  id;
 430         u8      major_rev;
 431         u8      minor_rev;
 432         __le32  number;
 433         __le32  logical_id;
 434         __le32  phys_id;
 435         u8      reserved[16];
 436 };
 437
 438 /* list of caps */
 439
 440 #define IAVF_AQ_CAP_ID_SWITCH_MODE      0x0001
 441 #define IAVF_AQ_CAP_ID_MNG_MODE         0x0002
 442 #define IAVF_AQ_CAP_ID_NPAR_ACTIVE      0x0003
 443 #define IAVF_AQ_CAP_ID_OS2BMC_CAP       0x0004
 444 #define IAVF_AQ_CAP_ID_FUNCTIONS_VALID  0x0005
 445 #define IAVF_AQ_CAP_ID_ALTERNATE_RAM    0x0006
 446 #define IAVF_AQ_CAP_ID_WOL_AND_PROXY    0x0008
 447 #define IAVF_AQ_CAP_ID_SRIOV            0x0012
 448 #define IAVF_AQ_CAP_ID_VF               0x0013
 449 #define IAVF_AQ_CAP_ID_VMDQ             0x0014
 450 #define IAVF_AQ_CAP_ID_8021QBG          0x0015
 451 #define IAVF_AQ_CAP_ID_8021QBR          0x0016
 452 #define IAVF_AQ_CAP_ID_VSI              0x0017
 453 #define IAVF_AQ_CAP_ID_DCB              0x0018
 454 #define IAVF_AQ_CAP_ID_FCOE             0x0021
 455 #define IAVF_AQ_CAP_ID_ISCSI            0x0022
 456 #define IAVF_AQ_CAP_ID_RSS              0x0040
 457 #define IAVF_AQ_CAP_ID_RXQ              0x0041
 458 #define IAVF_AQ_CAP_ID_TXQ              0x0042
 459 #define IAVF_AQ_CAP_ID_MSIX             0x0043
 460 #define IAVF_AQ_CAP_ID_VF_MSIX          0x0044
 461 #define IAVF_AQ_CAP_ID_FLOW_DIRECTOR    0x0045
 462 #define IAVF_AQ_CAP_ID_1588             0x0046
 463 #define IAVF_AQ_CAP_ID_IWARP            0x0051
 464 #define IAVF_AQ_CAP_ID_LED              0x0061
 465 #define IAVF_AQ_CAP_ID_SDP              0x0062
 466 #define IAVF_AQ_CAP_ID_MDIO             0x0063
 467 #define IAVF_AQ_CAP_ID_WSR_PROT         0x0064
 468 #define IAVF_AQ_CAP_ID_NVM_MGMT         0x0080
 469 #define IAVF_AQ_CAP_ID_FLEX10           0x00F1
 470 #define IAVF_AQ_CAP_ID_CEM              0x00F2
 471
 472 /* Set CPPM Configuration (direct 0x0103) */
 473 struct iavf_aqc_cppm_configuration {
 474         __le16  command_flags;
 475 #define IAVF_AQ_CPPM_EN_LTRC    0x0800
 476 #define IAVF_AQ_CPPM_EN_DMCTH   0x1000
 477 #define IAVF_AQ_CPPM_EN_DMCTLX  0x2000
 478 #define IAVF_AQ_CPPM_EN_HPTC    0x4000
 479 #define IAVF_AQ_CPPM_EN_DMARC   0x8000
 480         __le16  ttlx;
 481         __le32  dmacr;
 482         __le16  dmcth;
 483         u8      hptc;
 484         u8      reserved;
 485         __le32  pfltrc;
 486 };
 487
 488 IAVF_CHECK_CMD_LENGTH(iavf_aqc_cppm_configuration);
 489
 490 /* Set ARP Proxy command / response (indirect 0x0104) */
 491 struct iavf_aqc_arp_proxy_data {
 492         __le16  command_flags;
 493 #define IAVF_AQ_ARP_INIT_IPV4   0x0800
 494 #define IAVF_AQ_ARP_UNSUP_CTL   0x1000
 495 #define IAVF_AQ_ARP_ENA         0x2000
 496 #define IAVF_AQ_ARP_ADD_IPV4    0x4000
 497 #define IAVF_AQ_ARP_DEL_IPV4    0x8000
 498         __le16  table_id;
 499         __le32  enabled_offloads;
 500 #define IAVF_AQ_ARP_DIRECTED_OFFLOAD_ENABLE     0x00000020
 501 #define IAVF_AQ_ARP_OFFLOAD_ENABLE              0x00000800
 502         __le32  ip_addr;
 503         u8      mac_addr[6];
 504         u8      reserved[2];
 505 };
 506
 507 IAVF_CHECK_STRUCT_LEN(0x14, iavf_aqc_arp_proxy_data);
 508
 509 /* Set NS Proxy Table Entry Command (indirect 0x0105) */
 510 struct iavf_aqc_ns_proxy_data {
 511         __le16  table_idx_mac_addr_0;
 512         __le16  table_idx_mac_addr_1;
 513         __le16  table_idx_ipv6_0;
 514         __le16  table_idx_ipv6_1;
 515         __le16  control;
 516 #define IAVF_AQ_NS_PROXY_ADD_0          0x0001
 517 #define IAVF_AQ_NS_PROXY_DEL_0          0x0002
 518 #define IAVF_AQ_NS_PROXY_ADD_1          0x0004
 519 #define IAVF_AQ_NS_PROXY_DEL_1          0x0008
 520 #define IAVF_AQ_NS_PROXY_ADD_IPV6_0     0x0010
 521 #define IAVF_AQ_NS_PROXY_DEL_IPV6_0     0x0020
 522 #define IAVF_AQ_NS_PROXY_ADD_IPV6_1     0x0040
 523 #define IAVF_AQ_NS_PROXY_DEL_IPV6_1     0x0080
 524 #define IAVF_AQ_NS_PROXY_COMMAND_SEQ    0x0100
 525 #define IAVF_AQ_NS_PROXY_INIT_IPV6_TBL  0x0200
 526 #define IAVF_AQ_NS_PROXY_INIT_MAC_TBL   0x0400
 527 #define IAVF_AQ_NS_PROXY_OFFLOAD_ENABLE 0x0800
 528 #define IAVF_AQ_NS_PROXY_DIRECTED_OFFLOAD_ENABLE        0x1000
 529         u8      mac_addr_0[6];
 530         u8      mac_addr_1[6];
 531         u8      local_mac_addr[6];
 532         u8      ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */
 533         u8      ipv6_addr_1[16];
 534 };
 535
 536 IAVF_CHECK_STRUCT_LEN(0x3c, iavf_aqc_ns_proxy_data);
 537
 538 /* Manage LAA Command (0x0106) - obsolete */
 539 struct iavf_aqc_mng_laa {
 540         __le16  command_flags;
 541 #define IAVF_AQ_LAA_FLAG_WR     0x8000
 542         u8      reserved[2];
 543         __le32  sal;
 544         __le16  sah;
 545         u8      reserved2[6];
 546 };
 547
 548 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mng_laa);
 549
 550 /* Manage MAC Address Read Command (indirect 0x0107) */
 551 struct iavf_aqc_mac_address_read {
 552         __le16  command_flags;
 553 #define IAVF_AQC_LAN_ADDR_VALID         0x10
 554 #define IAVF_AQC_SAN_ADDR_VALID         0x20
 555 #define IAVF_AQC_PORT_ADDR_VALID        0x40
 556 #define IAVF_AQC_WOL_ADDR_VALID         0x80
 557 #define IAVF_AQC_MC_MAG_EN_VALID        0x100
 558 #define IAVF_AQC_WOL_PRESERVE_STATUS    0x200
 559 #define IAVF_AQC_ADDR_VALID_MASK        0x3F0
 560         u8      reserved[6];
 561         __le32  addr_high;
 562         __le32  addr_low;
 563 };
 564
 565 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_read);
 566
 567 struct iavf_aqc_mac_address_read_data {
 568         u8 pf_lan_mac[6];
 569         u8 pf_san_mac[6];
 570         u8 port_mac[6];
 571         u8 pf_wol_mac[6];
 572 };
 573
 574 IAVF_CHECK_STRUCT_LEN(24, iavf_aqc_mac_address_read_data);
 575
 576 /* Manage MAC Address Write Command (0x0108) */
 577 struct iavf_aqc_mac_address_write {
 578         __le16  command_flags;
 579 #define IAVF_AQC_MC_MAG_EN              0x0100
 580 #define IAVF_AQC_WOL_PRESERVE_ON_PFR    0x0200
 581 #define IAVF_AQC_WRITE_TYPE_LAA_ONLY    0x0000
 582 #define IAVF_AQC_WRITE_TYPE_LAA_WOL     0x4000
 583 #define IAVF_AQC_WRITE_TYPE_PORT        0x8000
 584 #define IAVF_AQC_WRITE_TYPE_UPDATE_MC_MAG       0xC000
 585 #define IAVF_AQC_WRITE_TYPE_MASK        0xC000
 586
 587         __le16  mac_sah;
 588         __le32  mac_sal;
 589         u8      reserved[8];
 590 };
 591
 592 IAVF_CHECK_CMD_LENGTH(iavf_aqc_mac_address_write);
 593
 594 /* PXE commands (0x011x) */
 595
 596 /* Clear PXE Command and response  (direct 0x0110) */
 597 struct iavf_aqc_clear_pxe {
 598         u8      rx_cnt;
 599         u8      reserved[15];
 600 };
 601
 602 IAVF_CHECK_CMD_LENGTH(iavf_aqc_clear_pxe);
 603
 604 /* Set WoL Filter (0x0120) */
 605
 606 struct iavf_aqc_set_wol_filter {
 607         __le16 filter_index;
 608 #define IAVF_AQC_MAX_NUM_WOL_FILTERS    8
 609 #define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT        15
 610 #define IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_MASK (0x1 << \
 611                 IAVF_AQC_SET_WOL_FILTER_TYPE_MAGIC_SHIFT)
 612
 613 #define IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT             0
 614 #define IAVF_AQC_SET_WOL_FILTER_INDEX_MASK      (0x7 << \
 615                 IAVF_AQC_SET_WOL_FILTER_INDEX_SHIFT)
 616         __le16 cmd_flags;
 617 #define IAVF_AQC_SET_WOL_FILTER                         0x8000
 618 #define IAVF_AQC_SET_WOL_FILTER_NO_TCO_WOL              0x4000
 619 #define IAVF_AQC_SET_WOL_FILTER_WOL_PRESERVE_ON_PFR     0x2000
 620 #define IAVF_AQC_SET_WOL_FILTER_ACTION_CLEAR            0
 621 #define IAVF_AQC_SET_WOL_FILTER_ACTION_SET              1
 622         __le16 valid_flags;
 623 #define IAVF_AQC_SET_WOL_FILTER_ACTION_VALID            0x8000
 624 #define IAVF_AQC_SET_WOL_FILTER_NO_TCO_ACTION_VALID     0x4000
 625         u8 reserved[2];
 626         __le32  address_high;
 627         __le32  address_low;
 628 };
 629
 630 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_wol_filter);
 631
 632 struct iavf_aqc_set_wol_filter_data {
 633         u8 filter[128];
 634         u8 mask[16];
 635 };
 636
 637 IAVF_CHECK_STRUCT_LEN(0x90, iavf_aqc_set_wol_filter_data);
 638
 639 /* Get Wake Reason (0x0121) */
 640
 641 struct iavf_aqc_get_wake_reason_completion {
 642         u8 reserved_1[2];
 643         __le16 wake_reason;
 644 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT      0
 645 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_MASK (0xFF << \
 646                 IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_MATCHED_INDEX_SHIFT)
 647 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT   8
 648 #define IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_MASK    (0xFF << \
 649                 IAVF_AQC_GET_WAKE_UP_REASON_WOL_REASON_RESERVED_SHIFT)
 650         u8 reserved_2[12];
 651 };
 652
 653 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_wake_reason_completion);
 654
 655 /* Switch configuration commands (0x02xx) */
 656
 657 /* Used by many indirect commands that only pass an seid and a buffer in the
 658  * command
 659  */
 660 struct iavf_aqc_switch_seid {
 661         __le16  seid;
 662         u8      reserved[6];
 663         __le32  addr_high;
 664         __le32  addr_low;
 665 };
 666
 667 IAVF_CHECK_CMD_LENGTH(iavf_aqc_switch_seid);
 668
 669 /* Get Switch Configuration command (indirect 0x0200)
 670  * uses iavf_aqc_switch_seid for the descriptor
 671  */
 672 struct iavf_aqc_get_switch_config_header_resp {
 673         __le16  num_reported;
 674         __le16  num_total;
 675         u8      reserved[12];
 676 };
 677
 678 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_config_header_resp);
 679
 680 struct iavf_aqc_switch_config_element_resp {
 681         u8      element_type;
 682 #define IAVF_AQ_SW_ELEM_TYPE_MAC        1
 683 #define IAVF_AQ_SW_ELEM_TYPE_PF         2
 684 #define IAVF_AQ_SW_ELEM_TYPE_VF         3
 685 #define IAVF_AQ_SW_ELEM_TYPE_EMP        4
 686 #define IAVF_AQ_SW_ELEM_TYPE_BMC        5
 687 #define IAVF_AQ_SW_ELEM_TYPE_PV         16
 688 #define IAVF_AQ_SW_ELEM_TYPE_VEB        17
 689 #define IAVF_AQ_SW_ELEM_TYPE_PA         18
 690 #define IAVF_AQ_SW_ELEM_TYPE_VSI        19
 691         u8      revision;
 692 #define IAVF_AQ_SW_ELEM_REV_1           1
 693         __le16  seid;
 694         __le16  uplink_seid;
 695         __le16  downlink_seid;
 696         u8      reserved[3];
 697         u8      connection_type;
 698 #define IAVF_AQ_CONN_TYPE_REGULAR       0x1
 699 #define IAVF_AQ_CONN_TYPE_DEFAULT       0x2
 700 #define IAVF_AQ_CONN_TYPE_CASCADED      0x3
 701         __le16  scheduler_id;
 702         __le16  element_info;
 703 };
 704
 705 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_config_element_resp);
 706
 707 /* Get Switch Configuration (indirect 0x0200)
 708  *    an array of elements are returned in the response buffer
 709  *    the first in the array is the header, remainder are elements
 710  */
 711 struct iavf_aqc_get_switch_config_resp {
 712         struct iavf_aqc_get_switch_config_header_resp   header;
 713         struct iavf_aqc_switch_config_element_resp      element[1];
 714 };
 715
 716 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_switch_config_resp);
 717
 718 /* Add Statistics (direct 0x0201)
 719  * Remove Statistics (direct 0x0202)
 720  */
 721 struct iavf_aqc_add_remove_statistics {
 722         __le16  seid;
 723         __le16  vlan;
 724         __le16  stat_index;
 725         u8      reserved[10];
 726 };
 727
 728 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_statistics);
 729
 730 /* Set Port Parameters command (direct 0x0203) */
 731 struct iavf_aqc_set_port_parameters {
 732         __le16  command_flags;
 733 #define IAVF_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS   1
 734 #define IAVF_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS  2 /* must set! */
 735 #define IAVF_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA    4
 736         __le16  bad_frame_vsi;
 737 #define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_SHIFT  0x0
 738 #define IAVF_AQ_SET_P_PARAMS_BFRAME_SEID_MASK   0x3FF
 739         __le16  default_seid;        /* reserved for command */
 740         u8      reserved[10];
 741 };
 742
 743 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_port_parameters);
 744
 745 /* Get Switch Resource Allocation (indirect 0x0204) */
 746 struct iavf_aqc_get_switch_resource_alloc {
 747         u8      num_entries;         /* reserved for command */
 748         u8      reserved[7];
 749         __le32  addr_high;
 750         __le32  addr_low;
 751 };
 752
 753 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_switch_resource_alloc);
 754
 755 /* expect an array of these structs in the response buffer */
 756 struct iavf_aqc_switch_resource_alloc_element_resp {
 757         u8      resource_type;
 758 #define IAVF_AQ_RESOURCE_TYPE_VEB               0x0
 759 #define IAVF_AQ_RESOURCE_TYPE_VSI               0x1
 760 #define IAVF_AQ_RESOURCE_TYPE_MACADDR           0x2
 761 #define IAVF_AQ_RESOURCE_TYPE_STAG              0x3
 762 #define IAVF_AQ_RESOURCE_TYPE_ETAG              0x4
 763 #define IAVF_AQ_RESOURCE_TYPE_MULTICAST_HASH    0x5
 764 #define IAVF_AQ_RESOURCE_TYPE_UNICAST_HASH      0x6
 765 #define IAVF_AQ_RESOURCE_TYPE_VLAN              0x7
 766 #define IAVF_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY    0x8
 767 #define IAVF_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY   0x9
 768 #define IAVF_AQ_RESOURCE_TYPE_VLAN_STAT_POOL    0xA
 769 #define IAVF_AQ_RESOURCE_TYPE_MIRROR_RULE       0xB
 770 #define IAVF_AQ_RESOURCE_TYPE_QUEUE_SETS        0xC
 771 #define IAVF_AQ_RESOURCE_TYPE_VLAN_FILTERS      0xD
 772 #define IAVF_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF
 773 #define IAVF_AQ_RESOURCE_TYPE_IP_FILTERS        0x10
 774 #define IAVF_AQ_RESOURCE_TYPE_GRE_VN_KEYS       0x11
 775 #define IAVF_AQ_RESOURCE_TYPE_VN2_KEYS          0x12
 776 #define IAVF_AQ_RESOURCE_TYPE_TUNNEL_PORTS      0x13
 777         u8      reserved1;
 778         __le16  guaranteed;
 779         __le16  total;
 780         __le16  used;
 781         __le16  total_unalloced;
 782         u8      reserved2[6];
 783 };
 784
 785 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_switch_resource_alloc_element_resp);
 786
 787 /* Set Switch Configuration (direct 0x0205) */
 788 struct iavf_aqc_set_switch_config {
 789         __le16  flags;
 790 /* flags used for both fields below */
 791 #define IAVF_AQ_SET_SWITCH_CFG_PROMISC          0x0001
 792 #define IAVF_AQ_SET_SWITCH_CFG_L2_FILTER        0x0002
 793 #define IAVF_AQ_SET_SWITCH_CFG_HW_ATR_EVICT     0x0004
 794         __le16  valid_flags;
 795         /* The ethertype in switch_tag is dropped on ingress and used
 796          * internally by the switch. Set this to zero for the default
 797          * of 0x88a8 (802.1ad). Should be zero for firmware API
 798          * versions lower than 1.7.
 799          */
 800         __le16  switch_tag;
 801         /* The ethertypes in first_tag and second_tag are used to
 802          * match the outer and inner VLAN tags (respectively) when HW
 803          * double VLAN tagging is enabled via the set port parameters
 804          * AQ command. Otherwise these are both ignored. Set them to
 805          * zero for their defaults of 0x8100 (802.1Q). Should be zero
 806          * for firmware API versions lower than 1.7.
 807          */
 808         __le16  first_tag;
 809         __le16  second_tag;
 810         u8      reserved[6];
 811 };
 812
 813 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_switch_config);
 814
 815 /* Read Receive control registers  (direct 0x0206)
 816  * Write Receive control registers (direct 0x0207)
 817  *     used for accessing Rx control registers that can be
 818  *     slow and need special handling when under high Rx load
 819  */
 820 struct iavf_aqc_rx_ctl_reg_read_write {
 821         __le32 reserved1;
 822         __le32 address;
 823         __le32 reserved2;
 824         __le32 value;
 825 };
 826
 827 IAVF_CHECK_CMD_LENGTH(iavf_aqc_rx_ctl_reg_read_write);
 828
 829 /* Add VSI (indirect 0x0210)
 830  *    this indirect command uses struct iavf_aqc_vsi_properties_data
 831  *    as the indirect buffer (128 bytes)
 832  *
 833  * Update VSI (indirect 0x211)
 834  *     uses the same data structure as Add VSI
 835  *
 836  * Get VSI (indirect 0x0212)
 837  *     uses the same completion and data structure as Add VSI
 838  */
 839 struct iavf_aqc_add_get_update_vsi {
 840         __le16  uplink_seid;
 841         u8      connection_type;
 842 #define IAVF_AQ_VSI_CONN_TYPE_NORMAL    0x1
 843 #define IAVF_AQ_VSI_CONN_TYPE_DEFAULT   0x2
 844 #define IAVF_AQ_VSI_CONN_TYPE_CASCADED  0x3
 845         u8      reserved1;
 846         u8      vf_id;
 847         u8      reserved2;
 848         __le16  vsi_flags;
 849 #define IAVF_AQ_VSI_TYPE_SHIFT          0x0
 850 #define IAVF_AQ_VSI_TYPE_MASK           (0x3 << IAVF_AQ_VSI_TYPE_SHIFT)
 851 #define IAVF_AQ_VSI_TYPE_VF             0x0
 852 #define IAVF_AQ_VSI_TYPE_VMDQ2          0x1
 853 #define IAVF_AQ_VSI_TYPE_PF             0x2
 854 #define IAVF_AQ_VSI_TYPE_EMP_MNG        0x3
 855 #define IAVF_AQ_VSI_FLAG_CASCADED_PV    0x4
 856         __le32  addr_high;
 857         __le32  addr_low;
 858 };
 859
 860 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi);
 861
 862 struct iavf_aqc_add_get_update_vsi_completion {
 863         __le16 seid;
 864         __le16 vsi_number;
 865         __le16 vsi_used;
 866         __le16 vsi_free;
 867         __le32 addr_high;
 868         __le32 addr_low;
 869 };
 870
 871 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_get_update_vsi_completion);
 872
 873 struct iavf_aqc_vsi_properties_data {
 874         /* first 96 byte are written by SW */
 875         __le16  valid_sections;
 876 #define IAVF_AQ_VSI_PROP_SWITCH_VALID           0x0001
 877 #define IAVF_AQ_VSI_PROP_SECURITY_VALID         0x0002
 878 #define IAVF_AQ_VSI_PROP_VLAN_VALID             0x0004
 879 #define IAVF_AQ_VSI_PROP_CAS_PV_VALID           0x0008
 880 #define IAVF_AQ_VSI_PROP_INGRESS_UP_VALID       0x0010
 881 #define IAVF_AQ_VSI_PROP_EGRESS_UP_VALID        0x0020
 882 #define IAVF_AQ_VSI_PROP_QUEUE_MAP_VALID        0x0040
 883 #define IAVF_AQ_VSI_PROP_QUEUE_OPT_VALID        0x0080
 884 #define IAVF_AQ_VSI_PROP_OUTER_UP_VALID         0x0100
 885 #define IAVF_AQ_VSI_PROP_SCHED_VALID            0x0200
 886         /* switch section */
 887         __le16  switch_id; /* 12bit id combined with flags below */
 888 #define IAVF_AQ_VSI_SW_ID_SHIFT         0x0000
 889 #define IAVF_AQ_VSI_SW_ID_MASK          (0xFFF << IAVF_AQ_VSI_SW_ID_SHIFT)
 890 #define IAVF_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000
 891 #define IAVF_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000
 892 #define IAVF_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000
 893         u8      sw_reserved[2];
 894         /* security section */
 895         u8      sec_flags;
 896 #define IAVF_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD    0x01
 897 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK    0x02
 898 #define IAVF_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK     0x04
 899         u8      sec_reserved;
 900         /* VLAN section */
 901         __le16  pvid; /* VLANS include priority bits */
 902         __le16  fcoe_pvid;
 903         u8      port_vlan_flags;
 904 #define IAVF_AQ_VSI_PVLAN_MODE_SHIFT    0x00
 905 #define IAVF_AQ_VSI_PVLAN_MODE_MASK     (0x03 << \
 906                                          IAVF_AQ_VSI_PVLAN_MODE_SHIFT)
 907 #define IAVF_AQ_VSI_PVLAN_MODE_TAGGED   0x01
 908 #define IAVF_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02
 909 #define IAVF_AQ_VSI_PVLAN_MODE_ALL      0x03
 910 #define IAVF_AQ_VSI_PVLAN_INSERT_PVID   0x04
 911 #define IAVF_AQ_VSI_PVLAN_EMOD_SHIFT    0x03
 912 #define IAVF_AQ_VSI_PVLAN_EMOD_MASK     (0x3 << \
 913                                          IAVF_AQ_VSI_PVLAN_EMOD_SHIFT)
 914 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0
 915 #define IAVF_AQ_VSI_PVLAN_EMOD_STR_UP   0x08
 916 #define IAVF_AQ_VSI_PVLAN_EMOD_STR      0x10
 917 #define IAVF_AQ_VSI_PVLAN_EMOD_NOTHING  0x18
 918         u8      pvlan_reserved[3];
 919         /* ingress egress up sections */
 920         __le32  ingress_table; /* bitmap, 3 bits per up */
 921 #define IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT  0
 922 #define IAVF_AQ_VSI_UP_TABLE_UP0_MASK   (0x7 << \
 923                                          IAVF_AQ_VSI_UP_TABLE_UP0_SHIFT)
 924 #define IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT  3
 925 #define IAVF_AQ_VSI_UP_TABLE_UP1_MASK   (0x7 << \
 926                                          IAVF_AQ_VSI_UP_TABLE_UP1_SHIFT)
 927 #define IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT  6
 928 #define IAVF_AQ_VSI_UP_TABLE_UP2_MASK   (0x7 << \
 929                                          IAVF_AQ_VSI_UP_TABLE_UP2_SHIFT)
 930 #define IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT  9
 931 #define IAVF_AQ_VSI_UP_TABLE_UP3_MASK   (0x7 << \
 932                                          IAVF_AQ_VSI_UP_TABLE_UP3_SHIFT)
 933 #define IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT  12
 934 #define IAVF_AQ_VSI_UP_TABLE_UP4_MASK   (0x7 << \
 935                                          IAVF_AQ_VSI_UP_TABLE_UP4_SHIFT)
 936 #define IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT  15
 937 #define IAVF_AQ_VSI_UP_TABLE_UP5_MASK   (0x7 << \
 938                                          IAVF_AQ_VSI_UP_TABLE_UP5_SHIFT)
 939 #define IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT  18
 940 #define IAVF_AQ_VSI_UP_TABLE_UP6_MASK   (0x7 << \
 941                                          IAVF_AQ_VSI_UP_TABLE_UP6_SHIFT)
 942 #define IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT  21
 943 #define IAVF_AQ_VSI_UP_TABLE_UP7_MASK   (0x7 << \
 944                                          IAVF_AQ_VSI_UP_TABLE_UP7_SHIFT)
 945         __le32  egress_table;   /* same defines as for ingress table */
 946         /* cascaded PV section */
 947         __le16  cas_pv_tag;
 948         u8      cas_pv_flags;
 949 #define IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT           0x00
 950 #define IAVF_AQ_VSI_CAS_PV_TAGX_MASK            (0x03 << \
 951                                                  IAVF_AQ_VSI_CAS_PV_TAGX_SHIFT)
 952 #define IAVF_AQ_VSI_CAS_PV_TAGX_LEAVE           0x00
 953 #define IAVF_AQ_VSI_CAS_PV_TAGX_REMOVE          0x01
 954 #define IAVF_AQ_VSI_CAS_PV_TAGX_COPY            0x02
 955 #define IAVF_AQ_VSI_CAS_PV_INSERT_TAG           0x10
 956 #define IAVF_AQ_VSI_CAS_PV_ETAG_PRUNE           0x20
 957 #define IAVF_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG      0x40
 958         u8      cas_pv_reserved;
 959         /* queue mapping section */
 960         __le16  mapping_flags;
 961 #define IAVF_AQ_VSI_QUE_MAP_CONTIG      0x0
 962 #define IAVF_AQ_VSI_QUE_MAP_NONCONTIG   0x1
 963         __le16  queue_mapping[16];
 964 #define IAVF_AQ_VSI_QUEUE_SHIFT         0x0
 965 #define IAVF_AQ_VSI_QUEUE_MASK          (0x7FF << IAVF_AQ_VSI_QUEUE_SHIFT)
 966         __le16  tc_mapping[8];
 967 #define IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT 0
 968 #define IAVF_AQ_VSI_TC_QUE_OFFSET_MASK  (0x1FF << \
 969                                          IAVF_AQ_VSI_TC_QUE_OFFSET_SHIFT)
 970 #define IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT 9
 971 #define IAVF_AQ_VSI_TC_QUE_NUMBER_MASK  (0x7 << \
 972                                          IAVF_AQ_VSI_TC_QUE_NUMBER_SHIFT)
 973         /* queueing option section */
 974         u8      queueing_opt_flags;
 975 #define IAVF_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA   0x04
 976 #define IAVF_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA     0x08
 977 #define IAVF_AQ_VSI_QUE_OPT_TCP_ENA     0x10
 978 #define IAVF_AQ_VSI_QUE_OPT_FCOE_ENA    0x20
 979 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_PF  0x00
 980 #define IAVF_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40
 981         u8      queueing_opt_reserved[3];
 982         /* scheduler section */
 983         u8      up_enable_bits;
 984         u8      sched_reserved;
 985         /* outer up section */
 986         __le32  outer_up_table; /* same structure and defines as ingress tbl */
 987         u8      cmd_reserved[8];
 988         /* last 32 bytes are written by FW */
 989         __le16  qs_handle[8];
 990 #define IAVF_AQ_VSI_QS_HANDLE_INVALID   0xFFFF
 991         __le16  stat_counter_idx;
 992         __le16  sched_id;
 993         u8      resp_reserved[12];
 994 };
 995
 996 IAVF_CHECK_STRUCT_LEN(128, iavf_aqc_vsi_properties_data);
 997
 998 /* Add Port Virtualizer (direct 0x0220)
 999  * also used for update PV (direct 0x0221) but only flags are used
1000  * (IS_CTRL_PORT only works on add PV)
1001  */
1002 struct iavf_aqc_add_update_pv {
1003         __le16  command_flags;
1004 #define IAVF_AQC_PV_FLAG_PV_TYPE                0x1
1005 #define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN    0x2
1006 #define IAVF_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN    0x4
1007 #define IAVF_AQC_PV_FLAG_IS_CTRL_PORT           0x8
1008         __le16  uplink_seid;
1009         __le16  connected_seid;
1010         u8      reserved[10];
1011 };
1012
1013 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv);
1014
1015 struct iavf_aqc_add_update_pv_completion {
1016         /* reserved for update; for add also encodes error if rc == ENOSPC */
1017         __le16  pv_seid;
1018 #define IAVF_AQC_PV_ERR_FLAG_NO_PV      0x1
1019 #define IAVF_AQC_PV_ERR_FLAG_NO_SCHED   0x2
1020 #define IAVF_AQC_PV_ERR_FLAG_NO_COUNTER 0x4
1021 #define IAVF_AQC_PV_ERR_FLAG_NO_ENTRY   0x8
1022         u8      reserved[14];
1023 };
1024
1025 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_update_pv_completion);
1026
1027 /* Get PV Params (direct 0x0222)
1028  * uses iavf_aqc_switch_seid for the descriptor
1029  */
1030
1031 struct iavf_aqc_get_pv_params_completion {
1032         __le16  seid;
1033         __le16  default_stag;
1034         __le16  pv_flags; /* same flags as add_pv */
1035 #define IAVF_AQC_GET_PV_PV_TYPE                 0x1
1036 #define IAVF_AQC_GET_PV_FRWD_UNKNOWN_STAG       0x2
1037 #define IAVF_AQC_GET_PV_FRWD_UNKNOWN_ETAG       0x4
1038         u8      reserved[8];
1039         __le16  default_port_seid;
1040 };
1041
1042 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_pv_params_completion);
1043
1044 /* Add VEB (direct 0x0230) */
1045 struct iavf_aqc_add_veb {
1046         __le16  uplink_seid;
1047         __le16  downlink_seid;
1048         __le16  veb_flags;
1049 #define IAVF_AQC_ADD_VEB_FLOATING               0x1
1050 #define IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT        1
1051 #define IAVF_AQC_ADD_VEB_PORT_TYPE_MASK         (0x3 << \
1052                                         IAVF_AQC_ADD_VEB_PORT_TYPE_SHIFT)
1053 #define IAVF_AQC_ADD_VEB_PORT_TYPE_DEFAULT      0x2
1054 #define IAVF_AQC_ADD_VEB_PORT_TYPE_DATA         0x4
1055 #define IAVF_AQC_ADD_VEB_ENABLE_L2_FILTER       0x8     /* deprecated */
1056 #define IAVF_AQC_ADD_VEB_ENABLE_DISABLE_STATS   0x10
1057         u8      enable_tcs;
1058         u8      reserved[9];
1059 };
1060
1061 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb);
1062
1063 struct iavf_aqc_add_veb_completion {
1064         u8      reserved[6];
1065         __le16  switch_seid;
1066         /* also encodes error if rc == ENOSPC; codes are the same as add_pv */
1067         __le16  veb_seid;
1068 #define IAVF_AQC_VEB_ERR_FLAG_NO_VEB            0x1
1069 #define IAVF_AQC_VEB_ERR_FLAG_NO_SCHED          0x2
1070 #define IAVF_AQC_VEB_ERR_FLAG_NO_COUNTER        0x4
1071 #define IAVF_AQC_VEB_ERR_FLAG_NO_ENTRY          0x8
1072         __le16  statistic_index;
1073         __le16  vebs_used;
1074         __le16  vebs_free;
1075 };
1076
1077 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_veb_completion);
1078
1079 /* Get VEB Parameters (direct 0x0232)
1080  * uses iavf_aqc_switch_seid for the descriptor
1081  */
1082 struct iavf_aqc_get_veb_parameters_completion {
1083         __le16  seid;
1084         __le16  switch_id;
1085         __le16  veb_flags; /* only the first/last flags from 0x0230 is valid */
1086         __le16  statistic_index;
1087         __le16  vebs_used;
1088         __le16  vebs_free;
1089         u8      reserved[4];
1090 };
1091
1092 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_veb_parameters_completion);
1093
1094 /* Delete Element (direct 0x0243)
1095  * uses the generic iavf_aqc_switch_seid
1096  */
1097
1098 /* Add MAC-VLAN (indirect 0x0250) */
1099
1100 /* used for the command for most vlan commands */
1101 struct iavf_aqc_macvlan {
1102         __le16  num_addresses;
1103         __le16  seid[3];
1104 #define IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT     0
1105 #define IAVF_AQC_MACVLAN_CMD_SEID_NUM_MASK      (0x3FF << \
1106                                         IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1107 #define IAVF_AQC_MACVLAN_CMD_SEID_VALID         0x8000
1108         __le32  addr_high;
1109         __le32  addr_low;
1110 };
1111
1112 IAVF_CHECK_CMD_LENGTH(iavf_aqc_macvlan);
1113
1114 /* indirect data for command and response */
1115 struct iavf_aqc_add_macvlan_element_data {
1116         u8      mac_addr[6];
1117         __le16  vlan_tag;
1118         __le16  flags;
1119 #define IAVF_AQC_MACVLAN_ADD_PERFECT_MATCH      0x0001
1120 #define IAVF_AQC_MACVLAN_ADD_HASH_MATCH         0x0002
1121 #define IAVF_AQC_MACVLAN_ADD_IGNORE_VLAN        0x0004
1122 #define IAVF_AQC_MACVLAN_ADD_TO_QUEUE           0x0008
1123 #define IAVF_AQC_MACVLAN_ADD_USE_SHARED_MAC     0x0010
1124         __le16  queue_number;
1125 #define IAVF_AQC_MACVLAN_CMD_QUEUE_SHIFT        0
1126 #define IAVF_AQC_MACVLAN_CMD_QUEUE_MASK         (0x7FF << \
1127                                         IAVF_AQC_MACVLAN_CMD_SEID_NUM_SHIFT)
1128         /* response section */
1129         u8      match_method;
1130 #define IAVF_AQC_MM_PERFECT_MATCH       0x01
1131 #define IAVF_AQC_MM_HASH_MATCH          0x02
1132 #define IAVF_AQC_MM_ERR_NO_RES          0xFF
1133         u8      reserved1[3];
1134 };
1135
1136 struct iavf_aqc_add_remove_macvlan_completion {
1137         __le16 perfect_mac_used;
1138         __le16 perfect_mac_free;
1139         __le16 unicast_hash_free;
1140         __le16 multicast_hash_free;
1141         __le32 addr_high;
1142         __le32 addr_low;
1143 };
1144
1145 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_macvlan_completion);
1146
1147 /* Remove MAC-VLAN (indirect 0x0251)
1148  * uses iavf_aqc_macvlan for the descriptor
1149  * data points to an array of num_addresses of elements
1150  */
1151
1152 struct iavf_aqc_remove_macvlan_element_data {
1153         u8      mac_addr[6];
1154         __le16  vlan_tag;
1155         u8      flags;
1156 #define IAVF_AQC_MACVLAN_DEL_PERFECT_MATCH      0x01
1157 #define IAVF_AQC_MACVLAN_DEL_HASH_MATCH         0x02
1158 #define IAVF_AQC_MACVLAN_DEL_IGNORE_VLAN        0x08
1159 #define IAVF_AQC_MACVLAN_DEL_ALL_VSIS           0x10
1160         u8      reserved[3];
1161         /* reply section */
1162         u8      error_code;
1163 #define IAVF_AQC_REMOVE_MACVLAN_SUCCESS         0x0
1164 #define IAVF_AQC_REMOVE_MACVLAN_FAIL            0xFF
1165         u8      reply_reserved[3];
1166 };
1167
1168 /* Add VLAN (indirect 0x0252)
1169  * Remove VLAN (indirect 0x0253)
1170  * use the generic iavf_aqc_macvlan for the command
1171  */
1172 struct iavf_aqc_add_remove_vlan_element_data {
1173         __le16  vlan_tag;
1174         u8      vlan_flags;
1175 /* flags for add VLAN */
1176 #define IAVF_AQC_ADD_VLAN_LOCAL                 0x1
1177 #define IAVF_AQC_ADD_PVLAN_TYPE_SHIFT           1
1178 #define IAVF_AQC_ADD_PVLAN_TYPE_MASK    (0x3 << IAVF_AQC_ADD_PVLAN_TYPE_SHIFT)
1179 #define IAVF_AQC_ADD_PVLAN_TYPE_REGULAR         0x0
1180 #define IAVF_AQC_ADD_PVLAN_TYPE_PRIMARY         0x2
1181 #define IAVF_AQC_ADD_PVLAN_TYPE_SECONDARY       0x4
1182 #define IAVF_AQC_VLAN_PTYPE_SHIFT               3
1183 #define IAVF_AQC_VLAN_PTYPE_MASK        (0x3 << IAVF_AQC_VLAN_PTYPE_SHIFT)
1184 #define IAVF_AQC_VLAN_PTYPE_REGULAR_VSI         0x0
1185 #define IAVF_AQC_VLAN_PTYPE_PROMISC_VSI         0x8
1186 #define IAVF_AQC_VLAN_PTYPE_COMMUNITY_VSI       0x10
1187 #define IAVF_AQC_VLAN_PTYPE_ISOLATED_VSI        0x18
1188 /* flags for remove VLAN */
1189 #define IAVF_AQC_REMOVE_VLAN_ALL        0x1
1190         u8      reserved;
1191         u8      result;
1192 /* flags for add VLAN */
1193 #define IAVF_AQC_ADD_VLAN_SUCCESS       0x0
1194 #define IAVF_AQC_ADD_VLAN_FAIL_REQUEST  0xFE
1195 #define IAVF_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF
1196 /* flags for remove VLAN */
1197 #define IAVF_AQC_REMOVE_VLAN_SUCCESS    0x0
1198 #define IAVF_AQC_REMOVE_VLAN_FAIL       0xFF
1199         u8      reserved1[3];
1200 };
1201
1202 struct iavf_aqc_add_remove_vlan_completion {
1203         u8      reserved[4];
1204         __le16  vlans_used;
1205         __le16  vlans_free;
1206         __le32  addr_high;
1207         __le32  addr_low;
1208 };
1209
1210 /* Set VSI Promiscuous Modes (direct 0x0254) */
1211 struct iavf_aqc_set_vsi_promiscuous_modes {
1212         __le16  promiscuous_flags;
1213         __le16  valid_flags;
1214 /* flags used for both fields above */
1215 #define IAVF_AQC_SET_VSI_PROMISC_UNICAST        0x01
1216 #define IAVF_AQC_SET_VSI_PROMISC_MULTICAST      0x02
1217 #define IAVF_AQC_SET_VSI_PROMISC_BROADCAST      0x04
1218 #define IAVF_AQC_SET_VSI_DEFAULT                0x08
1219 #define IAVF_AQC_SET_VSI_PROMISC_VLAN           0x10
1220 #define IAVF_AQC_SET_VSI_PROMISC_TX             0x8000
1221         __le16  seid;
1222 #define IAVF_AQC_VSI_PROM_CMD_SEID_MASK         0x3FF
1223         __le16  vlan_tag;
1224 #define IAVF_AQC_SET_VSI_VLAN_MASK              0x0FFF
1225 #define IAVF_AQC_SET_VSI_VLAN_VALID             0x8000
1226         u8      reserved[8];
1227 };
1228
1229 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_vsi_promiscuous_modes);
1230
1231 /* Add S/E-tag command (direct 0x0255)
1232  * Uses generic iavf_aqc_add_remove_tag_completion for completion
1233  */
1234 struct iavf_aqc_add_tag {
1235         __le16  flags;
1236 #define IAVF_AQC_ADD_TAG_FLAG_TO_QUEUE          0x0001
1237         __le16  seid;
1238 #define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT     0
1239 #define IAVF_AQC_ADD_TAG_CMD_SEID_NUM_MASK      (0x3FF << \
1240                                         IAVF_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT)
1241         __le16  tag;
1242         __le16  queue_number;
1243         u8      reserved[8];
1244 };
1245
1246 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_tag);
1247
1248 struct iavf_aqc_add_remove_tag_completion {
1249         u8      reserved[12];
1250         __le16  tags_used;
1251         __le16  tags_free;
1252 };
1253
1254 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_tag_completion);
1255
1256 /* Remove S/E-tag command (direct 0x0256)
1257  * Uses generic iavf_aqc_add_remove_tag_completion for completion
1258  */
1259 struct iavf_aqc_remove_tag {
1260         __le16  seid;
1261 #define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT  0
1262 #define IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1263                                         IAVF_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT)
1264         __le16  tag;
1265         u8      reserved[12];
1266 };
1267
1268 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_tag);
1269
1270 /* Add multicast E-Tag (direct 0x0257)
1271  * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields
1272  * and no external data
1273  */
1274 struct iavf_aqc_add_remove_mcast_etag {
1275         __le16  pv_seid;
1276         __le16  etag;
1277         u8      num_unicast_etags;
1278         u8      reserved[3];
1279         __le32  addr_high;          /* address of array of 2-byte s-tags */
1280         __le32  addr_low;
1281 };
1282
1283 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag);
1284
1285 struct iavf_aqc_add_remove_mcast_etag_completion {
1286         u8      reserved[4];
1287         __le16  mcast_etags_used;
1288         __le16  mcast_etags_free;
1289         __le32  addr_high;
1290         __le32  addr_low;
1291
1292 };
1293
1294 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_mcast_etag_completion);
1295
1296 /* Update S/E-Tag (direct 0x0259) */
1297 struct iavf_aqc_update_tag {
1298         __le16  seid;
1299 #define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT  0
1300 #define IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK   (0x3FF << \
1301                                         IAVF_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT)
1302         __le16  old_tag;
1303         __le16  new_tag;
1304         u8      reserved[10];
1305 };
1306
1307 IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag);
1308
1309 struct iavf_aqc_update_tag_completion {
1310         u8      reserved[12];
1311         __le16  tags_used;
1312         __le16  tags_free;
1313 };
1314
1315 IAVF_CHECK_CMD_LENGTH(iavf_aqc_update_tag_completion);
1316
1317 /* Add Control Packet filter (direct 0x025A)
1318  * Remove Control Packet filter (direct 0x025B)
1319  * uses the iavf_aqc_add_oveb_cloud,
1320  * and the generic direct completion structure
1321  */
1322 struct iavf_aqc_add_remove_control_packet_filter {
1323         u8      mac[6];
1324         __le16  etype;
1325         __le16  flags;
1326 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC    0x0001
1327 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_DROP          0x0002
1328 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE      0x0004
1329 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_TX            0x0008
1330 #define IAVF_AQC_ADD_CONTROL_PACKET_FLAGS_RX            0x0000
1331         __le16  seid;
1332 #define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT  0
1333 #define IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK   (0x3FF << \
1334                                 IAVF_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT)
1335         __le16  queue;
1336         u8      reserved[2];
1337 };
1338
1339 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter);
1340
1341 struct iavf_aqc_add_remove_control_packet_filter_completion {
1342         __le16  mac_etype_used;
1343         __le16  etype_used;
1344         __le16  mac_etype_free;
1345         __le16  etype_free;
1346         u8      reserved[8];
1347 };
1348
1349 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_control_packet_filter_completion);
1350
1351 /* Add Cloud filters (indirect 0x025C)
1352  * Remove Cloud filters (indirect 0x025D)
1353  * uses the iavf_aqc_add_remove_cloud_filters,
1354  * and the generic indirect completion structure
1355  */
1356 struct iavf_aqc_add_remove_cloud_filters {
1357         u8      num_filters;
1358         u8      reserved;
1359         __le16  seid;
1360 #define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT   0
1361 #define IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK    (0x3FF << \
1362                                         IAVF_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT)
1363         u8      big_buffer_flag;
1364 #define IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER   1
1365         u8      reserved2[3];
1366         __le32  addr_high;
1367         __le32  addr_low;
1368 };
1369
1370 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_remove_cloud_filters);
1371
1372 struct iavf_aqc_add_remove_cloud_filters_element_data {
1373         u8      outer_mac[6];
1374         u8      inner_mac[6];
1375         __le16  inner_vlan;
1376         union {
1377                 struct {
1378                         u8 reserved[12];
1379                         u8 data[4];
1380                 } v4;
1381                 struct {
1382                         u8 data[16];
1383                 } v6;
1384         } ipaddr;
1385         __le16  flags;
1386 #define IAVF_AQC_ADD_CLOUD_FILTER_SHIFT                 0
1387 #define IAVF_AQC_ADD_CLOUD_FILTER_MASK  (0x3F << \
1388                                         IAVF_AQC_ADD_CLOUD_FILTER_SHIFT)
1389 /* 0x0000 reserved */
1390 #define IAVF_AQC_ADD_CLOUD_FILTER_OIP                   0x0001
1391 /* 0x0002 reserved */
1392 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN            0x0003
1393 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID     0x0004
1394 /* 0x0005 reserved */
1395 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID           0x0006
1396 /* 0x0007 reserved */
1397 /* 0x0008 reserved */
1398 #define IAVF_AQC_ADD_CLOUD_FILTER_OMAC                  0x0009
1399 #define IAVF_AQC_ADD_CLOUD_FILTER_IMAC                  0x000A
1400 #define IAVF_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC      0x000B
1401 #define IAVF_AQC_ADD_CLOUD_FILTER_IIP                   0x000C
1402 /* 0x0010 to 0x0017 is for custom filters */
1403
1404 #define IAVF_AQC_ADD_CLOUD_FLAGS_TO_QUEUE               0x0080
1405 #define IAVF_AQC_ADD_CLOUD_VNK_SHIFT                    6
1406 #define IAVF_AQC_ADD_CLOUD_VNK_MASK                     0x00C0
1407 #define IAVF_AQC_ADD_CLOUD_FLAGS_IPV4                   0
1408 #define IAVF_AQC_ADD_CLOUD_FLAGS_IPV6                   0x0100
1409
1410 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_SHIFT               9
1411 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_MASK                0x1E00
1412 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN               0
1413 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC          1
1414 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_GENEVE              2
1415 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_IP                  3
1416 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_RESERVED            4
1417 #define IAVF_AQC_ADD_CLOUD_TNL_TYPE_VXLAN_GPE           5
1418
1419 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_MAC       0x2000
1420 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_INNER_MAC       0x4000
1421 #define IAVF_AQC_ADD_CLOUD_FLAGS_SHARED_OUTER_IP        0x8000
1422
1423         __le32  tenant_id;
1424         u8      reserved[4];
1425         __le16  queue_number;
1426 #define IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT          0
1427 #define IAVF_AQC_ADD_CLOUD_QUEUE_MASK           (0x7FF << \
1428                                                  IAVF_AQC_ADD_CLOUD_QUEUE_SHIFT)
1429         u8      reserved2[14];
1430         /* response section */
1431         u8      allocation_result;
1432 #define IAVF_AQC_ADD_CLOUD_FILTER_SUCCESS       0x0
1433 #define IAVF_AQC_ADD_CLOUD_FILTER_FAIL          0xFF
1434         u8      response_reserved[7];
1435 };
1436
1437 /* iavf_aqc_add_rm_cloud_filt_elem_ext is used when
1438  * IAVF_AQC_ADD_REM_CLOUD_CMD_BIG_BUFFER flag is set.
1439  */
1440 struct iavf_aqc_add_rm_cloud_filt_elem_ext {
1441         struct iavf_aqc_add_remove_cloud_filters_element_data element;
1442         u16     general_fields[32];
1443 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD0    0
1444 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD1    1
1445 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X10_WORD2    2
1446 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD0    3
1447 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD1    4
1448 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X11_WORD2    5
1449 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD0    6
1450 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD1    7
1451 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X12_WORD2    8
1452 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD0    9
1453 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD1    10
1454 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X13_WORD2    11
1455 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD0    12
1456 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD1    13
1457 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X14_WORD2    14
1458 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0    15
1459 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD1    16
1460 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD2    17
1461 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD3    18
1462 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD4    19
1463 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD5    20
1464 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD6    21
1465 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X16_WORD7    22
1466 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD0    23
1467 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD1    24
1468 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD2    25
1469 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD3    26
1470 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD4    27
1471 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD5    28
1472 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD6    29
1473 #define IAVF_AQC_ADD_CLOUD_FV_FLU_0X17_WORD7    30
1474 };
1475
1476 struct iavf_aqc_remove_cloud_filters_completion {
1477         __le16 perfect_ovlan_used;
1478         __le16 perfect_ovlan_free;
1479         __le16 vlan_used;
1480         __le16 vlan_free;
1481         __le32 addr_high;
1482         __le32 addr_low;
1483 };
1484
1485 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_cloud_filters_completion);
1486
1487 /* Replace filter Command 0x025F
1488  * uses the iavf_aqc_replace_cloud_filters,
1489  * and the generic indirect completion structure
1490  */
1491 struct iavf_filter_data {
1492         u8 filter_type;
1493         u8 input[3];
1494 };
1495
1496 struct iavf_aqc_replace_cloud_filters_cmd {
1497         u8      valid_flags;
1498 #define IAVF_AQC_REPLACE_L1_FILTER              0x0
1499 #define IAVF_AQC_REPLACE_CLOUD_FILTER           0x1
1500 #define IAVF_AQC_GET_CLOUD_FILTERS              0x2
1501 #define IAVF_AQC_MIRROR_CLOUD_FILTER            0x4
1502 #define IAVF_AQC_HIGH_PRIORITY_CLOUD_FILTER     0x8
1503         u8      old_filter_type;
1504         u8      new_filter_type;
1505         u8      tr_bit;
1506         u8      reserved[4];
1507         __le32 addr_high;
1508         __le32 addr_low;
1509 };
1510
1511 struct iavf_aqc_replace_cloud_filters_cmd_buf {
1512         u8      data[32];
1513 /* Filter type INPUT codes*/
1514 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_ENTRIES_MAX    3
1515 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_VALIDATED      (1 << 7UL)
1516
1517 /* Field Vector offsets */
1518 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_MAC_DA              0
1519 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_ETH            6
1520 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG                7
1521 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_VLAN                8
1522 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_OVLAN          9
1523 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_STAG_IVLAN          10
1524 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_TUNNLE_KEY          11
1525 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IMAC                12
1526 /* big FLU */
1527 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_IP_DA               14
1528 /* big FLU */
1529 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_OIP_DA              15
1530
1531 #define IAVF_AQC_REPLACE_CLOUD_CMD_INPUT_FV_INNER_VLAN          37
1532         struct iavf_filter_data filters[8];
1533 };
1534
1535 /* Add Mirror Rule (indirect or direct 0x0260)
1536  * Delete Mirror Rule (indirect or direct 0x0261)
1537  * note: some rule types (4,5) do not use an external buffer.
1538  *       take care to set the flags correctly.
1539  */
1540 struct iavf_aqc_add_delete_mirror_rule {
1541         __le16 seid;
1542         __le16 rule_type;
1543 #define IAVF_AQC_MIRROR_RULE_TYPE_SHIFT         0
1544 #define IAVF_AQC_MIRROR_RULE_TYPE_MASK          (0x7 << \
1545                                                 IAVF_AQC_MIRROR_RULE_TYPE_SHIFT)
1546 #define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1
1547 #define IAVF_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS  2
1548 #define IAVF_AQC_MIRROR_RULE_TYPE_VLAN          3
1549 #define IAVF_AQC_MIRROR_RULE_TYPE_ALL_INGRESS   4
1550 #define IAVF_AQC_MIRROR_RULE_TYPE_ALL_EGRESS    5
1551         __le16 num_entries;
1552         __le16 destination;  /* VSI for add, rule id for delete */
1553         __le32 addr_high;    /* address of array of 2-byte VSI or VLAN ids */
1554         __le32 addr_low;
1555 };
1556
1557 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule);
1558
1559 struct iavf_aqc_add_delete_mirror_rule_completion {
1560         u8      reserved[2];
1561         __le16  rule_id;  /* only used on add */
1562         __le16  mirror_rules_used;
1563         __le16  mirror_rules_free;
1564         __le32  addr_high;
1565         __le32  addr_low;
1566 };
1567
1568 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_delete_mirror_rule_completion);
1569
1570 /* Dynamic Device Personalization */
1571 struct iavf_aqc_write_personalization_profile {
1572         u8      flags;
1573         u8      reserved[3];
1574         __le32  profile_track_id;
1575         __le32  addr_high;
1576         __le32  addr_low;
1577 };
1578
1579 IAVF_CHECK_CMD_LENGTH(iavf_aqc_write_personalization_profile);
1580
1581 struct iavf_aqc_write_ddp_resp {
1582         __le32 error_offset;
1583         __le32 error_info;
1584         __le32 addr_high;
1585         __le32 addr_low;
1586 };
1587
1588 struct iavf_aqc_get_applied_profiles {
1589         u8      flags;
1590 #define IAVF_AQC_GET_DDP_GET_CONF       0x1
1591 #define IAVF_AQC_GET_DDP_GET_RDPU_CONF  0x2
1592         u8      rsv[3];
1593         __le32  reserved;
1594         __le32  addr_high;
1595         __le32  addr_low;
1596 };
1597
1598 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_applied_profiles);
1599
1600 /* DCB 0x03xx*/
1601
1602 /* PFC Ignore (direct 0x0301)
1603  *    the command and response use the same descriptor structure
1604  */
1605 struct iavf_aqc_pfc_ignore {
1606         u8      tc_bitmap;
1607         u8      command_flags; /* unused on response */
1608 #define IAVF_AQC_PFC_IGNORE_SET         0x80
1609 #define IAVF_AQC_PFC_IGNORE_CLEAR       0x0
1610         u8      reserved[14];
1611 };
1612
1613 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pfc_ignore);
1614
1615 /* DCB Update (direct 0x0302) uses the iavf_aq_desc structure
1616  * with no parameters
1617  */
1618
1619 /* TX scheduler 0x04xx */
1620
1621 /* Almost all the indirect commands use
1622  * this generic struct to pass the SEID in param0
1623  */
1624 struct iavf_aqc_tx_sched_ind {
1625         __le16  vsi_seid;
1626         u8      reserved[6];
1627         __le32  addr_high;
1628         __le32  addr_low;
1629 };
1630
1631 IAVF_CHECK_CMD_LENGTH(iavf_aqc_tx_sched_ind);
1632
1633 /* Several commands respond with a set of queue set handles */
1634 struct iavf_aqc_qs_handles_resp {
1635         __le16 qs_handles[8];
1636 };
1637
1638 /* Configure VSI BW limits (direct 0x0400) */
1639 struct iavf_aqc_configure_vsi_bw_limit {
1640         __le16  vsi_seid;
1641         u8      reserved[2];
1642         __le16  credit;
1643         u8      reserved1[2];
1644         u8      max_credit; /* 0-3, limit = 2^max */
1645         u8      reserved2[7];
1646 };
1647
1648 IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_vsi_bw_limit);
1649
1650 /* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406)
1651  *    responds with iavf_aqc_qs_handles_resp
1652  */
1653 struct iavf_aqc_configure_vsi_ets_sla_bw_data {
1654         u8      tc_valid_bits;
1655         u8      reserved[15];
1656         __le16  tc_bw_credits[8]; /* FW writesback QS handles here */
1657
1658         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1659         __le16  tc_bw_max[2];
1660         u8      reserved1[28];
1661 };
1662
1663 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_configure_vsi_ets_sla_bw_data);
1664
1665 /* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407)
1666  *    responds with iavf_aqc_qs_handles_resp
1667  */
1668 struct iavf_aqc_configure_vsi_tc_bw_data {
1669         u8      tc_valid_bits;
1670         u8      reserved[3];
1671         u8      tc_bw_credits[8];
1672         u8      reserved1[4];
1673         __le16  qs_handles[8];
1674 };
1675
1676 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_vsi_tc_bw_data);
1677
1678 /* Query vsi bw configuration (indirect 0x0408) */
1679 struct iavf_aqc_query_vsi_bw_config_resp {
1680         u8      tc_valid_bits;
1681         u8      tc_suspended_bits;
1682         u8      reserved[14];
1683         __le16  qs_handles[8];
1684         u8      reserved1[4];
1685         __le16  port_bw_limit;
1686         u8      reserved2[2];
1687         u8      max_bw; /* 0-3, limit = 2^max */
1688         u8      reserved3[23];
1689 };
1690
1691 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_vsi_bw_config_resp);
1692
1693 /* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */
1694 struct iavf_aqc_query_vsi_ets_sla_config_resp {
1695         u8      tc_valid_bits;
1696         u8      reserved[3];
1697         u8      share_credits[8];
1698         __le16  credits[8];
1699
1700         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1701         __le16  tc_bw_max[2];
1702 };
1703
1704 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_vsi_ets_sla_config_resp);
1705
1706 /* Configure Switching Component Bandwidth Limit (direct 0x0410) */
1707 struct iavf_aqc_configure_switching_comp_bw_limit {
1708         __le16  seid;
1709         u8      reserved[2];
1710         __le16  credit;
1711         u8      reserved1[2];
1712         u8      max_bw; /* 0-3, limit = 2^max */
1713         u8      reserved2[7];
1714 };
1715
1716 IAVF_CHECK_CMD_LENGTH(iavf_aqc_configure_switching_comp_bw_limit);
1717
1718 /* Enable  Physical Port ETS (indirect 0x0413)
1719  * Modify  Physical Port ETS (indirect 0x0414)
1720  * Disable Physical Port ETS (indirect 0x0415)
1721  */
1722 struct iavf_aqc_configure_switching_comp_ets_data {
1723         u8      reserved[4];
1724         u8      tc_valid_bits;
1725         u8      seepage;
1726 #define IAVF_AQ_ETS_SEEPAGE_EN_MASK     0x1
1727         u8      tc_strict_priority_flags;
1728         u8      reserved1[17];
1729         u8      tc_bw_share_credits[8];
1730         u8      reserved2[96];
1731 };
1732
1733 IAVF_CHECK_STRUCT_LEN(0x80, iavf_aqc_configure_switching_comp_ets_data);
1734
1735 /* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */
1736 struct iavf_aqc_configure_switching_comp_ets_bw_limit_data {
1737         u8      tc_valid_bits;
1738         u8      reserved[15];
1739         __le16  tc_bw_credit[8];
1740
1741         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1742         __le16  tc_bw_max[2];
1743         u8      reserved1[28];
1744 };
1745
1746 IAVF_CHECK_STRUCT_LEN(0x40,
1747                       iavf_aqc_configure_switching_comp_ets_bw_limit_data);
1748
1749 /* Configure Switching Component Bandwidth Allocation per Tc
1750  * (indirect 0x0417)
1751  */
1752 struct iavf_aqc_configure_switching_comp_bw_config_data {
1753         u8      tc_valid_bits;
1754         u8      reserved[2];
1755         u8      absolute_credits; /* bool */
1756         u8      tc_bw_share_credits[8];
1757         u8      reserved1[20];
1758 };
1759
1760 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_configure_switching_comp_bw_config_data);
1761
1762 /* Query Switching Component Configuration (indirect 0x0418) */
1763 struct iavf_aqc_query_switching_comp_ets_config_resp {
1764         u8      tc_valid_bits;
1765         u8      reserved[35];
1766         __le16  port_bw_limit;
1767         u8      reserved1[2];
1768         u8      tc_bw_max; /* 0-3, limit = 2^max */
1769         u8      reserved2[23];
1770 };
1771
1772 IAVF_CHECK_STRUCT_LEN(0x40, iavf_aqc_query_switching_comp_ets_config_resp);
1773
1774 /* Query PhysicalPort ETS Configuration (indirect 0x0419) */
1775 struct iavf_aqc_query_port_ets_config_resp {
1776         u8      reserved[4];
1777         u8      tc_valid_bits;
1778         u8      reserved1;
1779         u8      tc_strict_priority_bits;
1780         u8      reserved2;
1781         u8      tc_bw_share_credits[8];
1782         __le16  tc_bw_limits[8];
1783
1784         /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */
1785         __le16  tc_bw_max[2];
1786         u8      reserved3[32];
1787 };
1788
1789 IAVF_CHECK_STRUCT_LEN(0x44, iavf_aqc_query_port_ets_config_resp);
1790
1791 /* Query Switching Component Bandwidth Allocation per Traffic Type
1792  * (indirect 0x041A)
1793  */
1794 struct iavf_aqc_query_switching_comp_bw_config_resp {
1795         u8      tc_valid_bits;
1796         u8      reserved[2];
1797         u8      absolute_credits_enable; /* bool */
1798         u8      tc_bw_share_credits[8];
1799         __le16  tc_bw_limits[8];
1800
1801         /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */
1802         __le16  tc_bw_max[2];
1803 };
1804
1805 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_query_switching_comp_bw_config_resp);
1806
1807 /* Suspend/resume port TX traffic
1808  * (direct 0x041B and 0x041C) uses the generic SEID struct
1809  */
1810
1811 /* Configure partition BW
1812  * (indirect 0x041D)
1813  */
1814 struct iavf_aqc_configure_partition_bw_data {
1815         __le16  pf_valid_bits;
1816         u8      min_bw[16];      /* guaranteed bandwidth */
1817         u8      max_bw[16];      /* bandwidth limit */
1818 };
1819
1820 IAVF_CHECK_STRUCT_LEN(0x22, iavf_aqc_configure_partition_bw_data);
1821
1822 /* Get and set the active HMC resource profile and status.
1823  * (direct 0x0500) and (direct 0x0501)
1824  */
1825 struct iavf_aq_get_set_hmc_resource_profile {
1826         u8      pm_profile;
1827         u8      pe_vf_enabled;
1828         u8      reserved[14];
1829 };
1830
1831 IAVF_CHECK_CMD_LENGTH(iavf_aq_get_set_hmc_resource_profile);
1832
1833 enum iavf_aq_hmc_profile {
1834         /* IAVF_HMC_PROFILE_NO_CHANGE   = 0, reserved */
1835         IAVF_HMC_PROFILE_DEFAULT        = 1,
1836         IAVF_HMC_PROFILE_FAVOR_VF       = 2,
1837         IAVF_HMC_PROFILE_EQUAL          = 3,
1838 };
1839
1840 /* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */
1841
1842 /* set in param0 for get phy abilities to report qualified modules */
1843 #define IAVF_AQ_PHY_REPORT_QUALIFIED_MODULES    0x0001
1844 #define IAVF_AQ_PHY_REPORT_INITIAL_VALUES       0x0002
1845
1846 enum iavf_aq_phy_type {
1847         IAVF_PHY_TYPE_SGMII                     = 0x0,
1848         IAVF_PHY_TYPE_1000BASE_KX               = 0x1,
1849         IAVF_PHY_TYPE_10GBASE_KX4               = 0x2,
1850         IAVF_PHY_TYPE_10GBASE_KR                = 0x3,
1851         IAVF_PHY_TYPE_40GBASE_KR4               = 0x4,
1852         IAVF_PHY_TYPE_XAUI                      = 0x5,
1853         IAVF_PHY_TYPE_XFI                       = 0x6,
1854         IAVF_PHY_TYPE_SFI                       = 0x7,
1855         IAVF_PHY_TYPE_XLAUI                     = 0x8,
1856         IAVF_PHY_TYPE_XLPPI                     = 0x9,
1857         IAVF_PHY_TYPE_40GBASE_CR4_CU            = 0xA,
1858         IAVF_PHY_TYPE_10GBASE_CR1_CU            = 0xB,
1859         IAVF_PHY_TYPE_10GBASE_AOC               = 0xC,
1860         IAVF_PHY_TYPE_40GBASE_AOC               = 0xD,
1861         IAVF_PHY_TYPE_UNRECOGNIZED              = 0xE,
1862         IAVF_PHY_TYPE_UNSUPPORTED               = 0xF,
1863         IAVF_PHY_TYPE_100BASE_TX                = 0x11,
1864         IAVF_PHY_TYPE_1000BASE_T                = 0x12,
1865         IAVF_PHY_TYPE_10GBASE_T                 = 0x13,
1866         IAVF_PHY_TYPE_10GBASE_SR                = 0x14,
1867         IAVF_PHY_TYPE_10GBASE_LR                = 0x15,
1868         IAVF_PHY_TYPE_10GBASE_SFPP_CU           = 0x16,
1869         IAVF_PHY_TYPE_10GBASE_CR1               = 0x17,
1870         IAVF_PHY_TYPE_40GBASE_CR4               = 0x18,
1871         IAVF_PHY_TYPE_40GBASE_SR4               = 0x19,
1872         IAVF_PHY_TYPE_40GBASE_LR4               = 0x1A,
1873         IAVF_PHY_TYPE_1000BASE_SX               = 0x1B,
1874         IAVF_PHY_TYPE_1000BASE_LX               = 0x1C,
1875         IAVF_PHY_TYPE_1000BASE_T_OPTICAL        = 0x1D,
1876         IAVF_PHY_TYPE_20GBASE_KR2               = 0x1E,
1877         IAVF_PHY_TYPE_25GBASE_KR                = 0x1F,
1878         IAVF_PHY_TYPE_25GBASE_CR                = 0x20,
1879         IAVF_PHY_TYPE_25GBASE_SR                = 0x21,
1880         IAVF_PHY_TYPE_25GBASE_LR                = 0x22,
1881         IAVF_PHY_TYPE_25GBASE_AOC               = 0x23,
1882         IAVF_PHY_TYPE_25GBASE_ACC               = 0x24,
1883         IAVF_PHY_TYPE_MAX,
1884         IAVF_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP   = 0xFD,
1885         IAVF_PHY_TYPE_EMPTY                     = 0xFE,
1886         IAVF_PHY_TYPE_DEFAULT                   = 0xFF,
1887 };
1888
1889 #define IAVF_LINK_SPEED_100MB_SHIFT     0x1
1890 #define IAVF_LINK_SPEED_1000MB_SHIFT    0x2
1891 #define IAVF_LINK_SPEED_10GB_SHIFT      0x3
1892 #define IAVF_LINK_SPEED_40GB_SHIFT      0x4
1893 #define IAVF_LINK_SPEED_20GB_SHIFT      0x5
1894 #define IAVF_LINK_SPEED_25GB_SHIFT      0x6
1895
1896 enum iavf_aq_link_speed {
1897         IAVF_LINK_SPEED_UNKNOWN = 0,
1898         IAVF_LINK_SPEED_100MB   = (1 << IAVF_LINK_SPEED_100MB_SHIFT),
1899         IAVF_LINK_SPEED_1GB     = (1 << IAVF_LINK_SPEED_1000MB_SHIFT),
1900         IAVF_LINK_SPEED_10GB    = (1 << IAVF_LINK_SPEED_10GB_SHIFT),
1901         IAVF_LINK_SPEED_40GB    = (1 << IAVF_LINK_SPEED_40GB_SHIFT),
1902         IAVF_LINK_SPEED_20GB    = (1 << IAVF_LINK_SPEED_20GB_SHIFT),
1903         IAVF_LINK_SPEED_25GB    = (1 << IAVF_LINK_SPEED_25GB_SHIFT),
1904 };
1905
1906 struct iavf_aqc_module_desc {
1907         u8 oui[3];
1908         u8 reserved1;
1909         u8 part_number[16];
1910         u8 revision[4];
1911         u8 reserved2[8];
1912 };
1913
1914 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_module_desc);
1915
1916 struct iavf_aq_get_phy_abilities_resp {
1917         __le32  phy_type;       /* bitmap using the above enum for offsets */
1918         u8      link_speed;     /* bitmap using the above enum bit patterns */
1919         u8      abilities;
1920 #define IAVF_AQ_PHY_FLAG_PAUSE_TX       0x01
1921 #define IAVF_AQ_PHY_FLAG_PAUSE_RX       0x02
1922 #define IAVF_AQ_PHY_FLAG_LOW_POWER      0x04
1923 #define IAVF_AQ_PHY_LINK_ENABLED        0x08
1924 #define IAVF_AQ_PHY_AN_ENABLED          0x10
1925 #define IAVF_AQ_PHY_FLAG_MODULE_QUAL    0x20
1926 #define IAVF_AQ_PHY_FEC_ABILITY_KR      0x40
1927 #define IAVF_AQ_PHY_FEC_ABILITY_RS      0x80
1928         __le16  eee_capability;
1929 #define IAVF_AQ_EEE_100BASE_TX          0x0002
1930 #define IAVF_AQ_EEE_1000BASE_T          0x0004
1931 #define IAVF_AQ_EEE_10GBASE_T           0x0008
1932 #define IAVF_AQ_EEE_1000BASE_KX         0x0010
1933 #define IAVF_AQ_EEE_10GBASE_KX4         0x0020
1934 #define IAVF_AQ_EEE_10GBASE_KR          0x0040
1935         __le32  eeer_val;
1936         u8      d3_lpan;
1937 #define IAVF_AQ_SET_PHY_D3_LPAN_ENA     0x01
1938         u8      phy_type_ext;
1939 #define IAVF_AQ_PHY_TYPE_EXT_25G_KR     0x01
1940 #define IAVF_AQ_PHY_TYPE_EXT_25G_CR     0x02
1941 #define IAVF_AQ_PHY_TYPE_EXT_25G_SR     0x04
1942 #define IAVF_AQ_PHY_TYPE_EXT_25G_LR     0x08
1943 #define IAVF_AQ_PHY_TYPE_EXT_25G_AOC    0x10
1944 #define IAVF_AQ_PHY_TYPE_EXT_25G_ACC    0x20
1945         u8      fec_cfg_curr_mod_ext_info;
1946 #define IAVF_AQ_ENABLE_FEC_KR           0x01
1947 #define IAVF_AQ_ENABLE_FEC_RS           0x02
1948 #define IAVF_AQ_REQUEST_FEC_KR          0x04
1949 #define IAVF_AQ_REQUEST_FEC_RS          0x08
1950 #define IAVF_AQ_ENABLE_FEC_AUTO         0x10
1951 #define IAVF_AQ_FEC
1952 #define IAVF_AQ_MODULE_TYPE_EXT_MASK    0xE0
1953 #define IAVF_AQ_MODULE_TYPE_EXT_SHIFT   5
1954
1955         u8      ext_comp_code;
1956         u8      phy_id[4];
1957         u8      module_type[3];
1958         u8      qualified_module_count;
1959 #define IAVF_AQ_PHY_MAX_QMS             16
1960         struct iavf_aqc_module_desc     qualified_module[IAVF_AQ_PHY_MAX_QMS];
1961 };
1962
1963 IAVF_CHECK_STRUCT_LEN(0x218, iavf_aq_get_phy_abilities_resp);
1964
1965 /* Set PHY Config (direct 0x0601) */
1966 struct iavf_aq_set_phy_config { /* same bits as above in all */
1967         __le32  phy_type;
1968         u8      link_speed;
1969         u8      abilities;
1970 /* bits 0-2 use the values from get_phy_abilities_resp */
1971 #define IAVF_AQ_PHY_ENABLE_LINK         0x08
1972 #define IAVF_AQ_PHY_ENABLE_AN           0x10
1973 #define IAVF_AQ_PHY_ENABLE_ATOMIC_LINK  0x20
1974         __le16  eee_capability;
1975         __le32  eeer;
1976         u8      low_power_ctrl;
1977         u8      phy_type_ext;
1978         u8      fec_config;
1979 #define IAVF_AQ_SET_FEC_ABILITY_KR      BIT(0)
1980 #define IAVF_AQ_SET_FEC_ABILITY_RS      BIT(1)
1981 #define IAVF_AQ_SET_FEC_REQUEST_KR      BIT(2)
1982 #define IAVF_AQ_SET_FEC_REQUEST_RS      BIT(3)
1983 #define IAVF_AQ_SET_FEC_AUTO            BIT(4)
1984 #define IAVF_AQ_PHY_FEC_CONFIG_SHIFT    0x0
1985 #define IAVF_AQ_PHY_FEC_CONFIG_MASK     (0x1F << IAVF_AQ_PHY_FEC_CONFIG_SHIFT)
1986         u8      reserved;
1987 };
1988
1989 IAVF_CHECK_CMD_LENGTH(iavf_aq_set_phy_config);
1990
1991 /* Set MAC Config command data structure (direct 0x0603) */
1992 struct iavf_aq_set_mac_config {
1993         __le16  max_frame_size;
1994         u8      params;
1995 #define IAVF_AQ_SET_MAC_CONFIG_CRC_EN           0x04
1996 #define IAVF_AQ_SET_MAC_CONFIG_PACING_MASK      0x78
1997 #define IAVF_AQ_SET_MAC_CONFIG_PACING_SHIFT     3
1998 #define IAVF_AQ_SET_MAC_CONFIG_PACING_NONE      0x0
1999 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1B_13TX   0xF
2000 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_9TX   0x9
2001 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_4TX   0x8
2002 #define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_7TX   0x7
2003 #define IAVF_AQ_SET_MAC_CONFIG_PACING_2DW_3TX   0x6
2004 #define IAVF_AQ_SET_MAC_CONFIG_PACING_1DW_1TX   0x5
2005 #define IAVF_AQ_SET_MAC_CONFIG_PACING_3DW_2TX   0x4
2006 #define IAVF_AQ_SET_MAC_CONFIG_PACING_7DW_3TX   0x3
2007 #define IAVF_AQ_SET_MAC_CONFIG_PACING_4DW_1TX   0x2
2008 #define IAVF_AQ_SET_MAC_CONFIG_PACING_9DW_1TX   0x1
2009         u8      tx_timer_priority; /* bitmap */
2010         __le16  tx_timer_value;
2011         __le16  fc_refresh_threshold;
2012         u8      reserved[8];
2013 };
2014
2015 IAVF_CHECK_CMD_LENGTH(iavf_aq_set_mac_config);
2016
2017 /* Restart Auto-Negotiation (direct 0x605) */
2018 struct iavf_aqc_set_link_restart_an {
2019         u8      command;
2020 #define IAVF_AQ_PHY_RESTART_AN  0x02
2021 #define IAVF_AQ_PHY_LINK_ENABLE 0x04
2022         u8      reserved[15];
2023 };
2024
2025 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_link_restart_an);
2026
2027 /* Get Link Status cmd & response data structure (direct 0x0607) */
2028 struct iavf_aqc_get_link_status {
2029         __le16  command_flags; /* only field set on command */
2030 #define IAVF_AQ_LSE_MASK                0x3
2031 #define IAVF_AQ_LSE_NOP                 0x0
2032 #define IAVF_AQ_LSE_DISABLE             0x2
2033 #define IAVF_AQ_LSE_ENABLE              0x3
2034 /* only response uses this flag */
2035 #define IAVF_AQ_LSE_IS_ENABLED          0x1
2036         u8      phy_type;    /* iavf_aq_phy_type   */
2037         u8      link_speed;  /* iavf_aq_link_speed */
2038         u8      link_info;
2039 #define IAVF_AQ_LINK_UP                 0x01    /* obsolete */
2040 #define IAVF_AQ_LINK_UP_FUNCTION        0x01
2041 #define IAVF_AQ_LINK_FAULT              0x02
2042 #define IAVF_AQ_LINK_FAULT_TX           0x04
2043 #define IAVF_AQ_LINK_FAULT_RX           0x08
2044 #define IAVF_AQ_LINK_FAULT_REMOTE       0x10
2045 #define IAVF_AQ_LINK_UP_PORT            0x20
2046 #define IAVF_AQ_MEDIA_AVAILABLE         0x40
2047 #define IAVF_AQ_SIGNAL_DETECT           0x80
2048         u8      an_info;
2049 #define IAVF_AQ_AN_COMPLETED            0x01
2050 #define IAVF_AQ_LP_AN_ABILITY           0x02
2051 #define IAVF_AQ_PD_FAULT                0x04
2052 #define IAVF_AQ_FEC_EN                  0x08
2053 #define IAVF_AQ_PHY_LOW_POWER           0x10
2054 #define IAVF_AQ_LINK_PAUSE_TX           0x20
2055 #define IAVF_AQ_LINK_PAUSE_RX           0x40
2056 #define IAVF_AQ_QUALIFIED_MODULE        0x80
2057         u8      ext_info;
2058 #define IAVF_AQ_LINK_PHY_TEMP_ALARM     0x01
2059 #define IAVF_AQ_LINK_XCESSIVE_ERRORS    0x02
2060 #define IAVF_AQ_LINK_TX_SHIFT           0x02
2061 #define IAVF_AQ_LINK_TX_MASK            (0x03 << IAVF_AQ_LINK_TX_SHIFT)
2062 #define IAVF_AQ_LINK_TX_ACTIVE          0x00
2063 #define IAVF_AQ_LINK_TX_DRAINED         0x01
2064 #define IAVF_AQ_LINK_TX_FLUSHED         0x03
2065 #define IAVF_AQ_LINK_FORCED_40G         0x10
2066 /* 25G Error Codes */
2067 #define IAVF_AQ_25G_NO_ERR              0X00
2068 #define IAVF_AQ_25G_NOT_PRESENT         0X01
2069 #define IAVF_AQ_25G_NVM_CRC_ERR         0X02
2070 #define IAVF_AQ_25G_SBUS_UCODE_ERR      0X03
2071 #define IAVF_AQ_25G_SERDES_UCODE_ERR    0X04
2072 #define IAVF_AQ_25G_NIMB_UCODE_ERR      0X05
2073         u8      loopback; /* use defines from iavf_aqc_set_lb_mode */
2074 /* Since firmware API 1.7 loopback field keeps power class info as well */
2075 #define IAVF_AQ_LOOPBACK_MASK           0x07
2076 #define IAVF_AQ_PWR_CLASS_SHIFT_LB      6
2077 #define IAVF_AQ_PWR_CLASS_MASK_LB       (0x03 << IAVF_AQ_PWR_CLASS_SHIFT_LB)
2078         __le16  max_frame_size;
2079         u8      config;
2080 #define IAVF_AQ_CONFIG_FEC_KR_ENA       0x01
2081 #define IAVF_AQ_CONFIG_FEC_RS_ENA       0x02
2082 #define IAVF_AQ_CONFIG_CRC_ENA          0x04
2083 #define IAVF_AQ_CONFIG_PACING_MASK      0x78
2084         union {
2085                 struct {
2086                         u8      power_desc;
2087 #define IAVF_AQ_LINK_POWER_CLASS_1      0x00
2088 #define IAVF_AQ_LINK_POWER_CLASS_2      0x01
2089 #define IAVF_AQ_LINK_POWER_CLASS_3      0x02
2090 #define IAVF_AQ_LINK_POWER_CLASS_4      0x03
2091 #define IAVF_AQ_PWR_CLASS_MASK          0x03
2092                         u8      reserved[4];
2093                 };
2094                 struct {
2095                         u8      link_type[4];
2096                         u8      link_type_ext;
2097                 };
2098         };
2099 };
2100
2101 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_link_status);
2102
2103 /* Set event mask command (direct 0x613) */
2104 struct iavf_aqc_set_phy_int_mask {
2105         u8      reserved[8];
2106         __le16  event_mask;
2107 #define IAVF_AQ_EVENT_LINK_UPDOWN       0x0002
2108 #define IAVF_AQ_EVENT_MEDIA_NA          0x0004
2109 #define IAVF_AQ_EVENT_LINK_FAULT        0x0008
2110 #define IAVF_AQ_EVENT_PHY_TEMP_ALARM    0x0010
2111 #define IAVF_AQ_EVENT_EXCESSIVE_ERRORS  0x0020
2112 #define IAVF_AQ_EVENT_SIGNAL_DETECT     0x0040
2113 #define IAVF_AQ_EVENT_AN_COMPLETED      0x0080
2114 #define IAVF_AQ_EVENT_MODULE_QUAL_FAIL  0x0100
2115 #define IAVF_AQ_EVENT_PORT_TX_SUSPENDED 0x0200
2116         u8      reserved1[6];
2117 };
2118
2119 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_int_mask);
2120
2121 /* Get Local AN advt register (direct 0x0614)
2122  * Set Local AN advt register (direct 0x0615)
2123  * Get Link Partner AN advt register (direct 0x0616)
2124  */
2125 struct iavf_aqc_an_advt_reg {
2126         __le32  local_an_reg0;
2127         __le16  local_an_reg1;
2128         u8      reserved[10];
2129 };
2130
2131 IAVF_CHECK_CMD_LENGTH(iavf_aqc_an_advt_reg);
2132
2133 /* Set Loopback mode (0x0618) */
2134 struct iavf_aqc_set_lb_mode {
2135         u8      lb_level;
2136 #define IAVF_AQ_LB_NONE 0
2137 #define IAVF_AQ_LB_MAC  1
2138 #define IAVF_AQ_LB_SERDES       2
2139 #define IAVF_AQ_LB_PHY_INT      3
2140 #define IAVF_AQ_LB_PHY_EXT      4
2141 #define IAVF_AQ_LB_CPVL_PCS     5
2142 #define IAVF_AQ_LB_CPVL_EXT     6
2143 #define IAVF_AQ_LB_PHY_LOCAL    0x01
2144 #define IAVF_AQ_LB_PHY_REMOTE   0x02
2145 #define IAVF_AQ_LB_MAC_LOCAL    0x04
2146         u8      lb_type;
2147 #define IAVF_AQ_LB_LOCAL        0
2148 #define IAVF_AQ_LB_FAR  0x01
2149         u8      speed;
2150 #define IAVF_AQ_LB_SPEED_NONE   0
2151 #define IAVF_AQ_LB_SPEED_1G     1
2152 #define IAVF_AQ_LB_SPEED_10G    2
2153 #define IAVF_AQ_LB_SPEED_40G    3
2154 #define IAVF_AQ_LB_SPEED_20G    4
2155         u8      force_speed;
2156         u8      reserved[12];
2157 };
2158
2159 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_lb_mode);
2160
2161 /* Set PHY Debug command (0x0622) */
2162 struct iavf_aqc_set_phy_debug {
2163         u8      command_flags;
2164 #define IAVF_AQ_PHY_DEBUG_RESET_INTERNAL        0x02
2165 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT  2
2166 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK   (0x03 << \
2167                                         IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT)
2168 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE   0x00
2169 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD   0x01
2170 #define IAVF_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT   0x02
2171 /* Disable link manageability on a single port */
2172 #define IAVF_AQ_PHY_DEBUG_DISABLE_LINK_FW       0x10
2173 /* Disable link manageability on all ports needs both bits 4 and 5 */
2174 #define IAVF_AQ_PHY_DEBUG_DISABLE_ALL_LINK_FW   0x20
2175         u8      reserved[15];
2176 };
2177
2178 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_phy_debug);
2179
2180 enum iavf_aq_phy_reg_type {
2181         IAVF_AQC_PHY_REG_INTERNAL       = 0x1,
2182         IAVF_AQC_PHY_REG_EXERNAL_BASET  = 0x2,
2183         IAVF_AQC_PHY_REG_EXERNAL_MODULE = 0x3
2184 };
2185
2186 /* Run PHY Activity (0x0626) */
2187 struct iavf_aqc_run_phy_activity {
2188         __le16  activity_id;
2189         u8      flags;
2190         u8      reserved1;
2191         __le32  control;
2192         __le32  data;
2193         u8      reserved2[4];
2194 };
2195
2196 IAVF_CHECK_CMD_LENGTH(iavf_aqc_run_phy_activity);
2197
2198 /* Set PHY Register command (0x0628) */
2199 /* Get PHY Register command (0x0629) */
2200 struct iavf_aqc_phy_register_access {
2201         u8      phy_interface;
2202 #define IAVF_AQ_PHY_REG_ACCESS_INTERNAL 0
2203 #define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL 1
2204 #define IAVF_AQ_PHY_REG_ACCESS_EXTERNAL_MODULE  2
2205         u8      dev_addres;
2206         u8      reserved1[2];
2207         __le32  reg_address;
2208         __le32  reg_value;
2209         u8      reserved2[4];
2210 };
2211
2212 IAVF_CHECK_CMD_LENGTH(iavf_aqc_phy_register_access);
2213
2214 /* NVM Read command (indirect 0x0701)
2215  * NVM Erase commands (direct 0x0702)
2216  * NVM Update commands (indirect 0x0703)
2217  */
2218 struct iavf_aqc_nvm_update {
2219         u8      command_flags;
2220 #define IAVF_AQ_NVM_LAST_CMD                    0x01
2221 #define IAVF_AQ_NVM_FLASH_ONLY                  0x80
2222 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_SHIFT    1
2223 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_MASK     0x03
2224 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_SELECTED 0x03
2225 #define IAVF_AQ_NVM_PRESERVATION_FLAGS_ALL      0x01
2226         u8      module_pointer;
2227         __le16  length;
2228         __le32  offset;
2229         __le32  addr_high;
2230         __le32  addr_low;
2231 };
2232
2233 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_update);
2234
2235 /* NVM Config Read (indirect 0x0704) */
2236 struct iavf_aqc_nvm_config_read {
2237         __le16  cmd_flags;
2238 #define IAVF_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK   1
2239 #define IAVF_AQ_ANVM_READ_SINGLE_FEATURE                0
2240 #define IAVF_AQ_ANVM_READ_MULTIPLE_FEATURES             1
2241         __le16  element_count;
2242         __le16  element_id;     /* Feature/field ID */
2243         __le16  element_id_msw; /* MSWord of field ID */
2244         __le32  address_high;
2245         __le32  address_low;
2246 };
2247
2248 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_read);
2249
2250 /* NVM Config Write (indirect 0x0705) */
2251 struct iavf_aqc_nvm_config_write {
2252         __le16  cmd_flags;
2253         __le16  element_count;
2254         u8      reserved[4];
2255         __le32  address_high;
2256         __le32  address_low;
2257 };
2258
2259 IAVF_CHECK_CMD_LENGTH(iavf_aqc_nvm_config_write);
2260
2261 /* Used for 0x0704 as well as for 0x0705 commands */
2262 #define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT         1
2263 #define IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK \
2264                                 (1 << IAVF_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT)
2265 #define IAVF_AQ_ANVM_FEATURE            0
2266 #define IAVF_AQ_ANVM_IMMEDIATE_FIELD    (1 << FEATURE_OR_IMMEDIATE_SHIFT)
2267 struct iavf_aqc_nvm_config_data_feature {
2268         __le16 feature_id;
2269 #define IAVF_AQ_ANVM_FEATURE_OPTION_OEM_ONLY            0x01
2270 #define IAVF_AQ_ANVM_FEATURE_OPTION_DWORD_MAP           0x08
2271 #define IAVF_AQ_ANVM_FEATURE_OPTION_POR_CSR             0x10
2272         __le16 feature_options;
2273         __le16 feature_selection;
2274 };
2275
2276 IAVF_CHECK_STRUCT_LEN(0x6, iavf_aqc_nvm_config_data_feature);
2277
2278 struct iavf_aqc_nvm_config_data_immediate_field {
2279         __le32 field_id;
2280         __le32 field_value;
2281         __le16 field_options;
2282         __le16 reserved;
2283 };
2284
2285 IAVF_CHECK_STRUCT_LEN(0xc, iavf_aqc_nvm_config_data_immediate_field);
2286
2287 /* OEM Post Update (indirect 0x0720)
2288  * no command data struct used
2289  */
2290 struct iavf_aqc_nvm_oem_post_update {
2291 #define IAVF_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA       0x01
2292         u8 sel_data;
2293         u8 reserved[7];
2294 };
2295
2296 IAVF_CHECK_STRUCT_LEN(0x8, iavf_aqc_nvm_oem_post_update);
2297
2298 struct iavf_aqc_nvm_oem_post_update_buffer {
2299         u8 str_len;
2300         u8 dev_addr;
2301         __le16 eeprom_addr;
2302         u8 data[36];
2303 };
2304
2305 IAVF_CHECK_STRUCT_LEN(0x28, iavf_aqc_nvm_oem_post_update_buffer);
2306
2307 /* Thermal Sensor (indirect 0x0721)
2308  *     read or set thermal sensor configs and values
2309  *     takes a sensor and command specific data buffer, not detailed here
2310  */
2311 struct iavf_aqc_thermal_sensor {
2312         u8 sensor_action;
2313 #define IAVF_AQ_THERMAL_SENSOR_READ_CONFIG      0
2314 #define IAVF_AQ_THERMAL_SENSOR_SET_CONFIG       1
2315 #define IAVF_AQ_THERMAL_SENSOR_READ_TEMP        2
2316         u8 reserved[7];
2317         __le32  addr_high;
2318         __le32  addr_low;
2319 };
2320
2321 IAVF_CHECK_CMD_LENGTH(iavf_aqc_thermal_sensor);
2322
2323 /* Send to PF command (indirect 0x0801) id is only used by PF
2324  * Send to VF command (indirect 0x0802) id is only used by PF
2325  * Send to Peer PF command (indirect 0x0803)
2326  */
2327 struct iavf_aqc_pf_vf_message {
2328         __le32  id;
2329         u8      reserved[4];
2330         __le32  addr_high;
2331         __le32  addr_low;
2332 };
2333
2334 IAVF_CHECK_CMD_LENGTH(iavf_aqc_pf_vf_message);
2335
2336 /* Alternate structure */
2337
2338 /* Direct write (direct 0x0900)
2339  * Direct read (direct 0x0902)
2340  */
2341 struct iavf_aqc_alternate_write {
2342         __le32 address0;
2343         __le32 data0;
2344         __le32 address1;
2345         __le32 data1;
2346 };
2347
2348 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write);
2349
2350 /* Indirect write (indirect 0x0901)
2351  * Indirect read (indirect 0x0903)
2352  */
2353
2354 struct iavf_aqc_alternate_ind_write {
2355         __le32 address;
2356         __le32 length;
2357         __le32 addr_high;
2358         __le32 addr_low;
2359 };
2360
2361 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_ind_write);
2362
2363 /* Done alternate write (direct 0x0904)
2364  * uses iavf_aq_desc
2365  */
2366 struct iavf_aqc_alternate_write_done {
2367         __le16  cmd_flags;
2368 #define IAVF_AQ_ALTERNATE_MODE_BIOS_MASK        1
2369 #define IAVF_AQ_ALTERNATE_MODE_BIOS_LEGACY      0
2370 #define IAVF_AQ_ALTERNATE_MODE_BIOS_UEFI        1
2371 #define IAVF_AQ_ALTERNATE_RESET_NEEDED          2
2372         u8      reserved[14];
2373 };
2374
2375 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_write_done);
2376
2377 /* Set OEM mode (direct 0x0905) */
2378 struct iavf_aqc_alternate_set_mode {
2379         __le32  mode;
2380 #define IAVF_AQ_ALTERNATE_MODE_NONE     0
2381 #define IAVF_AQ_ALTERNATE_MODE_OEM      1
2382         u8      reserved[12];
2383 };
2384
2385 IAVF_CHECK_CMD_LENGTH(iavf_aqc_alternate_set_mode);
2386
2387 /* Clear port Alternate RAM (direct 0x0906) uses iavf_aq_desc */
2388
2389 /* async events 0x10xx */
2390
2391 /* Lan Queue Overflow Event (direct, 0x1001) */
2392 struct iavf_aqc_lan_overflow {
2393         __le32  prtdcb_rupto;
2394         __le32  otx_ctl;
2395         u8      reserved[8];
2396 };
2397
2398 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lan_overflow);
2399
2400 /* Get LLDP MIB (indirect 0x0A00) */
2401 struct iavf_aqc_lldp_get_mib {
2402         u8      type;
2403         u8      reserved1;
2404 #define IAVF_AQ_LLDP_MIB_TYPE_MASK              0x3
2405 #define IAVF_AQ_LLDP_MIB_LOCAL                  0x0
2406 #define IAVF_AQ_LLDP_MIB_REMOTE                 0x1
2407 #define IAVF_AQ_LLDP_MIB_LOCAL_AND_REMOTE       0x2
2408 #define IAVF_AQ_LLDP_BRIDGE_TYPE_MASK           0xC
2409 #define IAVF_AQ_LLDP_BRIDGE_TYPE_SHIFT          0x2
2410 #define IAVF_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0
2411 #define IAVF_AQ_LLDP_BRIDGE_TYPE_NON_TPMR       0x1
2412 #define IAVF_AQ_LLDP_TX_SHIFT                   0x4
2413 #define IAVF_AQ_LLDP_TX_MASK                    (0x03 << IAVF_AQ_LLDP_TX_SHIFT)
2414 /* TX pause flags use IAVF_AQ_LINK_TX_* above */
2415         __le16  local_len;
2416         __le16  remote_len;
2417         u8      reserved2[2];
2418         __le32  addr_high;
2419         __le32  addr_low;
2420 };
2421
2422 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_get_mib);
2423
2424 /* Configure LLDP MIB Change Event (direct 0x0A01)
2425  * also used for the event (with type in the command field)
2426  */
2427 struct iavf_aqc_lldp_update_mib {
2428         u8      command;
2429 #define IAVF_AQ_LLDP_MIB_UPDATE_ENABLE  0x0
2430 #define IAVF_AQ_LLDP_MIB_UPDATE_DISABLE 0x1
2431         u8      reserved[7];
2432         __le32  addr_high;
2433         __le32  addr_low;
2434 };
2435
2436 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_mib);
2437
2438 /* Add LLDP TLV (indirect 0x0A02)
2439  * Delete LLDP TLV (indirect 0x0A04)
2440  */
2441 struct iavf_aqc_lldp_add_tlv {
2442         u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2443         u8      reserved1[1];
2444         __le16  len;
2445         u8      reserved2[4];
2446         __le32  addr_high;
2447         __le32  addr_low;
2448 };
2449
2450 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_add_tlv);
2451
2452 /* Update LLDP TLV (indirect 0x0A03) */
2453 struct iavf_aqc_lldp_update_tlv {
2454         u8      type; /* only nearest bridge and non-TPMR from 0x0A00 */
2455         u8      reserved;
2456         __le16  old_len;
2457         __le16  new_offset;
2458         __le16  new_len;
2459         __le32  addr_high;
2460         __le32  addr_low;
2461 };
2462
2463 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_update_tlv);
2464
2465 /* Stop LLDP (direct 0x0A05) */
2466 struct iavf_aqc_lldp_stop {
2467         u8      command;
2468 #define IAVF_AQ_LLDP_AGENT_STOP         0x0
2469 #define IAVF_AQ_LLDP_AGENT_SHUTDOWN     0x1
2470         u8      reserved[15];
2471 };
2472
2473 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop);
2474
2475 /* Start LLDP (direct 0x0A06) */
2476
2477 struct iavf_aqc_lldp_start {
2478         u8      command;
2479 #define IAVF_AQ_LLDP_AGENT_START        0x1
2480         u8      reserved[15];
2481 };
2482
2483 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_start);
2484
2485 /* Set DCB (direct 0x0303) */
2486 struct iavf_aqc_set_dcb_parameters {
2487         u8 command;
2488 #define IAVF_AQ_DCB_SET_AGENT   0x1
2489 #define IAVF_DCB_VALID          0x1
2490         u8 valid_flags;
2491         u8 reserved[14];
2492 };
2493
2494 IAVF_CHECK_CMD_LENGTH(iavf_aqc_set_dcb_parameters);
2495
2496 /* Get CEE DCBX Oper Config (0x0A07)
2497  * uses the generic descriptor struct
2498  * returns below as indirect response
2499  */
2500
2501 #define IAVF_AQC_CEE_APP_FCOE_SHIFT     0x0
2502 #define IAVF_AQC_CEE_APP_FCOE_MASK      (0x7 << IAVF_AQC_CEE_APP_FCOE_SHIFT)
2503 #define IAVF_AQC_CEE_APP_ISCSI_SHIFT    0x3
2504 #define IAVF_AQC_CEE_APP_ISCSI_MASK     (0x7 << IAVF_AQC_CEE_APP_ISCSI_SHIFT)
2505 #define IAVF_AQC_CEE_APP_FIP_SHIFT      0x8
2506 #define IAVF_AQC_CEE_APP_FIP_MASK       (0x7 << IAVF_AQC_CEE_APP_FIP_SHIFT)
2507
2508 #define IAVF_AQC_CEE_PG_STATUS_SHIFT    0x0
2509 #define IAVF_AQC_CEE_PG_STATUS_MASK     (0x7 << IAVF_AQC_CEE_PG_STATUS_SHIFT)
2510 #define IAVF_AQC_CEE_PFC_STATUS_SHIFT   0x3
2511 #define IAVF_AQC_CEE_PFC_STATUS_MASK    (0x7 << IAVF_AQC_CEE_PFC_STATUS_SHIFT)
2512 #define IAVF_AQC_CEE_APP_STATUS_SHIFT   0x8
2513 #define IAVF_AQC_CEE_APP_STATUS_MASK    (0x7 << IAVF_AQC_CEE_APP_STATUS_SHIFT)
2514 #define IAVF_AQC_CEE_FCOE_STATUS_SHIFT  0x8
2515 #define IAVF_AQC_CEE_FCOE_STATUS_MASK   (0x7 << IAVF_AQC_CEE_FCOE_STATUS_SHIFT)
2516 #define IAVF_AQC_CEE_ISCSI_STATUS_SHIFT 0xB
2517 #define IAVF_AQC_CEE_ISCSI_STATUS_MASK  (0x7 << IAVF_AQC_CEE_ISCSI_STATUS_SHIFT)
2518 #define IAVF_AQC_CEE_FIP_STATUS_SHIFT   0x10
2519 #define IAVF_AQC_CEE_FIP_STATUS_MASK    (0x7 << IAVF_AQC_CEE_FIP_STATUS_SHIFT)
2520
2521 /* struct iavf_aqc_get_cee_dcb_cfg_v1_resp was originally defined with
2522  * word boundary layout issues, which the Linux compilers silently deal
2523  * with by adding padding, making the actual struct larger than designed.
2524  * However, the FW compiler for the NIC is less lenient and complains
2525  * about the struct.  Hence, the struct defined here has an extra byte in
2526  * fields reserved3 and reserved4 to directly acknowledge that padding,
2527  * and the new length is used in the length check macro.
2528  */
2529 struct iavf_aqc_get_cee_dcb_cfg_v1_resp {
2530         u8      reserved1;
2531         u8      oper_num_tc;
2532         u8      oper_prio_tc[4];
2533         u8      reserved2;
2534         u8      oper_tc_bw[8];
2535         u8      oper_pfc_en;
2536         u8      reserved3[2];
2537         __le16  oper_app_prio;
2538         u8      reserved4[2];
2539         __le16  tlv_status;
2540 };
2541
2542 IAVF_CHECK_STRUCT_LEN(0x18, iavf_aqc_get_cee_dcb_cfg_v1_resp);
2543
2544 struct iavf_aqc_get_cee_dcb_cfg_resp {
2545         u8      oper_num_tc;
2546         u8      oper_prio_tc[4];
2547         u8      oper_tc_bw[8];
2548         u8      oper_pfc_en;
2549         __le16  oper_app_prio;
2550         __le32  tlv_status;
2551         u8      reserved[12];
2552 };
2553
2554 IAVF_CHECK_STRUCT_LEN(0x20, iavf_aqc_get_cee_dcb_cfg_resp);
2555
2556 /*      Set Local LLDP MIB (indirect 0x0A08)
2557  *      Used to replace the local MIB of a given LLDP agent. e.g. DCBx
2558  */
2559 struct iavf_aqc_lldp_set_local_mib {
2560 #define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT        0
2561 #define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << \
2562                                         SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT)
2563 #define SET_LOCAL_MIB_AC_TYPE_LOCAL_MIB 0x0
2564 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT    (1)
2565 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_MASK     (1 << \
2566                                 SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS_SHIFT)
2567 #define SET_LOCAL_MIB_AC_TYPE_NON_WILLING_APPS          0x1
2568         u8      type;
2569         u8      reserved0;
2570         __le16  length;
2571         u8      reserved1[4];
2572         __le32  address_high;
2573         __le32  address_low;
2574 };
2575
2576 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_set_local_mib);
2577
2578 struct iavf_aqc_lldp_set_local_mib_resp {
2579 #define SET_LOCAL_MIB_RESP_EVENT_TRIGGERED_MASK      0x01
2580         u8  status;
2581         u8  reserved[15];
2582 };
2583
2584 IAVF_CHECK_STRUCT_LEN(0x10, iavf_aqc_lldp_set_local_mib_resp);
2585
2586 /*      Stop/Start LLDP Agent (direct 0x0A09)
2587  *      Used for stopping/starting specific LLDP agent. e.g. DCBx
2588  */
2589 struct iavf_aqc_lldp_stop_start_specific_agent {
2590 #define IAVF_AQC_START_SPECIFIC_AGENT_SHIFT     0
2591 #define IAVF_AQC_START_SPECIFIC_AGENT_MASK \
2592                                 (1 << IAVF_AQC_START_SPECIFIC_AGENT_SHIFT)
2593         u8      command;
2594         u8      reserved[15];
2595 };
2596
2597 IAVF_CHECK_CMD_LENGTH(iavf_aqc_lldp_stop_start_specific_agent);
2598
2599 /* Add Udp Tunnel command and completion (direct 0x0B00) */
2600 struct iavf_aqc_add_udp_tunnel {
2601         __le16  udp_port;
2602         u8      reserved0[3];
2603         u8      protocol_type;
2604 #define IAVF_AQC_TUNNEL_TYPE_VXLAN      0x00
2605 #define IAVF_AQC_TUNNEL_TYPE_NGE        0x01
2606 #define IAVF_AQC_TUNNEL_TYPE_TEREDO     0x10
2607 #define IAVF_AQC_TUNNEL_TYPE_VXLAN_GPE  0x11
2608         u8      reserved1[10];
2609 };
2610
2611 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel);
2612
2613 struct iavf_aqc_add_udp_tunnel_completion {
2614         __le16  udp_port;
2615         u8      filter_entry_index;
2616         u8      multiple_pfs;
2617 #define IAVF_AQC_SINGLE_PF              0x0
2618 #define IAVF_AQC_MULTIPLE_PFS           0x1
2619         u8      total_filters;
2620         u8      reserved[11];
2621 };
2622
2623 IAVF_CHECK_CMD_LENGTH(iavf_aqc_add_udp_tunnel_completion);
2624
2625 /* remove UDP Tunnel command (0x0B01) */
2626 struct iavf_aqc_remove_udp_tunnel {
2627         u8      reserved[2];
2628         u8      index; /* 0 to 15 */
2629         u8      reserved2[13];
2630 };
2631
2632 IAVF_CHECK_CMD_LENGTH(iavf_aqc_remove_udp_tunnel);
2633
2634 struct iavf_aqc_del_udp_tunnel_completion {
2635         __le16  udp_port;
2636         u8      index; /* 0 to 15 */
2637         u8      multiple_pfs;
2638         u8      total_filters_used;
2639         u8      reserved1[11];
2640 };
2641
2642 IAVF_CHECK_CMD_LENGTH(iavf_aqc_del_udp_tunnel_completion);
2643
2644 struct iavf_aqc_get_set_rss_key {
2645 #define IAVF_AQC_SET_RSS_KEY_VSI_VALID          (0x1 << 15)
2646 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT       0
2647 #define IAVF_AQC_SET_RSS_KEY_VSI_ID_MASK        (0x3FF << \
2648                                         IAVF_AQC_SET_RSS_KEY_VSI_ID_SHIFT)
2649         __le16  vsi_id;
2650         u8      reserved[6];
2651         __le32  addr_high;
2652         __le32  addr_low;
2653 };
2654
2655 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_key);
2656
2657 struct iavf_aqc_get_set_rss_key_data {
2658         u8 standard_rss_key[0x28];
2659         u8 extended_hash_key[0xc];
2660 };
2661
2662 IAVF_CHECK_STRUCT_LEN(0x34, iavf_aqc_get_set_rss_key_data);
2663
2664 struct  iavf_aqc_get_set_rss_lut {
2665 #define IAVF_AQC_SET_RSS_LUT_VSI_VALID          (0x1 << 15)
2666 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT       0
2667 #define IAVF_AQC_SET_RSS_LUT_VSI_ID_MASK        (0x3FF << \
2668                                         IAVF_AQC_SET_RSS_LUT_VSI_ID_SHIFT)
2669         __le16  vsi_id;
2670 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT   0
2671 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_MASK    (0x1 << \
2672                                         IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT)
2673
2674 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_VSI     0
2675 #define IAVF_AQC_SET_RSS_LUT_TABLE_TYPE_PF      1
2676         __le16  flags;
2677         u8      reserved[4];
2678         __le32  addr_high;
2679         __le32  addr_low;
2680 };
2681
2682 IAVF_CHECK_CMD_LENGTH(iavf_aqc_get_set_rss_lut);
2683
2684 /* tunnel key structure 0x0B10 */
2685
2686 struct iavf_aqc_tunnel_key_structure {
2687         u8      key1_off;
2688         u8      key2_off;
2689         u8      key1_len;  /* 0 to 15 */
2690         u8      key2_len;  /* 0 to 15 */
2691         u8      flags;
2692 #define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDE     0x01
2693 /* response flags */
2694 #define IAVF_AQC_TUNNEL_KEY_STRUCT_SUCCESS      0x01
2695 #define IAVF_AQC_TUNNEL_KEY_STRUCT_MODIFIED     0x02
2696 #define IAVF_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN   0x03
2697         u8      network_key_index;
2698 #define IAVF_AQC_NETWORK_KEY_INDEX_VXLAN                0x0
2699 #define IAVF_AQC_NETWORK_KEY_INDEX_NGE                  0x1
2700 #define IAVF_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP      0x2
2701 #define IAVF_AQC_NETWORK_KEY_INDEX_GRE                  0x3
2702         u8      reserved[10];
2703 };
2704
2705 IAVF_CHECK_CMD_LENGTH(iavf_aqc_tunnel_key_structure);
2706
2707 /* OEM mode commands (direct 0xFE0x) */
2708 struct iavf_aqc_oem_param_change {
2709         __le32  param_type;
2710 #define IAVF_AQ_OEM_PARAM_TYPE_PF_CTL   0
2711 #define IAVF_AQ_OEM_PARAM_TYPE_BW_CTL   1
2712 #define IAVF_AQ_OEM_PARAM_MAC           2
2713         __le32  param_value1;
2714         __le16  param_value2;
2715         u8      reserved[6];
2716 };
2717
2718 IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_param_change);
2719
2720 struct iavf_aqc_oem_state_change {
2721         __le32  state;
2722 #define IAVF_AQ_OEM_STATE_LINK_DOWN     0x0
2723 #define IAVF_AQ_OEM_STATE_LINK_UP       0x1
2724         u8      reserved[12];
2725 };
2726
2727 IAVF_CHECK_CMD_LENGTH(iavf_aqc_oem_state_change);
2728
2729 /* Initialize OCSD (0xFE02, direct) */
2730 struct iavf_aqc_opc_oem_ocsd_initialize {
2731         u8 type_status;
2732         u8 reserved1[3];
2733         __le32 ocsd_memory_block_addr_high;
2734         __le32 ocsd_memory_block_addr_low;
2735         __le32 requested_update_interval;
2736 };
2737
2738 IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocsd_initialize);
2739
2740 /* Initialize OCBB  (0xFE03, direct) */
2741 struct iavf_aqc_opc_oem_ocbb_initialize {
2742         u8 type_status;
2743         u8 reserved1[3];
2744         __le32 ocbb_memory_block_addr_high;
2745         __le32 ocbb_memory_block_addr_low;
2746         u8 reserved2[4];
2747 };
2748
2749 IAVF_CHECK_CMD_LENGTH(iavf_aqc_opc_oem_ocbb_initialize);
2750
2751 /* debug commands */
2752
2753 /* get device id (0xFF00) uses the generic structure */
2754
2755 /* set test more (0xFF01, internal) */
2756
2757 struct iavf_acq_set_test_mode {
2758         u8      mode;
2759 #define IAVF_AQ_TEST_PARTIAL    0
2760 #define IAVF_AQ_TEST_FULL       1
2761 #define IAVF_AQ_TEST_NVM        2
2762         u8      reserved[3];
2763         u8      command;
2764 #define IAVF_AQ_TEST_OPEN       0
2765 #define IAVF_AQ_TEST_CLOSE      1
2766 #define IAVF_AQ_TEST_INC        2
2767         u8      reserved2[3];
2768         __le32  address_high;
2769         __le32  address_low;
2770 };
2771
2772 IAVF_CHECK_CMD_LENGTH(iavf_acq_set_test_mode);
2773
2774 /* Debug Read Register command (0xFF03)
2775  * Debug Write Register command (0xFF04)
2776  */
2777 struct iavf_aqc_debug_reg_read_write {
2778         __le32 reserved;
2779         __le32 address;
2780         __le32 value_high;
2781         __le32 value_low;
2782 };
2783
2784 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_reg_read_write);
2785
2786 /* Scatter/gather Reg Read  (indirect 0xFF05)
2787  * Scatter/gather Reg Write (indirect 0xFF06)
2788  */
2789
2790 /* iavf_aq_desc is used for the command */
2791 struct iavf_aqc_debug_reg_sg_element_data {
2792         __le32 address;
2793         __le32 value;
2794 };
2795
2796 /* Debug Modify register (direct 0xFF07) */
2797 struct iavf_aqc_debug_modify_reg {
2798         __le32 address;
2799         __le32 value;
2800         __le32 clear_mask;
2801         __le32 set_mask;
2802 };
2803
2804 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_reg);
2805
2806 /* dump internal data (0xFF08, indirect) */
2807
2808 #define IAVF_AQ_CLUSTER_ID_AUX          0
2809 #define IAVF_AQ_CLUSTER_ID_SWITCH_FLU   1
2810 #define IAVF_AQ_CLUSTER_ID_TXSCHED      2
2811 #define IAVF_AQ_CLUSTER_ID_HMC          3
2812 #define IAVF_AQ_CLUSTER_ID_MAC0         4
2813 #define IAVF_AQ_CLUSTER_ID_MAC1         5
2814 #define IAVF_AQ_CLUSTER_ID_MAC2         6
2815 #define IAVF_AQ_CLUSTER_ID_MAC3         7
2816 #define IAVF_AQ_CLUSTER_ID_DCB          8
2817 #define IAVF_AQ_CLUSTER_ID_EMP_MEM      9
2818 #define IAVF_AQ_CLUSTER_ID_PKT_BUF      10
2819 #define IAVF_AQ_CLUSTER_ID_ALTRAM       11
2820
2821 struct iavf_aqc_debug_dump_internals {
2822         u8      cluster_id;
2823         u8      table_id;
2824         __le16  data_size;
2825         __le32  idx;
2826         __le32  address_high;
2827         __le32  address_low;
2828 };
2829
2830 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_dump_internals);
2831
2832 struct iavf_aqc_debug_modify_internals {
2833         u8      cluster_id;
2834         u8      cluster_specific_params[7];
2835         __le32  address_high;
2836         __le32  address_low;
2837 };
2838
2839 IAVF_CHECK_CMD_LENGTH(iavf_aqc_debug_modify_internals);
2840
2841 #endif /* _IAVF_ADMINQ_CMD_H_ */