drivers/net/iavf/base/iavf_type.h

   1 /*******************************************************************************
   2
   3 Copyright (c) 2013 - 2015, Intel Corporation
   4 All rights reserved.
   5
   6 Redistribution and use in source and binary forms, with or without
   7 modification, are permitted provided that the following conditions are met:
   8
   9  1. Redistributions of source code must retain the above copyright notice,
  10     this list of conditions and the following disclaimer.
  11
  12  2. Redistributions in binary form must reproduce the above copyright
  13     notice, this list of conditions and the following disclaimer in the
  14     documentation and/or other materials provided with the distribution.
  15
  16  3. Neither the name of the Intel Corporation nor the names of its
  17     contributors may be used to endorse or promote products derived from
  18     this software without specific prior written permission.
  19
  20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  30 POSSIBILITY OF SUCH DAMAGE.
  31
  32 ***************************************************************************/
  33
  34 #ifndef _IAVF_TYPE_H_
  35 #define _IAVF_TYPE_H_
  36
  37 #include "iavf_status.h"
  38 #include "iavf_osdep.h"
  39 #include "iavf_register.h"
  40 #include "iavf_adminq.h"
  41 #include "iavf_hmc.h"
  42 #include "iavf_lan_hmc.h"
  43 #include "iavf_devids.h"
  44
  45 #define UNREFERENCED_XPARAMETER
  46 #define UNREFERENCED_1PARAMETER(_p) (_p);
  47 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  48 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  49 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  50 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  51
  52 #ifndef LINUX_MACROS
  53 #ifndef BIT
  54 #define BIT(a) (1UL << (a))
  55 #endif /* BIT */
  56 #ifndef BIT_ULL
  57 #define BIT_ULL(a) (1ULL << (a))
  58 #endif /* BIT_ULL */
  59 #endif /* LINUX_MACROS */
  60
  61 #ifndef IAVF_MASK
  62 /* IAVF_MASK is a macro used on 32 bit registers */
  63 #define IAVF_MASK(mask, shift) (mask << shift)
  64 #endif
  65
  66 #define IAVF_MAX_PF                     16
  67 #define IAVF_MAX_PF_VSI                 64
  68 #define IAVF_MAX_PF_QP                  128
  69 #define IAVF_MAX_VSI_QP                 16
  70 #define IAVF_MAX_VF_VSI                 3
  71 #define IAVF_MAX_CHAINED_RX_BUFFERS     5
  72 #define IAVF_MAX_PF_UDP_OFFLOAD_PORTS   16
  73
  74 /* something less than 1 minute */
  75 #define IAVF_HEARTBEAT_TIMEOUT          (HZ * 50)
  76
  77 /* Max default timeout in ms, */
  78 #define IAVF_MAX_NVM_TIMEOUT            18000
  79
  80 /* Max timeout in ms for the phy to respond */
  81 #define IAVF_MAX_PHY_TIMEOUT            500
  82
  83 /* Check whether address is multicast. */
  84 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  85
  86 /* Check whether an address is broadcast. */
  87 #define IAVF_IS_BROADCAST(address)      \
  88         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  89         (((u8 *)(address))[1] == ((u8)0xff)))
  90
  91 /* Switch from ms to the 1usec global time (this is the GTIME resolution) */
  92 #define IAVF_MS_TO_GTIME(time)          ((time) * 1000)
  93
  94 /* forward declaration */
  95 struct iavf_hw;
  96 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
  97
  98 #ifndef ETH_ALEN
  99 #define ETH_ALEN        6
 100 #endif
 101 /* Data type manipulation macros. */
 102 #define IAVF_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
 103 #define IAVF_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
 104
 105 #define IAVF_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
 106 #define IAVF_LO_WORD(x)         ((u16)((x) & 0xFFFF))
 107
 108 #define IAVF_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
 109 #define IAVF_LO_BYTE(x)         ((u8)((x) & 0xFF))
 110
 111 /* Number of Transmit Descriptors must be a multiple of 8. */
 112 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8
 113 /* Number of Receive Descriptors must be a multiple of 32 if
 114  * the number of descriptors is greater than 32.
 115  */
 116 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32
 117
 118 #define IAVF_DESC_UNUSED(R)     \
 119         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
 120         (R)->next_to_clean - (R)->next_to_use - 1)
 121
 122 /* bitfields for Tx queue mapping in QTX_CTL */
 123 #define IAVF_QTX_CTL_VF_QUEUE   0x0
 124 #define IAVF_QTX_CTL_VM_QUEUE   0x1
 125 #define IAVF_QTX_CTL_PF_QUEUE   0x2
 126
 127 /* debug masks - set these bits in hw->debug_mask to control output */
 128 enum iavf_debug_mask {
 129         IAVF_DEBUG_INIT                 = 0x00000001,
 130         IAVF_DEBUG_RELEASE              = 0x00000002,
 131
 132         IAVF_DEBUG_LINK                 = 0x00000010,
 133         IAVF_DEBUG_PHY                  = 0x00000020,
 134         IAVF_DEBUG_HMC                  = 0x00000040,
 135         IAVF_DEBUG_NVM                  = 0x00000080,
 136         IAVF_DEBUG_LAN                  = 0x00000100,
 137         IAVF_DEBUG_FLOW                 = 0x00000200,
 138         IAVF_DEBUG_DCB                  = 0x00000400,
 139         IAVF_DEBUG_DIAG                 = 0x00000800,
 140         IAVF_DEBUG_FD                   = 0x00001000,
 141         IAVF_DEBUG_PACKAGE              = 0x00002000,
 142
 143         IAVF_DEBUG_AQ_MESSAGE           = 0x01000000,
 144         IAVF_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
 145         IAVF_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
 146         IAVF_DEBUG_AQ_COMMAND           = 0x06000000,
 147         IAVF_DEBUG_AQ                   = 0x0F000000,
 148
 149         IAVF_DEBUG_USER                 = 0xF0000000,
 150
 151         IAVF_DEBUG_ALL                  = 0xFFFFFFFF
 152 };
 153
 154 /* PCI Bus Info */
 155 #define IAVF_PCI_LINK_STATUS            0xB2
 156 #define IAVF_PCI_LINK_WIDTH             0x3F0
 157 #define IAVF_PCI_LINK_WIDTH_1           0x10
 158 #define IAVF_PCI_LINK_WIDTH_2           0x20
 159 #define IAVF_PCI_LINK_WIDTH_4           0x40
 160 #define IAVF_PCI_LINK_WIDTH_8           0x80
 161 #define IAVF_PCI_LINK_SPEED             0xF
 162 #define IAVF_PCI_LINK_SPEED_2500        0x1
 163 #define IAVF_PCI_LINK_SPEED_5000        0x2
 164 #define IAVF_PCI_LINK_SPEED_8000        0x3
 165
 166 #define IAVF_MDIO_CLAUSE22_STCODE_MASK  IAVF_MASK(1, \
 167                                                   IAVF_GLGEN_MSCA_STCODE_SHIFT)
 168 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK    IAVF_MASK(1, \
 169                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 170 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK     IAVF_MASK(2, \
 171                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 172
 173 #define IAVF_MDIO_CLAUSE45_STCODE_MASK  IAVF_MASK(0, \
 174                                                   IAVF_GLGEN_MSCA_STCODE_SHIFT)
 175 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  IAVF_MASK(0, \
 176                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 177 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK    IAVF_MASK(1, \
 178                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 179 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    IAVF_MASK(2, \
 180                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 181 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK     IAVF_MASK(3, \
 182                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 183
 184 #define IAVF_PHY_COM_REG_PAGE                   0x1E
 185 #define IAVF_PHY_LED_LINK_MODE_MASK             0xF0
 186 #define IAVF_PHY_LED_MANUAL_ON                  0x100
 187 #define IAVF_PHY_LED_PROV_REG_1                 0xC430
 188 #define IAVF_PHY_LED_MODE_MASK                  0xFFFF
 189 #define IAVF_PHY_LED_MODE_ORIG                  0x80000000
 190
 191 /* Memory types */
 192 enum iavf_memset_type {
 193         IAVF_NONDMA_MEM = 0,
 194         IAVF_DMA_MEM
 195 };
 196
 197 /* Memcpy types */
 198 enum iavf_memcpy_type {
 199         IAVF_NONDMA_TO_NONDMA = 0,
 200         IAVF_NONDMA_TO_DMA,
 201         IAVF_DMA_TO_DMA,
 202         IAVF_DMA_TO_NONDMA
 203 };
 204
 205 /* These are structs for managing the hardware information and the operations.
 206  * The structures of function pointers are filled out at init time when we
 207  * know for sure exactly which hardware we're working with.  This gives us the
 208  * flexibility of using the same main driver code but adapting to slightly
 209  * different hardware needs as new parts are developed.  For this architecture,
 210  * the Firmware and AdminQ are intended to insulate the driver from most of the
 211  * future changes, but these structures will also do part of the job.
 212  */
 213 enum iavf_mac_type {
 214         IAVF_MAC_UNKNOWN = 0,
 215         IAVF_MAC_XL710,
 216         IAVF_MAC_VF,
 217         IAVF_MAC_X722,
 218         IAVF_MAC_X722_VF,
 219         IAVF_MAC_GENERIC,
 220 };
 221
 222 enum iavf_media_type {
 223         IAVF_MEDIA_TYPE_UNKNOWN = 0,
 224         IAVF_MEDIA_TYPE_FIBER,
 225         IAVF_MEDIA_TYPE_BASET,
 226         IAVF_MEDIA_TYPE_BACKPLANE,
 227         IAVF_MEDIA_TYPE_CX4,
 228         IAVF_MEDIA_TYPE_DA,
 229         IAVF_MEDIA_TYPE_VIRTUAL
 230 };
 231
 232 enum iavf_fc_mode {
 233         IAVF_FC_NONE = 0,
 234         IAVF_FC_RX_PAUSE,
 235         IAVF_FC_TX_PAUSE,
 236         IAVF_FC_FULL,
 237         IAVF_FC_PFC,
 238         IAVF_FC_DEFAULT
 239 };
 240
 241 enum iavf_set_fc_aq_failures {
 242         IAVF_SET_FC_AQ_FAIL_NONE = 0,
 243         IAVF_SET_FC_AQ_FAIL_GET = 1,
 244         IAVF_SET_FC_AQ_FAIL_SET = 2,
 245         IAVF_SET_FC_AQ_FAIL_UPDATE = 4,
 246         IAVF_SET_FC_AQ_FAIL_SET_UPDATE = 6
 247 };
 248
 249 enum iavf_vsi_type {
 250         IAVF_VSI_MAIN   = 0,
 251         IAVF_VSI_VMDQ1  = 1,
 252         IAVF_VSI_VMDQ2  = 2,
 253         IAVF_VSI_CTRL   = 3,
 254         IAVF_VSI_FCOE   = 4,
 255         IAVF_VSI_MIRROR = 5,
 256         IAVF_VSI_SRIOV  = 6,
 257         IAVF_VSI_FDIR   = 7,
 258         IAVF_VSI_TYPE_UNKNOWN
 259 };
 260
 261 enum iavf_queue_type {
 262         IAVF_QUEUE_TYPE_RX = 0,
 263         IAVF_QUEUE_TYPE_TX,
 264         IAVF_QUEUE_TYPE_PE_CEQ,
 265         IAVF_QUEUE_TYPE_UNKNOWN
 266 };
 267
 268 struct iavf_link_status {
 269         enum iavf_aq_phy_type phy_type;
 270         enum iavf_aq_link_speed link_speed;
 271         u8 link_info;
 272         u8 an_info;
 273         u8 req_fec_info;
 274         u8 fec_info;
 275         u8 ext_info;
 276         u8 loopback;
 277         /* is Link Status Event notification to SW enabled */
 278         bool lse_enable;
 279         u16 max_frame_size;
 280         bool crc_enable;
 281         u8 pacing;
 282         u8 requested_speeds;
 283         u8 module_type[3];
 284         /* 1st byte: module identifier */
 285 #define IAVF_MODULE_TYPE_SFP            0x03
 286 #define IAVF_MODULE_TYPE_QSFP           0x0D
 287         /* 2nd byte: ethernet compliance codes for 10/40G */
 288 #define IAVF_MODULE_TYPE_40G_ACTIVE     0x01
 289 #define IAVF_MODULE_TYPE_40G_LR4        0x02
 290 #define IAVF_MODULE_TYPE_40G_SR4        0x04
 291 #define IAVF_MODULE_TYPE_40G_CR4        0x08
 292 #define IAVF_MODULE_TYPE_10G_BASE_SR    0x10
 293 #define IAVF_MODULE_TYPE_10G_BASE_LR    0x20
 294 #define IAVF_MODULE_TYPE_10G_BASE_LRM   0x40
 295 #define IAVF_MODULE_TYPE_10G_BASE_ER    0x80
 296         /* 3rd byte: ethernet compliance codes for 1G */
 297 #define IAVF_MODULE_TYPE_1000BASE_SX    0x01
 298 #define IAVF_MODULE_TYPE_1000BASE_LX    0x02
 299 #define IAVF_MODULE_TYPE_1000BASE_CX    0x04
 300 #define IAVF_MODULE_TYPE_1000BASE_T     0x08
 301 };
 302
 303 struct iavf_phy_info {
 304         struct iavf_link_status link_info;
 305         struct iavf_link_status link_info_old;
 306         bool get_link_info;
 307         enum iavf_media_type media_type;
 308         /* all the phy types the NVM is capable of */
 309         u64 phy_types;
 310 };
 311
 312 #define IAVF_CAP_PHY_TYPE_SGMII BIT_ULL(IAVF_PHY_TYPE_SGMII)
 313 #define IAVF_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(IAVF_PHY_TYPE_1000BASE_KX)
 314 #define IAVF_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(IAVF_PHY_TYPE_10GBASE_KX4)
 315 #define IAVF_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(IAVF_PHY_TYPE_10GBASE_KR)
 316 #define IAVF_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_KR4)
 317 #define IAVF_CAP_PHY_TYPE_XAUI BIT_ULL(IAVF_PHY_TYPE_XAUI)
 318 #define IAVF_CAP_PHY_TYPE_XFI BIT_ULL(IAVF_PHY_TYPE_XFI)
 319 #define IAVF_CAP_PHY_TYPE_SFI BIT_ULL(IAVF_PHY_TYPE_SFI)
 320 #define IAVF_CAP_PHY_TYPE_XLAUI BIT_ULL(IAVF_PHY_TYPE_XLAUI)
 321 #define IAVF_CAP_PHY_TYPE_XLPPI BIT_ULL(IAVF_PHY_TYPE_XLPPI)
 322 #define IAVF_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4_CU)
 323 #define IAVF_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1_CU)
 324 #define IAVF_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_10GBASE_AOC)
 325 #define IAVF_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_40GBASE_AOC)
 326 #define IAVF_CAP_PHY_TYPE_100BASE_TX BIT_ULL(IAVF_PHY_TYPE_100BASE_TX)
 327 #define IAVF_CAP_PHY_TYPE_1000BASE_T BIT_ULL(IAVF_PHY_TYPE_1000BASE_T)
 328 #define IAVF_CAP_PHY_TYPE_10GBASE_T BIT_ULL(IAVF_PHY_TYPE_10GBASE_T)
 329 #define IAVF_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(IAVF_PHY_TYPE_10GBASE_SR)
 330 #define IAVF_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(IAVF_PHY_TYPE_10GBASE_LR)
 331 #define IAVF_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(IAVF_PHY_TYPE_10GBASE_SFPP_CU)
 332 #define IAVF_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(IAVF_PHY_TYPE_10GBASE_CR1)
 333 #define IAVF_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_CR4)
 334 #define IAVF_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_SR4)
 335 #define IAVF_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(IAVF_PHY_TYPE_40GBASE_LR4)
 336 #define IAVF_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(IAVF_PHY_TYPE_1000BASE_SX)
 337 #define IAVF_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(IAVF_PHY_TYPE_1000BASE_LX)
 338 #define IAVF_CAP_PHY_TYPE_1000BASE_T_OPTICAL \
 339                                 BIT_ULL(IAVF_PHY_TYPE_1000BASE_T_OPTICAL)
 340 #define IAVF_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(IAVF_PHY_TYPE_20GBASE_KR2)
 341 /*
 342  * Defining the macro IAVF_TYPE_OFFSET to implement a bit shift for some
 343  * PHY types. There is an unused bit (31) in the IAVF_CAP_PHY_TYPE_* bit
 344  * fields but no corresponding gap in the iavf_aq_phy_type enumeration. So,
 345  * a shift is needed to adjust for this with values larger than 31. The
 346  * only affected values are IAVF_PHY_TYPE_25GBASE_*.
 347  */
 348 #define IAVF_PHY_TYPE_OFFSET 1
 349 #define IAVF_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(IAVF_PHY_TYPE_25GBASE_KR + \
 350                                              IAVF_PHY_TYPE_OFFSET)
 351 #define IAVF_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(IAVF_PHY_TYPE_25GBASE_CR + \
 352                                              IAVF_PHY_TYPE_OFFSET)
 353 #define IAVF_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(IAVF_PHY_TYPE_25GBASE_SR + \
 354                                              IAVF_PHY_TYPE_OFFSET)
 355 #define IAVF_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(IAVF_PHY_TYPE_25GBASE_LR + \
 356                                              IAVF_PHY_TYPE_OFFSET)
 357 #define IAVF_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(IAVF_PHY_TYPE_25GBASE_AOC + \
 358                                              IAVF_PHY_TYPE_OFFSET)
 359 #define IAVF_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(IAVF_PHY_TYPE_25GBASE_ACC + \
 360                                              IAVF_PHY_TYPE_OFFSET)
 361 #define IAVF_HW_CAP_MAX_GPIO                    30
 362 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO         0
 363 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C          1
 364
 365 enum iavf_acpi_programming_method {
 366         IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 367         IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 368 };
 369
 370 #define IAVF_WOL_SUPPORT_MASK                   0x1
 371 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK       0x2
 372 #define IAVF_PROXY_SUPPORT_MASK                 0x4
 373
 374 /* Capabilities of a PF or a VF or the whole device */
 375 struct iavf_hw_capabilities {
 376         u32  switch_mode;
 377 #define IAVF_NVM_IMAGE_TYPE_EVB         0x0
 378 #define IAVF_NVM_IMAGE_TYPE_CLOUD       0x2
 379 #define IAVF_NVM_IMAGE_TYPE_UDP_CLOUD   0x3
 380
 381         u32  management_mode;
 382         u32  mng_protocols_over_mctp;
 383 #define IAVF_MNG_PROTOCOL_PLDM          0x2
 384 #define IAVF_MNG_PROTOCOL_OEM_COMMANDS  0x4
 385 #define IAVF_MNG_PROTOCOL_NCSI          0x8
 386         u32  npar_enable;
 387         u32  os2bmc;
 388         u32  valid_functions;
 389         bool sr_iov_1_1;
 390         bool vmdq;
 391         bool evb_802_1_qbg; /* Edge Virtual Bridging */
 392         bool evb_802_1_qbh; /* Bridge Port Extension */
 393         bool dcb;
 394         bool fcoe;
 395         bool iscsi; /* Indicates iSCSI enabled */
 396         bool flex10_enable;
 397         bool flex10_capable;
 398         u32  flex10_mode;
 399 #define IAVF_FLEX10_MODE_UNKNOWN        0x0
 400 #define IAVF_FLEX10_MODE_DCC            0x1
 401 #define IAVF_FLEX10_MODE_DCI            0x2
 402
 403         u32 flex10_status;
 404 #define IAVF_FLEX10_STATUS_DCC_ERROR    0x1
 405 #define IAVF_FLEX10_STATUS_VC_MODE      0x2
 406
 407         bool sec_rev_disabled;
 408         bool update_disabled;
 409 #define IAVF_NVM_MGMT_SEC_REV_DISABLED  0x1
 410 #define IAVF_NVM_MGMT_UPDATE_DISABLED   0x2
 411
 412         bool mgmt_cem;
 413         bool ieee_1588;
 414         bool iwarp;
 415         bool fd;
 416         u32 fd_filters_guaranteed;
 417         u32 fd_filters_best_effort;
 418         bool rss;
 419         u32 rss_table_size;
 420         u32 rss_table_entry_width;
 421         bool led[IAVF_HW_CAP_MAX_GPIO];
 422         bool sdp[IAVF_HW_CAP_MAX_GPIO];
 423         u32 nvm_image_type;
 424         u32 num_flow_director_filters;
 425         u32 num_vfs;
 426         u32 vf_base_id;
 427         u32 num_vsis;
 428         u32 num_rx_qp;
 429         u32 num_tx_qp;
 430         u32 base_queue;
 431         u32 num_msix_vectors;
 432         u32 num_msix_vectors_vf;
 433         u32 led_pin_num;
 434         u32 sdp_pin_num;
 435         u32 mdio_port_num;
 436         u32 mdio_port_mode;
 437         u8 rx_buf_chain_len;
 438         u32 enabled_tcmap;
 439         u32 maxtc;
 440         u64 wr_csr_prot;
 441         bool apm_wol_support;
 442         enum iavf_acpi_programming_method acpi_prog_method;
 443         bool proxy_support;
 444 };
 445
 446 struct iavf_mac_info {
 447         enum iavf_mac_type type;
 448         u8 addr[ETH_ALEN];
 449         u8 perm_addr[ETH_ALEN];
 450         u8 san_addr[ETH_ALEN];
 451         u8 port_addr[ETH_ALEN];
 452         u16 max_fcoeq;
 453 };
 454
 455 enum iavf_aq_resources_ids {
 456         IAVF_NVM_RESOURCE_ID = 1
 457 };
 458
 459 enum iavf_aq_resource_access_type {
 460         IAVF_RESOURCE_READ = 1,
 461         IAVF_RESOURCE_WRITE
 462 };
 463
 464 struct iavf_nvm_info {
 465         u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
 466         u32 timeout;              /* [ms] */
 467         u16 sr_size;              /* Shadow RAM size in words */
 468         bool blank_nvm_mode;      /* is NVM empty (no FW present)*/
 469         u16 version;              /* NVM package version */
 470         u32 eetrack;              /* NVM data version */
 471         u32 oem_ver;              /* OEM version info */
 472 };
 473
 474 /* definitions used in NVM update support */
 475
 476 enum iavf_nvmupd_cmd {
 477         IAVF_NVMUPD_INVALID,
 478         IAVF_NVMUPD_READ_CON,
 479         IAVF_NVMUPD_READ_SNT,
 480         IAVF_NVMUPD_READ_LCB,
 481         IAVF_NVMUPD_READ_SA,
 482         IAVF_NVMUPD_WRITE_ERA,
 483         IAVF_NVMUPD_WRITE_CON,
 484         IAVF_NVMUPD_WRITE_SNT,
 485         IAVF_NVMUPD_WRITE_LCB,
 486         IAVF_NVMUPD_WRITE_SA,
 487         IAVF_NVMUPD_CSUM_CON,
 488         IAVF_NVMUPD_CSUM_SA,
 489         IAVF_NVMUPD_CSUM_LCB,
 490         IAVF_NVMUPD_STATUS,
 491         IAVF_NVMUPD_EXEC_AQ,
 492         IAVF_NVMUPD_GET_AQ_RESULT,
 493         IAVF_NVMUPD_GET_AQ_EVENT,
 494 };
 495
 496 enum iavf_nvmupd_state {
 497         IAVF_NVMUPD_STATE_INIT,
 498         IAVF_NVMUPD_STATE_READING,
 499         IAVF_NVMUPD_STATE_WRITING,
 500         IAVF_NVMUPD_STATE_INIT_WAIT,
 501         IAVF_NVMUPD_STATE_WRITE_WAIT,
 502         IAVF_NVMUPD_STATE_ERROR
 503 };
 504
 505 /* nvm_access definition and its masks/shifts need to be accessible to
 506  * application, core driver, and shared code.  Where is the right file?
 507  */
 508 #define IAVF_NVM_READ   0xB
 509 #define IAVF_NVM_WRITE  0xC
 510
 511 #define IAVF_NVM_MOD_PNT_MASK 0xFF
 512
 513 #define IAVF_NVM_TRANS_SHIFT                    8
 514 #define IAVF_NVM_TRANS_MASK                     (0xf << IAVF_NVM_TRANS_SHIFT)
 515 #define IAVF_NVM_PRESERVATION_FLAGS_SHIFT       12
 516 #define IAVF_NVM_PRESERVATION_FLAGS_MASK \
 517                                 (0x3 << IAVF_NVM_PRESERVATION_FLAGS_SHIFT)
 518 #define IAVF_NVM_PRESERVATION_FLAGS_SELECTED    0x01
 519 #define IAVF_NVM_PRESERVATION_FLAGS_ALL         0x02
 520 #define IAVF_NVM_CON                            0x0
 521 #define IAVF_NVM_SNT                            0x1
 522 #define IAVF_NVM_LCB                            0x2
 523 #define IAVF_NVM_SA                             (IAVF_NVM_SNT | IAVF_NVM_LCB)
 524 #define IAVF_NVM_ERA                            0x4
 525 #define IAVF_NVM_CSUM                           0x8
 526 #define IAVF_NVM_AQE                            0xe
 527 #define IAVF_NVM_EXEC                           0xf
 528
 529 #define IAVF_NVM_ADAPT_SHIFT    16
 530 #define IAVF_NVM_ADAPT_MASK     (0xffffULL << IAVF_NVM_ADAPT_SHIFT)
 531
 532 #define IAVF_NVMUPD_MAX_DATA    4096
 533 #define IAVF_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
 534
 535 struct iavf_nvm_access {
 536         u32 command;
 537         u32 config;
 538         u32 offset;     /* in bytes */
 539         u32 data_size;  /* in bytes */
 540         u8 data[1];
 541 };
 542
 543 /* (Q)SFP module access definitions */
 544 #define IAVF_I2C_EEPROM_DEV_ADDR        0xA0
 545 #define IAVF_I2C_EEPROM_DEV_ADDR2       0xA2
 546 #define IAVF_MODULE_TYPE_ADDR           0x00
 547 #define IAVF_MODULE_REVISION_ADDR       0x01
 548 #define IAVF_MODULE_SFF_8472_COMP       0x5E
 549 #define IAVF_MODULE_SFF_8472_SWAP       0x5C
 550 #define IAVF_MODULE_SFF_ADDR_MODE       0x04
 551 #define IAVF_MODULE_SFF_DIAG_CAPAB      0x40
 552 #define IAVF_MODULE_TYPE_QSFP_PLUS      0x0D
 553 #define IAVF_MODULE_TYPE_QSFP28         0x11
 554 #define IAVF_MODULE_QSFP_MAX_LEN        640
 555
 556 /* PCI bus types */
 557 enum iavf_bus_type {
 558         iavf_bus_type_unknown = 0,
 559         iavf_bus_type_pci,
 560         iavf_bus_type_pcix,
 561         iavf_bus_type_pci_express,
 562         iavf_bus_type_reserved
 563 };
 564
 565 /* PCI bus speeds */
 566 enum iavf_bus_speed {
 567         iavf_bus_speed_unknown  = 0,
 568         iavf_bus_speed_33       = 33,
 569         iavf_bus_speed_66       = 66,
 570         iavf_bus_speed_100      = 100,
 571         iavf_bus_speed_120      = 120,
 572         iavf_bus_speed_133      = 133,
 573         iavf_bus_speed_2500     = 2500,
 574         iavf_bus_speed_5000     = 5000,
 575         iavf_bus_speed_8000     = 8000,
 576         iavf_bus_speed_reserved
 577 };
 578
 579 /* PCI bus widths */
 580 enum iavf_bus_width {
 581         iavf_bus_width_unknown  = 0,
 582         iavf_bus_width_pcie_x1  = 1,
 583         iavf_bus_width_pcie_x2  = 2,
 584         iavf_bus_width_pcie_x4  = 4,
 585         iavf_bus_width_pcie_x8  = 8,
 586         iavf_bus_width_32       = 32,
 587         iavf_bus_width_64       = 64,
 588         iavf_bus_width_reserved
 589 };
 590
 591 /* Bus parameters */
 592 struct iavf_bus_info {
 593         enum iavf_bus_speed speed;
 594         enum iavf_bus_width width;
 595         enum iavf_bus_type type;
 596
 597         u16 func;
 598         u16 device;
 599         u16 lan_id;
 600         u16 bus_id;
 601 };
 602
 603 /* Flow control (FC) parameters */
 604 struct iavf_fc_info {
 605         enum iavf_fc_mode current_mode; /* FC mode in effect */
 606         enum iavf_fc_mode requested_mode; /* FC mode requested by caller */
 607 };
 608
 609 #define IAVF_MAX_TRAFFIC_CLASS          8
 610 #define IAVF_MAX_USER_PRIORITY          8
 611 #define IAVF_DCBX_MAX_APPS              32
 612 #define IAVF_LLDPDU_SIZE                1500
 613 #define IAVF_TLV_STATUS_OPER            0x1
 614 #define IAVF_TLV_STATUS_SYNC            0x2
 615 #define IAVF_TLV_STATUS_ERR             0x4
 616 #define IAVF_CEE_OPER_MAX_APPS          3
 617 #define IAVF_APP_PROTOID_FCOE           0x8906
 618 #define IAVF_APP_PROTOID_ISCSI          0x0cbc
 619 #define IAVF_APP_PROTOID_FIP            0x8914
 620 #define IAVF_APP_SEL_ETHTYPE            0x1
 621 #define IAVF_APP_SEL_TCPIP              0x2
 622 #define IAVF_CEE_APP_SEL_ETHTYPE        0x0
 623 #define IAVF_CEE_APP_SEL_TCPIP          0x1
 624
 625 /* CEE or IEEE 802.1Qaz ETS Configuration data */
 626 struct iavf_dcb_ets_config {
 627         u8 willing;
 628         u8 cbs;
 629         u8 maxtcs;
 630         u8 prioritytable[IAVF_MAX_TRAFFIC_CLASS];
 631         u8 tcbwtable[IAVF_MAX_TRAFFIC_CLASS];
 632         u8 tsatable[IAVF_MAX_TRAFFIC_CLASS];
 633 };
 634
 635 /* CEE or IEEE 802.1Qaz PFC Configuration data */
 636 struct iavf_dcb_pfc_config {
 637         u8 willing;
 638         u8 mbc;
 639         u8 pfccap;
 640         u8 pfcenable;
 641 };
 642
 643 /* CEE or IEEE 802.1Qaz Application Priority data */
 644 struct iavf_dcb_app_priority_table {
 645         u8  priority;
 646         u8  selector;
 647         u16 protocolid;
 648 };
 649
 650 struct iavf_dcbx_config {
 651         u8  dcbx_mode;
 652 #define IAVF_DCBX_MODE_CEE      0x1
 653 #define IAVF_DCBX_MODE_IEEE     0x2
 654         u8  app_mode;
 655 #define IAVF_DCBX_APPS_NON_WILLING      0x1
 656         u32 numapps;
 657         u32 tlv_status; /* CEE mode TLV status */
 658         struct iavf_dcb_ets_config etscfg;
 659         struct iavf_dcb_ets_config etsrec;
 660         struct iavf_dcb_pfc_config pfc;
 661         struct iavf_dcb_app_priority_table app[IAVF_DCBX_MAX_APPS];
 662 };
 663
 664 /* Port hardware description */
 665 struct iavf_hw {
 666         u8 *hw_addr;
 667         void *back;
 668
 669         /* subsystem structs */
 670         struct iavf_phy_info phy;
 671         struct iavf_mac_info mac;
 672         struct iavf_bus_info bus;
 673         struct iavf_nvm_info nvm;
 674         struct iavf_fc_info fc;
 675
 676         /* pci info */
 677         u16 device_id;
 678         u16 vendor_id;
 679         u16 subsystem_device_id;
 680         u16 subsystem_vendor_id;
 681         u8 revision_id;
 682         u8 port;
 683         bool adapter_stopped;
 684
 685         /* capabilities for entire device and PCI func */
 686         struct iavf_hw_capabilities dev_caps;
 687         struct iavf_hw_capabilities func_caps;
 688
 689         /* Flow Director shared filter space */
 690         u16 fdir_shared_filter_count;
 691
 692         /* device profile info */
 693         u8  pf_id;
 694         u16 main_vsi_seid;
 695
 696         /* for multi-function MACs */
 697         u16 partition_id;
 698         u16 num_partitions;
 699         u16 num_ports;
 700
 701         /* Closest numa node to the device */
 702         u16 numa_node;
 703
 704         /* Admin Queue info */
 705         struct iavf_adminq_info aq;
 706
 707         /* state of nvm update process */
 708         enum iavf_nvmupd_state nvmupd_state;
 709         struct iavf_aq_desc nvm_wb_desc;
 710         struct iavf_aq_desc nvm_aq_event_desc;
 711         struct iavf_virt_mem nvm_buff;
 712         bool nvm_release_on_done;
 713         u16 nvm_wait_opcode;
 714
 715         /* HMC info */
 716         struct iavf_hmc_info hmc; /* HMC info struct */
 717
 718         /* LLDP/DCBX Status */
 719         u16 dcbx_status;
 720
 721         /* DCBX info */
 722         struct iavf_dcbx_config local_dcbx_config; /* Oper/Local Cfg */
 723         struct iavf_dcbx_config remote_dcbx_config; /* Peer Cfg */
 724         struct iavf_dcbx_config desired_dcbx_config; /* CEE Desired Cfg */
 725
 726         /* WoL and proxy support */
 727         u16 num_wol_proxy_filters;
 728         u16 wol_proxy_vsi_seid;
 729
 730 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 731 #define IAVF_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 732 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 733 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 734         u64 flags;
 735
 736         /* Used in set switch config AQ command */
 737         u16 switch_tag;
 738         u16 first_tag;
 739         u16 second_tag;
 740
 741         /* debug mask */
 742         u32 debug_mask;
 743         char err_str[16];
 744 };
 745
 746 STATIC INLINE bool iavf_is_vf(struct iavf_hw *hw)
 747 {
 748         return (hw->mac.type == IAVF_MAC_VF ||
 749                 hw->mac.type == IAVF_MAC_X722_VF);
 750 }
 751
 752 struct iavf_driver_version {
 753         u8 major_version;
 754         u8 minor_version;
 755         u8 build_version;
 756         u8 subbuild_version;
 757         u8 driver_string[32];
 758 };
 759
 760 /* RX Descriptors */
 761 union iavf_16byte_rx_desc {
 762         struct {
 763                 __le64 pkt_addr; /* Packet buffer address */
 764                 __le64 hdr_addr; /* Header buffer address */
 765         } read;
 766         struct {
 767                 struct {
 768                         struct {
 769                                 union {
 770                                         __le16 mirroring_status;
 771                                         __le16 fcoe_ctx_id;
 772                                 } mirr_fcoe;
 773                                 __le16 l2tag1;
 774                         } lo_dword;
 775                         union {
 776                                 __le32 rss; /* RSS Hash */
 777                                 __le32 fd_id; /* Flow director filter id */
 778                                 __le32 fcoe_param; /* FCoE DDP Context id */
 779                         } hi_dword;
 780                 } qword0;
 781                 struct {
 782                         /* ext status/error/pktype/length */
 783                         __le64 status_error_len;
 784                 } qword1;
 785         } wb;  /* writeback */
 786 };
 787
 788 union iavf_32byte_rx_desc {
 789         struct {
 790                 __le64  pkt_addr; /* Packet buffer address */
 791                 __le64  hdr_addr; /* Header buffer address */
 792                         /* bit 0 of hdr_buffer_addr is DD bit */
 793                 __le64  rsvd1;
 794                 __le64  rsvd2;
 795         } read;
 796         struct {
 797                 struct {
 798                         struct {
 799                                 union {
 800                                         __le16 mirroring_status;
 801                                         __le16 fcoe_ctx_id;
 802                                 } mirr_fcoe;
 803                                 __le16 l2tag1;
 804                         } lo_dword;
 805                         union {
 806                                 __le32 rss; /* RSS Hash */
 807                                 __le32 fcoe_param; /* FCoE DDP Context id */
 808                                 /* Flow director filter id in case of
 809                                  * Programming status desc WB
 810                                  */
 811                                 __le32 fd_id;
 812                         } hi_dword;
 813                 } qword0;
 814                 struct {
 815                         /* status/error/pktype/length */
 816                         __le64 status_error_len;
 817                 } qword1;
 818                 struct {
 819                         __le16 ext_status; /* extended status */
 820                         __le16 rsvd;
 821                         __le16 l2tag2_1;
 822                         __le16 l2tag2_2;
 823                 } qword2;
 824                 struct {
 825                         union {
 826                                 __le32 flex_bytes_lo;
 827                                 __le32 pe_status;
 828                         } lo_dword;
 829                         union {
 830                                 __le32 flex_bytes_hi;
 831                                 __le32 fd_id;
 832                         } hi_dword;
 833                 } qword3;
 834         } wb;  /* writeback */
 835 };
 836
 837 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT        8
 838 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 839                                          IAVF_RXD_QW0_MIRROR_STATUS_SHIFT)
 840 #define IAVF_RXD_QW0_FCOEINDX_SHIFT     0
 841 #define IAVF_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 842                                          IAVF_RXD_QW0_FCOEINDX_SHIFT)
 843
 844 enum iavf_rx_desc_status_bits {
 845         /* Note: These are predefined bit offsets */
 846         IAVF_RX_DESC_STATUS_DD_SHIFT            = 0,
 847         IAVF_RX_DESC_STATUS_EOF_SHIFT           = 1,
 848         IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 849         IAVF_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 850         IAVF_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 851         IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 852         IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 853         IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 854
 855         IAVF_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 856         IAVF_RX_DESC_STATUS_FLM_SHIFT           = 11,
 857         IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 858         IAVF_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 859         IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 860         IAVF_RX_DESC_STATUS_RESERVED2_SHIFT     = 16, /* 2 BITS */
 861         IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 862         IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 863 };
 864
 865 #define IAVF_RXD_QW1_STATUS_SHIFT       0
 866 #define IAVF_RXD_QW1_STATUS_MASK        ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) << \
 867                                          IAVF_RXD_QW1_STATUS_SHIFT)
 868
 869 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT   IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
 870 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK       (0x3UL << \
 871                                              IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 872
 873 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT  IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
 874 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 875
 876 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT       IAVF_RX_DESC_STATUS_UMBCAST
 877 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 878                                          IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT)
 879
 880 enum iavf_rx_desc_fltstat_values {
 881         IAVF_RX_DESC_FLTSTAT_NO_DATA    = 0,
 882         IAVF_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 883         IAVF_RX_DESC_FLTSTAT_RSV        = 2,
 884         IAVF_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 885 };
 886
 887 #define IAVF_RXD_PACKET_TYPE_UNICAST    0
 888 #define IAVF_RXD_PACKET_TYPE_MULTICAST  1
 889 #define IAVF_RXD_PACKET_TYPE_BROADCAST  2
 890 #define IAVF_RXD_PACKET_TYPE_MIRRORED   3
 891
 892 #define IAVF_RXD_QW1_ERROR_SHIFT        19
 893 #define IAVF_RXD_QW1_ERROR_MASK         (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT)
 894
 895 enum iavf_rx_desc_error_bits {
 896         /* Note: These are predefined bit offsets */
 897         IAVF_RX_DESC_ERROR_RXE_SHIFT            = 0,
 898         IAVF_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 899         IAVF_RX_DESC_ERROR_HBO_SHIFT            = 2,
 900         IAVF_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 901         IAVF_RX_DESC_ERROR_IPE_SHIFT            = 3,
 902         IAVF_RX_DESC_ERROR_L4E_SHIFT            = 4,
 903         IAVF_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 904         IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 905         IAVF_RX_DESC_ERROR_PPRS_SHIFT           = 7
 906 };
 907
 908 enum iavf_rx_desc_error_l3l4e_fcoe_masks {
 909         IAVF_RX_DESC_ERROR_L3L4E_NONE           = 0,
 910         IAVF_RX_DESC_ERROR_L3L4E_PROT           = 1,
 911         IAVF_RX_DESC_ERROR_L3L4E_FC             = 2,
 912         IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 913         IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 914 };
 915
 916 #define IAVF_RXD_QW1_PTYPE_SHIFT        30
 917 #define IAVF_RXD_QW1_PTYPE_MASK         (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT)
 918
 919 /* Packet type non-ip values */
 920 enum iavf_rx_l2_ptype {
 921         IAVF_RX_PTYPE_L2_RESERVED                       = 0,
 922         IAVF_RX_PTYPE_L2_MAC_PAY2                       = 1,
 923         IAVF_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 924         IAVF_RX_PTYPE_L2_FIP_PAY2                       = 3,
 925         IAVF_RX_PTYPE_L2_OUI_PAY2                       = 4,
 926         IAVF_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 927         IAVF_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 928         IAVF_RX_PTYPE_L2_ECP_PAY2                       = 7,
 929         IAVF_RX_PTYPE_L2_EVB_PAY2                       = 8,
 930         IAVF_RX_PTYPE_L2_QCN_PAY2                       = 9,
 931         IAVF_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 932         IAVF_RX_PTYPE_L2_ARP                            = 11,
 933         IAVF_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 934         IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 935         IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 936         IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 937         IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 938         IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 939         IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 940         IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 941         IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 942         IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 943         IAVF_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 944         IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 945         IAVF_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 946         IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 947 };
 948
 949 struct iavf_rx_ptype_decoded {
 950         u32 ptype:8;
 951         u32 known:1;
 952         u32 outer_ip:1;
 953         u32 outer_ip_ver:1;
 954         u32 outer_frag:1;
 955         u32 tunnel_type:3;
 956         u32 tunnel_end_prot:2;
 957         u32 tunnel_end_frag:1;
 958         u32 inner_prot:4;
 959         u32 payload_layer:3;
 960 };
 961
 962 enum iavf_rx_ptype_outer_ip {
 963         IAVF_RX_PTYPE_OUTER_L2  = 0,
 964         IAVF_RX_PTYPE_OUTER_IP  = 1
 965 };
 966
 967 enum iavf_rx_ptype_outer_ip_ver {
 968         IAVF_RX_PTYPE_OUTER_NONE        = 0,
 969         IAVF_RX_PTYPE_OUTER_IPV4        = 0,
 970         IAVF_RX_PTYPE_OUTER_IPV6        = 1
 971 };
 972
 973 enum iavf_rx_ptype_outer_fragmented {
 974         IAVF_RX_PTYPE_NOT_FRAG  = 0,
 975         IAVF_RX_PTYPE_FRAG      = 1
 976 };
 977
 978 enum iavf_rx_ptype_tunnel_type {
 979         IAVF_RX_PTYPE_TUNNEL_NONE               = 0,
 980         IAVF_RX_PTYPE_TUNNEL_IP_IP              = 1,
 981         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 982         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 983         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 984 };
 985
 986 enum iavf_rx_ptype_tunnel_end_prot {
 987         IAVF_RX_PTYPE_TUNNEL_END_NONE   = 0,
 988         IAVF_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 989         IAVF_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 990 };
 991
 992 enum iavf_rx_ptype_inner_prot {
 993         IAVF_RX_PTYPE_INNER_PROT_NONE           = 0,
 994         IAVF_RX_PTYPE_INNER_PROT_UDP            = 1,
 995         IAVF_RX_PTYPE_INNER_PROT_TCP            = 2,
 996         IAVF_RX_PTYPE_INNER_PROT_SCTP           = 3,
 997         IAVF_RX_PTYPE_INNER_PROT_ICMP           = 4,
 998         IAVF_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 999 };
1000
1001 enum iavf_rx_ptype_payload_layer {
1002         IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
1003         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
1004         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
1005         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
1006 };
1007
1008 #define IAVF_RX_PTYPE_BIT_MASK          0x0FFFFFFF
1009 #define IAVF_RX_PTYPE_SHIFT             56
1010
1011 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT  38
1012 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
1013                                          IAVF_RXD_QW1_LENGTH_PBUF_SHIFT)
1014
1015 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT  52
1016 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
1017                                          IAVF_RXD_QW1_LENGTH_HBUF_SHIFT)
1018
1019 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT   63
1020 #define IAVF_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
1021
1022 #define IAVF_RXD_QW1_NEXTP_SHIFT        38
1023 #define IAVF_RXD_QW1_NEXTP_MASK         (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT)
1024
1025 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT   0
1026 #define IAVF_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
1027                                          IAVF_RXD_QW2_EXT_STATUS_SHIFT)
1028
1029 enum iavf_rx_desc_ext_status_bits {
1030         /* Note: These are predefined bit offsets */
1031         IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
1032         IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
1033         IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
1034         IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
1035         IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
1036         IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
1037         IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
1038 };
1039
1040 #define IAVF_RXD_QW2_L2TAG2_SHIFT       0
1041 #define IAVF_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT)
1042
1043 #define IAVF_RXD_QW2_L2TAG3_SHIFT       16
1044 #define IAVF_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT)
1045
1046 enum iavf_rx_desc_pe_status_bits {
1047         /* Note: These are predefined bit offsets */
1048         IAVF_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
1049         IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
1050         IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
1051         IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
1052         IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
1053         IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
1054         IAVF_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
1055         IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
1056         IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
1057 };
1058
1059 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
1060 #define IAVF_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
1061
1062 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
1063 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
1064                                 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
1065
1066 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
1067 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
1068                                 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
1069
1070 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
1071 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
1072                                 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
1073
1074 enum iavf_rx_prog_status_desc_status_bits {
1075         /* Note: These are predefined bit offsets */
1076         IAVF_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
1077         IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
1078 };
1079
1080 enum iavf_rx_prog_status_desc_prog_id_masks {
1081         IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
1082         IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
1083         IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
1084 };
1085
1086 enum iavf_rx_prog_status_desc_error_bits {
1087         /* Note: These are predefined bit offsets */
1088         IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
1089         IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
1090         IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
1091         IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
1092 };
1093
1094 #define IAVF_TWO_BIT_MASK       0x3
1095 #define IAVF_THREE_BIT_MASK     0x7
1096 #define IAVF_FOUR_BIT_MASK      0xF
1097 #define IAVF_EIGHTEEN_BIT_MASK  0x3FFFF
1098
1099 /* TX Descriptor */
1100 struct iavf_tx_desc {
1101         __le64 buffer_addr; /* Address of descriptor's data buf */
1102         __le64 cmd_type_offset_bsz;
1103 };
1104
1105 #define IAVF_TXD_QW1_DTYPE_SHIFT        0
1106 #define IAVF_TXD_QW1_DTYPE_MASK         (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
1107
1108 enum iavf_tx_desc_dtype_value {
1109         IAVF_TX_DESC_DTYPE_DATA         = 0x0,
1110         IAVF_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
1111         IAVF_TX_DESC_DTYPE_CONTEXT      = 0x1,
1112         IAVF_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
1113         IAVF_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
1114         IAVF_TX_DESC_DTYPE_DDP_CTX      = 0x9,
1115         IAVF_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
1116         IAVF_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
1117         IAVF_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
1118         IAVF_TX_DESC_DTYPE_DESC_DONE    = 0xF
1119 };
1120
1121 #define IAVF_TXD_QW1_CMD_SHIFT  4
1122 #define IAVF_TXD_QW1_CMD_MASK   (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)
1123
1124 enum iavf_tx_desc_cmd_bits {
1125         IAVF_TX_DESC_CMD_EOP                    = 0x0001,
1126         IAVF_TX_DESC_CMD_RS                     = 0x0002,
1127         IAVF_TX_DESC_CMD_ICRC                   = 0x0004,
1128         IAVF_TX_DESC_CMD_IL2TAG1                = 0x0008,
1129         IAVF_TX_DESC_CMD_DUMMY                  = 0x0010,
1130         IAVF_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
1131         IAVF_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
1132         IAVF_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
1133         IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
1134         IAVF_TX_DESC_CMD_FCOET                  = 0x0080,
1135         IAVF_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
1136         IAVF_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
1137         IAVF_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
1138         IAVF_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
1139         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
1140         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
1141         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
1142         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
1143 };
1144
1145 #define IAVF_TXD_QW1_OFFSET_SHIFT       16
1146 #define IAVF_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
1147                                          IAVF_TXD_QW1_OFFSET_SHIFT)
1148
1149 enum iavf_tx_desc_length_fields {
1150         /* Note: These are predefined bit offsets */
1151         IAVF_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
1152         IAVF_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
1153         IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
1154 };
1155
1156 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
1157 #define IAVF_TXD_QW1_IPLEN_MASK  (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
1158 #define IAVF_TXD_QW1_L4LEN_MASK  (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1159 #define IAVF_TXD_QW1_FCLEN_MASK  (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
1160
1161 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT    34
1162 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
1163                                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
1164
1165 #define IAVF_TXD_QW1_L2TAG1_SHIFT       48
1166 #define IAVF_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)
1167
1168 /* Context descriptors */
1169 struct iavf_tx_context_desc {
1170         __le32 tunneling_params;
1171         __le16 l2tag2;
1172         __le16 rsvd;
1173         __le64 type_cmd_tso_mss;
1174 };
1175
1176 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT    0
1177 #define IAVF_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT)
1178
1179 #define IAVF_TXD_CTX_QW1_CMD_SHIFT      4
1180 #define IAVF_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)
1181
1182 enum iavf_tx_ctx_desc_cmd_bits {
1183         IAVF_TX_CTX_DESC_TSO            = 0x01,
1184         IAVF_TX_CTX_DESC_TSYN           = 0x02,
1185         IAVF_TX_CTX_DESC_IL2TAG2        = 0x04,
1186         IAVF_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
1187         IAVF_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
1188         IAVF_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
1189         IAVF_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
1190         IAVF_TX_CTX_DESC_SWTCH_VSI      = 0x30,
1191         IAVF_TX_CTX_DESC_SWPE           = 0x40
1192 };
1193
1194 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT  30
1195 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
1196                                          IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
1197
1198 #define IAVF_TXD_CTX_QW1_MSS_SHIFT      50
1199 #define IAVF_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
1200                                          IAVF_TXD_CTX_QW1_MSS_SHIFT)
1201
1202 #define IAVF_TXD_CTX_QW1_VSI_SHIFT      50
1203 #define IAVF_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
1204
1205 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT   0
1206 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
1207                                          IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
1208
1209 enum iavf_tx_ctx_desc_eipt_offload {
1210         IAVF_TX_CTX_EXT_IP_NONE         = 0x0,
1211         IAVF_TX_CTX_EXT_IP_IPV6         = 0x1,
1212         IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
1213         IAVF_TX_CTX_EXT_IP_IPV4         = 0x3
1214 };
1215
1216 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
1217 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
1218                                          IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
1219
1220 #define IAVF_TXD_CTX_QW0_NATT_SHIFT     9
1221 #define IAVF_TXD_CTX_QW0_NATT_MASK      (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
1222
1223 #define IAVF_TXD_CTX_UDP_TUNNELING      BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
1224 #define IAVF_TXD_CTX_GRE_TUNNELING      (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
1225
1226 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
1227 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
1228
1229 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST       IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
1230
1231 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT   12
1232 #define IAVF_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
1233                                          IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
1234
1235 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT   19
1236 #define IAVF_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
1237                                          IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
1238
1239 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT   23
1240 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
1241 struct iavf_nop_desc {
1242         __le64 rsvd;
1243         __le64 dtype_cmd;
1244 };
1245
1246 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT    0
1247 #define IAVF_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT)
1248
1249 #define IAVF_TXD_NOP_QW1_CMD_SHIFT      4
1250 #define IAVF_TXD_NOP_QW1_CMD_MASK       (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT)
1251
1252 enum iavf_tx_nop_desc_cmd_bits {
1253         /* Note: These are predefined bit offsets */
1254         IAVF_TX_NOP_DESC_EOP_SHIFT      = 0,
1255         IAVF_TX_NOP_DESC_RS_SHIFT       = 1,
1256         IAVF_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
1257 };
1258
1259 struct iavf_filter_program_desc {
1260         __le32 qindex_flex_ptype_vsi;
1261         __le32 rsvd;
1262         __le32 dtype_cmd_cntindex;
1263         __le32 fd_id;
1264 };
1265 #define IAVF_TXD_FLTR_QW0_QINDEX_SHIFT  0
1266 #define IAVF_TXD_FLTR_QW0_QINDEX_MASK   (0x7FFUL << \
1267                                          IAVF_TXD_FLTR_QW0_QINDEX_SHIFT)
1268 #define IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
1269 #define IAVF_TXD_FLTR_QW0_FLEXOFF_MASK  (0x7UL << \
1270                                          IAVF_TXD_FLTR_QW0_FLEXOFF_SHIFT)
1271 #define IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT  17
1272 #define IAVF_TXD_FLTR_QW0_PCTYPE_MASK   (0x3FUL << \
1273                                          IAVF_TXD_FLTR_QW0_PCTYPE_SHIFT)
1274
1275 /* Packet Classifier Types for filters */
1276 enum iavf_filter_pctype {
1277         /* Note: Values 0-28 are reserved for future use.
1278          * Value 29, 30, 32 are not supported on XL710 and X710.
1279          */
1280         IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
1281         IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
1282         IAVF_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
1283         IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
1284         IAVF_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
1285         IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
1286         IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
1287         IAVF_FILTER_PCTYPE_FRAG_IPV4                    = 36,
1288         /* Note: Values 37-38 are reserved for future use.
1289          * Value 39, 40, 42 are not supported on XL710 and X710.
1290          */
1291         IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
1292         IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
1293         IAVF_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
1294         IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
1295         IAVF_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
1296         IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
1297         IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
1298         IAVF_FILTER_PCTYPE_FRAG_IPV6                    = 46,
1299         /* Note: Value 47 is reserved for future use */
1300         IAVF_FILTER_PCTYPE_FCOE_OX                      = 48,
1301         IAVF_FILTER_PCTYPE_FCOE_RX                      = 49,
1302         IAVF_FILTER_PCTYPE_FCOE_OTHER                   = 50,
1303         /* Note: Values 51-62 are reserved for future use */
1304         IAVF_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
1305 };
1306
1307 enum iavf_filter_program_desc_dest {
1308         IAVF_FILTER_PROGRAM_DESC_DEST_DROP_PACKET               = 0x0,
1309         IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX      = 0x1,
1310         IAVF_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER       = 0x2,
1311 };
1312
1313 enum iavf_filter_program_desc_fd_status {
1314         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_NONE                 = 0x0,
1315         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID                = 0x1,
1316         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES    = 0x2,
1317         IAVF_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES          = 0x3,
1318 };
1319
1320 #define IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT        23
1321 #define IAVF_TXD_FLTR_QW0_DEST_VSI_MASK (0x1FFUL << \
1322                                          IAVF_TXD_FLTR_QW0_DEST_VSI_SHIFT)
1323
1324 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT   0
1325 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT)
1326
1327 #define IAVF_TXD_FLTR_QW1_CMD_SHIFT     4
1328 #define IAVF_TXD_FLTR_QW1_CMD_MASK      (0xFFFFULL << \
1329                                          IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1330
1331 #define IAVF_TXD_FLTR_QW1_PCMD_SHIFT    (0x0ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1332 #define IAVF_TXD_FLTR_QW1_PCMD_MASK     (0x7ULL << IAVF_TXD_FLTR_QW1_PCMD_SHIFT)
1333
1334 enum iavf_filter_program_desc_pcmd {
1335         IAVF_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE        = 0x1,
1336         IAVF_FILTER_PROGRAM_DESC_PCMD_REMOVE            = 0x2,
1337 };
1338
1339 #define IAVF_TXD_FLTR_QW1_DEST_SHIFT    (0x3ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1340 #define IAVF_TXD_FLTR_QW1_DEST_MASK     (0x3ULL << IAVF_TXD_FLTR_QW1_DEST_SHIFT)
1341
1342 #define IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1343 #define IAVF_TXD_FLTR_QW1_CNT_ENA_MASK  BIT_ULL(IAVF_TXD_FLTR_QW1_CNT_ENA_SHIFT)
1344
1345 #define IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT       (0x9ULL + \
1346                                                  IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1347 #define IAVF_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1348                                           IAVF_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1349
1350 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
1351                                          IAVF_TXD_FLTR_QW1_CMD_SHIFT)
1352 #define IAVF_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
1353
1354 #define IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1355 #define IAVF_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1356                                          IAVF_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1357
1358 enum iavf_filter_type {
1359         IAVF_FLOW_DIRECTOR_FLTR = 0,
1360         IAVF_PE_QUAD_HASH_FLTR = 1,
1361         IAVF_ETHERTYPE_FLTR,
1362         IAVF_FCOE_CTX_FLTR,
1363         IAVF_MAC_VLAN_FLTR,
1364         IAVF_HASH_FLTR
1365 };
1366
1367 struct iavf_vsi_context {
1368         u16 seid;
1369         u16 uplink_seid;
1370         u16 vsi_number;
1371         u16 vsis_allocated;
1372         u16 vsis_unallocated;
1373         u16 flags;
1374         u8 pf_num;
1375         u8 vf_num;
1376         u8 connection_type;
1377         struct iavf_aqc_vsi_properties_data info;
1378 };
1379
1380 struct iavf_veb_context {
1381         u16 seid;
1382         u16 uplink_seid;
1383         u16 veb_number;
1384         u16 vebs_allocated;
1385         u16 vebs_unallocated;
1386         u16 flags;
1387         struct iavf_aqc_get_veb_parameters_completion info;
1388 };
1389
1390 /* Statistics collected by each port, VSI, VEB, and S-channel */
1391 struct iavf_eth_stats {
1392         u64 rx_bytes;                   /* gorc */
1393         u64 rx_unicast;                 /* uprc */
1394         u64 rx_multicast;               /* mprc */
1395         u64 rx_broadcast;               /* bprc */
1396         u64 rx_discards;                /* rdpc */
1397         u64 rx_unknown_protocol;        /* rupp */
1398         u64 tx_bytes;                   /* gotc */
1399         u64 tx_unicast;                 /* uptc */
1400         u64 tx_multicast;               /* mptc */
1401         u64 tx_broadcast;               /* bptc */
1402         u64 tx_discards;                /* tdpc */
1403         u64 tx_errors;                  /* tepc */
1404 };
1405
1406 /* Statistics collected per VEB per TC */
1407 struct iavf_veb_tc_stats {
1408         u64 tc_rx_packets[IAVF_MAX_TRAFFIC_CLASS];
1409         u64 tc_rx_bytes[IAVF_MAX_TRAFFIC_CLASS];
1410         u64 tc_tx_packets[IAVF_MAX_TRAFFIC_CLASS];
1411         u64 tc_tx_bytes[IAVF_MAX_TRAFFIC_CLASS];
1412 };
1413
1414 /* Statistics collected per function for FCoE */
1415 struct iavf_fcoe_stats {
1416         u64 rx_fcoe_packets;            /* fcoeprc */
1417         u64 rx_fcoe_dwords;             /* focedwrc */
1418         u64 rx_fcoe_dropped;            /* fcoerpdc */
1419         u64 tx_fcoe_packets;            /* fcoeptc */
1420         u64 tx_fcoe_dwords;             /* focedwtc */
1421         u64 fcoe_bad_fccrc;             /* fcoecrc */
1422         u64 fcoe_last_error;            /* fcoelast */
1423         u64 fcoe_ddp_count;             /* fcoeddpc */
1424 };
1425
1426 /* offset to per function FCoE statistics block */
1427 #define IAVF_FCOE_VF_STAT_OFFSET        0
1428 #define IAVF_FCOE_PF_STAT_OFFSET        128
1429 #define IAVF_FCOE_STAT_MAX              (IAVF_FCOE_PF_STAT_OFFSET + IAVF_MAX_PF)
1430
1431 /* Statistics collected by the MAC */
1432 struct iavf_hw_port_stats {
1433         /* eth stats collected by the port */
1434         struct iavf_eth_stats eth;
1435
1436         /* additional port specific stats */
1437         u64 tx_dropped_link_down;       /* tdold */
1438         u64 crc_errors;                 /* crcerrs */
1439         u64 illegal_bytes;              /* illerrc */
1440         u64 error_bytes;                /* errbc */
1441         u64 mac_local_faults;           /* mlfc */
1442         u64 mac_remote_faults;          /* mrfc */
1443         u64 rx_length_errors;           /* rlec */
1444         u64 link_xon_rx;                /* lxonrxc */
1445         u64 link_xoff_rx;               /* lxoffrxc */
1446         u64 priority_xon_rx[8];         /* pxonrxc[8] */
1447         u64 priority_xoff_rx[8];        /* pxoffrxc[8] */
1448         u64 link_xon_tx;                /* lxontxc */
1449         u64 link_xoff_tx;               /* lxofftxc */
1450         u64 priority_xon_tx[8];         /* pxontxc[8] */
1451         u64 priority_xoff_tx[8];        /* pxofftxc[8] */
1452         u64 priority_xon_2_xoff[8];     /* pxon2offc[8] */
1453         u64 rx_size_64;                 /* prc64 */
1454         u64 rx_size_127;                /* prc127 */
1455         u64 rx_size_255;                /* prc255 */
1456         u64 rx_size_511;                /* prc511 */
1457         u64 rx_size_1023;               /* prc1023 */
1458         u64 rx_size_1522;               /* prc1522 */
1459         u64 rx_size_big;                /* prc9522 */
1460         u64 rx_undersize;               /* ruc */
1461         u64 rx_fragments;               /* rfc */
1462         u64 rx_oversize;                /* roc */
1463         u64 rx_jabber;                  /* rjc */
1464         u64 tx_size_64;                 /* ptc64 */
1465         u64 tx_size_127;                /* ptc127 */
1466         u64 tx_size_255;                /* ptc255 */
1467         u64 tx_size_511;                /* ptc511 */
1468         u64 tx_size_1023;               /* ptc1023 */
1469         u64 tx_size_1522;               /* ptc1522 */
1470         u64 tx_size_big;                /* ptc9522 */
1471         u64 mac_short_packet_dropped;   /* mspdc */
1472         u64 checksum_error;             /* xec */
1473         /* flow director stats */
1474         u64 fd_atr_match;
1475         u64 fd_sb_match;
1476         u64 fd_atr_tunnel_match;
1477         u32 fd_atr_status;
1478         u32 fd_sb_status;
1479         /* EEE LPI */
1480         u32 tx_lpi_status;
1481         u32 rx_lpi_status;
1482         u64 tx_lpi_count;               /* etlpic */
1483         u64 rx_lpi_count;               /* erlpic */
1484 };
1485
1486 /* Checksum and Shadow RAM pointers */
1487 #define IAVF_SR_NVM_CONTROL_WORD                0x00
1488 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR          0x03
1489 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR           0x04
1490 #define IAVF_SR_OPTION_ROM_PTR                  0x05
1491 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
1492 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR     0x07
1493 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
1494 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR           0x09
1495 #define IAVF_SR_RO_PCIE_LCB_PTR                 0x0A
1496 #define IAVF_SR_EMP_IMAGE_PTR                   0x0B
1497 #define IAVF_SR_PE_IMAGE_PTR                    0x0C
1498 #define IAVF_SR_CSR_PROTECTED_LIST_PTR          0x0D
1499 #define IAVF_SR_MNG_CONFIG_PTR                  0x0E
1500 #define IAVF_EMP_MODULE_PTR                     0x0F
1501 #define IAVF_SR_EMP_MODULE_PTR                  0x48
1502 #define IAVF_SR_PBA_FLAGS                       0x15
1503 #define IAVF_SR_PBA_BLOCK_PTR                   0x16
1504 #define IAVF_SR_BOOT_CONFIG_PTR                 0x17
1505 #define IAVF_NVM_OEM_VER_OFF                    0x83
1506 #define IAVF_SR_NVM_DEV_STARTER_VERSION         0x18
1507 #define IAVF_SR_NVM_WAKE_ON_LAN                 0x19
1508 #define IAVF_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR   0x27
1509 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
1510 #define IAVF_SR_NVM_MAP_VERSION                 0x29
1511 #define IAVF_SR_NVM_IMAGE_VERSION               0x2A
1512 #define IAVF_SR_NVM_STRUCTURE_VERSION           0x2B
1513 #define IAVF_SR_NVM_EETRACK_LO                  0x2D
1514 #define IAVF_SR_NVM_EETRACK_HI                  0x2E
1515 #define IAVF_SR_VPD_PTR                         0x2F
1516 #define IAVF_SR_PXE_SETUP_PTR                   0x30
1517 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
1518 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO         0x34
1519 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI         0x35
1520 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
1521 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR          0x38
1522 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
1523 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
1524 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
1525 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR           0x3D
1526 #define IAVF_SR_PCIE_ALT_AUTO_LOAD_PTR          0x3E
1527 #define IAVF_SR_SW_CHECKSUM_WORD                0x3F
1528 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
1529 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
1530 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
1531 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
1532 #define IAVF_SR_EMP_SR_SETTINGS_PTR             0x48
1533 #define IAVF_SR_FEATURE_CONFIGURATION_PTR       0x49
1534 #define IAVF_SR_CONFIGURATION_METADATA_PTR      0x4D
1535 #define IAVF_SR_IMMEDIATE_VALUES_PTR            0x4E
1536
1537 /* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1538 #define IAVF_SR_VPD_MODULE_MAX_SIZE             1024
1539 #define IAVF_SR_PCIE_ALT_MODULE_MAX_SIZE        1024
1540 #define IAVF_SR_CONTROL_WORD_1_SHIFT            0x06
1541 #define IAVF_SR_CONTROL_WORD_1_MASK     (0x03 << IAVF_SR_CONTROL_WORD_1_SHIFT)
1542 #define IAVF_SR_CONTROL_WORD_1_NVM_BANK_VALID   BIT(5)
1543 #define IAVF_SR_NVM_MAP_STRUCTURE_TYPE          BIT(12)
1544 #define IAVF_PTR_TYPE                           BIT(15)
1545
1546 /* Shadow RAM related */
1547 #define IAVF_SR_SECTOR_SIZE_IN_WORDS    0x800
1548 #define IAVF_SR_BUF_ALIGNMENT           4096
1549 #define IAVF_SR_WORDS_IN_1KB            512
1550 /* Checksum should be calculated such that after adding all the words,
1551  * including the checksum word itself, the sum should be 0xBABA.
1552  */
1553 #define IAVF_SR_SW_CHECKSUM_BASE        0xBABA
1554
1555 #define IAVF_SRRD_SRCTL_ATTEMPTS        100000
1556
1557 /* FCoE Tx context descriptor - Use the iavf_tx_context_desc struct */
1558
1559 enum i40E_fcoe_tx_ctx_desc_cmd_bits {
1560         IAVF_FCOE_TX_CTX_DESC_OPCODE_SINGLE_SEND        = 0x00, /* 4 BITS */
1561         IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS2      = 0x01, /* 4 BITS */
1562         IAVF_FCOE_TX_CTX_DESC_OPCODE_TSO_FC_CLASS3      = 0x05, /* 4 BITS */
1563         IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS2     = 0x02, /* 4 BITS */
1564         IAVF_FCOE_TX_CTX_DESC_OPCODE_ETSO_FC_CLASS3     = 0x06, /* 4 BITS */
1565         IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS2      = 0x03, /* 4 BITS */
1566         IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_FC_CLASS3      = 0x07, /* 4 BITS */
1567         IAVF_FCOE_TX_CTX_DESC_OPCODE_DDP_CTX_INVL       = 0x08, /* 4 BITS */
1568         IAVF_FCOE_TX_CTX_DESC_OPCODE_DWO_CTX_INVL       = 0x09, /* 4 BITS */
1569         IAVF_FCOE_TX_CTX_DESC_RELOFF                    = 0x10,
1570         IAVF_FCOE_TX_CTX_DESC_CLRSEQ                    = 0x20,
1571         IAVF_FCOE_TX_CTX_DESC_DIFENA                    = 0x40,
1572         IAVF_FCOE_TX_CTX_DESC_IL2TAG2                   = 0x80
1573 };
1574
1575 /* FCoE DIF/DIX Context descriptor */
1576 struct iavf_fcoe_difdix_context_desc {
1577         __le64 flags_buff0_buff1_ref;
1578         __le64 difapp_msk_bias;
1579 };
1580
1581 #define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT    0
1582 #define IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_MASK     (0xFFFULL << \
1583                                         IAVF_FCOE_DIFDIX_CTX_QW0_FLAGS_SHIFT)
1584
1585 enum iavf_fcoe_difdix_ctx_desc_flags_bits {
1586         /* 2 BITS */
1587         IAVF_FCOE_DIFDIX_CTX_DESC_RSVD                          = 0x0000,
1588         /* 1 BIT  */
1589         IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGCHK                = 0x0000,
1590         /* 1 BIT  */
1591         IAVF_FCOE_DIFDIX_CTX_DESC_APPTYPE_TAGNOTCHK             = 0x0004,
1592         /* 2 BITS */
1593         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_OPAQUE                  = 0x0000,
1594         /* 2 BITS */
1595         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY            = 0x0008,
1596         /* 2 BITS */
1597         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPTAG     = 0x0010,
1598         /* 2 BITS */
1599         IAVF_FCOE_DIFDIX_CTX_DESC_GTYPE_CHKINTEGRITY_APPREFTAG  = 0x0018,
1600         /* 2 BITS */
1601         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_CNST                  = 0x0000,
1602         /* 2 BITS */
1603         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_INC1BLK               = 0x0020,
1604         /* 2 BITS */
1605         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_APPTAG                = 0x0040,
1606         /* 2 BITS */
1607         IAVF_FCOE_DIFDIX_CTX_DESC_REFTYPE_RSVD                  = 0x0060,
1608         /* 1 BIT  */
1609         IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_XSUM                  = 0x0000,
1610         /* 1 BIT  */
1611         IAVF_FCOE_DIFDIX_CTX_DESC_DIXMODE_CRC                   = 0x0080,
1612         /* 2 BITS */
1613         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_UNTAG                 = 0x0000,
1614         /* 2 BITS */
1615         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_BUF                   = 0x0100,
1616         /* 2 BITS */
1617         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_RSVD                  = 0x0200,
1618         /* 2 BITS */
1619         IAVF_FCOE_DIFDIX_CTX_DESC_DIFHOST_EMBDTAGS              = 0x0300,
1620         /* 1 BIT  */
1621         IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_UNTAG                  = 0x0000,
1622         /* 1 BIT  */
1623         IAVF_FCOE_DIFDIX_CTX_DESC_DIFLAN_TAG                    = 0x0400,
1624         /* 1 BIT */
1625         IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_512B                   = 0x0000,
1626         /* 1 BIT */
1627         IAVF_FCOE_DIFDIX_CTX_DESC_DIFBLK_4K                     = 0x0800
1628 };
1629
1630 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT    12
1631 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_MASK     (0x3FFULL << \
1632                                         IAVF_FCOE_DIFDIX_CTX_QW0_BUFF0_SHIFT)
1633
1634 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT    22
1635 #define IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_MASK     (0x3FFULL << \
1636                                         IAVF_FCOE_DIFDIX_CTX_QW0_BUFF1_SHIFT)
1637
1638 #define IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT      32
1639 #define IAVF_FCOE_DIFDIX_CTX_QW0_REF_MASK       (0xFFFFFFFFULL << \
1640                                         IAVF_FCOE_DIFDIX_CTX_QW0_REF_SHIFT)
1641
1642 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT      0
1643 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MASK       (0xFFFFULL << \
1644                                         IAVF_FCOE_DIFDIX_CTX_QW1_APP_SHIFT)
1645
1646 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT  16
1647 #define IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_MASK   (0xFFFFULL << \
1648                                         IAVF_FCOE_DIFDIX_CTX_QW1_APP_MSK_SHIFT)
1649
1650 #define IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT 32
1651 #define IAVF_FCOE_DIFDIX_CTX_QW0_REF_BIAS_MASK  (0xFFFFFFFFULL << \
1652                                         IAVF_FCOE_DIFDIX_CTX_QW1_REF_BIAS_SHIFT)
1653
1654 /* FCoE DIF/DIX Buffers descriptor */
1655 struct iavf_fcoe_difdix_buffers_desc {
1656         __le64 buff_addr0;
1657         __le64 buff_addr1;
1658 };
1659
1660 /* FCoE DDP Context descriptor */
1661 struct iavf_fcoe_ddp_context_desc {
1662         __le64 rsvd;
1663         __le64 type_cmd_foff_lsize;
1664 };
1665
1666 #define IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT       0
1667 #define IAVF_FCOE_DDP_CTX_QW1_DTYPE_MASK        (0xFULL << \
1668                                         IAVF_FCOE_DDP_CTX_QW1_DTYPE_SHIFT)
1669
1670 #define IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT 4
1671 #define IAVF_FCOE_DDP_CTX_QW1_CMD_MASK  (0xFULL << \
1672                                          IAVF_FCOE_DDP_CTX_QW1_CMD_SHIFT)
1673
1674 enum iavf_fcoe_ddp_ctx_desc_cmd_bits {
1675         IAVF_FCOE_DDP_CTX_DESC_BSIZE_512B       = 0x00, /* 2 BITS */
1676         IAVF_FCOE_DDP_CTX_DESC_BSIZE_4K         = 0x01, /* 2 BITS */
1677         IAVF_FCOE_DDP_CTX_DESC_BSIZE_8K         = 0x02, /* 2 BITS */
1678         IAVF_FCOE_DDP_CTX_DESC_BSIZE_16K        = 0x03, /* 2 BITS */
1679         IAVF_FCOE_DDP_CTX_DESC_DIFENA           = 0x04, /* 1 BIT  */
1680         IAVF_FCOE_DDP_CTX_DESC_LASTSEQH         = 0x08, /* 1 BIT  */
1681 };
1682
1683 #define IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT        16
1684 #define IAVF_FCOE_DDP_CTX_QW1_FOFF_MASK (0x3FFFULL << \
1685                                          IAVF_FCOE_DDP_CTX_QW1_FOFF_SHIFT)
1686
1687 #define IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT       32
1688 #define IAVF_FCOE_DDP_CTX_QW1_LSIZE_MASK        (0x3FFFULL << \
1689                                         IAVF_FCOE_DDP_CTX_QW1_LSIZE_SHIFT)
1690
1691 /* FCoE DDP/DWO Queue Context descriptor */
1692 struct iavf_fcoe_queue_context_desc {
1693         __le64 dmaindx_fbase;           /* 0:11 DMAINDX, 12:63 FBASE */
1694         __le64 flen_tph;                /* 0:12 FLEN, 13:15 TPH */
1695 };
1696
1697 #define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT   0
1698 #define IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_MASK    (0xFFFULL << \
1699                                         IAVF_FCOE_QUEUE_CTX_QW0_DMAINDX_SHIFT)
1700
1701 #define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT     12
1702 #define IAVF_FCOE_QUEUE_CTX_QW0_FBASE_MASK      (0xFFFFFFFFFFFFFULL << \
1703                                         IAVF_FCOE_QUEUE_CTX_QW0_FBASE_SHIFT)
1704
1705 #define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT      0
1706 #define IAVF_FCOE_QUEUE_CTX_QW1_FLEN_MASK       (0x1FFFULL << \
1707                                         IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1708
1709 #define IAVF_FCOE_QUEUE_CTX_QW1_TPH_SHIFT       13
1710 #define IAVF_FCOE_QUEUE_CTX_QW1_TPH_MASK        (0x7ULL << \
1711                                         IAVF_FCOE_QUEUE_CTX_QW1_FLEN_SHIFT)
1712
1713 enum iavf_fcoe_queue_ctx_desc_tph_bits {
1714         IAVF_FCOE_QUEUE_CTX_DESC_TPHRDESC       = 0x1,
1715         IAVF_FCOE_QUEUE_CTX_DESC_TPHDATA        = 0x2
1716 };
1717
1718 #define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT    30
1719 #define IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_MASK     (0x3ULL << \
1720                                         IAVF_FCOE_QUEUE_CTX_QW1_RECIPE_SHIFT)
1721
1722 /* FCoE DDP/DWO Filter Context descriptor */
1723 struct iavf_fcoe_filter_context_desc {
1724         __le32 param;
1725         __le16 seqn;
1726
1727         /* 48:51(0:3) RSVD, 52:63(4:15) DMAINDX */
1728         __le16 rsvd_dmaindx;
1729
1730         /* 0:7 FLAGS, 8:52 RSVD, 53:63 LANQ */
1731         __le64 flags_rsvd_lanq;
1732 };
1733
1734 #define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT  4
1735 #define IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_MASK   (0xFFF << \
1736                                         IAVF_FCOE_FILTER_CTX_QW0_DMAINDX_SHIFT)
1737
1738 enum iavf_fcoe_filter_ctx_desc_flags_bits {
1739         IAVF_FCOE_FILTER_CTX_DESC_CTYP_DDP      = 0x00,
1740         IAVF_FCOE_FILTER_CTX_DESC_CTYP_DWO      = 0x01,
1741         IAVF_FCOE_FILTER_CTX_DESC_ENODE_INIT    = 0x00,
1742         IAVF_FCOE_FILTER_CTX_DESC_ENODE_RSP     = 0x02,
1743         IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS2     = 0x00,
1744         IAVF_FCOE_FILTER_CTX_DESC_FC_CLASS3     = 0x04
1745 };
1746
1747 #define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT    0
1748 #define IAVF_FCOE_FILTER_CTX_QW1_FLAGS_MASK     (0xFFULL << \
1749                                         IAVF_FCOE_FILTER_CTX_QW1_FLAGS_SHIFT)
1750
1751 #define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT     8
1752 #define IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_MASK      (0x3FULL << \
1753                         IAVF_FCOE_FILTER_CTX_QW1_PCTYPE_SHIFT)
1754
1755 #define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT     53
1756 #define IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_MASK      (0x7FFULL << \
1757                         IAVF_FCOE_FILTER_CTX_QW1_LANQINDX_SHIFT)
1758
1759 enum iavf_switch_element_types {
1760         IAVF_SWITCH_ELEMENT_TYPE_MAC    = 1,
1761         IAVF_SWITCH_ELEMENT_TYPE_PF     = 2,
1762         IAVF_SWITCH_ELEMENT_TYPE_VF     = 3,
1763         IAVF_SWITCH_ELEMENT_TYPE_EMP    = 4,
1764         IAVF_SWITCH_ELEMENT_TYPE_BMC    = 6,
1765         IAVF_SWITCH_ELEMENT_TYPE_PE     = 16,
1766         IAVF_SWITCH_ELEMENT_TYPE_VEB    = 17,
1767         IAVF_SWITCH_ELEMENT_TYPE_PA     = 18,
1768         IAVF_SWITCH_ELEMENT_TYPE_VSI    = 19,
1769 };
1770
1771 /* Supported EtherType filters */
1772 enum iavf_ether_type_index {
1773         IAVF_ETHER_TYPE_1588            = 0,
1774         IAVF_ETHER_TYPE_FIP             = 1,
1775         IAVF_ETHER_TYPE_OUI_EXTENDED    = 2,
1776         IAVF_ETHER_TYPE_MAC_CONTROL     = 3,
1777         IAVF_ETHER_TYPE_LLDP            = 4,
1778         IAVF_ETHER_TYPE_EVB_PROTOCOL1   = 5,
1779         IAVF_ETHER_TYPE_EVB_PROTOCOL2   = 6,
1780         IAVF_ETHER_TYPE_QCN_CNM         = 7,
1781         IAVF_ETHER_TYPE_8021X           = 8,
1782         IAVF_ETHER_TYPE_ARP             = 9,
1783         IAVF_ETHER_TYPE_RSV1            = 10,
1784         IAVF_ETHER_TYPE_RSV2            = 11,
1785 };
1786
1787 /* Filter context base size is 1K */
1788 #define IAVF_HASH_FILTER_BASE_SIZE      1024
1789 /* Supported Hash filter values */
1790 enum iavf_hash_filter_size {
1791         IAVF_HASH_FILTER_SIZE_1K        = 0,
1792         IAVF_HASH_FILTER_SIZE_2K        = 1,
1793         IAVF_HASH_FILTER_SIZE_4K        = 2,
1794         IAVF_HASH_FILTER_SIZE_8K        = 3,
1795         IAVF_HASH_FILTER_SIZE_16K       = 4,
1796         IAVF_HASH_FILTER_SIZE_32K       = 5,
1797         IAVF_HASH_FILTER_SIZE_64K       = 6,
1798         IAVF_HASH_FILTER_SIZE_128K      = 7,
1799         IAVF_HASH_FILTER_SIZE_256K      = 8,
1800         IAVF_HASH_FILTER_SIZE_512K      = 9,
1801         IAVF_HASH_FILTER_SIZE_1M        = 10,
1802 };
1803
1804 /* DMA context base size is 0.5K */
1805 #define IAVF_DMA_CNTX_BASE_SIZE         512
1806 /* Supported DMA context values */
1807 enum iavf_dma_cntx_size {
1808         IAVF_DMA_CNTX_SIZE_512          = 0,
1809         IAVF_DMA_CNTX_SIZE_1K           = 1,
1810         IAVF_DMA_CNTX_SIZE_2K           = 2,
1811         IAVF_DMA_CNTX_SIZE_4K           = 3,
1812         IAVF_DMA_CNTX_SIZE_8K           = 4,
1813         IAVF_DMA_CNTX_SIZE_16K          = 5,
1814         IAVF_DMA_CNTX_SIZE_32K          = 6,
1815         IAVF_DMA_CNTX_SIZE_64K          = 7,
1816         IAVF_DMA_CNTX_SIZE_128K         = 8,
1817         IAVF_DMA_CNTX_SIZE_256K         = 9,
1818 };
1819
1820 /* Supported Hash look up table (LUT) sizes */
1821 enum iavf_hash_lut_size {
1822         IAVF_HASH_LUT_SIZE_128          = 0,
1823         IAVF_HASH_LUT_SIZE_512          = 1,
1824 };
1825
1826 /* Structure to hold a per PF filter control settings */
1827 struct iavf_filter_control_settings {
1828         /* number of PE Quad Hash filter buckets */
1829         enum iavf_hash_filter_size pe_filt_num;
1830         /* number of PE Quad Hash contexts */
1831         enum iavf_dma_cntx_size pe_cntx_num;
1832         /* number of FCoE filter buckets */
1833         enum iavf_hash_filter_size fcoe_filt_num;
1834         /* number of FCoE DDP contexts */
1835         enum iavf_dma_cntx_size fcoe_cntx_num;
1836         /* size of the Hash LUT */
1837         enum iavf_hash_lut_size hash_lut_size;
1838         /* enable FDIR filters for PF and its VFs */
1839         bool enable_fdir;
1840         /* enable Ethertype filters for PF and its VFs */
1841         bool enable_ethtype;
1842         /* enable MAC/VLAN filters for PF and its VFs */
1843         bool enable_macvlan;
1844 };
1845
1846 /* Structure to hold device level control filter counts */
1847 struct iavf_control_filter_stats {
1848         u16 mac_etype_used;   /* Used perfect match MAC/EtherType filters */
1849         u16 etype_used;       /* Used perfect EtherType filters */
1850         u16 mac_etype_free;   /* Un-used perfect match MAC/EtherType filters */
1851         u16 etype_free;       /* Un-used perfect EtherType filters */
1852 };
1853
1854 enum iavf_reset_type {
1855         IAVF_RESET_POR          = 0,
1856         IAVF_RESET_CORER        = 1,
1857         IAVF_RESET_GLOBR        = 2,
1858         IAVF_RESET_EMPR         = 3,
1859 };
1860
1861 /* IEEE 802.1AB LLDP Agent Variables from NVM */
1862 #define IAVF_NVM_LLDP_CFG_PTR   0x06
1863 #define IAVF_SR_LLDP_CFG_PTR    0x31
1864 struct iavf_lldp_variables {
1865         u16 length;
1866         u16 adminstatus;
1867         u16 msgfasttx;
1868         u16 msgtxinterval;
1869         u16 txparams;
1870         u16 timers;
1871         u16 crc8;
1872 };
1873
1874 /* Offsets into Alternate Ram */
1875 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
1876 #define IAVF_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
1877 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
1878 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
1879 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
1880 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
1881
1882 /* Alternate Ram Bandwidth Masks */
1883 #define IAVF_ALT_BW_VALUE_MASK          0xFF
1884 #define IAVF_ALT_BW_RELATIVE_MASK       0x40000000
1885 #define IAVF_ALT_BW_VALID_MASK          0x80000000
1886
1887 /* RSS Hash Table Size */
1888 #define IAVF_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
1889
1890 /* INPUT SET MASK for RSS, flow director, and flexible payload */
1891 #define IAVF_L3_SRC_SHIFT               47
1892 #define IAVF_L3_SRC_MASK                (0x3ULL << IAVF_L3_SRC_SHIFT)
1893 #define IAVF_L3_V6_SRC_SHIFT            43
1894 #define IAVF_L3_V6_SRC_MASK             (0xFFULL << IAVF_L3_V6_SRC_SHIFT)
1895 #define IAVF_L3_DST_SHIFT               35
1896 #define IAVF_L3_DST_MASK                (0x3ULL << IAVF_L3_DST_SHIFT)
1897 #define IAVF_L3_V6_DST_SHIFT            35
1898 #define IAVF_L3_V6_DST_MASK             (0xFFULL << IAVF_L3_V6_DST_SHIFT)
1899 #define IAVF_L4_SRC_SHIFT               34
1900 #define IAVF_L4_SRC_MASK                (0x1ULL << IAVF_L4_SRC_SHIFT)
1901 #define IAVF_L4_DST_SHIFT               33
1902 #define IAVF_L4_DST_MASK                (0x1ULL << IAVF_L4_DST_SHIFT)
1903 #define IAVF_VERIFY_TAG_SHIFT           31
1904 #define IAVF_VERIFY_TAG_MASK            (0x3ULL << IAVF_VERIFY_TAG_SHIFT)
1905
1906 #define IAVF_FLEX_50_SHIFT              13
1907 #define IAVF_FLEX_50_MASK               (0x1ULL << IAVF_FLEX_50_SHIFT)
1908 #define IAVF_FLEX_51_SHIFT              12
1909 #define IAVF_FLEX_51_MASK               (0x1ULL << IAVF_FLEX_51_SHIFT)
1910 #define IAVF_FLEX_52_SHIFT              11
1911 #define IAVF_FLEX_52_MASK               (0x1ULL << IAVF_FLEX_52_SHIFT)
1912 #define IAVF_FLEX_53_SHIFT              10
1913 #define IAVF_FLEX_53_MASK               (0x1ULL << IAVF_FLEX_53_SHIFT)
1914 #define IAVF_FLEX_54_SHIFT              9
1915 #define IAVF_FLEX_54_MASK               (0x1ULL << IAVF_FLEX_54_SHIFT)
1916 #define IAVF_FLEX_55_SHIFT              8
1917 #define IAVF_FLEX_55_MASK               (0x1ULL << IAVF_FLEX_55_SHIFT)
1918 #define IAVF_FLEX_56_SHIFT              7
1919 #define IAVF_FLEX_56_MASK               (0x1ULL << IAVF_FLEX_56_SHIFT)
1920 #define IAVF_FLEX_57_SHIFT              6
1921 #define IAVF_FLEX_57_MASK               (0x1ULL << IAVF_FLEX_57_SHIFT)
1922
1923 /* Version format for Dynamic Device Personalization(DDP) */
1924 struct iavf_ddp_version {
1925         u8 major;
1926         u8 minor;
1927         u8 update;
1928         u8 draft;
1929 };
1930
1931 #define IAVF_DDP_NAME_SIZE      32
1932
1933 /* Package header */
1934 struct iavf_package_header {
1935         struct iavf_ddp_version version;
1936         u32 segment_count;
1937         u32 segment_offset[1];
1938 };
1939
1940 /* Generic segment header */
1941 struct iavf_generic_seg_header {
1942 #define SEGMENT_TYPE_METADATA   0x00000001
1943 #define SEGMENT_TYPE_NOTES      0x00000002
1944 #define SEGMENT_TYPE_IAVF       0x00000011
1945 #define SEGMENT_TYPE_X722       0x00000012
1946         u32 type;
1947         struct iavf_ddp_version version;
1948         u32 size;
1949         char name[IAVF_DDP_NAME_SIZE];
1950 };
1951
1952 struct iavf_metadata_segment {
1953         struct iavf_generic_seg_header header;
1954         struct iavf_ddp_version version;
1955 #define IAVF_DDP_TRACKID_RDONLY         0
1956 #define IAVF_DDP_TRACKID_INVALID        0xFFFFFFFF
1957         u32 track_id;
1958         char name[IAVF_DDP_NAME_SIZE];
1959 };
1960
1961 struct iavf_device_id_entry {
1962         u32 vendor_dev_id;
1963         u32 sub_vendor_dev_id;
1964 };
1965
1966 struct iavf_profile_segment {
1967         struct iavf_generic_seg_header header;
1968         struct iavf_ddp_version version;
1969         char name[IAVF_DDP_NAME_SIZE];
1970         u32 device_table_count;
1971         struct iavf_device_id_entry device_table[1];
1972 };
1973
1974 struct iavf_section_table {
1975         u32 section_count;
1976         u32 section_offset[1];
1977 };
1978
1979 struct iavf_profile_section_header {
1980         u16 tbl_size;
1981         u16 data_end;
1982         struct {
1983 #define SECTION_TYPE_INFO       0x00000010
1984 #define SECTION_TYPE_MMIO       0x00000800
1985 #define SECTION_TYPE_RB_MMIO    0x00001800
1986 #define SECTION_TYPE_AQ         0x00000801
1987 #define SECTION_TYPE_RB_AQ      0x00001801
1988 #define SECTION_TYPE_NOTE       0x80000000
1989 #define SECTION_TYPE_NAME       0x80000001
1990 #define SECTION_TYPE_PROTO      0x80000002
1991 #define SECTION_TYPE_PCTYPE     0x80000003
1992 #define SECTION_TYPE_PTYPE      0x80000004
1993                 u32 type;
1994                 u32 offset;
1995                 u32 size;
1996         } section;
1997 };
1998
1999 struct iavf_profile_tlv_section_record {
2000         u8 rtype;
2001         u8 type;
2002         u16 len;
2003         u8 data[12];
2004 };
2005
2006 /* Generic AQ section in proflie */
2007 struct iavf_profile_aq_section {
2008         u16 opcode;
2009         u16 flags;
2010         u8  param[16];
2011         u16 datalen;
2012         u8  data[1];
2013 };
2014
2015 struct iavf_profile_info {
2016         u32 track_id;
2017         struct iavf_ddp_version version;
2018         u8 op;
2019 #define IAVF_DDP_ADD_TRACKID            0x01
2020 #define IAVF_DDP_REMOVE_TRACKID 0x02
2021         u8 reserved[7];
2022         u8 name[IAVF_DDP_NAME_SIZE];
2023 };
2024 #endif /* _IAVF_TYPE_H_ */