drivers/net/iavf/base/iavf_type.h

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2001-2019
   3  */
   4
   5 #ifndef _IAVF_TYPE_H_
   6 #define _IAVF_TYPE_H_
   7
   8 #include "iavf_status.h"
   9 #include "iavf_osdep.h"
  10 #include "iavf_register.h"
  11 #include "iavf_adminq.h"
  12 #include "iavf_devids.h"
  13
  14 #define IAVF_RXQ_CTX_DBUFF_SHIFT        7
  15
  16 #define UNREFERENCED_XPARAMETER
  17 #define UNREFERENCED_1PARAMETER(_p) (_p);
  18 #define UNREFERENCED_2PARAMETER(_p, _q) (_p); (_q);
  19 #define UNREFERENCED_3PARAMETER(_p, _q, _r) (_p); (_q); (_r);
  20 #define UNREFERENCED_4PARAMETER(_p, _q, _r, _s) (_p); (_q); (_r); (_s);
  21 #define UNREFERENCED_5PARAMETER(_p, _q, _r, _s, _t) (_p); (_q); (_r); (_s); (_t);
  22
  23 #define BIT(a) (1UL << (a))
  24 #define BIT_ULL(a) (1ULL << (a))
  25
  26 /* IAVF_MASK is a macro used on 32 bit registers */
  27 #define IAVF_MASK(mask, shift) (mask << shift)
  28
  29 #define IAVF_MAX_PF                     16
  30 #define IAVF_MAX_PF_VSI                 64
  31 #define IAVF_MAX_PF_QP                  128
  32 #define IAVF_MAX_VSI_QP                 16
  33 #define IAVF_MAX_VF_VSI                 4
  34 #define IAVF_MAX_CHAINED_RX_BUFFERS     5
  35
  36 /* something less than 1 minute */
  37 #define IAVF_HEARTBEAT_TIMEOUT          (HZ * 50)
  38
  39
  40 /* Check whether address is multicast. */
  41 #define IAVF_IS_MULTICAST(address) (bool)(((u8 *)(address))[0] & ((u8)0x01))
  42
  43 /* Check whether an address is broadcast. */
  44 #define IAVF_IS_BROADCAST(address)      \
  45         ((((u8 *)(address))[0] == ((u8)0xff)) && \
  46         (((u8 *)(address))[1] == ((u8)0xff)))
  47
  48
  49 /* forward declaration */
  50 struct iavf_hw;
  51 typedef void (*IAVF_ADMINQ_CALLBACK)(struct iavf_hw *, struct iavf_aq_desc *);
  52
  53 #define ETH_ALEN        6
  54 /* Data type manipulation macros. */
  55 #define IAVF_HI_DWORD(x)        ((u32)((((x) >> 16) >> 16) & 0xFFFFFFFF))
  56 #define IAVF_LO_DWORD(x)        ((u32)((x) & 0xFFFFFFFF))
  57
  58 #define IAVF_HI_WORD(x)         ((u16)(((x) >> 16) & 0xFFFF))
  59 #define IAVF_LO_WORD(x)         ((u16)((x) & 0xFFFF))
  60
  61 #define IAVF_HI_BYTE(x)         ((u8)(((x) >> 8) & 0xFF))
  62 #define IAVF_LO_BYTE(x)         ((u8)((x) & 0xFF))
  63
  64 /* Number of Transmit Descriptors must be a multiple of 8. */
  65 #define IAVF_REQ_TX_DESCRIPTOR_MULTIPLE 8
  66 /* Number of Receive Descriptors must be a multiple of 32 if
  67  * the number of descriptors is greater than 32.
  68  */
  69 #define IAVF_REQ_RX_DESCRIPTOR_MULTIPLE 32
  70
  71 #define IAVF_DESC_UNUSED(R)     \
  72         ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
  73         (R)->next_to_clean - (R)->next_to_use - 1)
  74
  75 /* bitfields for Tx queue mapping in QTX_CTL */
  76 #define IAVF_QTX_CTL_VF_QUEUE   0x0
  77 #define IAVF_QTX_CTL_VM_QUEUE   0x1
  78 #define IAVF_QTX_CTL_PF_QUEUE   0x2
  79
  80 /* debug masks - set these bits in hw->debug_mask to control output */
  81 enum iavf_debug_mask {
  82         IAVF_DEBUG_INIT                 = 0x00000001,
  83         IAVF_DEBUG_RELEASE              = 0x00000002,
  84
  85         IAVF_DEBUG_LINK                 = 0x00000010,
  86         IAVF_DEBUG_PHY                  = 0x00000020,
  87         IAVF_DEBUG_HMC                  = 0x00000040,
  88         IAVF_DEBUG_NVM                  = 0x00000080,
  89         IAVF_DEBUG_LAN                  = 0x00000100,
  90         IAVF_DEBUG_FLOW                 = 0x00000200,
  91         IAVF_DEBUG_DCB                  = 0x00000400,
  92         IAVF_DEBUG_DIAG                 = 0x00000800,
  93         IAVF_DEBUG_FD                   = 0x00001000,
  94         IAVF_DEBUG_PACKAGE              = 0x00002000,
  95
  96         IAVF_DEBUG_AQ_MESSAGE           = 0x01000000,
  97         IAVF_DEBUG_AQ_DESCRIPTOR        = 0x02000000,
  98         IAVF_DEBUG_AQ_DESC_BUFFER       = 0x04000000,
  99         IAVF_DEBUG_AQ_COMMAND           = 0x06000000,
 100         IAVF_DEBUG_AQ                   = 0x0F000000,
 101
 102         IAVF_DEBUG_USER                 = 0xF0000000,
 103
 104         IAVF_DEBUG_ALL                  = 0xFFFFFFFF
 105 };
 106
 107 /* PCI Bus Info */
 108 #define IAVF_PCI_LINK_STATUS            0xB2
 109 #define IAVF_PCI_LINK_WIDTH             0x3F0
 110 #define IAVF_PCI_LINK_WIDTH_1           0x10
 111 #define IAVF_PCI_LINK_WIDTH_2           0x20
 112 #define IAVF_PCI_LINK_WIDTH_4           0x40
 113 #define IAVF_PCI_LINK_WIDTH_8           0x80
 114 #define IAVF_PCI_LINK_SPEED             0xF
 115 #define IAVF_PCI_LINK_SPEED_2500        0x1
 116 #define IAVF_PCI_LINK_SPEED_5000        0x2
 117 #define IAVF_PCI_LINK_SPEED_8000        0x3
 118
 119 #define IAVF_MDIO_CLAUSE22_STCODE_MASK  IAVF_MASK(1, \
 120                                                   IAVF_GLGEN_MSCA_STCODE_SHIFT)
 121 #define IAVF_MDIO_CLAUSE22_OPCODE_WRITE_MASK    IAVF_MASK(1, \
 122                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 123 #define IAVF_MDIO_CLAUSE22_OPCODE_READ_MASK     IAVF_MASK(2, \
 124                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 125
 126 #define IAVF_MDIO_CLAUSE45_STCODE_MASK  IAVF_MASK(0, \
 127                                                   IAVF_GLGEN_MSCA_STCODE_SHIFT)
 128 #define IAVF_MDIO_CLAUSE45_OPCODE_ADDRESS_MASK  IAVF_MASK(0, \
 129                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 130 #define IAVF_MDIO_CLAUSE45_OPCODE_WRITE_MASK    IAVF_MASK(1, \
 131                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 132 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_INC_ADDR_MASK    IAVF_MASK(2, \
 133                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 134 #define IAVF_MDIO_CLAUSE45_OPCODE_READ_MASK     IAVF_MASK(3, \
 135                                                   IAVF_GLGEN_MSCA_OPCODE_SHIFT)
 136
 137 #define IAVF_PHY_COM_REG_PAGE                   0x1E
 138 #define IAVF_PHY_LED_LINK_MODE_MASK             0xF0
 139 #define IAVF_PHY_LED_MANUAL_ON                  0x100
 140 #define IAVF_PHY_LED_PROV_REG_1                 0xC430
 141 #define IAVF_PHY_LED_MODE_MASK                  0xFFFF
 142 #define IAVF_PHY_LED_MODE_ORIG                  0x80000000
 143
 144 /* Memory types */
 145 enum iavf_memset_type {
 146         IAVF_NONDMA_MEM = 0,
 147         IAVF_DMA_MEM
 148 };
 149
 150 /* Memcpy types */
 151 enum iavf_memcpy_type {
 152         IAVF_NONDMA_TO_NONDMA = 0,
 153         IAVF_NONDMA_TO_DMA,
 154         IAVF_DMA_TO_DMA,
 155         IAVF_DMA_TO_NONDMA
 156 };
 157
 158 /* These are structs for managing the hardware information and the operations.
 159  * The structures of function pointers are filled out at init time when we
 160  * know for sure exactly which hardware we're working with.  This gives us the
 161  * flexibility of using the same main driver code but adapting to slightly
 162  * different hardware needs as new parts are developed.  For this architecture,
 163  * the Firmware and AdminQ are intended to insulate the driver from most of the
 164  * future changes, but these structures will also do part of the job.
 165  */
 166 enum iavf_mac_type {
 167         IAVF_MAC_UNKNOWN = 0,
 168         IAVF_MAC_XL710,
 169         IAVF_MAC_VF,
 170         IAVF_MAC_X722,
 171         IAVF_MAC_X722_VF,
 172         IAVF_MAC_GENERIC,
 173 };
 174
 175 enum iavf_vsi_type {
 176         IAVF_VSI_MAIN   = 0,
 177         IAVF_VSI_VMDQ1  = 1,
 178         IAVF_VSI_VMDQ2  = 2,
 179         IAVF_VSI_CTRL   = 3,
 180         IAVF_VSI_FCOE   = 4,
 181         IAVF_VSI_MIRROR = 5,
 182         IAVF_VSI_SRIOV  = 6,
 183         IAVF_VSI_FDIR   = 7,
 184         IAVF_VSI_TYPE_UNKNOWN
 185 };
 186
 187 enum iavf_queue_type {
 188         IAVF_QUEUE_TYPE_RX = 0,
 189         IAVF_QUEUE_TYPE_TX,
 190         IAVF_QUEUE_TYPE_PE_CEQ,
 191         IAVF_QUEUE_TYPE_UNKNOWN
 192 };
 193
 194 #define IAVF_HW_CAP_MAX_GPIO                    30
 195 #define IAVF_HW_CAP_MDIO_PORT_MODE_MDIO         0
 196 #define IAVF_HW_CAP_MDIO_PORT_MODE_I2C          1
 197
 198 enum iavf_acpi_programming_method {
 199         IAVF_ACPI_PROGRAMMING_METHOD_HW_FVL = 0,
 200         IAVF_ACPI_PROGRAMMING_METHOD_AQC_FPK = 1
 201 };
 202
 203 #define IAVF_WOL_SUPPORT_MASK                   0x1
 204 #define IAVF_ACPI_PROGRAMMING_METHOD_MASK       0x2
 205 #define IAVF_PROXY_SUPPORT_MASK                 0x4
 206
 207 /* Capabilities of a PF or a VF or the whole device */
 208 struct iavf_hw_capabilities {
 209         /* Cloud filter modes:
 210          * Mode1: Filter on L4 port only
 211          * Mode2: Filter for non-tunneled traffic
 212          * Mode3: Filter for tunnel traffic
 213          */
 214 #define IAVF_CLOUD_FILTER_MODE1 0x6
 215 #define IAVF_CLOUD_FILTER_MODE2 0x7
 216 #define IAVF_CLOUD_FILTER_MODE3 0x8
 217 #define IAVF_SWITCH_MODE_MASK   0xF
 218
 219         bool dcb;
 220         bool fcoe;
 221         bool iwarp;
 222         u32 num_vsis;
 223         u32 num_rx_qp;
 224         u32 num_tx_qp;
 225         u32 base_queue;
 226         u32 num_msix_vectors_vf;
 227         bool apm_wol_support;
 228         enum iavf_acpi_programming_method acpi_prog_method;
 229         bool proxy_support;
 230 };
 231
 232 struct iavf_mac_info {
 233         enum iavf_mac_type type;
 234         u8 addr[ETH_ALEN];
 235         u8 perm_addr[ETH_ALEN];
 236         u8 san_addr[ETH_ALEN];
 237         u8 port_addr[ETH_ALEN];
 238         u16 max_fcoeq;
 239 };
 240
 241 #define IAVF_NVM_EXEC_GET_AQ_RESULT             0x0
 242 #define IAVF_NVM_EXEC_FEATURES                  0xe
 243 #define IAVF_NVM_EXEC_STATUS                    0xf
 244
 245 /* NVMUpdate features API */
 246 #define IAVF_NVMUPD_FEATURES_API_VER_MAJOR              0
 247 #define IAVF_NVMUPD_FEATURES_API_VER_MINOR              14
 248 #define IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN     12
 249
 250 #define IAVF_NVMUPD_FEATURE_FLAT_NVM_SUPPORT            BIT(0)
 251
 252 struct iavf_nvmupd_features {
 253         u8 major;
 254         u8 minor;
 255         u16 size;
 256         u8 features[IAVF_NVMUPD_FEATURES_API_FEATURES_ARRAY_LEN];
 257 };
 258
 259 #define IAVF_MODULE_SFF_DIAG_CAPAB      0x40
 260 /* PCI bus types */
 261 enum iavf_bus_type {
 262         iavf_bus_type_unknown = 0,
 263         iavf_bus_type_pci,
 264         iavf_bus_type_pcix,
 265         iavf_bus_type_pci_express,
 266         iavf_bus_type_reserved
 267 };
 268
 269 /* PCI bus speeds */
 270 enum iavf_bus_speed {
 271         iavf_bus_speed_unknown  = 0,
 272         iavf_bus_speed_33       = 33,
 273         iavf_bus_speed_66       = 66,
 274         iavf_bus_speed_100      = 100,
 275         iavf_bus_speed_120      = 120,
 276         iavf_bus_speed_133      = 133,
 277         iavf_bus_speed_2500     = 2500,
 278         iavf_bus_speed_5000     = 5000,
 279         iavf_bus_speed_8000     = 8000,
 280         iavf_bus_speed_reserved
 281 };
 282
 283 /* PCI bus widths */
 284 enum iavf_bus_width {
 285         iavf_bus_width_unknown  = 0,
 286         iavf_bus_width_pcie_x1  = 1,
 287         iavf_bus_width_pcie_x2  = 2,
 288         iavf_bus_width_pcie_x4  = 4,
 289         iavf_bus_width_pcie_x8  = 8,
 290         iavf_bus_width_32       = 32,
 291         iavf_bus_width_64       = 64,
 292         iavf_bus_width_reserved
 293 };
 294
 295 /* Bus parameters */
 296 struct iavf_bus_info {
 297         enum iavf_bus_speed speed;
 298         enum iavf_bus_width width;
 299         enum iavf_bus_type type;
 300
 301         u16 func;
 302         u16 device;
 303         u16 lan_id;
 304         u16 bus_id;
 305 };
 306
 307 #define IAVF_MAX_USER_PRIORITY          8
 308 #define IAVF_TLV_STATUS_OPER            0x1
 309 #define IAVF_TLV_STATUS_SYNC            0x2
 310 #define IAVF_TLV_STATUS_ERR             0x4
 311 #define IAVF_CEE_OPER_MAX_APPS          3
 312 #define IAVF_APP_PROTOID_FCOE           0x8906
 313 #define IAVF_APP_PROTOID_ISCSI          0x0cbc
 314 #define IAVF_APP_PROTOID_FIP            0x8914
 315 #define IAVF_APP_SEL_ETHTYPE            0x1
 316 #define IAVF_APP_SEL_TCPIP              0x2
 317 #define IAVF_CEE_APP_SEL_ETHTYPE        0x0
 318 #define IAVF_CEE_APP_SEL_TCPIP          0x1
 319
 320 /* Port hardware description */
 321 struct iavf_hw {
 322         u8 *hw_addr;
 323         void *back;
 324
 325         /* subsystem structs */
 326         struct iavf_mac_info mac;
 327         struct iavf_bus_info bus;
 328
 329         /* pci info */
 330         u16 device_id;
 331         u16 vendor_id;
 332         u16 subsystem_device_id;
 333         u16 subsystem_vendor_id;
 334         u8 revision_id;
 335
 336         /* capabilities for entire device and PCI func */
 337         struct iavf_hw_capabilities dev_caps;
 338
 339         /* Admin Queue info */
 340         struct iavf_adminq_info aq;
 341
 342         /* WoL and proxy support */
 343         u16 num_wol_proxy_filters;
 344         u16 wol_proxy_vsi_seid;
 345
 346 #define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
 347 #define IAVF_HW_FLAG_802_1AD_CAPABLE        BIT_ULL(1)
 348 #define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE  BIT_ULL(2)
 349 #define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
 350 #define IAVF_HW_FLAG_FW_LLDP_STOPPABLE      BIT_ULL(4)
 351         u64 flags;
 352
 353         /* NVMUpdate features */
 354         struct iavf_nvmupd_features nvmupd_features;
 355
 356         /* debug mask */
 357         u32 debug_mask;
 358         char err_str[16];
 359 };
 360
 361 struct iavf_driver_version {
 362         u8 major_version;
 363         u8 minor_version;
 364         u8 build_version;
 365         u8 subbuild_version;
 366         u8 driver_string[32];
 367 };
 368
 369 /* RX Descriptors */
 370 union iavf_16byte_rx_desc {
 371         struct {
 372                 __le64 pkt_addr; /* Packet buffer address */
 373                 __le64 hdr_addr; /* Header buffer address */
 374         } read;
 375         struct {
 376                 struct {
 377                         struct {
 378                                 union {
 379                                         __le16 mirroring_status;
 380                                         __le16 fcoe_ctx_id;
 381                                 } mirr_fcoe;
 382                                 __le16 l2tag1;
 383                         } lo_dword;
 384                         union {
 385                                 __le32 rss; /* RSS Hash */
 386                                 __le32 fd_id; /* Flow director filter id */
 387                                 __le32 fcoe_param; /* FCoE DDP Context id */
 388                         } hi_dword;
 389                 } qword0;
 390                 struct {
 391                         /* ext status/error/pktype/length */
 392                         __le64 status_error_len;
 393                 } qword1;
 394         } wb;  /* writeback */
 395 };
 396
 397 union iavf_32byte_rx_desc {
 398         struct {
 399                 __le64  pkt_addr; /* Packet buffer address */
 400                 __le64  hdr_addr; /* Header buffer address */
 401                         /* bit 0 of hdr_buffer_addr is DD bit */
 402                 __le64  rsvd1;
 403                 __le64  rsvd2;
 404         } read;
 405         struct {
 406                 struct {
 407                         struct {
 408                                 union {
 409                                         __le16 mirroring_status;
 410                                         __le16 fcoe_ctx_id;
 411                                 } mirr_fcoe;
 412                                 __le16 l2tag1;
 413                         } lo_dword;
 414                         union {
 415                                 __le32 rss; /* RSS Hash */
 416                                 __le32 fcoe_param; /* FCoE DDP Context id */
 417                                 /* Flow director filter id in case of
 418                                  * Programming status desc WB
 419                                  */
 420                                 __le32 fd_id;
 421                         } hi_dword;
 422                 } qword0;
 423                 struct {
 424                         /* status/error/pktype/length */
 425                         __le64 status_error_len;
 426                 } qword1;
 427                 struct {
 428                         __le16 ext_status; /* extended status */
 429                         __le16 rsvd;
 430                         __le16 l2tag2_1;
 431                         __le16 l2tag2_2;
 432                 } qword2;
 433                 struct {
 434                         union {
 435                                 __le32 flex_bytes_lo;
 436                                 __le32 pe_status;
 437                         } lo_dword;
 438                         union {
 439                                 __le32 flex_bytes_hi;
 440                                 __le32 fd_id;
 441                         } hi_dword;
 442                 } qword3;
 443         } wb;  /* writeback */
 444 };
 445
 446 #define IAVF_RXD_QW0_MIRROR_STATUS_SHIFT        8
 447 #define IAVF_RXD_QW0_MIRROR_STATUS_MASK (0x3FUL << \
 448                                          IAVF_RXD_QW0_MIRROR_STATUS_SHIFT)
 449 #define IAVF_RXD_QW0_FCOEINDX_SHIFT     0
 450 #define IAVF_RXD_QW0_FCOEINDX_MASK      (0xFFFUL << \
 451                                          IAVF_RXD_QW0_FCOEINDX_SHIFT)
 452
 453 enum iavf_rx_desc_status_bits {
 454         /* Note: These are predefined bit offsets */
 455         IAVF_RX_DESC_STATUS_DD_SHIFT            = 0,
 456         IAVF_RX_DESC_STATUS_EOF_SHIFT           = 1,
 457         IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT       = 2,
 458         IAVF_RX_DESC_STATUS_L3L4P_SHIFT         = 3,
 459         IAVF_RX_DESC_STATUS_CRCP_SHIFT          = 4,
 460         IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT      = 5, /* 2 BITS */
 461         IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT     = 7,
 462         IAVF_RX_DESC_STATUS_EXT_UDP_0_SHIFT     = 8,
 463
 464         IAVF_RX_DESC_STATUS_UMBCAST_SHIFT       = 9, /* 2 BITS */
 465         IAVF_RX_DESC_STATUS_FLM_SHIFT           = 11,
 466         IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT       = 12, /* 2 BITS */
 467         IAVF_RX_DESC_STATUS_LPBK_SHIFT          = 14,
 468         IAVF_RX_DESC_STATUS_IPV6EXADD_SHIFT     = 15,
 469         IAVF_RX_DESC_STATUS_RESERVED_SHIFT      = 16, /* 2 BITS */
 470         IAVF_RX_DESC_STATUS_INT_UDP_0_SHIFT     = 18,
 471         IAVF_RX_DESC_STATUS_LAST /* this entry must be last!!! */
 472 };
 473
 474 #define IAVF_RXD_QW1_STATUS_SHIFT       0
 475 #define IAVF_RXD_QW1_STATUS_MASK        ((BIT(IAVF_RX_DESC_STATUS_LAST) - 1) \
 476                                          << IAVF_RXD_QW1_STATUS_SHIFT)
 477
 478 #define IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT IAVF_RX_DESC_STATUS_TSYNINDX_SHIFT
 479 #define IAVF_RXD_QW1_STATUS_TSYNINDX_MASK  (0x3UL << \
 480                                             IAVF_RXD_QW1_STATUS_TSYNINDX_SHIFT)
 481
 482 #define IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT IAVF_RX_DESC_STATUS_TSYNVALID_SHIFT
 483 #define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK   BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
 484
 485 #define IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT       IAVF_RX_DESC_STATUS_UMBCAST
 486 #define IAVF_RXD_QW1_STATUS_UMBCAST_MASK        (0x3UL << \
 487                                          IAVF_RXD_QW1_STATUS_UMBCAST_SHIFT)
 488
 489 enum iavf_rx_desc_fltstat_values {
 490         IAVF_RX_DESC_FLTSTAT_NO_DATA    = 0,
 491         IAVF_RX_DESC_FLTSTAT_RSV_FD_ID  = 1, /* 16byte desc? FD_ID : RSV */
 492         IAVF_RX_DESC_FLTSTAT_RSV        = 2,
 493         IAVF_RX_DESC_FLTSTAT_RSS_HASH   = 3,
 494 };
 495
 496 #define IAVF_RXD_PACKET_TYPE_UNICAST    0
 497 #define IAVF_RXD_PACKET_TYPE_MULTICAST  1
 498 #define IAVF_RXD_PACKET_TYPE_BROADCAST  2
 499 #define IAVF_RXD_PACKET_TYPE_MIRRORED   3
 500
 501 #define IAVF_RXD_QW1_ERROR_SHIFT        19
 502 #define IAVF_RXD_QW1_ERROR_MASK         (0xFFUL << IAVF_RXD_QW1_ERROR_SHIFT)
 503
 504 enum iavf_rx_desc_error_bits {
 505         /* Note: These are predefined bit offsets */
 506         IAVF_RX_DESC_ERROR_RXE_SHIFT            = 0,
 507         IAVF_RX_DESC_ERROR_RECIPE_SHIFT         = 1,
 508         IAVF_RX_DESC_ERROR_HBO_SHIFT            = 2,
 509         IAVF_RX_DESC_ERROR_L3L4E_SHIFT          = 3, /* 3 BITS */
 510         IAVF_RX_DESC_ERROR_IPE_SHIFT            = 3,
 511         IAVF_RX_DESC_ERROR_L4E_SHIFT            = 4,
 512         IAVF_RX_DESC_ERROR_EIPE_SHIFT           = 5,
 513         IAVF_RX_DESC_ERROR_OVERSIZE_SHIFT       = 6,
 514         IAVF_RX_DESC_ERROR_PPRS_SHIFT           = 7
 515 };
 516
 517 enum iavf_rx_desc_error_l3l4e_fcoe_masks {
 518         IAVF_RX_DESC_ERROR_L3L4E_NONE           = 0,
 519         IAVF_RX_DESC_ERROR_L3L4E_PROT           = 1,
 520         IAVF_RX_DESC_ERROR_L3L4E_FC             = 2,
 521         IAVF_RX_DESC_ERROR_L3L4E_DMAC_ERR       = 3,
 522         IAVF_RX_DESC_ERROR_L3L4E_DMAC_WARN      = 4
 523 };
 524
 525 #define IAVF_RXD_QW1_PTYPE_SHIFT        30
 526 #define IAVF_RXD_QW1_PTYPE_MASK         (0xFFULL << IAVF_RXD_QW1_PTYPE_SHIFT)
 527
 528 /* Packet type non-ip values */
 529 enum iavf_rx_l2_ptype {
 530         IAVF_RX_PTYPE_L2_RESERVED                       = 0,
 531         IAVF_RX_PTYPE_L2_MAC_PAY2                       = 1,
 532         IAVF_RX_PTYPE_L2_TIMESYNC_PAY2                  = 2,
 533         IAVF_RX_PTYPE_L2_FIP_PAY2                       = 3,
 534         IAVF_RX_PTYPE_L2_OUI_PAY2                       = 4,
 535         IAVF_RX_PTYPE_L2_MACCNTRL_PAY2                  = 5,
 536         IAVF_RX_PTYPE_L2_LLDP_PAY2                      = 6,
 537         IAVF_RX_PTYPE_L2_ECP_PAY2                       = 7,
 538         IAVF_RX_PTYPE_L2_EVB_PAY2                       = 8,
 539         IAVF_RX_PTYPE_L2_QCN_PAY2                       = 9,
 540         IAVF_RX_PTYPE_L2_EAPOL_PAY2                     = 10,
 541         IAVF_RX_PTYPE_L2_ARP                            = 11,
 542         IAVF_RX_PTYPE_L2_FCOE_PAY3                      = 12,
 543         IAVF_RX_PTYPE_L2_FCOE_FCDATA_PAY3               = 13,
 544         IAVF_RX_PTYPE_L2_FCOE_FCRDY_PAY3                = 14,
 545         IAVF_RX_PTYPE_L2_FCOE_FCRSP_PAY3                = 15,
 546         IAVF_RX_PTYPE_L2_FCOE_FCOTHER_PA                = 16,
 547         IAVF_RX_PTYPE_L2_FCOE_VFT_PAY3                  = 17,
 548         IAVF_RX_PTYPE_L2_FCOE_VFT_FCDATA                = 18,
 549         IAVF_RX_PTYPE_L2_FCOE_VFT_FCRDY                 = 19,
 550         IAVF_RX_PTYPE_L2_FCOE_VFT_FCRSP                 = 20,
 551         IAVF_RX_PTYPE_L2_FCOE_VFT_FCOTHER               = 21,
 552         IAVF_RX_PTYPE_GRENAT4_MAC_PAY3                  = 58,
 553         IAVF_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4    = 87,
 554         IAVF_RX_PTYPE_GRENAT6_MAC_PAY3                  = 124,
 555         IAVF_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4    = 153
 556 };
 557
 558 struct iavf_rx_ptype_decoded {
 559         u32 ptype:8;
 560         u32 known:1;
 561         u32 outer_ip:1;
 562         u32 outer_ip_ver:1;
 563         u32 outer_frag:1;
 564         u32 tunnel_type:3;
 565         u32 tunnel_end_prot:2;
 566         u32 tunnel_end_frag:1;
 567         u32 inner_prot:4;
 568         u32 payload_layer:3;
 569 };
 570
 571 enum iavf_rx_ptype_outer_ip {
 572         IAVF_RX_PTYPE_OUTER_L2  = 0,
 573         IAVF_RX_PTYPE_OUTER_IP  = 1
 574 };
 575
 576 enum iavf_rx_ptype_outer_ip_ver {
 577         IAVF_RX_PTYPE_OUTER_NONE        = 0,
 578         IAVF_RX_PTYPE_OUTER_IPV4        = 0,
 579         IAVF_RX_PTYPE_OUTER_IPV6        = 1
 580 };
 581
 582 enum iavf_rx_ptype_outer_fragmented {
 583         IAVF_RX_PTYPE_NOT_FRAG  = 0,
 584         IAVF_RX_PTYPE_FRAG      = 1
 585 };
 586
 587 enum iavf_rx_ptype_tunnel_type {
 588         IAVF_RX_PTYPE_TUNNEL_NONE               = 0,
 589         IAVF_RX_PTYPE_TUNNEL_IP_IP              = 1,
 590         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT          = 2,
 591         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC      = 3,
 592         IAVF_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
 593 };
 594
 595 enum iavf_rx_ptype_tunnel_end_prot {
 596         IAVF_RX_PTYPE_TUNNEL_END_NONE   = 0,
 597         IAVF_RX_PTYPE_TUNNEL_END_IPV4   = 1,
 598         IAVF_RX_PTYPE_TUNNEL_END_IPV6   = 2,
 599 };
 600
 601 enum iavf_rx_ptype_inner_prot {
 602         IAVF_RX_PTYPE_INNER_PROT_NONE           = 0,
 603         IAVF_RX_PTYPE_INNER_PROT_UDP            = 1,
 604         IAVF_RX_PTYPE_INNER_PROT_TCP            = 2,
 605         IAVF_RX_PTYPE_INNER_PROT_SCTP           = 3,
 606         IAVF_RX_PTYPE_INNER_PROT_ICMP           = 4,
 607         IAVF_RX_PTYPE_INNER_PROT_TIMESYNC       = 5
 608 };
 609
 610 enum iavf_rx_ptype_payload_layer {
 611         IAVF_RX_PTYPE_PAYLOAD_LAYER_NONE        = 0,
 612         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY2        = 1,
 613         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY3        = 2,
 614         IAVF_RX_PTYPE_PAYLOAD_LAYER_PAY4        = 3,
 615 };
 616
 617 #define IAVF_RX_PTYPE_BIT_MASK          0x0FFFFFFF
 618 #define IAVF_RX_PTYPE_SHIFT             56
 619
 620 #define IAVF_RXD_QW1_LENGTH_PBUF_SHIFT  38
 621 #define IAVF_RXD_QW1_LENGTH_PBUF_MASK   (0x3FFFULL << \
 622                                          IAVF_RXD_QW1_LENGTH_PBUF_SHIFT)
 623
 624 #define IAVF_RXD_QW1_LENGTH_HBUF_SHIFT  52
 625 #define IAVF_RXD_QW1_LENGTH_HBUF_MASK   (0x7FFULL << \
 626                                          IAVF_RXD_QW1_LENGTH_HBUF_SHIFT)
 627
 628 #define IAVF_RXD_QW1_LENGTH_SPH_SHIFT   63
 629 #define IAVF_RXD_QW1_LENGTH_SPH_MASK    BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
 630
 631 #define IAVF_RXD_QW1_NEXTP_SHIFT        38
 632 #define IAVF_RXD_QW1_NEXTP_MASK         (0x1FFFULL << IAVF_RXD_QW1_NEXTP_SHIFT)
 633
 634 #define IAVF_RXD_QW2_EXT_STATUS_SHIFT   0
 635 #define IAVF_RXD_QW2_EXT_STATUS_MASK    (0xFFFFFUL << \
 636                                          IAVF_RXD_QW2_EXT_STATUS_SHIFT)
 637
 638 enum iavf_rx_desc_ext_status_bits {
 639         /* Note: These are predefined bit offsets */
 640         IAVF_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT   = 0,
 641         IAVF_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT   = 1,
 642         IAVF_RX_DESC_EXT_STATUS_FLEXBL_SHIFT    = 2, /* 2 BITS */
 643         IAVF_RX_DESC_EXT_STATUS_FLEXBH_SHIFT    = 4, /* 2 BITS */
 644         IAVF_RX_DESC_EXT_STATUS_FDLONGB_SHIFT   = 9,
 645         IAVF_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
 646         IAVF_RX_DESC_EXT_STATUS_PELONGB_SHIFT   = 11,
 647 };
 648
 649 #define IAVF_RXD_QW2_L2TAG2_SHIFT       0
 650 #define IAVF_RXD_QW2_L2TAG2_MASK        (0xFFFFUL << IAVF_RXD_QW2_L2TAG2_SHIFT)
 651
 652 #define IAVF_RXD_QW2_L2TAG3_SHIFT       16
 653 #define IAVF_RXD_QW2_L2TAG3_MASK        (0xFFFFUL << IAVF_RXD_QW2_L2TAG3_SHIFT)
 654
 655 enum iavf_rx_desc_pe_status_bits {
 656         /* Note: These are predefined bit offsets */
 657         IAVF_RX_DESC_PE_STATUS_QPID_SHIFT       = 0, /* 18 BITS */
 658         IAVF_RX_DESC_PE_STATUS_L4PORT_SHIFT     = 0, /* 16 BITS */
 659         IAVF_RX_DESC_PE_STATUS_IPINDEX_SHIFT    = 16, /* 8 BITS */
 660         IAVF_RX_DESC_PE_STATUS_QPIDHIT_SHIFT    = 24,
 661         IAVF_RX_DESC_PE_STATUS_APBVTHIT_SHIFT   = 25,
 662         IAVF_RX_DESC_PE_STATUS_PORTV_SHIFT      = 26,
 663         IAVF_RX_DESC_PE_STATUS_URG_SHIFT        = 27,
 664         IAVF_RX_DESC_PE_STATUS_IPFRAG_SHIFT     = 28,
 665         IAVF_RX_DESC_PE_STATUS_IPOPT_SHIFT      = 29
 666 };
 667
 668 #define IAVF_RX_PROG_STATUS_DESC_LENGTH_SHIFT           38
 669 #define IAVF_RX_PROG_STATUS_DESC_LENGTH                 0x2000000
 670
 671 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT       2
 672 #define IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_MASK        (0x7UL << \
 673                                 IAVF_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
 674
 675 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT       0
 676 #define IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_MASK        (0x7FFFUL << \
 677                                 IAVF_RX_PROG_STATUS_DESC_QW1_STATUS_SHIFT)
 678
 679 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT        19
 680 #define IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_MASK         (0x3FUL << \
 681                                 IAVF_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
 682
 683 enum iavf_rx_prog_status_desc_status_bits {
 684         /* Note: These are predefined bit offsets */
 685         IAVF_RX_PROG_STATUS_DESC_DD_SHIFT       = 0,
 686         IAVF_RX_PROG_STATUS_DESC_PROG_ID_SHIFT  = 2 /* 3 BITS */
 687 };
 688
 689 enum iavf_rx_prog_status_desc_prog_id_masks {
 690         IAVF_RX_PROG_STATUS_DESC_FD_FILTER_STATUS       = 1,
 691         IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS  = 2,
 692         IAVF_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS  = 4,
 693 };
 694
 695 enum iavf_rx_prog_status_desc_error_bits {
 696         /* Note: These are predefined bit offsets */
 697         IAVF_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT      = 0,
 698         IAVF_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT      = 1,
 699         IAVF_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT    = 2,
 700         IAVF_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT    = 3
 701 };
 702
 703 #define IAVF_TWO_BIT_MASK       0x3
 704 #define IAVF_THREE_BIT_MASK     0x7
 705 #define IAVF_FOUR_BIT_MASK      0xF
 706 #define IAVF_EIGHTEEN_BIT_MASK  0x3FFFF
 707
 708 /* TX Descriptor */
 709 struct iavf_tx_desc {
 710         __le64 buffer_addr; /* Address of descriptor's data buf */
 711         __le64 cmd_type_offset_bsz;
 712 };
 713
 714 #define IAVF_TXD_QW1_DTYPE_SHIFT        0
 715 #define IAVF_TXD_QW1_DTYPE_MASK         (0xFUL << IAVF_TXD_QW1_DTYPE_SHIFT)
 716
 717 enum iavf_tx_desc_dtype_value {
 718         IAVF_TX_DESC_DTYPE_DATA         = 0x0,
 719         IAVF_TX_DESC_DTYPE_NOP          = 0x1, /* same as Context desc */
 720         IAVF_TX_DESC_DTYPE_CONTEXT      = 0x1,
 721         IAVF_TX_DESC_DTYPE_FCOE_CTX     = 0x2,
 722         IAVF_TX_DESC_DTYPE_FILTER_PROG  = 0x8,
 723         IAVF_TX_DESC_DTYPE_DDP_CTX      = 0x9,
 724         IAVF_TX_DESC_DTYPE_FLEX_DATA    = 0xB,
 725         IAVF_TX_DESC_DTYPE_FLEX_CTX_1   = 0xC,
 726         IAVF_TX_DESC_DTYPE_FLEX_CTX_2   = 0xD,
 727         IAVF_TX_DESC_DTYPE_DESC_DONE    = 0xF
 728 };
 729
 730 #define IAVF_TXD_QW1_CMD_SHIFT  4
 731 #define IAVF_TXD_QW1_CMD_MASK   (0x3FFUL << IAVF_TXD_QW1_CMD_SHIFT)
 732
 733 enum iavf_tx_desc_cmd_bits {
 734         IAVF_TX_DESC_CMD_EOP                    = 0x0001,
 735         IAVF_TX_DESC_CMD_RS                     = 0x0002,
 736         IAVF_TX_DESC_CMD_ICRC                   = 0x0004,
 737         IAVF_TX_DESC_CMD_IL2TAG1                = 0x0008,
 738         IAVF_TX_DESC_CMD_DUMMY                  = 0x0010,
 739         IAVF_TX_DESC_CMD_IIPT_NONIP             = 0x0000, /* 2 BITS */
 740         IAVF_TX_DESC_CMD_IIPT_IPV6              = 0x0020, /* 2 BITS */
 741         IAVF_TX_DESC_CMD_IIPT_IPV4              = 0x0040, /* 2 BITS */
 742         IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM         = 0x0060, /* 2 BITS */
 743         IAVF_TX_DESC_CMD_FCOET                  = 0x0080,
 744         IAVF_TX_DESC_CMD_L4T_EOFT_UNK           = 0x0000, /* 2 BITS */
 745         IAVF_TX_DESC_CMD_L4T_EOFT_TCP           = 0x0100, /* 2 BITS */
 746         IAVF_TX_DESC_CMD_L4T_EOFT_SCTP          = 0x0200, /* 2 BITS */
 747         IAVF_TX_DESC_CMD_L4T_EOFT_UDP           = 0x0300, /* 2 BITS */
 748         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_N         = 0x0000, /* 2 BITS */
 749         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_T         = 0x0100, /* 2 BITS */
 750         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_NI        = 0x0200, /* 2 BITS */
 751         IAVF_TX_DESC_CMD_L4T_EOFT_EOF_A         = 0x0300, /* 2 BITS */
 752 };
 753
 754 #define IAVF_TXD_QW1_OFFSET_SHIFT       16
 755 #define IAVF_TXD_QW1_OFFSET_MASK        (0x3FFFFULL << \
 756                                          IAVF_TXD_QW1_OFFSET_SHIFT)
 757
 758 enum iavf_tx_desc_length_fields {
 759         /* Note: These are predefined bit offsets */
 760         IAVF_TX_DESC_LENGTH_MACLEN_SHIFT        = 0, /* 7 BITS */
 761         IAVF_TX_DESC_LENGTH_IPLEN_SHIFT         = 7, /* 7 BITS */
 762         IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT     = 14 /* 4 BITS */
 763 };
 764
 765 #define IAVF_TXD_QW1_MACLEN_MASK (0x7FUL << IAVF_TX_DESC_LENGTH_MACLEN_SHIFT)
 766 #define IAVF_TXD_QW1_IPLEN_MASK  (0x7FUL << IAVF_TX_DESC_LENGTH_IPLEN_SHIFT)
 767 #define IAVF_TXD_QW1_L4LEN_MASK  (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 768 #define IAVF_TXD_QW1_FCLEN_MASK  (0xFUL << IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT)
 769
 770 #define IAVF_TXD_QW1_TX_BUF_SZ_SHIFT    34
 771 #define IAVF_TXD_QW1_TX_BUF_SZ_MASK     (0x3FFFULL << \
 772                                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT)
 773
 774 #define IAVF_TXD_QW1_L2TAG1_SHIFT       48
 775 #define IAVF_TXD_QW1_L2TAG1_MASK        (0xFFFFULL << IAVF_TXD_QW1_L2TAG1_SHIFT)
 776
 777 /* Context descriptors */
 778 struct iavf_tx_context_desc {
 779         __le32 tunneling_params;
 780         __le16 l2tag2;
 781         __le16 rsvd;
 782         __le64 type_cmd_tso_mss;
 783 };
 784
 785 #define IAVF_TXD_CTX_QW1_DTYPE_SHIFT    0
 786 #define IAVF_TXD_CTX_QW1_DTYPE_MASK     (0xFUL << IAVF_TXD_CTX_QW1_DTYPE_SHIFT)
 787
 788 #define IAVF_TXD_CTX_QW1_CMD_SHIFT      4
 789 #define IAVF_TXD_CTX_QW1_CMD_MASK       (0xFFFFUL << IAVF_TXD_CTX_QW1_CMD_SHIFT)
 790
 791 enum iavf_tx_ctx_desc_cmd_bits {
 792         IAVF_TX_CTX_DESC_TSO            = 0x01,
 793         IAVF_TX_CTX_DESC_TSYN           = 0x02,
 794         IAVF_TX_CTX_DESC_IL2TAG2        = 0x04,
 795         IAVF_TX_CTX_DESC_IL2TAG2_IL2H   = 0x08,
 796         IAVF_TX_CTX_DESC_SWTCH_NOTAG    = 0x00,
 797         IAVF_TX_CTX_DESC_SWTCH_UPLINK   = 0x10,
 798         IAVF_TX_CTX_DESC_SWTCH_LOCAL    = 0x20,
 799         IAVF_TX_CTX_DESC_SWTCH_VSI      = 0x30,
 800         IAVF_TX_CTX_DESC_SWPE           = 0x40
 801 };
 802
 803 struct iavf_nop_desc {
 804         __le64 rsvd;
 805         __le64 dtype_cmd;
 806 };
 807
 808 #define IAVF_TXD_NOP_QW1_DTYPE_SHIFT    0
 809 #define IAVF_TXD_NOP_QW1_DTYPE_MASK     (0xFUL << IAVF_TXD_NOP_QW1_DTYPE_SHIFT)
 810
 811 #define IAVF_TXD_NOP_QW1_CMD_SHIFT      4
 812 #define IAVF_TXD_NOP_QW1_CMD_MASK       (0x7FUL << IAVF_TXD_NOP_QW1_CMD_SHIFT)
 813
 814 enum iavf_tx_nop_desc_cmd_bits {
 815         /* Note: These are predefined bit offsets */
 816         IAVF_TX_NOP_DESC_EOP_SHIFT      = 0,
 817         IAVF_TX_NOP_DESC_RS_SHIFT       = 1,
 818         IAVF_TX_NOP_DESC_RSV_SHIFT      = 2 /* 5 bits */
 819 };
 820
 821 /* Packet Classifier Types for filters */
 822 enum iavf_filter_pctype {
 823         /* Note: Values 0-28 are reserved for future use.
 824          * Value 29, 30, 32 are not supported on XL710 and X710.
 825          */
 826         IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP        = 29,
 827         IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP      = 30,
 828         IAVF_FILTER_PCTYPE_NONF_IPV4_UDP                = 31,
 829         IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK     = 32,
 830         IAVF_FILTER_PCTYPE_NONF_IPV4_TCP                = 33,
 831         IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP               = 34,
 832         IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER              = 35,
 833         IAVF_FILTER_PCTYPE_FRAG_IPV4                    = 36,
 834         /* Note: Values 37-38 are reserved for future use.
 835          * Value 39, 40, 42 are not supported on XL710 and X710.
 836          */
 837         IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP        = 39,
 838         IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP      = 40,
 839         IAVF_FILTER_PCTYPE_NONF_IPV6_UDP                = 41,
 840         IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK     = 42,
 841         IAVF_FILTER_PCTYPE_NONF_IPV6_TCP                = 43,
 842         IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP               = 44,
 843         IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER              = 45,
 844         IAVF_FILTER_PCTYPE_FRAG_IPV6                    = 46,
 845         /* Note: Value 47 is reserved for future use */
 846         IAVF_FILTER_PCTYPE_FCOE_OX                      = 48,
 847         IAVF_FILTER_PCTYPE_FCOE_RX                      = 49,
 848         IAVF_FILTER_PCTYPE_FCOE_OTHER                   = 50,
 849         /* Note: Values 51-62 are reserved for future use */
 850         IAVF_FILTER_PCTYPE_L2_PAYLOAD                   = 63,
 851 };
 852
 853 #define IAVF_TXD_FLTR_QW1_DTYPE_SHIFT   0
 854 #define IAVF_TXD_FLTR_QW1_DTYPE_MASK    (0xFUL << IAVF_TXD_FLTR_QW1_DTYPE_SHIFT)
 855
 856 #define IAVF_TXD_FLTR_QW1_ATR_SHIFT     (0xEULL + \
 857                                          IAVF_TXD_FLTR_QW1_CMD_SHIFT)
 858 #define IAVF_TXD_FLTR_QW1_ATR_MASK      BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
 859
 860
 861 #define IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT  30
 862 #define IAVF_TXD_CTX_QW1_TSO_LEN_MASK   (0x3FFFFULL << \
 863                                          IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT)
 864
 865 #define IAVF_TXD_CTX_QW1_MSS_SHIFT      50
 866 #define IAVF_TXD_CTX_QW1_MSS_MASK       (0x3FFFULL << \
 867                                          IAVF_TXD_CTX_QW1_MSS_SHIFT)
 868
 869 #define IAVF_TXD_CTX_QW1_VSI_SHIFT      50
 870 #define IAVF_TXD_CTX_QW1_VSI_MASK       (0x1FFULL << IAVF_TXD_CTX_QW1_VSI_SHIFT)
 871
 872 #define IAVF_TXD_CTX_QW0_EXT_IP_SHIFT   0
 873 #define IAVF_TXD_CTX_QW0_EXT_IP_MASK    (0x3ULL << \
 874                                          IAVF_TXD_CTX_QW0_EXT_IP_SHIFT)
 875
 876 enum iavf_tx_ctx_desc_eipt_offload {
 877         IAVF_TX_CTX_EXT_IP_NONE         = 0x0,
 878         IAVF_TX_CTX_EXT_IP_IPV6         = 0x1,
 879         IAVF_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
 880         IAVF_TX_CTX_EXT_IP_IPV4         = 0x3
 881 };
 882
 883 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT        2
 884 #define IAVF_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
 885                                          IAVF_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
 886
 887 #define IAVF_TXD_CTX_QW0_NATT_SHIFT     9
 888 #define IAVF_TXD_CTX_QW0_NATT_MASK      (0x3ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
 889
 890 #define IAVF_TXD_CTX_UDP_TUNNELING      BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
 891 #define IAVF_TXD_CTX_GRE_TUNNELING      (0x2ULL << IAVF_TXD_CTX_QW0_NATT_SHIFT)
 892
 893 #define IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT        11
 894 #define IAVF_TXD_CTX_QW0_EIP_NOINC_MASK \
 895                                        BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
 896
 897 #define IAVF_TXD_CTX_EIP_NOINC_IPID_CONST       IAVF_TXD_CTX_QW0_EIP_NOINC_MASK
 898
 899 #define IAVF_TXD_CTX_QW0_NATLEN_SHIFT   12
 900 #define IAVF_TXD_CTX_QW0_NATLEN_MASK    (0X7FULL << \
 901                                          IAVF_TXD_CTX_QW0_NATLEN_SHIFT)
 902
 903 #define IAVF_TXD_CTX_QW0_DECTTL_SHIFT   19
 904 #define IAVF_TXD_CTX_QW0_DECTTL_MASK    (0xFULL << \
 905                                          IAVF_TXD_CTX_QW0_DECTTL_SHIFT)
 906
 907 #define IAVF_TXD_CTX_QW0_L4T_CS_SHIFT   23
 908 #define IAVF_TXD_CTX_QW0_L4T_CS_MASK    BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
 909
 910 /* Statistics collected by each port, VSI, VEB, and S-channel */
 911 struct iavf_eth_stats {
 912         u64 rx_bytes;                   /* gorc */
 913         u64 rx_unicast;                 /* uprc */
 914         u64 rx_multicast;               /* mprc */
 915         u64 rx_broadcast;               /* bprc */
 916         u64 rx_discards;                /* rdpc */
 917         u64 rx_unknown_protocol;        /* rupp */
 918         u64 tx_bytes;                   /* gotc */
 919         u64 tx_unicast;                 /* uptc */
 920         u64 tx_multicast;               /* mptc */
 921         u64 tx_broadcast;               /* bptc */
 922         u64 tx_discards;                /* tdpc */
 923         u64 tx_errors;                  /* tepc */
 924 };
 925 #define IAVF_SR_PCIE_ANALOG_CONFIG_PTR          0x03
 926 #define IAVF_SR_PHY_ANALOG_CONFIG_PTR           0x04
 927 #define IAVF_SR_OPTION_ROM_PTR                  0x05
 928 #define IAVF_SR_RO_PCIR_REGS_AUTO_LOAD_PTR      0x06
 929 #define IAVF_SR_AUTO_GENERATED_POINTERS_PTR     0x07
 930 #define IAVF_SR_PCIR_REGS_AUTO_LOAD_PTR         0x08
 931 #define IAVF_SR_EMP_GLOBAL_MODULE_PTR           0x09
 932 #define IAVF_SR_RO_PCIE_LCB_PTR                 0x0A
 933 #define IAVF_SR_EMP_IMAGE_PTR                   0x0B
 934 #define IAVF_SR_PE_IMAGE_PTR                    0x0C
 935 #define IAVF_SR_CSR_PROTECTED_LIST_PTR          0x0D
 936 #define IAVF_SR_MNG_CONFIG_PTR                  0x0E
 937 #define IAVF_SR_PBA_FLAGS                       0x15
 938 #define IAVF_SR_PBA_BLOCK_PTR                   0x16
 939 #define IAVF_SR_BOOT_CONFIG_PTR                 0x17
 940 #define IAVF_SR_PERMANENT_SAN_MAC_ADDRESS_PTR   0x28
 941 #define IAVF_SR_NVM_MAP_VERSION                 0x29
 942 #define IAVF_SR_NVM_IMAGE_VERSION               0x2A
 943 #define IAVF_SR_NVM_STRUCTURE_VERSION           0x2B
 944 #define IAVF_SR_PXE_SETUP_PTR                   0x30
 945 #define IAVF_SR_PXE_CONFIG_CUST_OPTIONS_PTR     0x31
 946 #define IAVF_SR_NVM_ORIGINAL_EETRACK_LO         0x34
 947 #define IAVF_SR_NVM_ORIGINAL_EETRACK_HI         0x35
 948 #define IAVF_SR_SW_ETHERNET_MAC_ADDRESS_PTR     0x37
 949 #define IAVF_SR_POR_REGS_AUTO_LOAD_PTR          0x38
 950 #define IAVF_SR_EMPR_REGS_AUTO_LOAD_PTR         0x3A
 951 #define IAVF_SR_GLOBR_REGS_AUTO_LOAD_PTR        0x3B
 952 #define IAVF_SR_CORER_REGS_AUTO_LOAD_PTR        0x3C
 953 #define IAVF_SR_PHY_ACTIVITY_LIST_PTR           0x3D
 954 #define IAVF_SR_1ST_FREE_PROVISION_AREA_PTR     0x40
 955 #define IAVF_SR_4TH_FREE_PROVISION_AREA_PTR     0x42
 956 #define IAVF_SR_3RD_FREE_PROVISION_AREA_PTR     0x44
 957 #define IAVF_SR_2ND_FREE_PROVISION_AREA_PTR     0x46
 958 #define IAVF_SR_EMP_SR_SETTINGS_PTR             0x48
 959 #define IAVF_SR_FEATURE_CONFIGURATION_PTR       0x49
 960 #define IAVF_SR_CONFIGURATION_METADATA_PTR      0x4D
 961 #define IAVF_SR_IMMEDIATE_VALUES_PTR            0x4E
 962 #define IAVF_SR_OCP_CFG_WORD0                   0x2B
 963 #define IAVF_SR_OCP_ENABLED                     BIT(15)
 964 #define IAVF_SR_BUF_ALIGNMENT           4096
 965
 966
 967 struct iavf_lldp_variables {
 968         u16 length;
 969         u16 adminstatus;
 970         u16 msgfasttx;
 971         u16 msgtxinterval;
 972         u16 txparams;
 973         u16 timers;
 974         u16 crc8;
 975 };
 976
 977 /* Offsets into Alternate Ram */
 978 #define IAVF_ALT_STRUCT_FIRST_PF_OFFSET         0   /* in dwords */
 979 #define IAVF_ALT_STRUCT_DWORDS_PER_PF           64   /* in dwords */
 980 #define IAVF_ALT_STRUCT_OUTER_VLAN_TAG_OFFSET   0xD  /* in dwords */
 981 #define IAVF_ALT_STRUCT_USER_PRIORITY_OFFSET    0xC  /* in dwords */
 982 #define IAVF_ALT_STRUCT_MIN_BW_OFFSET           0xE  /* in dwords */
 983 #define IAVF_ALT_STRUCT_MAX_BW_OFFSET           0xF  /* in dwords */
 984
 985 /* Alternate Ram Bandwidth Masks */
 986 #define IAVF_ALT_BW_VALUE_MASK          0xFF
 987 #define IAVF_ALT_BW_RELATIVE_MASK       0x40000000
 988 #define IAVF_ALT_BW_VALID_MASK          0x80000000
 989
 990 #define IAVF_DDP_TRACKID_RDONLY         0
 991 #define IAVF_DDP_TRACKID_INVALID        0xFFFFFFFF
 992 #define SECTION_TYPE_RB_MMIO    0x00001800
 993 #define SECTION_TYPE_RB_AQ      0x00001801
 994 #define SECTION_TYPE_PROTO      0x80000002
 995 #define SECTION_TYPE_PCTYPE     0x80000003
 996 #define SECTION_TYPE_PTYPE      0x80000004
 997 struct iavf_profile_tlv_section_record {
 998         u8 rtype;
 999         u8 type;
1000         u16 len;
1001         u8 data[12];
1002 };
1003
1004 /* Generic AQ section in proflie */
1005 struct iavf_profile_aq_section {
1006         u16 opcode;
1007         u16 flags;
1008         u8  param[16];
1009         u16 datalen;
1010         u8  data[1];
1011 };
1012
1013 #endif /* _IAVF_TYPE_H_ */