drivers/net/iavf/iavf_rxtx.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2017 Intel Corporation
   3  */
   4
   5 #include <stdio.h>
   6 #include <stdlib.h>
   7 #include <string.h>
   8 #include <errno.h>
   9 #include <stdint.h>
  10 #include <stdarg.h>
  11 #include <unistd.h>
  12 #include <inttypes.h>
  13 #include <sys/queue.h>
  14
  15 #include <rte_string_fns.h>
  16 #include <rte_memzone.h>
  17 #include <rte_mbuf.h>
  18 #include <rte_malloc.h>
  19 #include <rte_ether.h>
  20 #include <rte_ethdev_driver.h>
  21 #include <rte_tcp.h>
  22 #include <rte_sctp.h>
  23 #include <rte_udp.h>
  24 #include <rte_ip.h>
  25 #include <rte_net.h>
  26
  27 #include "iavf.h"
  28 #include "iavf_rxtx.h"
  29
  30 static inline int
  31 check_rx_thresh(uint16_t nb_desc, uint16_t thresh)
  32 {
  33         /* The following constraints must be satisfied:
  34          *   thresh < rxq->nb_rx_desc
  35          */
  36         if (thresh >= nb_desc) {
  37                 PMD_INIT_LOG(ERR, "rx_free_thresh (%u) must be less than %u",
  38                              thresh, nb_desc);
  39                 return -EINVAL;
  40         }
  41         return 0;
  42 }
  43
  44 static inline int
  45 check_tx_thresh(uint16_t nb_desc, uint16_t tx_rs_thresh,
  46                 uint16_t tx_free_thresh)
  47 {
  48         /* TX descriptors will have their RS bit set after tx_rs_thresh
  49          * descriptors have been used. The TX descriptor ring will be cleaned
  50          * after tx_free_thresh descriptors are used or if the number of
  51          * descriptors required to transmit a packet is greater than the
  52          * number of free TX descriptors.
  53          *
  54          * The following constraints must be satisfied:
  55          *  - tx_rs_thresh must be less than the size of the ring minus 2.
  56          *  - tx_free_thresh must be less than the size of the ring minus 3.
  57          *  - tx_rs_thresh must be less than or equal to tx_free_thresh.
  58          *  - tx_rs_thresh must be a divisor of the ring size.
  59          *
  60          * One descriptor in the TX ring is used as a sentinel to avoid a H/W
  61          * race condition, hence the maximum threshold constraints. When set
  62          * to zero use default values.
  63          */
  64         if (tx_rs_thresh >= (nb_desc - 2)) {
  65                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than the "
  66                              "number of TX descriptors (%u) minus 2",
  67                              tx_rs_thresh, nb_desc);
  68                 return -EINVAL;
  69         }
  70         if (tx_free_thresh >= (nb_desc - 3)) {
  71                 PMD_INIT_LOG(ERR, "tx_free_thresh (%u) must be less than the "
  72                              "number of TX descriptors (%u) minus 3.",
  73                              tx_free_thresh, nb_desc);
  74                 return -EINVAL;
  75         }
  76         if (tx_rs_thresh > tx_free_thresh) {
  77                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be less than or "
  78                              "equal to tx_free_thresh (%u).",
  79                              tx_rs_thresh, tx_free_thresh);
  80                 return -EINVAL;
  81         }
  82         if ((nb_desc % tx_rs_thresh) != 0) {
  83                 PMD_INIT_LOG(ERR, "tx_rs_thresh (%u) must be a divisor of the "
  84                              "number of TX descriptors (%u).",
  85                              tx_rs_thresh, nb_desc);
  86                 return -EINVAL;
  87         }
  88
  89         return 0;
  90 }
  91
  92 static inline bool
  93 check_rx_vec_allow(struct iavf_rx_queue *rxq)
  94 {
  95         if (rxq->rx_free_thresh >= IAVF_VPMD_RX_MAX_BURST &&
  96             rxq->nb_rx_desc % rxq->rx_free_thresh == 0) {
  97                 PMD_INIT_LOG(DEBUG, "Vector Rx can be enabled on this rxq.");
  98                 return true;
  99         }
 100
 101         PMD_INIT_LOG(DEBUG, "Vector Rx cannot be enabled on this rxq.");
 102         return false;
 103 }
 104
 105 static inline bool
 106 check_tx_vec_allow(struct iavf_tx_queue *txq)
 107 {
 108         if (!(txq->offloads & IAVF_NO_VECTOR_FLAGS) &&
 109             txq->rs_thresh >= IAVF_VPMD_TX_MAX_BURST &&
 110             txq->rs_thresh <= IAVF_VPMD_TX_MAX_FREE_BUF) {
 111                 PMD_INIT_LOG(DEBUG, "Vector tx can be enabled on this txq.");
 112                 return true;
 113         }
 114         PMD_INIT_LOG(DEBUG, "Vector Tx cannot be enabled on this txq.");
 115         return false;
 116 }
 117
 118 static inline bool
 119 check_rx_bulk_allow(struct iavf_rx_queue *rxq)
 120 {
 121         int ret = true;
 122
 123         if (!(rxq->rx_free_thresh >= IAVF_RX_MAX_BURST)) {
 124                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 125                              "rxq->rx_free_thresh=%d, "
 126                              "IAVF_RX_MAX_BURST=%d",
 127                              rxq->rx_free_thresh, IAVF_RX_MAX_BURST);
 128                 ret = false;
 129         } else if (rxq->nb_rx_desc % rxq->rx_free_thresh != 0) {
 130                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions: "
 131                              "rxq->nb_rx_desc=%d, "
 132                              "rxq->rx_free_thresh=%d",
 133                              rxq->nb_rx_desc, rxq->rx_free_thresh);
 134                 ret = false;
 135         }
 136         return ret;
 137 }
 138
 139 static inline void
 140 reset_rx_queue(struct iavf_rx_queue *rxq)
 141 {
 142         uint16_t len;
 143         uint32_t i;
 144
 145         if (!rxq)
 146                 return;
 147
 148         len = rxq->nb_rx_desc + IAVF_RX_MAX_BURST;
 149
 150         for (i = 0; i < len * sizeof(union iavf_rx_desc); i++)
 151                 ((volatile char *)rxq->rx_ring)[i] = 0;
 152
 153         memset(&rxq->fake_mbuf, 0x0, sizeof(rxq->fake_mbuf));
 154
 155         for (i = 0; i < IAVF_RX_MAX_BURST; i++)
 156                 rxq->sw_ring[rxq->nb_rx_desc + i] = &rxq->fake_mbuf;
 157
 158         /* for rx bulk */
 159         rxq->rx_nb_avail = 0;
 160         rxq->rx_next_avail = 0;
 161         rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
 162
 163         rxq->rx_tail = 0;
 164         rxq->nb_rx_hold = 0;
 165         rxq->pkt_first_seg = NULL;
 166         rxq->pkt_last_seg = NULL;
 167 }
 168
 169 static inline void
 170 reset_tx_queue(struct iavf_tx_queue *txq)
 171 {
 172         struct iavf_tx_entry *txe;
 173         uint32_t i, size;
 174         uint16_t prev;
 175
 176         if (!txq) {
 177                 PMD_DRV_LOG(DEBUG, "Pointer to txq is NULL");
 178                 return;
 179         }
 180
 181         txe = txq->sw_ring;
 182         size = sizeof(struct iavf_tx_desc) * txq->nb_tx_desc;
 183         for (i = 0; i < size; i++)
 184                 ((volatile char *)txq->tx_ring)[i] = 0;
 185
 186         prev = (uint16_t)(txq->nb_tx_desc - 1);
 187         for (i = 0; i < txq->nb_tx_desc; i++) {
 188                 txq->tx_ring[i].cmd_type_offset_bsz =
 189                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE);
 190                 txe[i].mbuf =  NULL;
 191                 txe[i].last_id = i;
 192                 txe[prev].next_id = i;
 193                 prev = i;
 194         }
 195
 196         txq->tx_tail = 0;
 197         txq->nb_used = 0;
 198
 199         txq->last_desc_cleaned = txq->nb_tx_desc - 1;
 200         txq->nb_free = txq->nb_tx_desc - 1;
 201
 202         txq->next_dd = txq->rs_thresh - 1;
 203         txq->next_rs = txq->rs_thresh - 1;
 204 }
 205
 206 static int
 207 alloc_rxq_mbufs(struct iavf_rx_queue *rxq)
 208 {
 209         volatile union iavf_rx_desc *rxd;
 210         struct rte_mbuf *mbuf = NULL;
 211         uint64_t dma_addr;
 212         uint16_t i;
 213
 214         for (i = 0; i < rxq->nb_rx_desc; i++) {
 215                 mbuf = rte_mbuf_raw_alloc(rxq->mp);
 216                 if (unlikely(!mbuf)) {
 217                         PMD_DRV_LOG(ERR, "Failed to allocate mbuf for RX");
 218                         return -ENOMEM;
 219                 }
 220
 221                 rte_mbuf_refcnt_set(mbuf, 1);
 222                 mbuf->next = NULL;
 223                 mbuf->data_off = RTE_PKTMBUF_HEADROOM;
 224                 mbuf->nb_segs = 1;
 225                 mbuf->port = rxq->port_id;
 226
 227                 dma_addr =
 228                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(mbuf));
 229
 230                 rxd = &rxq->rx_ring[i];
 231                 rxd->read.pkt_addr = dma_addr;
 232                 rxd->read.hdr_addr = 0;
 233 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 234                 rxd->read.rsvd1 = 0;
 235                 rxd->read.rsvd2 = 0;
 236 #endif
 237
 238                 rxq->sw_ring[i] = mbuf;
 239         }
 240
 241         return 0;
 242 }
 243
 244 static inline void
 245 release_rxq_mbufs(struct iavf_rx_queue *rxq)
 246 {
 247         uint16_t i;
 248
 249         if (!rxq->sw_ring)
 250                 return;
 251
 252         for (i = 0; i < rxq->nb_rx_desc; i++) {
 253                 if (rxq->sw_ring[i]) {
 254                         rte_pktmbuf_free_seg(rxq->sw_ring[i]);
 255                         rxq->sw_ring[i] = NULL;
 256                 }
 257         }
 258
 259         /* for rx bulk */
 260         if (rxq->rx_nb_avail == 0)
 261                 return;
 262         for (i = 0; i < rxq->rx_nb_avail; i++) {
 263                 struct rte_mbuf *mbuf;
 264
 265                 mbuf = rxq->rx_stage[rxq->rx_next_avail + i];
 266                 rte_pktmbuf_free_seg(mbuf);
 267         }
 268         rxq->rx_nb_avail = 0;
 269 }
 270
 271 static inline void
 272 release_txq_mbufs(struct iavf_tx_queue *txq)
 273 {
 274         uint16_t i;
 275
 276         if (!txq || !txq->sw_ring) {
 277                 PMD_DRV_LOG(DEBUG, "Pointer to rxq or sw_ring is NULL");
 278                 return;
 279         }
 280
 281         for (i = 0; i < txq->nb_tx_desc; i++) {
 282                 if (txq->sw_ring[i].mbuf) {
 283                         rte_pktmbuf_free_seg(txq->sw_ring[i].mbuf);
 284                         txq->sw_ring[i].mbuf = NULL;
 285                 }
 286         }
 287 }
 288
 289 static const struct iavf_rxq_ops def_rxq_ops = {
 290         .release_mbufs = release_rxq_mbufs,
 291 };
 292
 293 static const struct iavf_txq_ops def_txq_ops = {
 294         .release_mbufs = release_txq_mbufs,
 295 };
 296
 297 int
 298 iavf_dev_rx_queue_setup(struct rte_eth_dev *dev, uint16_t queue_idx,
 299                        uint16_t nb_desc, unsigned int socket_id,
 300                        const struct rte_eth_rxconf *rx_conf,
 301                        struct rte_mempool *mp)
 302 {
 303         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 304         struct iavf_adapter *ad =
 305                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 306         struct iavf_info *vf =
 307                 IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
 308         struct iavf_vsi *vsi = &vf->vsi;
 309         struct iavf_rx_queue *rxq;
 310         const struct rte_memzone *mz;
 311         uint32_t ring_size;
 312         uint16_t len;
 313         uint16_t rx_free_thresh;
 314
 315         PMD_INIT_FUNC_TRACE();
 316
 317         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 318             nb_desc > IAVF_MAX_RING_DESC ||
 319             nb_desc < IAVF_MIN_RING_DESC) {
 320                 PMD_INIT_LOG(ERR, "Number (%u) of receive descriptors is "
 321                              "invalid", nb_desc);
 322                 return -EINVAL;
 323         }
 324
 325         /* Check free threshold */
 326         rx_free_thresh = (rx_conf->rx_free_thresh == 0) ?
 327                          IAVF_DEFAULT_RX_FREE_THRESH :
 328                          rx_conf->rx_free_thresh;
 329         if (check_rx_thresh(nb_desc, rx_free_thresh) != 0)
 330                 return -EINVAL;
 331
 332         /* Free memory if needed */
 333         if (dev->data->rx_queues[queue_idx]) {
 334                 iavf_dev_rx_queue_release(dev->data->rx_queues[queue_idx]);
 335                 dev->data->rx_queues[queue_idx] = NULL;
 336         }
 337
 338         /* Allocate the rx queue data structure */
 339         rxq = rte_zmalloc_socket("iavf rxq",
 340                                  sizeof(struct iavf_rx_queue),
 341                                  RTE_CACHE_LINE_SIZE,
 342                                  socket_id);
 343         if (!rxq) {
 344                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 345                              "rx queue data structure");
 346                 return -ENOMEM;
 347         }
 348
 349         if (vf->vf_res->vf_cap_flags &
 350             VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC &&
 351             vf->supported_rxdid & BIT(IAVF_RXDID_COMMS_OVS_1)) {
 352                 rxq->rxdid = IAVF_RXDID_COMMS_OVS_1;
 353         } else {
 354                 rxq->rxdid = IAVF_RXDID_LEGACY_1;
 355         }
 356
 357         rxq->mp = mp;
 358         rxq->nb_rx_desc = nb_desc;
 359         rxq->rx_free_thresh = rx_free_thresh;
 360         rxq->queue_id = queue_idx;
 361         rxq->port_id = dev->data->port_id;
 362         rxq->crc_len = 0; /* crc stripping by default */
 363         rxq->rx_deferred_start = rx_conf->rx_deferred_start;
 364         rxq->rx_hdr_len = 0;
 365         rxq->vsi = vsi;
 366
 367         len = rte_pktmbuf_data_room_size(rxq->mp) - RTE_PKTMBUF_HEADROOM;
 368         rxq->rx_buf_len = RTE_ALIGN(len, (1 << IAVF_RXQ_CTX_DBUFF_SHIFT));
 369
 370         /* Allocate the software ring. */
 371         len = nb_desc + IAVF_RX_MAX_BURST;
 372         rxq->sw_ring =
 373                 rte_zmalloc_socket("iavf rx sw ring",
 374                                    sizeof(struct rte_mbuf *) * len,
 375                                    RTE_CACHE_LINE_SIZE,
 376                                    socket_id);
 377         if (!rxq->sw_ring) {
 378                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW ring");
 379                 rte_free(rxq);
 380                 return -ENOMEM;
 381         }
 382
 383         /* Allocate the maximun number of RX ring hardware descriptor with
 384          * a liitle more to support bulk allocate.
 385          */
 386         len = IAVF_MAX_RING_DESC + IAVF_RX_MAX_BURST;
 387         ring_size = RTE_ALIGN(len * sizeof(union iavf_rx_desc),
 388                               IAVF_DMA_MEM_ALIGN);
 389         mz = rte_eth_dma_zone_reserve(dev, "rx_ring", queue_idx,
 390                                       ring_size, IAVF_RING_BASE_ALIGN,
 391                                       socket_id);
 392         if (!mz) {
 393                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for RX");
 394                 rte_free(rxq->sw_ring);
 395                 rte_free(rxq);
 396                 return -ENOMEM;
 397         }
 398         /* Zero all the descriptors in the ring. */
 399         memset(mz->addr, 0, ring_size);
 400         rxq->rx_ring_phys_addr = mz->iova;
 401         rxq->rx_ring = (union iavf_rx_desc *)mz->addr;
 402
 403         rxq->mz = mz;
 404         reset_rx_queue(rxq);
 405         rxq->q_set = true;
 406         dev->data->rx_queues[queue_idx] = rxq;
 407         rxq->qrx_tail = hw->hw_addr + IAVF_QRX_TAIL1(rxq->queue_id);
 408         rxq->ops = &def_rxq_ops;
 409
 410         if (check_rx_bulk_allow(rxq) == true) {
 411                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 412                              "satisfied. Rx Burst Bulk Alloc function will be "
 413                              "used on port=%d, queue=%d.",
 414                              rxq->port_id, rxq->queue_id);
 415         } else {
 416                 PMD_INIT_LOG(DEBUG, "Rx Burst Bulk Alloc Preconditions are "
 417                              "not satisfied, Scattered Rx is requested "
 418                              "on port=%d, queue=%d.",
 419                              rxq->port_id, rxq->queue_id);
 420                 ad->rx_bulk_alloc_allowed = false;
 421         }
 422
 423         if (check_rx_vec_allow(rxq) == false)
 424                 ad->rx_vec_allowed = false;
 425
 426         return 0;
 427 }
 428
 429 int
 430 iavf_dev_tx_queue_setup(struct rte_eth_dev *dev,
 431                        uint16_t queue_idx,
 432                        uint16_t nb_desc,
 433                        unsigned int socket_id,
 434                        const struct rte_eth_txconf *tx_conf)
 435 {
 436         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 437         struct iavf_tx_queue *txq;
 438         const struct rte_memzone *mz;
 439         uint32_t ring_size;
 440         uint16_t tx_rs_thresh, tx_free_thresh;
 441         uint64_t offloads;
 442
 443         PMD_INIT_FUNC_TRACE();
 444
 445         offloads = tx_conf->offloads | dev->data->dev_conf.txmode.offloads;
 446
 447         if (nb_desc % IAVF_ALIGN_RING_DESC != 0 ||
 448             nb_desc > IAVF_MAX_RING_DESC ||
 449             nb_desc < IAVF_MIN_RING_DESC) {
 450                 PMD_INIT_LOG(ERR, "Number (%u) of transmit descriptors is "
 451                             "invalid", nb_desc);
 452                 return -EINVAL;
 453         }
 454
 455         tx_rs_thresh = (uint16_t)((tx_conf->tx_rs_thresh) ?
 456                 tx_conf->tx_rs_thresh : DEFAULT_TX_RS_THRESH);
 457         tx_free_thresh = (uint16_t)((tx_conf->tx_free_thresh) ?
 458                 tx_conf->tx_free_thresh : DEFAULT_TX_FREE_THRESH);
 459         check_tx_thresh(nb_desc, tx_rs_thresh, tx_rs_thresh);
 460
 461         /* Free memory if needed. */
 462         if (dev->data->tx_queues[queue_idx]) {
 463                 iavf_dev_tx_queue_release(dev->data->tx_queues[queue_idx]);
 464                 dev->data->tx_queues[queue_idx] = NULL;
 465         }
 466
 467         /* Allocate the TX queue data structure. */
 468         txq = rte_zmalloc_socket("iavf txq",
 469                                  sizeof(struct iavf_tx_queue),
 470                                  RTE_CACHE_LINE_SIZE,
 471                                  socket_id);
 472         if (!txq) {
 473                 PMD_INIT_LOG(ERR, "Failed to allocate memory for "
 474                              "tx queue structure");
 475                 return -ENOMEM;
 476         }
 477
 478         txq->nb_tx_desc = nb_desc;
 479         txq->rs_thresh = tx_rs_thresh;
 480         txq->free_thresh = tx_free_thresh;
 481         txq->queue_id = queue_idx;
 482         txq->port_id = dev->data->port_id;
 483         txq->offloads = offloads;
 484         txq->tx_deferred_start = tx_conf->tx_deferred_start;
 485
 486         /* Allocate software ring */
 487         txq->sw_ring =
 488                 rte_zmalloc_socket("iavf tx sw ring",
 489                                    sizeof(struct iavf_tx_entry) * nb_desc,
 490                                    RTE_CACHE_LINE_SIZE,
 491                                    socket_id);
 492         if (!txq->sw_ring) {
 493                 PMD_INIT_LOG(ERR, "Failed to allocate memory for SW TX ring");
 494                 rte_free(txq);
 495                 return -ENOMEM;
 496         }
 497
 498         /* Allocate TX hardware ring descriptors. */
 499         ring_size = sizeof(struct iavf_tx_desc) * IAVF_MAX_RING_DESC;
 500         ring_size = RTE_ALIGN(ring_size, IAVF_DMA_MEM_ALIGN);
 501         mz = rte_eth_dma_zone_reserve(dev, "tx_ring", queue_idx,
 502                                       ring_size, IAVF_RING_BASE_ALIGN,
 503                                       socket_id);
 504         if (!mz) {
 505                 PMD_INIT_LOG(ERR, "Failed to reserve DMA memory for TX");
 506                 rte_free(txq->sw_ring);
 507                 rte_free(txq);
 508                 return -ENOMEM;
 509         }
 510         txq->tx_ring_phys_addr = mz->iova;
 511         txq->tx_ring = (struct iavf_tx_desc *)mz->addr;
 512
 513         txq->mz = mz;
 514         reset_tx_queue(txq);
 515         txq->q_set = true;
 516         dev->data->tx_queues[queue_idx] = txq;
 517         txq->qtx_tail = hw->hw_addr + IAVF_QTX_TAIL1(queue_idx);
 518         txq->ops = &def_txq_ops;
 519
 520         if (check_tx_vec_allow(txq) == false) {
 521                 struct iavf_adapter *ad =
 522                         IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 523                 ad->tx_vec_allowed = false;
 524         }
 525
 526         return 0;
 527 }
 528
 529 int
 530 iavf_dev_rx_queue_start(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 531 {
 532         struct iavf_adapter *adapter =
 533                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 534         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 535         struct iavf_rx_queue *rxq;
 536         int err = 0;
 537
 538         PMD_DRV_FUNC_TRACE();
 539
 540         if (rx_queue_id >= dev->data->nb_rx_queues)
 541                 return -EINVAL;
 542
 543         rxq = dev->data->rx_queues[rx_queue_id];
 544
 545         err = alloc_rxq_mbufs(rxq);
 546         if (err) {
 547                 PMD_DRV_LOG(ERR, "Failed to allocate RX queue mbuf");
 548                 return err;
 549         }
 550
 551         rte_wmb();
 552
 553         /* Init the RX tail register. */
 554         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rxq->nb_rx_desc - 1);
 555         IAVF_WRITE_FLUSH(hw);
 556
 557         /* Ready to switch the queue on */
 558         err = iavf_switch_queue(adapter, rx_queue_id, true, true);
 559         if (err)
 560                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u on",
 561                             rx_queue_id);
 562         else
 563                 dev->data->rx_queue_state[rx_queue_id] =
 564                         RTE_ETH_QUEUE_STATE_STARTED;
 565
 566         return err;
 567 }
 568
 569 int
 570 iavf_dev_tx_queue_start(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 571 {
 572         struct iavf_adapter *adapter =
 573                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 574         struct iavf_hw *hw = IAVF_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 575         struct iavf_tx_queue *txq;
 576         int err = 0;
 577
 578         PMD_DRV_FUNC_TRACE();
 579
 580         if (tx_queue_id >= dev->data->nb_tx_queues)
 581                 return -EINVAL;
 582
 583         txq = dev->data->tx_queues[tx_queue_id];
 584
 585         /* Init the RX tail register. */
 586         IAVF_PCI_REG_WRITE(txq->qtx_tail, 0);
 587         IAVF_WRITE_FLUSH(hw);
 588
 589         /* Ready to switch the queue on */
 590         err = iavf_switch_queue(adapter, tx_queue_id, false, true);
 591
 592         if (err)
 593                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u on",
 594                             tx_queue_id);
 595         else
 596                 dev->data->tx_queue_state[tx_queue_id] =
 597                         RTE_ETH_QUEUE_STATE_STARTED;
 598
 599         return err;
 600 }
 601
 602 int
 603 iavf_dev_rx_queue_stop(struct rte_eth_dev *dev, uint16_t rx_queue_id)
 604 {
 605         struct iavf_adapter *adapter =
 606                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 607         struct iavf_rx_queue *rxq;
 608         int err;
 609
 610         PMD_DRV_FUNC_TRACE();
 611
 612         if (rx_queue_id >= dev->data->nb_rx_queues)
 613                 return -EINVAL;
 614
 615         err = iavf_switch_queue(adapter, rx_queue_id, true, false);
 616         if (err) {
 617                 PMD_DRV_LOG(ERR, "Failed to switch RX queue %u off",
 618                             rx_queue_id);
 619                 return err;
 620         }
 621
 622         rxq = dev->data->rx_queues[rx_queue_id];
 623         rxq->ops->release_mbufs(rxq);
 624         reset_rx_queue(rxq);
 625         dev->data->rx_queue_state[rx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 626
 627         return 0;
 628 }
 629
 630 int
 631 iavf_dev_tx_queue_stop(struct rte_eth_dev *dev, uint16_t tx_queue_id)
 632 {
 633         struct iavf_adapter *adapter =
 634                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 635         struct iavf_tx_queue *txq;
 636         int err;
 637
 638         PMD_DRV_FUNC_TRACE();
 639
 640         if (tx_queue_id >= dev->data->nb_tx_queues)
 641                 return -EINVAL;
 642
 643         err = iavf_switch_queue(adapter, tx_queue_id, false, false);
 644         if (err) {
 645                 PMD_DRV_LOG(ERR, "Failed to switch TX queue %u off",
 646                             tx_queue_id);
 647                 return err;
 648         }
 649
 650         txq = dev->data->tx_queues[tx_queue_id];
 651         txq->ops->release_mbufs(txq);
 652         reset_tx_queue(txq);
 653         dev->data->tx_queue_state[tx_queue_id] = RTE_ETH_QUEUE_STATE_STOPPED;
 654
 655         return 0;
 656 }
 657
 658 void
 659 iavf_dev_rx_queue_release(void *rxq)
 660 {
 661         struct iavf_rx_queue *q = (struct iavf_rx_queue *)rxq;
 662
 663         if (!q)
 664                 return;
 665
 666         q->ops->release_mbufs(q);
 667         rte_free(q->sw_ring);
 668         rte_memzone_free(q->mz);
 669         rte_free(q);
 670 }
 671
 672 void
 673 iavf_dev_tx_queue_release(void *txq)
 674 {
 675         struct iavf_tx_queue *q = (struct iavf_tx_queue *)txq;
 676
 677         if (!q)
 678                 return;
 679
 680         q->ops->release_mbufs(q);
 681         rte_free(q->sw_ring);
 682         rte_memzone_free(q->mz);
 683         rte_free(q);
 684 }
 685
 686 void
 687 iavf_stop_queues(struct rte_eth_dev *dev)
 688 {
 689         struct iavf_adapter *adapter =
 690                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
 691         struct iavf_rx_queue *rxq;
 692         struct iavf_tx_queue *txq;
 693         int ret, i;
 694
 695         /* Stop All queues */
 696         ret = iavf_disable_queues(adapter);
 697         if (ret)
 698                 PMD_DRV_LOG(WARNING, "Fail to stop queues");
 699
 700         for (i = 0; i < dev->data->nb_tx_queues; i++) {
 701                 txq = dev->data->tx_queues[i];
 702                 if (!txq)
 703                         continue;
 704                 txq->ops->release_mbufs(txq);
 705                 reset_tx_queue(txq);
 706                 dev->data->tx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 707         }
 708         for (i = 0; i < dev->data->nb_rx_queues; i++) {
 709                 rxq = dev->data->rx_queues[i];
 710                 if (!rxq)
 711                         continue;
 712                 rxq->ops->release_mbufs(rxq);
 713                 reset_rx_queue(rxq);
 714                 dev->data->rx_queue_state[i] = RTE_ETH_QUEUE_STATE_STOPPED;
 715         }
 716 }
 717
 718 static inline void
 719 iavf_rxd_to_vlan_tci(struct rte_mbuf *mb, volatile union iavf_rx_desc *rxdp)
 720 {
 721         if (rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
 722                 (1 << IAVF_RX_DESC_STATUS_L2TAG1P_SHIFT)) {
 723                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 724                 mb->vlan_tci =
 725                         rte_le_to_cpu_16(rxdp->wb.qword0.lo_dword.l2tag1);
 726         } else {
 727                 mb->vlan_tci = 0;
 728         }
 729 }
 730
 731 static inline void
 732 iavf_flex_rxd_to_vlan_tci(struct rte_mbuf *mb,
 733                           volatile union iavf_rx_flex_desc *rxdp)
 734 {
 735         if (rte_le_to_cpu_64(rxdp->wb.status_error0) &
 736                 (1 << IAVF_RX_FLEX_DESC_STATUS0_L2TAG1P_S)) {
 737                 mb->ol_flags |= PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED;
 738                 mb->vlan_tci =
 739                         rte_le_to_cpu_16(rxdp->wb.l2tag1);
 740         } else {
 741                 mb->vlan_tci = 0;
 742         }
 743 }
 744
 745 /* Translate the rx descriptor status and error fields to pkt flags */
 746 static inline uint64_t
 747 iavf_rxd_to_pkt_flags(uint64_t qword)
 748 {
 749         uint64_t flags;
 750         uint64_t error_bits = (qword >> IAVF_RXD_QW1_ERROR_SHIFT);
 751
 752 #define IAVF_RX_ERR_BITS 0x3f
 753
 754         /* Check if RSS_HASH */
 755         flags = (((qword >> IAVF_RX_DESC_STATUS_FLTSTAT_SHIFT) &
 756                                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ==
 757                         IAVF_RX_DESC_FLTSTAT_RSS_HASH) ? PKT_RX_RSS_HASH : 0;
 758
 759         if (likely((error_bits & IAVF_RX_ERR_BITS) == 0)) {
 760                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 761                 return flags;
 762         }
 763
 764         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_IPE_SHIFT)))
 765                 flags |= PKT_RX_IP_CKSUM_BAD;
 766         else
 767                 flags |= PKT_RX_IP_CKSUM_GOOD;
 768
 769         if (unlikely(error_bits & (1 << IAVF_RX_DESC_ERROR_L4E_SHIFT)))
 770                 flags |= PKT_RX_L4_CKSUM_BAD;
 771         else
 772                 flags |= PKT_RX_L4_CKSUM_GOOD;
 773
 774         /* TODO: Oversize error bit is not processed here */
 775
 776         return flags;
 777 }
 778
 779 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 780 /* Translate the rx flex descriptor status to pkt flags */
 781 static inline void
 782 iavf_rxd_to_pkt_fields(struct rte_mbuf *mb,
 783                        volatile union iavf_rx_flex_desc *rxdp)
 784 {
 785         volatile struct iavf_32b_rx_flex_desc_comms_ovs *desc =
 786                         (volatile struct iavf_32b_rx_flex_desc_comms_ovs *)rxdp;
 787         uint16_t stat_err;
 788
 789         stat_err = rte_le_to_cpu_16(desc->status_error0);
 790         if (likely(stat_err & (1 << IAVF_RX_FLEX_DESC_STATUS0_RSS_VALID_S))) {
 791                 mb->ol_flags |= PKT_RX_RSS_HASH;
 792                 mb->hash.rss = rte_le_to_cpu_32(desc->rss_hash);
 793         }
 794 }
 795 #endif
 796
 797 #define IAVF_RX_FLEX_ERR0_BITS  \
 798         ((1 << IAVF_RX_FLEX_DESC_STATUS0_HBO_S) |       \
 799          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S) |  \
 800          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S) |  \
 801          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S) | \
 802          (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EUDPE_S) |        \
 803          (1 << IAVF_RX_FLEX_DESC_STATUS0_RXE_S))
 804
 805 /* Rx L3/L4 checksum */
 806 static inline uint64_t
 807 iavf_flex_rxd_error_to_pkt_flags(uint16_t stat_err0)
 808 {
 809         uint64_t flags = 0;
 810
 811         /* check if HW has decoded the packet and checksum */
 812         if (unlikely(!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_L3L4P_S))))
 813                 return 0;
 814
 815         if (likely(!(stat_err0 & IAVF_RX_FLEX_ERR0_BITS))) {
 816                 flags |= (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD);
 817                 return flags;
 818         }
 819
 820         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_IPE_S)))
 821                 flags |= PKT_RX_IP_CKSUM_BAD;
 822         else
 823                 flags |= PKT_RX_IP_CKSUM_GOOD;
 824
 825         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_L4E_S)))
 826                 flags |= PKT_RX_L4_CKSUM_BAD;
 827         else
 828                 flags |= PKT_RX_L4_CKSUM_GOOD;
 829
 830         if (unlikely(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_XSUM_EIPE_S)))
 831                 flags |= PKT_RX_EIP_CKSUM_BAD;
 832
 833         return flags;
 834 }
 835
 836 /* If the number of free RX descriptors is greater than the RX free
 837  * threshold of the queue, advance the Receive Descriptor Tail (RDT)
 838  * register. Update the RDT with the value of the last processed RX
 839  * descriptor minus 1, to guarantee that the RDT register is never
 840  * equal to the RDH register, which creates a "full" ring situation
 841  * from the hardware point of view.
 842  */
 843 static inline void
 844 iavf_update_rx_tail(struct iavf_rx_queue *rxq, uint16_t nb_hold, uint16_t rx_id)
 845 {
 846         nb_hold = (uint16_t)(nb_hold + rxq->nb_rx_hold);
 847
 848         if (nb_hold > rxq->rx_free_thresh) {
 849                 PMD_RX_LOG(DEBUG,
 850                            "port_id=%u queue_id=%u rx_tail=%u nb_hold=%u",
 851                            rxq->port_id, rxq->queue_id, rx_id, nb_hold);
 852                 rx_id = (uint16_t)((rx_id == 0) ?
 853                         (rxq->nb_rx_desc - 1) : (rx_id - 1));
 854                 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 855                 nb_hold = 0;
 856         }
 857         rxq->nb_rx_hold = nb_hold;
 858 }
 859
 860 /* implement recv_pkts */
 861 uint16_t
 862 iavf_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 863 {
 864         volatile union iavf_rx_desc *rx_ring;
 865         volatile union iavf_rx_desc *rxdp;
 866         struct iavf_rx_queue *rxq;
 867         union iavf_rx_desc rxd;
 868         struct rte_mbuf *rxe;
 869         struct rte_eth_dev *dev;
 870         struct rte_mbuf *rxm;
 871         struct rte_mbuf *nmb;
 872         uint16_t nb_rx;
 873         uint32_t rx_status;
 874         uint64_t qword1;
 875         uint16_t rx_packet_len;
 876         uint16_t rx_id, nb_hold;
 877         uint64_t dma_addr;
 878         uint64_t pkt_flags;
 879         const uint32_t *ptype_tbl;
 880
 881         nb_rx = 0;
 882         nb_hold = 0;
 883         rxq = rx_queue;
 884         rx_id = rxq->rx_tail;
 885         rx_ring = rxq->rx_ring;
 886         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 887
 888         while (nb_rx < nb_pkts) {
 889                 rxdp = &rx_ring[rx_id];
 890                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
 891                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
 892                             IAVF_RXD_QW1_STATUS_SHIFT;
 893
 894                 /* Check the DD bit first */
 895                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 896                         break;
 897                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
 898
 899                 nmb = rte_mbuf_raw_alloc(rxq->mp);
 900                 if (unlikely(!nmb)) {
 901                         dev = &rte_eth_devices[rxq->port_id];
 902                         dev->data->rx_mbuf_alloc_failed++;
 903                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
 904                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
 905                         break;
 906                 }
 907
 908                 rxd = *rxdp;
 909                 nb_hold++;
 910                 rxe = rxq->sw_ring[rx_id];
 911                 rx_id++;
 912                 if (unlikely(rx_id == rxq->nb_rx_desc))
 913                         rx_id = 0;
 914
 915                 /* Prefetch next mbuf */
 916                 rte_prefetch0(rxq->sw_ring[rx_id]);
 917
 918                 /* When next RX descriptor is on a cache line boundary,
 919                  * prefetch the next 4 RX descriptors and next 8 pointers
 920                  * to mbufs.
 921                  */
 922                 if ((rx_id & 0x3) == 0) {
 923                         rte_prefetch0(&rx_ring[rx_id]);
 924                         rte_prefetch0(rxq->sw_ring[rx_id]);
 925                 }
 926                 rxm = rxe;
 927                 rxe = nmb;
 928                 dma_addr =
 929                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
 930                 rxdp->read.hdr_addr = 0;
 931                 rxdp->read.pkt_addr = dma_addr;
 932
 933                 rx_packet_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
 934                                 IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
 935
 936                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
 937                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
 938                 rxm->nb_segs = 1;
 939                 rxm->next = NULL;
 940                 rxm->pkt_len = rx_packet_len;
 941                 rxm->data_len = rx_packet_len;
 942                 rxm->port = rxq->port_id;
 943                 rxm->ol_flags = 0;
 944                 iavf_rxd_to_vlan_tci(rxm, &rxd);
 945                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
 946                 rxm->packet_type =
 947                         ptype_tbl[(uint8_t)((qword1 &
 948                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
 949
 950                 if (pkt_flags & PKT_RX_RSS_HASH)
 951                         rxm->hash.rss =
 952                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
 953
 954                 rxm->ol_flags |= pkt_flags;
 955
 956                 rx_pkts[nb_rx++] = rxm;
 957         }
 958         rxq->rx_tail = rx_id;
 959
 960         iavf_update_rx_tail(rxq, nb_hold, rx_id);
 961
 962         return nb_rx;
 963 }
 964
 965 /* implement recv_pkts for flexible Rx descriptor */
 966 uint16_t
 967 iavf_recv_pkts_flex_rxd(void *rx_queue,
 968                         struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
 969 {
 970         volatile union iavf_rx_desc *rx_ring;
 971         volatile union iavf_rx_flex_desc *rxdp;
 972         struct iavf_rx_queue *rxq;
 973         union iavf_rx_flex_desc rxd;
 974         struct rte_mbuf *rxe;
 975         struct rte_eth_dev *dev;
 976         struct rte_mbuf *rxm;
 977         struct rte_mbuf *nmb;
 978         uint16_t nb_rx;
 979         uint16_t rx_stat_err0;
 980         uint16_t rx_packet_len;
 981         uint16_t rx_id, nb_hold;
 982         uint64_t dma_addr;
 983         uint64_t pkt_flags;
 984         const uint32_t *ptype_tbl;
 985
 986         nb_rx = 0;
 987         nb_hold = 0;
 988         rxq = rx_queue;
 989         rx_id = rxq->rx_tail;
 990         rx_ring = rxq->rx_ring;
 991         ptype_tbl = rxq->vsi->adapter->ptype_tbl;
 992
 993         while (nb_rx < nb_pkts) {
 994                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
 995                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
 996
 997                 /* Check the DD bit first */
 998                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
 999                         break;
1000                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1001
1002                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1003                 if (unlikely(!nmb)) {
1004                         dev = &rte_eth_devices[rxq->port_id];
1005                         dev->data->rx_mbuf_alloc_failed++;
1006                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1007                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1008                         break;
1009                 }
1010
1011                 rxd = *rxdp;
1012                 nb_hold++;
1013                 rxe = rxq->sw_ring[rx_id];
1014                 rx_id++;
1015                 if (unlikely(rx_id == rxq->nb_rx_desc))
1016                         rx_id = 0;
1017
1018                 /* Prefetch next mbuf */
1019                 rte_prefetch0(rxq->sw_ring[rx_id]);
1020
1021                 /* When next RX descriptor is on a cache line boundary,
1022                  * prefetch the next 4 RX descriptors and next 8 pointers
1023                  * to mbufs.
1024                  */
1025                 if ((rx_id & 0x3) == 0) {
1026                         rte_prefetch0(&rx_ring[rx_id]);
1027                         rte_prefetch0(rxq->sw_ring[rx_id]);
1028                 }
1029                 rxm = rxe;
1030                 rxe = nmb;
1031                 dma_addr =
1032                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1033                 rxdp->read.hdr_addr = 0;
1034                 rxdp->read.pkt_addr = dma_addr;
1035
1036                 rx_packet_len = (rte_le_to_cpu_16(rxd.wb.pkt_len) &
1037                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1038
1039                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1040                 rte_prefetch0(RTE_PTR_ADD(rxm->buf_addr, RTE_PKTMBUF_HEADROOM));
1041                 rxm->nb_segs = 1;
1042                 rxm->next = NULL;
1043                 rxm->pkt_len = rx_packet_len;
1044                 rxm->data_len = rx_packet_len;
1045                 rxm->port = rxq->port_id;
1046                 rxm->ol_flags = 0;
1047                 rxm->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1048                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1049                 iavf_flex_rxd_to_vlan_tci(rxm, &rxd);
1050 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1051                 iavf_rxd_to_pkt_fields(rxm, &rxd);
1052 #endif
1053                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1054                 rxm->ol_flags |= pkt_flags;
1055
1056                 rx_pkts[nb_rx++] = rxm;
1057         }
1058         rxq->rx_tail = rx_id;
1059
1060         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1061
1062         return nb_rx;
1063 }
1064
1065 /* implement recv_scattered_pkts for flexible Rx descriptor */
1066 uint16_t
1067 iavf_recv_scattered_pkts_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1068                                   uint16_t nb_pkts)
1069 {
1070         struct iavf_rx_queue *rxq = rx_queue;
1071         union iavf_rx_flex_desc rxd;
1072         struct rte_mbuf *rxe;
1073         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1074         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1075         struct rte_mbuf *nmb, *rxm;
1076         uint16_t rx_id = rxq->rx_tail;
1077         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1078         struct rte_eth_dev *dev;
1079         uint16_t rx_stat_err0;
1080         uint64_t dma_addr;
1081         uint64_t pkt_flags;
1082
1083         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1084         volatile union iavf_rx_flex_desc *rxdp;
1085         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1086
1087         while (nb_rx < nb_pkts) {
1088                 rxdp = (volatile union iavf_rx_flex_desc *)&rx_ring[rx_id];
1089                 rx_stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1090
1091                 /* Check the DD bit */
1092                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1093                         break;
1094                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1095
1096                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1097                 if (unlikely(!nmb)) {
1098                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1099                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1100                         dev = &rte_eth_devices[rxq->port_id];
1101                         dev->data->rx_mbuf_alloc_failed++;
1102                         break;
1103                 }
1104
1105                 rxd = *rxdp;
1106                 nb_hold++;
1107                 rxe = rxq->sw_ring[rx_id];
1108                 rx_id++;
1109                 if (rx_id == rxq->nb_rx_desc)
1110                         rx_id = 0;
1111
1112                 /* Prefetch next mbuf */
1113                 rte_prefetch0(rxq->sw_ring[rx_id]);
1114
1115                 /* When next RX descriptor is on a cache line boundary,
1116                  * prefetch the next 4 RX descriptors and next 8 pointers
1117                  * to mbufs.
1118                  */
1119                 if ((rx_id & 0x3) == 0) {
1120                         rte_prefetch0(&rx_ring[rx_id]);
1121                         rte_prefetch0(rxq->sw_ring[rx_id]);
1122                 }
1123
1124                 rxm = rxe;
1125                 rxe = nmb;
1126                 dma_addr =
1127                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1128
1129                 /* Set data buffer address and data length of the mbuf */
1130                 rxdp->read.hdr_addr = 0;
1131                 rxdp->read.pkt_addr = dma_addr;
1132                 rx_packet_len = rte_le_to_cpu_16(rxd.wb.pkt_len) &
1133                                 IAVF_RX_FLX_DESC_PKT_LEN_M;
1134                 rxm->data_len = rx_packet_len;
1135                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1136
1137                 /* If this is the first buffer of the received packet, set the
1138                  * pointer to the first mbuf of the packet and initialize its
1139                  * context. Otherwise, update the total length and the number
1140                  * of segments of the current scattered packet, and update the
1141                  * pointer to the last mbuf of the current packet.
1142                  */
1143                 if (!first_seg) {
1144                         first_seg = rxm;
1145                         first_seg->nb_segs = 1;
1146                         first_seg->pkt_len = rx_packet_len;
1147                 } else {
1148                         first_seg->pkt_len =
1149                                 (uint16_t)(first_seg->pkt_len +
1150                                                 rx_packet_len);
1151                         first_seg->nb_segs++;
1152                         last_seg->next = rxm;
1153                 }
1154
1155                 /* If this is not the last buffer of the received packet,
1156                  * update the pointer to the last mbuf of the current scattered
1157                  * packet and continue to parse the RX ring.
1158                  */
1159                 if (!(rx_stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_EOF_S))) {
1160                         last_seg = rxm;
1161                         continue;
1162                 }
1163
1164                 /* This is the last buffer of the received packet. If the CRC
1165                  * is not stripped by the hardware:
1166                  *  - Subtract the CRC length from the total packet length.
1167                  *  - If the last buffer only contains the whole CRC or a part
1168                  *  of it, free the mbuf associated to the last buffer. If part
1169                  *  of the CRC is also contained in the previous mbuf, subtract
1170                  *  the length of that CRC part from the data length of the
1171                  *  previous mbuf.
1172                  */
1173                 rxm->next = NULL;
1174                 if (unlikely(rxq->crc_len > 0)) {
1175                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1176                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1177                                 rte_pktmbuf_free_seg(rxm);
1178                                 first_seg->nb_segs--;
1179                                 last_seg->data_len =
1180                                         (uint16_t)(last_seg->data_len -
1181                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1182                                 last_seg->next = NULL;
1183                         } else {
1184                                 rxm->data_len = (uint16_t)(rx_packet_len -
1185                                                         RTE_ETHER_CRC_LEN);
1186                         }
1187                 }
1188
1189                 first_seg->port = rxq->port_id;
1190                 first_seg->ol_flags = 0;
1191                 first_seg->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1192                         rte_le_to_cpu_16(rxd.wb.ptype_flex_flags0)];
1193                 iavf_flex_rxd_to_vlan_tci(first_seg, &rxd);
1194 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1195                 iavf_rxd_to_pkt_fields(first_seg, &rxd);
1196 #endif
1197                 pkt_flags = iavf_flex_rxd_error_to_pkt_flags(rx_stat_err0);
1198
1199                 first_seg->ol_flags |= pkt_flags;
1200
1201                 /* Prefetch data of first segment, if configured to do so. */
1202                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1203                                           first_seg->data_off));
1204                 rx_pkts[nb_rx++] = first_seg;
1205                 first_seg = NULL;
1206         }
1207
1208         /* Record index of the next RX descriptor to probe. */
1209         rxq->rx_tail = rx_id;
1210         rxq->pkt_first_seg = first_seg;
1211         rxq->pkt_last_seg = last_seg;
1212
1213         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1214
1215         return nb_rx;
1216 }
1217
1218 /* implement recv_scattered_pkts  */
1219 uint16_t
1220 iavf_recv_scattered_pkts(void *rx_queue, struct rte_mbuf **rx_pkts,
1221                         uint16_t nb_pkts)
1222 {
1223         struct iavf_rx_queue *rxq = rx_queue;
1224         union iavf_rx_desc rxd;
1225         struct rte_mbuf *rxe;
1226         struct rte_mbuf *first_seg = rxq->pkt_first_seg;
1227         struct rte_mbuf *last_seg = rxq->pkt_last_seg;
1228         struct rte_mbuf *nmb, *rxm;
1229         uint16_t rx_id = rxq->rx_tail;
1230         uint16_t nb_rx = 0, nb_hold = 0, rx_packet_len;
1231         struct rte_eth_dev *dev;
1232         uint32_t rx_status;
1233         uint64_t qword1;
1234         uint64_t dma_addr;
1235         uint64_t pkt_flags;
1236
1237         volatile union iavf_rx_desc *rx_ring = rxq->rx_ring;
1238         volatile union iavf_rx_desc *rxdp;
1239         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1240
1241         while (nb_rx < nb_pkts) {
1242                 rxdp = &rx_ring[rx_id];
1243                 qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1244                 rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1245                             IAVF_RXD_QW1_STATUS_SHIFT;
1246
1247                 /* Check the DD bit */
1248                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1249                         break;
1250                 IAVF_DUMP_RX_DESC(rxq, rxdp, rx_id);
1251
1252                 nmb = rte_mbuf_raw_alloc(rxq->mp);
1253                 if (unlikely(!nmb)) {
1254                         PMD_RX_LOG(DEBUG, "RX mbuf alloc failed port_id=%u "
1255                                    "queue_id=%u", rxq->port_id, rxq->queue_id);
1256                         dev = &rte_eth_devices[rxq->port_id];
1257                         dev->data->rx_mbuf_alloc_failed++;
1258                         break;
1259                 }
1260
1261                 rxd = *rxdp;
1262                 nb_hold++;
1263                 rxe = rxq->sw_ring[rx_id];
1264                 rx_id++;
1265                 if (rx_id == rxq->nb_rx_desc)
1266                         rx_id = 0;
1267
1268                 /* Prefetch next mbuf */
1269                 rte_prefetch0(rxq->sw_ring[rx_id]);
1270
1271                 /* When next RX descriptor is on a cache line boundary,
1272                  * prefetch the next 4 RX descriptors and next 8 pointers
1273                  * to mbufs.
1274                  */
1275                 if ((rx_id & 0x3) == 0) {
1276                         rte_prefetch0(&rx_ring[rx_id]);
1277                         rte_prefetch0(rxq->sw_ring[rx_id]);
1278                 }
1279
1280                 rxm = rxe;
1281                 rxe = nmb;
1282                 dma_addr =
1283                         rte_cpu_to_le_64(rte_mbuf_data_iova_default(nmb));
1284
1285                 /* Set data buffer address and data length of the mbuf */
1286                 rxdp->read.hdr_addr = 0;
1287                 rxdp->read.pkt_addr = dma_addr;
1288                 rx_packet_len = (qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1289                                  IAVF_RXD_QW1_LENGTH_PBUF_SHIFT;
1290                 rxm->data_len = rx_packet_len;
1291                 rxm->data_off = RTE_PKTMBUF_HEADROOM;
1292
1293                 /* If this is the first buffer of the received packet, set the
1294                  * pointer to the first mbuf of the packet and initialize its
1295                  * context. Otherwise, update the total length and the number
1296                  * of segments of the current scattered packet, and update the
1297                  * pointer to the last mbuf of the current packet.
1298                  */
1299                 if (!first_seg) {
1300                         first_seg = rxm;
1301                         first_seg->nb_segs = 1;
1302                         first_seg->pkt_len = rx_packet_len;
1303                 } else {
1304                         first_seg->pkt_len =
1305                                 (uint16_t)(first_seg->pkt_len +
1306                                                 rx_packet_len);
1307                         first_seg->nb_segs++;
1308                         last_seg->next = rxm;
1309                 }
1310
1311                 /* If this is not the last buffer of the received packet,
1312                  * update the pointer to the last mbuf of the current scattered
1313                  * packet and continue to parse the RX ring.
1314                  */
1315                 if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_EOF_SHIFT))) {
1316                         last_seg = rxm;
1317                         continue;
1318                 }
1319
1320                 /* This is the last buffer of the received packet. If the CRC
1321                  * is not stripped by the hardware:
1322                  *  - Subtract the CRC length from the total packet length.
1323                  *  - If the last buffer only contains the whole CRC or a part
1324                  *  of it, free the mbuf associated to the last buffer. If part
1325                  *  of the CRC is also contained in the previous mbuf, subtract
1326                  *  the length of that CRC part from the data length of the
1327                  *  previous mbuf.
1328                  */
1329                 rxm->next = NULL;
1330                 if (unlikely(rxq->crc_len > 0)) {
1331                         first_seg->pkt_len -= RTE_ETHER_CRC_LEN;
1332                         if (rx_packet_len <= RTE_ETHER_CRC_LEN) {
1333                                 rte_pktmbuf_free_seg(rxm);
1334                                 first_seg->nb_segs--;
1335                                 last_seg->data_len =
1336                                         (uint16_t)(last_seg->data_len -
1337                                         (RTE_ETHER_CRC_LEN - rx_packet_len));
1338                                 last_seg->next = NULL;
1339                         } else
1340                                 rxm->data_len = (uint16_t)(rx_packet_len -
1341                                                         RTE_ETHER_CRC_LEN);
1342                 }
1343
1344                 first_seg->port = rxq->port_id;
1345                 first_seg->ol_flags = 0;
1346                 iavf_rxd_to_vlan_tci(first_seg, &rxd);
1347                 pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1348                 first_seg->packet_type =
1349                         ptype_tbl[(uint8_t)((qword1 &
1350                         IAVF_RXD_QW1_PTYPE_MASK) >> IAVF_RXD_QW1_PTYPE_SHIFT)];
1351
1352                 if (pkt_flags & PKT_RX_RSS_HASH)
1353                         first_seg->hash.rss =
1354                                 rte_le_to_cpu_32(rxd.wb.qword0.hi_dword.rss);
1355
1356                 first_seg->ol_flags |= pkt_flags;
1357
1358                 /* Prefetch data of first segment, if configured to do so. */
1359                 rte_prefetch0(RTE_PTR_ADD(first_seg->buf_addr,
1360                                           first_seg->data_off));
1361                 rx_pkts[nb_rx++] = first_seg;
1362                 first_seg = NULL;
1363         }
1364
1365         /* Record index of the next RX descriptor to probe. */
1366         rxq->rx_tail = rx_id;
1367         rxq->pkt_first_seg = first_seg;
1368         rxq->pkt_last_seg = last_seg;
1369
1370         iavf_update_rx_tail(rxq, nb_hold, rx_id);
1371
1372         return nb_rx;
1373 }
1374
1375 #define IAVF_LOOK_AHEAD 8
1376 static inline int
1377 iavf_rx_scan_hw_ring_flex_rxd(struct iavf_rx_queue *rxq)
1378 {
1379         volatile union iavf_rx_flex_desc *rxdp;
1380         struct rte_mbuf **rxep;
1381         struct rte_mbuf *mb;
1382         uint16_t stat_err0;
1383         uint16_t pkt_len;
1384         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1385         int32_t i, j, nb_rx = 0;
1386         uint64_t pkt_flags;
1387         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1388
1389         rxdp = (volatile union iavf_rx_flex_desc *)&rxq->rx_ring[rxq->rx_tail];
1390         rxep = &rxq->sw_ring[rxq->rx_tail];
1391
1392         stat_err0 = rte_le_to_cpu_16(rxdp->wb.status_error0);
1393
1394         /* Make sure there is at least 1 packet to receive */
1395         if (!(stat_err0 & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
1396                 return 0;
1397
1398         /* Scan LOOK_AHEAD descriptors at a time to determine which
1399          * descriptors reference packets that are ready to be received.
1400          */
1401         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1402              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1403                 /* Read desc statuses backwards to avoid race condition */
1404                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--)
1405                         s[j] = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1406
1407                 rte_smp_rmb();
1408
1409                 /* Compute how many status bits were set */
1410                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1411                         nb_dd += s[j] & (1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S);
1412
1413                 nb_rx += nb_dd;
1414
1415                 /* Translate descriptor info to mbuf parameters */
1416                 for (j = 0; j < nb_dd; j++) {
1417                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1418                                           rxq->rx_tail +
1419                                           i * IAVF_LOOK_AHEAD + j);
1420
1421                         mb = rxep[j];
1422                         pkt_len = (rte_le_to_cpu_16(rxdp[j].wb.pkt_len) &
1423                                 IAVF_RX_FLX_DESC_PKT_LEN_M) - rxq->crc_len;
1424                         mb->data_len = pkt_len;
1425                         mb->pkt_len = pkt_len;
1426                         mb->ol_flags = 0;
1427
1428                         mb->packet_type = ptype_tbl[IAVF_RX_FLEX_DESC_PTYPE_M &
1429                                 rte_le_to_cpu_16(rxdp[j].wb.ptype_flex_flags0)];
1430                         iavf_flex_rxd_to_vlan_tci(mb, &rxdp[j]);
1431 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1432                         iavf_rxd_to_pkt_fields(mb, &rxdp[j]);
1433 #endif
1434                         stat_err0 = rte_le_to_cpu_16(rxdp[j].wb.status_error0);
1435                         pkt_flags = iavf_flex_rxd_error_to_pkt_flags(stat_err0);
1436
1437                         mb->ol_flags |= pkt_flags;
1438                 }
1439
1440                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1441                         rxq->rx_stage[i + j] = rxep[j];
1442
1443                 if (nb_dd != IAVF_LOOK_AHEAD)
1444                         break;
1445         }
1446
1447         /* Clear software ring entries */
1448         for (i = 0; i < nb_rx; i++)
1449                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1450
1451         return nb_rx;
1452 }
1453
1454 static inline int
1455 iavf_rx_scan_hw_ring(struct iavf_rx_queue *rxq)
1456 {
1457         volatile union iavf_rx_desc *rxdp;
1458         struct rte_mbuf **rxep;
1459         struct rte_mbuf *mb;
1460         uint16_t pkt_len;
1461         uint64_t qword1;
1462         uint32_t rx_status;
1463         int32_t s[IAVF_LOOK_AHEAD], nb_dd;
1464         int32_t i, j, nb_rx = 0;
1465         uint64_t pkt_flags;
1466         const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
1467
1468         rxdp = &rxq->rx_ring[rxq->rx_tail];
1469         rxep = &rxq->sw_ring[rxq->rx_tail];
1470
1471         qword1 = rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len);
1472         rx_status = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1473                     IAVF_RXD_QW1_STATUS_SHIFT;
1474
1475         /* Make sure there is at least 1 packet to receive */
1476         if (!(rx_status & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
1477                 return 0;
1478
1479         /* Scan LOOK_AHEAD descriptors at a time to determine which
1480          * descriptors reference packets that are ready to be received.
1481          */
1482         for (i = 0; i < IAVF_RX_MAX_BURST; i += IAVF_LOOK_AHEAD,
1483              rxdp += IAVF_LOOK_AHEAD, rxep += IAVF_LOOK_AHEAD) {
1484                 /* Read desc statuses backwards to avoid race condition */
1485                 for (j = IAVF_LOOK_AHEAD - 1; j >= 0; j--) {
1486                         qword1 = rte_le_to_cpu_64(
1487                                 rxdp[j].wb.qword1.status_error_len);
1488                         s[j] = (qword1 & IAVF_RXD_QW1_STATUS_MASK) >>
1489                                IAVF_RXD_QW1_STATUS_SHIFT;
1490                 }
1491
1492                 rte_smp_rmb();
1493
1494                 /* Compute how many status bits were set */
1495                 for (j = 0, nb_dd = 0; j < IAVF_LOOK_AHEAD; j++)
1496                         nb_dd += s[j] & (1 << IAVF_RX_DESC_STATUS_DD_SHIFT);
1497
1498                 nb_rx += nb_dd;
1499
1500                 /* Translate descriptor info to mbuf parameters */
1501                 for (j = 0; j < nb_dd; j++) {
1502                         IAVF_DUMP_RX_DESC(rxq, &rxdp[j],
1503                                          rxq->rx_tail + i * IAVF_LOOK_AHEAD + j);
1504
1505                         mb = rxep[j];
1506                         qword1 = rte_le_to_cpu_64
1507                                         (rxdp[j].wb.qword1.status_error_len);
1508                         pkt_len = ((qword1 & IAVF_RXD_QW1_LENGTH_PBUF_MASK) >>
1509                                   IAVF_RXD_QW1_LENGTH_PBUF_SHIFT) - rxq->crc_len;
1510                         mb->data_len = pkt_len;
1511                         mb->pkt_len = pkt_len;
1512                         mb->ol_flags = 0;
1513                         iavf_rxd_to_vlan_tci(mb, &rxdp[j]);
1514                         pkt_flags = iavf_rxd_to_pkt_flags(qword1);
1515                         mb->packet_type =
1516                                 ptype_tbl[(uint8_t)((qword1 &
1517                                 IAVF_RXD_QW1_PTYPE_MASK) >>
1518                                 IAVF_RXD_QW1_PTYPE_SHIFT)];
1519
1520                         if (pkt_flags & PKT_RX_RSS_HASH)
1521                                 mb->hash.rss = rte_le_to_cpu_32(
1522                                         rxdp[j].wb.qword0.hi_dword.rss);
1523
1524                         mb->ol_flags |= pkt_flags;
1525                 }
1526
1527                 for (j = 0; j < IAVF_LOOK_AHEAD; j++)
1528                         rxq->rx_stage[i + j] = rxep[j];
1529
1530                 if (nb_dd != IAVF_LOOK_AHEAD)
1531                         break;
1532         }
1533
1534         /* Clear software ring entries */
1535         for (i = 0; i < nb_rx; i++)
1536                 rxq->sw_ring[rxq->rx_tail + i] = NULL;
1537
1538         return nb_rx;
1539 }
1540
1541 static inline uint16_t
1542 iavf_rx_fill_from_stage(struct iavf_rx_queue *rxq,
1543                        struct rte_mbuf **rx_pkts,
1544                        uint16_t nb_pkts)
1545 {
1546         uint16_t i;
1547         struct rte_mbuf **stage = &rxq->rx_stage[rxq->rx_next_avail];
1548
1549         nb_pkts = (uint16_t)RTE_MIN(nb_pkts, rxq->rx_nb_avail);
1550
1551         for (i = 0; i < nb_pkts; i++)
1552                 rx_pkts[i] = stage[i];
1553
1554         rxq->rx_nb_avail = (uint16_t)(rxq->rx_nb_avail - nb_pkts);
1555         rxq->rx_next_avail = (uint16_t)(rxq->rx_next_avail + nb_pkts);
1556
1557         return nb_pkts;
1558 }
1559
1560 static inline int
1561 iavf_rx_alloc_bufs(struct iavf_rx_queue *rxq)
1562 {
1563         volatile union iavf_rx_desc *rxdp;
1564         struct rte_mbuf **rxep;
1565         struct rte_mbuf *mb;
1566         uint16_t alloc_idx, i;
1567         uint64_t dma_addr;
1568         int diag;
1569
1570         /* Allocate buffers in bulk */
1571         alloc_idx = (uint16_t)(rxq->rx_free_trigger -
1572                                 (rxq->rx_free_thresh - 1));
1573         rxep = &rxq->sw_ring[alloc_idx];
1574         diag = rte_mempool_get_bulk(rxq->mp, (void *)rxep,
1575                                     rxq->rx_free_thresh);
1576         if (unlikely(diag != 0)) {
1577                 PMD_RX_LOG(ERR, "Failed to get mbufs in bulk");
1578                 return -ENOMEM;
1579         }
1580
1581         rxdp = &rxq->rx_ring[alloc_idx];
1582         for (i = 0; i < rxq->rx_free_thresh; i++) {
1583                 if (likely(i < (rxq->rx_free_thresh - 1)))
1584                         /* Prefetch next mbuf */
1585                         rte_prefetch0(rxep[i + 1]);
1586
1587                 mb = rxep[i];
1588                 rte_mbuf_refcnt_set(mb, 1);
1589                 mb->next = NULL;
1590                 mb->data_off = RTE_PKTMBUF_HEADROOM;
1591                 mb->nb_segs = 1;
1592                 mb->port = rxq->port_id;
1593                 dma_addr = rte_cpu_to_le_64(rte_mbuf_data_iova_default(mb));
1594                 rxdp[i].read.hdr_addr = 0;
1595                 rxdp[i].read.pkt_addr = dma_addr;
1596         }
1597
1598         /* Update rx tail register */
1599         rte_wmb();
1600         IAVF_PCI_REG_WRITE_RELAXED(rxq->qrx_tail, rxq->rx_free_trigger);
1601
1602         rxq->rx_free_trigger =
1603                 (uint16_t)(rxq->rx_free_trigger + rxq->rx_free_thresh);
1604         if (rxq->rx_free_trigger >= rxq->nb_rx_desc)
1605                 rxq->rx_free_trigger = (uint16_t)(rxq->rx_free_thresh - 1);
1606
1607         return 0;
1608 }
1609
1610 static inline uint16_t
1611 rx_recv_pkts(void *rx_queue, struct rte_mbuf **rx_pkts, uint16_t nb_pkts)
1612 {
1613         struct iavf_rx_queue *rxq = (struct iavf_rx_queue *)rx_queue;
1614         uint16_t nb_rx = 0;
1615
1616         if (!nb_pkts)
1617                 return 0;
1618
1619         if (rxq->rx_nb_avail)
1620                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1621
1622         if (rxq->rxdid == IAVF_RXDID_COMMS_OVS_1)
1623                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring_flex_rxd(rxq);
1624         else
1625                 nb_rx = (uint16_t)iavf_rx_scan_hw_ring(rxq);
1626         rxq->rx_next_avail = 0;
1627         rxq->rx_nb_avail = nb_rx;
1628         rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_rx);
1629
1630         if (rxq->rx_tail > rxq->rx_free_trigger) {
1631                 if (iavf_rx_alloc_bufs(rxq) != 0) {
1632                         uint16_t i, j;
1633
1634                         /* TODO: count rx_mbuf_alloc_failed here */
1635
1636                         rxq->rx_nb_avail = 0;
1637                         rxq->rx_tail = (uint16_t)(rxq->rx_tail - nb_rx);
1638                         for (i = 0, j = rxq->rx_tail; i < nb_rx; i++, j++)
1639                                 rxq->sw_ring[j] = rxq->rx_stage[i];
1640
1641                         return 0;
1642                 }
1643         }
1644
1645         if (rxq->rx_tail >= rxq->nb_rx_desc)
1646                 rxq->rx_tail = 0;
1647
1648         PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u, nb_rx=%u",
1649                    rxq->port_id, rxq->queue_id,
1650                    rxq->rx_tail, nb_rx);
1651
1652         if (rxq->rx_nb_avail)
1653                 return iavf_rx_fill_from_stage(rxq, rx_pkts, nb_pkts);
1654
1655         return 0;
1656 }
1657
1658 static uint16_t
1659 iavf_recv_pkts_bulk_alloc(void *rx_queue,
1660                          struct rte_mbuf **rx_pkts,
1661                          uint16_t nb_pkts)
1662 {
1663         uint16_t nb_rx = 0, n, count;
1664
1665         if (unlikely(nb_pkts == 0))
1666                 return 0;
1667
1668         if (likely(nb_pkts <= IAVF_RX_MAX_BURST))
1669                 return rx_recv_pkts(rx_queue, rx_pkts, nb_pkts);
1670
1671         while (nb_pkts) {
1672                 n = RTE_MIN(nb_pkts, IAVF_RX_MAX_BURST);
1673                 count = rx_recv_pkts(rx_queue, &rx_pkts[nb_rx], n);
1674                 nb_rx = (uint16_t)(nb_rx + count);
1675                 nb_pkts = (uint16_t)(nb_pkts - count);
1676                 if (count < n)
1677                         break;
1678         }
1679
1680         return nb_rx;
1681 }
1682
1683 static inline int
1684 iavf_xmit_cleanup(struct iavf_tx_queue *txq)
1685 {
1686         struct iavf_tx_entry *sw_ring = txq->sw_ring;
1687         uint16_t last_desc_cleaned = txq->last_desc_cleaned;
1688         uint16_t nb_tx_desc = txq->nb_tx_desc;
1689         uint16_t desc_to_clean_to;
1690         uint16_t nb_tx_to_clean;
1691
1692         volatile struct iavf_tx_desc *txd = txq->tx_ring;
1693
1694         desc_to_clean_to = (uint16_t)(last_desc_cleaned + txq->rs_thresh);
1695         if (desc_to_clean_to >= nb_tx_desc)
1696                 desc_to_clean_to = (uint16_t)(desc_to_clean_to - nb_tx_desc);
1697
1698         desc_to_clean_to = sw_ring[desc_to_clean_to].last_id;
1699         if ((txd[desc_to_clean_to].cmd_type_offset_bsz &
1700                         rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1701                         rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE)) {
1702                 PMD_TX_FREE_LOG(DEBUG, "TX descriptor %4u is not done "
1703                                 "(port=%d queue=%d)", desc_to_clean_to,
1704                                 txq->port_id, txq->queue_id);
1705                 return -1;
1706         }
1707
1708         if (last_desc_cleaned > desc_to_clean_to)
1709                 nb_tx_to_clean = (uint16_t)((nb_tx_desc - last_desc_cleaned) +
1710                                                         desc_to_clean_to);
1711         else
1712                 nb_tx_to_clean = (uint16_t)(desc_to_clean_to -
1713                                         last_desc_cleaned);
1714
1715         txd[desc_to_clean_to].cmd_type_offset_bsz = 0;
1716
1717         txq->last_desc_cleaned = desc_to_clean_to;
1718         txq->nb_free = (uint16_t)(txq->nb_free + nb_tx_to_clean);
1719
1720         return 0;
1721 }
1722
1723 /* Check if the context descriptor is needed for TX offloading */
1724 static inline uint16_t
1725 iavf_calc_context_desc(uint64_t flags)
1726 {
1727         static uint64_t mask = PKT_TX_TCP_SEG;
1728
1729         return (flags & mask) ? 1 : 0;
1730 }
1731
1732 static inline void
1733 iavf_txd_enable_checksum(uint64_t ol_flags,
1734                         uint32_t *td_cmd,
1735                         uint32_t *td_offset,
1736                         union iavf_tx_offload tx_offload)
1737 {
1738         /* Set MACLEN */
1739         *td_offset |= (tx_offload.l2_len >> 1) <<
1740                       IAVF_TX_DESC_LENGTH_MACLEN_SHIFT;
1741
1742         /* Enable L3 checksum offloads */
1743         if (ol_flags & PKT_TX_IP_CKSUM) {
1744                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4_CSUM;
1745                 *td_offset |= (tx_offload.l3_len >> 2) <<
1746                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1747         } else if (ol_flags & PKT_TX_IPV4) {
1748                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV4;
1749                 *td_offset |= (tx_offload.l3_len >> 2) <<
1750                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1751         } else if (ol_flags & PKT_TX_IPV6) {
1752                 *td_cmd |= IAVF_TX_DESC_CMD_IIPT_IPV6;
1753                 *td_offset |= (tx_offload.l3_len >> 2) <<
1754                               IAVF_TX_DESC_LENGTH_IPLEN_SHIFT;
1755         }
1756
1757         if (ol_flags & PKT_TX_TCP_SEG) {
1758                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1759                 *td_offset |= (tx_offload.l4_len >> 2) <<
1760                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1761                 return;
1762         }
1763
1764         /* Enable L4 checksum offloads */
1765         switch (ol_flags & PKT_TX_L4_MASK) {
1766         case PKT_TX_TCP_CKSUM:
1767                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_TCP;
1768                 *td_offset |= (sizeof(struct rte_tcp_hdr) >> 2) <<
1769                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1770                 break;
1771         case PKT_TX_SCTP_CKSUM:
1772                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_SCTP;
1773                 *td_offset |= (sizeof(struct rte_sctp_hdr) >> 2) <<
1774                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1775                 break;
1776         case PKT_TX_UDP_CKSUM:
1777                 *td_cmd |= IAVF_TX_DESC_CMD_L4T_EOFT_UDP;
1778                 *td_offset |= (sizeof(struct rte_udp_hdr) >> 2) <<
1779                               IAVF_TX_DESC_LENGTH_L4_FC_LEN_SHIFT;
1780                 break;
1781         default:
1782                 break;
1783         }
1784 }
1785
1786 /* set TSO context descriptor
1787  * support IP -> L4 and IP -> IP -> L4
1788  */
1789 static inline uint64_t
1790 iavf_set_tso_ctx(struct rte_mbuf *mbuf, union iavf_tx_offload tx_offload)
1791 {
1792         uint64_t ctx_desc = 0;
1793         uint32_t cd_cmd, hdr_len, cd_tso_len;
1794
1795         if (!tx_offload.l4_len) {
1796                 PMD_TX_LOG(DEBUG, "L4 length set to 0");
1797                 return ctx_desc;
1798         }
1799
1800         hdr_len = tx_offload.l2_len +
1801                   tx_offload.l3_len +
1802                   tx_offload.l4_len;
1803
1804         cd_cmd = IAVF_TX_CTX_DESC_TSO;
1805         cd_tso_len = mbuf->pkt_len - hdr_len;
1806         ctx_desc |= ((uint64_t)cd_cmd << IAVF_TXD_CTX_QW1_CMD_SHIFT) |
1807                      ((uint64_t)cd_tso_len << IAVF_TXD_CTX_QW1_TSO_LEN_SHIFT) |
1808                      ((uint64_t)mbuf->tso_segsz << IAVF_TXD_CTX_QW1_MSS_SHIFT);
1809
1810         return ctx_desc;
1811 }
1812
1813 /* Construct the tx flags */
1814 static inline uint64_t
1815 iavf_build_ctob(uint32_t td_cmd, uint32_t td_offset, unsigned int size,
1816                uint32_t td_tag)
1817 {
1818         return rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DATA |
1819                                 ((uint64_t)td_cmd  << IAVF_TXD_QW1_CMD_SHIFT) |
1820                                 ((uint64_t)td_offset <<
1821                                  IAVF_TXD_QW1_OFFSET_SHIFT) |
1822                                 ((uint64_t)size  <<
1823                                  IAVF_TXD_QW1_TX_BUF_SZ_SHIFT) |
1824                                 ((uint64_t)td_tag  <<
1825                                  IAVF_TXD_QW1_L2TAG1_SHIFT));
1826 }
1827
1828 /* TX function */
1829 uint16_t
1830 iavf_xmit_pkts(void *tx_queue, struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1831 {
1832         volatile struct iavf_tx_desc *txd;
1833         volatile struct iavf_tx_desc *txr;
1834         struct iavf_tx_queue *txq;
1835         struct iavf_tx_entry *sw_ring;
1836         struct iavf_tx_entry *txe, *txn;
1837         struct rte_mbuf *tx_pkt;
1838         struct rte_mbuf *m_seg;
1839         uint16_t tx_id;
1840         uint16_t nb_tx;
1841         uint32_t td_cmd;
1842         uint32_t td_offset;
1843         uint32_t td_tag;
1844         uint64_t ol_flags;
1845         uint16_t nb_used;
1846         uint16_t nb_ctx;
1847         uint16_t tx_last;
1848         uint16_t slen;
1849         uint64_t buf_dma_addr;
1850         union iavf_tx_offload tx_offload = {0};
1851
1852         txq = tx_queue;
1853         sw_ring = txq->sw_ring;
1854         txr = txq->tx_ring;
1855         tx_id = txq->tx_tail;
1856         txe = &sw_ring[tx_id];
1857
1858         /* Check if the descriptor ring needs to be cleaned. */
1859         if (txq->nb_free < txq->free_thresh)
1860                 iavf_xmit_cleanup(txq);
1861
1862         for (nb_tx = 0; nb_tx < nb_pkts; nb_tx++) {
1863                 td_cmd = 0;
1864                 td_tag = 0;
1865                 td_offset = 0;
1866
1867                 tx_pkt = *tx_pkts++;
1868                 RTE_MBUF_PREFETCH_TO_FREE(txe->mbuf);
1869
1870                 ol_flags = tx_pkt->ol_flags;
1871                 tx_offload.l2_len = tx_pkt->l2_len;
1872                 tx_offload.l3_len = tx_pkt->l3_len;
1873                 tx_offload.l4_len = tx_pkt->l4_len;
1874                 tx_offload.tso_segsz = tx_pkt->tso_segsz;
1875
1876                 /* Calculate the number of context descriptors needed. */
1877                 nb_ctx = iavf_calc_context_desc(ol_flags);
1878
1879                 /* The number of descriptors that must be allocated for
1880                  * a packet equals to the number of the segments of that
1881                  * packet plus 1 context descriptor if needed.
1882                  */
1883                 nb_used = (uint16_t)(tx_pkt->nb_segs + nb_ctx);
1884                 tx_last = (uint16_t)(tx_id + nb_used - 1);
1885
1886                 /* Circular ring */
1887                 if (tx_last >= txq->nb_tx_desc)
1888                         tx_last = (uint16_t)(tx_last - txq->nb_tx_desc);
1889
1890                 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u"
1891                            " tx_first=%u tx_last=%u",
1892                            txq->port_id, txq->queue_id, tx_id, tx_last);
1893
1894                 if (nb_used > txq->nb_free) {
1895                         if (iavf_xmit_cleanup(txq)) {
1896                                 if (nb_tx == 0)
1897                                         return 0;
1898                                 goto end_of_tx;
1899                         }
1900                         if (unlikely(nb_used > txq->rs_thresh)) {
1901                                 while (nb_used > txq->nb_free) {
1902                                         if (iavf_xmit_cleanup(txq)) {
1903                                                 if (nb_tx == 0)
1904                                                         return 0;
1905                                                 goto end_of_tx;
1906                                         }
1907                                 }
1908                         }
1909                 }
1910
1911                 /* Descriptor based VLAN insertion */
1912                 if (ol_flags & PKT_TX_VLAN_PKT) {
1913                         td_cmd |= IAVF_TX_DESC_CMD_IL2TAG1;
1914                         td_tag = tx_pkt->vlan_tci;
1915                 }
1916
1917                 /* According to datasheet, the bit2 is reserved and must be
1918                  * set to 1.
1919                  */
1920                 td_cmd |= 0x04;
1921
1922                 /* Enable checksum offloading */
1923                 if (ol_flags & IAVF_TX_CKSUM_OFFLOAD_MASK)
1924                         iavf_txd_enable_checksum(ol_flags, &td_cmd,
1925                                                 &td_offset, tx_offload);
1926
1927                 if (nb_ctx) {
1928                         /* Setup TX context descriptor if required */
1929                         uint64_t cd_type_cmd_tso_mss =
1930                                 IAVF_TX_DESC_DTYPE_CONTEXT;
1931                         volatile struct iavf_tx_context_desc *ctx_txd =
1932                                 (volatile struct iavf_tx_context_desc *)
1933                                                         &txr[tx_id];
1934
1935                         txn = &sw_ring[txe->next_id];
1936                         RTE_MBUF_PREFETCH_TO_FREE(txn->mbuf);
1937                         if (txe->mbuf) {
1938                                 rte_pktmbuf_free_seg(txe->mbuf);
1939                                 txe->mbuf = NULL;
1940                         }
1941
1942                         /* TSO enabled */
1943                         if (ol_flags & PKT_TX_TCP_SEG)
1944                                 cd_type_cmd_tso_mss |=
1945                                         iavf_set_tso_ctx(tx_pkt, tx_offload);
1946
1947                         ctx_txd->type_cmd_tso_mss =
1948                                 rte_cpu_to_le_64(cd_type_cmd_tso_mss);
1949
1950                         IAVF_DUMP_TX_DESC(txq, &txr[tx_id], tx_id);
1951                         txe->last_id = tx_last;
1952                         tx_id = txe->next_id;
1953                         txe = txn;
1954                 }
1955
1956                 m_seg = tx_pkt;
1957                 do {
1958                         txd = &txr[tx_id];
1959                         txn = &sw_ring[txe->next_id];
1960
1961                         if (txe->mbuf)
1962                                 rte_pktmbuf_free_seg(txe->mbuf);
1963                         txe->mbuf = m_seg;
1964
1965                         /* Setup TX Descriptor */
1966                         slen = m_seg->data_len;
1967                         buf_dma_addr = rte_mbuf_data_iova(m_seg);
1968                         txd->buffer_addr = rte_cpu_to_le_64(buf_dma_addr);
1969                         txd->cmd_type_offset_bsz = iavf_build_ctob(td_cmd,
1970                                                                   td_offset,
1971                                                                   slen,
1972                                                                   td_tag);
1973
1974                         IAVF_DUMP_TX_DESC(txq, txd, tx_id);
1975                         txe->last_id = tx_last;
1976                         tx_id = txe->next_id;
1977                         txe = txn;
1978                         m_seg = m_seg->next;
1979                 } while (m_seg);
1980
1981                 /* The last packet data descriptor needs End Of Packet (EOP) */
1982                 td_cmd |= IAVF_TX_DESC_CMD_EOP;
1983                 txq->nb_used = (uint16_t)(txq->nb_used + nb_used);
1984                 txq->nb_free = (uint16_t)(txq->nb_free - nb_used);
1985
1986                 if (txq->nb_used >= txq->rs_thresh) {
1987                         PMD_TX_LOG(DEBUG, "Setting RS bit on TXD id="
1988                                    "%4u (port=%d queue=%d)",
1989                                    tx_last, txq->port_id, txq->queue_id);
1990
1991                         td_cmd |= IAVF_TX_DESC_CMD_RS;
1992
1993                         /* Update txq RS bit counters */
1994                         txq->nb_used = 0;
1995                 }
1996
1997                 txd->cmd_type_offset_bsz |=
1998                         rte_cpu_to_le_64(((uint64_t)td_cmd) <<
1999                                          IAVF_TXD_QW1_CMD_SHIFT);
2000                 IAVF_DUMP_TX_DESC(txq, txd, tx_id);
2001         }
2002
2003 end_of_tx:
2004         rte_wmb();
2005
2006         PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_tx=%u",
2007                    txq->port_id, txq->queue_id, tx_id, nb_tx);
2008
2009         IAVF_PCI_REG_WRITE_RELAXED(txq->qtx_tail, tx_id);
2010         txq->tx_tail = tx_id;
2011
2012         return nb_tx;
2013 }
2014
2015 /* TX prep functions */
2016 uint16_t
2017 iavf_prep_pkts(__rte_unused void *tx_queue, struct rte_mbuf **tx_pkts,
2018               uint16_t nb_pkts)
2019 {
2020         int i, ret;
2021         uint64_t ol_flags;
2022         struct rte_mbuf *m;
2023
2024         for (i = 0; i < nb_pkts; i++) {
2025                 m = tx_pkts[i];
2026                 ol_flags = m->ol_flags;
2027
2028                 /* Check condition for nb_segs > IAVF_TX_MAX_MTU_SEG. */
2029                 if (!(ol_flags & PKT_TX_TCP_SEG)) {
2030                         if (m->nb_segs > IAVF_TX_MAX_MTU_SEG) {
2031                                 rte_errno = EINVAL;
2032                                 return i;
2033                         }
2034                 } else if ((m->tso_segsz < IAVF_MIN_TSO_MSS) ||
2035                            (m->tso_segsz > IAVF_MAX_TSO_MSS)) {
2036                         /* MSS outside the range are considered malicious */
2037                         rte_errno = EINVAL;
2038                         return i;
2039                 }
2040
2041                 if (ol_flags & IAVF_TX_OFFLOAD_NOTSUP_MASK) {
2042                         rte_errno = ENOTSUP;
2043                         return i;
2044                 }
2045
2046 #ifdef RTE_LIBRTE_ETHDEV_DEBUG
2047                 ret = rte_validate_tx_offload(m);
2048                 if (ret != 0) {
2049                         rte_errno = -ret;
2050                         return i;
2051                 }
2052 #endif
2053                 ret = rte_net_intel_cksum_prepare(m);
2054                 if (ret != 0) {
2055                         rte_errno = -ret;
2056                         return i;
2057                 }
2058         }
2059
2060         return i;
2061 }
2062
2063 /* choose rx function*/
2064 void
2065 iavf_set_rx_function(struct rte_eth_dev *dev)
2066 {
2067         struct iavf_adapter *adapter =
2068                 IAVF_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2069         struct iavf_info *vf = IAVF_DEV_PRIVATE_TO_VF(dev->data->dev_private);
2070 #ifdef RTE_ARCH_X86
2071         struct iavf_rx_queue *rxq;
2072         int i;
2073         bool use_avx2 = false;
2074
2075         if (!iavf_rx_vec_dev_check(dev)) {
2076                 for (i = 0; i < dev->data->nb_rx_queues; i++) {
2077                         rxq = dev->data->rx_queues[i];
2078                         (void)iavf_rxq_vec_setup(rxq);
2079                 }
2080
2081                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2082                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2083                         use_avx2 = true;
2084
2085                 if (dev->data->scattered_rx) {
2086                         PMD_DRV_LOG(DEBUG,
2087                                     "Using %sVector Scattered Rx (port %d).",
2088                                     use_avx2 ? "avx2 " : "",
2089                                     dev->data->port_id);
2090                         dev->rx_pkt_burst = use_avx2 ?
2091                                             iavf_recv_scattered_pkts_vec_avx2 :
2092                                             iavf_recv_scattered_pkts_vec;
2093                 } else {
2094                         PMD_DRV_LOG(DEBUG, "Using %sVector Rx (port %d).",
2095                                     use_avx2 ? "avx2 " : "",
2096                                     dev->data->port_id);
2097                         dev->rx_pkt_burst = use_avx2 ?
2098                                             iavf_recv_pkts_vec_avx2 :
2099                                             iavf_recv_pkts_vec;
2100                 }
2101
2102                 return;
2103         }
2104 #endif
2105
2106         if (dev->data->scattered_rx) {
2107                 PMD_DRV_LOG(DEBUG, "Using a Scattered Rx callback (port=%d).",
2108                             dev->data->port_id);
2109                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2110                         dev->rx_pkt_burst = iavf_recv_scattered_pkts_flex_rxd;
2111                 else
2112                         dev->rx_pkt_burst = iavf_recv_scattered_pkts;
2113         } else if (adapter->rx_bulk_alloc_allowed) {
2114                 PMD_DRV_LOG(DEBUG, "Using bulk Rx callback (port=%d).",
2115                             dev->data->port_id);
2116                 dev->rx_pkt_burst = iavf_recv_pkts_bulk_alloc;
2117         } else {
2118                 PMD_DRV_LOG(DEBUG, "Using Basic Rx callback (port=%d).",
2119                             dev->data->port_id);
2120                 if (vf->vf_res->vf_cap_flags & VIRTCHNL_VF_OFFLOAD_RX_FLEX_DESC)
2121                         dev->rx_pkt_burst = iavf_recv_pkts_flex_rxd;
2122                 else
2123                         dev->rx_pkt_burst = iavf_recv_pkts;
2124         }
2125 }
2126
2127 /* choose tx function*/
2128 void
2129 iavf_set_tx_function(struct rte_eth_dev *dev)
2130 {
2131 #ifdef RTE_ARCH_X86
2132         struct iavf_tx_queue *txq;
2133         int i;
2134         bool use_avx2 = false;
2135
2136         if (!iavf_tx_vec_dev_check(dev)) {
2137                 for (i = 0; i < dev->data->nb_tx_queues; i++) {
2138                         txq = dev->data->tx_queues[i];
2139                         if (!txq)
2140                                 continue;
2141                         iavf_txq_vec_setup(txq);
2142                 }
2143
2144                 if (rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX2) == 1 ||
2145                     rte_cpu_get_flag_enabled(RTE_CPUFLAG_AVX512F) == 1)
2146                         use_avx2 = true;
2147
2148                 PMD_DRV_LOG(DEBUG, "Using %sVector Tx (port %d).",
2149                             use_avx2 ? "avx2 " : "",
2150                             dev->data->port_id);
2151                 dev->tx_pkt_burst = use_avx2 ?
2152                                     iavf_xmit_pkts_vec_avx2 :
2153                                     iavf_xmit_pkts_vec;
2154                 dev->tx_pkt_prepare = NULL;
2155
2156                 return;
2157         }
2158 #endif
2159
2160         PMD_DRV_LOG(DEBUG, "Using Basic Tx callback (port=%d).",
2161                     dev->data->port_id);
2162         dev->tx_pkt_burst = iavf_xmit_pkts;
2163         dev->tx_pkt_prepare = iavf_prep_pkts;
2164 }
2165
2166 void
2167 iavf_dev_rxq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2168                      struct rte_eth_rxq_info *qinfo)
2169 {
2170         struct iavf_rx_queue *rxq;
2171
2172         rxq = dev->data->rx_queues[queue_id];
2173
2174         qinfo->mp = rxq->mp;
2175         qinfo->scattered_rx = dev->data->scattered_rx;
2176         qinfo->nb_desc = rxq->nb_rx_desc;
2177
2178         qinfo->conf.rx_free_thresh = rxq->rx_free_thresh;
2179         qinfo->conf.rx_drop_en = true;
2180         qinfo->conf.rx_deferred_start = rxq->rx_deferred_start;
2181 }
2182
2183 void
2184 iavf_dev_txq_info_get(struct rte_eth_dev *dev, uint16_t queue_id,
2185                      struct rte_eth_txq_info *qinfo)
2186 {
2187         struct iavf_tx_queue *txq;
2188
2189         txq = dev->data->tx_queues[queue_id];
2190
2191         qinfo->nb_desc = txq->nb_tx_desc;
2192
2193         qinfo->conf.tx_free_thresh = txq->free_thresh;
2194         qinfo->conf.tx_rs_thresh = txq->rs_thresh;
2195         qinfo->conf.offloads = txq->offloads;
2196         qinfo->conf.tx_deferred_start = txq->tx_deferred_start;
2197 }
2198
2199 /* Get the number of used descriptors of a rx queue */
2200 uint32_t
2201 iavf_dev_rxq_count(struct rte_eth_dev *dev, uint16_t queue_id)
2202 {
2203 #define IAVF_RXQ_SCAN_INTERVAL 4
2204         volatile union iavf_rx_desc *rxdp;
2205         struct iavf_rx_queue *rxq;
2206         uint16_t desc = 0;
2207
2208         rxq = dev->data->rx_queues[queue_id];
2209         rxdp = &rxq->rx_ring[rxq->rx_tail];
2210
2211         while ((desc < rxq->nb_rx_desc) &&
2212                ((rte_le_to_cpu_64(rxdp->wb.qword1.status_error_len) &
2213                  IAVF_RXD_QW1_STATUS_MASK) >> IAVF_RXD_QW1_STATUS_SHIFT) &
2214                (1 << IAVF_RX_DESC_STATUS_DD_SHIFT)) {
2215                 /* Check the DD bit of a rx descriptor of each 4 in a group,
2216                  * to avoid checking too frequently and downgrading performance
2217                  * too much.
2218                  */
2219                 desc += IAVF_RXQ_SCAN_INTERVAL;
2220                 rxdp += IAVF_RXQ_SCAN_INTERVAL;
2221                 if (rxq->rx_tail + desc >= rxq->nb_rx_desc)
2222                         rxdp = &(rxq->rx_ring[rxq->rx_tail +
2223                                         desc - rxq->nb_rx_desc]);
2224         }
2225
2226         return desc;
2227 }
2228
2229 int
2230 iavf_dev_rx_desc_status(void *rx_queue, uint16_t offset)
2231 {
2232         struct iavf_rx_queue *rxq = rx_queue;
2233         volatile uint64_t *status;
2234         uint64_t mask;
2235         uint32_t desc;
2236
2237         if (unlikely(offset >= rxq->nb_rx_desc))
2238                 return -EINVAL;
2239
2240         if (offset >= rxq->nb_rx_desc - rxq->nb_rx_hold)
2241                 return RTE_ETH_RX_DESC_UNAVAIL;
2242
2243         desc = rxq->rx_tail + offset;
2244         if (desc >= rxq->nb_rx_desc)
2245                 desc -= rxq->nb_rx_desc;
2246
2247         status = &rxq->rx_ring[desc].wb.qword1.status_error_len;
2248         mask = rte_le_to_cpu_64((1ULL << IAVF_RX_DESC_STATUS_DD_SHIFT)
2249                 << IAVF_RXD_QW1_STATUS_SHIFT);
2250         if (*status & mask)
2251                 return RTE_ETH_RX_DESC_DONE;
2252
2253         return RTE_ETH_RX_DESC_AVAIL;
2254 }
2255
2256 int
2257 iavf_dev_tx_desc_status(void *tx_queue, uint16_t offset)
2258 {
2259         struct iavf_tx_queue *txq = tx_queue;
2260         volatile uint64_t *status;
2261         uint64_t mask, expect;
2262         uint32_t desc;
2263
2264         if (unlikely(offset >= txq->nb_tx_desc))
2265                 return -EINVAL;
2266
2267         desc = txq->tx_tail + offset;
2268         /* go to next desc that has the RS bit */
2269         desc = ((desc + txq->rs_thresh - 1) / txq->rs_thresh) *
2270                 txq->rs_thresh;
2271         if (desc >= txq->nb_tx_desc) {
2272                 desc -= txq->nb_tx_desc;
2273                 if (desc >= txq->nb_tx_desc)
2274                         desc -= txq->nb_tx_desc;
2275         }
2276
2277         status = &txq->tx_ring[desc].cmd_type_offset_bsz;
2278         mask = rte_le_to_cpu_64(IAVF_TXD_QW1_DTYPE_MASK);
2279         expect = rte_cpu_to_le_64(
2280                  IAVF_TX_DESC_DTYPE_DESC_DONE << IAVF_TXD_QW1_DTYPE_SHIFT);
2281         if ((*status & mask) == expect)
2282                 return RTE_ETH_TX_DESC_DONE;
2283
2284         return RTE_ETH_TX_DESC_FULL;
2285 }
2286
2287 const uint32_t *
2288 iavf_get_default_ptype_table(void)
2289 {
2290         static const uint32_t ptype_tbl[IAVF_MAX_PKT_TYPE]
2291                 __rte_cache_aligned = {
2292                 /* L2 types */
2293                 /* [0] reserved */
2294                 [1] = RTE_PTYPE_L2_ETHER,
2295                 [2] = RTE_PTYPE_L2_ETHER_TIMESYNC,
2296                 /* [3] - [5] reserved */
2297                 [6] = RTE_PTYPE_L2_ETHER_LLDP,
2298                 /* [7] - [10] reserved */
2299                 [11] = RTE_PTYPE_L2_ETHER_ARP,
2300                 /* [12] - [21] reserved */
2301
2302                 /* Non tunneled IPv4 */
2303                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2304                        RTE_PTYPE_L4_FRAG,
2305                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2306                        RTE_PTYPE_L4_NONFRAG,
2307                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2308                        RTE_PTYPE_L4_UDP,
2309                 /* [25] reserved */
2310                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2311                        RTE_PTYPE_L4_TCP,
2312                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2313                        RTE_PTYPE_L4_SCTP,
2314                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2315                        RTE_PTYPE_L4_ICMP,
2316
2317                 /* IPv4 --> IPv4 */
2318                 [29] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2319                        RTE_PTYPE_TUNNEL_IP |
2320                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2321                        RTE_PTYPE_INNER_L4_FRAG,
2322                 [30] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2323                        RTE_PTYPE_TUNNEL_IP |
2324                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2325                        RTE_PTYPE_INNER_L4_NONFRAG,
2326                 [31] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2327                        RTE_PTYPE_TUNNEL_IP |
2328                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2329                        RTE_PTYPE_INNER_L4_UDP,
2330                 /* [32] reserved */
2331                 [33] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2332                        RTE_PTYPE_TUNNEL_IP |
2333                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2334                        RTE_PTYPE_INNER_L4_TCP,
2335                 [34] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2336                        RTE_PTYPE_TUNNEL_IP |
2337                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2338                        RTE_PTYPE_INNER_L4_SCTP,
2339                 [35] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2340                        RTE_PTYPE_TUNNEL_IP |
2341                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2342                        RTE_PTYPE_INNER_L4_ICMP,
2343
2344                 /* IPv4 --> IPv6 */
2345                 [36] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2346                        RTE_PTYPE_TUNNEL_IP |
2347                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2348                        RTE_PTYPE_INNER_L4_FRAG,
2349                 [37] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2350                        RTE_PTYPE_TUNNEL_IP |
2351                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2352                        RTE_PTYPE_INNER_L4_NONFRAG,
2353                 [38] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2354                        RTE_PTYPE_TUNNEL_IP |
2355                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2356                        RTE_PTYPE_INNER_L4_UDP,
2357                 /* [39] reserved */
2358                 [40] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2359                        RTE_PTYPE_TUNNEL_IP |
2360                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2361                        RTE_PTYPE_INNER_L4_TCP,
2362                 [41] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2363                        RTE_PTYPE_TUNNEL_IP |
2364                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2365                        RTE_PTYPE_INNER_L4_SCTP,
2366                 [42] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2367                        RTE_PTYPE_TUNNEL_IP |
2368                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2369                        RTE_PTYPE_INNER_L4_ICMP,
2370
2371                 /* IPv4 --> GRE/Teredo/VXLAN */
2372                 [43] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2373                        RTE_PTYPE_TUNNEL_GRENAT,
2374
2375                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv4 */
2376                 [44] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2377                        RTE_PTYPE_TUNNEL_GRENAT |
2378                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2379                        RTE_PTYPE_INNER_L4_FRAG,
2380                 [45] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2381                        RTE_PTYPE_TUNNEL_GRENAT |
2382                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2383                        RTE_PTYPE_INNER_L4_NONFRAG,
2384                 [46] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2385                        RTE_PTYPE_TUNNEL_GRENAT |
2386                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2387                        RTE_PTYPE_INNER_L4_UDP,
2388                 /* [47] reserved */
2389                 [48] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2390                        RTE_PTYPE_TUNNEL_GRENAT |
2391                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2392                        RTE_PTYPE_INNER_L4_TCP,
2393                 [49] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2394                        RTE_PTYPE_TUNNEL_GRENAT |
2395                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2396                        RTE_PTYPE_INNER_L4_SCTP,
2397                 [50] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2398                        RTE_PTYPE_TUNNEL_GRENAT |
2399                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2400                        RTE_PTYPE_INNER_L4_ICMP,
2401
2402                 /* IPv4 --> GRE/Teredo/VXLAN --> IPv6 */
2403                 [51] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2404                        RTE_PTYPE_TUNNEL_GRENAT |
2405                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2406                        RTE_PTYPE_INNER_L4_FRAG,
2407                 [52] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2408                        RTE_PTYPE_TUNNEL_GRENAT |
2409                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2410                        RTE_PTYPE_INNER_L4_NONFRAG,
2411                 [53] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2412                        RTE_PTYPE_TUNNEL_GRENAT |
2413                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2414                        RTE_PTYPE_INNER_L4_UDP,
2415                 /* [54] reserved */
2416                 [55] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2417                        RTE_PTYPE_TUNNEL_GRENAT |
2418                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2419                        RTE_PTYPE_INNER_L4_TCP,
2420                 [56] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2421                        RTE_PTYPE_TUNNEL_GRENAT |
2422                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2423                        RTE_PTYPE_INNER_L4_SCTP,
2424                 [57] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2425                        RTE_PTYPE_TUNNEL_GRENAT |
2426                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2427                        RTE_PTYPE_INNER_L4_ICMP,
2428
2429                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC */
2430                 [58] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2431                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2432
2433                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2434                 [59] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2435                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2436                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2437                        RTE_PTYPE_INNER_L4_FRAG,
2438                 [60] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2439                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2440                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2441                        RTE_PTYPE_INNER_L4_NONFRAG,
2442                 [61] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2443                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2444                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2445                        RTE_PTYPE_INNER_L4_UDP,
2446                 /* [62] reserved */
2447                 [63] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2448                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2449                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2450                        RTE_PTYPE_INNER_L4_TCP,
2451                 [64] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2452                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2453                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2454                        RTE_PTYPE_INNER_L4_SCTP,
2455                 [65] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2456                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2457                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2458                        RTE_PTYPE_INNER_L4_ICMP,
2459
2460                 /* IPv4 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2461                 [66] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2462                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2463                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2464                        RTE_PTYPE_INNER_L4_FRAG,
2465                 [67] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2466                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2467                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2468                        RTE_PTYPE_INNER_L4_NONFRAG,
2469                 [68] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2470                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2471                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2472                        RTE_PTYPE_INNER_L4_UDP,
2473                 /* [69] reserved */
2474                 [70] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2475                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2476                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2477                        RTE_PTYPE_INNER_L4_TCP,
2478                 [71] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2479                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2480                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2481                        RTE_PTYPE_INNER_L4_SCTP,
2482                 [72] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2483                        RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2484                        RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2485                        RTE_PTYPE_INNER_L4_ICMP,
2486                 /* [73] - [87] reserved */
2487
2488                 /* Non tunneled IPv6 */
2489                 [88] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2490                        RTE_PTYPE_L4_FRAG,
2491                 [89] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2492                        RTE_PTYPE_L4_NONFRAG,
2493                 [90] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2494                        RTE_PTYPE_L4_UDP,
2495                 /* [91] reserved */
2496                 [92] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2497                        RTE_PTYPE_L4_TCP,
2498                 [93] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2499                        RTE_PTYPE_L4_SCTP,
2500                 [94] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2501                        RTE_PTYPE_L4_ICMP,
2502
2503                 /* IPv6 --> IPv4 */
2504                 [95] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2505                        RTE_PTYPE_TUNNEL_IP |
2506                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2507                        RTE_PTYPE_INNER_L4_FRAG,
2508                 [96] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2509                        RTE_PTYPE_TUNNEL_IP |
2510                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2511                        RTE_PTYPE_INNER_L4_NONFRAG,
2512                 [97] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2513                        RTE_PTYPE_TUNNEL_IP |
2514                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2515                        RTE_PTYPE_INNER_L4_UDP,
2516                 /* [98] reserved */
2517                 [99] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2518                        RTE_PTYPE_TUNNEL_IP |
2519                        RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2520                        RTE_PTYPE_INNER_L4_TCP,
2521                 [100] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2522                         RTE_PTYPE_TUNNEL_IP |
2523                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2524                         RTE_PTYPE_INNER_L4_SCTP,
2525                 [101] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2526                         RTE_PTYPE_TUNNEL_IP |
2527                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2528                         RTE_PTYPE_INNER_L4_ICMP,
2529
2530                 /* IPv6 --> IPv6 */
2531                 [102] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2532                         RTE_PTYPE_TUNNEL_IP |
2533                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2534                         RTE_PTYPE_INNER_L4_FRAG,
2535                 [103] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2536                         RTE_PTYPE_TUNNEL_IP |
2537                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2538                         RTE_PTYPE_INNER_L4_NONFRAG,
2539                 [104] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2540                         RTE_PTYPE_TUNNEL_IP |
2541                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2542                         RTE_PTYPE_INNER_L4_UDP,
2543                 /* [105] reserved */
2544                 [106] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2545                         RTE_PTYPE_TUNNEL_IP |
2546                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2547                         RTE_PTYPE_INNER_L4_TCP,
2548                 [107] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2549                         RTE_PTYPE_TUNNEL_IP |
2550                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2551                         RTE_PTYPE_INNER_L4_SCTP,
2552                 [108] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2553                         RTE_PTYPE_TUNNEL_IP |
2554                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2555                         RTE_PTYPE_INNER_L4_ICMP,
2556
2557                 /* IPv6 --> GRE/Teredo/VXLAN */
2558                 [109] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2559                         RTE_PTYPE_TUNNEL_GRENAT,
2560
2561                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv4 */
2562                 [110] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2563                         RTE_PTYPE_TUNNEL_GRENAT |
2564                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2565                         RTE_PTYPE_INNER_L4_FRAG,
2566                 [111] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2567                         RTE_PTYPE_TUNNEL_GRENAT |
2568                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2569                         RTE_PTYPE_INNER_L4_NONFRAG,
2570                 [112] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2571                         RTE_PTYPE_TUNNEL_GRENAT |
2572                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2573                         RTE_PTYPE_INNER_L4_UDP,
2574                 /* [113] reserved */
2575                 [114] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2576                         RTE_PTYPE_TUNNEL_GRENAT |
2577                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2578                         RTE_PTYPE_INNER_L4_TCP,
2579                 [115] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2580                         RTE_PTYPE_TUNNEL_GRENAT |
2581                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2582                         RTE_PTYPE_INNER_L4_SCTP,
2583                 [116] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2584                         RTE_PTYPE_TUNNEL_GRENAT |
2585                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2586                         RTE_PTYPE_INNER_L4_ICMP,
2587
2588                 /* IPv6 --> GRE/Teredo/VXLAN --> IPv6 */
2589                 [117] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2590                         RTE_PTYPE_TUNNEL_GRENAT |
2591                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2592                         RTE_PTYPE_INNER_L4_FRAG,
2593                 [118] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2594                         RTE_PTYPE_TUNNEL_GRENAT |
2595                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2596                         RTE_PTYPE_INNER_L4_NONFRAG,
2597                 [119] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2598                         RTE_PTYPE_TUNNEL_GRENAT |
2599                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2600                         RTE_PTYPE_INNER_L4_UDP,
2601                 /* [120] reserved */
2602                 [121] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2603                         RTE_PTYPE_TUNNEL_GRENAT |
2604                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2605                         RTE_PTYPE_INNER_L4_TCP,
2606                 [122] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2607                         RTE_PTYPE_TUNNEL_GRENAT |
2608                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2609                         RTE_PTYPE_INNER_L4_SCTP,
2610                 [123] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2611                         RTE_PTYPE_TUNNEL_GRENAT |
2612                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2613                         RTE_PTYPE_INNER_L4_ICMP,
2614
2615                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC */
2616                 [124] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2617                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER,
2618
2619                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv4 */
2620                 [125] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2621                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2622                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2623                         RTE_PTYPE_INNER_L4_FRAG,
2624                 [126] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2625                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2626                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2627                         RTE_PTYPE_INNER_L4_NONFRAG,
2628                 [127] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2629                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2630                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2631                         RTE_PTYPE_INNER_L4_UDP,
2632                 /* [128] reserved */
2633                 [129] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2634                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2635                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2636                         RTE_PTYPE_INNER_L4_TCP,
2637                 [130] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2638                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2639                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2640                         RTE_PTYPE_INNER_L4_SCTP,
2641                 [131] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2642                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2643                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2644                         RTE_PTYPE_INNER_L4_ICMP,
2645
2646                 /* IPv6 --> GRE/Teredo/VXLAN --> MAC --> IPv6 */
2647                 [132] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2648                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2649                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2650                         RTE_PTYPE_INNER_L4_FRAG,
2651                 [133] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2652                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2653                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2654                         RTE_PTYPE_INNER_L4_NONFRAG,
2655                 [134] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2656                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2657                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2658                         RTE_PTYPE_INNER_L4_UDP,
2659                 /* [135] reserved */
2660                 [136] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2661                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2662                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2663                         RTE_PTYPE_INNER_L4_TCP,
2664                 [137] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2665                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2666                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2667                         RTE_PTYPE_INNER_L4_SCTP,
2668                 [138] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2669                         RTE_PTYPE_TUNNEL_GRENAT | RTE_PTYPE_INNER_L2_ETHER |
2670                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2671                         RTE_PTYPE_INNER_L4_ICMP,
2672                 /* [139] - [299] reserved */
2673
2674                 /* PPPoE */
2675                 [300] = RTE_PTYPE_L2_ETHER_PPPOE,
2676                 [301] = RTE_PTYPE_L2_ETHER_PPPOE,
2677
2678                 /* PPPoE --> IPv4 */
2679                 [302] = RTE_PTYPE_L2_ETHER_PPPOE |
2680                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2681                         RTE_PTYPE_L4_FRAG,
2682                 [303] = RTE_PTYPE_L2_ETHER_PPPOE |
2683                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2684                         RTE_PTYPE_L4_NONFRAG,
2685                 [304] = RTE_PTYPE_L2_ETHER_PPPOE |
2686                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2687                         RTE_PTYPE_L4_UDP,
2688                 [305] = RTE_PTYPE_L2_ETHER_PPPOE |
2689                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2690                         RTE_PTYPE_L4_TCP,
2691                 [306] = RTE_PTYPE_L2_ETHER_PPPOE |
2692                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2693                         RTE_PTYPE_L4_SCTP,
2694                 [307] = RTE_PTYPE_L2_ETHER_PPPOE |
2695                         RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2696                         RTE_PTYPE_L4_ICMP,
2697
2698                 /* PPPoE --> IPv6 */
2699                 [308] = RTE_PTYPE_L2_ETHER_PPPOE |
2700                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2701                         RTE_PTYPE_L4_FRAG,
2702                 [309] = RTE_PTYPE_L2_ETHER_PPPOE |
2703                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2704                         RTE_PTYPE_L4_NONFRAG,
2705                 [310] = RTE_PTYPE_L2_ETHER_PPPOE |
2706                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2707                         RTE_PTYPE_L4_UDP,
2708                 [311] = RTE_PTYPE_L2_ETHER_PPPOE |
2709                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2710                         RTE_PTYPE_L4_TCP,
2711                 [312] = RTE_PTYPE_L2_ETHER_PPPOE |
2712                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2713                         RTE_PTYPE_L4_SCTP,
2714                 [313] = RTE_PTYPE_L2_ETHER_PPPOE |
2715                         RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2716                         RTE_PTYPE_L4_ICMP,
2717                 /* [314] - [324] reserved */
2718
2719                 /* IPv4/IPv6 --> GTPC/GTPU */
2720                 [325] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2721                         RTE_PTYPE_TUNNEL_GTPC,
2722                 [326] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2723                         RTE_PTYPE_TUNNEL_GTPC,
2724                 [327] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2725                         RTE_PTYPE_TUNNEL_GTPC,
2726                 [328] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2727                         RTE_PTYPE_TUNNEL_GTPC,
2728                 [329] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2729                         RTE_PTYPE_TUNNEL_GTPU,
2730                 [330] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2731                         RTE_PTYPE_TUNNEL_GTPU,
2732
2733                 /* IPv4 --> GTPU --> IPv4 */
2734                 [331] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2735                         RTE_PTYPE_TUNNEL_GTPU |
2736                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2737                         RTE_PTYPE_INNER_L4_FRAG,
2738                 [332] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2739                         RTE_PTYPE_TUNNEL_GTPU |
2740                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2741                         RTE_PTYPE_INNER_L4_NONFRAG,
2742                 [333] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2743                         RTE_PTYPE_TUNNEL_GTPU |
2744                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2745                         RTE_PTYPE_INNER_L4_UDP,
2746                 [334] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2747                         RTE_PTYPE_TUNNEL_GTPU |
2748                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2749                         RTE_PTYPE_INNER_L4_TCP,
2750                 [335] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2751                         RTE_PTYPE_TUNNEL_GTPU |
2752                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2753                         RTE_PTYPE_INNER_L4_ICMP,
2754
2755                 /* IPv6 --> GTPU --> IPv4 */
2756                 [336] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2757                         RTE_PTYPE_TUNNEL_GTPU |
2758                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2759                         RTE_PTYPE_INNER_L4_FRAG,
2760                 [337] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2761                         RTE_PTYPE_TUNNEL_GTPU |
2762                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2763                         RTE_PTYPE_INNER_L4_NONFRAG,
2764                 [338] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2765                         RTE_PTYPE_TUNNEL_GTPU |
2766                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2767                         RTE_PTYPE_INNER_L4_UDP,
2768                 [339] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2769                         RTE_PTYPE_TUNNEL_GTPU |
2770                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2771                         RTE_PTYPE_INNER_L4_TCP,
2772                 [340] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2773                         RTE_PTYPE_TUNNEL_GTPU |
2774                         RTE_PTYPE_INNER_L3_IPV4_EXT_UNKNOWN |
2775                         RTE_PTYPE_INNER_L4_ICMP,
2776
2777                 /* IPv4 --> GTPU --> IPv6 */
2778                 [341] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2779                         RTE_PTYPE_TUNNEL_GTPU |
2780                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2781                         RTE_PTYPE_INNER_L4_FRAG,
2782                 [342] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2783                         RTE_PTYPE_TUNNEL_GTPU |
2784                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2785                         RTE_PTYPE_INNER_L4_NONFRAG,
2786                 [343] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2787                         RTE_PTYPE_TUNNEL_GTPU |
2788                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2789                         RTE_PTYPE_INNER_L4_UDP,
2790                 [344] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2791                         RTE_PTYPE_TUNNEL_GTPU |
2792                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2793                         RTE_PTYPE_INNER_L4_TCP,
2794                 [345] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
2795                         RTE_PTYPE_TUNNEL_GTPU |
2796                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2797                         RTE_PTYPE_INNER_L4_ICMP,
2798
2799                 /* IPv6 --> GTPU --> IPv6 */
2800                 [346] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2801                         RTE_PTYPE_TUNNEL_GTPU |
2802                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2803                         RTE_PTYPE_INNER_L4_FRAG,
2804                 [347] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2805                         RTE_PTYPE_TUNNEL_GTPU |
2806                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2807                         RTE_PTYPE_INNER_L4_NONFRAG,
2808                 [348] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2809                         RTE_PTYPE_TUNNEL_GTPU |
2810                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2811                         RTE_PTYPE_INNER_L4_UDP,
2812                 [349] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2813                         RTE_PTYPE_TUNNEL_GTPU |
2814                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2815                         RTE_PTYPE_INNER_L4_TCP,
2816                 [350] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV6_EXT_UNKNOWN |
2817                         RTE_PTYPE_TUNNEL_GTPU |
2818                         RTE_PTYPE_INNER_L3_IPV6_EXT_UNKNOWN |
2819                         RTE_PTYPE_INNER_L4_ICMP,
2820                 /* All others reserved */
2821         };
2822
2823         return ptype_tbl;
2824 }