drivers/net/iavf/iavf_rxtx_vec_avx2.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2019 Intel Corporation
   3  */
   4
   5 #include "base/iavf_prototype.h"
   6 #include "iavf_rxtx_vec_common.h"
   7
   8 #include <x86intrin.h>
   9
  10 #ifndef __INTEL_COMPILER
  11 #pragma GCC diagnostic ignored "-Wcast-qual"
  12 #endif
  13
  14 static inline void
  15 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  16 {
  17         int i;
  18         uint16_t rx_id;
  19         volatile union iavf_rx_desc *rxdp;
  20         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  21
  22         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  23
  24         /* Pull 'n' more MBUFs into the software ring */
  25         if (rte_mempool_get_bulk(rxq->mp,
  26                                  (void *)rxp,
  27                                  IAVF_RXQ_REARM_THRESH) < 0) {
  28                 if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
  29                     rxq->nb_rx_desc) {
  30                         __m128i dma_addr0;
  31
  32                         dma_addr0 = _mm_setzero_si128();
  33                         for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  34                                 rxp[i] = &rxq->fake_mbuf;
  35                                 _mm_store_si128((__m128i *)&rxdp[i].read,
  36                                                 dma_addr0);
  37                         }
  38                 }
  39                 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  40                         IAVF_RXQ_REARM_THRESH;
  41                 return;
  42         }
  43
  44 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  45         struct rte_mbuf *mb0, *mb1;
  46         __m128i dma_addr0, dma_addr1;
  47         __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
  48                         RTE_PKTMBUF_HEADROOM);
  49         /* Initialize the mbufs in vector, process 2 mbufs in one loop */
  50         for (i = 0; i < IAVF_RXQ_REARM_THRESH; i += 2, rxp += 2) {
  51                 __m128i vaddr0, vaddr1;
  52
  53                 mb0 = rxp[0];
  54                 mb1 = rxp[1];
  55
  56                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  57                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
  58                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  59                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  60                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  61
  62                 /* convert pa to dma_addr hdr/data */
  63                 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
  64                 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
  65
  66                 /* add headroom to pa values */
  67                 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
  68                 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
  69
  70                 /* flush desc with pa dma_addr */
  71                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
  72                 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
  73         }
  74 #else
  75         struct rte_mbuf *mb0, *mb1, *mb2, *mb3;
  76         __m256i dma_addr0_1, dma_addr2_3;
  77         __m256i hdr_room = _mm256_set1_epi64x(RTE_PKTMBUF_HEADROOM);
  78         /* Initialize the mbufs in vector, process 4 mbufs in one loop */
  79         for (i = 0; i < IAVF_RXQ_REARM_THRESH;
  80                         i += 4, rxp += 4, rxdp += 4) {
  81                 __m128i vaddr0, vaddr1, vaddr2, vaddr3;
  82                 __m256i vaddr0_1, vaddr2_3;
  83
  84                 mb0 = rxp[0];
  85                 mb1 = rxp[1];
  86                 mb2 = rxp[2];
  87                 mb3 = rxp[3];
  88
  89                 /* load buf_addr(lo 64bit) and buf_physaddr(hi 64bit) */
  90                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_physaddr) !=
  91                                 offsetof(struct rte_mbuf, buf_addr) + 8);
  92                 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
  93                 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
  94                 vaddr2 = _mm_loadu_si128((__m128i *)&mb2->buf_addr);
  95                 vaddr3 = _mm_loadu_si128((__m128i *)&mb3->buf_addr);
  96
  97                 /**
  98                  * merge 0 & 1, by casting 0 to 256-bit and inserting 1
  99                  * into the high lanes. Similarly for 2 & 3
 100                  */
 101                 vaddr0_1 =
 102                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr0),
 103                                                 vaddr1, 1);
 104                 vaddr2_3 =
 105                         _mm256_inserti128_si256(_mm256_castsi128_si256(vaddr2),
 106                                                 vaddr3, 1);
 107
 108                 /* convert pa to dma_addr hdr/data */
 109                 dma_addr0_1 = _mm256_unpackhi_epi64(vaddr0_1, vaddr0_1);
 110                 dma_addr2_3 = _mm256_unpackhi_epi64(vaddr2_3, vaddr2_3);
 111
 112                 /* add headroom to pa values */
 113                 dma_addr0_1 = _mm256_add_epi64(dma_addr0_1, hdr_room);
 114                 dma_addr2_3 = _mm256_add_epi64(dma_addr2_3, hdr_room);
 115
 116                 /* flush desc with pa dma_addr */
 117                 _mm256_store_si256((__m256i *)&rxdp->read, dma_addr0_1);
 118                 _mm256_store_si256((__m256i *)&(rxdp + 2)->read, dma_addr2_3);
 119         }
 120
 121 #endif
 122
 123         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 124         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 125                 rxq->rxrearm_start = 0;
 126
 127         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 128
 129         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 130                              (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 131
 132         /* Update the tail pointer on the NIC */
 133         IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
 134 }
 135
 136 #define PKTLEN_SHIFT     10
 137
 138 static inline uint16_t
 139 _iavf_recv_raw_pkts_vec_avx2(struct iavf_rx_queue *rxq,
 140                              struct rte_mbuf **rx_pkts,
 141                              uint16_t nb_pkts, uint8_t *split_packet)
 142 {
 143 #define IAVF_DESCS_PER_LOOP_AVX 8
 144
 145         /* const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl; */
 146         static const uint32_t type_table[UINT8_MAX + 1] __rte_cache_aligned = {
 147                 /* [0] reserved */
 148                 [1] = RTE_PTYPE_L2_ETHER,
 149                 /* [2] - [21] reserved */
 150                 [22] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 151                         RTE_PTYPE_L4_FRAG,
 152                 [23] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 153                         RTE_PTYPE_L4_NONFRAG,
 154                 [24] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 155                         RTE_PTYPE_L4_UDP,
 156                 /* [25] reserved */
 157                 [26] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 158                         RTE_PTYPE_L4_TCP,
 159                 [27] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 160                         RTE_PTYPE_L4_SCTP,
 161                 [28] = RTE_PTYPE_L2_ETHER | RTE_PTYPE_L3_IPV4_EXT_UNKNOWN |
 162                         RTE_PTYPE_L4_ICMP,
 163                 /* All others reserved */
 164         };
 165         const __m256i mbuf_init = _mm256_set_epi64x(0, 0,
 166                         0, rxq->mbuf_initializer);
 167         /* struct iavf_rx_entry *sw_ring = &rxq->sw_ring[rxq->rx_tail]; */
 168         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 169         volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 170         const int avx_aligned = ((rxq->rx_tail & 1) == 0);
 171
 172         rte_prefetch0(rxdp);
 173
 174         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 175         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 176
 177         /* See if we need to rearm the RX queue - gives the prefetch a bit
 178          * of time to act
 179          */
 180         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 181                 iavf_rxq_rearm(rxq);
 182
 183         /* Before we start moving massive data around, check to see if
 184          * there is actually a packet available
 185          */
 186         if (!(rxdp->wb.qword1.status_error_len &
 187                         rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 188                 return 0;
 189
 190         /* constants used in processing loop */
 191         const __m256i crc_adjust =
 192                 _mm256_set_epi16
 193                         (/* first descriptor */
 194                          0, 0, 0,       /* ignore non-length fields */
 195                          -rxq->crc_len, /* sub crc on data_len */
 196                          0,             /* ignore high-16bits of pkt_len */
 197                          -rxq->crc_len, /* sub crc on pkt_len */
 198                          0, 0,          /* ignore pkt_type field */
 199                          /* second descriptor */
 200                          0, 0, 0,       /* ignore non-length fields */
 201                          -rxq->crc_len, /* sub crc on data_len */
 202                          0,             /* ignore high-16bits of pkt_len */
 203                          -rxq->crc_len, /* sub crc on pkt_len */
 204                          0, 0           /* ignore pkt_type field */
 205                         );
 206
 207         /* 8 packets DD mask, LSB in each 32-bit value */
 208         const __m256i dd_check = _mm256_set1_epi32(1);
 209
 210         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 211         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 212                         IAVF_RX_DESC_STATUS_EOF_SHIFT);
 213
 214         /* mask to shuffle from desc. to mbuf (2 descriptors)*/
 215         const __m256i shuf_msk =
 216                 _mm256_set_epi8
 217                         (/* first descriptor */
 218                          7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 219                          3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 220                          15, 14,      /* octet 15~14, 16 bits data_len */
 221                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 222                          15, 14,      /* octet 15~14, low 16 bits pkt_len */
 223                          0xFF, 0xFF,  /* pkt_type set as unknown */
 224                          0xFF, 0xFF,  /*pkt_type set as unknown */
 225                          /* second descriptor */
 226                          7, 6, 5, 4,  /* octet 4~7, 32bits rss */
 227                          3, 2,        /* octet 2~3, low 16 bits vlan_macip */
 228                          15, 14,      /* octet 15~14, 16 bits data_len */
 229                          0xFF, 0xFF,  /* skip high 16 bits pkt_len, zero out */
 230                          15, 14,      /* octet 15~14, low 16 bits pkt_len */
 231                          0xFF, 0xFF,  /* pkt_type set as unknown */
 232                          0xFF, 0xFF   /*pkt_type set as unknown */
 233                         );
 234         /**
 235          * compile-time check the above crc and shuffle layout is correct.
 236          * NOTE: the first field (lowest address) is given last in set_epi
 237          * calls above.
 238          */
 239         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 240                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 241         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 242                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 243         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 244                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 245         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 246                         offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 247
 248         /* Status/Error flag masks */
 249         /**
 250          * mask everything except RSS, flow director and VLAN flags
 251          * bit2 is for VLAN tag, bit11 for flow director indication
 252          * bit13:12 for RSS indication. Bits 3-5 of error
 253          * field (bits 22-24) are for IP/L4 checksum errors
 254          */
 255         const __m256i flags_mask =
 256                  _mm256_set1_epi32((1 << 2) | (1 << 11) |
 257                                    (3 << 12) | (7 << 22));
 258         /**
 259          * data to be shuffled by result of flag mask. If VLAN bit is set,
 260          * (bit 2), then position 4 in this array will be used in the
 261          * destination
 262          */
 263         const __m256i vlan_flags_shuf =
 264                 _mm256_set_epi32(0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0,
 265                                  0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED, 0);
 266         /**
 267          * data to be shuffled by result of flag mask, shifted down 11.
 268          * If RSS/FDIR bits are set, shuffle moves appropriate flags in
 269          * place.
 270          */
 271         const __m256i rss_flags_shuf =
 272                 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 273                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 274                                 0, 0, 0, 0, PKT_RX_FDIR, 0,/* end up 128-bits */
 275                                 0, 0, 0, 0, 0, 0, 0, 0,
 276                                 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH,
 277                                 0, 0, 0, 0, PKT_RX_FDIR, 0);
 278
 279         /**
 280          * data to be shuffled by the result of the flags mask shifted by 22
 281          * bits.  This gives use the l3_l4 flags.
 282          */
 283         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 284                         /* shift right 1 bit to make sure it not exceed 255 */
 285                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 286                          PKT_RX_IP_CKSUM_BAD) >> 1,
 287                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 288                          PKT_RX_L4_CKSUM_BAD) >> 1,
 289                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 290                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 291                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 292                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 293                         PKT_RX_IP_CKSUM_BAD >> 1,
 294                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1,
 295                         /* second 128-bits */
 296                         0, 0, 0, 0, 0, 0, 0, 0,
 297                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
 298                          PKT_RX_IP_CKSUM_BAD) >> 1,
 299                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
 300                          PKT_RX_L4_CKSUM_BAD) >> 1,
 301                         (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 302                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
 303                         (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
 304                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
 305                         PKT_RX_IP_CKSUM_BAD >> 1,
 306                         (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
 307
 308         const __m256i cksum_mask =
 309                  _mm256_set1_epi32(PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
 310                                    PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
 311                                    PKT_RX_EIP_CKSUM_BAD);
 312
 313         RTE_SET_USED(avx_aligned); /* for 32B descriptors we don't use this */
 314
 315         uint16_t i, received;
 316
 317         for (i = 0, received = 0; i < nb_pkts;
 318              i += IAVF_DESCS_PER_LOOP_AVX,
 319              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 320                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 321                 _mm256_storeu_si256((void *)&rx_pkts[i],
 322                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 323 #ifdef RTE_ARCH_X86_64
 324                 _mm256_storeu_si256
 325                         ((void *)&rx_pkts[i + 4],
 326                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 327 #endif
 328
 329                 __m256i raw_desc0_1, raw_desc2_3, raw_desc4_5, raw_desc6_7;
 330 #ifdef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 331                 /* for AVX we need alignment otherwise loads are not atomic */
 332                 if (avx_aligned) {
 333                         /* load in descriptors, 2 at a time, in reverse order */
 334                         raw_desc6_7 = _mm256_load_si256((void *)(rxdp + 6));
 335                         rte_compiler_barrier();
 336                         raw_desc4_5 = _mm256_load_si256((void *)(rxdp + 4));
 337                         rte_compiler_barrier();
 338                         raw_desc2_3 = _mm256_load_si256((void *)(rxdp + 2));
 339                         rte_compiler_barrier();
 340                         raw_desc0_1 = _mm256_load_si256((void *)(rxdp + 0));
 341                 } else
 342 #endif
 343                 {
 344                         const __m128i raw_desc7 =
 345                                 _mm_load_si128((void *)(rxdp + 7));
 346                         rte_compiler_barrier();
 347                         const __m128i raw_desc6 =
 348                                 _mm_load_si128((void *)(rxdp + 6));
 349                         rte_compiler_barrier();
 350                         const __m128i raw_desc5 =
 351                                 _mm_load_si128((void *)(rxdp + 5));
 352                         rte_compiler_barrier();
 353                         const __m128i raw_desc4 =
 354                                 _mm_load_si128((void *)(rxdp + 4));
 355                         rte_compiler_barrier();
 356                         const __m128i raw_desc3 =
 357                                 _mm_load_si128((void *)(rxdp + 3));
 358                         rte_compiler_barrier();
 359                         const __m128i raw_desc2 =
 360                                 _mm_load_si128((void *)(rxdp + 2));
 361                         rte_compiler_barrier();
 362                         const __m128i raw_desc1 =
 363                                 _mm_load_si128((void *)(rxdp + 1));
 364                         rte_compiler_barrier();
 365                         const __m128i raw_desc0 =
 366                                 _mm_load_si128((void *)(rxdp + 0));
 367
 368                         raw_desc6_7 =
 369                                 _mm256_inserti128_si256
 370                                         (_mm256_castsi128_si256(raw_desc6),
 371                                          raw_desc7, 1);
 372                         raw_desc4_5 =
 373                                 _mm256_inserti128_si256
 374                                         (_mm256_castsi128_si256(raw_desc4),
 375                                          raw_desc5, 1);
 376                         raw_desc2_3 =
 377                                 _mm256_inserti128_si256
 378                                         (_mm256_castsi128_si256(raw_desc2),
 379                                          raw_desc3, 1);
 380                         raw_desc0_1 =
 381                                 _mm256_inserti128_si256
 382                                         (_mm256_castsi128_si256(raw_desc0),
 383                                          raw_desc1, 1);
 384                 }
 385
 386                 if (split_packet) {
 387                         int j;
 388
 389                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 390                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 391                 }
 392
 393                 /**
 394                  * convert descriptors 4-7 into mbufs, adjusting length and
 395                  * re-arranging fields. Then write into the mbuf
 396                  */
 397                 const __m256i len6_7 = _mm256_slli_epi32(raw_desc6_7,
 398                                                          PKTLEN_SHIFT);
 399                 const __m256i len4_5 = _mm256_slli_epi32(raw_desc4_5,
 400                                                          PKTLEN_SHIFT);
 401                 const __m256i desc6_7 = _mm256_blend_epi16(raw_desc6_7,
 402                                                            len6_7, 0x80);
 403                 const __m256i desc4_5 = _mm256_blend_epi16(raw_desc4_5,
 404                                                            len4_5, 0x80);
 405                 __m256i mb6_7 = _mm256_shuffle_epi8(desc6_7, shuf_msk);
 406                 __m256i mb4_5 = _mm256_shuffle_epi8(desc4_5, shuf_msk);
 407
 408                 mb6_7 = _mm256_add_epi16(mb6_7, crc_adjust);
 409                 mb4_5 = _mm256_add_epi16(mb4_5, crc_adjust);
 410                 /**
 411                  * to get packet types, shift 64-bit values down 30 bits
 412                  * and so ptype is in lower 8-bits in each
 413                  */
 414                 const __m256i ptypes6_7 = _mm256_srli_epi64(desc6_7, 30);
 415                 const __m256i ptypes4_5 = _mm256_srli_epi64(desc4_5, 30);
 416                 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
 417                 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
 418                 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
 419                 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
 420
 421                 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype7], 4);
 422                 mb6_7 = _mm256_insert_epi32(mb6_7, type_table[ptype6], 0);
 423                 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype5], 4);
 424                 mb4_5 = _mm256_insert_epi32(mb4_5, type_table[ptype4], 0);
 425                 /* merge the status bits into one register */
 426                 const __m256i status4_7 = _mm256_unpackhi_epi32(desc6_7,
 427                                 desc4_5);
 428
 429                 /**
 430                  * convert descriptors 0-3 into mbufs, adjusting length and
 431                  * re-arranging fields. Then write into the mbuf
 432                  */
 433                 const __m256i len2_3 = _mm256_slli_epi32(raw_desc2_3,
 434                                                          PKTLEN_SHIFT);
 435                 const __m256i len0_1 = _mm256_slli_epi32(raw_desc0_1,
 436                                                          PKTLEN_SHIFT);
 437                 const __m256i desc2_3 = _mm256_blend_epi16(raw_desc2_3,
 438                                                            len2_3, 0x80);
 439                 const __m256i desc0_1 = _mm256_blend_epi16(raw_desc0_1,
 440                                                            len0_1, 0x80);
 441                 __m256i mb2_3 = _mm256_shuffle_epi8(desc2_3, shuf_msk);
 442                 __m256i mb0_1 = _mm256_shuffle_epi8(desc0_1, shuf_msk);
 443
 444                 mb2_3 = _mm256_add_epi16(mb2_3, crc_adjust);
 445                 mb0_1 = _mm256_add_epi16(mb0_1, crc_adjust);
 446                 /* get the packet types */
 447                 const __m256i ptypes2_3 = _mm256_srli_epi64(desc2_3, 30);
 448                 const __m256i ptypes0_1 = _mm256_srli_epi64(desc0_1, 30);
 449                 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
 450                 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
 451                 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
 452                 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
 453
 454                 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype3], 4);
 455                 mb2_3 = _mm256_insert_epi32(mb2_3, type_table[ptype2], 0);
 456                 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype1], 4);
 457                 mb0_1 = _mm256_insert_epi32(mb0_1, type_table[ptype0], 0);
 458                 /* merge the status bits into one register */
 459                 const __m256i status0_3 = _mm256_unpackhi_epi32(desc2_3,
 460                                                                 desc0_1);
 461
 462                 /**
 463                  * take the two sets of status bits and merge to one
 464                  * After merge, the packets status flags are in the
 465                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 466                  */
 467                 __m256i status0_7 = _mm256_unpacklo_epi64(status4_7,
 468                                                           status0_3);
 469
 470                 /* now do flag manipulation */
 471
 472                 /* get only flag/error bits we want */
 473                 const __m256i flag_bits =
 474                         _mm256_and_si256(status0_7, flags_mask);
 475                 /* set vlan and rss flags */
 476                 const __m256i vlan_flags =
 477                         _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
 478                 const __m256i rss_flags =
 479                         _mm256_shuffle_epi8(rss_flags_shuf,
 480                                             _mm256_srli_epi32(flag_bits, 11));
 481                 /**
 482                  * l3_l4_error flags, shuffle, then shift to correct adjustment
 483                  * of flags in flags_shuf, and finally mask out extra bits
 484                  */
 485                 __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 486                                 _mm256_srli_epi32(flag_bits, 22));
 487                 l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 488                 l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 489
 490                 /* merge flags */
 491                 const __m256i mbuf_flags = _mm256_or_si256(l3_l4_flags,
 492                                 _mm256_or_si256(rss_flags, vlan_flags));
 493                 /**
 494                  * At this point, we have the 8 sets of flags in the low 16-bits
 495                  * of each 32-bit value in vlan0.
 496                  * We want to extract these, and merge them with the mbuf init
 497                  * data so we can do a single write to the mbuf to set the flags
 498                  * and all the other initialization fields. Extracting the
 499                  * appropriate flags means that we have to do a shift and blend
 500                  * for each mbuf before we do the write. However, we can also
 501                  * add in the previously computed rx_descriptor fields to
 502                  * make a single 256-bit write per mbuf
 503                  */
 504                 /* check the structure matches expectations */
 505                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 506                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 507                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 508                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 509                                                     rearm_data),
 510                                            16));
 511                 /* build up data and do writes */
 512                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 513                         rearm6, rearm7;
 514                 rearm6 = _mm256_blend_epi32(mbuf_init,
 515                                             _mm256_slli_si256(mbuf_flags, 8),
 516                                             0x04);
 517                 rearm4 = _mm256_blend_epi32(mbuf_init,
 518                                             _mm256_slli_si256(mbuf_flags, 4),
 519                                             0x04);
 520                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 521                 rearm0 = _mm256_blend_epi32(mbuf_init,
 522                                             _mm256_srli_si256(mbuf_flags, 4),
 523                                             0x04);
 524                 /* permute to add in the rx_descriptor e.g. rss fields */
 525                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 526                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 527                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 528                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 529                 /* write to mbuf */
 530                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 531                                     rearm6);
 532                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 533                                     rearm4);
 534                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 535                                     rearm2);
 536                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 537                                     rearm0);
 538
 539                 /* repeat for the odd mbufs */
 540                 const __m256i odd_flags =
 541                         _mm256_castsi128_si256
 542                                 (_mm256_extracti128_si256(mbuf_flags, 1));
 543                 rearm7 = _mm256_blend_epi32(mbuf_init,
 544                                             _mm256_slli_si256(odd_flags, 8),
 545                                             0x04);
 546                 rearm5 = _mm256_blend_epi32(mbuf_init,
 547                                             _mm256_slli_si256(odd_flags, 4),
 548                                             0x04);
 549                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 550                 rearm1 = _mm256_blend_epi32(mbuf_init,
 551                                             _mm256_srli_si256(odd_flags, 4),
 552                                             0x04);
 553                 /* since odd mbufs are already in hi 128-bits use blend */
 554                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 555                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 556                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 557                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 558                 /* again write to mbufs */
 559                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 560                                     rearm7);
 561                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 562                                     rearm5);
 563                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 564                                     rearm3);
 565                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 566                                     rearm1);
 567
 568                 /* extract and record EOP bit */
 569                 if (split_packet) {
 570                         const __m128i eop_mask =
 571                                 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
 572                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 573                                                                      eop_check);
 574                         /* pack status bits into a single 128-bit register */
 575                         const __m128i eop_bits =
 576                                 _mm_packus_epi32
 577                                         (_mm256_castsi256_si128(eop_bits256),
 578                                          _mm256_extractf128_si256(eop_bits256,
 579                                                                   1));
 580                         /**
 581                          * flip bits, and mask out the EOP bit, which is now
 582                          * a split-packet bit i.e. !EOP, rather than EOP one.
 583                          */
 584                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 585                                         eop_mask);
 586                         /**
 587                          * eop bits are out of order, so we need to shuffle them
 588                          * back into order again. In doing so, only use low 8
 589                          * bits, which acts like another pack instruction
 590                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 591                          * [Since we use epi8, the 16-bit positions are
 592                          * multiplied by 2 in the eop_shuffle value.]
 593                          */
 594                         __m128i eop_shuffle =
 595                                 _mm_set_epi8(/* zero hi 64b */
 596                                              0xFF, 0xFF, 0xFF, 0xFF,
 597                                              0xFF, 0xFF, 0xFF, 0xFF,
 598                                              /* move values to lo 64b */
 599                                              8, 0, 10, 2,
 600                                              12, 4, 14, 6);
 601                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 602                         *(uint64_t *)split_packet =
 603                                 _mm_cvtsi128_si64(split_bits);
 604                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
 605                 }
 606
 607                 /* perform dd_check */
 608                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 609                 status0_7 = _mm256_packs_epi32(status0_7,
 610                                                _mm256_setzero_si256());
 611
 612                 uint64_t burst = __builtin_popcountll
 613                                         (_mm_cvtsi128_si64
 614                                                 (_mm256_extracti128_si256
 615                                                         (status0_7, 1)));
 616                 burst += __builtin_popcountll
 617                                 (_mm_cvtsi128_si64
 618                                         (_mm256_castsi256_si128(status0_7)));
 619                 received += burst;
 620                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
 621                         break;
 622         }
 623
 624         /* update tail pointers */
 625         rxq->rx_tail += received;
 626         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 627         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep avx2 aligned */
 628                 rxq->rx_tail--;
 629                 received--;
 630         }
 631         rxq->rxrearm_nb += received;
 632         return received;
 633 }
 634
 635 /**
 636  * Notice:
 637  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 638  */
 639 uint16_t
 640 iavf_recv_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 641                         uint16_t nb_pkts)
 642 {
 643         return _iavf_recv_raw_pkts_vec_avx2(rx_queue, rx_pkts, nb_pkts, NULL);
 644 }
 645
 646 /**
 647  * vPMD receive routine that reassembles single burst of 32 scattered packets
 648  * Notice:
 649  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 650  */
 651 static uint16_t
 652 iavf_recv_scattered_burst_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 653                                    uint16_t nb_pkts)
 654 {
 655         struct iavf_rx_queue *rxq = rx_queue;
 656         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
 657
 658         /* get some new buffers */
 659         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx2(rxq, rx_pkts, nb_pkts,
 660                                                        split_flags);
 661         if (nb_bufs == 0)
 662                 return 0;
 663
 664         /* happy day case, full burst + no packets to be joined */
 665         const uint64_t *split_fl64 = (uint64_t *)split_flags;
 666
 667         if (!rxq->pkt_first_seg &&
 668             split_fl64[0] == 0 && split_fl64[1] == 0 &&
 669             split_fl64[2] == 0 && split_fl64[3] == 0)
 670                 return nb_bufs;
 671
 672         /* reassemble any packets that need reassembly*/
 673         unsigned int i = 0;
 674
 675         if (!rxq->pkt_first_seg) {
 676                 /* find the first split flag, and only reassemble then*/
 677                 while (i < nb_bufs && !split_flags[i])
 678                         i++;
 679                 if (i == nb_bufs)
 680                         return nb_bufs;
 681                 rxq->pkt_first_seg = rx_pkts[i];
 682         }
 683         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
 684                                              &split_flags[i]);
 685 }
 686
 687 /**
 688  * vPMD receive routine that reassembles scattered packets.
 689  * Main receive routine that can handle arbitrary burst sizes
 690  * Notice:
 691  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
 692  */
 693 uint16_t
 694 iavf_recv_scattered_pkts_vec_avx2(void *rx_queue, struct rte_mbuf **rx_pkts,
 695                                   uint16_t nb_pkts)
 696 {
 697         uint16_t retval = 0;
 698
 699         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
 700                 uint16_t burst = iavf_recv_scattered_burst_vec_avx2(rx_queue,
 701                                 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST);
 702                 retval += burst;
 703                 nb_pkts -= burst;
 704                 if (burst < IAVF_VPMD_RX_MAX_BURST)
 705                         return retval;
 706         }
 707         return retval + iavf_recv_scattered_burst_vec_avx2(rx_queue,
 708                                 rx_pkts + retval, nb_pkts);
 709 }
 710
 711 static inline void
 712 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
 713           struct rte_mbuf *pkt, uint64_t flags)
 714 {
 715         uint64_t high_qw =
 716                 (IAVF_TX_DESC_DTYPE_DATA |
 717                  ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
 718                  ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
 719
 720         __m128i descriptor = _mm_set_epi64x(high_qw,
 721                                 pkt->buf_physaddr + pkt->data_off);
 722         _mm_store_si128((__m128i *)txdp, descriptor);
 723 }
 724
 725 static inline void
 726 iavf_vtx(volatile struct iavf_tx_desc *txdp,
 727          struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags)
 728 {
 729         const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
 730                         ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT));
 731
 732         /* if unaligned on 32-bit boundary, do one to align */
 733         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
 734                 iavf_vtx1(txdp, *pkt, flags);
 735                 nb_pkts--, txdp++, pkt++;
 736         }
 737
 738         /* do two at a time while possible, in bursts */
 739         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
 740                 uint64_t hi_qw3 =
 741                         hi_qw_tmpl |
 742                         ((uint64_t)pkt[3]->data_len <<
 743                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
 744                 uint64_t hi_qw2 =
 745                         hi_qw_tmpl |
 746                         ((uint64_t)pkt[2]->data_len <<
 747                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
 748                 uint64_t hi_qw1 =
 749                         hi_qw_tmpl |
 750                         ((uint64_t)pkt[1]->data_len <<
 751                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
 752                 uint64_t hi_qw0 =
 753                         hi_qw_tmpl |
 754                         ((uint64_t)pkt[0]->data_len <<
 755                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
 756
 757                 __m256i desc2_3 =
 758                         _mm256_set_epi64x
 759                                 (hi_qw3,
 760                                  pkt[3]->buf_physaddr + pkt[3]->data_off,
 761                                  hi_qw2,
 762                                  pkt[2]->buf_physaddr + pkt[2]->data_off);
 763                 __m256i desc0_1 =
 764                         _mm256_set_epi64x
 765                                 (hi_qw1,
 766                                  pkt[1]->buf_physaddr + pkt[1]->data_off,
 767                                  hi_qw0,
 768                                  pkt[0]->buf_physaddr + pkt[0]->data_off);
 769                 _mm256_store_si256((void *)(txdp + 2), desc2_3);
 770                 _mm256_store_si256((void *)txdp, desc0_1);
 771         }
 772
 773         /* do any last ones */
 774         while (nb_pkts) {
 775                 iavf_vtx1(txdp, *pkt, flags);
 776                 txdp++, pkt++, nb_pkts--;
 777         }
 778 }
 779
 780 static inline uint16_t
 781 iavf_xmit_fixed_burst_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 782                                uint16_t nb_pkts)
 783 {
 784         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
 785         volatile struct iavf_tx_desc *txdp;
 786         struct iavf_tx_entry *txep;
 787         uint16_t n, nb_commit, tx_id;
 788         /* bit2 is reserved and must be set to 1 according to Spec */
 789         uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
 790         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
 791
 792         /* cross rx_thresh boundary is not allowed */
 793         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
 794
 795         if (txq->nb_free < txq->free_thresh)
 796                 iavf_tx_free_bufs(txq);
 797
 798         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
 799         if (unlikely(nb_pkts == 0))
 800                 return 0;
 801
 802         tx_id = txq->tx_tail;
 803         txdp = &txq->tx_ring[tx_id];
 804         txep = &txq->sw_ring[tx_id];
 805
 806         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
 807
 808         n = (uint16_t)(txq->nb_tx_desc - tx_id);
 809         if (nb_commit >= n) {
 810                 tx_backlog_entry(txep, tx_pkts, n);
 811
 812                 iavf_vtx(txdp, tx_pkts, n - 1, flags);
 813                 tx_pkts += (n - 1);
 814                 txdp += (n - 1);
 815
 816                 iavf_vtx1(txdp, *tx_pkts++, rs);
 817
 818                 nb_commit = (uint16_t)(nb_commit - n);
 819
 820                 tx_id = 0;
 821                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
 822
 823                 /* avoid reach the end of ring */
 824                 txdp = &txq->tx_ring[tx_id];
 825                 txep = &txq->sw_ring[tx_id];
 826         }
 827
 828         tx_backlog_entry(txep, tx_pkts, nb_commit);
 829
 830         iavf_vtx(txdp, tx_pkts, nb_commit, flags);
 831
 832         tx_id = (uint16_t)(tx_id + nb_commit);
 833         if (tx_id > txq->next_rs) {
 834                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
 835                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
 836                                          IAVF_TXD_QW1_CMD_SHIFT);
 837                 txq->next_rs =
 838                         (uint16_t)(txq->next_rs + txq->rs_thresh);
 839         }
 840
 841         txq->tx_tail = tx_id;
 842
 843         IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
 844
 845         return nb_pkts;
 846 }
 847
 848 uint16_t
 849 iavf_xmit_pkts_vec_avx2(void *tx_queue, struct rte_mbuf **tx_pkts,
 850                         uint16_t nb_pkts)
 851 {
 852         uint16_t nb_tx = 0;
 853         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
 854
 855         while (nb_pkts) {
 856                 uint16_t ret, num;
 857
 858                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
 859                 ret = iavf_xmit_fixed_burst_vec_avx2(tx_queue, &tx_pkts[nb_tx],
 860                                                      num);
 861                 nb_tx += ret;
 862                 nb_pkts -= ret;
 863                 if (ret < num)
 864                         break;
 865         }
 866
 867         return nb_tx;
 868 }