drivers/net/iavf/iavf_rxtx_vec_avx512.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2020 Intel Corporation
   3  */
   4
   5 #include "iavf_rxtx_vec_common.h"
   6
   7 #include <x86intrin.h>
   8
   9 #ifndef __INTEL_COMPILER
  10 #pragma GCC diagnostic ignored "-Wcast-qual"
  11 #endif
  12
  13 #define IAVF_DESCS_PER_LOOP_AVX 8
  14 #define PKTLEN_SHIFT 10
  15
  16 /******************************************************************************
  17  * If user knows a specific offload is not enabled by APP,
  18  * the macro can be commented to save the effort of fast path.
  19  * Currently below 2 features are supported in RX path,
  20  * 1, checksum offload
  21  * 2, VLAN/QINQ stripping
  22  * 3, RSS hash
  23  * 4, packet type analysis
  24  * 5, flow director ID report
  25  ******************************************************************************/
  26 #define IAVF_RX_CSUM_OFFLOAD
  27 #define IAVF_RX_VLAN_OFFLOAD
  28 #define IAVF_RX_RSS_OFFLOAD
  29 #define IAVF_RX_PTYPE_OFFLOAD
  30 #define IAVF_RX_FDIR_OFFLOAD
  31
  32 static __rte_always_inline void
  33 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
  34 {
  35         int i;
  36         uint16_t rx_id;
  37         volatile union iavf_rx_desc *rxdp;
  38         struct rte_mempool_cache *cache =
  39                 rte_mempool_default_cache(rxq->mp, rte_lcore_id());
  40         struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
  41
  42         rxdp = rxq->rx_ring + rxq->rxrearm_start;
  43
  44         if (unlikely(!cache))
  45                 return iavf_rxq_rearm_common(rxq, true);
  46
  47         /* We need to pull 'n' more MBUFs into the software ring from mempool
  48          * We inline the mempool function here, so we can vectorize the copy
  49          * from the cache into the shadow ring.
  50          */
  51
  52         /* Can this be satisfied from the cache? */
  53         if (cache->len < IAVF_RXQ_REARM_THRESH) {
  54                 /* No. Backfill the cache first, and then fill from it */
  55                 uint32_t req = IAVF_RXQ_REARM_THRESH + (cache->size -
  56                                                         cache->len);
  57
  58                 /* How many do we require i.e. number to fill the cache + the request */
  59                 int ret = rte_mempool_ops_dequeue_bulk
  60                                 (rxq->mp, &cache->objs[cache->len], req);
  61                 if (ret == 0) {
  62                         cache->len += req;
  63                 } else {
  64                         if (rxq->rxrearm_nb + IAVF_RXQ_REARM_THRESH >=
  65                             rxq->nb_rx_desc) {
  66                                 __m128i dma_addr0;
  67
  68                                 dma_addr0 = _mm_setzero_si128();
  69                                 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
  70                                         rxp[i] = &rxq->fake_mbuf;
  71                                         _mm_storeu_si128((__m128i *)&rxdp[i].read,
  72                                                          dma_addr0);
  73                                 }
  74                         }
  75                         rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
  76                                         IAVF_RXQ_REARM_THRESH;
  77                         return;
  78                 }
  79         }
  80
  81         const __m512i iova_offsets =  _mm512_set1_epi64(offsetof
  82                                                         (struct rte_mbuf, buf_iova));
  83         const __m512i headroom = _mm512_set1_epi64(RTE_PKTMBUF_HEADROOM);
  84
  85 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
  86         /* to shuffle the addresses to correct slots. Values 4-7 will contain
  87          * zeros, so use 7 for a zero-value.
  88          */
  89         const __m512i permute_idx = _mm512_set_epi64(7, 7, 3, 1, 7, 7, 2, 0);
  90 #else
  91         const __m512i permute_idx = _mm512_set_epi64(7, 3, 6, 2, 5, 1, 4, 0);
  92 #endif
  93
  94         /* Initialize the mbufs in vector, process 8 mbufs in one loop, taking
  95          * from mempool cache and populating both shadow and HW rings
  96          */
  97         for (i = 0; i < IAVF_RXQ_REARM_THRESH / IAVF_DESCS_PER_LOOP_AVX; i++) {
  98                 const __m512i mbuf_ptrs = _mm512_loadu_si512
  99                         (&cache->objs[cache->len - IAVF_DESCS_PER_LOOP_AVX]);
 100                 _mm512_storeu_si512(rxp, mbuf_ptrs);
 101
 102                 const __m512i iova_base_addrs = _mm512_i64gather_epi64
 103                                 (_mm512_add_epi64(mbuf_ptrs, iova_offsets),
 104                                  0, /* base */
 105                                  1  /* scale */);
 106                 const __m512i iova_addrs = _mm512_add_epi64(iova_base_addrs,
 107                                 headroom);
 108 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
 109                 const __m512i iovas0 = _mm512_castsi256_si512
 110                                 (_mm512_extracti64x4_epi64(iova_addrs, 0));
 111                 const __m512i iovas1 = _mm512_castsi256_si512
 112                                 (_mm512_extracti64x4_epi64(iova_addrs, 1));
 113
 114                 /* permute leaves desc 2-3 addresses in header address slots 0-1
 115                  * but these are ignored by driver since header split not
 116                  * enabled. Similarly for desc 6 & 7.
 117                  */
 118                 const __m512i desc0_1 = _mm512_permutexvar_epi64
 119                                 (permute_idx,
 120                                  iovas0);
 121                 const __m512i desc2_3 = _mm512_bsrli_epi128(desc0_1, 8);
 122
 123                 const __m512i desc4_5 = _mm512_permutexvar_epi64
 124                                 (permute_idx,
 125                                  iovas1);
 126                 const __m512i desc6_7 = _mm512_bsrli_epi128(desc4_5, 8);
 127
 128                 _mm512_storeu_si512((void *)rxdp, desc0_1);
 129                 _mm512_storeu_si512((void *)(rxdp + 2), desc2_3);
 130                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_5);
 131                 _mm512_storeu_si512((void *)(rxdp + 6), desc6_7);
 132 #else
 133                 /* permute leaves desc 4-7 addresses in header address slots 0-3
 134                  * but these are ignored by driver since header split not
 135                  * enabled.
 136                  */
 137                 const __m512i desc0_3 = _mm512_permutexvar_epi64(permute_idx,
 138                                                                  iova_addrs);
 139                 const __m512i desc4_7 = _mm512_bsrli_epi128(desc0_3, 8);
 140
 141                 _mm512_storeu_si512((void *)rxdp, desc0_3);
 142                 _mm512_storeu_si512((void *)(rxdp + 4), desc4_7);
 143 #endif
 144                 rxp += IAVF_DESCS_PER_LOOP_AVX;
 145                 rxdp += IAVF_DESCS_PER_LOOP_AVX;
 146                 cache->len -= IAVF_DESCS_PER_LOOP_AVX;
 147         }
 148
 149         rxq->rxrearm_start += IAVF_RXQ_REARM_THRESH;
 150         if (rxq->rxrearm_start >= rxq->nb_rx_desc)
 151                 rxq->rxrearm_start = 0;
 152
 153         rxq->rxrearm_nb -= IAVF_RXQ_REARM_THRESH;
 154
 155         rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
 156                            (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
 157
 158         /* Update the tail pointer on the NIC */
 159         IAVF_PCI_REG_WC_WRITE(rxq->qrx_tail, rx_id);
 160 }
 161
 162 #define IAVF_RX_LEN_MASK 0x80808080
 163 static __rte_always_inline uint16_t
 164 _iavf_recv_raw_pkts_vec_avx512(struct iavf_rx_queue *rxq,
 165                                struct rte_mbuf **rx_pkts,
 166                                uint16_t nb_pkts, uint8_t *split_packet,
 167                                bool offload)
 168 {
 169 #ifdef IAVF_RX_PTYPE_OFFLOAD
 170         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 171 #endif
 172
 173         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 174                                                     rxq->mbuf_initializer);
 175         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 176         volatile union iavf_rx_desc *rxdp = rxq->rx_ring + rxq->rx_tail;
 177
 178         rte_prefetch0(rxdp);
 179
 180         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 181         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 182
 183         /* See if we need to rearm the RX queue - gives the prefetch a bit
 184          * of time to act
 185          */
 186         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 187                 iavf_rxq_rearm(rxq);
 188
 189         /* Before we start moving massive data around, check to see if
 190          * there is actually a packet available
 191          */
 192         if (!(rxdp->wb.qword1.status_error_len &
 193               rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
 194                 return 0;
 195
 196         /* constants used in processing loop */
 197         const __m512i crc_adjust =
 198                 _mm512_set_epi32
 199                         (/* 1st descriptor */
 200                          0,             /* ignore non-length fields */
 201                          -rxq->crc_len, /* sub crc on data_len */
 202                          -rxq->crc_len, /* sub crc on pkt_len */
 203                          0,             /* ignore pkt_type field */
 204                          /* 2nd descriptor */
 205                          0,             /* ignore non-length fields */
 206                          -rxq->crc_len, /* sub crc on data_len */
 207                          -rxq->crc_len, /* sub crc on pkt_len */
 208                          0,             /* ignore pkt_type field */
 209                          /* 3rd descriptor */
 210                          0,             /* ignore non-length fields */
 211                          -rxq->crc_len, /* sub crc on data_len */
 212                          -rxq->crc_len, /* sub crc on pkt_len */
 213                          0,             /* ignore pkt_type field */
 214                          /* 4th descriptor */
 215                          0,             /* ignore non-length fields */
 216                          -rxq->crc_len, /* sub crc on data_len */
 217                          -rxq->crc_len, /* sub crc on pkt_len */
 218                          0              /* ignore pkt_type field */
 219                         );
 220
 221         /* 8 packets DD mask, LSB in each 32-bit value */
 222         const __m256i dd_check = _mm256_set1_epi32(1);
 223
 224         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 225         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 226                         IAVF_RX_DESC_STATUS_EOF_SHIFT);
 227
 228         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 229         const __m512i shuf_msk =
 230                 _mm512_set_epi32
 231                         (/* 1st descriptor */
 232                          0x07060504,    /* octet 4~7, 32bits rss */
 233                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 234                                         /* octet 15~14, 16 bits data_len */
 235                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 236                                         /* octet 15~14, low 16 bits pkt_len */
 237                          0xFFFFFFFF,    /* pkt_type set as unknown */
 238                          /* 2nd descriptor */
 239                          0x07060504,    /* octet 4~7, 32bits rss */
 240                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 241                                         /* octet 15~14, 16 bits data_len */
 242                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 243                                         /* octet 15~14, low 16 bits pkt_len */
 244                          0xFFFFFFFF,    /* pkt_type set as unknown */
 245                          /* 3rd descriptor */
 246                          0x07060504,    /* octet 4~7, 32bits rss */
 247                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 248                                         /* octet 15~14, 16 bits data_len */
 249                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 250                                         /* octet 15~14, low 16 bits pkt_len */
 251                          0xFFFFFFFF,    /* pkt_type set as unknown */
 252                          /* 4th descriptor */
 253                          0x07060504,    /* octet 4~7, 32bits rss */
 254                          0x03020F0E,    /* octet 2~3, low 16 bits vlan_macip */
 255                                         /* octet 15~14, 16 bits data_len */
 256                          0xFFFF0F0E,    /* skip high 16 bits pkt_len, zero out */
 257                                         /* octet 15~14, low 16 bits pkt_len */
 258                          0xFFFFFFFF     /* pkt_type set as unknown */
 259                         );
 260         /**
 261          * compile-time check the above crc and shuffle layout is correct.
 262          * NOTE: the first field (lowest address) is given last in set_epi
 263          * calls above.
 264          */
 265         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 266                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 267         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 268                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 269         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 270                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 271         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 272                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 273
 274         uint16_t i, received;
 275
 276         for (i = 0, received = 0; i < nb_pkts;
 277              i += IAVF_DESCS_PER_LOOP_AVX,
 278              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 279                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 280                 _mm256_storeu_si256((void *)&rx_pkts[i],
 281                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 282 #ifdef RTE_ARCH_X86_64
 283                 _mm256_storeu_si256
 284                         ((void *)&rx_pkts[i + 4],
 285                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 286 #endif
 287
 288                 __m512i raw_desc0_3, raw_desc4_7;
 289                 const __m128i raw_desc7 =
 290                         _mm_load_si128((void *)(rxdp + 7));
 291                 rte_compiler_barrier();
 292                 const __m128i raw_desc6 =
 293                         _mm_load_si128((void *)(rxdp + 6));
 294                 rte_compiler_barrier();
 295                 const __m128i raw_desc5 =
 296                         _mm_load_si128((void *)(rxdp + 5));
 297                 rte_compiler_barrier();
 298                 const __m128i raw_desc4 =
 299                         _mm_load_si128((void *)(rxdp + 4));
 300                 rte_compiler_barrier();
 301                 const __m128i raw_desc3 =
 302                         _mm_load_si128((void *)(rxdp + 3));
 303                 rte_compiler_barrier();
 304                 const __m128i raw_desc2 =
 305                         _mm_load_si128((void *)(rxdp + 2));
 306                 rte_compiler_barrier();
 307                 const __m128i raw_desc1 =
 308                         _mm_load_si128((void *)(rxdp + 1));
 309                 rte_compiler_barrier();
 310                 const __m128i raw_desc0 =
 311                         _mm_load_si128((void *)(rxdp + 0));
 312
 313                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 314                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 315                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 316                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 317                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 318                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 319                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 320                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 321
 322                 if (split_packet) {
 323                         int j;
 324
 325                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 326                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 327                 }
 328
 329                 /**
 330                  * convert descriptors 4-7 into mbufs, adjusting length and
 331                  * re-arranging fields. Then write into the mbuf
 332                  */
 333                 const __m512i len4_7 = _mm512_slli_epi32(raw_desc4_7,
 334                                                          PKTLEN_SHIFT);
 335                 const __m512i desc4_7 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 336                                                                 raw_desc4_7,
 337                                                                 len4_7);
 338                 __m512i mb4_7 = _mm512_shuffle_epi8(desc4_7, shuf_msk);
 339
 340                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 341 #ifdef IAVF_RX_PTYPE_OFFLOAD
 342                 /**
 343                  * to get packet types, shift 64-bit values down 30 bits
 344                  * and so ptype is in lower 8-bits in each
 345                  */
 346                 const __m512i ptypes4_7 = _mm512_srli_epi64(desc4_7, 30);
 347                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 348                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 349                 const uint8_t ptype7 = _mm256_extract_epi8(ptypes6_7, 24);
 350                 const uint8_t ptype6 = _mm256_extract_epi8(ptypes6_7, 8);
 351                 const uint8_t ptype5 = _mm256_extract_epi8(ptypes4_5, 24);
 352                 const uint8_t ptype4 = _mm256_extract_epi8(ptypes4_5, 8);
 353
 354                 const __m512i ptype4_7 = _mm512_set_epi32
 355                         (0, 0, 0, type_table[ptype7],
 356                          0, 0, 0, type_table[ptype6],
 357                          0, 0, 0, type_table[ptype5],
 358                          0, 0, 0, type_table[ptype4]);
 359                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 360 #endif
 361
 362                 /**
 363                  * convert descriptors 0-3 into mbufs, adjusting length and
 364                  * re-arranging fields. Then write into the mbuf
 365                  */
 366                 const __m512i len0_3 = _mm512_slli_epi32(raw_desc0_3,
 367                                                          PKTLEN_SHIFT);
 368                 const __m512i desc0_3 = _mm512_mask_blend_epi16(IAVF_RX_LEN_MASK,
 369                                                                 raw_desc0_3,
 370                                                                 len0_3);
 371                 __m512i mb0_3 = _mm512_shuffle_epi8(desc0_3, shuf_msk);
 372
 373                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 374 #ifdef IAVF_RX_PTYPE_OFFLOAD
 375                 /* get the packet types */
 376                 const __m512i ptypes0_3 = _mm512_srli_epi64(desc0_3, 30);
 377                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 378                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 379                 const uint8_t ptype3 = _mm256_extract_epi8(ptypes2_3, 24);
 380                 const uint8_t ptype2 = _mm256_extract_epi8(ptypes2_3, 8);
 381                 const uint8_t ptype1 = _mm256_extract_epi8(ptypes0_1, 24);
 382                 const uint8_t ptype0 = _mm256_extract_epi8(ptypes0_1, 8);
 383
 384                 const __m512i ptype0_3 = _mm512_set_epi32
 385                         (0, 0, 0, type_table[ptype3],
 386                          0, 0, 0, type_table[ptype2],
 387                          0, 0, 0, type_table[ptype1],
 388                          0, 0, 0, type_table[ptype0]);
 389                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 390 #endif
 391
 392                 /**
 393                  * use permute/extract to get status content
 394                  * After the operations, the packets status flags are in the
 395                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 396                  */
 397                 /* merge the status bits into one register */
 398                 const __m512i status_permute_msk = _mm512_set_epi32
 399                         (0, 0, 0, 0,
 400                          0, 0, 0, 0,
 401                          22, 30, 6, 14,
 402                          18, 26, 2, 10);
 403                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 404                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 405                 __m256i status0_7 = _mm512_extracti64x4_epi64
 406                         (raw_status0_7, 0);
 407
 408                 /* now do flag manipulation */
 409
 410                 /* merge flags */
 411                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 412
 413                 if (offload) {
 414 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 415                         /* Status/Error flag masks */
 416                         /**
 417                          * mask everything except RSS, flow director and VLAN flags
 418                          * bit2 is for VLAN tag, bit11 for flow director indication
 419                          * bit13:12 for RSS indication. Bits 3-5 of error
 420                          * field (bits 22-24) are for IP/L4 checksum errors
 421                          */
 422                         const __m256i flags_mask =
 423                                 _mm256_set1_epi32((1 << 2) | (1 << 11) |
 424                                                   (3 << 12) | (7 << 22));
 425 #endif
 426
 427 #ifdef IAVF_RX_VLAN_OFFLOAD
 428                         /**
 429                          * data to be shuffled by result of flag mask. If VLAN bit is set,
 430                          * (bit 2), then position 4 in this array will be used in the
 431                          * destination
 432                          */
 433                         const __m256i vlan_flags_shuf =
 434                                 _mm256_set_epi32(0, 0,
 435                                                  RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
 436                                                  0,
 437                                                  0, 0,
 438                                                  RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
 439                                                  0);
 440 #endif
 441
 442 #ifdef IAVF_RX_RSS_OFFLOAD
 443                         /**
 444                          * data to be shuffled by result of flag mask, shifted down 11.
 445                          * If RSS/FDIR bits are set, shuffle moves appropriate flags in
 446                          * place.
 447                          */
 448                         const __m256i rss_flags_shuf =
 449                                 _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 450                                                 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR,
 451                                                 RTE_MBUF_F_RX_RSS_HASH,
 452                                                 0, 0, 0, 0,
 453                                                 RTE_MBUF_F_RX_FDIR, 0,
 454                                                 /* end up 128-bits */
 455                                                 0, 0, 0, 0, 0, 0, 0, 0,
 456                                                 RTE_MBUF_F_RX_RSS_HASH | RTE_MBUF_F_RX_FDIR,
 457                                                 RTE_MBUF_F_RX_RSS_HASH,
 458                                                 0, 0, 0, 0,
 459                                                 RTE_MBUF_F_RX_FDIR, 0);
 460 #endif
 461
 462 #ifdef IAVF_RX_CSUM_OFFLOAD
 463                         /**
 464                          * data to be shuffled by the result of the flags mask shifted by 22
 465                          * bits.  This gives use the l3_l4 flags.
 466                          */
 467                         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 468                                         /* shift right 1 bit to make sure it not exceed 255 */
 469                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 470                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 471                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
 472                                          RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 473                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 474                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
 475                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 476                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 477                                         RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
 478                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1,
 479                                         /* second 128-bits */
 480                                         0, 0, 0, 0, 0, 0, 0, 0,
 481                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 482                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 483                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD |
 484                                          RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 485                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 486                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD) >> 1,
 487                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 488                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD) >> 1,
 489                                         RTE_MBUF_F_RX_IP_CKSUM_BAD >> 1,
 490                                         (RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_GOOD) >> 1);
 491
 492                         const __m256i cksum_mask =
 493                                 _mm256_set1_epi32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
 494                                                   RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 495                                                   RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
 496 #endif
 497
 498 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 499                         /* get only flag/error bits we want */
 500                         const __m256i flag_bits =
 501                                 _mm256_and_si256(status0_7, flags_mask);
 502 #endif
 503                         /* set vlan and rss flags */
 504 #ifdef IAVF_RX_VLAN_OFFLOAD
 505                         const __m256i vlan_flags =
 506                                 _mm256_shuffle_epi8(vlan_flags_shuf, flag_bits);
 507 #endif
 508 #ifdef IAVF_RX_RSS_OFFLOAD
 509                         const __m256i rss_flags =
 510                                 _mm256_shuffle_epi8(rss_flags_shuf,
 511                                                     _mm256_srli_epi32(flag_bits, 11));
 512 #endif
 513 #ifdef IAVF_RX_CSUM_OFFLOAD
 514                         /**
 515                          * l3_l4_error flags, shuffle, then shift to correct adjustment
 516                          * of flags in flags_shuf, and finally mask out extra bits
 517                          */
 518                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
 519                                                         _mm256_srli_epi32(flag_bits, 22));
 520                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
 521                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
 522 #endif
 523
 524 #ifdef IAVF_RX_CSUM_OFFLOAD
 525                         mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
 526 #endif
 527 #ifdef IAVF_RX_RSS_OFFLOAD
 528                         mbuf_flags = _mm256_or_si256(mbuf_flags, rss_flags);
 529 #endif
 530 #ifdef IAVF_RX_VLAN_OFFLOAD
 531                         mbuf_flags = _mm256_or_si256(mbuf_flags, vlan_flags);
 532 #endif
 533                 }
 534
 535                 /**
 536                  * At this point, we have the 8 sets of flags in the low 16-bits
 537                  * of each 32-bit value in vlan0.
 538                  * We want to extract these, and merge them with the mbuf init
 539                  * data so we can do a single write to the mbuf to set the flags
 540                  * and all the other initialization fields. Extracting the
 541                  * appropriate flags means that we have to do a shift and blend
 542                  * for each mbuf before we do the write. However, we can also
 543                  * add in the previously computed rx_descriptor fields to
 544                  * make a single 256-bit write per mbuf
 545                  */
 546                 /* check the structure matches expectations */
 547                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
 548                                  offsetof(struct rte_mbuf, rearm_data) + 8);
 549                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
 550                                  RTE_ALIGN(offsetof(struct rte_mbuf,
 551                                                     rearm_data),
 552                                                     16));
 553                 /* build up data and do writes */
 554                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
 555                         rearm6, rearm7;
 556                 const __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
 557                 const __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
 558                 const __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
 559                 const __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
 560
 561                 if (offload) {
 562                         rearm6 = _mm256_blend_epi32(mbuf_init,
 563                                                     _mm256_slli_si256(mbuf_flags, 8),
 564                                                     0x04);
 565                         rearm4 = _mm256_blend_epi32(mbuf_init,
 566                                                     _mm256_slli_si256(mbuf_flags, 4),
 567                                                     0x04);
 568                         rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
 569                         rearm0 = _mm256_blend_epi32(mbuf_init,
 570                                                     _mm256_srli_si256(mbuf_flags, 4),
 571                                                     0x04);
 572                         /* permute to add in the rx_descriptor e.g. rss fields */
 573                         rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
 574                         rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
 575                         rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
 576                         rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
 577                 } else {
 578                         rearm6 = _mm256_permute2f128_si256(mbuf_init, mb6_7, 0x20);
 579                         rearm4 = _mm256_permute2f128_si256(mbuf_init, mb4_5, 0x20);
 580                         rearm2 = _mm256_permute2f128_si256(mbuf_init, mb2_3, 0x20);
 581                         rearm0 = _mm256_permute2f128_si256(mbuf_init, mb0_1, 0x20);
 582                 }
 583                 /* write to mbuf */
 584                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
 585                                     rearm6);
 586                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
 587                                     rearm4);
 588                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
 589                                     rearm2);
 590                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
 591                                     rearm0);
 592
 593                 /* repeat for the odd mbufs */
 594                 if (offload) {
 595                         const __m256i odd_flags =
 596                                 _mm256_castsi128_si256
 597                                         (_mm256_extracti128_si256(mbuf_flags, 1));
 598                         rearm7 = _mm256_blend_epi32(mbuf_init,
 599                                                     _mm256_slli_si256(odd_flags, 8),
 600                                                     0x04);
 601                         rearm5 = _mm256_blend_epi32(mbuf_init,
 602                                                     _mm256_slli_si256(odd_flags, 4),
 603                                                     0x04);
 604                         rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
 605                         rearm1 = _mm256_blend_epi32(mbuf_init,
 606                                                     _mm256_srli_si256(odd_flags, 4),
 607                                                     0x04);
 608                         /* since odd mbufs are already in hi 128-bits use blend */
 609                         rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
 610                         rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
 611                         rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
 612                         rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
 613                 } else {
 614                         rearm7 = _mm256_blend_epi32(mbuf_init, mb6_7, 0xF0);
 615                         rearm5 = _mm256_blend_epi32(mbuf_init, mb4_5, 0xF0);
 616                         rearm3 = _mm256_blend_epi32(mbuf_init, mb2_3, 0xF0);
 617                         rearm1 = _mm256_blend_epi32(mbuf_init, mb0_1, 0xF0);
 618                 }
 619                 /* again write to mbufs */
 620                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
 621                                     rearm7);
 622                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
 623                                     rearm5);
 624                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
 625                                     rearm3);
 626                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
 627                                     rearm1);
 628
 629                 /* extract and record EOP bit */
 630                 if (split_packet) {
 631                         const __m128i eop_mask =
 632                                 _mm_set1_epi16(1 << IAVF_RX_DESC_STATUS_EOF_SHIFT);
 633                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
 634                                                                      eop_check);
 635                         /* pack status bits into a single 128-bit register */
 636                         const __m128i eop_bits =
 637                                 _mm_packus_epi32
 638                                         (_mm256_castsi256_si128(eop_bits256),
 639                                          _mm256_extractf128_si256(eop_bits256,
 640                                                                   1));
 641                         /**
 642                          * flip bits, and mask out the EOP bit, which is now
 643                          * a split-packet bit i.e. !EOP, rather than EOP one.
 644                          */
 645                         __m128i split_bits = _mm_andnot_si128(eop_bits,
 646                                                               eop_mask);
 647                         /**
 648                          * eop bits are out of order, so we need to shuffle them
 649                          * back into order again. In doing so, only use low 8
 650                          * bits, which acts like another pack instruction
 651                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
 652                          * [Since we use epi8, the 16-bit positions are
 653                          * multiplied by 2 in the eop_shuffle value.]
 654                          */
 655                         __m128i eop_shuffle =
 656                                 _mm_set_epi8(/* zero hi 64b */
 657                                              0xFF, 0xFF, 0xFF, 0xFF,
 658                                              0xFF, 0xFF, 0xFF, 0xFF,
 659                                              /* move values to lo 64b */
 660                                              8, 0, 10, 2,
 661                                              12, 4, 14, 6);
 662                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
 663                         *(uint64_t *)split_packet =
 664                                 _mm_cvtsi128_si64(split_bits);
 665                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
 666                 }
 667
 668                 /* perform dd_check */
 669                 status0_7 = _mm256_and_si256(status0_7, dd_check);
 670                 status0_7 = _mm256_packs_epi32(status0_7,
 671                                                _mm256_setzero_si256());
 672
 673                 uint64_t burst = __builtin_popcountll
 674                                         (_mm_cvtsi128_si64
 675                                                 (_mm256_extracti128_si256
 676                                                         (status0_7, 1)));
 677                 burst += __builtin_popcountll
 678                                 (_mm_cvtsi128_si64
 679                                         (_mm256_castsi256_si128(status0_7)));
 680                 received += burst;
 681                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
 682                         break;
 683         }
 684
 685         /* update tail pointers */
 686         rxq->rx_tail += received;
 687         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
 688         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
 689                 rxq->rx_tail--;
 690                 received--;
 691         }
 692         rxq->rxrearm_nb += received;
 693         return received;
 694 }
 695
 696 static __rte_always_inline __m256i
 697 flex_rxd_to_fdir_flags_vec_avx512(const __m256i fdir_id0_7)
 698 {
 699 #define FDID_MIS_MAGIC 0xFFFFFFFF
 700         RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR != (1 << 2));
 701         RTE_BUILD_BUG_ON(RTE_MBUF_F_RX_FDIR_ID != (1 << 13));
 702         const __m256i pkt_fdir_bit = _mm256_set1_epi32(RTE_MBUF_F_RX_FDIR |
 703                                                        RTE_MBUF_F_RX_FDIR_ID);
 704         /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
 705         const __m256i fdir_mis_mask = _mm256_set1_epi32(FDID_MIS_MAGIC);
 706         __m256i fdir_mask = _mm256_cmpeq_epi32(fdir_id0_7,
 707                                                fdir_mis_mask);
 708         /* this XOR op results to bit-reverse the fdir_mask */
 709         fdir_mask = _mm256_xor_si256(fdir_mask, fdir_mis_mask);
 710         const __m256i fdir_flags = _mm256_and_si256(fdir_mask, pkt_fdir_bit);
 711
 712         return fdir_flags;
 713 }
 714
 715 static __rte_always_inline uint16_t
 716 _iavf_recv_raw_pkts_vec_avx512_flex_rxd(struct iavf_rx_queue *rxq,
 717                                         struct rte_mbuf **rx_pkts,
 718                                         uint16_t nb_pkts,
 719                                         uint8_t *split_packet,
 720                                         bool offload)
 721 {
 722 #ifdef IAVF_RX_PTYPE_OFFLOAD
 723         const uint32_t *type_table = rxq->vsi->adapter->ptype_tbl;
 724 #endif
 725
 726         const __m256i mbuf_init = _mm256_set_epi64x(0, 0, 0,
 727                                                     rxq->mbuf_initializer);
 728         struct rte_mbuf **sw_ring = &rxq->sw_ring[rxq->rx_tail];
 729         volatile union iavf_rx_flex_desc *rxdp =
 730                 (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
 731
 732         rte_prefetch0(rxdp);
 733
 734         /* nb_pkts has to be floor-aligned to IAVF_DESCS_PER_LOOP_AVX */
 735         nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_DESCS_PER_LOOP_AVX);
 736
 737         /* See if we need to rearm the RX queue - gives the prefetch a bit
 738          * of time to act
 739          */
 740         if (rxq->rxrearm_nb > IAVF_RXQ_REARM_THRESH)
 741                 iavf_rxq_rearm(rxq);
 742
 743         /* Before we start moving massive data around, check to see if
 744          * there is actually a packet available
 745          */
 746         if (!(rxdp->wb.status_error0 &
 747               rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
 748                 return 0;
 749
 750         /* constants used in processing loop */
 751         const __m512i crc_adjust =
 752                 _mm512_set_epi32
 753                         (/* 1st descriptor */
 754                          0,             /* ignore non-length fields */
 755                          -rxq->crc_len, /* sub crc on data_len */
 756                          -rxq->crc_len, /* sub crc on pkt_len */
 757                          0,             /* ignore pkt_type field */
 758                          /* 2nd descriptor */
 759                          0,             /* ignore non-length fields */
 760                          -rxq->crc_len, /* sub crc on data_len */
 761                          -rxq->crc_len, /* sub crc on pkt_len */
 762                          0,             /* ignore pkt_type field */
 763                          /* 3rd descriptor */
 764                          0,             /* ignore non-length fields */
 765                          -rxq->crc_len, /* sub crc on data_len */
 766                          -rxq->crc_len, /* sub crc on pkt_len */
 767                          0,             /* ignore pkt_type field */
 768                          /* 4th descriptor */
 769                          0,             /* ignore non-length fields */
 770                          -rxq->crc_len, /* sub crc on data_len */
 771                          -rxq->crc_len, /* sub crc on pkt_len */
 772                          0              /* ignore pkt_type field */
 773                         );
 774
 775         /* 8 packets DD mask, LSB in each 32-bit value */
 776         const __m256i dd_check = _mm256_set1_epi32(1);
 777
 778         /* 8 packets EOP mask, second-LSB in each 32-bit value */
 779         const __m256i eop_check = _mm256_slli_epi32(dd_check,
 780                         IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
 781
 782         /* mask to shuffle from desc. to mbuf (4 descriptors)*/
 783         const __m512i shuf_msk =
 784                 _mm512_set_epi32
 785                         (/* 1st descriptor */
 786                          0xFFFFFFFF,    /* rss hash parsed separately */
 787                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 788                                         /* octet 4~5, 16 bits data_len */
 789                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 790                                         /* octet 4~5, 16 bits pkt_len */
 791                          0xFFFFFFFF,    /* pkt_type set as unknown */
 792                          /* 2nd descriptor */
 793                          0xFFFFFFFF,    /* rss hash parsed separately */
 794                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 795                                         /* octet 4~5, 16 bits data_len */
 796                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 797                                         /* octet 4~5, 16 bits pkt_len */
 798                          0xFFFFFFFF,    /* pkt_type set as unknown */
 799                          /* 3rd descriptor */
 800                          0xFFFFFFFF,    /* rss hash parsed separately */
 801                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 802                                         /* octet 4~5, 16 bits data_len */
 803                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 804                                         /* octet 4~5, 16 bits pkt_len */
 805                          0xFFFFFFFF,    /* pkt_type set as unknown */
 806                          /* 4th descriptor */
 807                          0xFFFFFFFF,    /* rss hash parsed separately */
 808                          0x0B0A0504,    /* octet 10~11, 16 bits vlan_macip */
 809                                         /* octet 4~5, 16 bits data_len */
 810                          0xFFFF0504,    /* skip hi 16 bits pkt_len, zero out */
 811                                         /* octet 4~5, 16 bits pkt_len */
 812                          0xFFFFFFFF     /* pkt_type set as unknown */
 813                         );
 814         /**
 815          * compile-time check the above crc and shuffle layout is correct.
 816          * NOTE: the first field (lowest address) is given last in set_epi
 817          * calls above.
 818          */
 819         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
 820                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
 821         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
 822                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
 823         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
 824                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
 825         RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
 826                          offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
 827
 828         uint16_t i, received;
 829
 830         for (i = 0, received = 0; i < nb_pkts;
 831              i += IAVF_DESCS_PER_LOOP_AVX,
 832              rxdp += IAVF_DESCS_PER_LOOP_AVX) {
 833                 /* step 1, copy over 8 mbuf pointers to rx_pkts array */
 834                 _mm256_storeu_si256((void *)&rx_pkts[i],
 835                                     _mm256_loadu_si256((void *)&sw_ring[i]));
 836 #ifdef RTE_ARCH_X86_64
 837                 _mm256_storeu_si256
 838                         ((void *)&rx_pkts[i + 4],
 839                          _mm256_loadu_si256((void *)&sw_ring[i + 4]));
 840 #endif
 841
 842                 __m512i raw_desc0_3, raw_desc4_7;
 843
 844                 const __m128i raw_desc7 =
 845                         _mm_load_si128((void *)(rxdp + 7));
 846                 rte_compiler_barrier();
 847                 const __m128i raw_desc6 =
 848                         _mm_load_si128((void *)(rxdp + 6));
 849                 rte_compiler_barrier();
 850                 const __m128i raw_desc5 =
 851                         _mm_load_si128((void *)(rxdp + 5));
 852                 rte_compiler_barrier();
 853                 const __m128i raw_desc4 =
 854                         _mm_load_si128((void *)(rxdp + 4));
 855                 rte_compiler_barrier();
 856                 const __m128i raw_desc3 =
 857                         _mm_load_si128((void *)(rxdp + 3));
 858                 rte_compiler_barrier();
 859                 const __m128i raw_desc2 =
 860                         _mm_load_si128((void *)(rxdp + 2));
 861                 rte_compiler_barrier();
 862                 const __m128i raw_desc1 =
 863                         _mm_load_si128((void *)(rxdp + 1));
 864                 rte_compiler_barrier();
 865                 const __m128i raw_desc0 =
 866                         _mm_load_si128((void *)(rxdp + 0));
 867
 868                 raw_desc4_7 = _mm512_broadcast_i32x4(raw_desc4);
 869                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc5, 1);
 870                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc6, 2);
 871                 raw_desc4_7 = _mm512_inserti32x4(raw_desc4_7, raw_desc7, 3);
 872                 raw_desc0_3 = _mm512_broadcast_i32x4(raw_desc0);
 873                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc1, 1);
 874                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc2, 2);
 875                 raw_desc0_3 = _mm512_inserti32x4(raw_desc0_3, raw_desc3, 3);
 876
 877                 if (split_packet) {
 878                         int j;
 879
 880                         for (j = 0; j < IAVF_DESCS_PER_LOOP_AVX; j++)
 881                                 rte_mbuf_prefetch_part2(rx_pkts[i + j]);
 882                 }
 883
 884                 /**
 885                  * convert descriptors 4-7 into mbufs, re-arrange fields.
 886                  * Then write into the mbuf.
 887                  */
 888                 __m512i mb4_7 = _mm512_shuffle_epi8(raw_desc4_7, shuf_msk);
 889
 890                 mb4_7 = _mm512_add_epi32(mb4_7, crc_adjust);
 891 #ifdef IAVF_RX_PTYPE_OFFLOAD
 892                 /**
 893                  * to get packet types, ptype is located in bit16-25
 894                  * of each 128bits
 895                  */
 896                 const __m512i ptype_mask =
 897                         _mm512_set1_epi16(IAVF_RX_FLEX_DESC_PTYPE_M);
 898                 const __m512i ptypes4_7 =
 899                         _mm512_and_si512(raw_desc4_7, ptype_mask);
 900                 const __m256i ptypes6_7 = _mm512_extracti64x4_epi64(ptypes4_7, 1);
 901                 const __m256i ptypes4_5 = _mm512_extracti64x4_epi64(ptypes4_7, 0);
 902                 const uint16_t ptype7 = _mm256_extract_epi16(ptypes6_7, 9);
 903                 const uint16_t ptype6 = _mm256_extract_epi16(ptypes6_7, 1);
 904                 const uint16_t ptype5 = _mm256_extract_epi16(ptypes4_5, 9);
 905                 const uint16_t ptype4 = _mm256_extract_epi16(ptypes4_5, 1);
 906
 907                 const __m512i ptype4_7 = _mm512_set_epi32
 908                         (0, 0, 0, type_table[ptype7],
 909                          0, 0, 0, type_table[ptype6],
 910                          0, 0, 0, type_table[ptype5],
 911                          0, 0, 0, type_table[ptype4]);
 912                 mb4_7 = _mm512_mask_blend_epi32(0x1111, mb4_7, ptype4_7);
 913 #endif
 914
 915                 /**
 916                  * convert descriptors 0-3 into mbufs, re-arrange fields.
 917                  * Then write into the mbuf.
 918                  */
 919                 __m512i mb0_3 = _mm512_shuffle_epi8(raw_desc0_3, shuf_msk);
 920
 921                 mb0_3 = _mm512_add_epi32(mb0_3, crc_adjust);
 922 #ifdef IAVF_RX_PTYPE_OFFLOAD
 923                 /**
 924                  * to get packet types, ptype is located in bit16-25
 925                  * of each 128bits
 926                  */
 927                 const __m512i ptypes0_3 =
 928                         _mm512_and_si512(raw_desc0_3, ptype_mask);
 929                 const __m256i ptypes2_3 = _mm512_extracti64x4_epi64(ptypes0_3, 1);
 930                 const __m256i ptypes0_1 = _mm512_extracti64x4_epi64(ptypes0_3, 0);
 931                 const uint16_t ptype3 = _mm256_extract_epi16(ptypes2_3, 9);
 932                 const uint16_t ptype2 = _mm256_extract_epi16(ptypes2_3, 1);
 933                 const uint16_t ptype1 = _mm256_extract_epi16(ptypes0_1, 9);
 934                 const uint16_t ptype0 = _mm256_extract_epi16(ptypes0_1, 1);
 935
 936                 const __m512i ptype0_3 = _mm512_set_epi32
 937                         (0, 0, 0, type_table[ptype3],
 938                          0, 0, 0, type_table[ptype2],
 939                          0, 0, 0, type_table[ptype1],
 940                          0, 0, 0, type_table[ptype0]);
 941                 mb0_3 = _mm512_mask_blend_epi32(0x1111, mb0_3, ptype0_3);
 942 #endif
 943
 944                 /**
 945                  * use permute/extract to get status content
 946                  * After the operations, the packets status flags are in the
 947                  * order (hi->lo): [1, 3, 5, 7, 0, 2, 4, 6]
 948                  */
 949                 /* merge the status bits into one register */
 950                 const __m512i status_permute_msk = _mm512_set_epi32
 951                         (0, 0, 0, 0,
 952                          0, 0, 0, 0,
 953                          22, 30, 6, 14,
 954                          18, 26, 2, 10);
 955                 const __m512i raw_status0_7 = _mm512_permutex2var_epi32
 956                         (raw_desc4_7, status_permute_msk, raw_desc0_3);
 957                 __m256i status0_7 = _mm512_extracti64x4_epi64
 958                         (raw_status0_7, 0);
 959
 960                 /* now do flag manipulation */
 961
 962                 /* merge flags */
 963                 __m256i mbuf_flags = _mm256_set1_epi32(0);
 964                 __m256i vlan_flags = _mm256_setzero_si256();
 965
 966                 if (offload) {
 967 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
 968                         /* Status/Error flag masks */
 969                         /**
 970                          * mask everything except Checksum Reports, RSS indication
 971                          * and VLAN indication.
 972                          * bit6:4 for IP/L4 checksum errors.
 973                          * bit12 is for RSS indication.
 974                          * bit13 is for VLAN indication.
 975                          */
 976                         const __m256i flags_mask =
 977                                 _mm256_set1_epi32((7 << 4) | (1 << 12) | (1 << 13));
 978 #endif
 979 #ifdef IAVF_RX_CSUM_OFFLOAD
 980                         /**
 981                          * data to be shuffled by the result of the flags mask shifted by 4
 982                          * bits.  This gives use the l3_l4 flags.
 983                          */
 984                         const __m256i l3_l4_flags_shuf = _mm256_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
 985                                         /* shift right 1 bit to make sure it not exceed 255 */
 986                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 987                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 988                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
 989                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 990                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
 991                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 992                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
 993                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 994                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 995                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 996                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
 997                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
 998                                         /* second 128-bits */
 999                                         0, 0, 0, 0, 0, 0, 0, 0,
1000                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
1001                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
1002                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
1003                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
1004                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
1005                                          RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
1006                                         (RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD | RTE_MBUF_F_RX_L4_CKSUM_GOOD |
1007                                          RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
1008                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
1009                                         (RTE_MBUF_F_RX_L4_CKSUM_BAD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1,
1010                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD) >> 1,
1011                                         (RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_GOOD) >> 1);
1012                         const __m256i cksum_mask =
1013                                 _mm256_set1_epi32(RTE_MBUF_F_RX_IP_CKSUM_GOOD | RTE_MBUF_F_RX_IP_CKSUM_BAD |
1014                                                   RTE_MBUF_F_RX_L4_CKSUM_GOOD | RTE_MBUF_F_RX_L4_CKSUM_BAD |
1015                                                   RTE_MBUF_F_RX_OUTER_IP_CKSUM_BAD);
1016 #endif
1017 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1018                         /**
1019                          * data to be shuffled by result of flag mask, shifted down 12.
1020                          * If RSS(bit12)/VLAN(bit13) are set,
1021                          * shuffle moves appropriate flags in place.
1022                          */
1023                         const __m256i rss_flags_shuf = _mm256_set_epi8
1024                                         (0, 0, 0, 0,
1025                                          0, 0, 0, 0,
1026                                          0, 0, 0, 0,
1027                                          RTE_MBUF_F_RX_RSS_HASH, 0,
1028                                          RTE_MBUF_F_RX_RSS_HASH, 0,
1029                                          /* end up 128-bits */
1030                                          0, 0, 0, 0,
1031                                          0, 0, 0, 0,
1032                                          0, 0, 0, 0,
1033                                          RTE_MBUF_F_RX_RSS_HASH, 0,
1034                                          RTE_MBUF_F_RX_RSS_HASH, 0);
1035
1036                         const __m256i vlan_flags_shuf = _mm256_set_epi8
1037                                         (0, 0, 0, 0,
1038                                          0, 0, 0, 0,
1039                                          0, 0, 0, 0,
1040                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1041                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1042                                          0, 0,
1043                                          /* end up 128-bits */
1044                                          0, 0, 0, 0,
1045                                          0, 0, 0, 0,
1046                                          0, 0, 0, 0,
1047                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1048                                          RTE_MBUF_F_RX_VLAN | RTE_MBUF_F_RX_VLAN_STRIPPED,
1049                                          0, 0);
1050 #endif
1051
1052 #if defined(IAVF_RX_CSUM_OFFLOAD) || defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1053                         /* get only flag/error bits we want */
1054                         const __m256i flag_bits =
1055                                 _mm256_and_si256(status0_7, flags_mask);
1056 #endif
1057 #ifdef IAVF_RX_CSUM_OFFLOAD
1058                         /**
1059                          * l3_l4_error flags, shuffle, then shift to correct adjustment
1060                          * of flags in flags_shuf, and finally mask out extra bits
1061                          */
1062                         __m256i l3_l4_flags = _mm256_shuffle_epi8(l3_l4_flags_shuf,
1063                                         _mm256_srli_epi32(flag_bits, 4));
1064                         l3_l4_flags = _mm256_slli_epi32(l3_l4_flags, 1);
1065                         l3_l4_flags = _mm256_and_si256(l3_l4_flags, cksum_mask);
1066 #endif
1067 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1068                         /* set rss and vlan flags */
1069                         const __m256i rss_vlan_flag_bits =
1070                                 _mm256_srli_epi32(flag_bits, 12);
1071                         const __m256i rss_flags =
1072                                 _mm256_shuffle_epi8(rss_flags_shuf,
1073                                                     rss_vlan_flag_bits);
1074
1075                         if (rxq->rx_flags == IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG1)
1076                                 vlan_flags =
1077                                         _mm256_shuffle_epi8(vlan_flags_shuf,
1078                                                             rss_vlan_flag_bits);
1079
1080                         const __m256i rss_vlan_flags =
1081                                 _mm256_or_si256(rss_flags, vlan_flags);
1082
1083 #endif
1084
1085 #ifdef IAVF_RX_CSUM_OFFLOAD
1086                         mbuf_flags = _mm256_or_si256(mbuf_flags, l3_l4_flags);
1087 #endif
1088 #if defined(IAVF_RX_VLAN_OFFLOAD) || defined(IAVF_RX_RSS_OFFLOAD)
1089                         mbuf_flags = _mm256_or_si256(mbuf_flags, rss_vlan_flags);
1090 #endif
1091                 }
1092
1093 #ifdef IAVF_RX_FDIR_OFFLOAD
1094                 if (rxq->fdir_enabled) {
1095                         const __m512i fdir_permute_mask = _mm512_set_epi32
1096                                 (0, 0, 0, 0,
1097                                  0, 0, 0, 0,
1098                                  7, 15, 23, 31,
1099                                  3, 11, 19, 27);
1100                         __m512i fdir_tmp = _mm512_permutex2var_epi32
1101                                 (raw_desc0_3, fdir_permute_mask, raw_desc4_7);
1102                         const __m256i fdir_id0_7 = _mm512_extracti64x4_epi64
1103                                 (fdir_tmp, 0);
1104                         const __m256i fdir_flags =
1105                                 flex_rxd_to_fdir_flags_vec_avx512(fdir_id0_7);
1106
1107                         /* merge with fdir_flags */
1108                         mbuf_flags = _mm256_or_si256(mbuf_flags, fdir_flags);
1109
1110                         /* write to mbuf: have to use scalar store here */
1111                         rx_pkts[i + 0]->hash.fdir.hi =
1112                                 _mm256_extract_epi32(fdir_id0_7, 3);
1113
1114                         rx_pkts[i + 1]->hash.fdir.hi =
1115                                 _mm256_extract_epi32(fdir_id0_7, 7);
1116
1117                         rx_pkts[i + 2]->hash.fdir.hi =
1118                                 _mm256_extract_epi32(fdir_id0_7, 2);
1119
1120                         rx_pkts[i + 3]->hash.fdir.hi =
1121                                 _mm256_extract_epi32(fdir_id0_7, 6);
1122
1123                         rx_pkts[i + 4]->hash.fdir.hi =
1124                                 _mm256_extract_epi32(fdir_id0_7, 1);
1125
1126                         rx_pkts[i + 5]->hash.fdir.hi =
1127                                 _mm256_extract_epi32(fdir_id0_7, 5);
1128
1129                         rx_pkts[i + 6]->hash.fdir.hi =
1130                                 _mm256_extract_epi32(fdir_id0_7, 0);
1131
1132                         rx_pkts[i + 7]->hash.fdir.hi =
1133                                 _mm256_extract_epi32(fdir_id0_7, 4);
1134                 } /* if() on fdir_enabled */
1135 #endif
1136
1137                 __m256i mb4_5 = _mm512_extracti64x4_epi64(mb4_7, 0);
1138                 __m256i mb6_7 = _mm512_extracti64x4_epi64(mb4_7, 1);
1139                 __m256i mb0_1 = _mm512_extracti64x4_epi64(mb0_3, 0);
1140                 __m256i mb2_3 = _mm512_extracti64x4_epi64(mb0_3, 1);
1141
1142 #ifndef RTE_LIBRTE_IAVF_16BYTE_RX_DESC
1143                 if (offload) {
1144 #ifdef IAVF_RX_RSS_OFFLOAD
1145                         /**
1146                          * needs to load 2nd 16B of each desc for RSS hash parsing,
1147                          * will cause performance drop to get into this context.
1148                          */
1149                         if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1150                             DEV_RX_OFFLOAD_RSS_HASH ||
1151                             rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1152                                 /* load bottom half of every 32B desc */
1153                                 const __m128i raw_desc_bh7 =
1154                                         _mm_load_si128
1155                                                 ((void *)(&rxdp[7].wb.status_error1));
1156                                 rte_compiler_barrier();
1157                                 const __m128i raw_desc_bh6 =
1158                                         _mm_load_si128
1159                                                 ((void *)(&rxdp[6].wb.status_error1));
1160                                 rte_compiler_barrier();
1161                                 const __m128i raw_desc_bh5 =
1162                                         _mm_load_si128
1163                                                 ((void *)(&rxdp[5].wb.status_error1));
1164                                 rte_compiler_barrier();
1165                                 const __m128i raw_desc_bh4 =
1166                                         _mm_load_si128
1167                                                 ((void *)(&rxdp[4].wb.status_error1));
1168                                 rte_compiler_barrier();
1169                                 const __m128i raw_desc_bh3 =
1170                                         _mm_load_si128
1171                                                 ((void *)(&rxdp[3].wb.status_error1));
1172                                 rte_compiler_barrier();
1173                                 const __m128i raw_desc_bh2 =
1174                                         _mm_load_si128
1175                                                 ((void *)(&rxdp[2].wb.status_error1));
1176                                 rte_compiler_barrier();
1177                                 const __m128i raw_desc_bh1 =
1178                                         _mm_load_si128
1179                                                 ((void *)(&rxdp[1].wb.status_error1));
1180                                 rte_compiler_barrier();
1181                                 const __m128i raw_desc_bh0 =
1182                                         _mm_load_si128
1183                                                 ((void *)(&rxdp[0].wb.status_error1));
1184
1185                                 __m256i raw_desc_bh6_7 =
1186                                         _mm256_inserti128_si256
1187                                                 (_mm256_castsi128_si256(raw_desc_bh6),
1188                                                  raw_desc_bh7, 1);
1189                                 __m256i raw_desc_bh4_5 =
1190                                         _mm256_inserti128_si256
1191                                                 (_mm256_castsi128_si256(raw_desc_bh4),
1192                                                  raw_desc_bh5, 1);
1193                                 __m256i raw_desc_bh2_3 =
1194                                         _mm256_inserti128_si256
1195                                                 (_mm256_castsi128_si256(raw_desc_bh2),
1196                                                  raw_desc_bh3, 1);
1197                                 __m256i raw_desc_bh0_1 =
1198                                         _mm256_inserti128_si256
1199                                                 (_mm256_castsi128_si256(raw_desc_bh0),
1200                                                  raw_desc_bh1, 1);
1201
1202                                 if (rxq->vsi->adapter->eth_dev->data->dev_conf.rxmode.offloads &
1203                                                 DEV_RX_OFFLOAD_RSS_HASH) {
1204                                         /**
1205                                          * to shift the 32b RSS hash value to the
1206                                          * highest 32b of each 128b before mask
1207                                          */
1208                                         __m256i rss_hash6_7 =
1209                                                 _mm256_slli_epi64
1210                                                 (raw_desc_bh6_7, 32);
1211                                         __m256i rss_hash4_5 =
1212                                                 _mm256_slli_epi64
1213                                                 (raw_desc_bh4_5, 32);
1214                                         __m256i rss_hash2_3 =
1215                                                 _mm256_slli_epi64
1216                                                 (raw_desc_bh2_3, 32);
1217                                         __m256i rss_hash0_1 =
1218                                                 _mm256_slli_epi64
1219                                                 (raw_desc_bh0_1, 32);
1220
1221                                         const __m256i rss_hash_msk =
1222                                                 _mm256_set_epi32
1223                                                 (0xFFFFFFFF, 0, 0, 0,
1224                                                  0xFFFFFFFF, 0, 0, 0);
1225
1226                                         rss_hash6_7 = _mm256_and_si256
1227                                                 (rss_hash6_7, rss_hash_msk);
1228                                         rss_hash4_5 = _mm256_and_si256
1229                                                 (rss_hash4_5, rss_hash_msk);
1230                                         rss_hash2_3 = _mm256_and_si256
1231                                                 (rss_hash2_3, rss_hash_msk);
1232                                         rss_hash0_1 = _mm256_and_si256
1233                                                 (rss_hash0_1, rss_hash_msk);
1234
1235                                         mb6_7 = _mm256_or_si256
1236                                                 (mb6_7, rss_hash6_7);
1237                                         mb4_5 = _mm256_or_si256
1238                                                 (mb4_5, rss_hash4_5);
1239                                         mb2_3 = _mm256_or_si256
1240                                                 (mb2_3, rss_hash2_3);
1241                                         mb0_1 = _mm256_or_si256
1242                                                 (mb0_1, rss_hash0_1);
1243                                 }
1244
1245                                 if (rxq->rx_flags & IAVF_RX_FLAGS_VLAN_TAG_LOC_L2TAG2_2) {
1246                                         /* merge the status/error-1 bits into one register */
1247                                         const __m256i status1_4_7 =
1248                                                 _mm256_unpacklo_epi32
1249                                                 (raw_desc_bh6_7,
1250                                                  raw_desc_bh4_5);
1251                                         const __m256i status1_0_3 =
1252                                                 _mm256_unpacklo_epi32
1253                                                 (raw_desc_bh2_3,
1254                                                  raw_desc_bh0_1);
1255
1256                                         const __m256i status1_0_7 =
1257                                                 _mm256_unpacklo_epi64
1258                                                 (status1_4_7, status1_0_3);
1259
1260                                         const __m256i l2tag2p_flag_mask =
1261                                                 _mm256_set1_epi32
1262                                                 (1 << IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1263
1264                                         __m256i l2tag2p_flag_bits =
1265                                                 _mm256_and_si256
1266                                                 (status1_0_7,
1267                                                  l2tag2p_flag_mask);
1268
1269                                         l2tag2p_flag_bits =
1270                                                 _mm256_srli_epi32
1271                                                 (l2tag2p_flag_bits,
1272                                                  IAVF_RX_FLEX_DESC_STATUS1_L2TAG2P_S);
1273
1274                                         const __m256i l2tag2_flags_shuf =
1275                                                 _mm256_set_epi8
1276                                                         (0, 0, 0, 0,
1277                                                          0, 0, 0, 0,
1278                                                          0, 0, 0, 0,
1279                                                          0, 0, 0, 0,
1280                                                          /* end up 128-bits */
1281                                                          0, 0, 0, 0,
1282                                                          0, 0, 0, 0,
1283                                                          0, 0, 0, 0,
1284                                                          0, 0,
1285                                                          RTE_MBUF_F_RX_VLAN |
1286                                                          RTE_MBUF_F_RX_VLAN_STRIPPED,
1287                                                          0);
1288
1289                                         vlan_flags =
1290                                                 _mm256_shuffle_epi8
1291                                                         (l2tag2_flags_shuf,
1292                                                          l2tag2p_flag_bits);
1293
1294                                         /* merge with vlan_flags */
1295                                         mbuf_flags = _mm256_or_si256
1296                                                         (mbuf_flags,
1297                                                          vlan_flags);
1298
1299                                         /* L2TAG2_2 */
1300                                         __m256i vlan_tci6_7 =
1301                                                 _mm256_slli_si256
1302                                                         (raw_desc_bh6_7, 4);
1303                                         __m256i vlan_tci4_5 =
1304                                                 _mm256_slli_si256
1305                                                         (raw_desc_bh4_5, 4);
1306                                         __m256i vlan_tci2_3 =
1307                                                 _mm256_slli_si256
1308                                                         (raw_desc_bh2_3, 4);
1309                                         __m256i vlan_tci0_1 =
1310                                                 _mm256_slli_si256
1311                                                         (raw_desc_bh0_1, 4);
1312
1313                                         const __m256i vlan_tci_msk =
1314                                                 _mm256_set_epi32
1315                                                 (0, 0xFFFF0000, 0, 0,
1316                                                  0, 0xFFFF0000, 0, 0);
1317
1318                                         vlan_tci6_7 = _mm256_and_si256
1319                                                         (vlan_tci6_7,
1320                                                          vlan_tci_msk);
1321                                         vlan_tci4_5 = _mm256_and_si256
1322                                                         (vlan_tci4_5,
1323                                                          vlan_tci_msk);
1324                                         vlan_tci2_3 = _mm256_and_si256
1325                                                         (vlan_tci2_3,
1326                                                          vlan_tci_msk);
1327                                         vlan_tci0_1 = _mm256_and_si256
1328                                                         (vlan_tci0_1,
1329                                                          vlan_tci_msk);
1330
1331                                         mb6_7 = _mm256_or_si256
1332                                                         (mb6_7, vlan_tci6_7);
1333                                         mb4_5 = _mm256_or_si256
1334                                                         (mb4_5, vlan_tci4_5);
1335                                         mb2_3 = _mm256_or_si256
1336                                                         (mb2_3, vlan_tci2_3);
1337                                         mb0_1 = _mm256_or_si256
1338                                                         (mb0_1, vlan_tci0_1);
1339                                 }
1340                         } /* if() on RSS hash parsing */
1341 #endif
1342                 }
1343 #endif
1344
1345                 /**
1346                  * At this point, we have the 8 sets of flags in the low 16-bits
1347                  * of each 32-bit value in vlan0.
1348                  * We want to extract these, and merge them with the mbuf init
1349                  * data so we can do a single write to the mbuf to set the flags
1350                  * and all the other initialization fields. Extracting the
1351                  * appropriate flags means that we have to do a shift and blend
1352                  * for each mbuf before we do the write. However, we can also
1353                  * add in the previously computed rx_descriptor fields to
1354                  * make a single 256-bit write per mbuf
1355                  */
1356                 /* check the structure matches expectations */
1357                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
1358                                  offsetof(struct rte_mbuf, rearm_data) + 8);
1359                 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
1360                                  RTE_ALIGN(offsetof(struct rte_mbuf,
1361                                                     rearm_data),
1362                                                     16));
1363                 /* build up data and do writes */
1364                 __m256i rearm0, rearm1, rearm2, rearm3, rearm4, rearm5,
1365                         rearm6, rearm7;
1366                 rearm6 = _mm256_blend_epi32(mbuf_init,
1367                                             _mm256_slli_si256(mbuf_flags, 8),
1368                                             0x04);
1369                 rearm4 = _mm256_blend_epi32(mbuf_init,
1370                                             _mm256_slli_si256(mbuf_flags, 4),
1371                                             0x04);
1372                 rearm2 = _mm256_blend_epi32(mbuf_init, mbuf_flags, 0x04);
1373                 rearm0 = _mm256_blend_epi32(mbuf_init,
1374                                             _mm256_srli_si256(mbuf_flags, 4),
1375                                             0x04);
1376                 /* permute to add in the rx_descriptor e.g. rss fields */
1377                 rearm6 = _mm256_permute2f128_si256(rearm6, mb6_7, 0x20);
1378                 rearm4 = _mm256_permute2f128_si256(rearm4, mb4_5, 0x20);
1379                 rearm2 = _mm256_permute2f128_si256(rearm2, mb2_3, 0x20);
1380                 rearm0 = _mm256_permute2f128_si256(rearm0, mb0_1, 0x20);
1381                 /* write to mbuf */
1382                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 6]->rearm_data,
1383                                     rearm6);
1384                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 4]->rearm_data,
1385                                     rearm4);
1386                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 2]->rearm_data,
1387                                     rearm2);
1388                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 0]->rearm_data,
1389                                     rearm0);
1390
1391                 /* repeat for the odd mbufs */
1392                 const __m256i odd_flags =
1393                         _mm256_castsi128_si256
1394                                 (_mm256_extracti128_si256(mbuf_flags, 1));
1395                 rearm7 = _mm256_blend_epi32(mbuf_init,
1396                                             _mm256_slli_si256(odd_flags, 8),
1397                                             0x04);
1398                 rearm5 = _mm256_blend_epi32(mbuf_init,
1399                                             _mm256_slli_si256(odd_flags, 4),
1400                                             0x04);
1401                 rearm3 = _mm256_blend_epi32(mbuf_init, odd_flags, 0x04);
1402                 rearm1 = _mm256_blend_epi32(mbuf_init,
1403                                             _mm256_srli_si256(odd_flags, 4),
1404                                             0x04);
1405                 /* since odd mbufs are already in hi 128-bits use blend */
1406                 rearm7 = _mm256_blend_epi32(rearm7, mb6_7, 0xF0);
1407                 rearm5 = _mm256_blend_epi32(rearm5, mb4_5, 0xF0);
1408                 rearm3 = _mm256_blend_epi32(rearm3, mb2_3, 0xF0);
1409                 rearm1 = _mm256_blend_epi32(rearm1, mb0_1, 0xF0);
1410                 /* again write to mbufs */
1411                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 7]->rearm_data,
1412                                     rearm7);
1413                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 5]->rearm_data,
1414                                     rearm5);
1415                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 3]->rearm_data,
1416                                     rearm3);
1417                 _mm256_storeu_si256((__m256i *)&rx_pkts[i + 1]->rearm_data,
1418                                     rearm1);
1419
1420                 /* extract and record EOP bit */
1421                 if (split_packet) {
1422                         const __m128i eop_mask =
1423                                 _mm_set1_epi16(1 <<
1424                                                IAVF_RX_FLEX_DESC_STATUS0_EOF_S);
1425                         const __m256i eop_bits256 = _mm256_and_si256(status0_7,
1426                                                                      eop_check);
1427                         /* pack status bits into a single 128-bit register */
1428                         const __m128i eop_bits =
1429                                 _mm_packus_epi32
1430                                         (_mm256_castsi256_si128(eop_bits256),
1431                                          _mm256_extractf128_si256(eop_bits256,
1432                                                                   1));
1433                         /**
1434                          * flip bits, and mask out the EOP bit, which is now
1435                          * a split-packet bit i.e. !EOP, rather than EOP one.
1436                          */
1437                         __m128i split_bits = _mm_andnot_si128(eop_bits,
1438                                                               eop_mask);
1439                         /**
1440                          * eop bits are out of order, so we need to shuffle them
1441                          * back into order again. In doing so, only use low 8
1442                          * bits, which acts like another pack instruction
1443                          * The original order is (hi->lo): 1,3,5,7,0,2,4,6
1444                          * [Since we use epi8, the 16-bit positions are
1445                          * multiplied by 2 in the eop_shuffle value.]
1446                          */
1447                         __m128i eop_shuffle =
1448                                 _mm_set_epi8(/* zero hi 64b */
1449                                              0xFF, 0xFF, 0xFF, 0xFF,
1450                                              0xFF, 0xFF, 0xFF, 0xFF,
1451                                              /* move values to lo 64b */
1452                                              8, 0, 10, 2,
1453                                              12, 4, 14, 6);
1454                         split_bits = _mm_shuffle_epi8(split_bits, eop_shuffle);
1455                         *(uint64_t *)split_packet =
1456                                 _mm_cvtsi128_si64(split_bits);
1457                         split_packet += IAVF_DESCS_PER_LOOP_AVX;
1458                 }
1459
1460                 /* perform dd_check */
1461                 status0_7 = _mm256_and_si256(status0_7, dd_check);
1462                 status0_7 = _mm256_packs_epi32(status0_7,
1463                                                _mm256_setzero_si256());
1464
1465                 uint64_t burst = __builtin_popcountll
1466                                         (_mm_cvtsi128_si64
1467                                                 (_mm256_extracti128_si256
1468                                                         (status0_7, 1)));
1469                 burst += __builtin_popcountll
1470                                 (_mm_cvtsi128_si64
1471                                         (_mm256_castsi256_si128(status0_7)));
1472                 received += burst;
1473                 if (burst != IAVF_DESCS_PER_LOOP_AVX)
1474                         break;
1475         }
1476
1477         /* update tail pointers */
1478         rxq->rx_tail += received;
1479         rxq->rx_tail &= (rxq->nb_rx_desc - 1);
1480         if ((rxq->rx_tail & 1) == 1 && received > 1) { /* keep aligned */
1481                 rxq->rx_tail--;
1482                 received--;
1483         }
1484         rxq->rxrearm_nb += received;
1485         return received;
1486 }
1487
1488 /**
1489  * Notice:
1490  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1491  */
1492 uint16_t
1493 iavf_recv_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1494                           uint16_t nb_pkts)
1495 {
1496         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts, nb_pkts,
1497                                               NULL, false);
1498 }
1499
1500 /**
1501  * Notice:
1502  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1503  */
1504 uint16_t
1505 iavf_recv_pkts_vec_avx512_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
1506                                    uint16_t nb_pkts)
1507 {
1508         return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue, rx_pkts,
1509                                                        nb_pkts, NULL, false);
1510 }
1511
1512 /**
1513  * vPMD receive routine that reassembles single burst of 32 scattered packets
1514  * Notice:
1515  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1516  */
1517 static __rte_always_inline uint16_t
1518 iavf_recv_scattered_burst_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1519                                      uint16_t nb_pkts, bool offload)
1520 {
1521         struct iavf_rx_queue *rxq = rx_queue;
1522         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1523
1524         /* get some new buffers */
1525         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512(rxq, rx_pkts, nb_pkts,
1526                                                           split_flags, offload);
1527         if (nb_bufs == 0)
1528                 return 0;
1529
1530         /* happy day case, full burst + no packets to be joined */
1531         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1532
1533         if (!rxq->pkt_first_seg &&
1534             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1535             split_fl64[2] == 0 && split_fl64[3] == 0)
1536                 return nb_bufs;
1537
1538         /* reassemble any packets that need reassembly*/
1539         unsigned int i = 0;
1540
1541         if (!rxq->pkt_first_seg) {
1542                 /* find the first split flag, and only reassemble then*/
1543                 while (i < nb_bufs && !split_flags[i])
1544                         i++;
1545                 if (i == nb_bufs)
1546                         return nb_bufs;
1547                 rxq->pkt_first_seg = rx_pkts[i];
1548         }
1549         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1550                                       &split_flags[i]);
1551 }
1552
1553 /**
1554  * vPMD receive routine that reassembles scattered packets.
1555  * Main receive routine that can handle arbitrary burst sizes
1556  * Notice:
1557  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1558  */
1559 static __rte_always_inline uint16_t
1560 iavf_recv_scattered_pkts_vec_avx512_cmn(void *rx_queue, struct rte_mbuf **rx_pkts,
1561                                         uint16_t nb_pkts, bool offload)
1562 {
1563         uint16_t retval = 0;
1564
1565         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1566                 uint16_t burst = iavf_recv_scattered_burst_vec_avx512(rx_queue,
1567                                 rx_pkts + retval, IAVF_VPMD_RX_MAX_BURST, offload);
1568                 retval += burst;
1569                 nb_pkts -= burst;
1570                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1571                         return retval;
1572         }
1573         return retval + iavf_recv_scattered_burst_vec_avx512(rx_queue,
1574                                 rx_pkts + retval, nb_pkts, offload);
1575 }
1576
1577 uint16_t
1578 iavf_recv_scattered_pkts_vec_avx512(void *rx_queue, struct rte_mbuf **rx_pkts,
1579                                     uint16_t nb_pkts)
1580 {
1581         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1582                                                        nb_pkts, false);
1583 }
1584
1585 /**
1586  * vPMD receive routine that reassembles single burst of
1587  * 32 scattered packets for flex RxD
1588  * Notice:
1589  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1590  */
1591 static __rte_always_inline uint16_t
1592 iavf_recv_scattered_burst_vec_avx512_flex_rxd(void *rx_queue,
1593                                               struct rte_mbuf **rx_pkts,
1594                                               uint16_t nb_pkts,
1595                                               bool offload)
1596 {
1597         struct iavf_rx_queue *rxq = rx_queue;
1598         uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
1599
1600         /* get some new buffers */
1601         uint16_t nb_bufs = _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rxq,
1602                                         rx_pkts, nb_pkts, split_flags, offload);
1603         if (nb_bufs == 0)
1604                 return 0;
1605
1606         /* happy day case, full burst + no packets to be joined */
1607         const uint64_t *split_fl64 = (uint64_t *)split_flags;
1608
1609         if (!rxq->pkt_first_seg &&
1610             split_fl64[0] == 0 && split_fl64[1] == 0 &&
1611             split_fl64[2] == 0 && split_fl64[3] == 0)
1612                 return nb_bufs;
1613
1614         /* reassemble any packets that need reassembly*/
1615         unsigned int i = 0;
1616
1617         if (!rxq->pkt_first_seg) {
1618                 /* find the first split flag, and only reassemble then*/
1619                 while (i < nb_bufs && !split_flags[i])
1620                         i++;
1621                 if (i == nb_bufs)
1622                         return nb_bufs;
1623                 rxq->pkt_first_seg = rx_pkts[i];
1624         }
1625         return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
1626                                       &split_flags[i]);
1627 }
1628
1629 /**
1630  * vPMD receive routine that reassembles scattered packets for flex RxD.
1631  * Main receive routine that can handle arbitrary burst sizes
1632  * Notice:
1633  * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
1634  */
1635 static __rte_always_inline uint16_t
1636 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(void *rx_queue,
1637                                                  struct rte_mbuf **rx_pkts,
1638                                                  uint16_t nb_pkts,
1639                                                  bool offload)
1640 {
1641         uint16_t retval = 0;
1642
1643         while (nb_pkts > IAVF_VPMD_RX_MAX_BURST) {
1644                 uint16_t burst =
1645                         iavf_recv_scattered_burst_vec_avx512_flex_rxd
1646                                 (rx_queue, rx_pkts + retval,
1647                                  IAVF_VPMD_RX_MAX_BURST, offload);
1648                 retval += burst;
1649                 nb_pkts -= burst;
1650                 if (burst < IAVF_VPMD_RX_MAX_BURST)
1651                         return retval;
1652         }
1653         return retval + iavf_recv_scattered_burst_vec_avx512_flex_rxd(rx_queue,
1654                                 rx_pkts + retval, nb_pkts, offload);
1655 }
1656
1657 uint16_t
1658 iavf_recv_scattered_pkts_vec_avx512_flex_rxd(void *rx_queue,
1659                                              struct rte_mbuf **rx_pkts,
1660                                              uint16_t nb_pkts)
1661 {
1662         return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1663                                                                 rx_pkts,
1664                                                                 nb_pkts,
1665                                                                 false);
1666 }
1667
1668 uint16_t
1669 iavf_recv_pkts_vec_avx512_offload(void *rx_queue, struct rte_mbuf **rx_pkts,
1670                                   uint16_t nb_pkts)
1671 {
1672         return _iavf_recv_raw_pkts_vec_avx512(rx_queue, rx_pkts,
1673                                               nb_pkts, NULL, true);
1674 }
1675
1676 uint16_t
1677 iavf_recv_scattered_pkts_vec_avx512_offload(void *rx_queue,
1678                                             struct rte_mbuf **rx_pkts,
1679                                             uint16_t nb_pkts)
1680 {
1681         return iavf_recv_scattered_pkts_vec_avx512_cmn(rx_queue, rx_pkts,
1682                                                        nb_pkts, true);
1683 }
1684
1685 uint16_t
1686 iavf_recv_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1687                                            struct rte_mbuf **rx_pkts,
1688                                            uint16_t nb_pkts)
1689 {
1690         return _iavf_recv_raw_pkts_vec_avx512_flex_rxd(rx_queue,
1691                                                        rx_pkts,
1692                                                        nb_pkts,
1693                                                        NULL,
1694                                                        true);
1695 }
1696
1697 uint16_t
1698 iavf_recv_scattered_pkts_vec_avx512_flex_rxd_offload(void *rx_queue,
1699                                                      struct rte_mbuf **rx_pkts,
1700                                                      uint16_t nb_pkts)
1701 {
1702         return iavf_recv_scattered_pkts_vec_avx512_flex_rxd_cmn(rx_queue,
1703                                                                 rx_pkts,
1704                                                                 nb_pkts,
1705                                                                 true);
1706 }
1707
1708 static __rte_always_inline int
1709 iavf_tx_free_bufs_avx512(struct iavf_tx_queue *txq)
1710 {
1711         struct iavf_tx_vec_entry *txep;
1712         uint32_t n;
1713         uint32_t i;
1714         int nb_free = 0;
1715         struct rte_mbuf *m, *free[IAVF_VPMD_TX_MAX_FREE_BUF];
1716
1717         /* check DD bits on threshold descriptor */
1718         if ((txq->tx_ring[txq->next_dd].cmd_type_offset_bsz &
1719              rte_cpu_to_le_64(IAVF_TXD_QW1_DTYPE_MASK)) !=
1720             rte_cpu_to_le_64(IAVF_TX_DESC_DTYPE_DESC_DONE))
1721                 return 0;
1722
1723         n = txq->rs_thresh;
1724
1725          /* first buffer to free from S/W ring is at index
1726           * tx_next_dd - (tx_rs_thresh-1)
1727           */
1728         txep = (void *)txq->sw_ring;
1729         txep += txq->next_dd - (n - 1);
1730
1731         if (txq->offloads & DEV_TX_OFFLOAD_MBUF_FAST_FREE && (n & 31) == 0) {
1732                 struct rte_mempool *mp = txep[0].mbuf->pool;
1733                 struct rte_mempool_cache *cache = rte_mempool_default_cache(mp,
1734                                                                 rte_lcore_id());
1735                 void **cache_objs;
1736
1737                 if (!cache || cache->len == 0)
1738                         goto normal;
1739
1740                 cache_objs = &cache->objs[cache->len];
1741
1742                 if (n > RTE_MEMPOOL_CACHE_MAX_SIZE) {
1743                         rte_mempool_ops_enqueue_bulk(mp, (void *)txep, n);
1744                         goto done;
1745                 }
1746
1747                 /* The cache follows the following algorithm
1748                  *   1. Add the objects to the cache
1749                  *   2. Anything greater than the cache min value (if it crosses the
1750                  *   cache flush threshold) is flushed to the ring.
1751                  */
1752                 /* Add elements back into the cache */
1753                 uint32_t copied = 0;
1754                 /* n is multiple of 32 */
1755                 while (copied < n) {
1756                         const __m512i a = _mm512_loadu_si512(&txep[copied]);
1757                         const __m512i b = _mm512_loadu_si512(&txep[copied + 8]);
1758                         const __m512i c = _mm512_loadu_si512(&txep[copied + 16]);
1759                         const __m512i d = _mm512_loadu_si512(&txep[copied + 24]);
1760
1761                         _mm512_storeu_si512(&cache_objs[copied], a);
1762                         _mm512_storeu_si512(&cache_objs[copied + 8], b);
1763                         _mm512_storeu_si512(&cache_objs[copied + 16], c);
1764                         _mm512_storeu_si512(&cache_objs[copied + 24], d);
1765                         copied += 32;
1766                 }
1767                 cache->len += n;
1768
1769                 if (cache->len >= cache->flushthresh) {
1770                         rte_mempool_ops_enqueue_bulk(mp,
1771                                                      &cache->objs[cache->size],
1772                                                      cache->len - cache->size);
1773                         cache->len = cache->size;
1774                 }
1775                 goto done;
1776         }
1777
1778 normal:
1779         m = rte_pktmbuf_prefree_seg(txep[0].mbuf);
1780         if (likely(m)) {
1781                 free[0] = m;
1782                 nb_free = 1;
1783                 for (i = 1; i < n; i++) {
1784                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1785                         if (likely(m)) {
1786                                 if (likely(m->pool == free[0]->pool)) {
1787                                         free[nb_free++] = m;
1788                                 } else {
1789                                         rte_mempool_put_bulk(free[0]->pool,
1790                                                              (void *)free,
1791                                                              nb_free);
1792                                         free[0] = m;
1793                                         nb_free = 1;
1794                                 }
1795                         }
1796                 }
1797                 rte_mempool_put_bulk(free[0]->pool, (void **)free, nb_free);
1798         } else {
1799                 for (i = 1; i < n; i++) {
1800                         m = rte_pktmbuf_prefree_seg(txep[i].mbuf);
1801                         if (m)
1802                                 rte_mempool_put(m->pool, m);
1803                 }
1804         }
1805
1806 done:
1807         /* buffers were freed, update counters */
1808         txq->nb_free = (uint16_t)(txq->nb_free + txq->rs_thresh);
1809         txq->next_dd = (uint16_t)(txq->next_dd + txq->rs_thresh);
1810         if (txq->next_dd >= txq->nb_tx_desc)
1811                 txq->next_dd = (uint16_t)(txq->rs_thresh - 1);
1812
1813         return txq->rs_thresh;
1814 }
1815
1816 static __rte_always_inline void
1817 tx_backlog_entry_avx512(struct iavf_tx_vec_entry *txep,
1818                         struct rte_mbuf **tx_pkts, uint16_t nb_pkts)
1819 {
1820         int i;
1821
1822         for (i = 0; i < (int)nb_pkts; ++i)
1823                 txep[i].mbuf = tx_pkts[i];
1824 }
1825
1826 static __rte_always_inline void
1827 iavf_vtx1(volatile struct iavf_tx_desc *txdp,
1828           struct rte_mbuf *pkt, uint64_t flags, bool offload)
1829 {
1830         uint64_t high_qw =
1831                 (IAVF_TX_DESC_DTYPE_DATA |
1832                  ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT) |
1833                  ((uint64_t)pkt->data_len << IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
1834         if (offload)
1835                 iavf_txd_enable_offload(pkt, &high_qw);
1836
1837         __m128i descriptor = _mm_set_epi64x(high_qw,
1838                                             pkt->buf_iova + pkt->data_off);
1839         _mm_storeu_si128((__m128i *)txdp, descriptor);
1840 }
1841
1842 #define IAVF_TX_LEN_MASK 0xAA
1843 #define IAVF_TX_OFF_MASK 0x55
1844 static __rte_always_inline void
1845 iavf_vtx(volatile struct iavf_tx_desc *txdp,
1846          struct rte_mbuf **pkt, uint16_t nb_pkts,  uint64_t flags,
1847          bool offload)
1848 {
1849         const uint64_t hi_qw_tmpl = (IAVF_TX_DESC_DTYPE_DATA |
1850                         ((uint64_t)flags  << IAVF_TXD_QW1_CMD_SHIFT));
1851
1852         /* if unaligned on 32-bit boundary, do one to align */
1853         if (((uintptr_t)txdp & 0x1F) != 0 && nb_pkts != 0) {
1854                 iavf_vtx1(txdp, *pkt, flags, offload);
1855                 nb_pkts--, txdp++, pkt++;
1856         }
1857
1858         /* do 4 at a time while possible, in bursts */
1859         for (; nb_pkts > 3; txdp += 4, pkt += 4, nb_pkts -= 4) {
1860                 uint64_t hi_qw3 =
1861                         hi_qw_tmpl |
1862                         ((uint64_t)pkt[3]->data_len <<
1863                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1864                 if (offload)
1865                         iavf_txd_enable_offload(pkt[3], &hi_qw3);
1866                 uint64_t hi_qw2 =
1867                         hi_qw_tmpl |
1868                         ((uint64_t)pkt[2]->data_len <<
1869                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1870                 if (offload)
1871                         iavf_txd_enable_offload(pkt[2], &hi_qw2);
1872                 uint64_t hi_qw1 =
1873                         hi_qw_tmpl |
1874                         ((uint64_t)pkt[1]->data_len <<
1875                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1876                 if (offload)
1877                         iavf_txd_enable_offload(pkt[1], &hi_qw1);
1878                 uint64_t hi_qw0 =
1879                         hi_qw_tmpl |
1880                         ((uint64_t)pkt[0]->data_len <<
1881                          IAVF_TXD_QW1_TX_BUF_SZ_SHIFT);
1882                 if (offload)
1883                         iavf_txd_enable_offload(pkt[0], &hi_qw0);
1884
1885                 __m512i desc0_3 =
1886                         _mm512_set_epi64
1887                                 (hi_qw3,
1888                                  pkt[3]->buf_iova + pkt[3]->data_off,
1889                                  hi_qw2,
1890                                  pkt[2]->buf_iova + pkt[2]->data_off,
1891                                  hi_qw1,
1892                                  pkt[1]->buf_iova + pkt[1]->data_off,
1893                                  hi_qw0,
1894                                  pkt[0]->buf_iova + pkt[0]->data_off);
1895                 _mm512_storeu_si512((void *)txdp, desc0_3);
1896         }
1897
1898         /* do any last ones */
1899         while (nb_pkts) {
1900                 iavf_vtx1(txdp, *pkt, flags, offload);
1901                 txdp++, pkt++, nb_pkts--;
1902         }
1903 }
1904
1905 static __rte_always_inline uint16_t
1906 iavf_xmit_fixed_burst_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1907                                  uint16_t nb_pkts, bool offload)
1908 {
1909         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1910         volatile struct iavf_tx_desc *txdp;
1911         struct iavf_tx_vec_entry *txep;
1912         uint16_t n, nb_commit, tx_id;
1913         /* bit2 is reserved and must be set to 1 according to Spec */
1914         uint64_t flags = IAVF_TX_DESC_CMD_EOP | IAVF_TX_DESC_CMD_ICRC;
1915         uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1916
1917         /* cross rx_thresh boundary is not allowed */
1918         nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
1919
1920         if (txq->nb_free < txq->free_thresh)
1921                 iavf_tx_free_bufs_avx512(txq);
1922
1923         nb_commit = nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1924         if (unlikely(nb_pkts == 0))
1925                 return 0;
1926
1927         tx_id = txq->tx_tail;
1928         txdp = &txq->tx_ring[tx_id];
1929         txep = (void *)txq->sw_ring;
1930         txep += tx_id;
1931
1932         txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1933
1934         n = (uint16_t)(txq->nb_tx_desc - tx_id);
1935         if (nb_commit >= n) {
1936                 tx_backlog_entry_avx512(txep, tx_pkts, n);
1937
1938                 iavf_vtx(txdp, tx_pkts, n - 1, flags, offload);
1939                 tx_pkts += (n - 1);
1940                 txdp += (n - 1);
1941
1942                 iavf_vtx1(txdp, *tx_pkts++, rs, offload);
1943
1944                 nb_commit = (uint16_t)(nb_commit - n);
1945
1946                 tx_id = 0;
1947                 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1948
1949                 /* avoid reach the end of ring */
1950                 txdp = &txq->tx_ring[tx_id];
1951                 txep = (void *)txq->sw_ring;
1952                 txep += tx_id;
1953         }
1954
1955         tx_backlog_entry_avx512(txep, tx_pkts, nb_commit);
1956
1957         iavf_vtx(txdp, tx_pkts, nb_commit, flags, offload);
1958
1959         tx_id = (uint16_t)(tx_id + nb_commit);
1960         if (tx_id > txq->next_rs) {
1961                 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1962                         rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1963                                          IAVF_TXD_QW1_CMD_SHIFT);
1964                 txq->next_rs =
1965                         (uint16_t)(txq->next_rs + txq->rs_thresh);
1966         }
1967
1968         txq->tx_tail = tx_id;
1969
1970         IAVF_PCI_REG_WC_WRITE(txq->qtx_tail, txq->tx_tail);
1971
1972         return nb_pkts;
1973 }
1974
1975 static __rte_always_inline uint16_t
1976 iavf_xmit_pkts_vec_avx512_cmn(void *tx_queue, struct rte_mbuf **tx_pkts,
1977                               uint16_t nb_pkts, bool offload)
1978 {
1979         uint16_t nb_tx = 0;
1980         struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1981
1982         while (nb_pkts) {
1983                 uint16_t ret, num;
1984
1985                 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1986                 ret = iavf_xmit_fixed_burst_vec_avx512(tx_queue, &tx_pkts[nb_tx],
1987                                                        num, offload);
1988                 nb_tx += ret;
1989                 nb_pkts -= ret;
1990                 if (ret < num)
1991                         break;
1992         }
1993
1994         return nb_tx;
1995 }
1996
1997 uint16_t
1998 iavf_xmit_pkts_vec_avx512(void *tx_queue, struct rte_mbuf **tx_pkts,
1999                           uint16_t nb_pkts)
2000 {
2001         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, false);
2002 }
2003
2004 static inline void
2005 iavf_tx_queue_release_mbufs_avx512(struct iavf_tx_queue *txq)
2006 {
2007         unsigned int i;
2008         const uint16_t max_desc = (uint16_t)(txq->nb_tx_desc - 1);
2009         struct iavf_tx_vec_entry *swr = (void *)txq->sw_ring;
2010
2011         if (!txq->sw_ring || txq->nb_free == max_desc)
2012                 return;
2013
2014         i = txq->next_dd - txq->rs_thresh + 1;
2015         if (txq->tx_tail < i) {
2016                 for (; i < txq->nb_tx_desc; i++) {
2017                         rte_pktmbuf_free_seg(swr[i].mbuf);
2018                         swr[i].mbuf = NULL;
2019                 }
2020                 i = 0;
2021         }
2022 }
2023
2024 static const struct iavf_txq_ops avx512_vec_txq_ops = {
2025         .release_mbufs = iavf_tx_queue_release_mbufs_avx512,
2026 };
2027
2028 int __rte_cold
2029 iavf_txq_vec_setup_avx512(struct iavf_tx_queue *txq)
2030 {
2031         txq->ops = &avx512_vec_txq_ops;
2032         return 0;
2033 }
2034
2035 uint16_t
2036 iavf_xmit_pkts_vec_avx512_offload(void *tx_queue, struct rte_mbuf **tx_pkts,
2037                                   uint16_t nb_pkts)
2038 {
2039         return iavf_xmit_pkts_vec_avx512_cmn(tx_queue, tx_pkts, nb_pkts, true);
2040 }