1 /* SPDX-License-Identifier: BSD-3-Clause
2 * Copyright(c) 2017 Intel Corporation
6 #include <rte_ethdev_driver.h>
7 #include <rte_malloc.h>
10 #include "iavf_rxtx.h"
11 #include "iavf_rxtx_vec_common.h"
13 #include <tmmintrin.h>
15 #ifndef __INTEL_COMPILER
16 #pragma GCC diagnostic ignored "-Wcast-qual"
20 iavf_rxq_rearm(struct iavf_rx_queue *rxq)
25 volatile union iavf_rx_desc *rxdp;
26 struct rte_mbuf **rxp = &rxq->sw_ring[rxq->rxrearm_start];
27 struct rte_mbuf *mb0, *mb1;
28 __m128i hdr_room = _mm_set_epi64x(RTE_PKTMBUF_HEADROOM,
29 RTE_PKTMBUF_HEADROOM);
30 __m128i dma_addr0, dma_addr1;
32 rxdp = rxq->rx_ring + rxq->rxrearm_start;
34 /* Pull 'n' more MBUFs into the software ring */
35 if (rte_mempool_get_bulk(rxq->mp, (void *)rxp,
36 rxq->rx_free_thresh) < 0) {
37 if (rxq->rxrearm_nb + rxq->rx_free_thresh >= rxq->nb_rx_desc) {
38 dma_addr0 = _mm_setzero_si128();
39 for (i = 0; i < IAVF_VPMD_DESCS_PER_LOOP; i++) {
40 rxp[i] = &rxq->fake_mbuf;
41 _mm_store_si128((__m128i *)&rxdp[i].read,
45 rte_eth_devices[rxq->port_id].data->rx_mbuf_alloc_failed +=
50 /* Initialize the mbufs in vector, process 2 mbufs in one loop */
51 for (i = 0; i < rxq->rx_free_thresh; i += 2, rxp += 2) {
52 __m128i vaddr0, vaddr1;
57 /* load buf_addr(lo 64bit) and buf_iova(hi 64bit) */
58 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, buf_iova) !=
59 offsetof(struct rte_mbuf, buf_addr) + 8);
60 vaddr0 = _mm_loadu_si128((__m128i *)&mb0->buf_addr);
61 vaddr1 = _mm_loadu_si128((__m128i *)&mb1->buf_addr);
63 /* convert pa to dma_addr hdr/data */
64 dma_addr0 = _mm_unpackhi_epi64(vaddr0, vaddr0);
65 dma_addr1 = _mm_unpackhi_epi64(vaddr1, vaddr1);
67 /* add headroom to pa values */
68 dma_addr0 = _mm_add_epi64(dma_addr0, hdr_room);
69 dma_addr1 = _mm_add_epi64(dma_addr1, hdr_room);
71 /* flush desc with pa dma_addr */
72 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr0);
73 _mm_store_si128((__m128i *)&rxdp++->read, dma_addr1);
76 rxq->rxrearm_start += rxq->rx_free_thresh;
77 if (rxq->rxrearm_start >= rxq->nb_rx_desc)
78 rxq->rxrearm_start = 0;
80 rxq->rxrearm_nb -= rxq->rx_free_thresh;
82 rx_id = (uint16_t)((rxq->rxrearm_start == 0) ?
83 (rxq->nb_rx_desc - 1) : (rxq->rxrearm_start - 1));
85 PMD_RX_LOG(DEBUG, "port_id=%u queue_id=%u rx_tail=%u "
86 "rearm_start=%u rearm_nb=%u",
87 rxq->port_id, rxq->queue_id,
88 rx_id, rxq->rxrearm_start, rxq->rxrearm_nb);
90 /* Update the tail pointer on the NIC */
91 IAVF_PCI_REG_WRITE(rxq->qrx_tail, rx_id);
95 desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
96 struct rte_mbuf **rx_pkts)
98 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
99 __m128i rearm0, rearm1, rearm2, rearm3;
101 __m128i vlan0, vlan1, rss, l3_l4e;
103 /* mask everything except RSS, flow director and VLAN flags
104 * bit2 is for VLAN tag, bit11 for flow director indication
105 * bit13:12 for RSS indication.
107 const __m128i rss_vlan_msk = _mm_set_epi32(
108 0x1c03804, 0x1c03804, 0x1c03804, 0x1c03804);
110 const __m128i cksum_mask = _mm_set_epi32(
111 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
112 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
113 PKT_RX_EIP_CKSUM_BAD,
114 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
115 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
116 PKT_RX_EIP_CKSUM_BAD,
117 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
118 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
119 PKT_RX_EIP_CKSUM_BAD,
120 PKT_RX_IP_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD |
121 PKT_RX_L4_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD |
122 PKT_RX_EIP_CKSUM_BAD);
124 /* map rss and vlan type to rss hash and vlan flag */
125 const __m128i vlan_flags = _mm_set_epi8(0, 0, 0, 0,
127 0, 0, 0, PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
130 const __m128i rss_flags = _mm_set_epi8(0, 0, 0, 0,
132 PKT_RX_RSS_HASH | PKT_RX_FDIR, PKT_RX_RSS_HASH, 0, 0,
133 0, 0, PKT_RX_FDIR, 0);
135 const __m128i l3_l4e_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
136 /* shift right 1 bit to make sure it not exceed 255 */
137 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
138 PKT_RX_IP_CKSUM_BAD) >> 1,
139 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD |
140 PKT_RX_L4_CKSUM_BAD) >> 1,
141 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
142 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_EIP_CKSUM_BAD) >> 1,
143 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
144 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_BAD) >> 1,
145 PKT_RX_IP_CKSUM_BAD >> 1,
146 (PKT_RX_IP_CKSUM_GOOD | PKT_RX_L4_CKSUM_GOOD) >> 1);
148 vlan0 = _mm_unpackhi_epi32(descs[0], descs[1]);
149 vlan1 = _mm_unpackhi_epi32(descs[2], descs[3]);
150 vlan0 = _mm_unpacklo_epi64(vlan0, vlan1);
152 vlan1 = _mm_and_si128(vlan0, rss_vlan_msk);
153 vlan0 = _mm_shuffle_epi8(vlan_flags, vlan1);
155 rss = _mm_srli_epi32(vlan1, 11);
156 rss = _mm_shuffle_epi8(rss_flags, rss);
158 l3_l4e = _mm_srli_epi32(vlan1, 22);
159 l3_l4e = _mm_shuffle_epi8(l3_l4e_flags, l3_l4e);
160 /* then we shift left 1 bit */
161 l3_l4e = _mm_slli_epi32(l3_l4e, 1);
162 /* we need to mask out the reduntant bits */
163 l3_l4e = _mm_and_si128(l3_l4e, cksum_mask);
165 vlan0 = _mm_or_si128(vlan0, rss);
166 vlan0 = _mm_or_si128(vlan0, l3_l4e);
168 /* At this point, we have the 4 sets of flags in the low 16-bits
169 * of each 32-bit value in vlan0.
170 * We want to extract these, and merge them with the mbuf init data
171 * so we can do a single 16-byte write to the mbuf to set the flags
172 * and all the other initialization fields. Extracting the
173 * appropriate flags means that we have to do a shift and blend for
174 * each mbuf before we do the write.
176 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 8), 0x10);
177 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(vlan0, 4), 0x10);
178 rearm2 = _mm_blend_epi16(mbuf_init, vlan0, 0x10);
179 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(vlan0, 4), 0x10);
181 /* write the rearm data and the olflags in one write */
182 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
183 offsetof(struct rte_mbuf, rearm_data) + 8);
184 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
185 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
186 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
187 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
188 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
189 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
192 static inline __m128i
193 flex_rxd_to_fdir_flags_vec(const __m128i fdir_id0_3)
195 #define FDID_MIS_MAGIC 0xFFFFFFFF
196 RTE_BUILD_BUG_ON(PKT_RX_FDIR != (1 << 2));
197 RTE_BUILD_BUG_ON(PKT_RX_FDIR_ID != (1 << 13));
198 const __m128i pkt_fdir_bit = _mm_set1_epi32(PKT_RX_FDIR |
200 /* desc->flow_id field == 0xFFFFFFFF means fdir mismatch */
201 const __m128i fdir_mis_mask = _mm_set1_epi32(FDID_MIS_MAGIC);
202 __m128i fdir_mask = _mm_cmpeq_epi32(fdir_id0_3,
204 /* this XOR op results to bit-reverse the fdir_mask */
205 fdir_mask = _mm_xor_si128(fdir_mask, fdir_mis_mask);
206 const __m128i fdir_flags = _mm_and_si128(fdir_mask, pkt_fdir_bit);
212 flex_desc_to_olflags_v(struct iavf_rx_queue *rxq, __m128i descs[4],
213 struct rte_mbuf **rx_pkts)
215 const __m128i mbuf_init = _mm_set_epi64x(0, rxq->mbuf_initializer);
216 __m128i rearm0, rearm1, rearm2, rearm3;
218 __m128i tmp_desc, flags, rss_vlan;
220 /* mask everything except checksum, RSS and VLAN flags.
221 * bit6:4 for checksum.
222 * bit12 for RSS indication.
223 * bit13 for VLAN indication.
225 const __m128i desc_mask = _mm_set_epi32(0x3070, 0x3070,
228 const __m128i cksum_mask = _mm_set_epi32(PKT_RX_IP_CKSUM_MASK |
229 PKT_RX_L4_CKSUM_MASK |
230 PKT_RX_EIP_CKSUM_BAD,
231 PKT_RX_IP_CKSUM_MASK |
232 PKT_RX_L4_CKSUM_MASK |
233 PKT_RX_EIP_CKSUM_BAD,
234 PKT_RX_IP_CKSUM_MASK |
235 PKT_RX_L4_CKSUM_MASK |
236 PKT_RX_EIP_CKSUM_BAD,
237 PKT_RX_IP_CKSUM_MASK |
238 PKT_RX_L4_CKSUM_MASK |
239 PKT_RX_EIP_CKSUM_BAD);
241 /* map the checksum, rss and vlan fields to the checksum, rss
244 const __m128i cksum_flags = _mm_set_epi8(0, 0, 0, 0, 0, 0, 0, 0,
245 /* shift right 1 bit to make sure it not exceed 255 */
246 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
247 PKT_RX_IP_CKSUM_BAD) >> 1,
248 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_BAD |
249 PKT_RX_IP_CKSUM_GOOD) >> 1,
250 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
251 PKT_RX_IP_CKSUM_BAD) >> 1,
252 (PKT_RX_EIP_CKSUM_BAD | PKT_RX_L4_CKSUM_GOOD |
253 PKT_RX_IP_CKSUM_GOOD) >> 1,
254 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_BAD) >> 1,
255 (PKT_RX_L4_CKSUM_BAD | PKT_RX_IP_CKSUM_GOOD) >> 1,
256 (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_BAD) >> 1,
257 (PKT_RX_L4_CKSUM_GOOD | PKT_RX_IP_CKSUM_GOOD) >> 1);
259 const __m128i rss_vlan_flags = _mm_set_epi8(0, 0, 0, 0,
262 PKT_RX_RSS_HASH | PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
263 PKT_RX_VLAN | PKT_RX_VLAN_STRIPPED,
266 /* merge 4 descriptors */
267 flags = _mm_unpackhi_epi32(descs[0], descs[1]);
268 tmp_desc = _mm_unpackhi_epi32(descs[2], descs[3]);
269 tmp_desc = _mm_unpacklo_epi64(flags, tmp_desc);
270 tmp_desc = _mm_and_si128(flags, desc_mask);
273 tmp_desc = _mm_srli_epi32(tmp_desc, 4);
274 flags = _mm_shuffle_epi8(cksum_flags, tmp_desc);
275 /* then we shift left 1 bit */
276 flags = _mm_slli_epi32(flags, 1);
277 /* we need to mask out the redundant bits introduced by RSS or
280 flags = _mm_and_si128(flags, cksum_mask);
283 tmp_desc = _mm_srli_epi32(tmp_desc, 8);
284 rss_vlan = _mm_shuffle_epi8(rss_vlan_flags, tmp_desc);
286 /* merge the flags */
287 flags = _mm_or_si128(flags, rss_vlan);
289 if (rxq->fdir_enabled) {
290 const __m128i fdir_id0_1 =
291 _mm_unpackhi_epi32(descs[0], descs[1]);
293 const __m128i fdir_id2_3 =
294 _mm_unpackhi_epi32(descs[2], descs[3]);
296 const __m128i fdir_id0_3 =
297 _mm_unpackhi_epi64(fdir_id0_1, fdir_id2_3);
299 const __m128i fdir_flags =
300 flex_rxd_to_fdir_flags_vec(fdir_id0_3);
302 /* merge with fdir_flags */
303 flags = _mm_or_si128(flags, fdir_flags);
305 /* write fdir_id to mbuf */
306 rx_pkts[0]->hash.fdir.hi =
307 _mm_extract_epi32(fdir_id0_3, 0);
309 rx_pkts[1]->hash.fdir.hi =
310 _mm_extract_epi32(fdir_id0_3, 1);
312 rx_pkts[2]->hash.fdir.hi =
313 _mm_extract_epi32(fdir_id0_3, 2);
315 rx_pkts[3]->hash.fdir.hi =
316 _mm_extract_epi32(fdir_id0_3, 3);
317 } /* if() on fdir_enabled */
320 * At this point, we have the 4 sets of flags in the low 16-bits
321 * of each 32-bit value in flags.
322 * We want to extract these, and merge them with the mbuf init data
323 * so we can do a single 16-byte write to the mbuf to set the flags
324 * and all the other initialization fields. Extracting the
325 * appropriate flags means that we have to do a shift and blend for
326 * each mbuf before we do the write.
328 rearm0 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 8), 0x10);
329 rearm1 = _mm_blend_epi16(mbuf_init, _mm_slli_si128(flags, 4), 0x10);
330 rearm2 = _mm_blend_epi16(mbuf_init, flags, 0x10);
331 rearm3 = _mm_blend_epi16(mbuf_init, _mm_srli_si128(flags, 4), 0x10);
333 /* write the rearm data and the olflags in one write */
334 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, ol_flags) !=
335 offsetof(struct rte_mbuf, rearm_data) + 8);
336 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, rearm_data) !=
337 RTE_ALIGN(offsetof(struct rte_mbuf, rearm_data), 16));
338 _mm_store_si128((__m128i *)&rx_pkts[0]->rearm_data, rearm0);
339 _mm_store_si128((__m128i *)&rx_pkts[1]->rearm_data, rearm1);
340 _mm_store_si128((__m128i *)&rx_pkts[2]->rearm_data, rearm2);
341 _mm_store_si128((__m128i *)&rx_pkts[3]->rearm_data, rearm3);
344 #define PKTLEN_SHIFT 10
347 desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
348 const uint32_t *type_table)
350 __m128i ptype0 = _mm_unpackhi_epi64(descs[0], descs[1]);
351 __m128i ptype1 = _mm_unpackhi_epi64(descs[2], descs[3]);
353 ptype0 = _mm_srli_epi64(ptype0, 30);
354 ptype1 = _mm_srli_epi64(ptype1, 30);
356 rx_pkts[0]->packet_type = type_table[_mm_extract_epi8(ptype0, 0)];
357 rx_pkts[1]->packet_type = type_table[_mm_extract_epi8(ptype0, 8)];
358 rx_pkts[2]->packet_type = type_table[_mm_extract_epi8(ptype1, 0)];
359 rx_pkts[3]->packet_type = type_table[_mm_extract_epi8(ptype1, 8)];
363 flex_desc_to_ptype_v(__m128i descs[4], struct rte_mbuf **rx_pkts,
364 const uint32_t *type_table)
366 const __m128i ptype_mask = _mm_set_epi16(0, IAVF_RX_FLEX_DESC_PTYPE_M,
367 0, IAVF_RX_FLEX_DESC_PTYPE_M,
368 0, IAVF_RX_FLEX_DESC_PTYPE_M,
369 0, IAVF_RX_FLEX_DESC_PTYPE_M);
370 __m128i ptype_01 = _mm_unpacklo_epi32(descs[0], descs[1]);
371 __m128i ptype_23 = _mm_unpacklo_epi32(descs[2], descs[3]);
372 __m128i ptype_all = _mm_unpacklo_epi64(ptype_01, ptype_23);
374 ptype_all = _mm_and_si128(ptype_all, ptype_mask);
376 rx_pkts[0]->packet_type = type_table[_mm_extract_epi16(ptype_all, 1)];
377 rx_pkts[1]->packet_type = type_table[_mm_extract_epi16(ptype_all, 3)];
378 rx_pkts[2]->packet_type = type_table[_mm_extract_epi16(ptype_all, 5)];
379 rx_pkts[3]->packet_type = type_table[_mm_extract_epi16(ptype_all, 7)];
383 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
384 * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
387 static inline uint16_t
388 _recv_raw_pkts_vec(struct iavf_rx_queue *rxq, struct rte_mbuf **rx_pkts,
389 uint16_t nb_pkts, uint8_t *split_packet)
391 volatile union iavf_rx_desc *rxdp;
392 struct rte_mbuf **sw_ring;
393 uint16_t nb_pkts_recd;
397 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
399 __m128i crc_adjust = _mm_set_epi16(
400 0, 0, 0, /* ignore non-length fields */
401 -rxq->crc_len, /* sub crc on data_len */
402 0, /* ignore high-16bits of pkt_len */
403 -rxq->crc_len, /* sub crc on pkt_len */
404 0, 0 /* ignore pkt_type field */
406 /* compile-time check the above crc_adjust layout is correct.
407 * NOTE: the first field (lowest address) is given last in set_epi16
410 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
411 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
412 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
413 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
414 __m128i dd_check, eop_check;
416 /* nb_pkts shall be less equal than IAVF_VPMD_RX_MAX_BURST */
417 nb_pkts = RTE_MIN(nb_pkts, IAVF_VPMD_RX_MAX_BURST);
419 /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
420 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
422 /* Just the act of getting into the function from the application is
423 * going to cost about 7 cycles
425 rxdp = rxq->rx_ring + rxq->rx_tail;
429 /* See if we need to rearm the RX queue - gives the prefetch a bit
432 if (rxq->rxrearm_nb > rxq->rx_free_thresh)
435 /* Before we start moving massive data around, check to see if
436 * there is actually a packet available
438 if (!(rxdp->wb.qword1.status_error_len &
439 rte_cpu_to_le_32(1 << IAVF_RX_DESC_STATUS_DD_SHIFT)))
442 /* 4 packets DD mask */
443 dd_check = _mm_set_epi64x(0x0000000100000001LL, 0x0000000100000001LL);
445 /* 4 packets EOP mask */
446 eop_check = _mm_set_epi64x(0x0000000200000002LL, 0x0000000200000002LL);
448 /* mask to shuffle from desc. to mbuf */
449 shuf_msk = _mm_set_epi8(
450 7, 6, 5, 4, /* octet 4~7, 32bits rss */
451 3, 2, /* octet 2~3, low 16 bits vlan_macip */
452 15, 14, /* octet 15~14, 16 bits data_len */
453 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
454 15, 14, /* octet 15~14, low 16 bits pkt_len */
455 0xFF, 0xFF, 0xFF, 0xFF /* pkt_type set as unknown */
457 /* Compile-time verify the shuffle mask
458 * NOTE: some field positions already verified above, but duplicated
459 * here for completeness in case of future modifications.
461 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
462 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
463 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
464 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
465 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
466 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
467 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
468 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
470 /* Cache is empty -> need to scan the buffer rings, but first move
471 * the next 'n' mbufs into the cache
473 sw_ring = &rxq->sw_ring[rxq->rx_tail];
475 /* A. load 4 packet in one loop
476 * [A*. mask out 4 unused dirty field in desc]
477 * B. copy 4 mbuf point from swring to rx_pkts
478 * C. calc the number of DD bits among the 4 packets
479 * [C*. extract the end-of-packet bit, if requested]
480 * D. fill info. from desc to mbuf
483 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
484 pos += IAVF_VPMD_DESCS_PER_LOOP,
485 rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
486 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
487 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
488 __m128i zero, staterr, sterr_tmp1, sterr_tmp2;
489 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
491 #if defined(RTE_ARCH_X86_64)
495 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
496 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
497 /* Read desc statuses backwards to avoid race condition */
498 /* A.1 load 4 pkts desc */
499 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
500 rte_compiler_barrier();
502 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
503 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
505 #if defined(RTE_ARCH_X86_64)
506 /* B.1 load 2 64 bit mbuf points */
507 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
510 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
511 rte_compiler_barrier();
512 /* B.1 load 2 mbuf point */
513 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
514 rte_compiler_barrier();
515 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
517 #if defined(RTE_ARCH_X86_64)
518 /* B.2 copy 2 mbuf point into rx_pkts */
519 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
523 rte_mbuf_prefetch_part2(rx_pkts[pos]);
524 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
525 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
526 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
529 /* avoid compiler reorder optimization */
530 rte_compiler_barrier();
532 /* pkt 3,4 shift the pktlen field to be 16-bit aligned*/
533 const __m128i len3 = _mm_slli_epi32(descs[3], PKTLEN_SHIFT);
534 const __m128i len2 = _mm_slli_epi32(descs[2], PKTLEN_SHIFT);
536 /* merge the now-aligned packet length fields back in */
537 descs[3] = _mm_blend_epi16(descs[3], len3, 0x80);
538 descs[2] = _mm_blend_epi16(descs[2], len2, 0x80);
540 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
541 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
542 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
544 /* C.1 4=>2 status err info only */
545 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
546 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
548 desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
550 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
551 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
552 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
554 /* pkt 1,2 shift the pktlen field to be 16-bit aligned*/
555 const __m128i len1 = _mm_slli_epi32(descs[1], PKTLEN_SHIFT);
556 const __m128i len0 = _mm_slli_epi32(descs[0], PKTLEN_SHIFT);
558 /* merge the now-aligned packet length fields back in */
559 descs[1] = _mm_blend_epi16(descs[1], len1, 0x80);
560 descs[0] = _mm_blend_epi16(descs[0], len0, 0x80);
562 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
563 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
564 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
566 /* C.2 get 4 pkts status err value */
567 zero = _mm_xor_si128(dd_check, dd_check);
568 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
570 /* D.3 copy final 3,4 data to rx_pkts */
572 (void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
575 (void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
578 /* D.2 pkt 1,2 remove crc */
579 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
580 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
582 /* C* extract and record EOP bit */
584 __m128i eop_shuf_mask = _mm_set_epi8(
585 0xFF, 0xFF, 0xFF, 0xFF,
586 0xFF, 0xFF, 0xFF, 0xFF,
587 0xFF, 0xFF, 0xFF, 0xFF,
588 0x04, 0x0C, 0x00, 0x08
591 /* and with mask to extract bits, flipping 1-0 */
592 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
593 /* the staterr values are not in order, as the count
594 * count of dd bits doesn't care. However, for end of
595 * packet tracking, we do care, so shuffle. This also
596 * compresses the 32-bit values to 8-bit
598 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
599 /* store the resulting 32-bit value */
600 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
601 split_packet += IAVF_VPMD_DESCS_PER_LOOP;
604 /* C.3 calc available number of desc */
605 staterr = _mm_and_si128(staterr, dd_check);
606 staterr = _mm_packs_epi32(staterr, zero);
608 /* D.3 copy final 1,2 data to rx_pkts */
610 (void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
612 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
614 desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
615 /* C.4 calc avaialbe number of desc */
616 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
618 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
622 /* Update our internal tail pointer */
623 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
624 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
625 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
631 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
632 * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
635 static inline uint16_t
636 _recv_raw_pkts_vec_flex_rxd(struct iavf_rx_queue *rxq,
637 struct rte_mbuf **rx_pkts,
638 uint16_t nb_pkts, uint8_t *split_packet)
640 volatile union iavf_rx_flex_desc *rxdp;
641 struct rte_mbuf **sw_ring;
642 uint16_t nb_pkts_recd;
645 const uint32_t *ptype_tbl = rxq->vsi->adapter->ptype_tbl;
646 __m128i crc_adjust = _mm_set_epi16
647 (0, 0, 0, /* ignore non-length fields */
648 -rxq->crc_len, /* sub crc on data_len */
649 0, /* ignore high-16bits of pkt_len */
650 -rxq->crc_len, /* sub crc on pkt_len */
651 0, 0 /* ignore pkt_type field */
653 const __m128i zero = _mm_setzero_si128();
654 /* mask to shuffle from desc. to mbuf */
655 const __m128i shuf_msk = _mm_set_epi8
657 0xFF, 0xFF, /* rss not supported */
658 11, 10, /* octet 10~11, 16 bits vlan_macip */
659 5, 4, /* octet 4~5, 16 bits data_len */
660 0xFF, 0xFF, /* skip high 16 bits pkt_len, zero out */
661 5, 4, /* octet 4~5, low 16 bits pkt_len */
662 0xFF, 0xFF, /* pkt_type set as unknown */
663 0xFF, 0xFF /* pkt_type set as unknown */
665 const __m128i eop_shuf_mask = _mm_set_epi8(0xFF, 0xFF,
675 * compile-time check the above crc_adjust layout is correct.
676 * NOTE: the first field (lowest address) is given last in set_epi16
679 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
680 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
681 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
682 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
684 /* 4 packets DD mask */
685 const __m128i dd_check = _mm_set_epi64x(0x0000000100000001LL,
686 0x0000000100000001LL);
687 /* 4 packets EOP mask */
688 const __m128i eop_check = _mm_set_epi64x(0x0000000200000002LL,
689 0x0000000200000002LL);
691 /* nb_pkts shall be less equal than IAVF_VPMD_RX_MAX_BURST */
692 nb_pkts = RTE_MIN(nb_pkts, IAVF_VPMD_RX_MAX_BURST);
694 /* nb_pkts has to be floor-aligned to IAVF_VPMD_DESCS_PER_LOOP */
695 nb_pkts = RTE_ALIGN_FLOOR(nb_pkts, IAVF_VPMD_DESCS_PER_LOOP);
697 /* Just the act of getting into the function from the application is
698 * going to cost about 7 cycles
700 rxdp = (union iavf_rx_flex_desc *)rxq->rx_ring + rxq->rx_tail;
704 /* See if we need to rearm the RX queue - gives the prefetch a bit
707 if (rxq->rxrearm_nb > rxq->rx_free_thresh)
710 /* Before we start moving massive data around, check to see if
711 * there is actually a packet available
713 if (!(rxdp->wb.status_error0 &
714 rte_cpu_to_le_32(1 << IAVF_RX_FLEX_DESC_STATUS0_DD_S)))
718 * Compile-time verify the shuffle mask
719 * NOTE: some field positions already verified above, but duplicated
720 * here for completeness in case of future modifications.
722 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, pkt_len) !=
723 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 4);
724 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, data_len) !=
725 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 8);
726 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, vlan_tci) !=
727 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 10);
728 RTE_BUILD_BUG_ON(offsetof(struct rte_mbuf, hash) !=
729 offsetof(struct rte_mbuf, rx_descriptor_fields1) + 12);
731 /* Cache is empty -> need to scan the buffer rings, but first move
732 * the next 'n' mbufs into the cache
734 sw_ring = &rxq->sw_ring[rxq->rx_tail];
736 /* A. load 4 packet in one loop
737 * [A*. mask out 4 unused dirty field in desc]
738 * B. copy 4 mbuf point from swring to rx_pkts
739 * C. calc the number of DD bits among the 4 packets
740 * [C*. extract the end-of-packet bit, if requested]
741 * D. fill info. from desc to mbuf
744 for (pos = 0, nb_pkts_recd = 0; pos < nb_pkts;
745 pos += IAVF_VPMD_DESCS_PER_LOOP,
746 rxdp += IAVF_VPMD_DESCS_PER_LOOP) {
747 __m128i descs[IAVF_VPMD_DESCS_PER_LOOP];
748 __m128i pkt_mb1, pkt_mb2, pkt_mb3, pkt_mb4;
749 __m128i staterr, sterr_tmp1, sterr_tmp2;
750 /* 2 64 bit or 4 32 bit mbuf pointers in one XMM reg. */
752 #if defined(RTE_ARCH_X86_64)
756 /* B.1 load 2 (64 bit) or 4 (32 bit) mbuf points */
757 mbp1 = _mm_loadu_si128((__m128i *)&sw_ring[pos]);
758 /* Read desc statuses backwards to avoid race condition */
759 /* A.1 load 4 pkts desc */
760 descs[3] = _mm_loadu_si128((__m128i *)(rxdp + 3));
761 rte_compiler_barrier();
763 /* B.2 copy 2 64 bit or 4 32 bit mbuf point into rx_pkts */
764 _mm_storeu_si128((__m128i *)&rx_pkts[pos], mbp1);
766 #if defined(RTE_ARCH_X86_64)
767 /* B.1 load 2 64 bit mbuf points */
768 mbp2 = _mm_loadu_si128((__m128i *)&sw_ring[pos + 2]);
771 descs[2] = _mm_loadu_si128((__m128i *)(rxdp + 2));
772 rte_compiler_barrier();
773 /* B.1 load 2 mbuf point */
774 descs[1] = _mm_loadu_si128((__m128i *)(rxdp + 1));
775 rte_compiler_barrier();
776 descs[0] = _mm_loadu_si128((__m128i *)(rxdp));
778 #if defined(RTE_ARCH_X86_64)
779 /* B.2 copy 2 mbuf point into rx_pkts */
780 _mm_storeu_si128((__m128i *)&rx_pkts[pos + 2], mbp2);
784 rte_mbuf_prefetch_part2(rx_pkts[pos]);
785 rte_mbuf_prefetch_part2(rx_pkts[pos + 1]);
786 rte_mbuf_prefetch_part2(rx_pkts[pos + 2]);
787 rte_mbuf_prefetch_part2(rx_pkts[pos + 3]);
790 /* avoid compiler reorder optimization */
791 rte_compiler_barrier();
793 /* D.1 pkt 3,4 convert format from desc to pktmbuf */
794 pkt_mb4 = _mm_shuffle_epi8(descs[3], shuf_msk);
795 pkt_mb3 = _mm_shuffle_epi8(descs[2], shuf_msk);
797 /* C.1 4=>2 filter staterr info only */
798 sterr_tmp2 = _mm_unpackhi_epi32(descs[3], descs[2]);
799 /* C.1 4=>2 filter staterr info only */
800 sterr_tmp1 = _mm_unpackhi_epi32(descs[1], descs[0]);
802 flex_desc_to_olflags_v(rxq, descs, &rx_pkts[pos]);
804 /* D.2 pkt 3,4 set in_port/nb_seg and remove crc */
805 pkt_mb4 = _mm_add_epi16(pkt_mb4, crc_adjust);
806 pkt_mb3 = _mm_add_epi16(pkt_mb3, crc_adjust);
808 /* D.1 pkt 1,2 convert format from desc to pktmbuf */
809 pkt_mb2 = _mm_shuffle_epi8(descs[1], shuf_msk);
810 pkt_mb1 = _mm_shuffle_epi8(descs[0], shuf_msk);
812 /* C.2 get 4 pkts staterr value */
813 staterr = _mm_unpacklo_epi32(sterr_tmp1, sterr_tmp2);
815 /* D.3 copy final 3,4 data to rx_pkts */
817 ((void *)&rx_pkts[pos + 3]->rx_descriptor_fields1,
820 ((void *)&rx_pkts[pos + 2]->rx_descriptor_fields1,
823 /* D.2 pkt 1,2 set in_port/nb_seg and remove crc */
824 pkt_mb2 = _mm_add_epi16(pkt_mb2, crc_adjust);
825 pkt_mb1 = _mm_add_epi16(pkt_mb1, crc_adjust);
827 /* C* extract and record EOP bit */
829 /* and with mask to extract bits, flipping 1-0 */
830 __m128i eop_bits = _mm_andnot_si128(staterr, eop_check);
831 /* the staterr values are not in order, as the count
832 * count of dd bits doesn't care. However, for end of
833 * packet tracking, we do care, so shuffle. This also
834 * compresses the 32-bit values to 8-bit
836 eop_bits = _mm_shuffle_epi8(eop_bits, eop_shuf_mask);
837 /* store the resulting 32-bit value */
838 *(int *)split_packet = _mm_cvtsi128_si32(eop_bits);
839 split_packet += IAVF_VPMD_DESCS_PER_LOOP;
842 /* C.3 calc available number of desc */
843 staterr = _mm_and_si128(staterr, dd_check);
844 staterr = _mm_packs_epi32(staterr, zero);
846 /* D.3 copy final 1,2 data to rx_pkts */
848 ((void *)&rx_pkts[pos + 1]->rx_descriptor_fields1,
850 _mm_storeu_si128((void *)&rx_pkts[pos]->rx_descriptor_fields1,
852 flex_desc_to_ptype_v(descs, &rx_pkts[pos], ptype_tbl);
853 /* C.4 calc available number of desc */
854 var = __builtin_popcountll(_mm_cvtsi128_si64(staterr));
856 if (likely(var != IAVF_VPMD_DESCS_PER_LOOP))
860 /* Update our internal tail pointer */
861 rxq->rx_tail = (uint16_t)(rxq->rx_tail + nb_pkts_recd);
862 rxq->rx_tail = (uint16_t)(rxq->rx_tail & (rxq->nb_rx_desc - 1));
863 rxq->rxrearm_nb = (uint16_t)(rxq->rxrearm_nb + nb_pkts_recd);
869 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
870 * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
874 iavf_recv_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
877 return _recv_raw_pkts_vec(rx_queue, rx_pkts, nb_pkts, NULL);
881 * - nb_pkts < IAVF_DESCS_PER_LOOP, just return no packet
882 * - nb_pkts > IAVF_VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
886 iavf_recv_pkts_vec_flex_rxd(void *rx_queue, struct rte_mbuf **rx_pkts,
889 return _recv_raw_pkts_vec_flex_rxd(rx_queue, rx_pkts, nb_pkts, NULL);
892 /* vPMD receive routine that reassembles scattered packets
894 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
895 * - nb_pkts > VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
899 iavf_recv_scattered_pkts_vec(void *rx_queue, struct rte_mbuf **rx_pkts,
902 struct iavf_rx_queue *rxq = rx_queue;
903 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
906 /* get some new buffers */
907 uint16_t nb_bufs = _recv_raw_pkts_vec(rxq, rx_pkts, nb_pkts,
912 /* happy day case, full burst + no packets to be joined */
913 const uint64_t *split_fl64 = (uint64_t *)split_flags;
915 if (!rxq->pkt_first_seg &&
916 split_fl64[0] == 0 && split_fl64[1] == 0 &&
917 split_fl64[2] == 0 && split_fl64[3] == 0)
920 /* reassemble any packets that need reassembly*/
921 if (!rxq->pkt_first_seg) {
922 /* find the first split flag, and only reassemble then*/
923 while (i < nb_bufs && !split_flags[i])
927 rxq->pkt_first_seg = rx_pkts[i];
929 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
933 /* vPMD receive routine that reassembles scattered packets for flex RxD
935 * - nb_pkts < IAVF_VPMD_DESCS_PER_LOOP, just return no packet
936 * - nb_pkts > VPMD_RX_MAX_BURST, only scan IAVF_VPMD_RX_MAX_BURST
940 iavf_recv_scattered_pkts_vec_flex_rxd(void *rx_queue,
941 struct rte_mbuf **rx_pkts,
944 struct iavf_rx_queue *rxq = rx_queue;
945 uint8_t split_flags[IAVF_VPMD_RX_MAX_BURST] = {0};
948 /* get some new buffers */
949 uint16_t nb_bufs = _recv_raw_pkts_vec_flex_rxd(rxq, rx_pkts, nb_pkts,
954 /* happy day case, full burst + no packets to be joined */
955 const uint64_t *split_fl64 = (uint64_t *)split_flags;
957 if (!rxq->pkt_first_seg &&
958 split_fl64[0] == 0 && split_fl64[1] == 0 &&
959 split_fl64[2] == 0 && split_fl64[3] == 0)
962 /* reassemble any packets that need reassembly*/
963 if (!rxq->pkt_first_seg) {
964 /* find the first split flag, and only reassemble then*/
965 while (i < nb_bufs && !split_flags[i])
969 rxq->pkt_first_seg = rx_pkts[i];
971 return i + reassemble_packets(rxq, &rx_pkts[i], nb_bufs - i,
976 vtx1(volatile struct iavf_tx_desc *txdp, struct rte_mbuf *pkt, uint64_t flags)
979 (IAVF_TX_DESC_DTYPE_DATA |
980 ((uint64_t)flags << IAVF_TXD_QW1_CMD_SHIFT) |
981 ((uint64_t)pkt->data_len <<
982 IAVF_TXD_QW1_TX_BUF_SZ_SHIFT));
984 __m128i descriptor = _mm_set_epi64x(high_qw,
985 pkt->buf_iova + pkt->data_off);
986 _mm_store_si128((__m128i *)txdp, descriptor);
990 iavf_vtx(volatile struct iavf_tx_desc *txdp, struct rte_mbuf **pkt,
991 uint16_t nb_pkts, uint64_t flags)
995 for (i = 0; i < nb_pkts; ++i, ++txdp, ++pkt)
996 vtx1(txdp, *pkt, flags);
1000 iavf_xmit_fixed_burst_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1003 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1004 volatile struct iavf_tx_desc *txdp;
1005 struct iavf_tx_entry *txep;
1006 uint16_t n, nb_commit, tx_id;
1007 uint64_t flags = IAVF_TX_DESC_CMD_EOP | 0x04; /* bit 2 must be set */
1008 uint64_t rs = IAVF_TX_DESC_CMD_RS | flags;
1011 /* cross rx_thresh boundary is not allowed */
1012 nb_pkts = RTE_MIN(nb_pkts, txq->rs_thresh);
1014 if (txq->nb_free < txq->free_thresh)
1015 iavf_tx_free_bufs(txq);
1017 nb_pkts = (uint16_t)RTE_MIN(txq->nb_free, nb_pkts);
1018 if (unlikely(nb_pkts == 0))
1020 nb_commit = nb_pkts;
1022 tx_id = txq->tx_tail;
1023 txdp = &txq->tx_ring[tx_id];
1024 txep = &txq->sw_ring[tx_id];
1026 txq->nb_free = (uint16_t)(txq->nb_free - nb_pkts);
1028 n = (uint16_t)(txq->nb_tx_desc - tx_id);
1029 if (nb_commit >= n) {
1030 tx_backlog_entry(txep, tx_pkts, n);
1032 for (i = 0; i < n - 1; ++i, ++tx_pkts, ++txdp)
1033 vtx1(txdp, *tx_pkts, flags);
1035 vtx1(txdp, *tx_pkts++, rs);
1037 nb_commit = (uint16_t)(nb_commit - n);
1040 txq->next_rs = (uint16_t)(txq->rs_thresh - 1);
1042 /* avoid reach the end of ring */
1043 txdp = &txq->tx_ring[tx_id];
1044 txep = &txq->sw_ring[tx_id];
1047 tx_backlog_entry(txep, tx_pkts, nb_commit);
1049 iavf_vtx(txdp, tx_pkts, nb_commit, flags);
1051 tx_id = (uint16_t)(tx_id + nb_commit);
1052 if (tx_id > txq->next_rs) {
1053 txq->tx_ring[txq->next_rs].cmd_type_offset_bsz |=
1054 rte_cpu_to_le_64(((uint64_t)IAVF_TX_DESC_CMD_RS) <<
1055 IAVF_TXD_QW1_CMD_SHIFT);
1057 (uint16_t)(txq->next_rs + txq->rs_thresh);
1060 txq->tx_tail = tx_id;
1062 PMD_TX_LOG(DEBUG, "port_id=%u queue_id=%u tx_tail=%u nb_pkts=%u",
1063 txq->port_id, txq->queue_id, tx_id, nb_pkts);
1065 IAVF_PCI_REG_WRITE(txq->qtx_tail, txq->tx_tail);
1071 iavf_xmit_pkts_vec(void *tx_queue, struct rte_mbuf **tx_pkts,
1075 struct iavf_tx_queue *txq = (struct iavf_tx_queue *)tx_queue;
1080 num = (uint16_t)RTE_MIN(nb_pkts, txq->rs_thresh);
1081 ret = iavf_xmit_fixed_burst_vec(tx_queue, &tx_pkts[nb_tx], num);
1091 static void __rte_cold
1092 iavf_rx_queue_release_mbufs_sse(struct iavf_rx_queue *rxq)
1094 _iavf_rx_queue_release_mbufs_vec(rxq);
1097 static void __rte_cold
1098 iavf_tx_queue_release_mbufs_sse(struct iavf_tx_queue *txq)
1100 _iavf_tx_queue_release_mbufs_vec(txq);
1103 static const struct iavf_rxq_ops sse_vec_rxq_ops = {
1104 .release_mbufs = iavf_rx_queue_release_mbufs_sse,
1107 static const struct iavf_txq_ops sse_vec_txq_ops = {
1108 .release_mbufs = iavf_tx_queue_release_mbufs_sse,
1112 iavf_txq_vec_setup(struct iavf_tx_queue *txq)
1114 txq->ops = &sse_vec_txq_ops;
1119 iavf_rxq_vec_setup(struct iavf_rx_queue *rxq)
1121 rxq->ops = &sse_vec_rxq_ops;
1122 return iavf_rxq_vec_setup_default(rxq);
1126 iavf_rx_vec_dev_check(struct rte_eth_dev *dev)
1128 return iavf_rx_vec_dev_check_default(dev);
1132 iavf_tx_vec_dev_check(struct rte_eth_dev *dev)
1134 return iavf_tx_vec_dev_check_default(dev);