drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <rte_ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include "base/ice_sched.h"
  14 #include "base/ice_flow.h"
  15 #include "base/ice_dcb.h"
  16 #include "ice_ethdev.h"
  17 #include "ice_rxtx.h"
  18
  19 #define ICE_MAX_QP_NUM "max_queue_pair_num"
  20 #define ICE_DFLT_OUTER_TAG_TYPE ICE_AQ_VSI_OUTER_TAG_VLAN_9100
  21 #define ICE_DFLT_PKG_FILE "/lib/firmware/intel/ice/ddp/ice.pkg"
  22
  23 int ice_logtype_init;
  24 int ice_logtype_driver;
  25
  26 static int ice_dev_configure(struct rte_eth_dev *dev);
  27 static int ice_dev_start(struct rte_eth_dev *dev);
  28 static void ice_dev_stop(struct rte_eth_dev *dev);
  29 static void ice_dev_close(struct rte_eth_dev *dev);
  30 static int ice_dev_reset(struct rte_eth_dev *dev);
  31 static void ice_dev_info_get(struct rte_eth_dev *dev,
  32                              struct rte_eth_dev_info *dev_info);
  33 static int ice_link_update(struct rte_eth_dev *dev,
  34                            int wait_to_complete);
  35 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  36 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  37
  38 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  39 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  40 static int ice_vlan_tpid_set(struct rte_eth_dev *dev,
  41                              enum rte_vlan_type vlan_type,
  42                              uint16_t tpid);
  43 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  44                                struct rte_eth_rss_reta_entry64 *reta_conf,
  45                                uint16_t reta_size);
  46 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  47                               struct rte_eth_rss_reta_entry64 *reta_conf,
  48                               uint16_t reta_size);
  49 static int ice_rss_hash_update(struct rte_eth_dev *dev,
  50                                struct rte_eth_rss_conf *rss_conf);
  51 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
  52                                  struct rte_eth_rss_conf *rss_conf);
  53 static void ice_promisc_enable(struct rte_eth_dev *dev);
  54 static void ice_promisc_disable(struct rte_eth_dev *dev);
  55 static void ice_allmulti_enable(struct rte_eth_dev *dev);
  56 static void ice_allmulti_disable(struct rte_eth_dev *dev);
  57 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
  58                                uint16_t vlan_id,
  59                                int on);
  60 static int ice_macaddr_set(struct rte_eth_dev *dev,
  61                            struct ether_addr *mac_addr);
  62 static int ice_macaddr_add(struct rte_eth_dev *dev,
  63                            struct ether_addr *mac_addr,
  64                            __rte_unused uint32_t index,
  65                            uint32_t pool);
  66 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
  67 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
  68                                     uint16_t queue_id);
  69 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
  70                                      uint16_t queue_id);
  71 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
  72                               size_t fw_size);
  73 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
  74                              uint16_t pvid, int on);
  75 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
  76 static int ice_get_eeprom(struct rte_eth_dev *dev,
  77                           struct rte_dev_eeprom_info *eeprom);
  78 static int ice_stats_get(struct rte_eth_dev *dev,
  79                          struct rte_eth_stats *stats);
  80 static void ice_stats_reset(struct rte_eth_dev *dev);
  81 static int ice_xstats_get(struct rte_eth_dev *dev,
  82                           struct rte_eth_xstat *xstats, unsigned int n);
  83 static int ice_xstats_get_names(struct rte_eth_dev *dev,
  84                                 struct rte_eth_xstat_name *xstats_names,
  85                                 unsigned int limit);
  86
  87 static const struct rte_pci_id pci_id_ice_map[] = {
  88         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
  89         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
  90         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
  91         { .vendor_id = 0, /* sentinel */ },
  92 };
  93
  94 static const struct eth_dev_ops ice_eth_dev_ops = {
  95         .dev_configure                = ice_dev_configure,
  96         .dev_start                    = ice_dev_start,
  97         .dev_stop                     = ice_dev_stop,
  98         .dev_close                    = ice_dev_close,
  99         .dev_reset                    = ice_dev_reset,
 100         .dev_set_link_up              = ice_dev_set_link_up,
 101         .dev_set_link_down            = ice_dev_set_link_down,
 102         .rx_queue_start               = ice_rx_queue_start,
 103         .rx_queue_stop                = ice_rx_queue_stop,
 104         .tx_queue_start               = ice_tx_queue_start,
 105         .tx_queue_stop                = ice_tx_queue_stop,
 106         .rx_queue_setup               = ice_rx_queue_setup,
 107         .rx_queue_release             = ice_rx_queue_release,
 108         .tx_queue_setup               = ice_tx_queue_setup,
 109         .tx_queue_release             = ice_tx_queue_release,
 110         .dev_infos_get                = ice_dev_info_get,
 111         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 112         .link_update                  = ice_link_update,
 113         .mtu_set                      = ice_mtu_set,
 114         .mac_addr_set                 = ice_macaddr_set,
 115         .mac_addr_add                 = ice_macaddr_add,
 116         .mac_addr_remove              = ice_macaddr_remove,
 117         .vlan_filter_set              = ice_vlan_filter_set,
 118         .vlan_offload_set             = ice_vlan_offload_set,
 119         .vlan_tpid_set                = ice_vlan_tpid_set,
 120         .reta_update                  = ice_rss_reta_update,
 121         .reta_query                   = ice_rss_reta_query,
 122         .rss_hash_update              = ice_rss_hash_update,
 123         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 124         .promiscuous_enable           = ice_promisc_enable,
 125         .promiscuous_disable          = ice_promisc_disable,
 126         .allmulticast_enable          = ice_allmulti_enable,
 127         .allmulticast_disable         = ice_allmulti_disable,
 128         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 129         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 130         .fw_version_get               = ice_fw_version_get,
 131         .vlan_pvid_set                = ice_vlan_pvid_set,
 132         .rxq_info_get                 = ice_rxq_info_get,
 133         .txq_info_get                 = ice_txq_info_get,
 134         .get_eeprom_length            = ice_get_eeprom_length,
 135         .get_eeprom                   = ice_get_eeprom,
 136         .rx_queue_count               = ice_rx_queue_count,
 137         .rx_descriptor_status         = ice_rx_descriptor_status,
 138         .tx_descriptor_status         = ice_tx_descriptor_status,
 139         .stats_get                    = ice_stats_get,
 140         .stats_reset                  = ice_stats_reset,
 141         .xstats_get                   = ice_xstats_get,
 142         .xstats_get_names             = ice_xstats_get_names,
 143         .xstats_reset                 = ice_stats_reset,
 144 };
 145
 146 /* store statistics names and its offset in stats structure */
 147 struct ice_xstats_name_off {
 148         char name[RTE_ETH_XSTATS_NAME_SIZE];
 149         unsigned int offset;
 150 };
 151
 152 static const struct ice_xstats_name_off ice_stats_strings[] = {
 153         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 154         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 155         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 156         {"rx_dropped", offsetof(struct ice_eth_stats, rx_discards)},
 157         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 158                 rx_unknown_protocol)},
 159         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 160         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 161         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 162         {"tx_dropped", offsetof(struct ice_eth_stats, tx_discards)},
 163 };
 164
 165 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 166                 sizeof(ice_stats_strings[0]))
 167
 168 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 169         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 170                 tx_dropped_link_down)},
 171         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 172         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 173                 illegal_bytes)},
 174         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 175         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 176                 mac_local_faults)},
 177         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 178                 mac_remote_faults)},
 179         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 180                 rx_len_errors)},
 181         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 182         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 183         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 184         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 185         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 186         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 187                 rx_size_127)},
 188         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 189                 rx_size_255)},
 190         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 191                 rx_size_511)},
 192         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 193                 rx_size_1023)},
 194         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 195                 rx_size_1522)},
 196         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 197                 rx_size_big)},
 198         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 199                 rx_undersize)},
 200         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 201                 rx_oversize)},
 202         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 203                 mac_short_pkt_dropped)},
 204         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 205                 rx_fragments)},
 206         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 207         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 208         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 209                 tx_size_127)},
 210         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 211                 tx_size_255)},
 212         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 213                 tx_size_511)},
 214         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 215                 tx_size_1023)},
 216         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 217                 tx_size_1522)},
 218         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 219                 tx_size_big)},
 220 };
 221
 222 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 223                 sizeof(ice_hw_port_strings[0]))
 224
 225 static void
 226 ice_init_controlq_parameter(struct ice_hw *hw)
 227 {
 228         /* fields for adminq */
 229         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 230         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 231         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 232         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 233
 234         /* fields for mailboxq, DPDK used as PF host */
 235         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 236         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 237         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 238         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 239 }
 240
 241 static int
 242 ice_check_qp_num(const char *key, const char *qp_value,
 243                  __rte_unused void *opaque)
 244 {
 245         char *end = NULL;
 246         int num = 0;
 247
 248         while (isblank(*qp_value))
 249                 qp_value++;
 250
 251         num = strtoul(qp_value, &end, 10);
 252
 253         if (!num || (*end == '-') || errno) {
 254                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
 255                             "value must be > 0",
 256                             qp_value, key);
 257                 return -1;
 258         }
 259
 260         return num;
 261 }
 262
 263 static int
 264 ice_config_max_queue_pair_num(struct rte_devargs *devargs)
 265 {
 266         struct rte_kvargs *kvlist;
 267         const char *queue_num_key = ICE_MAX_QP_NUM;
 268         int ret;
 269
 270         if (!devargs)
 271                 return 0;
 272
 273         kvlist = rte_kvargs_parse(devargs->args, NULL);
 274         if (!kvlist)
 275                 return 0;
 276
 277         if (!rte_kvargs_count(kvlist, queue_num_key)) {
 278                 rte_kvargs_free(kvlist);
 279                 return 0;
 280         }
 281
 282         if (rte_kvargs_process(kvlist, queue_num_key,
 283                                ice_check_qp_num, NULL) < 0) {
 284                 rte_kvargs_free(kvlist);
 285                 return 0;
 286         }
 287         ret = rte_kvargs_process(kvlist, queue_num_key,
 288                                  ice_check_qp_num, NULL);
 289         rte_kvargs_free(kvlist);
 290
 291         return ret;
 292 }
 293
 294 static int
 295 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 296                   uint32_t num)
 297 {
 298         struct pool_entry *entry;
 299
 300         if (!pool || !num)
 301                 return -EINVAL;
 302
 303         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 304         if (!entry) {
 305                 PMD_INIT_LOG(ERR,
 306                              "Failed to allocate memory for resource pool");
 307                 return -ENOMEM;
 308         }
 309
 310         /* queue heap initialize */
 311         pool->num_free = num;
 312         pool->num_alloc = 0;
 313         pool->base = base;
 314         LIST_INIT(&pool->alloc_list);
 315         LIST_INIT(&pool->free_list);
 316
 317         /* Initialize element  */
 318         entry->base = 0;
 319         entry->len = num;
 320
 321         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 322         return 0;
 323 }
 324
 325 static int
 326 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 327                    uint16_t num)
 328 {
 329         struct pool_entry *entry, *valid_entry;
 330
 331         if (!pool || !num) {
 332                 PMD_INIT_LOG(ERR, "Invalid parameter");
 333                 return -EINVAL;
 334         }
 335
 336         if (pool->num_free < num) {
 337                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 338                              num, pool->num_free);
 339                 return -ENOMEM;
 340         }
 341
 342         valid_entry = NULL;
 343         /* Lookup  in free list and find most fit one */
 344         LIST_FOREACH(entry, &pool->free_list, next) {
 345                 if (entry->len >= num) {
 346                         /* Find best one */
 347                         if (entry->len == num) {
 348                                 valid_entry = entry;
 349                                 break;
 350                         }
 351                         if (!valid_entry ||
 352                             valid_entry->len > entry->len)
 353                                 valid_entry = entry;
 354                 }
 355         }
 356
 357         /* Not find one to satisfy the request, return */
 358         if (!valid_entry) {
 359                 PMD_INIT_LOG(ERR, "No valid entry found");
 360                 return -ENOMEM;
 361         }
 362         /**
 363          * The entry have equal queue number as requested,
 364          * remove it from alloc_list.
 365          */
 366         if (valid_entry->len == num) {
 367                 LIST_REMOVE(valid_entry, next);
 368         } else {
 369                 /**
 370                  * The entry have more numbers than requested,
 371                  * create a new entry for alloc_list and minus its
 372                  * queue base and number in free_list.
 373                  */
 374                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 375                 if (!entry) {
 376                         PMD_INIT_LOG(ERR,
 377                                      "Failed to allocate memory for "
 378                                      "resource pool");
 379                         return -ENOMEM;
 380                 }
 381                 entry->base = valid_entry->base;
 382                 entry->len = num;
 383                 valid_entry->base += num;
 384                 valid_entry->len -= num;
 385                 valid_entry = entry;
 386         }
 387
 388         /* Insert it into alloc list, not sorted */
 389         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 390
 391         pool->num_free -= valid_entry->len;
 392         pool->num_alloc += valid_entry->len;
 393
 394         return valid_entry->base + pool->base;
 395 }
 396
 397 static void
 398 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 399 {
 400         struct pool_entry *entry, *next_entry;
 401
 402         if (!pool)
 403                 return;
 404
 405         for (entry = LIST_FIRST(&pool->alloc_list);
 406              entry && (next_entry = LIST_NEXT(entry, next), 1);
 407              entry = next_entry) {
 408                 LIST_REMOVE(entry, next);
 409                 rte_free(entry);
 410         }
 411
 412         for (entry = LIST_FIRST(&pool->free_list);
 413              entry && (next_entry = LIST_NEXT(entry, next), 1);
 414              entry = next_entry) {
 415                 LIST_REMOVE(entry, next);
 416                 rte_free(entry);
 417         }
 418
 419         pool->num_free = 0;
 420         pool->num_alloc = 0;
 421         pool->base = 0;
 422         LIST_INIT(&pool->alloc_list);
 423         LIST_INIT(&pool->free_list);
 424 }
 425
 426 static void
 427 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 428 {
 429         /* Set VSI LUT selection */
 430         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 431                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 432         /* Set Hash scheme */
 433         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 434                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 435         /* enable TC */
 436         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 437 }
 438
 439 static enum ice_status
 440 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 441                                 struct ice_aqc_vsi_props *info,
 442                                 uint8_t enabled_tcmap)
 443 {
 444         uint16_t bsf, qp_idx;
 445
 446         /* default tc 0 now. Multi-TC supporting need to be done later.
 447          * Configure TC and queue mapping parameters, for enabled TC,
 448          * allocate qpnum_per_tc queues to this traffic.
 449          */
 450         if (enabled_tcmap != 0x01) {
 451                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 452                 return -ENOTSUP;
 453         }
 454
 455         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 456         bsf = rte_bsf32(vsi->nb_qps);
 457         /* Adjust the queue number to actual queues that can be applied */
 458         vsi->nb_qps = 0x1 << bsf;
 459
 460         qp_idx = 0;
 461         /* Set tc and queue mapping with VSI */
 462         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 463                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 464                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 465
 466         /* Associate queue number with VSI */
 467         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 468         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 469         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 470         info->valid_sections |=
 471                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 472         /* Set the info.ingress_table and info.egress_table
 473          * for UP translate table. Now just set it to 1:1 map by default
 474          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 475          */
 476 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 477         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 478         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 479         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 480         return 0;
 481 }
 482
 483 static int
 484 ice_init_mac_address(struct rte_eth_dev *dev)
 485 {
 486         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 487
 488         if (!is_unicast_ether_addr
 489                 ((struct ether_addr *)hw->port_info[0].mac.lan_addr)) {
 490                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 491                 return -EINVAL;
 492         }
 493
 494         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.lan_addr,
 495                         (struct ether_addr *)hw->port_info[0].mac.perm_addr);
 496
 497         dev->data->mac_addrs = rte_zmalloc(NULL, sizeof(struct ether_addr), 0);
 498         if (!dev->data->mac_addrs) {
 499                 PMD_INIT_LOG(ERR,
 500                              "Failed to allocate memory to store mac address");
 501                 return -ENOMEM;
 502         }
 503         /* store it to dev data */
 504         ether_addr_copy((struct ether_addr *)hw->port_info[0].mac.perm_addr,
 505                         &dev->data->mac_addrs[0]);
 506         return 0;
 507 }
 508
 509 /* Find out specific MAC filter */
 510 static struct ice_mac_filter *
 511 ice_find_mac_filter(struct ice_vsi *vsi, struct ether_addr *macaddr)
 512 {
 513         struct ice_mac_filter *f;
 514
 515         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 516                 if (is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 517                         return f;
 518         }
 519
 520         return NULL;
 521 }
 522
 523 static int
 524 ice_add_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 525 {
 526         struct ice_fltr_list_entry *m_list_itr = NULL;
 527         struct ice_mac_filter *f;
 528         struct LIST_HEAD_TYPE list_head;
 529         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 530         int ret = 0;
 531
 532         /* If it's added and configured, return */
 533         f = ice_find_mac_filter(vsi, mac_addr);
 534         if (f) {
 535                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 536                 return 0;
 537         }
 538
 539         INIT_LIST_HEAD(&list_head);
 540
 541         m_list_itr = (struct ice_fltr_list_entry *)
 542                 ice_malloc(hw, sizeof(*m_list_itr));
 543         if (!m_list_itr) {
 544                 ret = -ENOMEM;
 545                 goto DONE;
 546         }
 547         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 548                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 549         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 550         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 551         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 552         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 553         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 554
 555         LIST_ADD(&m_list_itr->list_entry, &list_head);
 556
 557         /* Add the mac */
 558         ret = ice_add_mac(hw, &list_head);
 559         if (ret != ICE_SUCCESS) {
 560                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 561                 ret = -EINVAL;
 562                 goto DONE;
 563         }
 564         /* Add the mac addr into mac list */
 565         f = rte_zmalloc(NULL, sizeof(*f), 0);
 566         if (!f) {
 567                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 568                 ret = -ENOMEM;
 569                 goto DONE;
 570         }
 571         rte_memcpy(&f->mac_info.mac_addr, mac_addr, ETH_ADDR_LEN);
 572         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 573         vsi->mac_num++;
 574
 575         ret = 0;
 576
 577 DONE:
 578         rte_free(m_list_itr);
 579         return ret;
 580 }
 581
 582 static int
 583 ice_remove_mac_filter(struct ice_vsi *vsi, struct ether_addr *mac_addr)
 584 {
 585         struct ice_fltr_list_entry *m_list_itr = NULL;
 586         struct ice_mac_filter *f;
 587         struct LIST_HEAD_TYPE list_head;
 588         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 589         int ret = 0;
 590
 591         /* Can't find it, return an error */
 592         f = ice_find_mac_filter(vsi, mac_addr);
 593         if (!f)
 594                 return -EINVAL;
 595
 596         INIT_LIST_HEAD(&list_head);
 597
 598         m_list_itr = (struct ice_fltr_list_entry *)
 599                 ice_malloc(hw, sizeof(*m_list_itr));
 600         if (!m_list_itr) {
 601                 ret = -ENOMEM;
 602                 goto DONE;
 603         }
 604         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 605                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 606         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 607         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 608         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 609         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 610         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 611
 612         LIST_ADD(&m_list_itr->list_entry, &list_head);
 613
 614         /* remove the mac filter */
 615         ret = ice_remove_mac(hw, &list_head);
 616         if (ret != ICE_SUCCESS) {
 617                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 618                 ret = -EINVAL;
 619                 goto DONE;
 620         }
 621
 622         /* Remove the mac addr from mac list */
 623         TAILQ_REMOVE(&vsi->mac_list, f, next);
 624         rte_free(f);
 625         vsi->mac_num--;
 626
 627         ret = 0;
 628 DONE:
 629         rte_free(m_list_itr);
 630         return ret;
 631 }
 632
 633 /* Find out specific VLAN filter */
 634 static struct ice_vlan_filter *
 635 ice_find_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 636 {
 637         struct ice_vlan_filter *f;
 638
 639         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 640                 if (vlan_id == f->vlan_info.vlan_id)
 641                         return f;
 642         }
 643
 644         return NULL;
 645 }
 646
 647 static int
 648 ice_add_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 649 {
 650         struct ice_fltr_list_entry *v_list_itr = NULL;
 651         struct ice_vlan_filter *f;
 652         struct LIST_HEAD_TYPE list_head;
 653         struct ice_hw *hw;
 654         int ret = 0;
 655
 656         if (!vsi || vlan_id > ETHER_MAX_VLAN_ID)
 657                 return -EINVAL;
 658
 659         hw = ICE_VSI_TO_HW(vsi);
 660
 661         /* If it's added and configured, return. */
 662         f = ice_find_vlan_filter(vsi, vlan_id);
 663         if (f) {
 664                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 665                 return 0;
 666         }
 667
 668         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 669                 return 0;
 670
 671         INIT_LIST_HEAD(&list_head);
 672
 673         v_list_itr = (struct ice_fltr_list_entry *)
 674                       ice_malloc(hw, sizeof(*v_list_itr));
 675         if (!v_list_itr) {
 676                 ret = -ENOMEM;
 677                 goto DONE;
 678         }
 679         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 680         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 681         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 682         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 683         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 684         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 685
 686         LIST_ADD(&v_list_itr->list_entry, &list_head);
 687
 688         /* Add the vlan */
 689         ret = ice_add_vlan(hw, &list_head);
 690         if (ret != ICE_SUCCESS) {
 691                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
 692                 ret = -EINVAL;
 693                 goto DONE;
 694         }
 695
 696         /* Add vlan into vlan list */
 697         f = rte_zmalloc(NULL, sizeof(*f), 0);
 698         if (!f) {
 699                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 700                 ret = -ENOMEM;
 701                 goto DONE;
 702         }
 703         f->vlan_info.vlan_id = vlan_id;
 704         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
 705         vsi->vlan_num++;
 706
 707         ret = 0;
 708
 709 DONE:
 710         rte_free(v_list_itr);
 711         return ret;
 712 }
 713
 714 static int
 715 ice_remove_vlan_filter(struct ice_vsi *vsi, uint16_t vlan_id)
 716 {
 717         struct ice_fltr_list_entry *v_list_itr = NULL;
 718         struct ice_vlan_filter *f;
 719         struct LIST_HEAD_TYPE list_head;
 720         struct ice_hw *hw;
 721         int ret = 0;
 722
 723         /**
 724          * Vlan 0 is the generic filter for untagged packets
 725          * and can't be removed.
 726          */
 727         if (!vsi || vlan_id == 0 || vlan_id > ETHER_MAX_VLAN_ID)
 728                 return -EINVAL;
 729
 730         hw = ICE_VSI_TO_HW(vsi);
 731
 732         /* Can't find it, return an error */
 733         f = ice_find_vlan_filter(vsi, vlan_id);
 734         if (!f)
 735                 return -EINVAL;
 736
 737         INIT_LIST_HEAD(&list_head);
 738
 739         v_list_itr = (struct ice_fltr_list_entry *)
 740                       ice_malloc(hw, sizeof(*v_list_itr));
 741         if (!v_list_itr) {
 742                 ret = -ENOMEM;
 743                 goto DONE;
 744         }
 745
 746         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan_id;
 747         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 748         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 749         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
 750         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
 751         v_list_itr->fltr_info.vsi_handle = vsi->idx;
 752
 753         LIST_ADD(&v_list_itr->list_entry, &list_head);
 754
 755         /* remove the vlan filter */
 756         ret = ice_remove_vlan(hw, &list_head);
 757         if (ret != ICE_SUCCESS) {
 758                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
 759                 ret = -EINVAL;
 760                 goto DONE;
 761         }
 762
 763         /* Remove the vlan id from vlan list */
 764         TAILQ_REMOVE(&vsi->vlan_list, f, next);
 765         rte_free(f);
 766         vsi->vlan_num--;
 767
 768         ret = 0;
 769 DONE:
 770         rte_free(v_list_itr);
 771         return ret;
 772 }
 773
 774 static int
 775 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
 776 {
 777         struct ice_mac_filter *m_f;
 778         struct ice_vlan_filter *v_f;
 779         int ret = 0;
 780
 781         if (!vsi || !vsi->mac_num)
 782                 return -EINVAL;
 783
 784         TAILQ_FOREACH(m_f, &vsi->mac_list, next) {
 785                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
 786                 if (ret != ICE_SUCCESS) {
 787                         ret = -EINVAL;
 788                         goto DONE;
 789                 }
 790         }
 791
 792         if (vsi->vlan_num == 0)
 793                 return 0;
 794
 795         TAILQ_FOREACH(v_f, &vsi->vlan_list, next) {
 796                 ret = ice_remove_vlan_filter(vsi, v_f->vlan_info.vlan_id);
 797                 if (ret != ICE_SUCCESS) {
 798                         ret = -EINVAL;
 799                         goto DONE;
 800                 }
 801         }
 802
 803 DONE:
 804         return ret;
 805 }
 806
 807 static int
 808 ice_vsi_config_qinq_insertion(struct ice_vsi *vsi, bool on)
 809 {
 810         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 811         struct ice_vsi_ctx ctxt;
 812         uint8_t qinq_flags;
 813         int ret = 0;
 814
 815         /* Check if it has been already on or off */
 816         if (vsi->info.valid_sections &
 817                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 818                 if (on) {
 819                         if ((vsi->info.outer_tag_flags &
 820                              ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST) ==
 821                             ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST)
 822                                 return 0; /* already on */
 823                 } else {
 824                         if (!(vsi->info.outer_tag_flags &
 825                               ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST))
 826                                 return 0; /* already off */
 827                 }
 828         }
 829
 830         if (on)
 831                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST;
 832         else
 833                 qinq_flags = 0;
 834         /* clear global insertion and use per packet insertion */
 835         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_INSERT);
 836         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_ACCEPT_HOST);
 837         vsi->info.outer_tag_flags |= qinq_flags;
 838         /* use default vlan type 0x8100 */
 839         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 840         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 841                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 842         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 843         ctxt.info.valid_sections =
 844                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 845         ctxt.vsi_num = vsi->vsi_id;
 846         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 847         if (ret) {
 848                 PMD_DRV_LOG(INFO,
 849                             "Update VSI failed to %s qinq stripping",
 850                             on ? "enable" : "disable");
 851                 return -EINVAL;
 852         }
 853
 854         vsi->info.valid_sections |=
 855                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 856
 857         return ret;
 858 }
 859
 860 static int
 861 ice_vsi_config_qinq_stripping(struct ice_vsi *vsi, bool on)
 862 {
 863         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 864         struct ice_vsi_ctx ctxt;
 865         uint8_t qinq_flags;
 866         int ret = 0;
 867
 868         /* Check if it has been already on or off */
 869         if (vsi->info.valid_sections &
 870                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID)) {
 871                 if (on) {
 872                         if ((vsi->info.outer_tag_flags &
 873                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 874                             ICE_AQ_VSI_OUTER_TAG_COPY)
 875                                 return 0; /* already on */
 876                 } else {
 877                         if ((vsi->info.outer_tag_flags &
 878                              ICE_AQ_VSI_OUTER_TAG_MODE_M) ==
 879                             ICE_AQ_VSI_OUTER_TAG_NOTHING)
 880                                 return 0; /* already off */
 881                 }
 882         }
 883
 884         if (on)
 885                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_COPY;
 886         else
 887                 qinq_flags = ICE_AQ_VSI_OUTER_TAG_NOTHING;
 888         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_MODE_M);
 889         vsi->info.outer_tag_flags |= qinq_flags;
 890         /* use default vlan type 0x8100 */
 891         vsi->info.outer_tag_flags &= ~(ICE_AQ_VSI_OUTER_TAG_TYPE_M);
 892         vsi->info.outer_tag_flags |= ICE_DFLT_OUTER_TAG_TYPE <<
 893                                      ICE_AQ_VSI_OUTER_TAG_TYPE_S;
 894         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
 895         ctxt.info.valid_sections =
 896                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 897         ctxt.vsi_num = vsi->vsi_id;
 898         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
 899         if (ret) {
 900                 PMD_DRV_LOG(INFO,
 901                             "Update VSI failed to %s qinq stripping",
 902                             on ? "enable" : "disable");
 903                 return -EINVAL;
 904         }
 905
 906         vsi->info.valid_sections |=
 907                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
 908
 909         return ret;
 910 }
 911
 912 static int
 913 ice_vsi_config_double_vlan(struct ice_vsi *vsi, int on)
 914 {
 915         int ret;
 916
 917         ret = ice_vsi_config_qinq_stripping(vsi, on);
 918         if (ret)
 919                 PMD_DRV_LOG(ERR, "Fail to set qinq stripping - %d", ret);
 920
 921         ret = ice_vsi_config_qinq_insertion(vsi, on);
 922         if (ret)
 923                 PMD_DRV_LOG(ERR, "Fail to set qinq insertion - %d", ret);
 924
 925         return ret;
 926 }
 927
 928 /* Enable IRQ0 */
 929 static void
 930 ice_pf_enable_irq0(struct ice_hw *hw)
 931 {
 932         /* reset the registers */
 933         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
 934         ICE_READ_REG(hw, PFINT_OICR);
 935
 936 #ifdef ICE_LSE_SPT
 937         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
 938                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
 939                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
 940
 941         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
 942                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
 943                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
 944                        PFINT_OICR_CTL_ITR_INDX_M) |
 945                       PFINT_OICR_CTL_CAUSE_ENA_M);
 946
 947         ICE_WRITE_REG(hw, PFINT_FW_CTL,
 948                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
 949                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
 950                        PFINT_FW_CTL_ITR_INDX_M) |
 951                       PFINT_FW_CTL_CAUSE_ENA_M);
 952 #else
 953         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
 954 #endif
 955
 956         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
 957                       GLINT_DYN_CTL_INTENA_M |
 958                       GLINT_DYN_CTL_CLEARPBA_M |
 959                       GLINT_DYN_CTL_ITR_INDX_M);
 960
 961         ice_flush(hw);
 962 }
 963
 964 /* Disable IRQ0 */
 965 static void
 966 ice_pf_disable_irq0(struct ice_hw *hw)
 967 {
 968         /* Disable all interrupt types */
 969         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
 970         ice_flush(hw);
 971 }
 972
 973 #ifdef ICE_LSE_SPT
 974 static void
 975 ice_handle_aq_msg(struct rte_eth_dev *dev)
 976 {
 977         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 978         struct ice_ctl_q_info *cq = &hw->adminq;
 979         struct ice_rq_event_info event;
 980         uint16_t pending, opcode;
 981         int ret;
 982
 983         event.buf_len = ICE_AQ_MAX_BUF_LEN;
 984         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
 985         if (!event.msg_buf) {
 986                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
 987                 return;
 988         }
 989
 990         pending = 1;
 991         while (pending) {
 992                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
 993
 994                 if (ret != ICE_SUCCESS) {
 995                         PMD_DRV_LOG(INFO,
 996                                     "Failed to read msg from AdminQ, "
 997                                     "adminq_err: %u",
 998                                     hw->adminq.sq_last_status);
 999                         break;
1000                 }
1001                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1002
1003                 switch (opcode) {
1004                 case ice_aqc_opc_get_link_status:
1005                         ret = ice_link_update(dev, 0);
1006                         if (!ret)
1007                                 _rte_eth_dev_callback_process
1008                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1009                         break;
1010                 default:
1011                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1012                                     opcode);
1013                         break;
1014                 }
1015         }
1016         rte_free(event.msg_buf);
1017 }
1018 #endif
1019
1020 /**
1021  * Interrupt handler triggered by NIC for handling
1022  * specific interrupt.
1023  *
1024  * @param handle
1025  *  Pointer to interrupt handle.
1026  * @param param
1027  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1028  *
1029  * @return
1030  *  void
1031  */
1032 static void
1033 ice_interrupt_handler(void *param)
1034 {
1035         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1036         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1037         uint32_t oicr;
1038         uint32_t reg;
1039         uint8_t pf_num;
1040         uint8_t event;
1041         uint16_t queue;
1042 #ifdef ICE_LSE_SPT
1043         uint32_t int_fw_ctl;
1044 #endif
1045
1046         /* Disable interrupt */
1047         ice_pf_disable_irq0(hw);
1048
1049         /* read out interrupt causes */
1050         oicr = ICE_READ_REG(hw, PFINT_OICR);
1051 #ifdef ICE_LSE_SPT
1052         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1053 #endif
1054
1055         /* No interrupt event indicated */
1056         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1057                 PMD_DRV_LOG(INFO, "No interrupt event");
1058                 goto done;
1059         }
1060
1061 #ifdef ICE_LSE_SPT
1062         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1063                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1064                 ice_handle_aq_msg(dev);
1065         }
1066 #else
1067         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1068                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1069                 ice_link_update(dev, 0);
1070         }
1071 #endif
1072
1073         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1074                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1075                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1076                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1077                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1078                                  GL_MDET_TX_PQM_PF_NUM_S;
1079                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1080                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1081                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1082                                 GL_MDET_TX_PQM_QNUM_S;
1083
1084                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1085                                     "%d by PQM on TX queue %d PF# %d",
1086                                     event, queue, pf_num);
1087                 }
1088
1089                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1090                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1091                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1092                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1093                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1094                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1095                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1096                                 GL_MDET_TX_TCLAN_QNUM_S;
1097
1098                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1099                                     "%d by TCLAN on TX queue %d PF# %d",
1100                                     event, queue, pf_num);
1101                 }
1102         }
1103 done:
1104         /* Enable interrupt */
1105         ice_pf_enable_irq0(hw);
1106         rte_intr_enable(dev->intr_handle);
1107 }
1108
1109 /*  Initialize SW parameters of PF */
1110 static int
1111 ice_pf_sw_init(struct rte_eth_dev *dev)
1112 {
1113         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1114         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1115
1116         if (ice_config_max_queue_pair_num(dev->device->devargs) > 0)
1117                 pf->lan_nb_qp_max =
1118                         ice_config_max_queue_pair_num(dev->device->devargs);
1119         else
1120                 pf->lan_nb_qp_max =
1121                         (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1122                                           hw->func_caps.common_cap.num_rxq);
1123
1124         pf->lan_nb_qps = pf->lan_nb_qp_max;
1125
1126         return 0;
1127 }
1128
1129 static struct ice_vsi *
1130 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1131 {
1132         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1133         struct ice_vsi *vsi = NULL;
1134         struct ice_vsi_ctx vsi_ctx;
1135         int ret;
1136         struct ether_addr broadcast = {
1137                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1138         struct ether_addr mac_addr;
1139         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1140         uint8_t tc_bitmap = 0x1;
1141
1142         /* hw->num_lports = 1 in NIC mode */
1143         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1144         if (!vsi)
1145                 return NULL;
1146
1147         vsi->idx = pf->next_vsi_idx;
1148         pf->next_vsi_idx++;
1149         vsi->type = type;
1150         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1151         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1152         vsi->vlan_anti_spoof_on = 0;
1153         vsi->vlan_filter_on = 1;
1154         TAILQ_INIT(&vsi->mac_list);
1155         TAILQ_INIT(&vsi->vlan_list);
1156
1157         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1158         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1159                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1160                         hw->func_caps.common_cap.rss_table_size;
1161         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1162
1163         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1164         /* base_queue in used in queue mapping of VSI add/update command.
1165          * Suppose vsi->base_queue is 0 now, don't consider SRIOV, VMDQ
1166          * cases in the first stage. Only Main VSI.
1167          */
1168         vsi->base_queue = 0;
1169         switch (type) {
1170         case ICE_VSI_PF:
1171                 vsi->nb_qps = pf->lan_nb_qps;
1172                 ice_vsi_config_default_rss(&vsi_ctx.info);
1173                 vsi_ctx.alloc_from_pool = true;
1174                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1175                 /* switch_id is queried by get_switch_config aq, which is done
1176                  * by ice_init_hw
1177                  */
1178                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1179                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1180                 /* Allow all untagged or tagged packets */
1181                 vsi_ctx.info.vlan_flags = ICE_AQ_VSI_VLAN_MODE_ALL;
1182                 vsi_ctx.info.vlan_flags |= ICE_AQ_VSI_VLAN_EMOD_NOTHING;
1183                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1184                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1185                 /* Enable VLAN/UP trip */
1186                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1187                                                       &vsi_ctx.info,
1188                                                       ICE_DEFAULT_TCMAP);
1189                 if (ret) {
1190                         PMD_INIT_LOG(ERR,
1191                                      "tc queue mapping with vsi failed, "
1192                                      "err = %d",
1193                                      ret);
1194                         goto fail_mem;
1195                 }
1196
1197                 break;
1198         default:
1199                 /* for other types of VSI */
1200                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1201                 goto fail_mem;
1202         }
1203
1204         /* VF has MSIX interrupt in VF range, don't allocate here */
1205         if (type == ICE_VSI_PF) {
1206                 ret = ice_res_pool_alloc(&pf->msix_pool,
1207                                          RTE_MIN(vsi->nb_qps,
1208                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1209                 if (ret < 0) {
1210                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1211                                      vsi->vsi_id, ret);
1212                 }
1213                 vsi->msix_intr = ret;
1214                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1215         } else {
1216                 vsi->msix_intr = 0;
1217                 vsi->nb_msix = 0;
1218         }
1219         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1220         if (ret != ICE_SUCCESS) {
1221                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1222                 goto fail_mem;
1223         }
1224         /* store vsi information is SW structure */
1225         vsi->vsi_id = vsi_ctx.vsi_num;
1226         vsi->info = vsi_ctx.info;
1227         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1228         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1229
1230         /* MAC configuration */
1231         rte_memcpy(pf->dev_addr.addr_bytes,
1232                    hw->port_info->mac.perm_addr,
1233                    ETH_ADDR_LEN);
1234
1235         rte_memcpy(&mac_addr, &pf->dev_addr, ETHER_ADDR_LEN);
1236         ret = ice_add_mac_filter(vsi, &mac_addr);
1237         if (ret != ICE_SUCCESS)
1238                 PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1239
1240         rte_memcpy(&mac_addr, &broadcast, ETHER_ADDR_LEN);
1241         ret = ice_add_mac_filter(vsi, &mac_addr);
1242         if (ret != ICE_SUCCESS)
1243                 PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1244
1245         /* At the beginning, only TC0. */
1246         /* What we need here is the maximam number of the TX queues.
1247          * Currently vsi->nb_qps means it.
1248          * Correct it if any change.
1249          */
1250         max_txqs[0] = vsi->nb_qps;
1251         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1252                               tc_bitmap, max_txqs);
1253         if (ret != ICE_SUCCESS)
1254                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1255
1256         return vsi;
1257 fail_mem:
1258         rte_free(vsi);
1259         pf->next_vsi_idx--;
1260         return NULL;
1261 }
1262
1263 static int
1264 ice_send_driver_ver(struct ice_hw *hw)
1265 {
1266         struct ice_driver_ver dv;
1267
1268         /* we don't have driver version use 0 for dummy */
1269         dv.major_ver = 0;
1270         dv.minor_ver = 0;
1271         dv.build_ver = 0;
1272         dv.subbuild_ver = 0;
1273         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1274
1275         return ice_aq_send_driver_ver(hw, &dv, NULL);
1276 }
1277
1278 static int
1279 ice_pf_setup(struct ice_pf *pf)
1280 {
1281         struct ice_vsi *vsi;
1282
1283         /* Clear all stats counters */
1284         pf->offset_loaded = FALSE;
1285         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1286         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1287         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1288         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1289
1290         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1291         if (!vsi) {
1292                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1293                 return -EINVAL;
1294         }
1295
1296         pf->main_vsi = vsi;
1297
1298         return 0;
1299 }
1300
1301 static int ice_load_pkg(struct rte_eth_dev *dev)
1302 {
1303         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1304         const char *pkg_file = ICE_DFLT_PKG_FILE;
1305         int err;
1306         uint8_t *buf;
1307         int buf_len;
1308         FILE *file;
1309         struct stat fstat;
1310
1311         file = fopen(pkg_file, "rb");
1312         if (!file)  {
1313                 PMD_INIT_LOG(ERR, "failed to open file: %s\n", pkg_file);
1314                 return -1;
1315         }
1316
1317         err = stat(pkg_file, &fstat);
1318         if (err) {
1319                 PMD_INIT_LOG(ERR, "failed to get file stats\n");
1320                 fclose(file);
1321                 return err;
1322         }
1323
1324         buf_len = fstat.st_size;
1325         buf = rte_malloc(NULL, buf_len, 0);
1326
1327         if (!buf) {
1328                 PMD_INIT_LOG(ERR, "failed to allocate buf of size %d for package\n",
1329                                 buf_len);
1330                 fclose(file);
1331                 return -1;
1332         }
1333
1334         err = fread(buf, buf_len, 1, file);
1335         if (err != 1) {
1336                 PMD_INIT_LOG(ERR, "failed to read package data\n");
1337                 fclose(file);
1338                 err = -1;
1339                 goto fail_exit;
1340         }
1341
1342         fclose(file);
1343
1344         err = ice_copy_and_init_pkg(hw, buf, buf_len);
1345         if (err) {
1346                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1347                 goto fail_exit;
1348         }
1349         err = ice_init_hw_tbls(hw);
1350         if (err) {
1351                 PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", err);
1352                 goto fail_init_tbls;
1353         }
1354
1355         return 0;
1356
1357 fail_init_tbls:
1358         rte_free(hw->pkg_copy);
1359 fail_exit:
1360         rte_free(buf);
1361         return err;
1362 }
1363
1364 static int
1365 ice_dev_init(struct rte_eth_dev *dev)
1366 {
1367         struct rte_pci_device *pci_dev;
1368         struct rte_intr_handle *intr_handle;
1369         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1370         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1371         struct ice_adapter *ad =
1372                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1373         struct ice_vsi *vsi;
1374         int ret;
1375
1376         dev->dev_ops = &ice_eth_dev_ops;
1377         dev->rx_pkt_burst = ice_recv_pkts;
1378         dev->tx_pkt_burst = ice_xmit_pkts;
1379         dev->tx_pkt_prepare = ice_prep_pkts;
1380
1381         ice_set_default_ptype_table(dev);
1382         pci_dev = RTE_DEV_TO_PCI(dev->device);
1383         intr_handle = &pci_dev->intr_handle;
1384
1385         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1386         pf->adapter->eth_dev = dev;
1387         pf->dev_data = dev->data;
1388         hw->back = pf->adapter;
1389         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
1390         hw->vendor_id = pci_dev->id.vendor_id;
1391         hw->device_id = pci_dev->id.device_id;
1392         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
1393         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
1394         hw->bus.device = pci_dev->addr.devid;
1395         hw->bus.func = pci_dev->addr.function;
1396
1397         ice_init_controlq_parameter(hw);
1398
1399         ret = ice_init_hw(hw);
1400         if (ret) {
1401                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
1402                 return -EINVAL;
1403         }
1404
1405         ret = ice_load_pkg(dev);
1406         if (ret) {
1407                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
1408                                 "Entering Safe Mode");
1409                 ad->is_safe_mode = 1;
1410         }
1411
1412         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
1413                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
1414                      hw->api_maj_ver, hw->api_min_ver);
1415
1416         ice_pf_sw_init(dev);
1417         ret = ice_init_mac_address(dev);
1418         if (ret) {
1419                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
1420                 goto err_init_mac;
1421         }
1422
1423         ret = ice_res_pool_init(&pf->msix_pool, 1,
1424                                 hw->func_caps.common_cap.num_msix_vectors - 1);
1425         if (ret) {
1426                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
1427                 goto err_msix_pool_init;
1428         }
1429
1430         ret = ice_pf_setup(pf);
1431         if (ret) {
1432                 PMD_INIT_LOG(ERR, "Failed to setup PF");
1433                 goto err_pf_setup;
1434         }
1435
1436         ret = ice_send_driver_ver(hw);
1437         if (ret) {
1438                 PMD_INIT_LOG(ERR, "Failed to send driver version");
1439                 goto err_pf_setup;
1440         }
1441
1442         vsi = pf->main_vsi;
1443
1444         /* Disable double vlan by default */
1445         ice_vsi_config_double_vlan(vsi, FALSE);
1446
1447         ret = ice_aq_stop_lldp(hw, TRUE, NULL);
1448         if (ret != ICE_SUCCESS)
1449                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
1450
1451         /* register callback func to eal lib */
1452         rte_intr_callback_register(intr_handle,
1453                                    ice_interrupt_handler, dev);
1454
1455         ice_pf_enable_irq0(hw);
1456
1457         /* enable uio intr after callback register */
1458         rte_intr_enable(intr_handle);
1459
1460         return 0;
1461
1462 err_pf_setup:
1463         ice_res_pool_destroy(&pf->msix_pool);
1464 err_msix_pool_init:
1465         rte_free(dev->data->mac_addrs);
1466 err_init_mac:
1467         ice_sched_cleanup_all(hw);
1468         rte_free(hw->port_info);
1469         ice_shutdown_all_ctrlq(hw);
1470
1471         return ret;
1472 }
1473
1474 static int
1475 ice_release_vsi(struct ice_vsi *vsi)
1476 {
1477         struct ice_hw *hw;
1478         struct ice_vsi_ctx vsi_ctx;
1479         enum ice_status ret;
1480
1481         if (!vsi)
1482                 return 0;
1483
1484         hw = ICE_VSI_TO_HW(vsi);
1485
1486         ice_remove_all_mac_vlan_filters(vsi);
1487
1488         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1489
1490         vsi_ctx.vsi_num = vsi->vsi_id;
1491         vsi_ctx.info = vsi->info;
1492         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
1493         if (ret != ICE_SUCCESS) {
1494                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
1495                 rte_free(vsi);
1496                 return -1;
1497         }
1498
1499         rte_free(vsi);
1500         return 0;
1501 }
1502
1503 static void
1504 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
1505 {
1506         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1507         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1508         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1509         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1510         uint16_t msix_intr, i;
1511
1512         /* disable interrupt and also clear all the exist config */
1513         for (i = 0; i < vsi->nb_qps; i++) {
1514                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1515                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1516                 rte_wmb();
1517         }
1518
1519         if (rte_intr_allow_others(intr_handle))
1520                 /* vfio-pci */
1521                 for (i = 0; i < vsi->nb_msix; i++) {
1522                         msix_intr = vsi->msix_intr + i;
1523                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1524                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1525                 }
1526         else
1527                 /* igb_uio */
1528                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1529 }
1530
1531 static void
1532 ice_dev_stop(struct rte_eth_dev *dev)
1533 {
1534         struct rte_eth_dev_data *data = dev->data;
1535         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1536         struct ice_vsi *main_vsi = pf->main_vsi;
1537         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1538         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1539         uint16_t i;
1540
1541         /* avoid stopping again */
1542         if (pf->adapter_stopped)
1543                 return;
1544
1545         /* stop and clear all Rx queues */
1546         for (i = 0; i < data->nb_rx_queues; i++)
1547                 ice_rx_queue_stop(dev, i);
1548
1549         /* stop and clear all Tx queues */
1550         for (i = 0; i < data->nb_tx_queues; i++)
1551                 ice_tx_queue_stop(dev, i);
1552
1553         /* disable all queue interrupts */
1554         ice_vsi_disable_queues_intr(main_vsi);
1555
1556         /* Clear all queues and release mbufs */
1557         ice_clear_queues(dev);
1558
1559         ice_dev_set_link_down(dev);
1560
1561         /* Clean datapath event and queue/vec mapping */
1562         rte_intr_efd_disable(intr_handle);
1563         if (intr_handle->intr_vec) {
1564                 rte_free(intr_handle->intr_vec);
1565                 intr_handle->intr_vec = NULL;
1566         }
1567
1568         pf->adapter_stopped = true;
1569 }
1570
1571 static void
1572 ice_dev_close(struct rte_eth_dev *dev)
1573 {
1574         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1575         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1576
1577         /* Since stop will make link down, then the link event will be
1578          * triggered, disable the irq firstly to avoid the port_infoe etc
1579          * resources deallocation causing the interrupt service thread
1580          * crash.
1581          */
1582         ice_pf_disable_irq0(hw);
1583
1584         ice_dev_stop(dev);
1585
1586         /* release all queue resource */
1587         ice_free_queues(dev);
1588
1589         ice_res_pool_destroy(&pf->msix_pool);
1590         ice_release_vsi(pf->main_vsi);
1591         ice_sched_cleanup_all(hw);
1592         rte_free(hw->port_info);
1593         hw->port_info = NULL;
1594         ice_shutdown_all_ctrlq(hw);
1595 }
1596
1597 static int
1598 ice_dev_uninit(struct rte_eth_dev *dev)
1599 {
1600         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
1601         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1602
1603         ice_dev_close(dev);
1604
1605         dev->dev_ops = NULL;
1606         dev->rx_pkt_burst = NULL;
1607         dev->tx_pkt_burst = NULL;
1608
1609         rte_free(dev->data->mac_addrs);
1610         dev->data->mac_addrs = NULL;
1611
1612         /* disable uio intr before callback unregister */
1613         rte_intr_disable(intr_handle);
1614
1615         /* unregister callback func from eal lib */
1616         rte_intr_callback_unregister(intr_handle,
1617                                      ice_interrupt_handler, dev);
1618
1619         return 0;
1620 }
1621
1622 static int
1623 ice_dev_configure(__rte_unused struct rte_eth_dev *dev)
1624 {
1625         struct ice_adapter *ad =
1626                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1627
1628         /* Initialize to TRUE. If any of Rx queues doesn't meet the
1629          * bulk allocation or vector Rx preconditions we will reset it.
1630          */
1631         ad->rx_bulk_alloc_allowed = true;
1632         ad->tx_simple_allowed = true;
1633
1634         return 0;
1635 }
1636
1637 static int ice_init_rss(struct ice_pf *pf)
1638 {
1639         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1640         struct ice_vsi *vsi = pf->main_vsi;
1641         struct rte_eth_dev *dev = pf->adapter->eth_dev;
1642         struct rte_eth_rss_conf *rss_conf;
1643         struct ice_aqc_get_set_rss_keys key;
1644         uint16_t i, nb_q;
1645         int ret = 0;
1646         bool is_safe_mode = pf->adapter->is_safe_mode;
1647
1648         rss_conf = &dev->data->dev_conf.rx_adv_conf.rss_conf;
1649         nb_q = dev->data->nb_rx_queues;
1650         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
1651         vsi->rss_lut_size = pf->hash_lut_size;
1652
1653         if (is_safe_mode) {
1654                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
1655                 return 0;
1656         }
1657
1658         if (!vsi->rss_key)
1659                 vsi->rss_key = rte_zmalloc(NULL,
1660                                            vsi->rss_key_size, 0);
1661         if (!vsi->rss_lut)
1662                 vsi->rss_lut = rte_zmalloc(NULL,
1663                                            vsi->rss_lut_size, 0);
1664
1665         /* configure RSS key */
1666         if (!rss_conf->rss_key) {
1667                 /* Calculate the default hash key */
1668                 for (i = 0; i <= vsi->rss_key_size; i++)
1669                         vsi->rss_key[i] = (uint8_t)rte_rand();
1670         } else {
1671                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
1672                            RTE_MIN(rss_conf->rss_key_len,
1673                                    vsi->rss_key_size));
1674         }
1675         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
1676         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
1677         if (ret)
1678                 return -EINVAL;
1679
1680         /* init RSS LUT table */
1681         for (i = 0; i < vsi->rss_lut_size; i++)
1682                 vsi->rss_lut[i] = i % nb_q;
1683
1684         ret = ice_aq_set_rss_lut(hw, vsi->idx,
1685                                  ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF,
1686                                  vsi->rss_lut, vsi->rss_lut_size);
1687         if (ret)
1688                 return -EINVAL;
1689
1690         /* configure RSS for IPv4 with input set IPv4 src/dst */
1691         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1692                               ICE_FLOW_SEG_HDR_IPV4);
1693         if (ret)
1694                 PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d", __func__, ret);
1695
1696         /* configure RSS for IPv6 with input set IPv6 src/dst */
1697         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1698                               ICE_FLOW_SEG_HDR_IPV6);
1699         if (ret)
1700                 PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d", __func__, ret);
1701
1702         /* configure RSS for tcp6 with input set IPv6 src/dst, TCP src/dst */
1703         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV6,
1704                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6);
1705         if (ret)
1706                 PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d", __func__, ret);
1707
1708         /* configure RSS for udp6 with input set IPv6 src/dst, UDP src/dst */
1709         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV6,
1710                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6);
1711         if (ret)
1712                 PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d", __func__, ret);
1713
1714         /* configure RSS for sctp6 with input set IPv6 src/dst */
1715         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV6,
1716                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6);
1717         if (ret)
1718                 PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
1719                                 __func__, ret);
1720
1721         /* configure RSS for tcp4 with input set IP src/dst, TCP src/dst */
1722         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_TCP_IPV4,
1723                               ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4);
1724         if (ret)
1725                 PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d", __func__, ret);
1726
1727         /* configure RSS for udp4 with input set IP src/dst, UDP src/dst */
1728         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_HASH_UDP_IPV4,
1729                               ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4);
1730         if (ret)
1731                 PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d", __func__, ret);
1732
1733         /* configure RSS for sctp4 with input set IP src/dst */
1734         ret = ice_add_rss_cfg(hw, vsi->idx, ICE_FLOW_HASH_IPV4,
1735                               ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4);
1736         if (ret)
1737                 PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
1738                                 __func__, ret);
1739
1740         return 0;
1741 }
1742
1743 static void
1744 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
1745                        int base_queue, int nb_queue)
1746 {
1747         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1748         uint32_t val, val_tx;
1749         int i;
1750
1751         for (i = 0; i < nb_queue; i++) {
1752                 /*do actual bind*/
1753                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
1754                       (0 < QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
1755                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
1756                          (0 < QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
1757
1758                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
1759                             base_queue + i, msix_vect);
1760                 /* set ITR0 value */
1761                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x10);
1762                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
1763                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
1764         }
1765 }
1766
1767 static void
1768 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
1769 {
1770         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1771         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1772         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1773         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1774         uint16_t msix_vect = vsi->msix_intr;
1775         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
1776         uint16_t queue_idx = 0;
1777         int record = 0;
1778         int i;
1779
1780         /* clear Rx/Tx queue interrupt */
1781         for (i = 0; i < vsi->nb_used_qps; i++) {
1782                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
1783                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
1784         }
1785
1786         /* PF bind interrupt */
1787         if (rte_intr_dp_is_en(intr_handle)) {
1788                 queue_idx = 0;
1789                 record = 1;
1790         }
1791
1792         for (i = 0; i < vsi->nb_used_qps; i++) {
1793                 if (nb_msix <= 1) {
1794                         if (!rte_intr_allow_others(intr_handle))
1795                                 msix_vect = ICE_MISC_VEC_ID;
1796
1797                         /* uio mapping all queue to one msix_vect */
1798                         __vsi_queues_bind_intr(vsi, msix_vect,
1799                                                vsi->base_queue + i,
1800                                                vsi->nb_used_qps - i);
1801
1802                         for (; !!record && i < vsi->nb_used_qps; i++)
1803                                 intr_handle->intr_vec[queue_idx + i] =
1804                                         msix_vect;
1805                         break;
1806                 }
1807
1808                 /* vfio 1:1 queue/msix_vect mapping */
1809                 __vsi_queues_bind_intr(vsi, msix_vect,
1810                                        vsi->base_queue + i, 1);
1811
1812                 if (!!record)
1813                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
1814
1815                 msix_vect++;
1816                 nb_msix--;
1817         }
1818 }
1819
1820 static void
1821 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
1822 {
1823         struct rte_eth_dev *dev = vsi->adapter->eth_dev;
1824         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1825         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1826         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1827         uint16_t msix_intr, i;
1828
1829         if (rte_intr_allow_others(intr_handle))
1830                 for (i = 0; i < vsi->nb_used_qps; i++) {
1831                         msix_intr = vsi->msix_intr + i;
1832                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
1833                                       GLINT_DYN_CTL_INTENA_M |
1834                                       GLINT_DYN_CTL_CLEARPBA_M |
1835                                       GLINT_DYN_CTL_ITR_INDX_M |
1836                                       GLINT_DYN_CTL_WB_ON_ITR_M);
1837                 }
1838         else
1839                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1840                               GLINT_DYN_CTL_INTENA_M |
1841                               GLINT_DYN_CTL_CLEARPBA_M |
1842                               GLINT_DYN_CTL_ITR_INDX_M |
1843                               GLINT_DYN_CTL_WB_ON_ITR_M);
1844 }
1845
1846 static int
1847 ice_rxq_intr_setup(struct rte_eth_dev *dev)
1848 {
1849         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1850         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
1851         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
1852         struct ice_vsi *vsi = pf->main_vsi;
1853         uint32_t intr_vector = 0;
1854
1855         rte_intr_disable(intr_handle);
1856
1857         /* check and configure queue intr-vector mapping */
1858         if ((rte_intr_cap_multiple(intr_handle) ||
1859              !RTE_ETH_DEV_SRIOV(dev).active) &&
1860             dev->data->dev_conf.intr_conf.rxq != 0) {
1861                 intr_vector = dev->data->nb_rx_queues;
1862                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
1863                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
1864                                     ICE_MAX_INTR_QUEUE_NUM);
1865                         return -ENOTSUP;
1866                 }
1867                 if (rte_intr_efd_enable(intr_handle, intr_vector))
1868                         return -1;
1869         }
1870
1871         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
1872                 intr_handle->intr_vec =
1873                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
1874                             0);
1875                 if (!intr_handle->intr_vec) {
1876                         PMD_DRV_LOG(ERR,
1877                                     "Failed to allocate %d rx_queues intr_vec",
1878                                     dev->data->nb_rx_queues);
1879                         return -ENOMEM;
1880                 }
1881         }
1882
1883         /* Map queues with MSIX interrupt */
1884         vsi->nb_used_qps = dev->data->nb_rx_queues;
1885         ice_vsi_queues_bind_intr(vsi);
1886
1887         /* Enable interrupts for all the queues */
1888         ice_vsi_enable_queues_intr(vsi);
1889
1890         rte_intr_enable(intr_handle);
1891
1892         return 0;
1893 }
1894
1895 static int
1896 ice_dev_start(struct rte_eth_dev *dev)
1897 {
1898         struct rte_eth_dev_data *data = dev->data;
1899         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1900         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1901         struct ice_vsi *vsi = pf->main_vsi;
1902         uint16_t nb_rxq = 0;
1903         uint16_t nb_txq, i;
1904         int mask, ret;
1905
1906         /* program Tx queues' context in hardware */
1907         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
1908                 ret = ice_tx_queue_start(dev, nb_txq);
1909                 if (ret) {
1910                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
1911                         goto tx_err;
1912                 }
1913         }
1914
1915         /* program Rx queues' context in hardware*/
1916         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
1917                 ret = ice_rx_queue_start(dev, nb_rxq);
1918                 if (ret) {
1919                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
1920                         goto rx_err;
1921                 }
1922         }
1923
1924         ret = ice_init_rss(pf);
1925         if (ret) {
1926                 PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
1927                 goto rx_err;
1928         }
1929
1930         ice_set_rx_function(dev);
1931         ice_set_tx_function(dev);
1932
1933         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
1934                         ETH_VLAN_EXTEND_MASK;
1935         ret = ice_vlan_offload_set(dev, mask);
1936         if (ret) {
1937                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
1938                 goto rx_err;
1939         }
1940
1941         /* enable Rx interrput and mapping Rx queue to interrupt vector */
1942         if (ice_rxq_intr_setup(dev))
1943                 return -EIO;
1944
1945         /* Enable receiving broadcast packets and transmitting packets */
1946         ret = ice_set_vsi_promisc(hw, vsi->idx,
1947                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
1948                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
1949                                   0);
1950         if (ret != ICE_SUCCESS)
1951                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
1952
1953         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
1954                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
1955                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
1956                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
1957                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
1958                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
1959                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
1960                                      NULL);
1961         if (ret != ICE_SUCCESS)
1962                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
1963
1964         ice_dev_set_link_up(dev);
1965
1966         /* Call get_link_info aq commond to enable/disable LSE */
1967         ice_link_update(dev, 0);
1968
1969         pf->adapter_stopped = false;
1970
1971         return 0;
1972
1973         /* stop the started queues if failed to start all queues */
1974 rx_err:
1975         for (i = 0; i < nb_rxq; i++)
1976                 ice_rx_queue_stop(dev, i);
1977 tx_err:
1978         for (i = 0; i < nb_txq; i++)
1979                 ice_tx_queue_stop(dev, i);
1980
1981         return -EIO;
1982 }
1983
1984 static int
1985 ice_dev_reset(struct rte_eth_dev *dev)
1986 {
1987         int ret;
1988
1989         if (dev->data->sriov.active)
1990                 return -ENOTSUP;
1991
1992         ret = ice_dev_uninit(dev);
1993         if (ret) {
1994                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
1995                 return -ENXIO;
1996         }
1997
1998         ret = ice_dev_init(dev);
1999         if (ret) {
2000                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
2001                 return -ENXIO;
2002         }
2003
2004         return 0;
2005 }
2006
2007 static void
2008 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
2009 {
2010         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2011         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2012         struct ice_vsi *vsi = pf->main_vsi;
2013         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
2014         bool is_safe_mode = pf->adapter->is_safe_mode;
2015         u64 phy_type_low;
2016         u64 phy_type_high;
2017
2018         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
2019         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
2020         dev_info->max_rx_queues = vsi->nb_qps;
2021         dev_info->max_tx_queues = vsi->nb_qps;
2022         dev_info->max_mac_addrs = vsi->max_macaddrs;
2023         dev_info->max_vfs = pci_dev->max_vfs;
2024         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
2025         dev_info->min_mtu = ETHER_MIN_MTU;
2026
2027         dev_info->rx_offload_capa =
2028                 DEV_RX_OFFLOAD_VLAN_STRIP |
2029                 DEV_RX_OFFLOAD_JUMBO_FRAME |
2030                 DEV_RX_OFFLOAD_KEEP_CRC |
2031                 DEV_RX_OFFLOAD_SCATTER |
2032                 DEV_RX_OFFLOAD_VLAN_FILTER;
2033         dev_info->tx_offload_capa =
2034                 DEV_TX_OFFLOAD_VLAN_INSERT |
2035                 DEV_TX_OFFLOAD_TCP_TSO |
2036                 DEV_TX_OFFLOAD_MULTI_SEGS |
2037                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
2038         dev_info->flow_type_rss_offloads = 0;
2039
2040         if (!is_safe_mode) {
2041                 dev_info->rx_offload_capa |=
2042                         DEV_RX_OFFLOAD_IPV4_CKSUM |
2043                         DEV_RX_OFFLOAD_UDP_CKSUM |
2044                         DEV_RX_OFFLOAD_TCP_CKSUM |
2045                         DEV_RX_OFFLOAD_QINQ_STRIP |
2046                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
2047                         DEV_RX_OFFLOAD_VLAN_EXTEND;
2048                 dev_info->tx_offload_capa |=
2049                         DEV_TX_OFFLOAD_QINQ_INSERT |
2050                         DEV_TX_OFFLOAD_IPV4_CKSUM |
2051                         DEV_TX_OFFLOAD_UDP_CKSUM |
2052                         DEV_TX_OFFLOAD_TCP_CKSUM |
2053                         DEV_TX_OFFLOAD_SCTP_CKSUM |
2054                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM;
2055                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
2056         }
2057
2058         dev_info->rx_queue_offload_capa = 0;
2059         dev_info->tx_queue_offload_capa = 0;
2060
2061         dev_info->reta_size = pf->hash_lut_size;
2062         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2063
2064         dev_info->default_rxconf = (struct rte_eth_rxconf) {
2065                 .rx_thresh = {
2066                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
2067                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
2068                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
2069                 },
2070                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
2071                 .rx_drop_en = 0,
2072                 .offloads = 0,
2073         };
2074
2075         dev_info->default_txconf = (struct rte_eth_txconf) {
2076                 .tx_thresh = {
2077                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
2078                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
2079                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
2080                 },
2081                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
2082                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
2083                 .offloads = 0,
2084         };
2085
2086         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
2087                 .nb_max = ICE_MAX_RING_DESC,
2088                 .nb_min = ICE_MIN_RING_DESC,
2089                 .nb_align = ICE_ALIGN_RING_DESC,
2090         };
2091
2092         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
2093                 .nb_max = ICE_MAX_RING_DESC,
2094                 .nb_min = ICE_MIN_RING_DESC,
2095                 .nb_align = ICE_ALIGN_RING_DESC,
2096         };
2097
2098         dev_info->speed_capa = ETH_LINK_SPEED_10M |
2099                                ETH_LINK_SPEED_100M |
2100                                ETH_LINK_SPEED_1G |
2101                                ETH_LINK_SPEED_2_5G |
2102                                ETH_LINK_SPEED_5G |
2103                                ETH_LINK_SPEED_10G |
2104                                ETH_LINK_SPEED_20G |
2105                                ETH_LINK_SPEED_25G;
2106
2107         phy_type_low = hw->port_info->phy.phy_type_low;
2108         phy_type_high = hw->port_info->phy.phy_type_high;
2109
2110         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
2111                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
2112
2113         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
2114                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
2115                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
2116
2117         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
2118         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
2119
2120         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
2121         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
2122         dev_info->default_rxportconf.nb_queues = 1;
2123         dev_info->default_txportconf.nb_queues = 1;
2124         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
2125         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
2126 }
2127
2128 static inline int
2129 ice_atomic_read_link_status(struct rte_eth_dev *dev,
2130                             struct rte_eth_link *link)
2131 {
2132         struct rte_eth_link *dst = link;
2133         struct rte_eth_link *src = &dev->data->dev_link;
2134
2135         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2136                                 *(uint64_t *)src) == 0)
2137                 return -1;
2138
2139         return 0;
2140 }
2141
2142 static inline int
2143 ice_atomic_write_link_status(struct rte_eth_dev *dev,
2144                              struct rte_eth_link *link)
2145 {
2146         struct rte_eth_link *dst = &dev->data->dev_link;
2147         struct rte_eth_link *src = link;
2148
2149         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
2150                                 *(uint64_t *)src) == 0)
2151                 return -1;
2152
2153         return 0;
2154 }
2155
2156 static int
2157 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
2158 {
2159 #define CHECK_INTERVAL 100  /* 100ms */
2160 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
2161         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2162         struct ice_link_status link_status;
2163         struct rte_eth_link link, old;
2164         int status;
2165         unsigned int rep_cnt = MAX_REPEAT_TIME;
2166         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
2167
2168         memset(&link, 0, sizeof(link));
2169         memset(&old, 0, sizeof(old));
2170         memset(&link_status, 0, sizeof(link_status));
2171         ice_atomic_read_link_status(dev, &old);
2172
2173         do {
2174                 /* Get link status information from hardware */
2175                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
2176                                               &link_status, NULL);
2177                 if (status != ICE_SUCCESS) {
2178                         link.link_speed = ETH_SPEED_NUM_100M;
2179                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2180                         PMD_DRV_LOG(ERR, "Failed to get link info");
2181                         goto out;
2182                 }
2183
2184                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
2185                 if (!wait_to_complete || link.link_status)
2186                         break;
2187
2188                 rte_delay_ms(CHECK_INTERVAL);
2189         } while (--rep_cnt);
2190
2191         if (!link.link_status)
2192                 goto out;
2193
2194         /* Full-duplex operation at all supported speeds */
2195         link.link_duplex = ETH_LINK_FULL_DUPLEX;
2196
2197         /* Parse the link status */
2198         switch (link_status.link_speed) {
2199         case ICE_AQ_LINK_SPEED_10MB:
2200                 link.link_speed = ETH_SPEED_NUM_10M;
2201                 break;
2202         case ICE_AQ_LINK_SPEED_100MB:
2203                 link.link_speed = ETH_SPEED_NUM_100M;
2204                 break;
2205         case ICE_AQ_LINK_SPEED_1000MB:
2206                 link.link_speed = ETH_SPEED_NUM_1G;
2207                 break;
2208         case ICE_AQ_LINK_SPEED_2500MB:
2209                 link.link_speed = ETH_SPEED_NUM_2_5G;
2210                 break;
2211         case ICE_AQ_LINK_SPEED_5GB:
2212                 link.link_speed = ETH_SPEED_NUM_5G;
2213                 break;
2214         case ICE_AQ_LINK_SPEED_10GB:
2215                 link.link_speed = ETH_SPEED_NUM_10G;
2216                 break;
2217         case ICE_AQ_LINK_SPEED_20GB:
2218                 link.link_speed = ETH_SPEED_NUM_20G;
2219                 break;
2220         case ICE_AQ_LINK_SPEED_25GB:
2221                 link.link_speed = ETH_SPEED_NUM_25G;
2222                 break;
2223         case ICE_AQ_LINK_SPEED_40GB:
2224                 link.link_speed = ETH_SPEED_NUM_40G;
2225                 break;
2226         case ICE_AQ_LINK_SPEED_50GB:
2227                 link.link_speed = ETH_SPEED_NUM_50G;
2228                 break;
2229         case ICE_AQ_LINK_SPEED_100GB:
2230                 link.link_speed = ETH_SPEED_NUM_100G;
2231                 break;
2232         case ICE_AQ_LINK_SPEED_UNKNOWN:
2233         default:
2234                 PMD_DRV_LOG(ERR, "Unknown link speed");
2235                 link.link_speed = ETH_SPEED_NUM_NONE;
2236                 break;
2237         }
2238
2239         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
2240                               ETH_LINK_SPEED_FIXED);
2241
2242 out:
2243         ice_atomic_write_link_status(dev, &link);
2244         if (link.link_status == old.link_status)
2245                 return -1;
2246
2247         return 0;
2248 }
2249
2250 /* Force the physical link state by getting the current PHY capabilities from
2251  * hardware and setting the PHY config based on the determined capabilities. If
2252  * link changes, link event will be triggered because both the Enable Automatic
2253  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
2254  */
2255 static enum ice_status
2256 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
2257 {
2258         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
2259         struct ice_aqc_get_phy_caps_data *pcaps;
2260         struct ice_port_info *pi;
2261         enum ice_status status;
2262
2263         if (!hw || !hw->port_info)
2264                 return ICE_ERR_PARAM;
2265
2266         pi = hw->port_info;
2267
2268         pcaps = (struct ice_aqc_get_phy_caps_data *)
2269                 ice_malloc(hw, sizeof(*pcaps));
2270         if (!pcaps)
2271                 return ICE_ERR_NO_MEMORY;
2272
2273         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_SW_CFG, pcaps,
2274                                      NULL);
2275         if (status)
2276                 goto out;
2277
2278         /* No change in link */
2279         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
2280             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
2281                 goto out;
2282
2283         cfg.phy_type_low = pcaps->phy_type_low;
2284         cfg.phy_type_high = pcaps->phy_type_high;
2285         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
2286         cfg.low_power_ctrl = pcaps->low_power_ctrl;
2287         cfg.eee_cap = pcaps->eee_cap;
2288         cfg.eeer_value = pcaps->eeer_value;
2289         cfg.link_fec_opt = pcaps->link_fec_options;
2290         if (link_up)
2291                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
2292         else
2293                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
2294
2295         status = ice_aq_set_phy_cfg(hw, pi->lport, &cfg, NULL);
2296
2297 out:
2298         ice_free(hw, pcaps);
2299         return status;
2300 }
2301
2302 static int
2303 ice_dev_set_link_up(struct rte_eth_dev *dev)
2304 {
2305         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2306
2307         return ice_force_phys_link_state(hw, true);
2308 }
2309
2310 static int
2311 ice_dev_set_link_down(struct rte_eth_dev *dev)
2312 {
2313         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2314
2315         return ice_force_phys_link_state(hw, false);
2316 }
2317
2318 static int
2319 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
2320 {
2321         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2322         struct rte_eth_dev_data *dev_data = pf->dev_data;
2323         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
2324
2325         /* check if mtu is within the allowed range */
2326         if (mtu < ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
2327                 return -EINVAL;
2328
2329         /* mtu setting is forbidden if port is start */
2330         if (dev_data->dev_started) {
2331                 PMD_DRV_LOG(ERR,
2332                             "port %d must be stopped before configuration",
2333                             dev_data->port_id);
2334                 return -EBUSY;
2335         }
2336
2337         if (frame_size > ETHER_MAX_LEN)
2338                 dev_data->dev_conf.rxmode.offloads |=
2339                         DEV_RX_OFFLOAD_JUMBO_FRAME;
2340         else
2341                 dev_data->dev_conf.rxmode.offloads &=
2342                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
2343
2344         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
2345
2346         return 0;
2347 }
2348
2349 static int ice_macaddr_set(struct rte_eth_dev *dev,
2350                            struct ether_addr *mac_addr)
2351 {
2352         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2353         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2354         struct ice_vsi *vsi = pf->main_vsi;
2355         struct ice_mac_filter *f;
2356         uint8_t flags = 0;
2357         int ret;
2358
2359         if (!is_valid_assigned_ether_addr(mac_addr)) {
2360                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
2361                 return -EINVAL;
2362         }
2363
2364         TAILQ_FOREACH(f, &vsi->mac_list, next) {
2365                 if (is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
2366                         break;
2367         }
2368
2369         if (!f) {
2370                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
2371                 return -EIO;
2372         }
2373
2374         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
2375         if (ret != ICE_SUCCESS) {
2376                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
2377                 return -EIO;
2378         }
2379         ret = ice_add_mac_filter(vsi, mac_addr);
2380         if (ret != ICE_SUCCESS) {
2381                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
2382                 return -EIO;
2383         }
2384         memcpy(&pf->dev_addr, mac_addr, ETH_ADDR_LEN);
2385
2386         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
2387         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
2388         if (ret != ICE_SUCCESS)
2389                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
2390
2391         return 0;
2392 }
2393
2394 /* Add a MAC address, and update filters */
2395 static int
2396 ice_macaddr_add(struct rte_eth_dev *dev,
2397                 struct ether_addr *mac_addr,
2398                 __rte_unused uint32_t index,
2399                 __rte_unused uint32_t pool)
2400 {
2401         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2402         struct ice_vsi *vsi = pf->main_vsi;
2403         int ret;
2404
2405         ret = ice_add_mac_filter(vsi, mac_addr);
2406         if (ret != ICE_SUCCESS) {
2407                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
2408                 return -EINVAL;
2409         }
2410
2411         return ICE_SUCCESS;
2412 }
2413
2414 /* Remove a MAC address, and update filters */
2415 static void
2416 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
2417 {
2418         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2419         struct ice_vsi *vsi = pf->main_vsi;
2420         struct rte_eth_dev_data *data = dev->data;
2421         struct ether_addr *macaddr;
2422         int ret;
2423
2424         macaddr = &data->mac_addrs[index];
2425         ret = ice_remove_mac_filter(vsi, macaddr);
2426         if (ret) {
2427                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
2428                 return;
2429         }
2430 }
2431
2432 static int
2433 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
2434 {
2435         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2436         struct ice_vsi *vsi = pf->main_vsi;
2437         int ret;
2438
2439         PMD_INIT_FUNC_TRACE();
2440
2441         if (on) {
2442                 ret = ice_add_vlan_filter(vsi, vlan_id);
2443                 if (ret < 0) {
2444                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
2445                         return -EINVAL;
2446                 }
2447         } else {
2448                 ret = ice_remove_vlan_filter(vsi, vlan_id);
2449                 if (ret < 0) {
2450                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
2451                         return -EINVAL;
2452                 }
2453         }
2454
2455         return 0;
2456 }
2457
2458 /* Configure vlan filter on or off */
2459 static int
2460 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
2461 {
2462         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2463         struct ice_vsi_ctx ctxt;
2464         uint8_t sec_flags, sw_flags2;
2465         int ret = 0;
2466
2467         sec_flags = ICE_AQ_VSI_SEC_TX_VLAN_PRUNE_ENA <<
2468                     ICE_AQ_VSI_SEC_TX_PRUNE_ENA_S;
2469         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
2470
2471         if (on) {
2472                 vsi->info.sec_flags |= sec_flags;
2473                 vsi->info.sw_flags2 |= sw_flags2;
2474         } else {
2475                 vsi->info.sec_flags &= ~sec_flags;
2476                 vsi->info.sw_flags2 &= ~sw_flags2;
2477         }
2478         vsi->info.sw_id = hw->port_info->sw_id;
2479         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2480         ctxt.info.valid_sections =
2481                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2482                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
2483         ctxt.vsi_num = vsi->vsi_id;
2484
2485         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2486         if (ret) {
2487                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
2488                             on ? "enable" : "disable");
2489                 return -EINVAL;
2490         } else {
2491                 vsi->info.valid_sections |=
2492                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
2493                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
2494         }
2495
2496         /* consist with other drivers, allow untagged packet when vlan filter on */
2497         if (on)
2498                 ret = ice_add_vlan_filter(vsi, 0);
2499         else
2500                 ret = ice_remove_vlan_filter(vsi, 0);
2501
2502         return 0;
2503 }
2504
2505 static int
2506 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool on)
2507 {
2508         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2509         struct ice_vsi_ctx ctxt;
2510         uint8_t vlan_flags;
2511         int ret = 0;
2512
2513         /* Check if it has been already on or off */
2514         if (vsi->info.valid_sections &
2515                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID)) {
2516                 if (on) {
2517                         if ((vsi->info.vlan_flags &
2518                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2519                             ICE_AQ_VSI_VLAN_EMOD_STR_BOTH)
2520                                 return 0; /* already on */
2521                 } else {
2522                         if ((vsi->info.vlan_flags &
2523                              ICE_AQ_VSI_VLAN_EMOD_M) ==
2524                             ICE_AQ_VSI_VLAN_EMOD_NOTHING)
2525                                 return 0; /* already off */
2526                 }
2527         }
2528
2529         if (on)
2530                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_STR_BOTH;
2531         else
2532                 vlan_flags = ICE_AQ_VSI_VLAN_EMOD_NOTHING;
2533         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_VLAN_EMOD_M);
2534         vsi->info.vlan_flags |= vlan_flags;
2535         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
2536         ctxt.info.valid_sections =
2537                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2538         ctxt.vsi_num = vsi->vsi_id;
2539         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
2540         if (ret) {
2541                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan stripping",
2542                             on ? "enable" : "disable");
2543                 return -EINVAL;
2544         }
2545
2546         vsi->info.valid_sections |=
2547                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
2548
2549         return ret;
2550 }
2551
2552 static int
2553 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
2554 {
2555         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2556         struct ice_vsi *vsi = pf->main_vsi;
2557         struct rte_eth_rxmode *rxmode;
2558
2559         rxmode = &dev->data->dev_conf.rxmode;
2560         if (mask & ETH_VLAN_FILTER_MASK) {
2561                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
2562                         ice_vsi_config_vlan_filter(vsi, TRUE);
2563                 else
2564                         ice_vsi_config_vlan_filter(vsi, FALSE);
2565         }
2566
2567         if (mask & ETH_VLAN_STRIP_MASK) {
2568                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
2569                         ice_vsi_config_vlan_stripping(vsi, TRUE);
2570                 else
2571                         ice_vsi_config_vlan_stripping(vsi, FALSE);
2572         }
2573
2574         if (mask & ETH_VLAN_EXTEND_MASK) {
2575                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_EXTEND)
2576                         ice_vsi_config_double_vlan(vsi, TRUE);
2577                 else
2578                         ice_vsi_config_double_vlan(vsi, FALSE);
2579         }
2580
2581         return 0;
2582 }
2583
2584 static int
2585 ice_vlan_tpid_set(struct rte_eth_dev *dev,
2586                   enum rte_vlan_type vlan_type,
2587                   uint16_t tpid)
2588 {
2589         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2590         uint64_t reg_r = 0, reg_w = 0;
2591         uint16_t reg_id = 0;
2592         int ret = 0;
2593         int qinq = dev->data->dev_conf.rxmode.offloads &
2594                    DEV_RX_OFFLOAD_VLAN_EXTEND;
2595
2596         switch (vlan_type) {
2597         case ETH_VLAN_TYPE_OUTER:
2598                 if (qinq)
2599                         reg_id = 3;
2600                 else
2601                         reg_id = 5;
2602                 break;
2603         case ETH_VLAN_TYPE_INNER:
2604                 if (qinq) {
2605                         reg_id = 5;
2606                 } else {
2607                         PMD_DRV_LOG(ERR,
2608                                     "Unsupported vlan type in single vlan.");
2609                         return -EINVAL;
2610                 }
2611                 break;
2612         default:
2613                 PMD_DRV_LOG(ERR, "Unsupported vlan type %d", vlan_type);
2614                 return -EINVAL;
2615         }
2616         reg_r = ICE_READ_REG(hw, GL_SWT_L2TAGCTRL(reg_id));
2617         PMD_DRV_LOG(DEBUG, "Debug read from ICE GL_SWT_L2TAGCTRL[%d]: "
2618                     "0x%08"PRIx64"", reg_id, reg_r);
2619
2620         reg_w = reg_r & (~(GL_SWT_L2TAGCTRL_ETHERTYPE_M));
2621         reg_w |= ((uint64_t)tpid << GL_SWT_L2TAGCTRL_ETHERTYPE_S);
2622         if (reg_r == reg_w) {
2623                 PMD_DRV_LOG(DEBUG, "No need to write");
2624                 return 0;
2625         }
2626
2627         ICE_WRITE_REG(hw, GL_SWT_L2TAGCTRL(reg_id), reg_w);
2628         PMD_DRV_LOG(DEBUG, "Debug write 0x%08"PRIx64" to "
2629                     "ICE GL_SWT_L2TAGCTRL[%d]", reg_w, reg_id);
2630
2631         return ret;
2632 }
2633
2634 static int
2635 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2636 {
2637         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
2638         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2639         int ret;
2640
2641         if (!lut)
2642                 return -EINVAL;
2643
2644         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2645                 ret = ice_aq_get_rss_lut(hw, vsi->idx, TRUE,
2646                                          lut, lut_size);
2647                 if (ret) {
2648                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
2649                         return -EINVAL;
2650                 }
2651         } else {
2652                 uint64_t *lut_dw = (uint64_t *)lut;
2653                 uint16_t i, lut_size_dw = lut_size / 4;
2654
2655                 for (i = 0; i < lut_size_dw; i++)
2656                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
2657         }
2658
2659         return 0;
2660 }
2661
2662 static int
2663 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
2664 {
2665         struct ice_pf *pf;
2666         struct ice_hw *hw;
2667         int ret;
2668
2669         if (!vsi || !lut)
2670                 return -EINVAL;
2671
2672         pf = ICE_VSI_TO_PF(vsi);
2673         hw = ICE_VSI_TO_HW(vsi);
2674
2675         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
2676                 ret = ice_aq_set_rss_lut(hw, vsi->idx, TRUE,
2677                                          lut, lut_size);
2678                 if (ret) {
2679                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
2680                         return -EINVAL;
2681                 }
2682         } else {
2683                 uint64_t *lut_dw = (uint64_t *)lut;
2684                 uint16_t i, lut_size_dw = lut_size / 4;
2685
2686                 for (i = 0; i < lut_size_dw; i++)
2687                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
2688
2689                 ice_flush(hw);
2690         }
2691
2692         return 0;
2693 }
2694
2695 static int
2696 ice_rss_reta_update(struct rte_eth_dev *dev,
2697                     struct rte_eth_rss_reta_entry64 *reta_conf,
2698                     uint16_t reta_size)
2699 {
2700         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2701         uint16_t i, lut_size = pf->hash_lut_size;
2702         uint16_t idx, shift;
2703         uint8_t *lut;
2704         int ret;
2705
2706         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
2707             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
2708             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
2709                 PMD_DRV_LOG(ERR,
2710                             "The size of hash lookup table configured (%d)"
2711                             "doesn't match the number hardware can "
2712                             "supported (128, 512, 2048)",
2713                             reta_size);
2714                 return -EINVAL;
2715         }
2716
2717         /* It MUST use the current LUT size to get the RSS lookup table,
2718          * otherwise if will fail with -100 error code.
2719          */
2720         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
2721         if (!lut) {
2722                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2723                 return -ENOMEM;
2724         }
2725         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
2726         if (ret)
2727                 goto out;
2728
2729         for (i = 0; i < reta_size; i++) {
2730                 idx = i / RTE_RETA_GROUP_SIZE;
2731                 shift = i % RTE_RETA_GROUP_SIZE;
2732                 if (reta_conf[idx].mask & (1ULL << shift))
2733                         lut[i] = reta_conf[idx].reta[shift];
2734         }
2735         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
2736         if (ret == 0 && lut_size != reta_size) {
2737                 PMD_DRV_LOG(INFO,
2738                             "The size of hash lookup table is changed from (%d) to (%d)",
2739                             lut_size, reta_size);
2740                 pf->hash_lut_size = reta_size;
2741         }
2742
2743 out:
2744         rte_free(lut);
2745
2746         return ret;
2747 }
2748
2749 static int
2750 ice_rss_reta_query(struct rte_eth_dev *dev,
2751                    struct rte_eth_rss_reta_entry64 *reta_conf,
2752                    uint16_t reta_size)
2753 {
2754         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2755         uint16_t i, lut_size = pf->hash_lut_size;
2756         uint16_t idx, shift;
2757         uint8_t *lut;
2758         int ret;
2759
2760         if (reta_size != lut_size) {
2761                 PMD_DRV_LOG(ERR,
2762                             "The size of hash lookup table configured (%d)"
2763                             "doesn't match the number hardware can "
2764                             "supported (%d)",
2765                             reta_size, lut_size);
2766                 return -EINVAL;
2767         }
2768
2769         lut = rte_zmalloc(NULL, reta_size, 0);
2770         if (!lut) {
2771                 PMD_DRV_LOG(ERR, "No memory can be allocated");
2772                 return -ENOMEM;
2773         }
2774
2775         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
2776         if (ret)
2777                 goto out;
2778
2779         for (i = 0; i < reta_size; i++) {
2780                 idx = i / RTE_RETA_GROUP_SIZE;
2781                 shift = i % RTE_RETA_GROUP_SIZE;
2782                 if (reta_conf[idx].mask & (1ULL << shift))
2783                         reta_conf[idx].reta[shift] = lut[i];
2784         }
2785
2786 out:
2787         rte_free(lut);
2788
2789         return ret;
2790 }
2791
2792 static int
2793 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
2794 {
2795         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2796         int ret = 0;
2797
2798         if (!key || key_len == 0) {
2799                 PMD_DRV_LOG(DEBUG, "No key to be configured");
2800                 return 0;
2801         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
2802                    sizeof(uint32_t)) {
2803                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
2804                 return -EINVAL;
2805         }
2806
2807         struct ice_aqc_get_set_rss_keys *key_dw =
2808                 (struct ice_aqc_get_set_rss_keys *)key;
2809
2810         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
2811         if (ret) {
2812                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
2813                 ret = -EINVAL;
2814         }
2815
2816         return ret;
2817 }
2818
2819 static int
2820 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
2821 {
2822         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2823         int ret;
2824
2825         if (!key || !key_len)
2826                 return -EINVAL;
2827
2828         ret = ice_aq_get_rss_key
2829                 (hw, vsi->idx,
2830                  (struct ice_aqc_get_set_rss_keys *)key);
2831         if (ret) {
2832                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
2833                 return -EINVAL;
2834         }
2835         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
2836
2837         return 0;
2838 }
2839
2840 static int
2841 ice_rss_hash_update(struct rte_eth_dev *dev,
2842                     struct rte_eth_rss_conf *rss_conf)
2843 {
2844         enum ice_status status = ICE_SUCCESS;
2845         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2846         struct ice_vsi *vsi = pf->main_vsi;
2847
2848         /* set hash key */
2849         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
2850         if (status)
2851                 return status;
2852
2853         /* TODO: hash enable config, ice_add_rss_cfg */
2854         return 0;
2855 }
2856
2857 static int
2858 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
2859                       struct rte_eth_rss_conf *rss_conf)
2860 {
2861         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2862         struct ice_vsi *vsi = pf->main_vsi;
2863
2864         ice_get_rss_key(vsi, rss_conf->rss_key,
2865                         &rss_conf->rss_key_len);
2866
2867         /* TODO: default set to 0 as hf config is not supported now */
2868         rss_conf->rss_hf = 0;
2869         return 0;
2870 }
2871
2872 static void
2873 ice_promisc_enable(struct rte_eth_dev *dev)
2874 {
2875         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2876         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2877         struct ice_vsi *vsi = pf->main_vsi;
2878         enum ice_status status;
2879         uint8_t pmask;
2880
2881         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2882                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2883
2884         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2885         if (status == ICE_ERR_ALREADY_EXISTS)
2886                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
2887         else if (status != ICE_SUCCESS)
2888                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
2889 }
2890
2891 static void
2892 ice_promisc_disable(struct rte_eth_dev *dev)
2893 {
2894         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2895         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2896         struct ice_vsi *vsi = pf->main_vsi;
2897         enum ice_status status;
2898         uint8_t pmask;
2899
2900         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
2901                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2902
2903         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2904         if (status != ICE_SUCCESS)
2905                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
2906 }
2907
2908 static void
2909 ice_allmulti_enable(struct rte_eth_dev *dev)
2910 {
2911         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2912         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2913         struct ice_vsi *vsi = pf->main_vsi;
2914         enum ice_status status;
2915         uint8_t pmask;
2916
2917         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2918
2919         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
2920         if (status != ICE_SUCCESS)
2921                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
2922 }
2923
2924 static void
2925 ice_allmulti_disable(struct rte_eth_dev *dev)
2926 {
2927         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2928         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2929         struct ice_vsi *vsi = pf->main_vsi;
2930         enum ice_status status;
2931         uint8_t pmask;
2932
2933         if (dev->data->promiscuous == 1)
2934                 return; /* must remain in all_multicast mode */
2935
2936         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
2937
2938         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
2939         if (status != ICE_SUCCESS)
2940                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
2941 }
2942
2943 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
2944                                     uint16_t queue_id)
2945 {
2946         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2947         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2948         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2949         uint32_t val;
2950         uint16_t msix_intr;
2951
2952         msix_intr = intr_handle->intr_vec[queue_id];
2953
2954         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
2955               GLINT_DYN_CTL_ITR_INDX_M;
2956         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
2957
2958         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
2959         rte_intr_enable(&pci_dev->intr_handle);
2960
2961         return 0;
2962 }
2963
2964 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
2965                                      uint16_t queue_id)
2966 {
2967         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2968         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2969         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2970         uint16_t msix_intr;
2971
2972         msix_intr = intr_handle->intr_vec[queue_id];
2973
2974         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
2975
2976         return 0;
2977 }
2978
2979 static int
2980 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
2981 {
2982         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2983         u32 full_ver;
2984         u8 ver, patch;
2985         u16 build;
2986         int ret;
2987
2988         full_ver = hw->nvm.oem_ver;
2989         ver = (u8)(full_ver >> 24);
2990         build = (u16)((full_ver >> 8) & 0xffff);
2991         patch = (u8)(full_ver & 0xff);
2992
2993         ret = snprintf(fw_version, fw_size,
2994                         "%d.%d%d 0x%08x %d.%d.%d",
2995                         ((hw->nvm.ver >> 12) & 0xf),
2996                         ((hw->nvm.ver >> 4) & 0xff),
2997                         (hw->nvm.ver & 0xf), hw->nvm.eetrack,
2998                         ver, build, patch);
2999
3000         /* add the size of '\0' */
3001         ret += 1;
3002         if (fw_size < (u32)ret)
3003                 return ret;
3004         else
3005                 return 0;
3006 }
3007
3008 static int
3009 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
3010 {
3011         struct ice_hw *hw;
3012         struct ice_vsi_ctx ctxt;
3013         uint8_t vlan_flags = 0;
3014         int ret;
3015
3016         if (!vsi || !info) {
3017                 PMD_DRV_LOG(ERR, "invalid parameters");
3018                 return -EINVAL;
3019         }
3020
3021         if (info->on) {
3022                 vsi->info.pvid = info->config.pvid;
3023                 /**
3024                  * If insert pvid is enabled, only tagged pkts are
3025                  * allowed to be sent out.
3026                  */
3027                 vlan_flags = ICE_AQ_VSI_PVLAN_INSERT_PVID |
3028                              ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3029         } else {
3030                 vsi->info.pvid = 0;
3031                 if (info->config.reject.tagged == 0)
3032                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_TAGGED;
3033
3034                 if (info->config.reject.untagged == 0)
3035                         vlan_flags |= ICE_AQ_VSI_VLAN_MODE_UNTAGGED;
3036         }
3037         vsi->info.vlan_flags &= ~(ICE_AQ_VSI_PVLAN_INSERT_PVID |
3038                                   ICE_AQ_VSI_VLAN_MODE_M);
3039         vsi->info.vlan_flags |= vlan_flags;
3040         memset(&ctxt, 0, sizeof(ctxt));
3041         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3042         ctxt.info.valid_sections =
3043                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3044         ctxt.vsi_num = vsi->vsi_id;
3045
3046         hw = ICE_VSI_TO_HW(vsi);
3047         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3048         if (ret != ICE_SUCCESS) {
3049                 PMD_DRV_LOG(ERR,
3050                             "update VSI for VLAN insert failed, err %d",
3051                             ret);
3052                 return -EINVAL;
3053         }
3054
3055         vsi->info.valid_sections |=
3056                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
3057
3058         return ret;
3059 }
3060
3061 static int
3062 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
3063 {
3064         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3065         struct ice_vsi *vsi = pf->main_vsi;
3066         struct rte_eth_dev_data *data = pf->dev_data;
3067         struct ice_vsi_vlan_pvid_info info;
3068         int ret;
3069
3070         memset(&info, 0, sizeof(info));
3071         info.on = on;
3072         if (info.on) {
3073                 info.config.pvid = pvid;
3074         } else {
3075                 info.config.reject.tagged =
3076                         data->dev_conf.txmode.hw_vlan_reject_tagged;
3077                 info.config.reject.untagged =
3078                         data->dev_conf.txmode.hw_vlan_reject_untagged;
3079         }
3080
3081         ret = ice_vsi_vlan_pvid_set(vsi, &info);
3082         if (ret < 0) {
3083                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
3084                 return -EINVAL;
3085         }
3086
3087         return 0;
3088 }
3089
3090 static int
3091 ice_get_eeprom_length(struct rte_eth_dev *dev)
3092 {
3093         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3094
3095         /* Convert word count to byte count */
3096         return hw->nvm.sr_words << 1;
3097 }
3098
3099 static int
3100 ice_get_eeprom(struct rte_eth_dev *dev,
3101                struct rte_dev_eeprom_info *eeprom)
3102 {
3103         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3104         uint16_t *data = eeprom->data;
3105         uint16_t first_word, last_word, nwords;
3106         enum ice_status status = ICE_SUCCESS;
3107
3108         first_word = eeprom->offset >> 1;
3109         last_word = (eeprom->offset + eeprom->length - 1) >> 1;
3110         nwords = last_word - first_word + 1;
3111
3112         if (first_word >= hw->nvm.sr_words ||
3113             last_word >= hw->nvm.sr_words) {
3114                 PMD_DRV_LOG(ERR, "Requested EEPROM bytes out of range.");
3115                 return -EINVAL;
3116         }
3117
3118         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
3119
3120         status = ice_read_sr_buf(hw, first_word, &nwords, data);
3121         if (status) {
3122                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
3123                 eeprom->length = sizeof(uint16_t) * nwords;
3124                 return -EIO;
3125         }
3126
3127         return 0;
3128 }
3129
3130 static void
3131 ice_stat_update_32(struct ice_hw *hw,
3132                    uint32_t reg,
3133                    bool offset_loaded,
3134                    uint64_t *offset,
3135                    uint64_t *stat)
3136 {
3137         uint64_t new_data;
3138
3139         new_data = (uint64_t)ICE_READ_REG(hw, reg);
3140         if (!offset_loaded)
3141                 *offset = new_data;
3142
3143         if (new_data >= *offset)
3144                 *stat = (uint64_t)(new_data - *offset);
3145         else
3146                 *stat = (uint64_t)((new_data +
3147                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
3148                                    - *offset);
3149 }
3150
3151 static void
3152 ice_stat_update_40(struct ice_hw *hw,
3153                    uint32_t hireg,
3154                    uint32_t loreg,
3155                    bool offset_loaded,
3156                    uint64_t *offset,
3157                    uint64_t *stat)
3158 {
3159         uint64_t new_data;
3160
3161         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
3162         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
3163                     ICE_32_BIT_WIDTH;
3164
3165         if (!offset_loaded)
3166                 *offset = new_data;
3167
3168         if (new_data >= *offset)
3169                 *stat = new_data - *offset;
3170         else
3171                 *stat = (uint64_t)((new_data +
3172                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
3173                                    *offset);
3174
3175         *stat &= ICE_40_BIT_MASK;
3176 }
3177
3178 /* Get all the statistics of a VSI */
3179 static void
3180 ice_update_vsi_stats(struct ice_vsi *vsi)
3181 {
3182         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
3183         struct ice_eth_stats *nes = &vsi->eth_stats;
3184         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3185         int idx = rte_le_to_cpu_16(vsi->vsi_id);
3186
3187         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
3188                            vsi->offset_loaded, &oes->rx_bytes,
3189                            &nes->rx_bytes);
3190         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
3191                            vsi->offset_loaded, &oes->rx_unicast,
3192                            &nes->rx_unicast);
3193         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
3194                            vsi->offset_loaded, &oes->rx_multicast,
3195                            &nes->rx_multicast);
3196         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
3197                            vsi->offset_loaded, &oes->rx_broadcast,
3198                            &nes->rx_broadcast);
3199         /* exclude CRC bytes */
3200         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
3201                           nes->rx_broadcast) * ETHER_CRC_LEN;
3202
3203         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
3204                            &oes->rx_discards, &nes->rx_discards);
3205         /* GLV_REPC not supported */
3206         /* GLV_RMPC not supported */
3207         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
3208                            &oes->rx_unknown_protocol,
3209                            &nes->rx_unknown_protocol);
3210         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
3211                            vsi->offset_loaded, &oes->tx_bytes,
3212                            &nes->tx_bytes);
3213         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
3214                            vsi->offset_loaded, &oes->tx_unicast,
3215                            &nes->tx_unicast);
3216         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
3217                            vsi->offset_loaded, &oes->tx_multicast,
3218                            &nes->tx_multicast);
3219         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
3220                            vsi->offset_loaded,  &oes->tx_broadcast,
3221                            &nes->tx_broadcast);
3222         /* GLV_TDPC not supported */
3223         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
3224                            &oes->tx_errors, &nes->tx_errors);
3225         vsi->offset_loaded = true;
3226
3227         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
3228                     vsi->vsi_id);
3229         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
3230         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
3231         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
3232         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
3233         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
3234         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
3235                     nes->rx_unknown_protocol);
3236         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
3237         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
3238         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
3239         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
3240         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
3241         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
3242         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
3243                     vsi->vsi_id);
3244 }
3245
3246 static void
3247 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
3248 {
3249         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3250         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
3251
3252         /* Get statistics of struct ice_eth_stats */
3253         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
3254                            GLPRT_GORCL(hw->port_info->lport),
3255                            pf->offset_loaded, &os->eth.rx_bytes,
3256                            &ns->eth.rx_bytes);
3257         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
3258                            GLPRT_UPRCL(hw->port_info->lport),
3259                            pf->offset_loaded, &os->eth.rx_unicast,
3260                            &ns->eth.rx_unicast);
3261         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
3262                            GLPRT_MPRCL(hw->port_info->lport),
3263                            pf->offset_loaded, &os->eth.rx_multicast,
3264                            &ns->eth.rx_multicast);
3265         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
3266                            GLPRT_BPRCL(hw->port_info->lport),
3267                            pf->offset_loaded, &os->eth.rx_broadcast,
3268                            &ns->eth.rx_broadcast);
3269         ice_stat_update_32(hw, PRTRPB_RDPC,
3270                            pf->offset_loaded, &os->eth.rx_discards,
3271                            &ns->eth.rx_discards);
3272
3273         /* Workaround: CRC size should not be included in byte statistics,
3274          * so subtract ETHER_CRC_LEN from the byte counter for each rx packet.
3275          */
3276         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
3277                              ns->eth.rx_broadcast) * ETHER_CRC_LEN;
3278
3279         /* GLPRT_REPC not supported */
3280         /* GLPRT_RMPC not supported */
3281         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
3282                            pf->offset_loaded,
3283                            &os->eth.rx_unknown_protocol,
3284                            &ns->eth.rx_unknown_protocol);
3285         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
3286                            GLPRT_GOTCL(hw->port_info->lport),
3287                            pf->offset_loaded, &os->eth.tx_bytes,
3288                            &ns->eth.tx_bytes);
3289         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
3290                            GLPRT_UPTCL(hw->port_info->lport),
3291                            pf->offset_loaded, &os->eth.tx_unicast,
3292                            &ns->eth.tx_unicast);
3293         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
3294                            GLPRT_MPTCL(hw->port_info->lport),
3295                            pf->offset_loaded, &os->eth.tx_multicast,
3296                            &ns->eth.tx_multicast);
3297         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
3298                            GLPRT_BPTCL(hw->port_info->lport),
3299                            pf->offset_loaded, &os->eth.tx_broadcast,
3300                            &ns->eth.tx_broadcast);
3301         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
3302                              ns->eth.tx_broadcast) * ETHER_CRC_LEN;
3303
3304         /* GLPRT_TEPC not supported */
3305
3306         /* additional port specific stats */
3307         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
3308                            pf->offset_loaded, &os->tx_dropped_link_down,
3309                            &ns->tx_dropped_link_down);
3310         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
3311                            pf->offset_loaded, &os->crc_errors,
3312                            &ns->crc_errors);
3313         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
3314                            pf->offset_loaded, &os->illegal_bytes,
3315                            &ns->illegal_bytes);
3316         /* GLPRT_ERRBC not supported */
3317         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
3318                            pf->offset_loaded, &os->mac_local_faults,
3319                            &ns->mac_local_faults);
3320         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
3321                            pf->offset_loaded, &os->mac_remote_faults,
3322                            &ns->mac_remote_faults);
3323
3324         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
3325                            pf->offset_loaded, &os->rx_len_errors,
3326                            &ns->rx_len_errors);
3327
3328         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
3329                            pf->offset_loaded, &os->link_xon_rx,
3330                            &ns->link_xon_rx);
3331         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
3332                            pf->offset_loaded, &os->link_xoff_rx,
3333                            &ns->link_xoff_rx);
3334         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
3335                            pf->offset_loaded, &os->link_xon_tx,
3336                            &ns->link_xon_tx);
3337         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
3338                            pf->offset_loaded, &os->link_xoff_tx,
3339                            &ns->link_xoff_tx);
3340         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
3341                            GLPRT_PRC64L(hw->port_info->lport),
3342                            pf->offset_loaded, &os->rx_size_64,
3343                            &ns->rx_size_64);
3344         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
3345                            GLPRT_PRC127L(hw->port_info->lport),
3346                            pf->offset_loaded, &os->rx_size_127,
3347                            &ns->rx_size_127);
3348         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
3349                            GLPRT_PRC255L(hw->port_info->lport),
3350                            pf->offset_loaded, &os->rx_size_255,
3351                            &ns->rx_size_255);
3352         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
3353                            GLPRT_PRC511L(hw->port_info->lport),
3354                            pf->offset_loaded, &os->rx_size_511,
3355                            &ns->rx_size_511);
3356         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
3357                            GLPRT_PRC1023L(hw->port_info->lport),
3358                            pf->offset_loaded, &os->rx_size_1023,
3359                            &ns->rx_size_1023);
3360         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
3361                            GLPRT_PRC1522L(hw->port_info->lport),
3362                            pf->offset_loaded, &os->rx_size_1522,
3363                            &ns->rx_size_1522);
3364         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
3365                            GLPRT_PRC9522L(hw->port_info->lport),
3366                            pf->offset_loaded, &os->rx_size_big,
3367                            &ns->rx_size_big);
3368         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
3369                            pf->offset_loaded, &os->rx_undersize,
3370                            &ns->rx_undersize);
3371         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
3372                            pf->offset_loaded, &os->rx_fragments,
3373                            &ns->rx_fragments);
3374         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
3375                            pf->offset_loaded, &os->rx_oversize,
3376                            &ns->rx_oversize);
3377         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
3378                            pf->offset_loaded, &os->rx_jabber,
3379                            &ns->rx_jabber);
3380         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
3381                            GLPRT_PTC64L(hw->port_info->lport),
3382                            pf->offset_loaded, &os->tx_size_64,
3383                            &ns->tx_size_64);
3384         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
3385                            GLPRT_PTC127L(hw->port_info->lport),
3386                            pf->offset_loaded, &os->tx_size_127,
3387                            &ns->tx_size_127);
3388         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
3389                            GLPRT_PTC255L(hw->port_info->lport),
3390                            pf->offset_loaded, &os->tx_size_255,
3391                            &ns->tx_size_255);
3392         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
3393                            GLPRT_PTC511L(hw->port_info->lport),
3394                            pf->offset_loaded, &os->tx_size_511,
3395                            &ns->tx_size_511);
3396         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
3397                            GLPRT_PTC1023L(hw->port_info->lport),
3398                            pf->offset_loaded, &os->tx_size_1023,
3399                            &ns->tx_size_1023);
3400         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
3401                            GLPRT_PTC1522L(hw->port_info->lport),
3402                            pf->offset_loaded, &os->tx_size_1522,
3403                            &ns->tx_size_1522);
3404         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
3405                            GLPRT_PTC9522L(hw->port_info->lport),
3406                            pf->offset_loaded, &os->tx_size_big,
3407                            &ns->tx_size_big);
3408
3409         /* GLPRT_MSPDC not supported */
3410         /* GLPRT_XEC not supported */
3411
3412         pf->offset_loaded = true;
3413
3414         if (pf->main_vsi)
3415                 ice_update_vsi_stats(pf->main_vsi);
3416 }
3417
3418 /* Get all statistics of a port */
3419 static int
3420 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
3421 {
3422         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3423         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3424         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
3425
3426         /* call read registers - updates values, now write them to struct */
3427         ice_read_stats_registers(pf, hw);
3428
3429         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
3430                           pf->main_vsi->eth_stats.rx_multicast +
3431                           pf->main_vsi->eth_stats.rx_broadcast -
3432                           pf->main_vsi->eth_stats.rx_discards;
3433         stats->opackets = ns->eth.tx_unicast +
3434                           ns->eth.tx_multicast +
3435                           ns->eth.tx_broadcast;
3436         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
3437         stats->obytes   = ns->eth.tx_bytes;
3438         stats->oerrors  = ns->eth.tx_errors +
3439                           pf->main_vsi->eth_stats.tx_errors;
3440
3441         /* Rx Errors */
3442         stats->imissed  = ns->eth.rx_discards +
3443                           pf->main_vsi->eth_stats.rx_discards;
3444         stats->ierrors  = ns->crc_errors +
3445                           ns->rx_undersize +
3446                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
3447
3448         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
3449         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
3450         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
3451         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
3452         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
3453         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
3454         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
3455                     pf->main_vsi->eth_stats.rx_discards);
3456         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
3457                     ns->eth.rx_unknown_protocol);
3458         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
3459         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
3460         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
3461         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
3462         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
3463         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
3464                     pf->main_vsi->eth_stats.tx_discards);
3465         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
3466
3467         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
3468                     ns->tx_dropped_link_down);
3469         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
3470         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
3471                     ns->illegal_bytes);
3472         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
3473         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
3474                     ns->mac_local_faults);
3475         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
3476                     ns->mac_remote_faults);
3477         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
3478         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
3479         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
3480         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
3481         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
3482         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
3483         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
3484         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
3485         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
3486         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
3487         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
3488         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
3489         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
3490         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
3491         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
3492         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
3493         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
3494         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
3495         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
3496         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
3497         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
3498         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
3499         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
3500         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
3501         return 0;
3502 }
3503
3504 /* Reset the statistics */
3505 static void
3506 ice_stats_reset(struct rte_eth_dev *dev)
3507 {
3508         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3509         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3510
3511         /* Mark PF and VSI stats to update the offset, aka "reset" */
3512         pf->offset_loaded = false;
3513         if (pf->main_vsi)
3514                 pf->main_vsi->offset_loaded = false;
3515
3516         /* read the stats, reading current register values into offset */
3517         ice_read_stats_registers(pf, hw);
3518 }
3519
3520 static uint32_t
3521 ice_xstats_calc_num(void)
3522 {
3523         uint32_t num;
3524
3525         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
3526
3527         return num;
3528 }
3529
3530 static int
3531 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
3532                unsigned int n)
3533 {
3534         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3535         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3536         unsigned int i;
3537         unsigned int count;
3538         struct ice_hw_port_stats *hw_stats = &pf->stats;
3539
3540         count = ice_xstats_calc_num();
3541         if (n < count)
3542                 return count;
3543
3544         ice_read_stats_registers(pf, hw);
3545
3546         if (!xstats)
3547                 return 0;
3548
3549         count = 0;
3550
3551         /* Get stats from ice_eth_stats struct */
3552         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3553                 xstats[count].value =
3554                         *(uint64_t *)((char *)&hw_stats->eth +
3555                                       ice_stats_strings[i].offset);
3556                 xstats[count].id = count;
3557                 count++;
3558         }
3559
3560         /* Get individiual stats from ice_hw_port struct */
3561         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3562                 xstats[count].value =
3563                         *(uint64_t *)((char *)hw_stats +
3564                                       ice_hw_port_strings[i].offset);
3565                 xstats[count].id = count;
3566                 count++;
3567         }
3568
3569         return count;
3570 }
3571
3572 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
3573                                 struct rte_eth_xstat_name *xstats_names,
3574                                 __rte_unused unsigned int limit)
3575 {
3576         unsigned int count = 0;
3577         unsigned int i;
3578
3579         if (!xstats_names)
3580                 return ice_xstats_calc_num();
3581
3582         /* Note: limit checked in rte_eth_xstats_names() */
3583
3584         /* Get stats from ice_eth_stats struct */
3585         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
3586                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
3587                         sizeof(xstats_names[count].name));
3588                 count++;
3589         }
3590
3591         /* Get individiual stats from ice_hw_port struct */
3592         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
3593                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
3594                         sizeof(xstats_names[count].name));
3595                 count++;
3596         }
3597
3598         return count;
3599 }
3600
3601 static int
3602 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
3603               struct rte_pci_device *pci_dev)
3604 {
3605         return rte_eth_dev_pci_generic_probe(pci_dev,
3606                                              sizeof(struct ice_adapter),
3607                                              ice_dev_init);
3608 }
3609
3610 static int
3611 ice_pci_remove(struct rte_pci_device *pci_dev)
3612 {
3613         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
3614 }
3615
3616 static struct rte_pci_driver rte_ice_pmd = {
3617         .id_table = pci_id_ice_map,
3618         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC |
3619                      RTE_PCI_DRV_IOVA_AS_VA,
3620         .probe = ice_pci_probe,
3621         .remove = ice_pci_remove,
3622 };
3623
3624 /**
3625  * Driver initialization routine.
3626  * Invoked once at EAL init time.
3627  * Register itself as the [Poll Mode] Driver of PCI devices.
3628  */
3629 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
3630 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
3631 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
3632 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
3633                               ICE_MAX_QP_NUM "=<int>");
3634
3635 RTE_INIT(ice_init_log)
3636 {
3637         ice_logtype_init = rte_log_register("pmd.net.ice.init");
3638         if (ice_logtype_init >= 0)
3639                 rte_log_set_level(ice_logtype_init, RTE_LOG_NOTICE);
3640         ice_logtype_driver = rte_log_register("pmd.net.ice.driver");
3641         if (ice_logtype_driver >= 0)
3642                 rte_log_set_level(ice_logtype_driver, RTE_LOG_NOTICE);
3643 }