drivers/net/ice/ice_ethdev.c

   1 /* SPDX-License-Identifier: BSD-3-Clause
   2  * Copyright(c) 2018 Intel Corporation
   3  */
   4
   5 #include <rte_string_fns.h>
   6 #include <ethdev_pci.h>
   7
   8 #include <stdio.h>
   9 #include <sys/types.h>
  10 #include <sys/stat.h>
  11 #include <unistd.h>
  12
  13 #include <rte_tailq.h>
  14
  15 #include "eal_firmware.h"
  16
  17 #include "base/ice_sched.h"
  18 #include "base/ice_flow.h"
  19 #include "base/ice_dcb.h"
  20 #include "base/ice_common.h"
  21
  22 #include "rte_pmd_ice.h"
  23 #include "ice_ethdev.h"
  24 #include "ice_rxtx.h"
  25 #include "ice_generic_flow.h"
  26
  27 /* devargs */
  28 #define ICE_SAFE_MODE_SUPPORT_ARG "safe-mode-support"
  29 #define ICE_PIPELINE_MODE_SUPPORT_ARG  "pipeline-mode-support"
  30 #define ICE_PROTO_XTR_ARG         "proto_xtr"
  31 #define ICE_HW_DEBUG_MASK_ARG     "hw_debug_mask"
  32
  33 static const char * const ice_valid_args[] = {
  34         ICE_SAFE_MODE_SUPPORT_ARG,
  35         ICE_PIPELINE_MODE_SUPPORT_ARG,
  36         ICE_PROTO_XTR_ARG,
  37         ICE_HW_DEBUG_MASK_ARG,
  38         NULL
  39 };
  40
  41 static const struct rte_mbuf_dynfield ice_proto_xtr_metadata_param = {
  42         .name = "intel_pmd_dynfield_proto_xtr_metadata",
  43         .size = sizeof(uint32_t),
  44         .align = __alignof__(uint32_t),
  45         .flags = 0,
  46 };
  47
  48 struct proto_xtr_ol_flag {
  49         const struct rte_mbuf_dynflag param;
  50         uint64_t *ol_flag;
  51         bool required;
  52 };
  53
  54 static bool ice_proto_xtr_hw_support[PROTO_XTR_MAX];
  55
  56 static struct proto_xtr_ol_flag ice_proto_xtr_ol_flag_params[] = {
  57         [PROTO_XTR_VLAN] = {
  58                 .param = { .name = "intel_pmd_dynflag_proto_xtr_vlan" },
  59                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_vlan_mask },
  60         [PROTO_XTR_IPV4] = {
  61                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv4" },
  62                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv4_mask },
  63         [PROTO_XTR_IPV6] = {
  64                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6" },
  65                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_mask },
  66         [PROTO_XTR_IPV6_FLOW] = {
  67                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ipv6_flow" },
  68                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ipv6_flow_mask },
  69         [PROTO_XTR_TCP] = {
  70                 .param = { .name = "intel_pmd_dynflag_proto_xtr_tcp" },
  71                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_tcp_mask },
  72         [PROTO_XTR_IP_OFFSET] = {
  73                 .param = { .name = "intel_pmd_dynflag_proto_xtr_ip_offset" },
  74                 .ol_flag = &rte_net_ice_dynflag_proto_xtr_ip_offset_mask },
  75 };
  76
  77 #define ICE_OS_DEFAULT_PKG_NAME         "ICE OS Default Package"
  78 #define ICE_COMMS_PKG_NAME                      "ICE COMMS Package"
  79 #define ICE_MAX_RES_DESC_NUM        1024
  80
  81 static int ice_dev_configure(struct rte_eth_dev *dev);
  82 static int ice_dev_start(struct rte_eth_dev *dev);
  83 static int ice_dev_stop(struct rte_eth_dev *dev);
  84 static int ice_dev_close(struct rte_eth_dev *dev);
  85 static int ice_dev_reset(struct rte_eth_dev *dev);
  86 static int ice_dev_info_get(struct rte_eth_dev *dev,
  87                             struct rte_eth_dev_info *dev_info);
  88 static int ice_link_update(struct rte_eth_dev *dev,
  89                            int wait_to_complete);
  90 static int ice_dev_set_link_up(struct rte_eth_dev *dev);
  91 static int ice_dev_set_link_down(struct rte_eth_dev *dev);
  92
  93 static int ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu);
  94 static int ice_vlan_offload_set(struct rte_eth_dev *dev, int mask);
  95 static int ice_rss_reta_update(struct rte_eth_dev *dev,
  96                                struct rte_eth_rss_reta_entry64 *reta_conf,
  97                                uint16_t reta_size);
  98 static int ice_rss_reta_query(struct rte_eth_dev *dev,
  99                               struct rte_eth_rss_reta_entry64 *reta_conf,
 100                               uint16_t reta_size);
 101 static int ice_rss_hash_update(struct rte_eth_dev *dev,
 102                                struct rte_eth_rss_conf *rss_conf);
 103 static int ice_rss_hash_conf_get(struct rte_eth_dev *dev,
 104                                  struct rte_eth_rss_conf *rss_conf);
 105 static int ice_promisc_enable(struct rte_eth_dev *dev);
 106 static int ice_promisc_disable(struct rte_eth_dev *dev);
 107 static int ice_allmulti_enable(struct rte_eth_dev *dev);
 108 static int ice_allmulti_disable(struct rte_eth_dev *dev);
 109 static int ice_vlan_filter_set(struct rte_eth_dev *dev,
 110                                uint16_t vlan_id,
 111                                int on);
 112 static int ice_macaddr_set(struct rte_eth_dev *dev,
 113                            struct rte_ether_addr *mac_addr);
 114 static int ice_macaddr_add(struct rte_eth_dev *dev,
 115                            struct rte_ether_addr *mac_addr,
 116                            __rte_unused uint32_t index,
 117                            uint32_t pool);
 118 static void ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index);
 119 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
 120                                     uint16_t queue_id);
 121 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
 122                                      uint16_t queue_id);
 123 static int ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version,
 124                               size_t fw_size);
 125 static int ice_vlan_pvid_set(struct rte_eth_dev *dev,
 126                              uint16_t pvid, int on);
 127 static int ice_get_eeprom_length(struct rte_eth_dev *dev);
 128 static int ice_get_eeprom(struct rte_eth_dev *dev,
 129                           struct rte_dev_eeprom_info *eeprom);
 130 static int ice_stats_get(struct rte_eth_dev *dev,
 131                          struct rte_eth_stats *stats);
 132 static int ice_stats_reset(struct rte_eth_dev *dev);
 133 static int ice_xstats_get(struct rte_eth_dev *dev,
 134                           struct rte_eth_xstat *xstats, unsigned int n);
 135 static int ice_xstats_get_names(struct rte_eth_dev *dev,
 136                                 struct rte_eth_xstat_name *xstats_names,
 137                                 unsigned int limit);
 138 static int ice_dev_flow_ops_get(struct rte_eth_dev *dev,
 139                                 const struct rte_flow_ops **ops);
 140 static int ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
 141                         struct rte_eth_udp_tunnel *udp_tunnel);
 142 static int ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
 143                         struct rte_eth_udp_tunnel *udp_tunnel);
 144
 145 static const struct rte_pci_id pci_id_ice_map[] = {
 146         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_BACKPLANE) },
 147         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_SFP) },
 148         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_10G_BASE_T) },
 149         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_1GBE) },
 150         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823L_QSFP) },
 151         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_BACKPLANE) },
 152         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_QSFP) },
 153         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810C_SFP) },
 154         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_BACKPLANE) },
 155         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_QSFP) },
 156         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E810_XXV_SFP) },
 157         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_BACKPLANE) },
 158         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_QSFP) },
 159         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SFP) },
 160         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_10G_BASE_T) },
 161         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E823C_SGMII) },
 162         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_BACKPLANE) },
 163         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_QSFP) },
 164         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SFP) },
 165         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_10G_BASE_T) },
 166         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822C_SGMII) },
 167         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_BACKPLANE) },
 168         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SFP) },
 169         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_10G_BASE_T) },
 170         { RTE_PCI_DEVICE(ICE_INTEL_VENDOR_ID, ICE_DEV_ID_E822L_SGMII) },
 171         { .vendor_id = 0, /* sentinel */ },
 172 };
 173
 174 static const struct eth_dev_ops ice_eth_dev_ops = {
 175         .dev_configure                = ice_dev_configure,
 176         .dev_start                    = ice_dev_start,
 177         .dev_stop                     = ice_dev_stop,
 178         .dev_close                    = ice_dev_close,
 179         .dev_reset                    = ice_dev_reset,
 180         .dev_set_link_up              = ice_dev_set_link_up,
 181         .dev_set_link_down            = ice_dev_set_link_down,
 182         .rx_queue_start               = ice_rx_queue_start,
 183         .rx_queue_stop                = ice_rx_queue_stop,
 184         .tx_queue_start               = ice_tx_queue_start,
 185         .tx_queue_stop                = ice_tx_queue_stop,
 186         .rx_queue_setup               = ice_rx_queue_setup,
 187         .rx_queue_release             = ice_rx_queue_release,
 188         .tx_queue_setup               = ice_tx_queue_setup,
 189         .tx_queue_release             = ice_tx_queue_release,
 190         .dev_infos_get                = ice_dev_info_get,
 191         .dev_supported_ptypes_get     = ice_dev_supported_ptypes_get,
 192         .link_update                  = ice_link_update,
 193         .mtu_set                      = ice_mtu_set,
 194         .mac_addr_set                 = ice_macaddr_set,
 195         .mac_addr_add                 = ice_macaddr_add,
 196         .mac_addr_remove              = ice_macaddr_remove,
 197         .vlan_filter_set              = ice_vlan_filter_set,
 198         .vlan_offload_set             = ice_vlan_offload_set,
 199         .reta_update                  = ice_rss_reta_update,
 200         .reta_query                   = ice_rss_reta_query,
 201         .rss_hash_update              = ice_rss_hash_update,
 202         .rss_hash_conf_get            = ice_rss_hash_conf_get,
 203         .promiscuous_enable           = ice_promisc_enable,
 204         .promiscuous_disable          = ice_promisc_disable,
 205         .allmulticast_enable          = ice_allmulti_enable,
 206         .allmulticast_disable         = ice_allmulti_disable,
 207         .rx_queue_intr_enable         = ice_rx_queue_intr_enable,
 208         .rx_queue_intr_disable        = ice_rx_queue_intr_disable,
 209         .fw_version_get               = ice_fw_version_get,
 210         .vlan_pvid_set                = ice_vlan_pvid_set,
 211         .rxq_info_get                 = ice_rxq_info_get,
 212         .txq_info_get                 = ice_txq_info_get,
 213         .rx_burst_mode_get            = ice_rx_burst_mode_get,
 214         .tx_burst_mode_get            = ice_tx_burst_mode_get,
 215         .get_eeprom_length            = ice_get_eeprom_length,
 216         .get_eeprom                   = ice_get_eeprom,
 217         .stats_get                    = ice_stats_get,
 218         .stats_reset                  = ice_stats_reset,
 219         .xstats_get                   = ice_xstats_get,
 220         .xstats_get_names             = ice_xstats_get_names,
 221         .xstats_reset                 = ice_stats_reset,
 222         .flow_ops_get                 = ice_dev_flow_ops_get,
 223         .udp_tunnel_port_add          = ice_dev_udp_tunnel_port_add,
 224         .udp_tunnel_port_del          = ice_dev_udp_tunnel_port_del,
 225         .tx_done_cleanup              = ice_tx_done_cleanup,
 226         .get_monitor_addr             = ice_get_monitor_addr,
 227 };
 228
 229 /* store statistics names and its offset in stats structure */
 230 struct ice_xstats_name_off {
 231         char name[RTE_ETH_XSTATS_NAME_SIZE];
 232         unsigned int offset;
 233 };
 234
 235 static const struct ice_xstats_name_off ice_stats_strings[] = {
 236         {"rx_unicast_packets", offsetof(struct ice_eth_stats, rx_unicast)},
 237         {"rx_multicast_packets", offsetof(struct ice_eth_stats, rx_multicast)},
 238         {"rx_broadcast_packets", offsetof(struct ice_eth_stats, rx_broadcast)},
 239         {"rx_dropped_packets", offsetof(struct ice_eth_stats, rx_discards)},
 240         {"rx_unknown_protocol_packets", offsetof(struct ice_eth_stats,
 241                 rx_unknown_protocol)},
 242         {"tx_unicast_packets", offsetof(struct ice_eth_stats, tx_unicast)},
 243         {"tx_multicast_packets", offsetof(struct ice_eth_stats, tx_multicast)},
 244         {"tx_broadcast_packets", offsetof(struct ice_eth_stats, tx_broadcast)},
 245         {"tx_dropped_packets", offsetof(struct ice_eth_stats, tx_discards)},
 246 };
 247
 248 #define ICE_NB_ETH_XSTATS (sizeof(ice_stats_strings) / \
 249                 sizeof(ice_stats_strings[0]))
 250
 251 static const struct ice_xstats_name_off ice_hw_port_strings[] = {
 252         {"tx_link_down_dropped", offsetof(struct ice_hw_port_stats,
 253                 tx_dropped_link_down)},
 254         {"rx_crc_errors", offsetof(struct ice_hw_port_stats, crc_errors)},
 255         {"rx_illegal_byte_errors", offsetof(struct ice_hw_port_stats,
 256                 illegal_bytes)},
 257         {"rx_error_bytes", offsetof(struct ice_hw_port_stats, error_bytes)},
 258         {"mac_local_errors", offsetof(struct ice_hw_port_stats,
 259                 mac_local_faults)},
 260         {"mac_remote_errors", offsetof(struct ice_hw_port_stats,
 261                 mac_remote_faults)},
 262         {"rx_len_errors", offsetof(struct ice_hw_port_stats,
 263                 rx_len_errors)},
 264         {"tx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_tx)},
 265         {"rx_xon_packets", offsetof(struct ice_hw_port_stats, link_xon_rx)},
 266         {"tx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_tx)},
 267         {"rx_xoff_packets", offsetof(struct ice_hw_port_stats, link_xoff_rx)},
 268         {"rx_size_64_packets", offsetof(struct ice_hw_port_stats, rx_size_64)},
 269         {"rx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 270                 rx_size_127)},
 271         {"rx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 272                 rx_size_255)},
 273         {"rx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 274                 rx_size_511)},
 275         {"rx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 276                 rx_size_1023)},
 277         {"rx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 278                 rx_size_1522)},
 279         {"rx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 280                 rx_size_big)},
 281         {"rx_undersized_errors", offsetof(struct ice_hw_port_stats,
 282                 rx_undersize)},
 283         {"rx_oversize_errors", offsetof(struct ice_hw_port_stats,
 284                 rx_oversize)},
 285         {"rx_mac_short_pkt_dropped", offsetof(struct ice_hw_port_stats,
 286                 mac_short_pkt_dropped)},
 287         {"rx_fragmented_errors", offsetof(struct ice_hw_port_stats,
 288                 rx_fragments)},
 289         {"rx_jabber_errors", offsetof(struct ice_hw_port_stats, rx_jabber)},
 290         {"tx_size_64_packets", offsetof(struct ice_hw_port_stats, tx_size_64)},
 291         {"tx_size_65_to_127_packets", offsetof(struct ice_hw_port_stats,
 292                 tx_size_127)},
 293         {"tx_size_128_to_255_packets", offsetof(struct ice_hw_port_stats,
 294                 tx_size_255)},
 295         {"tx_size_256_to_511_packets", offsetof(struct ice_hw_port_stats,
 296                 tx_size_511)},
 297         {"tx_size_512_to_1023_packets", offsetof(struct ice_hw_port_stats,
 298                 tx_size_1023)},
 299         {"tx_size_1024_to_1522_packets", offsetof(struct ice_hw_port_stats,
 300                 tx_size_1522)},
 301         {"tx_size_1523_to_max_packets", offsetof(struct ice_hw_port_stats,
 302                 tx_size_big)},
 303 };
 304
 305 #define ICE_NB_HW_PORT_XSTATS (sizeof(ice_hw_port_strings) / \
 306                 sizeof(ice_hw_port_strings[0]))
 307
 308 static void
 309 ice_init_controlq_parameter(struct ice_hw *hw)
 310 {
 311         /* fields for adminq */
 312         hw->adminq.num_rq_entries = ICE_ADMINQ_LEN;
 313         hw->adminq.num_sq_entries = ICE_ADMINQ_LEN;
 314         hw->adminq.rq_buf_size = ICE_ADMINQ_BUF_SZ;
 315         hw->adminq.sq_buf_size = ICE_ADMINQ_BUF_SZ;
 316
 317         /* fields for mailboxq, DPDK used as PF host */
 318         hw->mailboxq.num_rq_entries = ICE_MAILBOXQ_LEN;
 319         hw->mailboxq.num_sq_entries = ICE_MAILBOXQ_LEN;
 320         hw->mailboxq.rq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 321         hw->mailboxq.sq_buf_size = ICE_MAILBOXQ_BUF_SZ;
 322 }
 323
 324 static int
 325 lookup_proto_xtr_type(const char *xtr_name)
 326 {
 327         static struct {
 328                 const char *name;
 329                 enum proto_xtr_type type;
 330         } xtr_type_map[] = {
 331                 { "vlan",      PROTO_XTR_VLAN      },
 332                 { "ipv4",      PROTO_XTR_IPV4      },
 333                 { "ipv6",      PROTO_XTR_IPV6      },
 334                 { "ipv6_flow", PROTO_XTR_IPV6_FLOW },
 335                 { "tcp",       PROTO_XTR_TCP       },
 336                 { "ip_offset", PROTO_XTR_IP_OFFSET },
 337         };
 338         uint32_t i;
 339
 340         for (i = 0; i < RTE_DIM(xtr_type_map); i++) {
 341                 if (strcmp(xtr_name, xtr_type_map[i].name) == 0)
 342                         return xtr_type_map[i].type;
 343         }
 344
 345         return -1;
 346 }
 347
 348 /*
 349  * Parse elem, the elem could be single number/range or '(' ')' group
 350  * 1) A single number elem, it's just a simple digit. e.g. 9
 351  * 2) A single range elem, two digits with a '-' between. e.g. 2-6
 352  * 3) A group elem, combines multiple 1) or 2) with '( )'. e.g (0,2-4,6)
 353  *    Within group elem, '-' used for a range separator;
 354  *                       ',' used for a single number.
 355  */
 356 static int
 357 parse_queue_set(const char *input, int xtr_type, struct ice_devargs *devargs)
 358 {
 359         const char *str = input;
 360         char *end = NULL;
 361         uint32_t min, max;
 362         uint32_t idx;
 363
 364         while (isblank(*str))
 365                 str++;
 366
 367         if (!isdigit(*str) && *str != '(')
 368                 return -1;
 369
 370         /* process single number or single range of number */
 371         if (*str != '(') {
 372                 errno = 0;
 373                 idx = strtoul(str, &end, 10);
 374                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 375                         return -1;
 376
 377                 while (isblank(*end))
 378                         end++;
 379
 380                 min = idx;
 381                 max = idx;
 382
 383                 /* process single <number>-<number> */
 384                 if (*end == '-') {
 385                         end++;
 386                         while (isblank(*end))
 387                                 end++;
 388                         if (!isdigit(*end))
 389                                 return -1;
 390
 391                         errno = 0;
 392                         idx = strtoul(end, &end, 10);
 393                         if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 394                                 return -1;
 395
 396                         max = idx;
 397                         while (isblank(*end))
 398                                 end++;
 399                 }
 400
 401                 if (*end != ':')
 402                         return -1;
 403
 404                 for (idx = RTE_MIN(min, max);
 405                      idx <= RTE_MAX(min, max); idx++)
 406                         devargs->proto_xtr[idx] = xtr_type;
 407
 408                 return 0;
 409         }
 410
 411         /* process set within bracket */
 412         str++;
 413         while (isblank(*str))
 414                 str++;
 415         if (*str == '\0')
 416                 return -1;
 417
 418         min = ICE_MAX_QUEUE_NUM;
 419         do {
 420                 /* go ahead to the first digit */
 421                 while (isblank(*str))
 422                         str++;
 423                 if (!isdigit(*str))
 424                         return -1;
 425
 426                 /* get the digit value */
 427                 errno = 0;
 428                 idx = strtoul(str, &end, 10);
 429                 if (errno || end == NULL || idx >= ICE_MAX_QUEUE_NUM)
 430                         return -1;
 431
 432                 /* go ahead to separator '-',',' and ')' */
 433                 while (isblank(*end))
 434                         end++;
 435                 if (*end == '-') {
 436                         if (min == ICE_MAX_QUEUE_NUM)
 437                                 min = idx;
 438                         else /* avoid continuous '-' */
 439                                 return -1;
 440                 } else if (*end == ',' || *end == ')') {
 441                         max = idx;
 442                         if (min == ICE_MAX_QUEUE_NUM)
 443                                 min = idx;
 444
 445                         for (idx = RTE_MIN(min, max);
 446                              idx <= RTE_MAX(min, max); idx++)
 447                                 devargs->proto_xtr[idx] = xtr_type;
 448
 449                         min = ICE_MAX_QUEUE_NUM;
 450                 } else {
 451                         return -1;
 452                 }
 453
 454                 str = end + 1;
 455         } while (*end != ')' && *end != '\0');
 456
 457         return 0;
 458 }
 459
 460 static int
 461 parse_queue_proto_xtr(const char *queues, struct ice_devargs *devargs)
 462 {
 463         const char *queue_start;
 464         uint32_t idx;
 465         int xtr_type;
 466         char xtr_name[32];
 467
 468         while (isblank(*queues))
 469                 queues++;
 470
 471         if (*queues != '[') {
 472                 xtr_type = lookup_proto_xtr_type(queues);
 473                 if (xtr_type < 0)
 474                         return -1;
 475
 476                 devargs->proto_xtr_dflt = xtr_type;
 477
 478                 return 0;
 479         }
 480
 481         queues++;
 482         do {
 483                 while (isblank(*queues))
 484                         queues++;
 485                 if (*queues == '\0')
 486                         return -1;
 487
 488                 queue_start = queues;
 489
 490                 /* go across a complete bracket */
 491                 if (*queue_start == '(') {
 492                         queues += strcspn(queues, ")");
 493                         if (*queues != ')')
 494                                 return -1;
 495                 }
 496
 497                 /* scan the separator ':' */
 498                 queues += strcspn(queues, ":");
 499                 if (*queues++ != ':')
 500                         return -1;
 501                 while (isblank(*queues))
 502                         queues++;
 503
 504                 for (idx = 0; ; idx++) {
 505                         if (isblank(queues[idx]) ||
 506                             queues[idx] == ',' ||
 507                             queues[idx] == ']' ||
 508                             queues[idx] == '\0')
 509                                 break;
 510
 511                         if (idx > sizeof(xtr_name) - 2)
 512                                 return -1;
 513
 514                         xtr_name[idx] = queues[idx];
 515                 }
 516                 xtr_name[idx] = '\0';
 517                 xtr_type = lookup_proto_xtr_type(xtr_name);
 518                 if (xtr_type < 0)
 519                         return -1;
 520
 521                 queues += idx;
 522
 523                 while (isblank(*queues) || *queues == ',' || *queues == ']')
 524                         queues++;
 525
 526                 if (parse_queue_set(queue_start, xtr_type, devargs) < 0)
 527                         return -1;
 528         } while (*queues != '\0');
 529
 530         return 0;
 531 }
 532
 533 static int
 534 handle_proto_xtr_arg(__rte_unused const char *key, const char *value,
 535                      void *extra_args)
 536 {
 537         struct ice_devargs *devargs = extra_args;
 538
 539         if (value == NULL || extra_args == NULL)
 540                 return -EINVAL;
 541
 542         if (parse_queue_proto_xtr(value, devargs) < 0) {
 543                 PMD_DRV_LOG(ERR,
 544                             "The protocol extraction parameter is wrong : '%s'",
 545                             value);
 546                 return -1;
 547         }
 548
 549         return 0;
 550 }
 551
 552 static void
 553 ice_check_proto_xtr_support(struct ice_hw *hw)
 554 {
 555 #define FLX_REG(val, fld, idx) \
 556         (((val) & GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_M) >> \
 557          GLFLXP_RXDID_FLX_WRD_##idx##_##fld##_S)
 558         static struct {
 559                 uint32_t rxdid;
 560                 uint8_t opcode;
 561                 uint8_t protid_0;
 562                 uint8_t protid_1;
 563         } xtr_sets[] = {
 564                 [PROTO_XTR_VLAN] = { ICE_RXDID_COMMS_AUX_VLAN,
 565                                      ICE_RX_OPC_EXTRACT,
 566                                      ICE_PROT_EVLAN_O, ICE_PROT_VLAN_O},
 567                 [PROTO_XTR_IPV4] = { ICE_RXDID_COMMS_AUX_IPV4,
 568                                      ICE_RX_OPC_EXTRACT,
 569                                      ICE_PROT_IPV4_OF_OR_S,
 570                                      ICE_PROT_IPV4_OF_OR_S },
 571                 [PROTO_XTR_IPV6] = { ICE_RXDID_COMMS_AUX_IPV6,
 572                                      ICE_RX_OPC_EXTRACT,
 573                                      ICE_PROT_IPV6_OF_OR_S,
 574                                      ICE_PROT_IPV6_OF_OR_S },
 575                 [PROTO_XTR_IPV6_FLOW] = { ICE_RXDID_COMMS_AUX_IPV6_FLOW,
 576                                           ICE_RX_OPC_EXTRACT,
 577                                           ICE_PROT_IPV6_OF_OR_S,
 578                                           ICE_PROT_IPV6_OF_OR_S },
 579                 [PROTO_XTR_TCP] = { ICE_RXDID_COMMS_AUX_TCP,
 580                                     ICE_RX_OPC_EXTRACT,
 581                                     ICE_PROT_TCP_IL, ICE_PROT_ID_INVAL },
 582                 [PROTO_XTR_IP_OFFSET] = { ICE_RXDID_COMMS_AUX_IP_OFFSET,
 583                                           ICE_RX_OPC_PROTID,
 584                                           ICE_PROT_IPV4_OF_OR_S,
 585                                           ICE_PROT_IPV6_OF_OR_S },
 586         };
 587         uint32_t i;
 588
 589         for (i = 0; i < RTE_DIM(xtr_sets); i++) {
 590                 uint32_t rxdid = xtr_sets[i].rxdid;
 591                 uint32_t v;
 592
 593                 if (xtr_sets[i].protid_0 != ICE_PROT_ID_INVAL) {
 594                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_4(rxdid));
 595
 596                         if (FLX_REG(v, PROT_MDID, 4) == xtr_sets[i].protid_0 &&
 597                             FLX_REG(v, RXDID_OPCODE, 4) == xtr_sets[i].opcode)
 598                                 ice_proto_xtr_hw_support[i] = true;
 599                 }
 600
 601                 if (xtr_sets[i].protid_1 != ICE_PROT_ID_INVAL) {
 602                         v = ICE_READ_REG(hw, GLFLXP_RXDID_FLX_WRD_5(rxdid));
 603
 604                         if (FLX_REG(v, PROT_MDID, 5) == xtr_sets[i].protid_1 &&
 605                             FLX_REG(v, RXDID_OPCODE, 5) == xtr_sets[i].opcode)
 606                                 ice_proto_xtr_hw_support[i] = true;
 607                 }
 608         }
 609 }
 610
 611 static int
 612 ice_res_pool_init(struct ice_res_pool_info *pool, uint32_t base,
 613                   uint32_t num)
 614 {
 615         struct pool_entry *entry;
 616
 617         if (!pool || !num)
 618                 return -EINVAL;
 619
 620         entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 621         if (!entry) {
 622                 PMD_INIT_LOG(ERR,
 623                              "Failed to allocate memory for resource pool");
 624                 return -ENOMEM;
 625         }
 626
 627         /* queue heap initialize */
 628         pool->num_free = num;
 629         pool->num_alloc = 0;
 630         pool->base = base;
 631         LIST_INIT(&pool->alloc_list);
 632         LIST_INIT(&pool->free_list);
 633
 634         /* Initialize element  */
 635         entry->base = 0;
 636         entry->len = num;
 637
 638         LIST_INSERT_HEAD(&pool->free_list, entry, next);
 639         return 0;
 640 }
 641
 642 static int
 643 ice_res_pool_alloc(struct ice_res_pool_info *pool,
 644                    uint16_t num)
 645 {
 646         struct pool_entry *entry, *valid_entry;
 647
 648         if (!pool || !num) {
 649                 PMD_INIT_LOG(ERR, "Invalid parameter");
 650                 return -EINVAL;
 651         }
 652
 653         if (pool->num_free < num) {
 654                 PMD_INIT_LOG(ERR, "No resource. ask:%u, available:%u",
 655                              num, pool->num_free);
 656                 return -ENOMEM;
 657         }
 658
 659         valid_entry = NULL;
 660         /* Lookup  in free list and find most fit one */
 661         LIST_FOREACH(entry, &pool->free_list, next) {
 662                 if (entry->len >= num) {
 663                         /* Find best one */
 664                         if (entry->len == num) {
 665                                 valid_entry = entry;
 666                                 break;
 667                         }
 668                         if (!valid_entry ||
 669                             valid_entry->len > entry->len)
 670                                 valid_entry = entry;
 671                 }
 672         }
 673
 674         /* Not find one to satisfy the request, return */
 675         if (!valid_entry) {
 676                 PMD_INIT_LOG(ERR, "No valid entry found");
 677                 return -ENOMEM;
 678         }
 679         /**
 680          * The entry have equal queue number as requested,
 681          * remove it from alloc_list.
 682          */
 683         if (valid_entry->len == num) {
 684                 LIST_REMOVE(valid_entry, next);
 685         } else {
 686                 /**
 687                  * The entry have more numbers than requested,
 688                  * create a new entry for alloc_list and minus its
 689                  * queue base and number in free_list.
 690                  */
 691                 entry = rte_zmalloc(NULL, sizeof(*entry), 0);
 692                 if (!entry) {
 693                         PMD_INIT_LOG(ERR,
 694                                      "Failed to allocate memory for "
 695                                      "resource pool");
 696                         return -ENOMEM;
 697                 }
 698                 entry->base = valid_entry->base;
 699                 entry->len = num;
 700                 valid_entry->base += num;
 701                 valid_entry->len -= num;
 702                 valid_entry = entry;
 703         }
 704
 705         /* Insert it into alloc list, not sorted */
 706         LIST_INSERT_HEAD(&pool->alloc_list, valid_entry, next);
 707
 708         pool->num_free -= valid_entry->len;
 709         pool->num_alloc += valid_entry->len;
 710
 711         return valid_entry->base + pool->base;
 712 }
 713
 714 static void
 715 ice_res_pool_destroy(struct ice_res_pool_info *pool)
 716 {
 717         struct pool_entry *entry, *next_entry;
 718
 719         if (!pool)
 720                 return;
 721
 722         for (entry = LIST_FIRST(&pool->alloc_list);
 723              entry && (next_entry = LIST_NEXT(entry, next), 1);
 724              entry = next_entry) {
 725                 LIST_REMOVE(entry, next);
 726                 rte_free(entry);
 727         }
 728
 729         for (entry = LIST_FIRST(&pool->free_list);
 730              entry && (next_entry = LIST_NEXT(entry, next), 1);
 731              entry = next_entry) {
 732                 LIST_REMOVE(entry, next);
 733                 rte_free(entry);
 734         }
 735
 736         pool->num_free = 0;
 737         pool->num_alloc = 0;
 738         pool->base = 0;
 739         LIST_INIT(&pool->alloc_list);
 740         LIST_INIT(&pool->free_list);
 741 }
 742
 743 static void
 744 ice_vsi_config_default_rss(struct ice_aqc_vsi_props *info)
 745 {
 746         /* Set VSI LUT selection */
 747         info->q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_VSI &
 748                           ICE_AQ_VSI_Q_OPT_RSS_LUT_M;
 749         /* Set Hash scheme */
 750         info->q_opt_rss |= ICE_AQ_VSI_Q_OPT_RSS_TPLZ &
 751                            ICE_AQ_VSI_Q_OPT_RSS_HASH_M;
 752         /* enable TC */
 753         info->q_opt_tc = ICE_AQ_VSI_Q_OPT_TC_OVR_M;
 754 }
 755
 756 static enum ice_status
 757 ice_vsi_config_tc_queue_mapping(struct ice_vsi *vsi,
 758                                 struct ice_aqc_vsi_props *info,
 759                                 uint8_t enabled_tcmap)
 760 {
 761         uint16_t bsf, qp_idx;
 762
 763         /* default tc 0 now. Multi-TC supporting need to be done later.
 764          * Configure TC and queue mapping parameters, for enabled TC,
 765          * allocate qpnum_per_tc queues to this traffic.
 766          */
 767         if (enabled_tcmap != 0x01) {
 768                 PMD_INIT_LOG(ERR, "only TC0 is supported");
 769                 return -ENOTSUP;
 770         }
 771
 772         vsi->nb_qps = RTE_MIN(vsi->nb_qps, ICE_MAX_Q_PER_TC);
 773         bsf = rte_bsf32(vsi->nb_qps);
 774         /* Adjust the queue number to actual queues that can be applied */
 775         vsi->nb_qps = 0x1 << bsf;
 776
 777         qp_idx = 0;
 778         /* Set tc and queue mapping with VSI */
 779         info->tc_mapping[0] = rte_cpu_to_le_16((qp_idx <<
 780                                                 ICE_AQ_VSI_TC_Q_OFFSET_S) |
 781                                                (bsf << ICE_AQ_VSI_TC_Q_NUM_S));
 782
 783         /* Associate queue number with VSI */
 784         info->mapping_flags |= rte_cpu_to_le_16(ICE_AQ_VSI_Q_MAP_CONTIG);
 785         info->q_mapping[0] = rte_cpu_to_le_16(vsi->base_queue);
 786         info->q_mapping[1] = rte_cpu_to_le_16(vsi->nb_qps);
 787         info->valid_sections |=
 788                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_RXQ_MAP_VALID);
 789         /* Set the info.ingress_table and info.egress_table
 790          * for UP translate table. Now just set it to 1:1 map by default
 791          * -- 0b 111 110 101 100 011 010 001 000 == 0xFAC688
 792          */
 793 #define ICE_TC_QUEUE_TABLE_DFLT 0x00FAC688
 794         info->ingress_table  = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 795         info->egress_table   = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 796         info->outer_up_table = rte_cpu_to_le_32(ICE_TC_QUEUE_TABLE_DFLT);
 797         return 0;
 798 }
 799
 800 static int
 801 ice_init_mac_address(struct rte_eth_dev *dev)
 802 {
 803         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
 804
 805         if (!rte_is_unicast_ether_addr
 806                 ((struct rte_ether_addr *)hw->port_info[0].mac.lan_addr)) {
 807                 PMD_INIT_LOG(ERR, "Invalid MAC address");
 808                 return -EINVAL;
 809         }
 810
 811         rte_ether_addr_copy(
 812                 (struct rte_ether_addr *)hw->port_info[0].mac.lan_addr,
 813                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr);
 814
 815         dev->data->mac_addrs =
 816                 rte_zmalloc(NULL, sizeof(struct rte_ether_addr) * ICE_NUM_MACADDR_MAX, 0);
 817         if (!dev->data->mac_addrs) {
 818                 PMD_INIT_LOG(ERR,
 819                              "Failed to allocate memory to store mac address");
 820                 return -ENOMEM;
 821         }
 822         /* store it to dev data */
 823         rte_ether_addr_copy(
 824                 (struct rte_ether_addr *)hw->port_info[0].mac.perm_addr,
 825                 &dev->data->mac_addrs[0]);
 826         return 0;
 827 }
 828
 829 /* Find out specific MAC filter */
 830 static struct ice_mac_filter *
 831 ice_find_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *macaddr)
 832 {
 833         struct ice_mac_filter *f;
 834
 835         TAILQ_FOREACH(f, &vsi->mac_list, next) {
 836                 if (rte_is_same_ether_addr(macaddr, &f->mac_info.mac_addr))
 837                         return f;
 838         }
 839
 840         return NULL;
 841 }
 842
 843 static int
 844 ice_add_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 845 {
 846         struct ice_fltr_list_entry *m_list_itr = NULL;
 847         struct ice_mac_filter *f;
 848         struct LIST_HEAD_TYPE list_head;
 849         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 850         int ret = 0;
 851
 852         /* If it's added and configured, return */
 853         f = ice_find_mac_filter(vsi, mac_addr);
 854         if (f) {
 855                 PMD_DRV_LOG(INFO, "This MAC filter already exists.");
 856                 return 0;
 857         }
 858
 859         INIT_LIST_HEAD(&list_head);
 860
 861         m_list_itr = (struct ice_fltr_list_entry *)
 862                 ice_malloc(hw, sizeof(*m_list_itr));
 863         if (!m_list_itr) {
 864                 ret = -ENOMEM;
 865                 goto DONE;
 866         }
 867         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 868                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 869         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 870         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 871         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 872         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 873         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 874
 875         LIST_ADD(&m_list_itr->list_entry, &list_head);
 876
 877         /* Add the mac */
 878         ret = ice_add_mac(hw, &list_head);
 879         if (ret != ICE_SUCCESS) {
 880                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
 881                 ret = -EINVAL;
 882                 goto DONE;
 883         }
 884         /* Add the mac addr into mac list */
 885         f = rte_zmalloc(NULL, sizeof(*f), 0);
 886         if (!f) {
 887                 PMD_DRV_LOG(ERR, "failed to allocate memory");
 888                 ret = -ENOMEM;
 889                 goto DONE;
 890         }
 891         rte_ether_addr_copy(mac_addr, &f->mac_info.mac_addr);
 892         TAILQ_INSERT_TAIL(&vsi->mac_list, f, next);
 893         vsi->mac_num++;
 894
 895         ret = 0;
 896
 897 DONE:
 898         rte_free(m_list_itr);
 899         return ret;
 900 }
 901
 902 static int
 903 ice_remove_mac_filter(struct ice_vsi *vsi, struct rte_ether_addr *mac_addr)
 904 {
 905         struct ice_fltr_list_entry *m_list_itr = NULL;
 906         struct ice_mac_filter *f;
 907         struct LIST_HEAD_TYPE list_head;
 908         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
 909         int ret = 0;
 910
 911         /* Can't find it, return an error */
 912         f = ice_find_mac_filter(vsi, mac_addr);
 913         if (!f)
 914                 return -EINVAL;
 915
 916         INIT_LIST_HEAD(&list_head);
 917
 918         m_list_itr = (struct ice_fltr_list_entry *)
 919                 ice_malloc(hw, sizeof(*m_list_itr));
 920         if (!m_list_itr) {
 921                 ret = -ENOMEM;
 922                 goto DONE;
 923         }
 924         ice_memcpy(m_list_itr->fltr_info.l_data.mac.mac_addr,
 925                    mac_addr, ETH_ALEN, ICE_NONDMA_TO_NONDMA);
 926         m_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
 927         m_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
 928         m_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_MAC;
 929         m_list_itr->fltr_info.flag = ICE_FLTR_TX;
 930         m_list_itr->fltr_info.vsi_handle = vsi->idx;
 931
 932         LIST_ADD(&m_list_itr->list_entry, &list_head);
 933
 934         /* remove the mac filter */
 935         ret = ice_remove_mac(hw, &list_head);
 936         if (ret != ICE_SUCCESS) {
 937                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
 938                 ret = -EINVAL;
 939                 goto DONE;
 940         }
 941
 942         /* Remove the mac addr from mac list */
 943         TAILQ_REMOVE(&vsi->mac_list, f, next);
 944         rte_free(f);
 945         vsi->mac_num--;
 946
 947         ret = 0;
 948 DONE:
 949         rte_free(m_list_itr);
 950         return ret;
 951 }
 952
 953 /* Find out specific VLAN filter */
 954 static struct ice_vlan_filter *
 955 ice_find_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 956 {
 957         struct ice_vlan_filter *f;
 958
 959         TAILQ_FOREACH(f, &vsi->vlan_list, next) {
 960                 if (vlan->tpid == f->vlan_info.vlan.tpid &&
 961                     vlan->vid == f->vlan_info.vlan.vid)
 962                         return f;
 963         }
 964
 965         return NULL;
 966 }
 967
 968 static int
 969 ice_add_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
 970 {
 971         struct ice_fltr_list_entry *v_list_itr = NULL;
 972         struct ice_vlan_filter *f;
 973         struct LIST_HEAD_TYPE list_head;
 974         struct ice_hw *hw;
 975         int ret = 0;
 976
 977         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
 978                 return -EINVAL;
 979
 980         hw = ICE_VSI_TO_HW(vsi);
 981
 982         /* If it's added and configured, return. */
 983         f = ice_find_vlan_filter(vsi, vlan);
 984         if (f) {
 985                 PMD_DRV_LOG(INFO, "This VLAN filter already exists.");
 986                 return 0;
 987         }
 988
 989         if (!vsi->vlan_anti_spoof_on && !vsi->vlan_filter_on)
 990                 return 0;
 991
 992         INIT_LIST_HEAD(&list_head);
 993
 994         v_list_itr = (struct ice_fltr_list_entry *)
 995                       ice_malloc(hw, sizeof(*v_list_itr));
 996         if (!v_list_itr) {
 997                 ret = -ENOMEM;
 998                 goto DONE;
 999         }
1000         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1001         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1002         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1003         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1004         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1005         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1006         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1007         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1008
1009         LIST_ADD(&v_list_itr->list_entry, &list_head);
1010
1011         /* Add the vlan */
1012         ret = ice_add_vlan(hw, &list_head);
1013         if (ret != ICE_SUCCESS) {
1014                 PMD_DRV_LOG(ERR, "Failed to add VLAN filter");
1015                 ret = -EINVAL;
1016                 goto DONE;
1017         }
1018
1019         /* Add vlan into vlan list */
1020         f = rte_zmalloc(NULL, sizeof(*f), 0);
1021         if (!f) {
1022                 PMD_DRV_LOG(ERR, "failed to allocate memory");
1023                 ret = -ENOMEM;
1024                 goto DONE;
1025         }
1026         f->vlan_info.vlan.tpid = vlan->tpid;
1027         f->vlan_info.vlan.vid = vlan->vid;
1028         TAILQ_INSERT_TAIL(&vsi->vlan_list, f, next);
1029         vsi->vlan_num++;
1030
1031         ret = 0;
1032
1033 DONE:
1034         rte_free(v_list_itr);
1035         return ret;
1036 }
1037
1038 static int
1039 ice_remove_vlan_filter(struct ice_vsi *vsi, struct ice_vlan *vlan)
1040 {
1041         struct ice_fltr_list_entry *v_list_itr = NULL;
1042         struct ice_vlan_filter *f;
1043         struct LIST_HEAD_TYPE list_head;
1044         struct ice_hw *hw;
1045         int ret = 0;
1046
1047         if (!vsi || vlan->vid > RTE_ETHER_MAX_VLAN_ID)
1048                 return -EINVAL;
1049
1050         hw = ICE_VSI_TO_HW(vsi);
1051
1052         /* Can't find it, return an error */
1053         f = ice_find_vlan_filter(vsi, vlan);
1054         if (!f)
1055                 return -EINVAL;
1056
1057         INIT_LIST_HEAD(&list_head);
1058
1059         v_list_itr = (struct ice_fltr_list_entry *)
1060                       ice_malloc(hw, sizeof(*v_list_itr));
1061         if (!v_list_itr) {
1062                 ret = -ENOMEM;
1063                 goto DONE;
1064         }
1065
1066         v_list_itr->fltr_info.l_data.vlan.vlan_id = vlan->vid;
1067         v_list_itr->fltr_info.l_data.vlan.tpid = vlan->tpid;
1068         v_list_itr->fltr_info.l_data.vlan.tpid_valid = true;
1069         v_list_itr->fltr_info.src_id = ICE_SRC_ID_VSI;
1070         v_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1071         v_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_VLAN;
1072         v_list_itr->fltr_info.flag = ICE_FLTR_TX;
1073         v_list_itr->fltr_info.vsi_handle = vsi->idx;
1074
1075         LIST_ADD(&v_list_itr->list_entry, &list_head);
1076
1077         /* remove the vlan filter */
1078         ret = ice_remove_vlan(hw, &list_head);
1079         if (ret != ICE_SUCCESS) {
1080                 PMD_DRV_LOG(ERR, "Failed to remove VLAN filter");
1081                 ret = -EINVAL;
1082                 goto DONE;
1083         }
1084
1085         /* Remove the vlan id from vlan list */
1086         TAILQ_REMOVE(&vsi->vlan_list, f, next);
1087         rte_free(f);
1088         vsi->vlan_num--;
1089
1090         ret = 0;
1091 DONE:
1092         rte_free(v_list_itr);
1093         return ret;
1094 }
1095
1096 static int
1097 ice_remove_all_mac_vlan_filters(struct ice_vsi *vsi)
1098 {
1099         struct ice_mac_filter *m_f;
1100         struct ice_vlan_filter *v_f;
1101         void *temp;
1102         int ret = 0;
1103
1104         if (!vsi || !vsi->mac_num)
1105                 return -EINVAL;
1106
1107         TAILQ_FOREACH_SAFE(m_f, &vsi->mac_list, next, temp) {
1108                 ret = ice_remove_mac_filter(vsi, &m_f->mac_info.mac_addr);
1109                 if (ret != ICE_SUCCESS) {
1110                         ret = -EINVAL;
1111                         goto DONE;
1112                 }
1113         }
1114
1115         if (vsi->vlan_num == 0)
1116                 return 0;
1117
1118         TAILQ_FOREACH_SAFE(v_f, &vsi->vlan_list, next, temp) {
1119                 ret = ice_remove_vlan_filter(vsi, &v_f->vlan_info.vlan);
1120                 if (ret != ICE_SUCCESS) {
1121                         ret = -EINVAL;
1122                         goto DONE;
1123                 }
1124         }
1125
1126 DONE:
1127         return ret;
1128 }
1129
1130 /* Enable IRQ0 */
1131 static void
1132 ice_pf_enable_irq0(struct ice_hw *hw)
1133 {
1134         /* reset the registers */
1135         ICE_WRITE_REG(hw, PFINT_OICR_ENA, 0);
1136         ICE_READ_REG(hw, PFINT_OICR);
1137
1138 #ifdef ICE_LSE_SPT
1139         ICE_WRITE_REG(hw, PFINT_OICR_ENA,
1140                       (uint32_t)(PFINT_OICR_ENA_INT_ENA_M &
1141                                  (~PFINT_OICR_LINK_STAT_CHANGE_M)));
1142
1143         ICE_WRITE_REG(hw, PFINT_OICR_CTL,
1144                       (0 & PFINT_OICR_CTL_MSIX_INDX_M) |
1145                       ((0 << PFINT_OICR_CTL_ITR_INDX_S) &
1146                        PFINT_OICR_CTL_ITR_INDX_M) |
1147                       PFINT_OICR_CTL_CAUSE_ENA_M);
1148
1149         ICE_WRITE_REG(hw, PFINT_FW_CTL,
1150                       (0 & PFINT_FW_CTL_MSIX_INDX_M) |
1151                       ((0 << PFINT_FW_CTL_ITR_INDX_S) &
1152                        PFINT_FW_CTL_ITR_INDX_M) |
1153                       PFINT_FW_CTL_CAUSE_ENA_M);
1154 #else
1155         ICE_WRITE_REG(hw, PFINT_OICR_ENA, PFINT_OICR_ENA_INT_ENA_M);
1156 #endif
1157
1158         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
1159                       GLINT_DYN_CTL_INTENA_M |
1160                       GLINT_DYN_CTL_CLEARPBA_M |
1161                       GLINT_DYN_CTL_ITR_INDX_M);
1162
1163         ice_flush(hw);
1164 }
1165
1166 /* Disable IRQ0 */
1167 static void
1168 ice_pf_disable_irq0(struct ice_hw *hw)
1169 {
1170         /* Disable all interrupt types */
1171         ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
1172         ice_flush(hw);
1173 }
1174
1175 #ifdef ICE_LSE_SPT
1176 static void
1177 ice_handle_aq_msg(struct rte_eth_dev *dev)
1178 {
1179         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1180         struct ice_ctl_q_info *cq = &hw->adminq;
1181         struct ice_rq_event_info event;
1182         uint16_t pending, opcode;
1183         int ret;
1184
1185         event.buf_len = ICE_AQ_MAX_BUF_LEN;
1186         event.msg_buf = rte_zmalloc(NULL, event.buf_len, 0);
1187         if (!event.msg_buf) {
1188                 PMD_DRV_LOG(ERR, "Failed to allocate mem");
1189                 return;
1190         }
1191
1192         pending = 1;
1193         while (pending) {
1194                 ret = ice_clean_rq_elem(hw, cq, &event, &pending);
1195
1196                 if (ret != ICE_SUCCESS) {
1197                         PMD_DRV_LOG(INFO,
1198                                     "Failed to read msg from AdminQ, "
1199                                     "adminq_err: %u",
1200                                     hw->adminq.sq_last_status);
1201                         break;
1202                 }
1203                 opcode = rte_le_to_cpu_16(event.desc.opcode);
1204
1205                 switch (opcode) {
1206                 case ice_aqc_opc_get_link_status:
1207                         ret = ice_link_update(dev, 0);
1208                         if (!ret)
1209                                 rte_eth_dev_callback_process
1210                                         (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1211                         break;
1212                 default:
1213                         PMD_DRV_LOG(DEBUG, "Request %u is not supported yet",
1214                                     opcode);
1215                         break;
1216                 }
1217         }
1218         rte_free(event.msg_buf);
1219 }
1220 #endif
1221
1222 /**
1223  * Interrupt handler triggered by NIC for handling
1224  * specific interrupt.
1225  *
1226  * @param handle
1227  *  Pointer to interrupt handle.
1228  * @param param
1229  *  The address of parameter (struct rte_eth_dev *) regsitered before.
1230  *
1231  * @return
1232  *  void
1233  */
1234 static void
1235 ice_interrupt_handler(void *param)
1236 {
1237         struct rte_eth_dev *dev = (struct rte_eth_dev *)param;
1238         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1239         uint32_t oicr;
1240         uint32_t reg;
1241         uint8_t pf_num;
1242         uint8_t event;
1243         uint16_t queue;
1244         int ret;
1245 #ifdef ICE_LSE_SPT
1246         uint32_t int_fw_ctl;
1247 #endif
1248
1249         /* Disable interrupt */
1250         ice_pf_disable_irq0(hw);
1251
1252         /* read out interrupt causes */
1253         oicr = ICE_READ_REG(hw, PFINT_OICR);
1254 #ifdef ICE_LSE_SPT
1255         int_fw_ctl = ICE_READ_REG(hw, PFINT_FW_CTL);
1256 #endif
1257
1258         /* No interrupt event indicated */
1259         if (!(oicr & PFINT_OICR_INTEVENT_M)) {
1260                 PMD_DRV_LOG(INFO, "No interrupt event");
1261                 goto done;
1262         }
1263
1264 #ifdef ICE_LSE_SPT
1265         if (int_fw_ctl & PFINT_FW_CTL_INTEVENT_M) {
1266                 PMD_DRV_LOG(INFO, "FW_CTL: link state change event");
1267                 ice_handle_aq_msg(dev);
1268         }
1269 #else
1270         if (oicr & PFINT_OICR_LINK_STAT_CHANGE_M) {
1271                 PMD_DRV_LOG(INFO, "OICR: link state change event");
1272                 ret = ice_link_update(dev, 0);
1273                 if (!ret)
1274                         rte_eth_dev_callback_process
1275                                 (dev, RTE_ETH_EVENT_INTR_LSC, NULL);
1276         }
1277 #endif
1278
1279         if (oicr & PFINT_OICR_MAL_DETECT_M) {
1280                 PMD_DRV_LOG(WARNING, "OICR: MDD event");
1281                 reg = ICE_READ_REG(hw, GL_MDET_TX_PQM);
1282                 if (reg & GL_MDET_TX_PQM_VALID_M) {
1283                         pf_num = (reg & GL_MDET_TX_PQM_PF_NUM_M) >>
1284                                  GL_MDET_TX_PQM_PF_NUM_S;
1285                         event = (reg & GL_MDET_TX_PQM_MAL_TYPE_M) >>
1286                                 GL_MDET_TX_PQM_MAL_TYPE_S;
1287                         queue = (reg & GL_MDET_TX_PQM_QNUM_M) >>
1288                                 GL_MDET_TX_PQM_QNUM_S;
1289
1290                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1291                                     "%d by PQM on TX queue %d PF# %d",
1292                                     event, queue, pf_num);
1293                 }
1294
1295                 reg = ICE_READ_REG(hw, GL_MDET_TX_TCLAN);
1296                 if (reg & GL_MDET_TX_TCLAN_VALID_M) {
1297                         pf_num = (reg & GL_MDET_TX_TCLAN_PF_NUM_M) >>
1298                                  GL_MDET_TX_TCLAN_PF_NUM_S;
1299                         event = (reg & GL_MDET_TX_TCLAN_MAL_TYPE_M) >>
1300                                 GL_MDET_TX_TCLAN_MAL_TYPE_S;
1301                         queue = (reg & GL_MDET_TX_TCLAN_QNUM_M) >>
1302                                 GL_MDET_TX_TCLAN_QNUM_S;
1303
1304                         PMD_DRV_LOG(WARNING, "Malicious Driver Detection event "
1305                                     "%d by TCLAN on TX queue %d PF# %d",
1306                                     event, queue, pf_num);
1307                 }
1308         }
1309 done:
1310         /* Enable interrupt */
1311         ice_pf_enable_irq0(hw);
1312         rte_intr_ack(dev->intr_handle);
1313 }
1314
1315 static void
1316 ice_init_proto_xtr(struct rte_eth_dev *dev)
1317 {
1318         struct ice_adapter *ad =
1319                         ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1320         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1321         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1322         const struct proto_xtr_ol_flag *ol_flag;
1323         bool proto_xtr_enable = false;
1324         int offset;
1325         uint16_t i;
1326
1327         pf->proto_xtr = rte_zmalloc(NULL, pf->lan_nb_qps, 0);
1328         if (unlikely(pf->proto_xtr == NULL)) {
1329                 PMD_DRV_LOG(ERR, "No memory for setting up protocol extraction table");
1330                 return;
1331         }
1332
1333         for (i = 0; i < pf->lan_nb_qps; i++) {
1334                 pf->proto_xtr[i] = ad->devargs.proto_xtr[i] != PROTO_XTR_NONE ?
1335                                    ad->devargs.proto_xtr[i] :
1336                                    ad->devargs.proto_xtr_dflt;
1337
1338                 if (pf->proto_xtr[i] != PROTO_XTR_NONE) {
1339                         uint8_t type = pf->proto_xtr[i];
1340
1341                         ice_proto_xtr_ol_flag_params[type].required = true;
1342                         proto_xtr_enable = true;
1343                 }
1344         }
1345
1346         if (likely(!proto_xtr_enable))
1347                 return;
1348
1349         ice_check_proto_xtr_support(hw);
1350
1351         offset = rte_mbuf_dynfield_register(&ice_proto_xtr_metadata_param);
1352         if (unlikely(offset == -1)) {
1353                 PMD_DRV_LOG(ERR,
1354                             "Protocol extraction metadata is disabled in mbuf with error %d",
1355                             -rte_errno);
1356                 return;
1357         }
1358
1359         PMD_DRV_LOG(DEBUG,
1360                     "Protocol extraction metadata offset in mbuf is : %d",
1361                     offset);
1362         rte_net_ice_dynfield_proto_xtr_metadata_offs = offset;
1363
1364         for (i = 0; i < RTE_DIM(ice_proto_xtr_ol_flag_params); i++) {
1365                 ol_flag = &ice_proto_xtr_ol_flag_params[i];
1366
1367                 if (!ol_flag->required)
1368                         continue;
1369
1370                 if (!ice_proto_xtr_hw_support[i]) {
1371                         PMD_DRV_LOG(ERR,
1372                                     "Protocol extraction type %u is not supported in hardware",
1373                                     i);
1374                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1375                         break;
1376                 }
1377
1378                 offset = rte_mbuf_dynflag_register(&ol_flag->param);
1379                 if (unlikely(offset == -1)) {
1380                         PMD_DRV_LOG(ERR,
1381                                     "Protocol extraction offload '%s' failed to register with error %d",
1382                                     ol_flag->param.name, -rte_errno);
1383
1384                         rte_net_ice_dynfield_proto_xtr_metadata_offs = -1;
1385                         break;
1386                 }
1387
1388                 PMD_DRV_LOG(DEBUG,
1389                             "Protocol extraction offload '%s' offset in mbuf is : %d",
1390                             ol_flag->param.name, offset);
1391                 *ol_flag->ol_flag = 1ULL << offset;
1392         }
1393 }
1394
1395 /*  Initialize SW parameters of PF */
1396 static int
1397 ice_pf_sw_init(struct rte_eth_dev *dev)
1398 {
1399         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1400         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1401
1402         pf->lan_nb_qp_max =
1403                 (uint16_t)RTE_MIN(hw->func_caps.common_cap.num_txq,
1404                                   hw->func_caps.common_cap.num_rxq);
1405
1406         pf->lan_nb_qps = pf->lan_nb_qp_max;
1407
1408         ice_init_proto_xtr(dev);
1409
1410         if (hw->func_caps.fd_fltr_guar > 0 ||
1411             hw->func_caps.fd_fltr_best_effort > 0) {
1412                 pf->flags |= ICE_FLAG_FDIR;
1413                 pf->fdir_nb_qps = ICE_DEFAULT_QP_NUM_FDIR;
1414                 pf->lan_nb_qps = pf->lan_nb_qp_max - pf->fdir_nb_qps;
1415         } else {
1416                 pf->fdir_nb_qps = 0;
1417         }
1418         pf->fdir_qp_offset = 0;
1419
1420         return 0;
1421 }
1422
1423 struct ice_vsi *
1424 ice_setup_vsi(struct ice_pf *pf, enum ice_vsi_type type)
1425 {
1426         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1427         struct ice_vsi *vsi = NULL;
1428         struct ice_vsi_ctx vsi_ctx;
1429         int ret;
1430         struct rte_ether_addr broadcast = {
1431                 .addr_bytes = {0xff, 0xff, 0xff, 0xff, 0xff, 0xff} };
1432         struct rte_ether_addr mac_addr;
1433         uint16_t max_txqs[ICE_MAX_TRAFFIC_CLASS] = { 0 };
1434         uint8_t tc_bitmap = 0x1;
1435         uint16_t cfg;
1436
1437         /* hw->num_lports = 1 in NIC mode */
1438         vsi = rte_zmalloc(NULL, sizeof(struct ice_vsi), 0);
1439         if (!vsi)
1440                 return NULL;
1441
1442         vsi->idx = pf->next_vsi_idx;
1443         pf->next_vsi_idx++;
1444         vsi->type = type;
1445         vsi->adapter = ICE_PF_TO_ADAPTER(pf);
1446         vsi->max_macaddrs = ICE_NUM_MACADDR_MAX;
1447         vsi->vlan_anti_spoof_on = 0;
1448         vsi->vlan_filter_on = 1;
1449         TAILQ_INIT(&vsi->mac_list);
1450         TAILQ_INIT(&vsi->vlan_list);
1451
1452         /* Be sync with ETH_RSS_RETA_SIZE_x maximum value definition */
1453         pf->hash_lut_size = hw->func_caps.common_cap.rss_table_size >
1454                         ETH_RSS_RETA_SIZE_512 ? ETH_RSS_RETA_SIZE_512 :
1455                         hw->func_caps.common_cap.rss_table_size;
1456         pf->flags |= ICE_FLAG_RSS_AQ_CAPABLE;
1457
1458         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
1459         switch (type) {
1460         case ICE_VSI_PF:
1461                 vsi->nb_qps = pf->lan_nb_qps;
1462                 vsi->base_queue = 1;
1463                 ice_vsi_config_default_rss(&vsi_ctx.info);
1464                 vsi_ctx.alloc_from_pool = true;
1465                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1466                 /* switch_id is queried by get_switch_config aq, which is done
1467                  * by ice_init_hw
1468                  */
1469                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1470                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1471                 /* Allow all untagged or tagged packets */
1472                 vsi_ctx.info.inner_vlan_flags = ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
1473                 vsi_ctx.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
1474                 vsi_ctx.info.q_opt_rss = ICE_AQ_VSI_Q_OPT_RSS_LUT_PF |
1475                                          ICE_AQ_VSI_Q_OPT_RSS_TPLZ;
1476                 if (ice_is_dvm_ena(hw)) {
1477                         vsi_ctx.info.outer_vlan_flags =
1478                                 (ICE_AQ_VSI_OUTER_VLAN_TX_MODE_ALL <<
1479                                  ICE_AQ_VSI_OUTER_VLAN_TX_MODE_S) &
1480                                 ICE_AQ_VSI_OUTER_VLAN_TX_MODE_M;
1481                         vsi_ctx.info.outer_vlan_flags |=
1482                                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
1483                                  ICE_AQ_VSI_OUTER_TAG_TYPE_S) &
1484                                 ICE_AQ_VSI_OUTER_TAG_TYPE_M;
1485                 }
1486
1487                 /* FDIR */
1488                 cfg = ICE_AQ_VSI_PROP_SECURITY_VALID |
1489                         ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1490                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1491                 cfg = ICE_AQ_VSI_FD_ENABLE;
1492                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1493                 vsi_ctx.info.max_fd_fltr_dedicated =
1494                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_guar);
1495                 vsi_ctx.info.max_fd_fltr_shared =
1496                         rte_cpu_to_le_16(hw->func_caps.fd_fltr_best_effort);
1497
1498                 /* Enable VLAN/UP trip */
1499                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1500                                                       &vsi_ctx.info,
1501                                                       ICE_DEFAULT_TCMAP);
1502                 if (ret) {
1503                         PMD_INIT_LOG(ERR,
1504                                      "tc queue mapping with vsi failed, "
1505                                      "err = %d",
1506                                      ret);
1507                         goto fail_mem;
1508                 }
1509
1510                 break;
1511         case ICE_VSI_CTRL:
1512                 vsi->nb_qps = pf->fdir_nb_qps;
1513                 vsi->base_queue = ICE_FDIR_QUEUE_ID;
1514                 vsi_ctx.alloc_from_pool = true;
1515                 vsi_ctx.flags = ICE_AQ_VSI_TYPE_PF;
1516
1517                 cfg = ICE_AQ_VSI_PROP_FLOW_DIR_VALID;
1518                 vsi_ctx.info.valid_sections |= rte_cpu_to_le_16(cfg);
1519                 cfg = ICE_AQ_VSI_FD_PROG_ENABLE;
1520                 vsi_ctx.info.fd_options = rte_cpu_to_le_16(cfg);
1521                 vsi_ctx.info.sw_id = hw->port_info->sw_id;
1522                 vsi_ctx.info.sw_flags2 = ICE_AQ_VSI_SW_FLAG_LAN_ENA;
1523                 ret = ice_vsi_config_tc_queue_mapping(vsi,
1524                                                       &vsi_ctx.info,
1525                                                       ICE_DEFAULT_TCMAP);
1526                 if (ret) {
1527                         PMD_INIT_LOG(ERR,
1528                                      "tc queue mapping with vsi failed, "
1529                                      "err = %d",
1530                                      ret);
1531                         goto fail_mem;
1532                 }
1533                 break;
1534         default:
1535                 /* for other types of VSI */
1536                 PMD_INIT_LOG(ERR, "other types of VSI not supported");
1537                 goto fail_mem;
1538         }
1539
1540         /* VF has MSIX interrupt in VF range, don't allocate here */
1541         if (type == ICE_VSI_PF) {
1542                 ret = ice_res_pool_alloc(&pf->msix_pool,
1543                                          RTE_MIN(vsi->nb_qps,
1544                                                  RTE_MAX_RXTX_INTR_VEC_ID));
1545                 if (ret < 0) {
1546                         PMD_INIT_LOG(ERR, "VSI MAIN %d get heap failed %d",
1547                                      vsi->vsi_id, ret);
1548                 }
1549                 vsi->msix_intr = ret;
1550                 vsi->nb_msix = RTE_MIN(vsi->nb_qps, RTE_MAX_RXTX_INTR_VEC_ID);
1551         } else if (type == ICE_VSI_CTRL) {
1552                 ret = ice_res_pool_alloc(&pf->msix_pool, 1);
1553                 if (ret < 0) {
1554                         PMD_DRV_LOG(ERR, "VSI %d get heap failed %d",
1555                                     vsi->vsi_id, ret);
1556                 }
1557                 vsi->msix_intr = ret;
1558                 vsi->nb_msix = 1;
1559         } else {
1560                 vsi->msix_intr = 0;
1561                 vsi->nb_msix = 0;
1562         }
1563         ret = ice_add_vsi(hw, vsi->idx, &vsi_ctx, NULL);
1564         if (ret != ICE_SUCCESS) {
1565                 PMD_INIT_LOG(ERR, "add vsi failed, err = %d", ret);
1566                 goto fail_mem;
1567         }
1568         /* store vsi information is SW structure */
1569         vsi->vsi_id = vsi_ctx.vsi_num;
1570         vsi->info = vsi_ctx.info;
1571         pf->vsis_allocated = vsi_ctx.vsis_allocd;
1572         pf->vsis_unallocated = vsi_ctx.vsis_unallocated;
1573
1574         if (type == ICE_VSI_PF) {
1575                 /* MAC configuration */
1576                 rte_ether_addr_copy((struct rte_ether_addr *)
1577                                         hw->port_info->mac.perm_addr,
1578                                     &pf->dev_addr);
1579
1580                 rte_ether_addr_copy(&pf->dev_addr, &mac_addr);
1581                 ret = ice_add_mac_filter(vsi, &mac_addr);
1582                 if (ret != ICE_SUCCESS)
1583                         PMD_INIT_LOG(ERR, "Failed to add dflt MAC filter");
1584
1585                 rte_ether_addr_copy(&broadcast, &mac_addr);
1586                 ret = ice_add_mac_filter(vsi, &mac_addr);
1587                 if (ret != ICE_SUCCESS)
1588                         PMD_INIT_LOG(ERR, "Failed to add MAC filter");
1589         }
1590
1591         /* At the beginning, only TC0. */
1592         /* What we need here is the maximam number of the TX queues.
1593          * Currently vsi->nb_qps means it.
1594          * Correct it if any change.
1595          */
1596         max_txqs[0] = vsi->nb_qps;
1597         ret = ice_cfg_vsi_lan(hw->port_info, vsi->idx,
1598                               tc_bitmap, max_txqs);
1599         if (ret != ICE_SUCCESS)
1600                 PMD_INIT_LOG(ERR, "Failed to config vsi sched");
1601
1602         return vsi;
1603 fail_mem:
1604         rte_free(vsi);
1605         pf->next_vsi_idx--;
1606         return NULL;
1607 }
1608
1609 static int
1610 ice_send_driver_ver(struct ice_hw *hw)
1611 {
1612         struct ice_driver_ver dv;
1613
1614         /* we don't have driver version use 0 for dummy */
1615         dv.major_ver = 0;
1616         dv.minor_ver = 0;
1617         dv.build_ver = 0;
1618         dv.subbuild_ver = 0;
1619         strncpy((char *)dv.driver_string, "dpdk", sizeof(dv.driver_string));
1620
1621         return ice_aq_send_driver_ver(hw, &dv, NULL);
1622 }
1623
1624 static int
1625 ice_pf_setup(struct ice_pf *pf)
1626 {
1627         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1628         struct ice_vsi *vsi;
1629         uint16_t unused;
1630
1631         /* Clear all stats counters */
1632         pf->offset_loaded = false;
1633         memset(&pf->stats, 0, sizeof(struct ice_hw_port_stats));
1634         memset(&pf->stats_offset, 0, sizeof(struct ice_hw_port_stats));
1635         memset(&pf->internal_stats, 0, sizeof(struct ice_eth_stats));
1636         memset(&pf->internal_stats_offset, 0, sizeof(struct ice_eth_stats));
1637
1638         /* force guaranteed filter pool for PF */
1639         ice_alloc_fd_guar_item(hw, &unused,
1640                                hw->func_caps.fd_fltr_guar);
1641         /* force shared filter pool for PF */
1642         ice_alloc_fd_shrd_item(hw, &unused,
1643                                hw->func_caps.fd_fltr_best_effort);
1644
1645         vsi = ice_setup_vsi(pf, ICE_VSI_PF);
1646         if (!vsi) {
1647                 PMD_INIT_LOG(ERR, "Failed to add vsi for PF");
1648                 return -EINVAL;
1649         }
1650
1651         pf->main_vsi = vsi;
1652
1653         return 0;
1654 }
1655
1656 static enum ice_pkg_type
1657 ice_load_pkg_type(struct ice_hw *hw)
1658 {
1659         enum ice_pkg_type package_type;
1660
1661         /* store the activated package type (OS default or Comms) */
1662         if (!strncmp((char *)hw->active_pkg_name, ICE_OS_DEFAULT_PKG_NAME,
1663                 ICE_PKG_NAME_SIZE))
1664                 package_type = ICE_PKG_TYPE_OS_DEFAULT;
1665         else if (!strncmp((char *)hw->active_pkg_name, ICE_COMMS_PKG_NAME,
1666                 ICE_PKG_NAME_SIZE))
1667                 package_type = ICE_PKG_TYPE_COMMS;
1668         else
1669                 package_type = ICE_PKG_TYPE_UNKNOWN;
1670
1671         PMD_INIT_LOG(NOTICE, "Active package is: %d.%d.%d.%d, %s (%s VLAN mode)",
1672                 hw->active_pkg_ver.major, hw->active_pkg_ver.minor,
1673                 hw->active_pkg_ver.update, hw->active_pkg_ver.draft,
1674                 hw->active_pkg_name,
1675                 ice_is_dvm_ena(hw) ? "double" : "single");
1676
1677         return package_type;
1678 }
1679
1680 int ice_load_pkg(struct ice_adapter *adapter, bool use_dsn, uint64_t dsn)
1681 {
1682         struct ice_hw *hw = &adapter->hw;
1683         char pkg_file[ICE_MAX_PKG_FILENAME_SIZE];
1684         char opt_ddp_filename[ICE_MAX_PKG_FILENAME_SIZE];
1685         void *buf;
1686         size_t bufsz;
1687         int err;
1688
1689         if (!use_dsn)
1690                 goto no_dsn;
1691
1692         memset(opt_ddp_filename, 0, ICE_MAX_PKG_FILENAME_SIZE);
1693         snprintf(opt_ddp_filename, ICE_MAX_PKG_FILENAME_SIZE,
1694                 "ice-%016" PRIx64 ".pkg", dsn);
1695         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_UPDATES,
1696                 ICE_MAX_PKG_FILENAME_SIZE);
1697         strcat(pkg_file, opt_ddp_filename);
1698         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1699                 goto load_fw;
1700
1701         strncpy(pkg_file, ICE_PKG_FILE_SEARCH_PATH_DEFAULT,
1702                 ICE_MAX_PKG_FILENAME_SIZE);
1703         strcat(pkg_file, opt_ddp_filename);
1704         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1705                 goto load_fw;
1706
1707 no_dsn:
1708         strncpy(pkg_file, ICE_PKG_FILE_UPDATES, ICE_MAX_PKG_FILENAME_SIZE);
1709         if (rte_firmware_read(pkg_file, &buf, &bufsz) == 0)
1710                 goto load_fw;
1711
1712         strncpy(pkg_file, ICE_PKG_FILE_DEFAULT, ICE_MAX_PKG_FILENAME_SIZE);
1713         if (rte_firmware_read(pkg_file, &buf, &bufsz) < 0) {
1714                 PMD_INIT_LOG(ERR, "failed to search file path\n");
1715                 return -1;
1716         }
1717
1718 load_fw:
1719         PMD_INIT_LOG(DEBUG, "DDP package name: %s", pkg_file);
1720
1721         err = ice_copy_and_init_pkg(hw, buf, bufsz);
1722         if (err) {
1723                 PMD_INIT_LOG(ERR, "ice_copy_and_init_hw failed: %d\n", err);
1724                 goto out;
1725         }
1726
1727         /* store the loaded pkg type info */
1728         adapter->active_pkg_type = ice_load_pkg_type(hw);
1729
1730 out:
1731         free(buf);
1732         return err;
1733 }
1734
1735 static void
1736 ice_base_queue_get(struct ice_pf *pf)
1737 {
1738         uint32_t reg;
1739         struct ice_hw *hw = ICE_PF_TO_HW(pf);
1740
1741         reg = ICE_READ_REG(hw, PFLAN_RX_QALLOC);
1742         if (reg & PFLAN_RX_QALLOC_VALID_M) {
1743                 pf->base_queue = reg & PFLAN_RX_QALLOC_FIRSTQ_M;
1744         } else {
1745                 PMD_INIT_LOG(WARNING, "Failed to get Rx base queue"
1746                                         " index");
1747         }
1748 }
1749
1750 static int
1751 parse_bool(const char *key, const char *value, void *args)
1752 {
1753         int *i = (int *)args;
1754         char *end;
1755         int num;
1756
1757         num = strtoul(value, &end, 10);
1758
1759         if (num != 0 && num != 1) {
1760                 PMD_DRV_LOG(WARNING, "invalid value:\"%s\" for key:\"%s\", "
1761                         "value must be 0 or 1",
1762                         value, key);
1763                 return -1;
1764         }
1765
1766         *i = num;
1767         return 0;
1768 }
1769
1770 static int
1771 parse_u64(const char *key, const char *value, void *args)
1772 {
1773         u64 *num = (u64 *)args;
1774         u64 tmp;
1775
1776         errno = 0;
1777         tmp = strtoull(value, NULL, 16);
1778         if (errno) {
1779                 PMD_DRV_LOG(WARNING, "%s: \"%s\" is not a valid u64",
1780                             key, value);
1781                 return -1;
1782         }
1783
1784         *num = tmp;
1785
1786         return 0;
1787 }
1788
1789 static int ice_parse_devargs(struct rte_eth_dev *dev)
1790 {
1791         struct ice_adapter *ad =
1792                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1793         struct rte_devargs *devargs = dev->device->devargs;
1794         struct rte_kvargs *kvlist;
1795         int ret;
1796
1797         if (devargs == NULL)
1798                 return 0;
1799
1800         kvlist = rte_kvargs_parse(devargs->args, ice_valid_args);
1801         if (kvlist == NULL) {
1802                 PMD_INIT_LOG(ERR, "Invalid kvargs key\n");
1803                 return -EINVAL;
1804         }
1805
1806         ad->devargs.proto_xtr_dflt = PROTO_XTR_NONE;
1807         memset(ad->devargs.proto_xtr, PROTO_XTR_NONE,
1808                sizeof(ad->devargs.proto_xtr));
1809
1810         ret = rte_kvargs_process(kvlist, ICE_PROTO_XTR_ARG,
1811                                  &handle_proto_xtr_arg, &ad->devargs);
1812         if (ret)
1813                 goto bail;
1814
1815         ret = rte_kvargs_process(kvlist, ICE_SAFE_MODE_SUPPORT_ARG,
1816                                  &parse_bool, &ad->devargs.safe_mode_support);
1817         if (ret)
1818                 goto bail;
1819
1820         ret = rte_kvargs_process(kvlist, ICE_PIPELINE_MODE_SUPPORT_ARG,
1821                                  &parse_bool, &ad->devargs.pipe_mode_support);
1822         if (ret)
1823                 goto bail;
1824
1825         ret = rte_kvargs_process(kvlist, ICE_HW_DEBUG_MASK_ARG,
1826                                  &parse_u64, &ad->hw.debug_mask);
1827         if (ret)
1828                 goto bail;
1829
1830 bail:
1831         rte_kvargs_free(kvlist);
1832         return ret;
1833 }
1834
1835 /* Forward LLDP packets to default VSI by set switch rules */
1836 static int
1837 ice_vsi_config_sw_lldp(struct ice_vsi *vsi,  bool on)
1838 {
1839         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
1840         struct ice_fltr_list_entry *s_list_itr = NULL;
1841         struct LIST_HEAD_TYPE list_head;
1842         int ret = 0;
1843
1844         INIT_LIST_HEAD(&list_head);
1845
1846         s_list_itr = (struct ice_fltr_list_entry *)
1847                         ice_malloc(hw, sizeof(*s_list_itr));
1848         if (!s_list_itr)
1849                 return -ENOMEM;
1850         s_list_itr->fltr_info.lkup_type = ICE_SW_LKUP_ETHERTYPE;
1851         s_list_itr->fltr_info.vsi_handle = vsi->idx;
1852         s_list_itr->fltr_info.l_data.ethertype_mac.ethertype =
1853                         RTE_ETHER_TYPE_LLDP;
1854         s_list_itr->fltr_info.fltr_act = ICE_FWD_TO_VSI;
1855         s_list_itr->fltr_info.flag = ICE_FLTR_RX;
1856         s_list_itr->fltr_info.src_id = ICE_SRC_ID_LPORT;
1857         LIST_ADD(&s_list_itr->list_entry, &list_head);
1858         if (on)
1859                 ret = ice_add_eth_mac(hw, &list_head);
1860         else
1861                 ret = ice_remove_eth_mac(hw, &list_head);
1862
1863         rte_free(s_list_itr);
1864         return ret;
1865 }
1866
1867 static enum ice_status
1868 ice_get_hw_res(struct ice_hw *hw, uint16_t res_type,
1869                 uint16_t num, uint16_t desc_id,
1870                 uint16_t *prof_buf, uint16_t *num_prof)
1871 {
1872         struct ice_aqc_res_elem *resp_buf;
1873         int ret;
1874         uint16_t buf_len;
1875         bool res_shared = 1;
1876         struct ice_aq_desc aq_desc;
1877         struct ice_sq_cd *cd = NULL;
1878         struct ice_aqc_get_allocd_res_desc *cmd =
1879                         &aq_desc.params.get_res_desc;
1880
1881         buf_len = sizeof(*resp_buf) * num;
1882         resp_buf = ice_malloc(hw, buf_len);
1883         if (!resp_buf)
1884                 return -ENOMEM;
1885
1886         ice_fill_dflt_direct_cmd_desc(&aq_desc,
1887                         ice_aqc_opc_get_allocd_res_desc);
1888
1889         cmd->ops.cmd.res = CPU_TO_LE16(((res_type << ICE_AQC_RES_TYPE_S) &
1890                                 ICE_AQC_RES_TYPE_M) | (res_shared ?
1891                                 ICE_AQC_RES_TYPE_FLAG_SHARED : 0));
1892         cmd->ops.cmd.first_desc = CPU_TO_LE16(desc_id);
1893
1894         ret = ice_aq_send_cmd(hw, &aq_desc, resp_buf, buf_len, cd);
1895         if (!ret)
1896                 *num_prof = LE16_TO_CPU(cmd->ops.resp.num_desc);
1897         else
1898                 goto exit;
1899
1900         ice_memcpy(prof_buf, resp_buf, sizeof(*resp_buf) *
1901                         (*num_prof), ICE_NONDMA_TO_NONDMA);
1902
1903 exit:
1904         rte_free(resp_buf);
1905         return ret;
1906 }
1907 static int
1908 ice_cleanup_resource(struct ice_hw *hw, uint16_t res_type)
1909 {
1910         int ret;
1911         uint16_t prof_id;
1912         uint16_t prof_buf[ICE_MAX_RES_DESC_NUM];
1913         uint16_t first_desc = 1;
1914         uint16_t num_prof = 0;
1915
1916         ret = ice_get_hw_res(hw, res_type, ICE_MAX_RES_DESC_NUM,
1917                         first_desc, prof_buf, &num_prof);
1918         if (ret) {
1919                 PMD_INIT_LOG(ERR, "Failed to get fxp resource");
1920                 return ret;
1921         }
1922
1923         for (prof_id = 0; prof_id < num_prof; prof_id++) {
1924                 ret = ice_free_hw_res(hw, res_type, 1, &prof_buf[prof_id]);
1925                 if (ret) {
1926                         PMD_INIT_LOG(ERR, "Failed to free fxp resource");
1927                         return ret;
1928                 }
1929         }
1930         return 0;
1931 }
1932
1933 static int
1934 ice_reset_fxp_resource(struct ice_hw *hw)
1935 {
1936         int ret;
1937
1938         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_FD_PROF_BLDR_PROFID);
1939         if (ret) {
1940                 PMD_INIT_LOG(ERR, "Failed to clearup fdir resource");
1941                 return ret;
1942         }
1943
1944         ret = ice_cleanup_resource(hw, ICE_AQC_RES_TYPE_HASH_PROF_BLDR_PROFID);
1945         if (ret) {
1946                 PMD_INIT_LOG(ERR, "Failed to clearup rss resource");
1947                 return ret;
1948         }
1949
1950         return 0;
1951 }
1952
1953 static void
1954 ice_rss_ctx_init(struct ice_pf *pf)
1955 {
1956         memset(&pf->hash_ctx, 0, sizeof(pf->hash_ctx));
1957 }
1958
1959 static uint64_t
1960 ice_get_supported_rxdid(struct ice_hw *hw)
1961 {
1962         uint64_t supported_rxdid = 0; /* bitmap for supported RXDID */
1963         uint32_t regval;
1964         int i;
1965
1966         supported_rxdid |= BIT(ICE_RXDID_LEGACY_1);
1967
1968         for (i = ICE_RXDID_FLEX_NIC; i < ICE_FLEX_DESC_RXDID_MAX_NUM; i++) {
1969                 regval = ICE_READ_REG(hw, GLFLXP_RXDID_FLAGS(i, 0));
1970                 if ((regval >> GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_S)
1971                         & GLFLXP_RXDID_FLAGS_FLEXIFLAG_4N_M)
1972                         supported_rxdid |= BIT(i);
1973         }
1974         return supported_rxdid;
1975 }
1976
1977 static int
1978 ice_dev_init(struct rte_eth_dev *dev)
1979 {
1980         struct rte_pci_device *pci_dev;
1981         struct rte_intr_handle *intr_handle;
1982         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
1983         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
1984         struct ice_adapter *ad =
1985                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
1986         struct ice_vsi *vsi;
1987         int ret;
1988 #ifndef RTE_EXEC_ENV_WINDOWS
1989         off_t pos;
1990         uint32_t dsn_low, dsn_high;
1991         uint64_t dsn;
1992         bool use_dsn;
1993 #endif
1994
1995         dev->dev_ops = &ice_eth_dev_ops;
1996         dev->rx_queue_count = ice_rx_queue_count;
1997         dev->rx_descriptor_status = ice_rx_descriptor_status;
1998         dev->tx_descriptor_status = ice_tx_descriptor_status;
1999         dev->rx_pkt_burst = ice_recv_pkts;
2000         dev->tx_pkt_burst = ice_xmit_pkts;
2001         dev->tx_pkt_prepare = ice_prep_pkts;
2002
2003         /* for secondary processes, we don't initialise any further as primary
2004          * has already done this work.
2005          */
2006         if (rte_eal_process_type() != RTE_PROC_PRIMARY) {
2007                 ice_set_rx_function(dev);
2008                 ice_set_tx_function(dev);
2009                 return 0;
2010         }
2011
2012         dev->data->dev_flags |= RTE_ETH_DEV_AUTOFILL_QUEUE_XSTATS;
2013
2014         ice_set_default_ptype_table(dev);
2015         pci_dev = RTE_DEV_TO_PCI(dev->device);
2016         intr_handle = &pci_dev->intr_handle;
2017
2018         pf->adapter = ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2019         pf->dev_data = dev->data;
2020         hw->back = pf->adapter;
2021         hw->hw_addr = (uint8_t *)pci_dev->mem_resource[0].addr;
2022         hw->vendor_id = pci_dev->id.vendor_id;
2023         hw->device_id = pci_dev->id.device_id;
2024         hw->subsystem_vendor_id = pci_dev->id.subsystem_vendor_id;
2025         hw->subsystem_device_id = pci_dev->id.subsystem_device_id;
2026         hw->bus.device = pci_dev->addr.devid;
2027         hw->bus.func = pci_dev->addr.function;
2028
2029         ret = ice_parse_devargs(dev);
2030         if (ret) {
2031                 PMD_INIT_LOG(ERR, "Failed to parse devargs");
2032                 return -EINVAL;
2033         }
2034
2035         ice_init_controlq_parameter(hw);
2036
2037         ret = ice_init_hw(hw);
2038         if (ret) {
2039                 PMD_INIT_LOG(ERR, "Failed to initialize HW");
2040                 return -EINVAL;
2041         }
2042
2043 #ifndef RTE_EXEC_ENV_WINDOWS
2044         use_dsn = false;
2045         dsn = 0;
2046         pos = rte_pci_find_ext_capability(pci_dev, RTE_PCI_EXT_CAP_ID_DSN);
2047         if (pos) {
2048                 if (rte_pci_read_config(pci_dev, &dsn_low, 4, pos + 4) < 0 ||
2049                                 rte_pci_read_config(pci_dev, &dsn_high, 4, pos + 8) < 0) {
2050                         PMD_INIT_LOG(ERR, "Failed to read pci config space\n");
2051                 } else {
2052                         use_dsn = true;
2053                         dsn = (uint64_t)dsn_high << 32 | dsn_low;
2054                 }
2055         } else {
2056                 PMD_INIT_LOG(ERR, "Failed to read device serial number\n");
2057         }
2058
2059         ret = ice_load_pkg(pf->adapter, use_dsn, dsn);
2060         if (ret == 0) {
2061                 ret = ice_init_hw_tbls(hw);
2062                 if (ret) {
2063                         PMD_INIT_LOG(ERR, "ice_init_hw_tbls failed: %d\n", ret);
2064                         rte_free(hw->pkg_copy);
2065                 }
2066         }
2067
2068         if (ret) {
2069                 if (ad->devargs.safe_mode_support == 0) {
2070                         PMD_INIT_LOG(ERR, "Failed to load the DDP package,"
2071                                         "Use safe-mode-support=1 to enter Safe Mode");
2072                         goto err_init_fw;
2073                 }
2074
2075                 PMD_INIT_LOG(WARNING, "Failed to load the DDP package,"
2076                                         "Entering Safe Mode");
2077                 ad->is_safe_mode = 1;
2078         }
2079 #endif
2080
2081         PMD_INIT_LOG(INFO, "FW %d.%d.%05d API %d.%d",
2082                      hw->fw_maj_ver, hw->fw_min_ver, hw->fw_build,
2083                      hw->api_maj_ver, hw->api_min_ver);
2084
2085         ice_pf_sw_init(dev);
2086         ret = ice_init_mac_address(dev);
2087         if (ret) {
2088                 PMD_INIT_LOG(ERR, "Failed to initialize mac address");
2089                 goto err_init_mac;
2090         }
2091
2092         ret = ice_res_pool_init(&pf->msix_pool, 1,
2093                                 hw->func_caps.common_cap.num_msix_vectors - 1);
2094         if (ret) {
2095                 PMD_INIT_LOG(ERR, "Failed to init MSIX pool");
2096                 goto err_msix_pool_init;
2097         }
2098
2099         ret = ice_pf_setup(pf);
2100         if (ret) {
2101                 PMD_INIT_LOG(ERR, "Failed to setup PF");
2102                 goto err_pf_setup;
2103         }
2104
2105         ret = ice_send_driver_ver(hw);
2106         if (ret) {
2107                 PMD_INIT_LOG(ERR, "Failed to send driver version");
2108                 goto err_pf_setup;
2109         }
2110
2111         vsi = pf->main_vsi;
2112
2113         ret = ice_aq_stop_lldp(hw, true, false, NULL);
2114         if (ret != ICE_SUCCESS)
2115                 PMD_INIT_LOG(DEBUG, "lldp has already stopped\n");
2116         ret = ice_init_dcb(hw, true);
2117         if (ret != ICE_SUCCESS)
2118                 PMD_INIT_LOG(DEBUG, "Failed to init DCB\n");
2119         /* Forward LLDP packets to default VSI */
2120         ret = ice_vsi_config_sw_lldp(vsi, true);
2121         if (ret != ICE_SUCCESS)
2122                 PMD_INIT_LOG(DEBUG, "Failed to cfg lldp\n");
2123         /* register callback func to eal lib */
2124         rte_intr_callback_register(intr_handle,
2125                                    ice_interrupt_handler, dev);
2126
2127         ice_pf_enable_irq0(hw);
2128
2129         /* enable uio intr after callback register */
2130         rte_intr_enable(intr_handle);
2131
2132         /* get base queue pairs index  in the device */
2133         ice_base_queue_get(pf);
2134
2135         /* Initialize RSS context for gtpu_eh */
2136         ice_rss_ctx_init(pf);
2137
2138         if (!ad->is_safe_mode) {
2139                 ret = ice_flow_init(ad);
2140                 if (ret) {
2141                         PMD_INIT_LOG(ERR, "Failed to initialize flow");
2142                         goto err_flow_init;
2143                 }
2144         }
2145
2146         ret = ice_reset_fxp_resource(hw);
2147         if (ret) {
2148                 PMD_INIT_LOG(ERR, "Failed to reset fxp resource");
2149                 goto err_flow_init;
2150         }
2151
2152         pf->supported_rxdid = ice_get_supported_rxdid(hw);
2153
2154         return 0;
2155
2156 err_flow_init:
2157         ice_flow_uninit(ad);
2158         rte_intr_disable(intr_handle);
2159         ice_pf_disable_irq0(hw);
2160         rte_intr_callback_unregister(intr_handle,
2161                                      ice_interrupt_handler, dev);
2162 err_pf_setup:
2163         ice_res_pool_destroy(&pf->msix_pool);
2164 err_msix_pool_init:
2165         rte_free(dev->data->mac_addrs);
2166         dev->data->mac_addrs = NULL;
2167 err_init_mac:
2168         rte_free(pf->proto_xtr);
2169 #ifndef RTE_EXEC_ENV_WINDOWS
2170 err_init_fw:
2171 #endif
2172         ice_deinit_hw(hw);
2173
2174         return ret;
2175 }
2176
2177 int
2178 ice_release_vsi(struct ice_vsi *vsi)
2179 {
2180         struct ice_hw *hw;
2181         struct ice_vsi_ctx vsi_ctx;
2182         enum ice_status ret;
2183         int error = 0;
2184
2185         if (!vsi)
2186                 return error;
2187
2188         hw = ICE_VSI_TO_HW(vsi);
2189
2190         ice_remove_all_mac_vlan_filters(vsi);
2191
2192         memset(&vsi_ctx, 0, sizeof(vsi_ctx));
2193
2194         vsi_ctx.vsi_num = vsi->vsi_id;
2195         vsi_ctx.info = vsi->info;
2196         ret = ice_free_vsi(hw, vsi->idx, &vsi_ctx, false, NULL);
2197         if (ret != ICE_SUCCESS) {
2198                 PMD_INIT_LOG(ERR, "Failed to free vsi by aq, %u", vsi->vsi_id);
2199                 error = -1;
2200         }
2201
2202         rte_free(vsi->rss_lut);
2203         rte_free(vsi->rss_key);
2204         rte_free(vsi);
2205         return error;
2206 }
2207
2208 void
2209 ice_vsi_disable_queues_intr(struct ice_vsi *vsi)
2210 {
2211         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
2212         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2213         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2214         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
2215         uint16_t msix_intr, i;
2216
2217         /* disable interrupt and also clear all the exist config */
2218         for (i = 0; i < vsi->nb_qps; i++) {
2219                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
2220                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
2221                 rte_wmb();
2222         }
2223
2224         if (rte_intr_allow_others(intr_handle))
2225                 /* vfio-pci */
2226                 for (i = 0; i < vsi->nb_msix; i++) {
2227                         msix_intr = vsi->msix_intr + i;
2228                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
2229                                       GLINT_DYN_CTL_WB_ON_ITR_M);
2230                 }
2231         else
2232                 /* igb_uio */
2233                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0), GLINT_DYN_CTL_WB_ON_ITR_M);
2234 }
2235
2236 static int
2237 ice_dev_stop(struct rte_eth_dev *dev)
2238 {
2239         struct rte_eth_dev_data *data = dev->data;
2240         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2241         struct ice_vsi *main_vsi = pf->main_vsi;
2242         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
2243         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2244         uint16_t i;
2245
2246         /* avoid stopping again */
2247         if (pf->adapter_stopped)
2248                 return 0;
2249
2250         /* stop and clear all Rx queues */
2251         for (i = 0; i < data->nb_rx_queues; i++)
2252                 ice_rx_queue_stop(dev, i);
2253
2254         /* stop and clear all Tx queues */
2255         for (i = 0; i < data->nb_tx_queues; i++)
2256                 ice_tx_queue_stop(dev, i);
2257
2258         /* disable all queue interrupts */
2259         ice_vsi_disable_queues_intr(main_vsi);
2260
2261         if (pf->init_link_up)
2262                 ice_dev_set_link_up(dev);
2263         else
2264                 ice_dev_set_link_down(dev);
2265
2266         /* Clean datapath event and queue/vec mapping */
2267         rte_intr_efd_disable(intr_handle);
2268         if (intr_handle->intr_vec) {
2269                 rte_free(intr_handle->intr_vec);
2270                 intr_handle->intr_vec = NULL;
2271         }
2272
2273         pf->adapter_stopped = true;
2274         dev->data->dev_started = 0;
2275
2276         return 0;
2277 }
2278
2279 static int
2280 ice_dev_close(struct rte_eth_dev *dev)
2281 {
2282         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
2283         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
2284         struct rte_pci_device *pci_dev = RTE_ETH_DEV_TO_PCI(dev);
2285         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
2286         struct ice_adapter *ad =
2287                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
2288         int ret;
2289
2290         if (rte_eal_process_type() != RTE_PROC_PRIMARY)
2291                 return 0;
2292
2293         /* Since stop will make link down, then the link event will be
2294          * triggered, disable the irq firstly to avoid the port_infoe etc
2295          * resources deallocation causing the interrupt service thread
2296          * crash.
2297          */
2298         ice_pf_disable_irq0(hw);
2299
2300         ret = ice_dev_stop(dev);
2301
2302         if (!ad->is_safe_mode)
2303                 ice_flow_uninit(ad);
2304
2305         /* release all queue resource */
2306         ice_free_queues(dev);
2307
2308         ice_res_pool_destroy(&pf->msix_pool);
2309         ice_release_vsi(pf->main_vsi);
2310         ice_sched_cleanup_all(hw);
2311         ice_free_hw_tbls(hw);
2312         rte_free(hw->port_info);
2313         hw->port_info = NULL;
2314         ice_shutdown_all_ctrlq(hw);
2315         rte_free(pf->proto_xtr);
2316         pf->proto_xtr = NULL;
2317
2318         /* disable uio intr before callback unregister */
2319         rte_intr_disable(intr_handle);
2320
2321         /* unregister callback func from eal lib */
2322         rte_intr_callback_unregister(intr_handle,
2323                                      ice_interrupt_handler, dev);
2324
2325         return ret;
2326 }
2327
2328 static int
2329 ice_dev_uninit(struct rte_eth_dev *dev)
2330 {
2331         ice_dev_close(dev);
2332
2333         return 0;
2334 }
2335
2336 static bool
2337 is_hash_cfg_valid(struct ice_rss_hash_cfg *cfg)
2338 {
2339         return (cfg->hash_flds != 0 && cfg->addl_hdrs != 0) ? true : false;
2340 }
2341
2342 static void
2343 hash_cfg_reset(struct ice_rss_hash_cfg *cfg)
2344 {
2345         cfg->hash_flds = 0;
2346         cfg->addl_hdrs = 0;
2347         cfg->symm = 0;
2348         cfg->hdr_type = ICE_RSS_OUTER_HEADERS;
2349 }
2350
2351 static int
2352 ice_hash_moveout(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2353 {
2354         enum ice_status status = ICE_SUCCESS;
2355         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2356         struct ice_vsi *vsi = pf->main_vsi;
2357
2358         if (!is_hash_cfg_valid(cfg))
2359                 return -ENOENT;
2360
2361         status = ice_rem_rss_cfg(hw, vsi->idx, cfg);
2362         if (status && status != ICE_ERR_DOES_NOT_EXIST) {
2363                 PMD_DRV_LOG(ERR,
2364                             "ice_rem_rss_cfg failed for VSI:%d, error:%d\n",
2365                             vsi->idx, status);
2366                 return -EBUSY;
2367         }
2368
2369         return 0;
2370 }
2371
2372 static int
2373 ice_hash_moveback(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2374 {
2375         enum ice_status status = ICE_SUCCESS;
2376         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2377         struct ice_vsi *vsi = pf->main_vsi;
2378
2379         if (!is_hash_cfg_valid(cfg))
2380                 return -ENOENT;
2381
2382         status = ice_add_rss_cfg(hw, vsi->idx, cfg);
2383         if (status) {
2384                 PMD_DRV_LOG(ERR,
2385                             "ice_add_rss_cfg failed for VSI:%d, error:%d\n",
2386                             vsi->idx, status);
2387                 return -EBUSY;
2388         }
2389
2390         return 0;
2391 }
2392
2393 static int
2394 ice_hash_remove(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2395 {
2396         int ret;
2397
2398         ret = ice_hash_moveout(pf, cfg);
2399         if (ret && (ret != -ENOENT))
2400                 return ret;
2401
2402         hash_cfg_reset(cfg);
2403
2404         return 0;
2405 }
2406
2407 static int
2408 ice_add_rss_cfg_pre_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2409                          u8 ctx_idx)
2410 {
2411         int ret;
2412
2413         switch (ctx_idx) {
2414         case ICE_HASH_GTPU_CTX_EH_IP:
2415                 ret = ice_hash_remove(pf,
2416                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2417                 if (ret && (ret != -ENOENT))
2418                         return ret;
2419
2420                 ret = ice_hash_remove(pf,
2421                                       &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2422                 if (ret && (ret != -ENOENT))
2423                         return ret;
2424
2425                 ret = ice_hash_remove(pf,
2426                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2427                 if (ret && (ret != -ENOENT))
2428                         return ret;
2429
2430                 ret = ice_hash_remove(pf,
2431                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2432                 if (ret && (ret != -ENOENT))
2433                         return ret;
2434
2435                 ret = ice_hash_remove(pf,
2436                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2437                 if (ret && (ret != -ENOENT))
2438                         return ret;
2439
2440                 ret = ice_hash_remove(pf,
2441                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2442                 if (ret && (ret != -ENOENT))
2443                         return ret;
2444
2445                 ret = ice_hash_remove(pf,
2446                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2447                 if (ret && (ret != -ENOENT))
2448                         return ret;
2449
2450                 ret = ice_hash_remove(pf,
2451                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2452                 if (ret && (ret != -ENOENT))
2453                         return ret;
2454
2455                 break;
2456         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2457                 ret = ice_hash_remove(pf,
2458                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2459                 if (ret && (ret != -ENOENT))
2460                         return ret;
2461
2462                 ret = ice_hash_remove(pf,
2463                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2464                 if (ret && (ret != -ENOENT))
2465                         return ret;
2466
2467                 ret = ice_hash_moveout(pf,
2468                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2469                 if (ret && (ret != -ENOENT))
2470                         return ret;
2471
2472                 ret = ice_hash_moveout(pf,
2473                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2474                 if (ret && (ret != -ENOENT))
2475                         return ret;
2476
2477                 ret = ice_hash_moveout(pf,
2478                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2479                 if (ret && (ret != -ENOENT))
2480                         return ret;
2481
2482                 ret = ice_hash_moveout(pf,
2483                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2484                 if (ret && (ret != -ENOENT))
2485                         return ret;
2486
2487                 break;
2488         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2489                 ret = ice_hash_remove(pf,
2490                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2491                 if (ret && (ret != -ENOENT))
2492                         return ret;
2493
2494                 ret = ice_hash_remove(pf,
2495                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2496                 if (ret && (ret != -ENOENT))
2497                         return ret;
2498
2499                 ret = ice_hash_moveout(pf,
2500                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2501                 if (ret && (ret != -ENOENT))
2502                         return ret;
2503
2504                 ret = ice_hash_moveout(pf,
2505                                        &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2506                 if (ret && (ret != -ENOENT))
2507                         return ret;
2508
2509                 ret = ice_hash_moveout(pf,
2510                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2511                 if (ret && (ret != -ENOENT))
2512                         return ret;
2513
2514                 ret = ice_hash_moveout(pf,
2515                                        &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2516                 if (ret && (ret != -ENOENT))
2517                         return ret;
2518
2519                 break;
2520         case ICE_HASH_GTPU_CTX_UP_IP:
2521                 ret = ice_hash_remove(pf,
2522                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2523                 if (ret && (ret != -ENOENT))
2524                         return ret;
2525
2526                 ret = ice_hash_remove(pf,
2527                                       &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2528                 if (ret && (ret != -ENOENT))
2529                         return ret;
2530
2531                 ret = ice_hash_moveout(pf,
2532                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2533                 if (ret && (ret != -ENOENT))
2534                         return ret;
2535
2536                 ret = ice_hash_moveout(pf,
2537                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2538                 if (ret && (ret != -ENOENT))
2539                         return ret;
2540
2541                 ret = ice_hash_moveout(pf,
2542                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2543                 if (ret && (ret != -ENOENT))
2544                         return ret;
2545
2546                 break;
2547         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2548         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2549                 ret = ice_hash_moveout(pf,
2550                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2551                 if (ret && (ret != -ENOENT))
2552                         return ret;
2553
2554                 ret = ice_hash_moveout(pf,
2555                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2556                 if (ret && (ret != -ENOENT))
2557                         return ret;
2558
2559                 ret = ice_hash_moveout(pf,
2560                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2561                 if (ret && (ret != -ENOENT))
2562                         return ret;
2563
2564                 break;
2565         case ICE_HASH_GTPU_CTX_DW_IP:
2566                 ret = ice_hash_remove(pf,
2567                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2568                 if (ret && (ret != -ENOENT))
2569                         return ret;
2570
2571                 ret = ice_hash_remove(pf,
2572                                       &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2573                 if (ret && (ret != -ENOENT))
2574                         return ret;
2575
2576                 ret = ice_hash_moveout(pf,
2577                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2578                 if (ret && (ret != -ENOENT))
2579                         return ret;
2580
2581                 ret = ice_hash_moveout(pf,
2582                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2583                 if (ret && (ret != -ENOENT))
2584                         return ret;
2585
2586                 ret = ice_hash_moveout(pf,
2587                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2588                 if (ret && (ret != -ENOENT))
2589                         return ret;
2590
2591                 break;
2592         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2593         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2594                 ret = ice_hash_moveout(pf,
2595                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2596                 if (ret && (ret != -ENOENT))
2597                         return ret;
2598
2599                 ret = ice_hash_moveout(pf,
2600                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2601                 if (ret && (ret != -ENOENT))
2602                         return ret;
2603
2604                 ret = ice_hash_moveout(pf,
2605                                        &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2606                 if (ret && (ret != -ENOENT))
2607                         return ret;
2608
2609                 break;
2610         default:
2611                 break;
2612         }
2613
2614         return 0;
2615 }
2616
2617 static u8 calc_gtpu_ctx_idx(uint32_t hdr)
2618 {
2619         u8 eh_idx, ip_idx;
2620
2621         if (hdr & ICE_FLOW_SEG_HDR_GTPU_EH)
2622                 eh_idx = 0;
2623         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_UP)
2624                 eh_idx = 1;
2625         else if (hdr & ICE_FLOW_SEG_HDR_GTPU_DWN)
2626                 eh_idx = 2;
2627         else
2628                 return ICE_HASH_GTPU_CTX_MAX;
2629
2630         ip_idx = 0;
2631         if (hdr & ICE_FLOW_SEG_HDR_UDP)
2632                 ip_idx = 1;
2633         else if (hdr & ICE_FLOW_SEG_HDR_TCP)
2634                 ip_idx = 2;
2635
2636         if (hdr & (ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV6))
2637                 return eh_idx * 3 + ip_idx;
2638         else
2639                 return ICE_HASH_GTPU_CTX_MAX;
2640 }
2641
2642 static int
2643 ice_add_rss_cfg_pre(struct ice_pf *pf, uint32_t hdr)
2644 {
2645         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2646
2647         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2648                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu4,
2649                                                 gtpu_ctx_idx);
2650         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2651                 return ice_add_rss_cfg_pre_gtpu(pf, &pf->hash_ctx.gtpu6,
2652                                                 gtpu_ctx_idx);
2653
2654         return 0;
2655 }
2656
2657 static int
2658 ice_add_rss_cfg_post_gtpu(struct ice_pf *pf, struct ice_hash_gtpu_ctx *ctx,
2659                           u8 ctx_idx, struct ice_rss_hash_cfg *cfg)
2660 {
2661         int ret;
2662
2663         if (ctx_idx < ICE_HASH_GTPU_CTX_MAX)
2664                 ctx->ctx[ctx_idx] = *cfg;
2665
2666         switch (ctx_idx) {
2667         case ICE_HASH_GTPU_CTX_EH_IP:
2668                 break;
2669         case ICE_HASH_GTPU_CTX_EH_IP_UDP:
2670                 ret = ice_hash_moveback(pf,
2671                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2672                 if (ret && (ret != -ENOENT))
2673                         return ret;
2674
2675                 ret = ice_hash_moveback(pf,
2676                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_TCP]);
2677                 if (ret && (ret != -ENOENT))
2678                         return ret;
2679
2680                 ret = ice_hash_moveback(pf,
2681                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2682                 if (ret && (ret != -ENOENT))
2683                         return ret;
2684
2685                 ret = ice_hash_moveback(pf,
2686                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_TCP]);
2687                 if (ret && (ret != -ENOENT))
2688                         return ret;
2689
2690                 break;
2691         case ICE_HASH_GTPU_CTX_EH_IP_TCP:
2692                 ret = ice_hash_moveback(pf,
2693                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP]);
2694                 if (ret && (ret != -ENOENT))
2695                         return ret;
2696
2697                 ret = ice_hash_moveback(pf,
2698                                         &ctx->ctx[ICE_HASH_GTPU_CTX_UP_IP_UDP]);
2699                 if (ret && (ret != -ENOENT))
2700                         return ret;
2701
2702                 ret = ice_hash_moveback(pf,
2703                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP]);
2704                 if (ret && (ret != -ENOENT))
2705                         return ret;
2706
2707                 ret = ice_hash_moveback(pf,
2708                                         &ctx->ctx[ICE_HASH_GTPU_CTX_DW_IP_UDP]);
2709                 if (ret && (ret != -ENOENT))
2710                         return ret;
2711
2712                 break;
2713         case ICE_HASH_GTPU_CTX_UP_IP:
2714         case ICE_HASH_GTPU_CTX_UP_IP_UDP:
2715         case ICE_HASH_GTPU_CTX_UP_IP_TCP:
2716         case ICE_HASH_GTPU_CTX_DW_IP:
2717         case ICE_HASH_GTPU_CTX_DW_IP_UDP:
2718         case ICE_HASH_GTPU_CTX_DW_IP_TCP:
2719                 ret = ice_hash_moveback(pf,
2720                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP]);
2721                 if (ret && (ret != -ENOENT))
2722                         return ret;
2723
2724                 ret = ice_hash_moveback(pf,
2725                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_UDP]);
2726                 if (ret && (ret != -ENOENT))
2727                         return ret;
2728
2729                 ret = ice_hash_moveback(pf,
2730                                         &ctx->ctx[ICE_HASH_GTPU_CTX_EH_IP_TCP]);
2731                 if (ret && (ret != -ENOENT))
2732                         return ret;
2733
2734                 break;
2735         default:
2736                 break;
2737         }
2738
2739         return 0;
2740 }
2741
2742 static int
2743 ice_add_rss_cfg_post(struct ice_pf *pf, struct ice_rss_hash_cfg *cfg)
2744 {
2745         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(cfg->addl_hdrs);
2746
2747         if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV4)
2748                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu4,
2749                                                  gtpu_ctx_idx, cfg);
2750         else if (cfg->addl_hdrs & ICE_FLOW_SEG_HDR_IPV6)
2751                 return ice_add_rss_cfg_post_gtpu(pf, &pf->hash_ctx.gtpu6,
2752                                                  gtpu_ctx_idx, cfg);
2753
2754         return 0;
2755 }
2756
2757 static void
2758 ice_rem_rss_cfg_post(struct ice_pf *pf, uint32_t hdr)
2759 {
2760         u8 gtpu_ctx_idx = calc_gtpu_ctx_idx(hdr);
2761
2762         if (gtpu_ctx_idx >= ICE_HASH_GTPU_CTX_MAX)
2763                 return;
2764
2765         if (hdr & ICE_FLOW_SEG_HDR_IPV4)
2766                 hash_cfg_reset(&pf->hash_ctx.gtpu4.ctx[gtpu_ctx_idx]);
2767         else if (hdr & ICE_FLOW_SEG_HDR_IPV6)
2768                 hash_cfg_reset(&pf->hash_ctx.gtpu6.ctx[gtpu_ctx_idx]);
2769 }
2770
2771 int
2772 ice_rem_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2773                      struct ice_rss_hash_cfg *cfg)
2774 {
2775         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2776         int ret;
2777
2778         ret = ice_rem_rss_cfg(hw, vsi_id, cfg);
2779         if (ret && ret != ICE_ERR_DOES_NOT_EXIST)
2780                 PMD_DRV_LOG(ERR, "remove rss cfg failed\n");
2781
2782         ice_rem_rss_cfg_post(pf, cfg->addl_hdrs);
2783
2784         return 0;
2785 }
2786
2787 int
2788 ice_add_rss_cfg_wrap(struct ice_pf *pf, uint16_t vsi_id,
2789                      struct ice_rss_hash_cfg *cfg)
2790 {
2791         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2792         int ret;
2793
2794         ret = ice_add_rss_cfg_pre(pf, cfg->addl_hdrs);
2795         if (ret)
2796                 PMD_DRV_LOG(ERR, "add rss cfg pre failed\n");
2797
2798         ret = ice_add_rss_cfg(hw, vsi_id, cfg);
2799         if (ret)
2800                 PMD_DRV_LOG(ERR, "add rss cfg failed\n");
2801
2802         ret = ice_add_rss_cfg_post(pf, cfg);
2803         if (ret)
2804                 PMD_DRV_LOG(ERR, "add rss cfg post failed\n");
2805
2806         return 0;
2807 }
2808
2809 static void
2810 ice_rss_hash_set(struct ice_pf *pf, uint64_t rss_hf)
2811 {
2812         struct ice_hw *hw = ICE_PF_TO_HW(pf);
2813         struct ice_vsi *vsi = pf->main_vsi;
2814         struct ice_rss_hash_cfg cfg;
2815         int ret;
2816
2817 #define ICE_RSS_HF_ALL ( \
2818         ETH_RSS_IPV4 | \
2819         ETH_RSS_IPV6 | \
2820         ETH_RSS_NONFRAG_IPV4_UDP | \
2821         ETH_RSS_NONFRAG_IPV6_UDP | \
2822         ETH_RSS_NONFRAG_IPV4_TCP | \
2823         ETH_RSS_NONFRAG_IPV6_TCP | \
2824         ETH_RSS_NONFRAG_IPV4_SCTP | \
2825         ETH_RSS_NONFRAG_IPV6_SCTP | \
2826         ETH_RSS_FRAG_IPV4 | \
2827         ETH_RSS_FRAG_IPV6)
2828
2829         ret = ice_rem_vsi_rss_cfg(hw, vsi->idx);
2830         if (ret)
2831                 PMD_DRV_LOG(ERR, "%s Remove rss vsi fail %d",
2832                             __func__, ret);
2833
2834         cfg.symm = 0;
2835         cfg.hdr_type = ICE_RSS_OUTER_HEADERS;
2836         /* Configure RSS for IPv4 with src/dst addr as input set */
2837         if (rss_hf & ETH_RSS_IPV4) {
2838                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2839                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2840                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2841                 if (ret)
2842                         PMD_DRV_LOG(ERR, "%s IPV4 rss flow fail %d",
2843                                     __func__, ret);
2844         }
2845
2846         /* Configure RSS for IPv6 with src/dst addr as input set */
2847         if (rss_hf & ETH_RSS_IPV6) {
2848                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2849                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2850                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2851                 if (ret)
2852                         PMD_DRV_LOG(ERR, "%s IPV6 rss flow fail %d",
2853                                     __func__, ret);
2854         }
2855
2856         /* Configure RSS for udp4 with src/dst addr and port as input set */
2857         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2858                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV4 |
2859                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2860                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2861                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2862                 if (ret)
2863                         PMD_DRV_LOG(ERR, "%s UDP_IPV4 rss flow fail %d",
2864                                     __func__, ret);
2865         }
2866
2867         /* Configure RSS for udp6 with src/dst addr and port as input set */
2868         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2869                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_UDP | ICE_FLOW_SEG_HDR_IPV6 |
2870                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2871                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2872                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2873                 if (ret)
2874                         PMD_DRV_LOG(ERR, "%s UDP_IPV6 rss flow fail %d",
2875                                     __func__, ret);
2876         }
2877
2878         /* Configure RSS for tcp4 with src/dst addr and port as input set */
2879         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2880                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV4 |
2881                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2882                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2883                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2884                 if (ret)
2885                         PMD_DRV_LOG(ERR, "%s TCP_IPV4 rss flow fail %d",
2886                                     __func__, ret);
2887         }
2888
2889         /* Configure RSS for tcp6 with src/dst addr and port as input set */
2890         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2891                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_TCP | ICE_FLOW_SEG_HDR_IPV6 |
2892                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2893                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2894                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2895                 if (ret)
2896                         PMD_DRV_LOG(ERR, "%s TCP_IPV6 rss flow fail %d",
2897                                     __func__, ret);
2898         }
2899
2900         /* Configure RSS for sctp4 with src/dst addr and port as input set */
2901         if (rss_hf & ETH_RSS_NONFRAG_IPV4_SCTP) {
2902                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV4 |
2903                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2904                 cfg.hash_flds = ICE_HASH_SCTP_IPV4;
2905                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2906                 if (ret)
2907                         PMD_DRV_LOG(ERR, "%s SCTP_IPV4 rss flow fail %d",
2908                                     __func__, ret);
2909         }
2910
2911         /* Configure RSS for sctp6 with src/dst addr and port as input set */
2912         if (rss_hf & ETH_RSS_NONFRAG_IPV6_SCTP) {
2913                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_SCTP | ICE_FLOW_SEG_HDR_IPV6 |
2914                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2915                 cfg.hash_flds = ICE_HASH_SCTP_IPV6;
2916                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2917                 if (ret)
2918                         PMD_DRV_LOG(ERR, "%s SCTP_IPV6 rss flow fail %d",
2919                                     __func__, ret);
2920         }
2921
2922         if (rss_hf & ETH_RSS_IPV4) {
2923                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV4 |
2924                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2925                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2926                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2927                 if (ret)
2928                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4 rss flow fail %d",
2929                                     __func__, ret);
2930         }
2931
2932         if (rss_hf & ETH_RSS_IPV6) {
2933                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_IPV6 |
2934                                 ICE_FLOW_SEG_HDR_IPV_OTHER;
2935                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2936                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2937                 if (ret)
2938                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6 rss flow fail %d",
2939                                     __func__, ret);
2940         }
2941
2942         if (rss_hf & ETH_RSS_NONFRAG_IPV4_UDP) {
2943                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2944                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2945                 cfg.hash_flds = ICE_HASH_UDP_IPV4;
2946                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2947                 if (ret)
2948                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_UDP rss flow fail %d",
2949                                     __func__, ret);
2950         }
2951
2952         if (rss_hf & ETH_RSS_NONFRAG_IPV6_UDP) {
2953                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_UDP |
2954                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2955                 cfg.hash_flds = ICE_HASH_UDP_IPV6;
2956                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2957                 if (ret)
2958                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_UDP rss flow fail %d",
2959                                     __func__, ret);
2960         }
2961
2962         if (rss_hf & ETH_RSS_NONFRAG_IPV4_TCP) {
2963                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
2964                                 ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2965                 cfg.hash_flds = ICE_HASH_TCP_IPV4;
2966                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2967                 if (ret)
2968                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV4_TCP rss flow fail %d",
2969                                     __func__, ret);
2970         }
2971
2972         if (rss_hf & ETH_RSS_NONFRAG_IPV6_TCP) {
2973                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_PPPOE | ICE_FLOW_SEG_HDR_TCP |
2974                                 ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_OTHER;
2975                 cfg.hash_flds = ICE_HASH_TCP_IPV6;
2976                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2977                 if (ret)
2978                         PMD_DRV_LOG(ERR, "%s PPPoE_IPV6_TCP rss flow fail %d",
2979                                     __func__, ret);
2980         }
2981
2982         if (rss_hf & ETH_RSS_FRAG_IPV4) {
2983                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV4 | ICE_FLOW_SEG_HDR_IPV_FRAG;
2984                 cfg.hash_flds = ICE_FLOW_HASH_IPV4;
2985                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2986                 if (ret)
2987                         PMD_DRV_LOG(ERR, "%s IPV4_FRAG rss flow fail %d",
2988                                     __func__, ret);
2989         }
2990
2991         if (rss_hf & ETH_RSS_FRAG_IPV6) {
2992                 cfg.addl_hdrs = ICE_FLOW_SEG_HDR_IPV6 | ICE_FLOW_SEG_HDR_IPV_FRAG;
2993                 cfg.hash_flds = ICE_FLOW_HASH_IPV6;
2994                 ret = ice_add_rss_cfg_wrap(pf, vsi->idx, &cfg);
2995                 if (ret)
2996                         PMD_DRV_LOG(ERR, "%s IPV6_FRAG rss flow fail %d",
2997                                     __func__, ret);
2998         }
2999
3000         pf->rss_hf = rss_hf & ICE_RSS_HF_ALL;
3001 }
3002
3003 static void
3004 ice_get_default_rss_key(uint8_t *rss_key, uint32_t rss_key_size)
3005 {
3006         static struct ice_aqc_get_set_rss_keys default_key;
3007         static bool default_key_done;
3008         uint8_t *key = (uint8_t *)&default_key;
3009         size_t i;
3010
3011         if (rss_key_size > sizeof(default_key)) {
3012                 PMD_DRV_LOG(WARNING,
3013                             "requested size %u is larger than default %zu, "
3014                             "only %zu bytes are gotten for key\n",
3015                             rss_key_size, sizeof(default_key),
3016                             sizeof(default_key));
3017         }
3018
3019         if (!default_key_done) {
3020                 /* Calculate the default hash key */
3021                 for (i = 0; i < sizeof(default_key); i++)
3022                         key[i] = (uint8_t)rte_rand();
3023                 default_key_done = true;
3024         }
3025         rte_memcpy(rss_key, key, RTE_MIN(rss_key_size, sizeof(default_key)));
3026 }
3027
3028 static int ice_init_rss(struct ice_pf *pf)
3029 {
3030         struct ice_hw *hw = ICE_PF_TO_HW(pf);
3031         struct ice_vsi *vsi = pf->main_vsi;
3032         struct rte_eth_dev_data *dev_data = pf->dev_data;
3033         struct ice_aq_get_set_rss_lut_params lut_params;
3034         struct rte_eth_rss_conf *rss_conf;
3035         struct ice_aqc_get_set_rss_keys key;
3036         uint16_t i, nb_q;
3037         int ret = 0;
3038         bool is_safe_mode = pf->adapter->is_safe_mode;
3039         uint32_t reg;
3040
3041         rss_conf = &dev_data->dev_conf.rx_adv_conf.rss_conf;
3042         nb_q = dev_data->nb_rx_queues;
3043         vsi->rss_key_size = ICE_AQC_GET_SET_RSS_KEY_DATA_RSS_KEY_SIZE;
3044         vsi->rss_lut_size = pf->hash_lut_size;
3045
3046         if (nb_q == 0) {
3047                 PMD_DRV_LOG(WARNING,
3048                         "RSS is not supported as rx queues number is zero\n");
3049                 return 0;
3050         }
3051
3052         if (is_safe_mode) {
3053                 PMD_DRV_LOG(WARNING, "RSS is not supported in safe mode\n");
3054                 return 0;
3055         }
3056
3057         if (!vsi->rss_key) {
3058                 vsi->rss_key = rte_zmalloc(NULL,
3059                                            vsi->rss_key_size, 0);
3060                 if (vsi->rss_key == NULL) {
3061                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3062                         return -ENOMEM;
3063                 }
3064         }
3065         if (!vsi->rss_lut) {
3066                 vsi->rss_lut = rte_zmalloc(NULL,
3067                                            vsi->rss_lut_size, 0);
3068                 if (vsi->rss_lut == NULL) {
3069                         PMD_DRV_LOG(ERR, "Failed to allocate memory for rss_key");
3070                         rte_free(vsi->rss_key);
3071                         vsi->rss_key = NULL;
3072                         return -ENOMEM;
3073                 }
3074         }
3075         /* configure RSS key */
3076         if (!rss_conf->rss_key)
3077                 ice_get_default_rss_key(vsi->rss_key, vsi->rss_key_size);
3078         else
3079                 rte_memcpy(vsi->rss_key, rss_conf->rss_key,
3080                            RTE_MIN(rss_conf->rss_key_len,
3081                                    vsi->rss_key_size));
3082
3083         rte_memcpy(key.standard_rss_key, vsi->rss_key, vsi->rss_key_size);
3084         ret = ice_aq_set_rss_key(hw, vsi->idx, &key);
3085         if (ret)
3086                 goto out;
3087
3088         /* init RSS LUT table */
3089         for (i = 0; i < vsi->rss_lut_size; i++)
3090                 vsi->rss_lut[i] = i % nb_q;
3091
3092         lut_params.vsi_handle = vsi->idx;
3093         lut_params.lut_size = vsi->rss_lut_size;
3094         lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
3095         lut_params.lut = vsi->rss_lut;
3096         lut_params.global_lut_id = 0;
3097         ret = ice_aq_set_rss_lut(hw, &lut_params);
3098         if (ret)
3099                 goto out;
3100
3101         /* Enable registers for symmetric_toeplitz function. */
3102         reg = ICE_READ_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id));
3103         reg = (reg & (~VSIQF_HASH_CTL_HASH_SCHEME_M)) |
3104                 (1 << VSIQF_HASH_CTL_HASH_SCHEME_S);
3105         ICE_WRITE_REG(hw, VSIQF_HASH_CTL(vsi->vsi_id), reg);
3106
3107         /* RSS hash configuration */
3108         ice_rss_hash_set(pf, rss_conf->rss_hf);
3109
3110         return 0;
3111 out:
3112         rte_free(vsi->rss_key);
3113         vsi->rss_key = NULL;
3114         rte_free(vsi->rss_lut);
3115         vsi->rss_lut = NULL;
3116         return -EINVAL;
3117 }
3118
3119 static int
3120 ice_dev_configure(struct rte_eth_dev *dev)
3121 {
3122         struct ice_adapter *ad =
3123                 ICE_DEV_PRIVATE_TO_ADAPTER(dev->data->dev_private);
3124         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3125         int ret;
3126
3127         /* Initialize to TRUE. If any of Rx queues doesn't meet the
3128          * bulk allocation or vector Rx preconditions we will reset it.
3129          */
3130         ad->rx_bulk_alloc_allowed = true;
3131         ad->tx_simple_allowed = true;
3132
3133         if (dev->data->dev_conf.rxmode.mq_mode & ETH_MQ_RX_RSS_FLAG)
3134                 dev->data->dev_conf.rxmode.offloads |= DEV_RX_OFFLOAD_RSS_HASH;
3135
3136         if (dev->data->nb_rx_queues) {
3137                 ret = ice_init_rss(pf);
3138                 if (ret) {
3139                         PMD_DRV_LOG(ERR, "Failed to enable rss for PF");
3140                         return ret;
3141                 }
3142         }
3143
3144         return 0;
3145 }
3146
3147 static void
3148 __vsi_queues_bind_intr(struct ice_vsi *vsi, uint16_t msix_vect,
3149                        int base_queue, int nb_queue)
3150 {
3151         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3152         uint32_t val, val_tx;
3153         int i;
3154
3155         for (i = 0; i < nb_queue; i++) {
3156                 /*do actual bind*/
3157                 val = (msix_vect & QINT_RQCTL_MSIX_INDX_M) |
3158                       (0 << QINT_RQCTL_ITR_INDX_S) | QINT_RQCTL_CAUSE_ENA_M;
3159                 val_tx = (msix_vect & QINT_TQCTL_MSIX_INDX_M) |
3160                          (0 << QINT_TQCTL_ITR_INDX_S) | QINT_TQCTL_CAUSE_ENA_M;
3161
3162                 PMD_DRV_LOG(INFO, "queue %d is binding to vect %d",
3163                             base_queue + i, msix_vect);
3164                 /* set ITR0 value */
3165                 ICE_WRITE_REG(hw, GLINT_ITR(0, msix_vect), 0x2);
3166                 ICE_WRITE_REG(hw, QINT_RQCTL(base_queue + i), val);
3167                 ICE_WRITE_REG(hw, QINT_TQCTL(base_queue + i), val_tx);
3168         }
3169 }
3170
3171 void
3172 ice_vsi_queues_bind_intr(struct ice_vsi *vsi)
3173 {
3174         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3175         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3176         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3177         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3178         uint16_t msix_vect = vsi->msix_intr;
3179         uint16_t nb_msix = RTE_MIN(vsi->nb_msix, intr_handle->nb_efd);
3180         uint16_t queue_idx = 0;
3181         int record = 0;
3182         int i;
3183
3184         /* clear Rx/Tx queue interrupt */
3185         for (i = 0; i < vsi->nb_used_qps; i++) {
3186                 ICE_WRITE_REG(hw, QINT_TQCTL(vsi->base_queue + i), 0);
3187                 ICE_WRITE_REG(hw, QINT_RQCTL(vsi->base_queue + i), 0);
3188         }
3189
3190         /* PF bind interrupt */
3191         if (rte_intr_dp_is_en(intr_handle)) {
3192                 queue_idx = 0;
3193                 record = 1;
3194         }
3195
3196         for (i = 0; i < vsi->nb_used_qps; i++) {
3197                 if (nb_msix <= 1) {
3198                         if (!rte_intr_allow_others(intr_handle))
3199                                 msix_vect = ICE_MISC_VEC_ID;
3200
3201                         /* uio mapping all queue to one msix_vect */
3202                         __vsi_queues_bind_intr(vsi, msix_vect,
3203                                                vsi->base_queue + i,
3204                                                vsi->nb_used_qps - i);
3205
3206                         for (; !!record && i < vsi->nb_used_qps; i++)
3207                                 intr_handle->intr_vec[queue_idx + i] =
3208                                         msix_vect;
3209                         break;
3210                 }
3211
3212                 /* vfio 1:1 queue/msix_vect mapping */
3213                 __vsi_queues_bind_intr(vsi, msix_vect,
3214                                        vsi->base_queue + i, 1);
3215
3216                 if (!!record)
3217                         intr_handle->intr_vec[queue_idx + i] = msix_vect;
3218
3219                 msix_vect++;
3220                 nb_msix--;
3221         }
3222 }
3223
3224 void
3225 ice_vsi_enable_queues_intr(struct ice_vsi *vsi)
3226 {
3227         struct rte_eth_dev *dev = &rte_eth_devices[vsi->adapter->pf.dev_data->port_id];
3228         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3229         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3230         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3231         uint16_t msix_intr, i;
3232
3233         if (rte_intr_allow_others(intr_handle))
3234                 for (i = 0; i < vsi->nb_used_qps; i++) {
3235                         msix_intr = vsi->msix_intr + i;
3236                         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr),
3237                                       GLINT_DYN_CTL_INTENA_M |
3238                                       GLINT_DYN_CTL_CLEARPBA_M |
3239                                       GLINT_DYN_CTL_ITR_INDX_M |
3240                                       GLINT_DYN_CTL_WB_ON_ITR_M);
3241                 }
3242         else
3243                 ICE_WRITE_REG(hw, GLINT_DYN_CTL(0),
3244                               GLINT_DYN_CTL_INTENA_M |
3245                               GLINT_DYN_CTL_CLEARPBA_M |
3246                               GLINT_DYN_CTL_ITR_INDX_M |
3247                               GLINT_DYN_CTL_WB_ON_ITR_M);
3248 }
3249
3250 static int
3251 ice_rxq_intr_setup(struct rte_eth_dev *dev)
3252 {
3253         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3254         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
3255         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
3256         struct ice_vsi *vsi = pf->main_vsi;
3257         uint32_t intr_vector = 0;
3258
3259         rte_intr_disable(intr_handle);
3260
3261         /* check and configure queue intr-vector mapping */
3262         if ((rte_intr_cap_multiple(intr_handle) ||
3263              !RTE_ETH_DEV_SRIOV(dev).active) &&
3264             dev->data->dev_conf.intr_conf.rxq != 0) {
3265                 intr_vector = dev->data->nb_rx_queues;
3266                 if (intr_vector > ICE_MAX_INTR_QUEUE_NUM) {
3267                         PMD_DRV_LOG(ERR, "At most %d intr queues supported",
3268                                     ICE_MAX_INTR_QUEUE_NUM);
3269                         return -ENOTSUP;
3270                 }
3271                 if (rte_intr_efd_enable(intr_handle, intr_vector))
3272                         return -1;
3273         }
3274
3275         if (rte_intr_dp_is_en(intr_handle) && !intr_handle->intr_vec) {
3276                 intr_handle->intr_vec =
3277                 rte_zmalloc(NULL, dev->data->nb_rx_queues * sizeof(int),
3278                             0);
3279                 if (!intr_handle->intr_vec) {
3280                         PMD_DRV_LOG(ERR,
3281                                     "Failed to allocate %d rx_queues intr_vec",
3282                                     dev->data->nb_rx_queues);
3283                         return -ENOMEM;
3284                 }
3285         }
3286
3287         /* Map queues with MSIX interrupt */
3288         vsi->nb_used_qps = dev->data->nb_rx_queues;
3289         ice_vsi_queues_bind_intr(vsi);
3290
3291         /* Enable interrupts for all the queues */
3292         ice_vsi_enable_queues_intr(vsi);
3293
3294         rte_intr_enable(intr_handle);
3295
3296         return 0;
3297 }
3298
3299 static void
3300 ice_get_init_link_status(struct rte_eth_dev *dev)
3301 {
3302         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3303         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3304         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3305         struct ice_link_status link_status;
3306         int ret;
3307
3308         ret = ice_aq_get_link_info(hw->port_info, enable_lse,
3309                                    &link_status, NULL);
3310         if (ret != ICE_SUCCESS) {
3311                 PMD_DRV_LOG(ERR, "Failed to get link info");
3312                 pf->init_link_up = false;
3313                 return;
3314         }
3315
3316         if (link_status.link_info & ICE_AQ_LINK_UP)
3317                 pf->init_link_up = true;
3318 }
3319
3320 static int
3321 ice_dev_start(struct rte_eth_dev *dev)
3322 {
3323         struct rte_eth_dev_data *data = dev->data;
3324         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3325         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3326         struct ice_vsi *vsi = pf->main_vsi;
3327         uint16_t nb_rxq = 0;
3328         uint16_t nb_txq, i;
3329         uint16_t max_frame_size;
3330         int mask, ret;
3331
3332         /* program Tx queues' context in hardware */
3333         for (nb_txq = 0; nb_txq < data->nb_tx_queues; nb_txq++) {
3334                 ret = ice_tx_queue_start(dev, nb_txq);
3335                 if (ret) {
3336                         PMD_DRV_LOG(ERR, "fail to start Tx queue %u", nb_txq);
3337                         goto tx_err;
3338                 }
3339         }
3340
3341         /* program Rx queues' context in hardware*/
3342         for (nb_rxq = 0; nb_rxq < data->nb_rx_queues; nb_rxq++) {
3343                 ret = ice_rx_queue_start(dev, nb_rxq);
3344                 if (ret) {
3345                         PMD_DRV_LOG(ERR, "fail to start Rx queue %u", nb_rxq);
3346                         goto rx_err;
3347                 }
3348         }
3349
3350         ice_set_rx_function(dev);
3351         ice_set_tx_function(dev);
3352
3353         mask = ETH_VLAN_STRIP_MASK | ETH_VLAN_FILTER_MASK |
3354                         ETH_VLAN_EXTEND_MASK;
3355         ret = ice_vlan_offload_set(dev, mask);
3356         if (ret) {
3357                 PMD_INIT_LOG(ERR, "Unable to set VLAN offload");
3358                 goto rx_err;
3359         }
3360
3361         /* enable Rx interrput and mapping Rx queue to interrupt vector */
3362         if (ice_rxq_intr_setup(dev))
3363                 return -EIO;
3364
3365         /* Enable receiving broadcast packets and transmitting packets */
3366         ret = ice_set_vsi_promisc(hw, vsi->idx,
3367                                   ICE_PROMISC_BCAST_RX | ICE_PROMISC_BCAST_TX |
3368                                   ICE_PROMISC_UCAST_TX | ICE_PROMISC_MCAST_TX,
3369                                   0);
3370         if (ret != ICE_SUCCESS)
3371                 PMD_DRV_LOG(INFO, "fail to set vsi broadcast");
3372
3373         ret = ice_aq_set_event_mask(hw, hw->port_info->lport,
3374                                     ((u16)(ICE_AQ_LINK_EVENT_LINK_FAULT |
3375                                      ICE_AQ_LINK_EVENT_PHY_TEMP_ALARM |
3376                                      ICE_AQ_LINK_EVENT_EXCESSIVE_ERRORS |
3377                                      ICE_AQ_LINK_EVENT_SIGNAL_DETECT |
3378                                      ICE_AQ_LINK_EVENT_AN_COMPLETED |
3379                                      ICE_AQ_LINK_EVENT_PORT_TX_SUSPENDED)),
3380                                      NULL);
3381         if (ret != ICE_SUCCESS)
3382                 PMD_DRV_LOG(WARNING, "Fail to set phy mask");
3383
3384         ice_get_init_link_status(dev);
3385
3386         ice_dev_set_link_up(dev);
3387
3388         /* Call get_link_info aq commond to enable/disable LSE */
3389         ice_link_update(dev, 0);
3390
3391         pf->adapter_stopped = false;
3392
3393         /* Set the max frame size to default value*/
3394         max_frame_size = pf->dev_data->dev_conf.rxmode.max_rx_pkt_len ?
3395                 pf->dev_data->dev_conf.rxmode.max_rx_pkt_len :
3396                 ICE_FRAME_SIZE_MAX;
3397
3398         /* Set the max frame size to HW*/
3399         ice_aq_set_mac_cfg(hw, max_frame_size, NULL);
3400
3401         return 0;
3402
3403         /* stop the started queues if failed to start all queues */
3404 rx_err:
3405         for (i = 0; i < nb_rxq; i++)
3406                 ice_rx_queue_stop(dev, i);
3407 tx_err:
3408         for (i = 0; i < nb_txq; i++)
3409                 ice_tx_queue_stop(dev, i);
3410
3411         return -EIO;
3412 }
3413
3414 static int
3415 ice_dev_reset(struct rte_eth_dev *dev)
3416 {
3417         int ret;
3418
3419         if (dev->data->sriov.active)
3420                 return -ENOTSUP;
3421
3422         ret = ice_dev_uninit(dev);
3423         if (ret) {
3424                 PMD_INIT_LOG(ERR, "failed to uninit device, status = %d", ret);
3425                 return -ENXIO;
3426         }
3427
3428         ret = ice_dev_init(dev);
3429         if (ret) {
3430                 PMD_INIT_LOG(ERR, "failed to init device, status = %d", ret);
3431                 return -ENXIO;
3432         }
3433
3434         return 0;
3435 }
3436
3437 static int
3438 ice_dev_info_get(struct rte_eth_dev *dev, struct rte_eth_dev_info *dev_info)
3439 {
3440         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3441         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3442         struct ice_vsi *vsi = pf->main_vsi;
3443         struct rte_pci_device *pci_dev = RTE_DEV_TO_PCI(dev->device);
3444         bool is_safe_mode = pf->adapter->is_safe_mode;
3445         u64 phy_type_low;
3446         u64 phy_type_high;
3447
3448         dev_info->min_rx_bufsize = ICE_BUF_SIZE_MIN;
3449         dev_info->max_rx_pktlen = ICE_FRAME_SIZE_MAX;
3450         dev_info->max_rx_queues = vsi->nb_qps;
3451         dev_info->max_tx_queues = vsi->nb_qps;
3452         dev_info->max_mac_addrs = vsi->max_macaddrs;
3453         dev_info->max_vfs = pci_dev->max_vfs;
3454         dev_info->max_mtu = dev_info->max_rx_pktlen - ICE_ETH_OVERHEAD;
3455         dev_info->min_mtu = RTE_ETHER_MIN_MTU;
3456
3457         dev_info->rx_offload_capa =
3458                 DEV_RX_OFFLOAD_VLAN_STRIP |
3459                 DEV_RX_OFFLOAD_JUMBO_FRAME |
3460                 DEV_RX_OFFLOAD_KEEP_CRC |
3461                 DEV_RX_OFFLOAD_SCATTER |
3462                 DEV_RX_OFFLOAD_VLAN_FILTER;
3463         dev_info->tx_offload_capa =
3464                 DEV_TX_OFFLOAD_VLAN_INSERT |
3465                 DEV_TX_OFFLOAD_TCP_TSO |
3466                 DEV_TX_OFFLOAD_MULTI_SEGS |
3467                 DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3468         dev_info->flow_type_rss_offloads = 0;
3469
3470         if (!is_safe_mode) {
3471                 dev_info->rx_offload_capa |=
3472                         DEV_RX_OFFLOAD_IPV4_CKSUM |
3473                         DEV_RX_OFFLOAD_UDP_CKSUM |
3474                         DEV_RX_OFFLOAD_TCP_CKSUM |
3475                         DEV_RX_OFFLOAD_QINQ_STRIP |
3476                         DEV_RX_OFFLOAD_OUTER_IPV4_CKSUM |
3477                         DEV_RX_OFFLOAD_VLAN_EXTEND |
3478                         DEV_RX_OFFLOAD_RSS_HASH;
3479                 dev_info->tx_offload_capa |=
3480                         DEV_TX_OFFLOAD_QINQ_INSERT |
3481                         DEV_TX_OFFLOAD_IPV4_CKSUM |
3482                         DEV_TX_OFFLOAD_UDP_CKSUM |
3483                         DEV_TX_OFFLOAD_TCP_CKSUM |
3484                         DEV_TX_OFFLOAD_SCTP_CKSUM |
3485                         DEV_TX_OFFLOAD_OUTER_IPV4_CKSUM |
3486                         DEV_TX_OFFLOAD_OUTER_UDP_CKSUM;
3487                 dev_info->flow_type_rss_offloads |= ICE_RSS_OFFLOAD_ALL;
3488         }
3489
3490         dev_info->rx_queue_offload_capa = 0;
3491         dev_info->tx_queue_offload_capa = DEV_TX_OFFLOAD_MBUF_FAST_FREE;
3492
3493         dev_info->reta_size = pf->hash_lut_size;
3494         dev_info->hash_key_size = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
3495
3496         dev_info->default_rxconf = (struct rte_eth_rxconf) {
3497                 .rx_thresh = {
3498                         .pthresh = ICE_DEFAULT_RX_PTHRESH,
3499                         .hthresh = ICE_DEFAULT_RX_HTHRESH,
3500                         .wthresh = ICE_DEFAULT_RX_WTHRESH,
3501                 },
3502                 .rx_free_thresh = ICE_DEFAULT_RX_FREE_THRESH,
3503                 .rx_drop_en = 0,
3504                 .offloads = 0,
3505         };
3506
3507         dev_info->default_txconf = (struct rte_eth_txconf) {
3508                 .tx_thresh = {
3509                         .pthresh = ICE_DEFAULT_TX_PTHRESH,
3510                         .hthresh = ICE_DEFAULT_TX_HTHRESH,
3511                         .wthresh = ICE_DEFAULT_TX_WTHRESH,
3512                 },
3513                 .tx_free_thresh = ICE_DEFAULT_TX_FREE_THRESH,
3514                 .tx_rs_thresh = ICE_DEFAULT_TX_RSBIT_THRESH,
3515                 .offloads = 0,
3516         };
3517
3518         dev_info->rx_desc_lim = (struct rte_eth_desc_lim) {
3519                 .nb_max = ICE_MAX_RING_DESC,
3520                 .nb_min = ICE_MIN_RING_DESC,
3521                 .nb_align = ICE_ALIGN_RING_DESC,
3522         };
3523
3524         dev_info->tx_desc_lim = (struct rte_eth_desc_lim) {
3525                 .nb_max = ICE_MAX_RING_DESC,
3526                 .nb_min = ICE_MIN_RING_DESC,
3527                 .nb_align = ICE_ALIGN_RING_DESC,
3528         };
3529
3530         dev_info->speed_capa = ETH_LINK_SPEED_10M |
3531                                ETH_LINK_SPEED_100M |
3532                                ETH_LINK_SPEED_1G |
3533                                ETH_LINK_SPEED_2_5G |
3534                                ETH_LINK_SPEED_5G |
3535                                ETH_LINK_SPEED_10G |
3536                                ETH_LINK_SPEED_20G |
3537                                ETH_LINK_SPEED_25G;
3538
3539         phy_type_low = hw->port_info->phy.phy_type_low;
3540         phy_type_high = hw->port_info->phy.phy_type_high;
3541
3542         if (ICE_PHY_TYPE_SUPPORT_50G(phy_type_low))
3543                 dev_info->speed_capa |= ETH_LINK_SPEED_50G;
3544
3545         if (ICE_PHY_TYPE_SUPPORT_100G_LOW(phy_type_low) ||
3546                         ICE_PHY_TYPE_SUPPORT_100G_HIGH(phy_type_high))
3547                 dev_info->speed_capa |= ETH_LINK_SPEED_100G;
3548
3549         dev_info->nb_rx_queues = dev->data->nb_rx_queues;
3550         dev_info->nb_tx_queues = dev->data->nb_tx_queues;
3551
3552         dev_info->default_rxportconf.burst_size = ICE_RX_MAX_BURST;
3553         dev_info->default_txportconf.burst_size = ICE_TX_MAX_BURST;
3554         dev_info->default_rxportconf.nb_queues = 1;
3555         dev_info->default_txportconf.nb_queues = 1;
3556         dev_info->default_rxportconf.ring_size = ICE_BUF_SIZE_MIN;
3557         dev_info->default_txportconf.ring_size = ICE_BUF_SIZE_MIN;
3558
3559         return 0;
3560 }
3561
3562 static inline int
3563 ice_atomic_read_link_status(struct rte_eth_dev *dev,
3564                             struct rte_eth_link *link)
3565 {
3566         struct rte_eth_link *dst = link;
3567         struct rte_eth_link *src = &dev->data->dev_link;
3568
3569         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3570                                 *(uint64_t *)src) == 0)
3571                 return -1;
3572
3573         return 0;
3574 }
3575
3576 static inline int
3577 ice_atomic_write_link_status(struct rte_eth_dev *dev,
3578                              struct rte_eth_link *link)
3579 {
3580         struct rte_eth_link *dst = &dev->data->dev_link;
3581         struct rte_eth_link *src = link;
3582
3583         if (rte_atomic64_cmpset((uint64_t *)dst, *(uint64_t *)dst,
3584                                 *(uint64_t *)src) == 0)
3585                 return -1;
3586
3587         return 0;
3588 }
3589
3590 static int
3591 ice_link_update(struct rte_eth_dev *dev, int wait_to_complete)
3592 {
3593 #define CHECK_INTERVAL 100  /* 100ms */
3594 #define MAX_REPEAT_TIME 10  /* 1s (10 * 100ms) in total */
3595         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3596         struct ice_link_status link_status;
3597         struct rte_eth_link link, old;
3598         int status;
3599         unsigned int rep_cnt = MAX_REPEAT_TIME;
3600         bool enable_lse = dev->data->dev_conf.intr_conf.lsc ? true : false;
3601
3602         memset(&link, 0, sizeof(link));
3603         memset(&old, 0, sizeof(old));
3604         memset(&link_status, 0, sizeof(link_status));
3605         ice_atomic_read_link_status(dev, &old);
3606
3607         do {
3608                 /* Get link status information from hardware */
3609                 status = ice_aq_get_link_info(hw->port_info, enable_lse,
3610                                               &link_status, NULL);
3611                 if (status != ICE_SUCCESS) {
3612                         link.link_speed = ETH_SPEED_NUM_100M;
3613                         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3614                         PMD_DRV_LOG(ERR, "Failed to get link info");
3615                         goto out;
3616                 }
3617
3618                 link.link_status = link_status.link_info & ICE_AQ_LINK_UP;
3619                 if (!wait_to_complete || link.link_status)
3620                         break;
3621
3622                 rte_delay_ms(CHECK_INTERVAL);
3623         } while (--rep_cnt);
3624
3625         if (!link.link_status)
3626                 goto out;
3627
3628         /* Full-duplex operation at all supported speeds */
3629         link.link_duplex = ETH_LINK_FULL_DUPLEX;
3630
3631         /* Parse the link status */
3632         switch (link_status.link_speed) {
3633         case ICE_AQ_LINK_SPEED_10MB:
3634                 link.link_speed = ETH_SPEED_NUM_10M;
3635                 break;
3636         case ICE_AQ_LINK_SPEED_100MB:
3637                 link.link_speed = ETH_SPEED_NUM_100M;
3638                 break;
3639         case ICE_AQ_LINK_SPEED_1000MB:
3640                 link.link_speed = ETH_SPEED_NUM_1G;
3641                 break;
3642         case ICE_AQ_LINK_SPEED_2500MB:
3643                 link.link_speed = ETH_SPEED_NUM_2_5G;
3644                 break;
3645         case ICE_AQ_LINK_SPEED_5GB:
3646                 link.link_speed = ETH_SPEED_NUM_5G;
3647                 break;
3648         case ICE_AQ_LINK_SPEED_10GB:
3649                 link.link_speed = ETH_SPEED_NUM_10G;
3650                 break;
3651         case ICE_AQ_LINK_SPEED_20GB:
3652                 link.link_speed = ETH_SPEED_NUM_20G;
3653                 break;
3654         case ICE_AQ_LINK_SPEED_25GB:
3655                 link.link_speed = ETH_SPEED_NUM_25G;
3656                 break;
3657         case ICE_AQ_LINK_SPEED_40GB:
3658                 link.link_speed = ETH_SPEED_NUM_40G;
3659                 break;
3660         case ICE_AQ_LINK_SPEED_50GB:
3661                 link.link_speed = ETH_SPEED_NUM_50G;
3662                 break;
3663         case ICE_AQ_LINK_SPEED_100GB:
3664                 link.link_speed = ETH_SPEED_NUM_100G;
3665                 break;
3666         case ICE_AQ_LINK_SPEED_UNKNOWN:
3667                 PMD_DRV_LOG(ERR, "Unknown link speed");
3668                 link.link_speed = ETH_SPEED_NUM_UNKNOWN;
3669                 break;
3670         default:
3671                 PMD_DRV_LOG(ERR, "None link speed");
3672                 link.link_speed = ETH_SPEED_NUM_NONE;
3673                 break;
3674         }
3675
3676         link.link_autoneg = !(dev->data->dev_conf.link_speeds &
3677                               ETH_LINK_SPEED_FIXED);
3678
3679 out:
3680         ice_atomic_write_link_status(dev, &link);
3681         if (link.link_status == old.link_status)
3682                 return -1;
3683
3684         return 0;
3685 }
3686
3687 /* Force the physical link state by getting the current PHY capabilities from
3688  * hardware and setting the PHY config based on the determined capabilities. If
3689  * link changes, link event will be triggered because both the Enable Automatic
3690  * Link Update and LESM Enable bits are set when setting the PHY capabilities.
3691  */
3692 static enum ice_status
3693 ice_force_phys_link_state(struct ice_hw *hw, bool link_up)
3694 {
3695         struct ice_aqc_set_phy_cfg_data cfg = { 0 };
3696         struct ice_aqc_get_phy_caps_data *pcaps;
3697         struct ice_port_info *pi;
3698         enum ice_status status;
3699
3700         if (!hw || !hw->port_info)
3701                 return ICE_ERR_PARAM;
3702
3703         pi = hw->port_info;
3704
3705         pcaps = (struct ice_aqc_get_phy_caps_data *)
3706                 ice_malloc(hw, sizeof(*pcaps));
3707         if (!pcaps)
3708                 return ICE_ERR_NO_MEMORY;
3709
3710         status = ice_aq_get_phy_caps(pi, false, ICE_AQC_REPORT_ACTIVE_CFG,
3711                                      pcaps, NULL);
3712         if (status)
3713                 goto out;
3714
3715         /* No change in link */
3716         if (link_up == !!(pcaps->caps & ICE_AQC_PHY_EN_LINK) &&
3717             link_up == !!(pi->phy.link_info.link_info & ICE_AQ_LINK_UP))
3718                 goto out;
3719
3720         cfg.phy_type_low = pcaps->phy_type_low;
3721         cfg.phy_type_high = pcaps->phy_type_high;
3722         cfg.caps = pcaps->caps | ICE_AQ_PHY_ENA_AUTO_LINK_UPDT;
3723         cfg.low_power_ctrl_an = pcaps->low_power_ctrl_an;
3724         cfg.eee_cap = pcaps->eee_cap;
3725         cfg.eeer_value = pcaps->eeer_value;
3726         cfg.link_fec_opt = pcaps->link_fec_options;
3727         if (link_up)
3728                 cfg.caps |= ICE_AQ_PHY_ENA_LINK;
3729         else
3730                 cfg.caps &= ~ICE_AQ_PHY_ENA_LINK;
3731
3732         status = ice_aq_set_phy_cfg(hw, pi, &cfg, NULL);
3733
3734 out:
3735         ice_free(hw, pcaps);
3736         return status;
3737 }
3738
3739 static int
3740 ice_dev_set_link_up(struct rte_eth_dev *dev)
3741 {
3742         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3743
3744         return ice_force_phys_link_state(hw, true);
3745 }
3746
3747 static int
3748 ice_dev_set_link_down(struct rte_eth_dev *dev)
3749 {
3750         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3751
3752         return ice_force_phys_link_state(hw, false);
3753 }
3754
3755 static int
3756 ice_mtu_set(struct rte_eth_dev *dev, uint16_t mtu)
3757 {
3758         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3759         struct rte_eth_dev_data *dev_data = pf->dev_data;
3760         uint32_t frame_size = mtu + ICE_ETH_OVERHEAD;
3761
3762         /* check if mtu is within the allowed range */
3763         if (mtu < RTE_ETHER_MIN_MTU || frame_size > ICE_FRAME_SIZE_MAX)
3764                 return -EINVAL;
3765
3766         /* mtu setting is forbidden if port is start */
3767         if (dev_data->dev_started) {
3768                 PMD_DRV_LOG(ERR,
3769                             "port %d must be stopped before configuration",
3770                             dev_data->port_id);
3771                 return -EBUSY;
3772         }
3773
3774         if (frame_size > ICE_ETH_MAX_LEN)
3775                 dev_data->dev_conf.rxmode.offloads |=
3776                         DEV_RX_OFFLOAD_JUMBO_FRAME;
3777         else
3778                 dev_data->dev_conf.rxmode.offloads &=
3779                         ~DEV_RX_OFFLOAD_JUMBO_FRAME;
3780
3781         dev_data->dev_conf.rxmode.max_rx_pkt_len = frame_size;
3782
3783         return 0;
3784 }
3785
3786 static int ice_macaddr_set(struct rte_eth_dev *dev,
3787                            struct rte_ether_addr *mac_addr)
3788 {
3789         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
3790         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3791         struct ice_vsi *vsi = pf->main_vsi;
3792         struct ice_mac_filter *f;
3793         uint8_t flags = 0;
3794         int ret;
3795
3796         if (!rte_is_valid_assigned_ether_addr(mac_addr)) {
3797                 PMD_DRV_LOG(ERR, "Tried to set invalid MAC address.");
3798                 return -EINVAL;
3799         }
3800
3801         TAILQ_FOREACH(f, &vsi->mac_list, next) {
3802                 if (rte_is_same_ether_addr(&pf->dev_addr, &f->mac_info.mac_addr))
3803                         break;
3804         }
3805
3806         if (!f) {
3807                 PMD_DRV_LOG(ERR, "Failed to find filter for default mac");
3808                 return -EIO;
3809         }
3810
3811         ret = ice_remove_mac_filter(vsi, &f->mac_info.mac_addr);
3812         if (ret != ICE_SUCCESS) {
3813                 PMD_DRV_LOG(ERR, "Failed to delete mac filter");
3814                 return -EIO;
3815         }
3816         ret = ice_add_mac_filter(vsi, mac_addr);
3817         if (ret != ICE_SUCCESS) {
3818                 PMD_DRV_LOG(ERR, "Failed to add mac filter");
3819                 return -EIO;
3820         }
3821         rte_ether_addr_copy(mac_addr, &pf->dev_addr);
3822
3823         flags = ICE_AQC_MAN_MAC_UPDATE_LAA_WOL;
3824         ret = ice_aq_manage_mac_write(hw, mac_addr->addr_bytes, flags, NULL);
3825         if (ret != ICE_SUCCESS)
3826                 PMD_DRV_LOG(ERR, "Failed to set manage mac");
3827
3828         return 0;
3829 }
3830
3831 /* Add a MAC address, and update filters */
3832 static int
3833 ice_macaddr_add(struct rte_eth_dev *dev,
3834                 struct rte_ether_addr *mac_addr,
3835                 __rte_unused uint32_t index,
3836                 __rte_unused uint32_t pool)
3837 {
3838         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3839         struct ice_vsi *vsi = pf->main_vsi;
3840         int ret;
3841
3842         ret = ice_add_mac_filter(vsi, mac_addr);
3843         if (ret != ICE_SUCCESS) {
3844                 PMD_DRV_LOG(ERR, "Failed to add MAC filter");
3845                 return -EINVAL;
3846         }
3847
3848         return ICE_SUCCESS;
3849 }
3850
3851 /* Remove a MAC address, and update filters */
3852 static void
3853 ice_macaddr_remove(struct rte_eth_dev *dev, uint32_t index)
3854 {
3855         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3856         struct ice_vsi *vsi = pf->main_vsi;
3857         struct rte_eth_dev_data *data = dev->data;
3858         struct rte_ether_addr *macaddr;
3859         int ret;
3860
3861         macaddr = &data->mac_addrs[index];
3862         ret = ice_remove_mac_filter(vsi, macaddr);
3863         if (ret) {
3864                 PMD_DRV_LOG(ERR, "Failed to remove MAC filter");
3865                 return;
3866         }
3867 }
3868
3869 static int
3870 ice_vlan_filter_set(struct rte_eth_dev *dev, uint16_t vlan_id, int on)
3871 {
3872         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
3873         struct ice_vlan vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, vlan_id);
3874         struct ice_vsi *vsi = pf->main_vsi;
3875         int ret;
3876
3877         PMD_INIT_FUNC_TRACE();
3878
3879         /**
3880          * Vlan 0 is the generic filter for untagged packets
3881          * and can't be removed or added by user.
3882          */
3883         if (vlan_id == 0)
3884                 return 0;
3885
3886         if (on) {
3887                 ret = ice_add_vlan_filter(vsi, &vlan);
3888                 if (ret < 0) {
3889                         PMD_DRV_LOG(ERR, "Failed to add vlan filter");
3890                         return -EINVAL;
3891                 }
3892         } else {
3893                 ret = ice_remove_vlan_filter(vsi, &vlan);
3894                 if (ret < 0) {
3895                         PMD_DRV_LOG(ERR, "Failed to remove vlan filter");
3896                         return -EINVAL;
3897                 }
3898         }
3899
3900         return 0;
3901 }
3902
3903 /* In Single VLAN Mode (SVM), single VLAN filters via ICE_SW_LKUP_VLAN are
3904  * based on the inner VLAN ID, so the VLAN TPID (i.e. 0x8100 or 0x888a8)
3905  * doesn't matter. In Double VLAN Mode (DVM), outer/single VLAN filters via
3906  * ICE_SW_LKUP_VLAN are based on the outer/single VLAN ID + VLAN TPID.
3907  *
3908  * For both modes add a VLAN 0 + no VLAN TPID filter to handle untagged traffic
3909  * when VLAN pruning is enabled. Also, this handles VLAN 0 priority tagged
3910  * traffic in SVM, since the VLAN TPID isn't part of filtering.
3911  *
3912  * If DVM is enabled then an explicit VLAN 0 + VLAN TPID filter needs to be
3913  * added to allow VLAN 0 priority tagged traffic in DVM, since the VLAN TPID is
3914  * part of filtering.
3915  */
3916 static int
3917 ice_vsi_add_vlan_zero(struct ice_vsi *vsi)
3918 {
3919         struct ice_vlan vlan;
3920         int err;
3921
3922         vlan = ICE_VLAN(0, 0);
3923         err = ice_add_vlan_filter(vsi, &vlan);
3924         if (err) {
3925                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0");
3926                 return err;
3927         }
3928
3929         /* in SVM both VLAN 0 filters are identical */
3930         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3931                 return 0;
3932
3933         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3934         err = ice_add_vlan_filter(vsi, &vlan);
3935         if (err) {
3936                 PMD_DRV_LOG(DEBUG, "Failed to add VLAN ID 0 in double VLAN mode");
3937                 return err;
3938         }
3939
3940         return 0;
3941 }
3942
3943 /*
3944  * Delete the VLAN 0 filters in the same manner that they were added in
3945  * ice_vsi_add_vlan_zero.
3946  */
3947 static int
3948 ice_vsi_del_vlan_zero(struct ice_vsi *vsi)
3949 {
3950         struct ice_vlan vlan;
3951         int err;
3952
3953         vlan = ICE_VLAN(0, 0);
3954         err = ice_remove_vlan_filter(vsi, &vlan);
3955         if (err) {
3956                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0");
3957                 return err;
3958         }
3959
3960         /* in SVM both VLAN 0 filters are identical */
3961         if (!ice_is_dvm_ena(&vsi->adapter->hw))
3962                 return 0;
3963
3964         vlan = ICE_VLAN(RTE_ETHER_TYPE_VLAN, 0);
3965         err = ice_remove_vlan_filter(vsi, &vlan);
3966         if (err) {
3967                 PMD_DRV_LOG(DEBUG, "Failed to remove VLAN ID 0 in double VLAN mode");
3968                 return err;
3969         }
3970
3971         return 0;
3972 }
3973
3974 /* Configure vlan filter on or off */
3975 static int
3976 ice_vsi_config_vlan_filter(struct ice_vsi *vsi, bool on)
3977 {
3978         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
3979         struct ice_vsi_ctx ctxt;
3980         uint8_t sw_flags2;
3981         int ret = 0;
3982
3983         sw_flags2 = ICE_AQ_VSI_SW_FLAG_RX_VLAN_PRUNE_ENA;
3984
3985         if (on)
3986                 vsi->info.sw_flags2 |= sw_flags2;
3987         else
3988                 vsi->info.sw_flags2 &= ~sw_flags2;
3989
3990         vsi->info.sw_id = hw->port_info->sw_id;
3991         (void)rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
3992         ctxt.info.valid_sections =
3993                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
3994                                  ICE_AQ_VSI_PROP_SECURITY_VALID);
3995         ctxt.vsi_num = vsi->vsi_id;
3996
3997         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
3998         if (ret) {
3999                 PMD_DRV_LOG(INFO, "Update VSI failed to %s vlan rx pruning",
4000                             on ? "enable" : "disable");
4001                 return -EINVAL;
4002         } else {
4003                 vsi->info.valid_sections |=
4004                         rte_cpu_to_le_16(ICE_AQ_VSI_PROP_SW_VALID |
4005                                          ICE_AQ_VSI_PROP_SECURITY_VALID);
4006         }
4007
4008         /* consist with other drivers, allow untagged packet when vlan filter on */
4009         if (on)
4010                 ret = ice_vsi_add_vlan_zero(vsi);
4011         else
4012                 ret = ice_vsi_del_vlan_zero(vsi);
4013
4014         return 0;
4015 }
4016
4017 /* Manage VLAN stripping for the VSI for Rx */
4018 static int
4019 ice_vsi_manage_vlan_stripping(struct ice_vsi *vsi, bool ena)
4020 {
4021         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4022         struct ice_vsi_ctx ctxt;
4023         enum ice_status status;
4024         int err = 0;
4025
4026         /* do not allow modifying VLAN stripping when a port VLAN is configured
4027          * on this VSI
4028          */
4029         if (vsi->info.port_based_inner_vlan)
4030                 return 0;
4031
4032         memset(&ctxt, 0, sizeof(ctxt));
4033
4034         if (ena)
4035                 /* Strip VLAN tag from Rx packet and put it in the desc */
4036                 ctxt.info.inner_vlan_flags =
4037                                         ICE_AQ_VSI_INNER_VLAN_EMODE_STR_BOTH;
4038         else
4039                 /* Disable stripping. Leave tag in packet */
4040                 ctxt.info.inner_vlan_flags =
4041                                         ICE_AQ_VSI_INNER_VLAN_EMODE_NOTHING;
4042
4043         /* Allow all packets untagged/tagged */
4044         ctxt.info.inner_vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ALL;
4045
4046         ctxt.info.valid_sections = rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4047
4048         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4049         if (status) {
4050                 PMD_DRV_LOG(ERR, "Update VSI failed to %s vlan stripping",
4051                             ena ? "enable" : "disable");
4052                 err = -EIO;
4053         } else {
4054                 vsi->info.inner_vlan_flags = ctxt.info.inner_vlan_flags;
4055         }
4056
4057         return err;
4058 }
4059
4060 static int
4061 ice_vsi_ena_inner_stripping(struct ice_vsi *vsi)
4062 {
4063         return ice_vsi_manage_vlan_stripping(vsi, true);
4064 }
4065
4066 static int
4067 ice_vsi_dis_inner_stripping(struct ice_vsi *vsi)
4068 {
4069         return ice_vsi_manage_vlan_stripping(vsi, false);
4070 }
4071
4072 static int ice_vsi_ena_outer_stripping(struct ice_vsi *vsi)
4073 {
4074         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4075         struct ice_vsi_ctx ctxt;
4076         enum ice_status status;
4077         int err = 0;
4078
4079         /* do not allow modifying VLAN stripping when a port VLAN is configured
4080          * on this VSI
4081          */
4082         if (vsi->info.port_based_outer_vlan)
4083                 return 0;
4084
4085         memset(&ctxt, 0, sizeof(ctxt));
4086
4087         ctxt.info.valid_sections =
4088                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4089         /* clear current outer VLAN strip settings */
4090         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4091                 ~(ICE_AQ_VSI_OUTER_VLAN_EMODE_M | ICE_AQ_VSI_OUTER_TAG_TYPE_M);
4092         ctxt.info.outer_vlan_flags |=
4093                 (ICE_AQ_VSI_OUTER_VLAN_EMODE_SHOW_BOTH <<
4094                  ICE_AQ_VSI_OUTER_VLAN_EMODE_S) |
4095                 (ICE_AQ_VSI_OUTER_TAG_VLAN_8100 <<
4096                  ICE_AQ_VSI_OUTER_TAG_TYPE_S);
4097
4098         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4099         if (status) {
4100                 PMD_DRV_LOG(ERR, "Update VSI failed to enable outer VLAN stripping");
4101                 err = -EIO;
4102         } else {
4103                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4104         }
4105
4106         return err;
4107 }
4108
4109 static int
4110 ice_vsi_dis_outer_stripping(struct ice_vsi *vsi)
4111 {
4112         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4113         struct ice_vsi_ctx ctxt;
4114         enum ice_status status;
4115         int err = 0;
4116
4117         if (vsi->info.port_based_outer_vlan)
4118                 return 0;
4119
4120         memset(&ctxt, 0, sizeof(ctxt));
4121
4122         ctxt.info.valid_sections =
4123                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_OUTER_TAG_VALID);
4124         /* clear current outer VLAN strip settings */
4125         ctxt.info.outer_vlan_flags = vsi->info.outer_vlan_flags &
4126                 ~ICE_AQ_VSI_OUTER_VLAN_EMODE_M;
4127         ctxt.info.outer_vlan_flags |= ICE_AQ_VSI_OUTER_VLAN_EMODE_NOTHING <<
4128                 ICE_AQ_VSI_OUTER_VLAN_EMODE_S;
4129
4130         status = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4131         if (status) {
4132                 PMD_DRV_LOG(ERR, "Update VSI failed to disable outer VLAN stripping");
4133                 err = -EIO;
4134         } else {
4135                 vsi->info.outer_vlan_flags = ctxt.info.outer_vlan_flags;
4136         }
4137
4138         return err;
4139 }
4140
4141 static int
4142 ice_vsi_config_vlan_stripping(struct ice_vsi *vsi, bool ena)
4143 {
4144         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4145         int ret;
4146
4147         if (ice_is_dvm_ena(hw)) {
4148                 if (ena)
4149                         ret = ice_vsi_ena_outer_stripping(vsi);
4150                 else
4151                         ret = ice_vsi_dis_outer_stripping(vsi);
4152         } else {
4153                 if (ena)
4154                         ret = ice_vsi_ena_inner_stripping(vsi);
4155                 else
4156                         ret = ice_vsi_dis_inner_stripping(vsi);
4157         }
4158
4159         return ret;
4160 }
4161
4162 static int
4163 ice_vlan_offload_set(struct rte_eth_dev *dev, int mask)
4164 {
4165         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4166         struct ice_vsi *vsi = pf->main_vsi;
4167         struct rte_eth_rxmode *rxmode;
4168
4169         rxmode = &dev->data->dev_conf.rxmode;
4170         if (mask & ETH_VLAN_FILTER_MASK) {
4171                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_FILTER)
4172                         ice_vsi_config_vlan_filter(vsi, true);
4173                 else
4174                         ice_vsi_config_vlan_filter(vsi, false);
4175         }
4176
4177         if (mask & ETH_VLAN_STRIP_MASK) {
4178                 if (rxmode->offloads & DEV_RX_OFFLOAD_VLAN_STRIP)
4179                         ice_vsi_config_vlan_stripping(vsi, true);
4180                 else
4181                         ice_vsi_config_vlan_stripping(vsi, false);
4182         }
4183
4184         return 0;
4185 }
4186
4187 static int
4188 ice_get_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4189 {
4190         struct ice_aq_get_set_rss_lut_params lut_params;
4191         struct ice_pf *pf = ICE_VSI_TO_PF(vsi);
4192         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4193         int ret;
4194
4195         if (!lut)
4196                 return -EINVAL;
4197
4198         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4199                 lut_params.vsi_handle = vsi->idx;
4200                 lut_params.lut_size = lut_size;
4201                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4202                 lut_params.lut = lut;
4203                 lut_params.global_lut_id = 0;
4204                 ret = ice_aq_get_rss_lut(hw, &lut_params);
4205                 if (ret) {
4206                         PMD_DRV_LOG(ERR, "Failed to get RSS lookup table");
4207                         return -EINVAL;
4208                 }
4209         } else {
4210                 uint64_t *lut_dw = (uint64_t *)lut;
4211                 uint16_t i, lut_size_dw = lut_size / 4;
4212
4213                 for (i = 0; i < lut_size_dw; i++)
4214                         lut_dw[i] = ICE_READ_REG(hw, PFQF_HLUT(i));
4215         }
4216
4217         return 0;
4218 }
4219
4220 static int
4221 ice_set_rss_lut(struct ice_vsi *vsi, uint8_t *lut, uint16_t lut_size)
4222 {
4223         struct ice_aq_get_set_rss_lut_params lut_params;
4224         struct ice_pf *pf;
4225         struct ice_hw *hw;
4226         int ret;
4227
4228         if (!vsi || !lut)
4229                 return -EINVAL;
4230
4231         pf = ICE_VSI_TO_PF(vsi);
4232         hw = ICE_VSI_TO_HW(vsi);
4233
4234         if (pf->flags & ICE_FLAG_RSS_AQ_CAPABLE) {
4235                 lut_params.vsi_handle = vsi->idx;
4236                 lut_params.lut_size = lut_size;
4237                 lut_params.lut_type = ICE_AQC_GSET_RSS_LUT_TABLE_TYPE_PF;
4238                 lut_params.lut = lut;
4239                 lut_params.global_lut_id = 0;
4240                 ret = ice_aq_set_rss_lut(hw, &lut_params);
4241                 if (ret) {
4242                         PMD_DRV_LOG(ERR, "Failed to set RSS lookup table");
4243                         return -EINVAL;
4244                 }
4245         } else {
4246                 uint64_t *lut_dw = (uint64_t *)lut;
4247                 uint16_t i, lut_size_dw = lut_size / 4;
4248
4249                 for (i = 0; i < lut_size_dw; i++)
4250                         ICE_WRITE_REG(hw, PFQF_HLUT(i), lut_dw[i]);
4251
4252                 ice_flush(hw);
4253         }
4254
4255         return 0;
4256 }
4257
4258 static int
4259 ice_rss_reta_update(struct rte_eth_dev *dev,
4260                     struct rte_eth_rss_reta_entry64 *reta_conf,
4261                     uint16_t reta_size)
4262 {
4263         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4264         uint16_t i, lut_size = pf->hash_lut_size;
4265         uint16_t idx, shift;
4266         uint8_t *lut;
4267         int ret;
4268
4269         if (reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_128 &&
4270             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_512 &&
4271             reta_size != ICE_AQC_GSET_RSS_LUT_TABLE_SIZE_2K) {
4272                 PMD_DRV_LOG(ERR,
4273                             "The size of hash lookup table configured (%d)"
4274                             "doesn't match the number hardware can "
4275                             "supported (128, 512, 2048)",
4276                             reta_size);
4277                 return -EINVAL;
4278         }
4279
4280         /* It MUST use the current LUT size to get the RSS lookup table,
4281          * otherwise if will fail with -100 error code.
4282          */
4283         lut = rte_zmalloc(NULL,  RTE_MAX(reta_size, lut_size), 0);
4284         if (!lut) {
4285                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4286                 return -ENOMEM;
4287         }
4288         ret = ice_get_rss_lut(pf->main_vsi, lut, lut_size);
4289         if (ret)
4290                 goto out;
4291
4292         for (i = 0; i < reta_size; i++) {
4293                 idx = i / RTE_RETA_GROUP_SIZE;
4294                 shift = i % RTE_RETA_GROUP_SIZE;
4295                 if (reta_conf[idx].mask & (1ULL << shift))
4296                         lut[i] = reta_conf[idx].reta[shift];
4297         }
4298         ret = ice_set_rss_lut(pf->main_vsi, lut, reta_size);
4299         if (ret == 0 && lut_size != reta_size) {
4300                 PMD_DRV_LOG(INFO,
4301                             "The size of hash lookup table is changed from (%d) to (%d)",
4302                             lut_size, reta_size);
4303                 pf->hash_lut_size = reta_size;
4304         }
4305
4306 out:
4307         rte_free(lut);
4308
4309         return ret;
4310 }
4311
4312 static int
4313 ice_rss_reta_query(struct rte_eth_dev *dev,
4314                    struct rte_eth_rss_reta_entry64 *reta_conf,
4315                    uint16_t reta_size)
4316 {
4317         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4318         uint16_t i, lut_size = pf->hash_lut_size;
4319         uint16_t idx, shift;
4320         uint8_t *lut;
4321         int ret;
4322
4323         if (reta_size != lut_size) {
4324                 PMD_DRV_LOG(ERR,
4325                             "The size of hash lookup table configured (%d)"
4326                             "doesn't match the number hardware can "
4327                             "supported (%d)",
4328                             reta_size, lut_size);
4329                 return -EINVAL;
4330         }
4331
4332         lut = rte_zmalloc(NULL, reta_size, 0);
4333         if (!lut) {
4334                 PMD_DRV_LOG(ERR, "No memory can be allocated");
4335                 return -ENOMEM;
4336         }
4337
4338         ret = ice_get_rss_lut(pf->main_vsi, lut, reta_size);
4339         if (ret)
4340                 goto out;
4341
4342         for (i = 0; i < reta_size; i++) {
4343                 idx = i / RTE_RETA_GROUP_SIZE;
4344                 shift = i % RTE_RETA_GROUP_SIZE;
4345                 if (reta_conf[idx].mask & (1ULL << shift))
4346                         reta_conf[idx].reta[shift] = lut[i];
4347         }
4348
4349 out:
4350         rte_free(lut);
4351
4352         return ret;
4353 }
4354
4355 static int
4356 ice_set_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t key_len)
4357 {
4358         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4359         int ret = 0;
4360
4361         if (!key || key_len == 0) {
4362                 PMD_DRV_LOG(DEBUG, "No key to be configured");
4363                 return 0;
4364         } else if (key_len != (VSIQF_HKEY_MAX_INDEX + 1) *
4365                    sizeof(uint32_t)) {
4366                 PMD_DRV_LOG(ERR, "Invalid key length %u", key_len);
4367                 return -EINVAL;
4368         }
4369
4370         struct ice_aqc_get_set_rss_keys *key_dw =
4371                 (struct ice_aqc_get_set_rss_keys *)key;
4372
4373         ret = ice_aq_set_rss_key(hw, vsi->idx, key_dw);
4374         if (ret) {
4375                 PMD_DRV_LOG(ERR, "Failed to configure RSS key via AQ");
4376                 ret = -EINVAL;
4377         }
4378
4379         return ret;
4380 }
4381
4382 static int
4383 ice_get_rss_key(struct ice_vsi *vsi, uint8_t *key, uint8_t *key_len)
4384 {
4385         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4386         int ret;
4387
4388         if (!key || !key_len)
4389                 return -EINVAL;
4390
4391         ret = ice_aq_get_rss_key
4392                 (hw, vsi->idx,
4393                  (struct ice_aqc_get_set_rss_keys *)key);
4394         if (ret) {
4395                 PMD_DRV_LOG(ERR, "Failed to get RSS key via AQ");
4396                 return -EINVAL;
4397         }
4398         *key_len = (VSIQF_HKEY_MAX_INDEX + 1) * sizeof(uint32_t);
4399
4400         return 0;
4401 }
4402
4403 static int
4404 ice_rss_hash_update(struct rte_eth_dev *dev,
4405                     struct rte_eth_rss_conf *rss_conf)
4406 {
4407         enum ice_status status = ICE_SUCCESS;
4408         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4409         struct ice_vsi *vsi = pf->main_vsi;
4410
4411         /* set hash key */
4412         status = ice_set_rss_key(vsi, rss_conf->rss_key, rss_conf->rss_key_len);
4413         if (status)
4414                 return status;
4415
4416         if (rss_conf->rss_hf == 0) {
4417                 pf->rss_hf = 0;
4418                 return 0;
4419         }
4420
4421         /* RSS hash configuration */
4422         ice_rss_hash_set(pf, rss_conf->rss_hf);
4423
4424         return 0;
4425 }
4426
4427 static int
4428 ice_rss_hash_conf_get(struct rte_eth_dev *dev,
4429                       struct rte_eth_rss_conf *rss_conf)
4430 {
4431         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4432         struct ice_vsi *vsi = pf->main_vsi;
4433
4434         ice_get_rss_key(vsi, rss_conf->rss_key,
4435                         &rss_conf->rss_key_len);
4436
4437         rss_conf->rss_hf = pf->rss_hf;
4438         return 0;
4439 }
4440
4441 static int
4442 ice_promisc_enable(struct rte_eth_dev *dev)
4443 {
4444         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4445         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4446         struct ice_vsi *vsi = pf->main_vsi;
4447         enum ice_status status;
4448         uint8_t pmask;
4449         int ret = 0;
4450
4451         pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4452                 ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4453
4454         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4455         switch (status) {
4456         case ICE_ERR_ALREADY_EXISTS:
4457                 PMD_DRV_LOG(DEBUG, "Promisc mode has already been enabled");
4458         case ICE_SUCCESS:
4459                 break;
4460         default:
4461                 PMD_DRV_LOG(ERR, "Failed to enable promisc, err=%d", status);
4462                 ret = -EAGAIN;
4463         }
4464
4465         return ret;
4466 }
4467
4468 static int
4469 ice_promisc_disable(struct rte_eth_dev *dev)
4470 {
4471         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4472         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4473         struct ice_vsi *vsi = pf->main_vsi;
4474         enum ice_status status;
4475         uint8_t pmask;
4476         int ret = 0;
4477
4478         if (dev->data->all_multicast == 1)
4479                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX;
4480         else
4481                 pmask = ICE_PROMISC_UCAST_RX | ICE_PROMISC_UCAST_TX |
4482                         ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4483
4484         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4485         if (status != ICE_SUCCESS) {
4486                 PMD_DRV_LOG(ERR, "Failed to clear promisc, err=%d", status);
4487                 ret = -EAGAIN;
4488         }
4489
4490         return ret;
4491 }
4492
4493 static int
4494 ice_allmulti_enable(struct rte_eth_dev *dev)
4495 {
4496         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4497         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4498         struct ice_vsi *vsi = pf->main_vsi;
4499         enum ice_status status;
4500         uint8_t pmask;
4501         int ret = 0;
4502
4503         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4504
4505         status = ice_set_vsi_promisc(hw, vsi->idx, pmask, 0);
4506
4507         switch (status) {
4508         case ICE_ERR_ALREADY_EXISTS:
4509                 PMD_DRV_LOG(DEBUG, "Allmulti has already been enabled");
4510         case ICE_SUCCESS:
4511                 break;
4512         default:
4513                 PMD_DRV_LOG(ERR, "Failed to enable allmulti, err=%d", status);
4514                 ret = -EAGAIN;
4515         }
4516
4517         return ret;
4518 }
4519
4520 static int
4521 ice_allmulti_disable(struct rte_eth_dev *dev)
4522 {
4523         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4524         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4525         struct ice_vsi *vsi = pf->main_vsi;
4526         enum ice_status status;
4527         uint8_t pmask;
4528         int ret = 0;
4529
4530         if (dev->data->promiscuous == 1)
4531                 return 0; /* must remain in all_multicast mode */
4532
4533         pmask = ICE_PROMISC_MCAST_RX | ICE_PROMISC_MCAST_TX;
4534
4535         status = ice_clear_vsi_promisc(hw, vsi->idx, pmask, 0);
4536         if (status != ICE_SUCCESS) {
4537                 PMD_DRV_LOG(ERR, "Failed to clear allmulti, err=%d", status);
4538                 ret = -EAGAIN;
4539         }
4540
4541         return ret;
4542 }
4543
4544 static int ice_rx_queue_intr_enable(struct rte_eth_dev *dev,
4545                                     uint16_t queue_id)
4546 {
4547         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4548         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4549         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4550         uint32_t val;
4551         uint16_t msix_intr;
4552
4553         msix_intr = intr_handle->intr_vec[queue_id];
4554
4555         val = GLINT_DYN_CTL_INTENA_M | GLINT_DYN_CTL_CLEARPBA_M |
4556               GLINT_DYN_CTL_ITR_INDX_M;
4557         val &= ~GLINT_DYN_CTL_WB_ON_ITR_M;
4558
4559         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), val);
4560         rte_intr_ack(&pci_dev->intr_handle);
4561
4562         return 0;
4563 }
4564
4565 static int ice_rx_queue_intr_disable(struct rte_eth_dev *dev,
4566                                      uint16_t queue_id)
4567 {
4568         struct rte_pci_device *pci_dev = ICE_DEV_TO_PCI(dev);
4569         struct rte_intr_handle *intr_handle = &pci_dev->intr_handle;
4570         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4571         uint16_t msix_intr;
4572
4573         msix_intr = intr_handle->intr_vec[queue_id];
4574
4575         ICE_WRITE_REG(hw, GLINT_DYN_CTL(msix_intr), GLINT_DYN_CTL_WB_ON_ITR_M);
4576
4577         return 0;
4578 }
4579
4580 static int
4581 ice_fw_version_get(struct rte_eth_dev *dev, char *fw_version, size_t fw_size)
4582 {
4583         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4584         u8 ver, patch;
4585         u16 build;
4586         int ret;
4587
4588         ver = hw->flash.orom.major;
4589         patch = hw->flash.orom.patch;
4590         build = hw->flash.orom.build;
4591
4592         ret = snprintf(fw_version, fw_size,
4593                         "%x.%02x 0x%08x %d.%d.%d",
4594                         hw->flash.nvm.major,
4595                         hw->flash.nvm.minor,
4596                         hw->flash.nvm.eetrack,
4597                         ver, build, patch);
4598         if (ret < 0)
4599                 return -EINVAL;
4600
4601         /* add the size of '\0' */
4602         ret += 1;
4603         if (fw_size < (size_t)ret)
4604                 return ret;
4605         else
4606                 return 0;
4607 }
4608
4609 static int
4610 ice_vsi_vlan_pvid_set(struct ice_vsi *vsi, struct ice_vsi_vlan_pvid_info *info)
4611 {
4612         struct ice_hw *hw;
4613         struct ice_vsi_ctx ctxt;
4614         uint8_t vlan_flags = 0;
4615         int ret;
4616
4617         if (!vsi || !info) {
4618                 PMD_DRV_LOG(ERR, "invalid parameters");
4619                 return -EINVAL;
4620         }
4621
4622         if (info->on) {
4623                 vsi->info.port_based_inner_vlan = info->config.pvid;
4624                 /**
4625                  * If insert pvid is enabled, only tagged pkts are
4626                  * allowed to be sent out.
4627                  */
4628                 vlan_flags = ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4629                              ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4630         } else {
4631                 vsi->info.port_based_inner_vlan = 0;
4632                 if (info->config.reject.tagged == 0)
4633                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTTAGGED;
4634
4635                 if (info->config.reject.untagged == 0)
4636                         vlan_flags |= ICE_AQ_VSI_INNER_VLAN_TX_MODE_ACCEPTUNTAGGED;
4637         }
4638         vsi->info.inner_vlan_flags &= ~(ICE_AQ_VSI_INNER_VLAN_INSERT_PVID |
4639                                   ICE_AQ_VSI_INNER_VLAN_EMODE_M);
4640         vsi->info.inner_vlan_flags |= vlan_flags;
4641         memset(&ctxt, 0, sizeof(ctxt));
4642         rte_memcpy(&ctxt.info, &vsi->info, sizeof(vsi->info));
4643         ctxt.info.valid_sections =
4644                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4645         ctxt.vsi_num = vsi->vsi_id;
4646
4647         hw = ICE_VSI_TO_HW(vsi);
4648         ret = ice_update_vsi(hw, vsi->idx, &ctxt, NULL);
4649         if (ret != ICE_SUCCESS) {
4650                 PMD_DRV_LOG(ERR,
4651                             "update VSI for VLAN insert failed, err %d",
4652                             ret);
4653                 return -EINVAL;
4654         }
4655
4656         vsi->info.valid_sections |=
4657                 rte_cpu_to_le_16(ICE_AQ_VSI_PROP_VLAN_VALID);
4658
4659         return ret;
4660 }
4661
4662 static int
4663 ice_vlan_pvid_set(struct rte_eth_dev *dev, uint16_t pvid, int on)
4664 {
4665         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
4666         struct ice_vsi *vsi = pf->main_vsi;
4667         struct rte_eth_dev_data *data = pf->dev_data;
4668         struct ice_vsi_vlan_pvid_info info;
4669         int ret;
4670
4671         memset(&info, 0, sizeof(info));
4672         info.on = on;
4673         if (info.on) {
4674                 info.config.pvid = pvid;
4675         } else {
4676                 info.config.reject.tagged =
4677                         data->dev_conf.txmode.hw_vlan_reject_tagged;
4678                 info.config.reject.untagged =
4679                         data->dev_conf.txmode.hw_vlan_reject_untagged;
4680         }
4681
4682         ret = ice_vsi_vlan_pvid_set(vsi, &info);
4683         if (ret < 0) {
4684                 PMD_DRV_LOG(ERR, "Failed to set pvid.");
4685                 return -EINVAL;
4686         }
4687
4688         return 0;
4689 }
4690
4691 static int
4692 ice_get_eeprom_length(struct rte_eth_dev *dev)
4693 {
4694         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4695
4696         return hw->flash.flash_size;
4697 }
4698
4699 static int
4700 ice_get_eeprom(struct rte_eth_dev *dev,
4701                struct rte_dev_eeprom_info *eeprom)
4702 {
4703         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
4704         enum ice_status status = ICE_SUCCESS;
4705         uint8_t *data = eeprom->data;
4706
4707         eeprom->magic = hw->vendor_id | (hw->device_id << 16);
4708
4709         status = ice_acquire_nvm(hw, ICE_RES_READ);
4710         if (status) {
4711                 PMD_DRV_LOG(ERR, "acquire nvm failed.");
4712                 return -EIO;
4713         }
4714
4715         status = ice_read_flat_nvm(hw, eeprom->offset, &eeprom->length,
4716                                    data, false);
4717
4718         ice_release_nvm(hw);
4719
4720         if (status) {
4721                 PMD_DRV_LOG(ERR, "EEPROM read failed.");
4722                 return -EIO;
4723         }
4724
4725         return 0;
4726 }
4727
4728 static void
4729 ice_stat_update_32(struct ice_hw *hw,
4730                    uint32_t reg,
4731                    bool offset_loaded,
4732                    uint64_t *offset,
4733                    uint64_t *stat)
4734 {
4735         uint64_t new_data;
4736
4737         new_data = (uint64_t)ICE_READ_REG(hw, reg);
4738         if (!offset_loaded)
4739                 *offset = new_data;
4740
4741         if (new_data >= *offset)
4742                 *stat = (uint64_t)(new_data - *offset);
4743         else
4744                 *stat = (uint64_t)((new_data +
4745                                     ((uint64_t)1 << ICE_32_BIT_WIDTH))
4746                                    - *offset);
4747 }
4748
4749 static void
4750 ice_stat_update_40(struct ice_hw *hw,
4751                    uint32_t hireg,
4752                    uint32_t loreg,
4753                    bool offset_loaded,
4754                    uint64_t *offset,
4755                    uint64_t *stat)
4756 {
4757         uint64_t new_data;
4758
4759         new_data = (uint64_t)ICE_READ_REG(hw, loreg);
4760         new_data |= (uint64_t)(ICE_READ_REG(hw, hireg) & ICE_8_BIT_MASK) <<
4761                     ICE_32_BIT_WIDTH;
4762
4763         if (!offset_loaded)
4764                 *offset = new_data;
4765
4766         if (new_data >= *offset)
4767                 *stat = new_data - *offset;
4768         else
4769                 *stat = (uint64_t)((new_data +
4770                                     ((uint64_t)1 << ICE_40_BIT_WIDTH)) -
4771                                    *offset);
4772
4773         *stat &= ICE_40_BIT_MASK;
4774 }
4775
4776 /* Get all the statistics of a VSI */
4777 static void
4778 ice_update_vsi_stats(struct ice_vsi *vsi)
4779 {
4780         struct ice_eth_stats *oes = &vsi->eth_stats_offset;
4781         struct ice_eth_stats *nes = &vsi->eth_stats;
4782         struct ice_hw *hw = ICE_VSI_TO_HW(vsi);
4783         int idx = rte_le_to_cpu_16(vsi->vsi_id);
4784
4785         ice_stat_update_40(hw, GLV_GORCH(idx), GLV_GORCL(idx),
4786                            vsi->offset_loaded, &oes->rx_bytes,
4787                            &nes->rx_bytes);
4788         ice_stat_update_40(hw, GLV_UPRCH(idx), GLV_UPRCL(idx),
4789                            vsi->offset_loaded, &oes->rx_unicast,
4790                            &nes->rx_unicast);
4791         ice_stat_update_40(hw, GLV_MPRCH(idx), GLV_MPRCL(idx),
4792                            vsi->offset_loaded, &oes->rx_multicast,
4793                            &nes->rx_multicast);
4794         ice_stat_update_40(hw, GLV_BPRCH(idx), GLV_BPRCL(idx),
4795                            vsi->offset_loaded, &oes->rx_broadcast,
4796                            &nes->rx_broadcast);
4797         /* enlarge the limitation when rx_bytes overflowed */
4798         if (vsi->offset_loaded) {
4799                 if (ICE_RXTX_BYTES_LOW(vsi->old_rx_bytes) > nes->rx_bytes)
4800                         nes->rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4801                 nes->rx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_rx_bytes);
4802         }
4803         vsi->old_rx_bytes = nes->rx_bytes;
4804         /* exclude CRC bytes */
4805         nes->rx_bytes -= (nes->rx_unicast + nes->rx_multicast +
4806                           nes->rx_broadcast) * RTE_ETHER_CRC_LEN;
4807
4808         ice_stat_update_32(hw, GLV_RDPC(idx), vsi->offset_loaded,
4809                            &oes->rx_discards, &nes->rx_discards);
4810         /* GLV_REPC not supported */
4811         /* GLV_RMPC not supported */
4812         ice_stat_update_32(hw, GLSWID_RUPP(idx), vsi->offset_loaded,
4813                            &oes->rx_unknown_protocol,
4814                            &nes->rx_unknown_protocol);
4815         ice_stat_update_40(hw, GLV_GOTCH(idx), GLV_GOTCL(idx),
4816                            vsi->offset_loaded, &oes->tx_bytes,
4817                            &nes->tx_bytes);
4818         ice_stat_update_40(hw, GLV_UPTCH(idx), GLV_UPTCL(idx),
4819                            vsi->offset_loaded, &oes->tx_unicast,
4820                            &nes->tx_unicast);
4821         ice_stat_update_40(hw, GLV_MPTCH(idx), GLV_MPTCL(idx),
4822                            vsi->offset_loaded, &oes->tx_multicast,
4823                            &nes->tx_multicast);
4824         ice_stat_update_40(hw, GLV_BPTCH(idx), GLV_BPTCL(idx),
4825                            vsi->offset_loaded,  &oes->tx_broadcast,
4826                            &nes->tx_broadcast);
4827         /* GLV_TDPC not supported */
4828         ice_stat_update_32(hw, GLV_TEPC(idx), vsi->offset_loaded,
4829                            &oes->tx_errors, &nes->tx_errors);
4830         /* enlarge the limitation when tx_bytes overflowed */
4831         if (vsi->offset_loaded) {
4832                 if (ICE_RXTX_BYTES_LOW(vsi->old_tx_bytes) > nes->tx_bytes)
4833                         nes->tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4834                 nes->tx_bytes += ICE_RXTX_BYTES_HIGH(vsi->old_tx_bytes);
4835         }
4836         vsi->old_tx_bytes = nes->tx_bytes;
4837         vsi->offset_loaded = true;
4838
4839         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats start **************",
4840                     vsi->vsi_id);
4841         PMD_DRV_LOG(DEBUG, "rx_bytes:            %"PRIu64"", nes->rx_bytes);
4842         PMD_DRV_LOG(DEBUG, "rx_unicast:          %"PRIu64"", nes->rx_unicast);
4843         PMD_DRV_LOG(DEBUG, "rx_multicast:        %"PRIu64"", nes->rx_multicast);
4844         PMD_DRV_LOG(DEBUG, "rx_broadcast:        %"PRIu64"", nes->rx_broadcast);
4845         PMD_DRV_LOG(DEBUG, "rx_discards:         %"PRIu64"", nes->rx_discards);
4846         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol: %"PRIu64"",
4847                     nes->rx_unknown_protocol);
4848         PMD_DRV_LOG(DEBUG, "tx_bytes:            %"PRIu64"", nes->tx_bytes);
4849         PMD_DRV_LOG(DEBUG, "tx_unicast:          %"PRIu64"", nes->tx_unicast);
4850         PMD_DRV_LOG(DEBUG, "tx_multicast:        %"PRIu64"", nes->tx_multicast);
4851         PMD_DRV_LOG(DEBUG, "tx_broadcast:        %"PRIu64"", nes->tx_broadcast);
4852         PMD_DRV_LOG(DEBUG, "tx_discards:         %"PRIu64"", nes->tx_discards);
4853         PMD_DRV_LOG(DEBUG, "tx_errors:           %"PRIu64"", nes->tx_errors);
4854         PMD_DRV_LOG(DEBUG, "************** VSI[%u] stats end ****************",
4855                     vsi->vsi_id);
4856 }
4857
4858 static void
4859 ice_read_stats_registers(struct ice_pf *pf, struct ice_hw *hw)
4860 {
4861         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
4862         struct ice_hw_port_stats *os = &pf->stats_offset; /* old stats */
4863
4864         /* Get statistics of struct ice_eth_stats */
4865         ice_stat_update_40(hw, GLPRT_GORCH(hw->port_info->lport),
4866                            GLPRT_GORCL(hw->port_info->lport),
4867                            pf->offset_loaded, &os->eth.rx_bytes,
4868                            &ns->eth.rx_bytes);
4869         ice_stat_update_40(hw, GLPRT_UPRCH(hw->port_info->lport),
4870                            GLPRT_UPRCL(hw->port_info->lport),
4871                            pf->offset_loaded, &os->eth.rx_unicast,
4872                            &ns->eth.rx_unicast);
4873         ice_stat_update_40(hw, GLPRT_MPRCH(hw->port_info->lport),
4874                            GLPRT_MPRCL(hw->port_info->lport),
4875                            pf->offset_loaded, &os->eth.rx_multicast,
4876                            &ns->eth.rx_multicast);
4877         ice_stat_update_40(hw, GLPRT_BPRCH(hw->port_info->lport),
4878                            GLPRT_BPRCL(hw->port_info->lport),
4879                            pf->offset_loaded, &os->eth.rx_broadcast,
4880                            &ns->eth.rx_broadcast);
4881         ice_stat_update_32(hw, PRTRPB_RDPC,
4882                            pf->offset_loaded, &os->eth.rx_discards,
4883                            &ns->eth.rx_discards);
4884         /* enlarge the limitation when rx_bytes overflowed */
4885         if (pf->offset_loaded) {
4886                 if (ICE_RXTX_BYTES_LOW(pf->old_rx_bytes) > ns->eth.rx_bytes)
4887                         ns->eth.rx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4888                 ns->eth.rx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_rx_bytes);
4889         }
4890         pf->old_rx_bytes = ns->eth.rx_bytes;
4891
4892         /* Workaround: CRC size should not be included in byte statistics,
4893          * so subtract RTE_ETHER_CRC_LEN from the byte counter for each rx
4894          * packet.
4895          */
4896         ns->eth.rx_bytes -= (ns->eth.rx_unicast + ns->eth.rx_multicast +
4897                              ns->eth.rx_broadcast) * RTE_ETHER_CRC_LEN;
4898
4899         /* GLPRT_REPC not supported */
4900         /* GLPRT_RMPC not supported */
4901         ice_stat_update_32(hw, GLSWID_RUPP(hw->port_info->lport),
4902                            pf->offset_loaded,
4903                            &os->eth.rx_unknown_protocol,
4904                            &ns->eth.rx_unknown_protocol);
4905         ice_stat_update_40(hw, GLPRT_GOTCH(hw->port_info->lport),
4906                            GLPRT_GOTCL(hw->port_info->lport),
4907                            pf->offset_loaded, &os->eth.tx_bytes,
4908                            &ns->eth.tx_bytes);
4909         ice_stat_update_40(hw, GLPRT_UPTCH(hw->port_info->lport),
4910                            GLPRT_UPTCL(hw->port_info->lport),
4911                            pf->offset_loaded, &os->eth.tx_unicast,
4912                            &ns->eth.tx_unicast);
4913         ice_stat_update_40(hw, GLPRT_MPTCH(hw->port_info->lport),
4914                            GLPRT_MPTCL(hw->port_info->lport),
4915                            pf->offset_loaded, &os->eth.tx_multicast,
4916                            &ns->eth.tx_multicast);
4917         ice_stat_update_40(hw, GLPRT_BPTCH(hw->port_info->lport),
4918                            GLPRT_BPTCL(hw->port_info->lport),
4919                            pf->offset_loaded, &os->eth.tx_broadcast,
4920                            &ns->eth.tx_broadcast);
4921         /* enlarge the limitation when tx_bytes overflowed */
4922         if (pf->offset_loaded) {
4923                 if (ICE_RXTX_BYTES_LOW(pf->old_tx_bytes) > ns->eth.tx_bytes)
4924                         ns->eth.tx_bytes += (uint64_t)1 << ICE_40_BIT_WIDTH;
4925                 ns->eth.tx_bytes += ICE_RXTX_BYTES_HIGH(pf->old_tx_bytes);
4926         }
4927         pf->old_tx_bytes = ns->eth.tx_bytes;
4928         ns->eth.tx_bytes -= (ns->eth.tx_unicast + ns->eth.tx_multicast +
4929                              ns->eth.tx_broadcast) * RTE_ETHER_CRC_LEN;
4930
4931         /* GLPRT_TEPC not supported */
4932
4933         /* additional port specific stats */
4934         ice_stat_update_32(hw, GLPRT_TDOLD(hw->port_info->lport),
4935                            pf->offset_loaded, &os->tx_dropped_link_down,
4936                            &ns->tx_dropped_link_down);
4937         ice_stat_update_32(hw, GLPRT_CRCERRS(hw->port_info->lport),
4938                            pf->offset_loaded, &os->crc_errors,
4939                            &ns->crc_errors);
4940         ice_stat_update_32(hw, GLPRT_ILLERRC(hw->port_info->lport),
4941                            pf->offset_loaded, &os->illegal_bytes,
4942                            &ns->illegal_bytes);
4943         /* GLPRT_ERRBC not supported */
4944         ice_stat_update_32(hw, GLPRT_MLFC(hw->port_info->lport),
4945                            pf->offset_loaded, &os->mac_local_faults,
4946                            &ns->mac_local_faults);
4947         ice_stat_update_32(hw, GLPRT_MRFC(hw->port_info->lport),
4948                            pf->offset_loaded, &os->mac_remote_faults,
4949                            &ns->mac_remote_faults);
4950
4951         ice_stat_update_32(hw, GLPRT_RLEC(hw->port_info->lport),
4952                            pf->offset_loaded, &os->rx_len_errors,
4953                            &ns->rx_len_errors);
4954
4955         ice_stat_update_32(hw, GLPRT_LXONRXC(hw->port_info->lport),
4956                            pf->offset_loaded, &os->link_xon_rx,
4957                            &ns->link_xon_rx);
4958         ice_stat_update_32(hw, GLPRT_LXOFFRXC(hw->port_info->lport),
4959                            pf->offset_loaded, &os->link_xoff_rx,
4960                            &ns->link_xoff_rx);
4961         ice_stat_update_32(hw, GLPRT_LXONTXC(hw->port_info->lport),
4962                            pf->offset_loaded, &os->link_xon_tx,
4963                            &ns->link_xon_tx);
4964         ice_stat_update_32(hw, GLPRT_LXOFFTXC(hw->port_info->lport),
4965                            pf->offset_loaded, &os->link_xoff_tx,
4966                            &ns->link_xoff_tx);
4967         ice_stat_update_40(hw, GLPRT_PRC64H(hw->port_info->lport),
4968                            GLPRT_PRC64L(hw->port_info->lport),
4969                            pf->offset_loaded, &os->rx_size_64,
4970                            &ns->rx_size_64);
4971         ice_stat_update_40(hw, GLPRT_PRC127H(hw->port_info->lport),
4972                            GLPRT_PRC127L(hw->port_info->lport),
4973                            pf->offset_loaded, &os->rx_size_127,
4974                            &ns->rx_size_127);
4975         ice_stat_update_40(hw, GLPRT_PRC255H(hw->port_info->lport),
4976                            GLPRT_PRC255L(hw->port_info->lport),
4977                            pf->offset_loaded, &os->rx_size_255,
4978                            &ns->rx_size_255);
4979         ice_stat_update_40(hw, GLPRT_PRC511H(hw->port_info->lport),
4980                            GLPRT_PRC511L(hw->port_info->lport),
4981                            pf->offset_loaded, &os->rx_size_511,
4982                            &ns->rx_size_511);
4983         ice_stat_update_40(hw, GLPRT_PRC1023H(hw->port_info->lport),
4984                            GLPRT_PRC1023L(hw->port_info->lport),
4985                            pf->offset_loaded, &os->rx_size_1023,
4986                            &ns->rx_size_1023);
4987         ice_stat_update_40(hw, GLPRT_PRC1522H(hw->port_info->lport),
4988                            GLPRT_PRC1522L(hw->port_info->lport),
4989                            pf->offset_loaded, &os->rx_size_1522,
4990                            &ns->rx_size_1522);
4991         ice_stat_update_40(hw, GLPRT_PRC9522H(hw->port_info->lport),
4992                            GLPRT_PRC9522L(hw->port_info->lport),
4993                            pf->offset_loaded, &os->rx_size_big,
4994                            &ns->rx_size_big);
4995         ice_stat_update_32(hw, GLPRT_RUC(hw->port_info->lport),
4996                            pf->offset_loaded, &os->rx_undersize,
4997                            &ns->rx_undersize);
4998         ice_stat_update_32(hw, GLPRT_RFC(hw->port_info->lport),
4999                            pf->offset_loaded, &os->rx_fragments,
5000                            &ns->rx_fragments);
5001         ice_stat_update_32(hw, GLPRT_ROC(hw->port_info->lport),
5002                            pf->offset_loaded, &os->rx_oversize,
5003                            &ns->rx_oversize);
5004         ice_stat_update_32(hw, GLPRT_RJC(hw->port_info->lport),
5005                            pf->offset_loaded, &os->rx_jabber,
5006                            &ns->rx_jabber);
5007         ice_stat_update_40(hw, GLPRT_PTC64H(hw->port_info->lport),
5008                            GLPRT_PTC64L(hw->port_info->lport),
5009                            pf->offset_loaded, &os->tx_size_64,
5010                            &ns->tx_size_64);
5011         ice_stat_update_40(hw, GLPRT_PTC127H(hw->port_info->lport),
5012                            GLPRT_PTC127L(hw->port_info->lport),
5013                            pf->offset_loaded, &os->tx_size_127,
5014                            &ns->tx_size_127);
5015         ice_stat_update_40(hw, GLPRT_PTC255H(hw->port_info->lport),
5016                            GLPRT_PTC255L(hw->port_info->lport),
5017                            pf->offset_loaded, &os->tx_size_255,
5018                            &ns->tx_size_255);
5019         ice_stat_update_40(hw, GLPRT_PTC511H(hw->port_info->lport),
5020                            GLPRT_PTC511L(hw->port_info->lport),
5021                            pf->offset_loaded, &os->tx_size_511,
5022                            &ns->tx_size_511);
5023         ice_stat_update_40(hw, GLPRT_PTC1023H(hw->port_info->lport),
5024                            GLPRT_PTC1023L(hw->port_info->lport),
5025                            pf->offset_loaded, &os->tx_size_1023,
5026                            &ns->tx_size_1023);
5027         ice_stat_update_40(hw, GLPRT_PTC1522H(hw->port_info->lport),
5028                            GLPRT_PTC1522L(hw->port_info->lport),
5029                            pf->offset_loaded, &os->tx_size_1522,
5030                            &ns->tx_size_1522);
5031         ice_stat_update_40(hw, GLPRT_PTC9522H(hw->port_info->lport),
5032                            GLPRT_PTC9522L(hw->port_info->lport),
5033                            pf->offset_loaded, &os->tx_size_big,
5034                            &ns->tx_size_big);
5035
5036         /* GLPRT_MSPDC not supported */
5037         /* GLPRT_XEC not supported */
5038
5039         pf->offset_loaded = true;
5040
5041         if (pf->main_vsi)
5042                 ice_update_vsi_stats(pf->main_vsi);
5043 }
5044
5045 /* Get all statistics of a port */
5046 static int
5047 ice_stats_get(struct rte_eth_dev *dev, struct rte_eth_stats *stats)
5048 {
5049         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5050         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5051         struct ice_hw_port_stats *ns = &pf->stats; /* new stats */
5052
5053         /* call read registers - updates values, now write them to struct */
5054         ice_read_stats_registers(pf, hw);
5055
5056         stats->ipackets = pf->main_vsi->eth_stats.rx_unicast +
5057                           pf->main_vsi->eth_stats.rx_multicast +
5058                           pf->main_vsi->eth_stats.rx_broadcast -
5059                           pf->main_vsi->eth_stats.rx_discards;
5060         stats->opackets = ns->eth.tx_unicast +
5061                           ns->eth.tx_multicast +
5062                           ns->eth.tx_broadcast;
5063         stats->ibytes   = pf->main_vsi->eth_stats.rx_bytes;
5064         stats->obytes   = ns->eth.tx_bytes;
5065         stats->oerrors  = ns->eth.tx_errors +
5066                           pf->main_vsi->eth_stats.tx_errors;
5067
5068         /* Rx Errors */
5069         stats->imissed  = ns->eth.rx_discards +
5070                           pf->main_vsi->eth_stats.rx_discards;
5071         stats->ierrors  = ns->crc_errors +
5072                           ns->rx_undersize +
5073                           ns->rx_oversize + ns->rx_fragments + ns->rx_jabber;
5074
5075         PMD_DRV_LOG(DEBUG, "*************** PF stats start *****************");
5076         PMD_DRV_LOG(DEBUG, "rx_bytes:   %"PRIu64"", ns->eth.rx_bytes);
5077         PMD_DRV_LOG(DEBUG, "rx_unicast: %"PRIu64"", ns->eth.rx_unicast);
5078         PMD_DRV_LOG(DEBUG, "rx_multicast:%"PRIu64"", ns->eth.rx_multicast);
5079         PMD_DRV_LOG(DEBUG, "rx_broadcast:%"PRIu64"", ns->eth.rx_broadcast);
5080         PMD_DRV_LOG(DEBUG, "rx_discards:%"PRIu64"", ns->eth.rx_discards);
5081         PMD_DRV_LOG(DEBUG, "vsi rx_discards:%"PRIu64"",
5082                     pf->main_vsi->eth_stats.rx_discards);
5083         PMD_DRV_LOG(DEBUG, "rx_unknown_protocol:  %"PRIu64"",
5084                     ns->eth.rx_unknown_protocol);
5085         PMD_DRV_LOG(DEBUG, "tx_bytes:   %"PRIu64"", ns->eth.tx_bytes);
5086         PMD_DRV_LOG(DEBUG, "tx_unicast: %"PRIu64"", ns->eth.tx_unicast);
5087         PMD_DRV_LOG(DEBUG, "tx_multicast:%"PRIu64"", ns->eth.tx_multicast);
5088         PMD_DRV_LOG(DEBUG, "tx_broadcast:%"PRIu64"", ns->eth.tx_broadcast);
5089         PMD_DRV_LOG(DEBUG, "tx_discards:%"PRIu64"", ns->eth.tx_discards);
5090         PMD_DRV_LOG(DEBUG, "vsi tx_discards:%"PRIu64"",
5091                     pf->main_vsi->eth_stats.tx_discards);
5092         PMD_DRV_LOG(DEBUG, "tx_errors:          %"PRIu64"", ns->eth.tx_errors);
5093
5094         PMD_DRV_LOG(DEBUG, "tx_dropped_link_down:       %"PRIu64"",
5095                     ns->tx_dropped_link_down);
5096         PMD_DRV_LOG(DEBUG, "crc_errors: %"PRIu64"", ns->crc_errors);
5097         PMD_DRV_LOG(DEBUG, "illegal_bytes:      %"PRIu64"",
5098                     ns->illegal_bytes);
5099         PMD_DRV_LOG(DEBUG, "error_bytes:        %"PRIu64"", ns->error_bytes);
5100         PMD_DRV_LOG(DEBUG, "mac_local_faults:   %"PRIu64"",
5101                     ns->mac_local_faults);
5102         PMD_DRV_LOG(DEBUG, "mac_remote_faults:  %"PRIu64"",
5103                     ns->mac_remote_faults);
5104         PMD_DRV_LOG(DEBUG, "link_xon_rx:        %"PRIu64"", ns->link_xon_rx);
5105         PMD_DRV_LOG(DEBUG, "link_xoff_rx:       %"PRIu64"", ns->link_xoff_rx);
5106         PMD_DRV_LOG(DEBUG, "link_xon_tx:        %"PRIu64"", ns->link_xon_tx);
5107         PMD_DRV_LOG(DEBUG, "link_xoff_tx:       %"PRIu64"", ns->link_xoff_tx);
5108         PMD_DRV_LOG(DEBUG, "rx_size_64:         %"PRIu64"", ns->rx_size_64);
5109         PMD_DRV_LOG(DEBUG, "rx_size_127:        %"PRIu64"", ns->rx_size_127);
5110         PMD_DRV_LOG(DEBUG, "rx_size_255:        %"PRIu64"", ns->rx_size_255);
5111         PMD_DRV_LOG(DEBUG, "rx_size_511:        %"PRIu64"", ns->rx_size_511);
5112         PMD_DRV_LOG(DEBUG, "rx_size_1023:       %"PRIu64"", ns->rx_size_1023);
5113         PMD_DRV_LOG(DEBUG, "rx_size_1522:       %"PRIu64"", ns->rx_size_1522);
5114         PMD_DRV_LOG(DEBUG, "rx_size_big:        %"PRIu64"", ns->rx_size_big);
5115         PMD_DRV_LOG(DEBUG, "rx_undersize:       %"PRIu64"", ns->rx_undersize);
5116         PMD_DRV_LOG(DEBUG, "rx_fragments:       %"PRIu64"", ns->rx_fragments);
5117         PMD_DRV_LOG(DEBUG, "rx_oversize:        %"PRIu64"", ns->rx_oversize);
5118         PMD_DRV_LOG(DEBUG, "rx_jabber:          %"PRIu64"", ns->rx_jabber);
5119         PMD_DRV_LOG(DEBUG, "tx_size_64:         %"PRIu64"", ns->tx_size_64);
5120         PMD_DRV_LOG(DEBUG, "tx_size_127:        %"PRIu64"", ns->tx_size_127);
5121         PMD_DRV_LOG(DEBUG, "tx_size_255:        %"PRIu64"", ns->tx_size_255);
5122         PMD_DRV_LOG(DEBUG, "tx_size_511:        %"PRIu64"", ns->tx_size_511);
5123         PMD_DRV_LOG(DEBUG, "tx_size_1023:       %"PRIu64"", ns->tx_size_1023);
5124         PMD_DRV_LOG(DEBUG, "tx_size_1522:       %"PRIu64"", ns->tx_size_1522);
5125         PMD_DRV_LOG(DEBUG, "tx_size_big:        %"PRIu64"", ns->tx_size_big);
5126         PMD_DRV_LOG(DEBUG, "rx_len_errors:      %"PRIu64"", ns->rx_len_errors);
5127         PMD_DRV_LOG(DEBUG, "************* PF stats end ****************");
5128         return 0;
5129 }
5130
5131 /* Reset the statistics */
5132 static int
5133 ice_stats_reset(struct rte_eth_dev *dev)
5134 {
5135         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5136         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5137
5138         /* Mark PF and VSI stats to update the offset, aka "reset" */
5139         pf->offset_loaded = false;
5140         if (pf->main_vsi)
5141                 pf->main_vsi->offset_loaded = false;
5142
5143         /* read the stats, reading current register values into offset */
5144         ice_read_stats_registers(pf, hw);
5145
5146         return 0;
5147 }
5148
5149 static uint32_t
5150 ice_xstats_calc_num(void)
5151 {
5152         uint32_t num;
5153
5154         num = ICE_NB_ETH_XSTATS + ICE_NB_HW_PORT_XSTATS;
5155
5156         return num;
5157 }
5158
5159 static int
5160 ice_xstats_get(struct rte_eth_dev *dev, struct rte_eth_xstat *xstats,
5161                unsigned int n)
5162 {
5163         struct ice_pf *pf = ICE_DEV_PRIVATE_TO_PF(dev->data->dev_private);
5164         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5165         unsigned int i;
5166         unsigned int count;
5167         struct ice_hw_port_stats *hw_stats = &pf->stats;
5168
5169         count = ice_xstats_calc_num();
5170         if (n < count)
5171                 return count;
5172
5173         ice_read_stats_registers(pf, hw);
5174
5175         if (!xstats)
5176                 return 0;
5177
5178         count = 0;
5179
5180         /* Get stats from ice_eth_stats struct */
5181         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5182                 xstats[count].value =
5183                         *(uint64_t *)((char *)&hw_stats->eth +
5184                                       ice_stats_strings[i].offset);
5185                 xstats[count].id = count;
5186                 count++;
5187         }
5188
5189         /* Get individiual stats from ice_hw_port struct */
5190         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5191                 xstats[count].value =
5192                         *(uint64_t *)((char *)hw_stats +
5193                                       ice_hw_port_strings[i].offset);
5194                 xstats[count].id = count;
5195                 count++;
5196         }
5197
5198         return count;
5199 }
5200
5201 static int ice_xstats_get_names(__rte_unused struct rte_eth_dev *dev,
5202                                 struct rte_eth_xstat_name *xstats_names,
5203                                 __rte_unused unsigned int limit)
5204 {
5205         unsigned int count = 0;
5206         unsigned int i;
5207
5208         if (!xstats_names)
5209                 return ice_xstats_calc_num();
5210
5211         /* Note: limit checked in rte_eth_xstats_names() */
5212
5213         /* Get stats from ice_eth_stats struct */
5214         for (i = 0; i < ICE_NB_ETH_XSTATS; i++) {
5215                 strlcpy(xstats_names[count].name, ice_stats_strings[i].name,
5216                         sizeof(xstats_names[count].name));
5217                 count++;
5218         }
5219
5220         /* Get individiual stats from ice_hw_port struct */
5221         for (i = 0; i < ICE_NB_HW_PORT_XSTATS; i++) {
5222                 strlcpy(xstats_names[count].name, ice_hw_port_strings[i].name,
5223                         sizeof(xstats_names[count].name));
5224                 count++;
5225         }
5226
5227         return count;
5228 }
5229
5230 static int
5231 ice_dev_flow_ops_get(struct rte_eth_dev *dev,
5232                      const struct rte_flow_ops **ops)
5233 {
5234         if (!dev)
5235                 return -EINVAL;
5236
5237         *ops = &ice_flow_ops;
5238         return 0;
5239 }
5240
5241 /* Add UDP tunneling port */
5242 static int
5243 ice_dev_udp_tunnel_port_add(struct rte_eth_dev *dev,
5244                              struct rte_eth_udp_tunnel *udp_tunnel)
5245 {
5246         int ret = 0;
5247         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5248
5249         if (udp_tunnel == NULL)
5250                 return -EINVAL;
5251
5252         switch (udp_tunnel->prot_type) {
5253         case RTE_TUNNEL_TYPE_VXLAN:
5254                 ret = ice_create_tunnel(hw, TNL_VXLAN, udp_tunnel->udp_port);
5255                 break;
5256         default:
5257                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5258                 ret = -EINVAL;
5259                 break;
5260         }
5261
5262         return ret;
5263 }
5264
5265 /* Delete UDP tunneling port */
5266 static int
5267 ice_dev_udp_tunnel_port_del(struct rte_eth_dev *dev,
5268                              struct rte_eth_udp_tunnel *udp_tunnel)
5269 {
5270         int ret = 0;
5271         struct ice_hw *hw = ICE_DEV_PRIVATE_TO_HW(dev->data->dev_private);
5272
5273         if (udp_tunnel == NULL)
5274                 return -EINVAL;
5275
5276         switch (udp_tunnel->prot_type) {
5277         case RTE_TUNNEL_TYPE_VXLAN:
5278                 ret = ice_destroy_tunnel(hw, udp_tunnel->udp_port, 0);
5279                 break;
5280         default:
5281                 PMD_DRV_LOG(ERR, "Invalid tunnel type");
5282                 ret = -EINVAL;
5283                 break;
5284         }
5285
5286         return ret;
5287 }
5288
5289 static int
5290 ice_pci_probe(struct rte_pci_driver *pci_drv __rte_unused,
5291               struct rte_pci_device *pci_dev)
5292 {
5293         return rte_eth_dev_pci_generic_probe(pci_dev,
5294                                              sizeof(struct ice_adapter),
5295                                              ice_dev_init);
5296 }
5297
5298 static int
5299 ice_pci_remove(struct rte_pci_device *pci_dev)
5300 {
5301         return rte_eth_dev_pci_generic_remove(pci_dev, ice_dev_uninit);
5302 }
5303
5304 static struct rte_pci_driver rte_ice_pmd = {
5305         .id_table = pci_id_ice_map,
5306         .drv_flags = RTE_PCI_DRV_NEED_MAPPING | RTE_PCI_DRV_INTR_LSC,
5307         .probe = ice_pci_probe,
5308         .remove = ice_pci_remove,
5309 };
5310
5311 /**
5312  * Driver initialization routine.
5313  * Invoked once at EAL init time.
5314  * Register itself as the [Poll Mode] Driver of PCI devices.
5315  */
5316 RTE_PMD_REGISTER_PCI(net_ice, rte_ice_pmd);
5317 RTE_PMD_REGISTER_PCI_TABLE(net_ice, pci_id_ice_map);
5318 RTE_PMD_REGISTER_KMOD_DEP(net_ice, "* igb_uio | uio_pci_generic | vfio-pci");
5319 RTE_PMD_REGISTER_PARAM_STRING(net_ice,
5320                               ICE_HW_DEBUG_MASK_ARG "=0xXXX"
5321                               ICE_PROTO_XTR_ARG "=[queue:]<vlan|ipv4|ipv6|ipv6_flow|tcp|ip_offset>"
5322                               ICE_SAFE_MODE_SUPPORT_ARG "=<0|1>"
5323                               ICE_PIPELINE_MODE_SUPPORT_ARG "=<0|1>");
5324
5325 RTE_LOG_REGISTER_SUFFIX(ice_logtype_init, init, NOTICE);
5326 RTE_LOG_REGISTER_SUFFIX(ice_logtype_driver, driver, NOTICE);
5327 #ifdef RTE_ETHDEV_DEBUG_RX
5328 RTE_LOG_REGISTER_SUFFIX(ice_logtype_rx, rx, DEBUG);
5329 #endif
5330 #ifdef RTE_ETHDEV_DEBUG_TX
5331 RTE_LOG_REGISTER_SUFFIX(ice_logtype_tx, tx, DEBUG);
5332 #endif